Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry_print_V_I

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Dependencies:   mbed-dsp mbed

Fork of Impedance_Fast_Circuitry by Jared Baxter

adc.cpp@47:54fafe151669, 2015-01-31 (annotated)

Committer:
timmey9
Date:
Sat Jan 31 16:44:40 2015 +0000
Revision:
47:54fafe151669
Parent:
46:a015ebf4663b
Child:
48:29f14bc30ba6
Quad decoder works and a self test is built in.  ADC one shot and continuous now working.  DMA still working.  Need to fix PDB.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 39:82dc3daecf32 1 #include "adc.h"
timmey9 45:d591d138cdeb 2
timmey9 44:41c262caf898 3 /*
timmey9 44:41c262caf898 4 TODO: remove interrupt handlers
timmey9 44:41c262caf898 5 add calibration
timmey9 45:d591d138cdeb 6 change clock speed
timmey9 44:41c262caf898 7
timmey9 45:d591d138cdeb 8 Possible causes of the triggering problem:
timmey9 45:d591d138cdeb 9 more multiplexing somehow?
timmey9 45:d591d138cdeb 10 does the ADC interrupt need to be enabled?
timmey9 45:d591d138cdeb 11 clock speed?
timmey9 45:d591d138cdeb 12 hardware/software trigger
timmey9 45:d591d138cdeb 13 channel A or B?
timmey9 45:d591d138cdeb 14 single vs continuous mode
timmey9 45:d591d138cdeb 15 does asynchronous clock have to do with this?
timmey9 44:41c262caf898 16 */
timmey9 45:d591d138cdeb 17 DigitalOut toggle1(PTC16);
timmey9 45:d591d138cdeb 18 DigitalOut green(LED_GREEN);
timmey9 45:d591d138cdeb 19 DigitalOut red(LED_RED);
timmey9 45:d591d138cdeb 20 Serial debug(USBTX,USBRX);
timmey9 39:82dc3daecf32 21
timmey9 45:d591d138cdeb 22 void adc_init()
timmey9 39:82dc3daecf32 23 {
timmey9 45:d591d138cdeb 24 // red, indicating now ready
timmey9 45:d591d138cdeb 25 red = 0;
timmey9 45:d591d138cdeb 26 green = 1;
timmey9 45:d591d138cdeb 27
timmey9 39:82dc3daecf32 28 // Turn on the ADC0 and ADC1 clocks
timmey9 39:82dc3daecf32 29 SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
timmey9 39:82dc3daecf32 30 SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK;
timmey9 40:bd6d8c35e822 31
timmey9 45:d591d138cdeb 32 // Set ADC hardware trigger to PDB0
timmey9 45:d591d138cdeb 33 SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0);
timmey9 46:a015ebf4663b 34 SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0);
timmey9 39:82dc3daecf32 35
timmey9 45:d591d138cdeb 36 // Setup Configuration Register 1
timmey9 45:d591d138cdeb 37 ADC0_CFG1 = 0; // clear register
timmey9 45:d591d138cdeb 38 ADC0_CFG1 |= ADC_CFG1_ADICLK(0); // select bus clock
timmey9 45:d591d138cdeb 39 ADC0_CFG1 |= ADC_CFG1_MODE(3); // select 16-bit 2's complement output
timmey9 45:d591d138cdeb 40 ADC0_CFG1 |= ADC_CFG1_ADIV(0); // select short sample time
timmey9 45:d591d138cdeb 41 ADC0_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time
timmey9 45:d591d138cdeb 42 ADC0_CFG1 &= ~ADC_CFG1_ADLPC_MASK; // select normal power configuration
timmey9 46:a015ebf4663b 43 ADC1_CFG1 = 0; // clear register
timmey9 46:a015ebf4663b 44 ADC1_CFG1 |= ADC_CFG1_ADICLK(0); // select bus clock
timmey9 46:a015ebf4663b 45 ADC1_CFG1 |= ADC_CFG1_MODE(3); // select 16-bit 2's complement output
timmey9 46:a015ebf4663b 46 ADC1_CFG1 |= ADC_CFG1_ADIV(0); // select short sample time
timmey9 46:a015ebf4663b 47 ADC1_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time
timmey9 46:a015ebf4663b 48 ADC1_CFG1 &= ~ADC_CFG1_ADLPC_MASK; // select normal power configuration
timmey9 45:d591d138cdeb 49
timmey9 45:d591d138cdeb 50 // Setup Configuration Register 2
timmey9 45:d591d138cdeb 51 ADC0_CFG2 = 0; // clear register
timmey9 47:54fafe151669 52 ADC0_CFG2 |= ADC_CFG2_ADHSC_MASK ; // select high-speed conversion
timmey9 45:d591d138cdeb 53 ADC0_CFG2 &= ~ADC_CFG2_MUXSEL_MASK; // select a channels
timmey9 39:82dc3daecf32 54
timmey9 45:d591d138cdeb 55 // Setup Status and Control Register 2
timmey9 47:54fafe151669 56 ADC0_SC2 = 0; // clear register
timmey9 47:54fafe151669 57 ADC0_SC2 |= ADC_SC2_REFSEL(0); // select external voltage reference
timmey9 47:54fafe151669 58 ADC0_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
timmey9 45:d591d138cdeb 59 ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // select software trigger until calibration is complete
timmey9 47:54fafe151669 60 ADC1_SC2 = 0; // clear register
timmey9 47:54fafe151669 61 ADC1_SC2 |= ADC_SC2_REFSEL(0); // select external voltage reference
timmey9 47:54fafe151669 62 ADC1_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
timmey9 46:a015ebf4663b 63 ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // select software trigger until calibration is complete
timmey9 45:d591d138cdeb 64
timmey9 45:d591d138cdeb 65 // Setup Status and Control Register 3
timmey9 45:d591d138cdeb 66 ADC0_SC3 = 0; // Hardware Average set to 4 samples averaged
timmey9 45:d591d138cdeb 67 // Hardware Average Disabled
timmey9 45:d591d138cdeb 68 // select single conversion mode
timmey9 46:a015ebf4663b 69 ADC1_SC3 = 0; // Hardware Average set to 4 samples averaged
timmey9 46:a015ebf4663b 70 // Hardware Average Disabled
timmey9 46:a015ebf4663b 71 // select single conversion mode
timmey9 39:82dc3daecf32 72
timmey9 45:d591d138cdeb 73 // calibrate the ADC
timmey9 45:d591d138cdeb 74 ADC0_SC3 |= ADC_SC3_CAL_MASK; // start calibration
timmey9 45:d591d138cdeb 75 while(ADC0_SC3&ADC_SC3_CALF_MASK) {} // wait for calibration to complete
timmey9 46:a015ebf4663b 76 ADC1_SC3 |= ADC_SC3_CAL_MASK; // start calibration
timmey9 46:a015ebf4663b 77 while(ADC1_SC3&ADC_SC3_CALF_MASK) {} // wait for calibration to complete
timmey9 46:a015ebf4663b 78
timmey9 45:d591d138cdeb 79
timmey9 45:d591d138cdeb 80 // calculate the gains (see user manual page 864)
timmey9 45:d591d138cdeb 81 int16_t gain = (ADC0_CLP0+ADC0_CLP1+ADC0_CLP2+ADC0_CLP3+ADC0_CLP4+ADC0_CLPS);
timmey9 45:d591d138cdeb 82 gain = (gain>>1); // divide by 2
timmey9 45:d591d138cdeb 83 gain |= 0x8000; // set the MSB
timmey9 45:d591d138cdeb 84 ADC0_PG = gain;
timmey9 45:d591d138cdeb 85
timmey9 46:a015ebf4663b 86 gain = (ADC1_CLP0+ADC1_CLP1+ADC1_CLP2+ADC1_CLP3+ADC1_CLP4+ADC1_CLPS);
timmey9 46:a015ebf4663b 87 gain = (gain>>1); // divide by 2
timmey9 46:a015ebf4663b 88 gain |= 0x8000; // set the MSB
timmey9 46:a015ebf4663b 89 ADC1_PG = gain;
timmey9 46:a015ebf4663b 90
timmey9 45:d591d138cdeb 91 gain = (ADC0_CLM0+ADC0_CLM1+ADC0_CLM2+ADC0_CLM3+ADC0_CLM4+ADC0_CLMS);
timmey9 45:d591d138cdeb 92 gain = (gain>>1); // divide by 2
timmey9 45:d591d138cdeb 93 gain |= 0x8000; // set the MSB
timmey9 45:d591d138cdeb 94 ADC0_MG = gain;
timmey9 39:82dc3daecf32 95
timmey9 46:a015ebf4663b 96 gain = (ADC1_CLM0+ADC1_CLM1+ADC1_CLM2+ADC1_CLM3+ADC1_CLM4+ADC1_CLMS);
timmey9 46:a015ebf4663b 97 gain = (gain>>1); // divide by 2
timmey9 46:a015ebf4663b 98 gain |= 0x8000; // set the MSB
timmey9 46:a015ebf4663b 99 ADC1_MG = gain;
timmey9 46:a015ebf4663b 100
timmey9 45:d591d138cdeb 101 ADC0_SC3 &= ~ADC_SC3_CAL_MASK; // stop calibration
timmey9 46:a015ebf4663b 102 ADC1_SC3 &= ~ADC_SC3_CAL_MASK; // stop calibration
timmey9 45:d591d138cdeb 103
timmey9 45:d591d138cdeb 104
timmey9 45:d591d138cdeb 105
timmey9 45:d591d138cdeb 106 // yellow indicating calibration complete
timmey9 45:d591d138cdeb 107 red = 0;
timmey9 45:d591d138cdeb 108 green = 0;
timmey9 45:d591d138cdeb 109
timmey9 45:d591d138cdeb 110 ADC0_SC2 |= ADC_SC2_ADTRG_MASK; // select hardware trigger now that calibration is complete
timmey9 46:a015ebf4663b 111 ADC1_SC2 |= ADC_SC2_ADTRG_MASK; // select hardware trigger now that calibration is complete
timmey9 45:d591d138cdeb 112
timmey9 45:d591d138cdeb 113 // Setup Status and Control Register 1A
timmey9 45:d591d138cdeb 114 ADC0_SC1A = 0; // clear register
timmey9 45:d591d138cdeb 115 ADC0_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
timmey9 45:d591d138cdeb 116 ADC0_SC1A |= ADC_SC1_AIEN_MASK; // enable interrupt (for debugging)
timmey9 45:d591d138cdeb 117 ADC0_SC1A |= ADC_SC1_ADCH(13); // select channel 13
timmey9 46:a015ebf4663b 118 ADC1_SC1A = 0; // clear register
timmey9 46:a015ebf4663b 119 ADC1_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
timmey9 46:a015ebf4663b 120 ADC1_SC1A |= ADC_SC1_AIEN_MASK; // enable interrupt (for debugging)
timmey9 46:a015ebf4663b 121 ADC1_SC1A |= ADC_SC1_ADCH(13); // select channel 13
timmey9 45:d591d138cdeb 122
timmey9 45:d591d138cdeb 123 // Check if ADC is finished initializing TODO: This part doesn't seem right, but I did it according to 871
timmey9 45:d591d138cdeb 124 while( (ADC0_SC1A&ADC_SC1_COCO_MASK)) {}
timmey9 45:d591d138cdeb 125 gain = ADC0_RA; // read the register to clear SC1A[COCO]
timmey9 46:a015ebf4663b 126 while( (ADC1_SC1A&ADC_SC1_COCO_MASK)) {}
timmey9 46:a015ebf4663b 127 gain = ADC1_RA; // read the register to clear SC1A[COCO]
timmey9 45:d591d138cdeb 128
timmey9 45:d591d138cdeb 129
timmey9 45:d591d138cdeb 130 // green indicating calibration and initialization complete
timmey9 45:d591d138cdeb 131 red = 1;
timmey9 45:d591d138cdeb 132 green = 0;
timmey9 45:d591d138cdeb 133
timmey9 45:d591d138cdeb 134 debug.printf("ADC0_SC1a: %08x\r\n",ADC0_SC1A); //(0x0000004d)
timmey9 45:d591d138cdeb 135 debug.printf("ADC0_SC1b: %08x\r\n",ADC0_SC1B); //(0x0000001f)
timmey9 45:d591d138cdeb 136 debug.printf("ADC0_CFG1: %08x\r\n",ADC0_CFG1); //(0x0000000c)
timmey9 45:d591d138cdeb 137 debug.printf("ADC0_CFG2: %08x\r\n",ADC0_CFG2); //(0x00000004)
timmey9 45:d591d138cdeb 138 debug.printf("ADC0_RA: %08x\r\n",ADC0_RA); //(0x00000000)
timmey9 45:d591d138cdeb 139 debug.printf("ADC0_RB: %08x\r\n",ADC0_RB); //(0x00000000)
timmey9 45:d591d138cdeb 140 debug.printf("ADC0_SC2: %08x\r\n",ADC0_SC2); //(0x00000044)
timmey9 45:d591d138cdeb 141 debug.printf("ADC0_SC3: %08x\r\n\n",ADC0_SC3); //(0x00000000)
timmey9 45:d591d138cdeb 142
timmey9 40:bd6d8c35e822 143 // Enable the ISR vector
timmey9 47:54fafe151669 144 //NVIC_SetVector(ADC0_IRQn, (uint32_t)&ADC0_IRQHandler);
timmey9 47:54fafe151669 145 //NVIC_EnableIRQ(ADC0_IRQn);
timmey9 40:bd6d8c35e822 146 }
timmey9 40:bd6d8c35e822 147
timmey9 41:3e0623d81b9a 148 void adc_start() {
timmey9 40:bd6d8c35e822 149 // reset DMA
timmey9 45:d591d138cdeb 150 dma_reset();
timmey9 40:bd6d8c35e822 151
timmey9 40:bd6d8c35e822 152 // set ADC to continuous mode
timmey9 40:bd6d8c35e822 153 ADC0_SC3 |= ADC_SC3_ADCO_MASK;
timmey9 46:a015ebf4663b 154 ADC1_SC3 |= ADC_SC3_ADCO_MASK;
timmey9 45:d591d138cdeb 155
timmey9 45:d591d138cdeb 156 // set ADC to software trigger
timmey9 47:54fafe151669 157 ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK;
timmey9 46:a015ebf4663b 158 ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK;
timmey9 40:bd6d8c35e822 159
timmey9 40:bd6d8c35e822 160 // start ADC conversion (SW trigger)
timmey9 46:a015ebf4663b 161 ADC0_SC1A |= ADC_SC1_ADCH(13); // write to SC1A causing a trigger
timmey9 46:a015ebf4663b 162 ADC1_SC1A |= ADC_SC1_ADCH(14); // write to SC1A causing a trigger
timmey9 40:bd6d8c35e822 163 }
timmey9 40:bd6d8c35e822 164
timmey9 41:3e0623d81b9a 165 void adc_stop() {
timmey9 45:d591d138cdeb 166 // set ADC to hardware trigger
timmey9 45:d591d138cdeb 167 ADC0_SC2 |= ADC_SC2_ADTRG_MASK;
timmey9 46:a015ebf4663b 168 ADC1_SC2 |= ADC_SC2_ADTRG_MASK;
timmey9 45:d591d138cdeb 169
timmey9 45:d591d138cdeb 170 // set to single conversion mode effectively stopping the ADC unless a timer triggers the ADC
timmey9 45:d591d138cdeb 171 ADC0_SC3 &= ~ADC_SC3_ADCO_MASK;
timmey9 46:a015ebf4663b 172 ADC1_SC3 &= ~ADC_SC3_ADCO_MASK;
timmey9 45:d591d138cdeb 173 }
timmey9 45:d591d138cdeb 174
timmey9 45:d591d138cdeb 175 void adc_single_sample() {
timmey9 45:d591d138cdeb 176 ADC0_SC3 &= ~ADC_SC3_ADCO_MASK; // single conversion mode
timmey9 46:a015ebf4663b 177 ADC1_SC3 &= ~ADC_SC3_ADCO_MASK; // single conversion mode
timmey9 45:d591d138cdeb 178 ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
timmey9 46:a015ebf4663b 179 ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
timmey9 45:d591d138cdeb 180 ADC0_SC1A |= ADC_SC1_ADCH(13); // write to SC1A causing a trigger
timmey9 46:a015ebf4663b 181 ADC1_SC1A |= ADC_SC1_ADCH(14); // write to SC1A causing a trigger
timmey9 40:bd6d8c35e822 182 }
timmey9 40:bd6d8c35e822 183
timmey9 40:bd6d8c35e822 184 void ADC0_IRQHandler() {
timmey9 47:54fafe151669 185
timmey9 45:d591d138cdeb 186 toggle1 = !toggle1;
timmey9 39:82dc3daecf32 187 }