Diff: dma.cpp

Revision:

46:a015ebf4663b

Parent:

45:d591d138cdeb

Child:

48:29f14bc30ba6

--- a/dma.cpp	Sat Jan 31 07:25:52 2015 +0000
+++ b/dma.cpp	Sat Jan 31 08:13:33 2015 +0000
@@ -8,20 +8,25 @@
 uint16_t sample_array0[TOTAL_SAMPLES];
 uint16_t sample_array1[TOTAL_SAMPLES];
 uint16_t angle_array[TOTAL_SAMPLES];
-DigitalIn AMT20_A(PTC0); // FTM2_QD_PHA, apparently the k64f has a quadrature decoder.  look into this (page 264)
-DigitalIn AMT20_B(PTC1);
+//DigitalIn AMT20_A(PTB18); // FTM2_QD_PHA, apparently the k64f has a quadrature decoder.  look into this (page 264)
+//DigitalIn AMT20_B(PTB10); // FTM2_QD_PHB
 
 void dma_init()
 {
     // Enable clock for DMAMUX and DMA
     SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
     SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;  
-    SIM_SCGC3 |= SIM_SCGC3_FTM2_MASK; // make sure clock is enabled for FTM2  
+    SIM_SCGC6 |= SIM_SCGC6_FTM2_MASK; // make sure clock is enabled for FTM2  
             
     // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
     DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
     DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
-    DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_TRIG_MASK | DMAMUX_CHCFG_SOURCE(51); // PortC
+    DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_TRIG_MASK | DMAMUX_CHCFG_SOURCE(48);
+    /* Source number    Source module    Source description
+           30                FTM2             Channel 0
+           31                FTM2             Channel 1
+           48                PDB                  -
+    */
     
     
     // Enable request signal for channel 0 
@@ -77,7 +82,7 @@
     // Setup control and status register
     DMA_TCD0_CSR = 0;
     DMA_TCD1_CSR = 0;
-    DMA_TCD2_CSR = 1;
+    DMA_TCD2_CSR = 0;
     
     
     /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);