Diff: pdb.cpp

Revision:

50:33524a27e08c

Parent:

49:4dcf4717a8bb

Child:

51:43143a3fc2d7

--- a/pdb.cpp	Sat Jan 31 19:16:22 2015 +0000
+++ b/pdb.cpp	Sat Jan 31 19:46:00 2015 +0000
@@ -11,17 +11,16 @@
     
     // set ADC trigger to PDB0
     SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); 
-    SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0); 
     
     // Configure the Peripheral Delay Block (PDB):
     PDB0_IDLY = 0x01;   // need to trigger interrupt every counter reset which happens when modulus reached
     PDB0_MOD = 0x0000ffff; // max
     PDB0_CH0DLY0 = 0xff;
-    PDB0_CH0DLY1 = 0xf0;
+    PDB0_CH0DLY1 = 0xff;
     PDB0_CH1DLY0 = 0xff;
-    PDB0_CH1DLY1 = 0xf0;
+    PDB0_CH1DLY1 = 0xff;
     PDB0_CH0C1 = PDB_C1_EN(2) | PDB_C1_TOS(2); // channel 0 pretrigger 0 and 1 enabled and delayed
-    PDB0_CH1C1 = PDB_C1_EN(2) | PDB_C1_TOS(2); // channel 1 pretrigger 0 and 1 enabled and delayed
+    PDB0_CH1C1 = PDB_C1_EN(1) | PDB_C1_TOS(1); // channel 1 pretrigger 0 and 1 enabled and delayed
     
     // Setup Staus and Control Register
     PDB0_SC = 0; // clear register
@@ -46,8 +45,8 @@
     debug2.printf("PDB0_CH1C1:    %08x\r\n",PDB0_CH1C1);
     debug2.printf("PDB0_CH1S:     %08x\r\n",PDB0_CH1S);
     debug2.printf("PDB0_CH1DLY0:  %08x\r\n",PDB0_CH1DLY0);
-    debug2.printf("PDB0_CH1DLY1:  %08x\r\n\n",PDB0_CH1DLY1);
-    /*debug2.printf("PDB0_DACINTC0: %08x\r\n",PDB0_DACINTC0);
+    debug2.printf("PDB0_CH1DLY1:  %08x\r\n",PDB0_CH1DLY1);
+    debug2.printf("PDB0_DACINTC0: %08x\r\n",PDB0_DACINTC0);
     debug2.printf("PDB0_DACINT0:  %08x\r\n",PDB0_DACINT0);
     debug2.printf("PDB0_DACINTC1: %08x\r\n",PDB0_DACINTC1);
     debug2.printf("PDB0_DACINT1:  %08x\r\n",PDB0_DACINT1);
@@ -55,7 +54,7 @@
     debug2.printf("PDB0_PO0DLY:   %08x\r\n",PDB0_PO0DLY);
     debug2.printf("PDB0_PO1DLY:   %08x\r\n",PDB0_PO1DLY);
     debug2.printf("PDB0_PO2DLY:   %08x\r\n\n",PDB0_PO2DLY);
-    */
+    
     //NVIC_SetVector(PDB0_IRQn, (uint32_t)&PDB0_IRQHandler);
     //NVIC_EnableIRQ(PDB0_IRQn);
 }