Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry_print_V_I

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Dependencies:   mbed-dsp mbed

Fork of Impedance_Fast_Circuitry by Jared Baxter

pdb.cpp@51:43143a3fc2d7, 2015-01-31 (annotated)

Committer:
timmey9
Date:
Sat Jan 31 20:17:58 2015 +0000
Revision:
51:43143a3fc2d7
Parent:
50:33524a27e08c 
Cleaned up the code a little bit.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 39:82dc3daecf32 1 #include "pdb.h"
timmey9 39:82dc3daecf32 2
timmey9 51:43143a3fc2d7 3 //Serial debug2(USBTX,USBRX);
timmey9 51:43143a3fc2d7 4
timmey9 45:d591d138cdeb 5
timmey9 51:43143a3fc2d7 6 /* The PDB is setup to run continuous (when enabled) so it will
timmey9 51:43143a3fc2d7 7 * periodically trigger the ADCs to sample and trigger DMA2 to
timmey9 51:43143a3fc2d7 8 * save the quadrature angle. The PDB can be started and stopped. */
timmey9 45:d591d138cdeb 9 void pdb_init() {
timmey9 39:82dc3daecf32 10
timmey9 39:82dc3daecf32 11 // initialize the Programmable Delay Block
timmey9 45:d591d138cdeb 12
timmey9 45:d591d138cdeb 13 // turn on the clock to the PDB
timmey9 47:54fafe151669 14 SIM->SCGC6 |= SIM_SCGC6_PDB_MASK;
timmey9 45:d591d138cdeb 15
timmey9 45:d591d138cdeb 16 // set ADC trigger to PDB0
timmey9 45:d591d138cdeb 17 SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0);
timmey9 47:54fafe151669 18
timmey9 39:82dc3daecf32 19 // Configure the Peripheral Delay Block (PDB):
timmey9 47:54fafe151669 20 PDB0_IDLY = 0x01; // need to trigger interrupt every counter reset which happens when modulus reached
timmey9 48:29f14bc30ba6 21 PDB0_MOD = 0x0000ffff; // max
timmey9 48:29f14bc30ba6 22 PDB0_CH0DLY0 = 0xff;
timmey9 50:33524a27e08c 23 PDB0_CH0DLY1 = 0xff;
timmey9 48:29f14bc30ba6 24 PDB0_CH1DLY0 = 0xff;
timmey9 50:33524a27e08c 25 PDB0_CH1DLY1 = 0xff;
timmey9 48:29f14bc30ba6 26 PDB0_CH0C1 = PDB_C1_EN(2) | PDB_C1_TOS(2); // channel 0 pretrigger 0 and 1 enabled and delayed
timmey9 50:33524a27e08c 27 PDB0_CH1C1 = PDB_C1_EN(1) | PDB_C1_TOS(1); // channel 1 pretrigger 0 and 1 enabled and delayed
timmey9 39:82dc3daecf32 28
timmey9 45:d591d138cdeb 29 // Setup Staus and Control Register
timmey9 45:d591d138cdeb 30 PDB0_SC = 0; // clear register
timmey9 48:29f14bc30ba6 31 PDB0_SC = PDB_SC_DMAEN_MASK // Enable DMA
timmey9 48:29f14bc30ba6 32 | PDB_SC_PRESCALER(0) // Slow down the period of the PDB for testing
timmey9 48:29f14bc30ba6 33 | PDB_SC_TRGSEL(0xf) // Trigger source is Software Trigger to be invoked in this file
timmey9 48:29f14bc30ba6 34 | PDB_SC_PDBEN_MASK // PDB enabled
timmey9 48:29f14bc30ba6 35 | PDB_SC_PDBIE_MASK // PDB Interrupt Enable
timmey9 48:29f14bc30ba6 36 | PDB_SC_MULT(0) // Multiplication factor 20 for the prescale divider for the counter clock
timmey9 48:29f14bc30ba6 37 | PDB_SC_CONT_MASK // Contintuous, rather than one-shot, mode
timmey9 48:29f14bc30ba6 38 | PDB_SC_LDOK_MASK; // Need to ok the loading or it will not load certain regsiters!
timmey9 39:82dc3daecf32 39
timmey9 51:43143a3fc2d7 40 //NVIC_SetVector(PDB0_IRQn, (uint32_t)&PDB0_IRQHandler);
timmey9 51:43143a3fc2d7 41 //NVIC_EnableIRQ(PDB0_IRQn);
timmey9 51:43143a3fc2d7 42 }
timmey9 51:43143a3fc2d7 43
timmey9 51:43143a3fc2d7 44 void PDB0_IRQHandler() {
timmey9 51:43143a3fc2d7 45
timmey9 51:43143a3fc2d7 46 }
timmey9 51:43143a3fc2d7 47
timmey9 51:43143a3fc2d7 48 void pdb_start() {
timmey9 51:43143a3fc2d7 49 PDB0_SC |= PDB_SC_PDBEN_MASK; // PDB enabled
timmey9 51:43143a3fc2d7 50 PDB0_SC |= PDB_SC_SWTRIG_MASK; // enable software trigger (start the PDB)
timmey9 51:43143a3fc2d7 51 }
timmey9 51:43143a3fc2d7 52
timmey9 51:43143a3fc2d7 53 void pdb_stop() {
timmey9 51:43143a3fc2d7 54 //PDB0_SC &= ~PDB_SC_CONT_MASK; // change to one-shot mode, so pdb will stop after current count
timmey9 51:43143a3fc2d7 55 PDB0_SC &= ~PDB_SC_PDBEN_MASK; // PDB disabled
timmey9 51:43143a3fc2d7 56 }
timmey9 51:43143a3fc2d7 57
timmey9 51:43143a3fc2d7 58
timmey9 51:43143a3fc2d7 59 /*
timmey9 45:d591d138cdeb 60 debug2.printf("PDB0_SC: %08x\r\n",PDB0_SC);
timmey9 45:d591d138cdeb 61 debug2.printf("PDB0_MOD: %08x\r\n",PDB0_MOD);
timmey9 45:d591d138cdeb 62 debug2.printf("PDB0_CNT: %08x\r\n",PDB0_CNT);
timmey9 45:d591d138cdeb 63 debug2.printf("PDB0_IDLY: %08x\r\n",PDB0_IDLY);
timmey9 45:d591d138cdeb 64 debug2.printf("PDB0_CH0C1: %08x\r\n",PDB0_CH0C1);
timmey9 45:d591d138cdeb 65 debug2.printf("PDB0_CH0S: %08x\r\n",PDB0_CH0S);
timmey9 45:d591d138cdeb 66 debug2.printf("PDB0_CH0DLY0: %08x\r\n",PDB0_CH0DLY0);
timmey9 45:d591d138cdeb 67 debug2.printf("PDB0_CH0DLY1: %08x\r\n",PDB0_CH0DLY1);
timmey9 45:d591d138cdeb 68 debug2.printf("PDB0_CH1C1: %08x\r\n",PDB0_CH1C1);
timmey9 45:d591d138cdeb 69 debug2.printf("PDB0_CH1S: %08x\r\n",PDB0_CH1S);
timmey9 45:d591d138cdeb 70 debug2.printf("PDB0_CH1DLY0: %08x\r\n",PDB0_CH1DLY0);
timmey9 50:33524a27e08c 71 debug2.printf("PDB0_CH1DLY1: %08x\r\n",PDB0_CH1DLY1);
timmey9 50:33524a27e08c 72 debug2.printf("PDB0_DACINTC0: %08x\r\n",PDB0_DACINTC0);
timmey9 45:d591d138cdeb 73 debug2.printf("PDB0_DACINT0: %08x\r\n",PDB0_DACINT0);
timmey9 45:d591d138cdeb 74 debug2.printf("PDB0_DACINTC1: %08x\r\n",PDB0_DACINTC1);
timmey9 45:d591d138cdeb 75 debug2.printf("PDB0_DACINT1: %08x\r\n",PDB0_DACINT1);
timmey9 45:d591d138cdeb 76 debug2.printf("PDB0_POEN: %08x\r\n",PDB0_POEN);
timmey9 45:d591d138cdeb 77 debug2.printf("PDB0_PO0DLY: %08x\r\n",PDB0_PO0DLY);
timmey9 45:d591d138cdeb 78 debug2.printf("PDB0_PO1DLY: %08x\r\n",PDB0_PO1DLY);
timmey9 45:d591d138cdeb 79 debug2.printf("PDB0_PO2DLY: %08x\r\n\n",PDB0_PO2DLY);
timmey9 51:43143a3fc2d7 80 */