Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

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Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

Sample/dma.cpp@52:5a40cc58c4c2, 2015-01-31 (annotated)

Committer:
timmey9
Date:
Sat Jan 31 20:56:04 2015 +0000
Revision:
52:5a40cc58c4c2
Parent:
dma.cpp@51:43143a3fc2d7 
Made minor cosmetic and comment changes.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 45:d591d138cdeb 1 /**
timmey9 45:d591d138cdeb 2 * Setup triggering for DMA2 and PortC
timmey9 34:44cc9b76a507 3 */
timmey9 34:44cc9b76a507 4 #include "dma.h"
timmey9 34:44cc9b76a507 5
timmey9 45:d591d138cdeb 6 #define TOTAL_SAMPLES 10
timmey9 45:d591d138cdeb 7 int len = TOTAL_SAMPLES;
timmey9 45:d591d138cdeb 8 uint16_t sample_array0[TOTAL_SAMPLES];
timmey9 45:d591d138cdeb 9 uint16_t sample_array1[TOTAL_SAMPLES];
timmey9 45:d591d138cdeb 10 uint16_t angle_array[TOTAL_SAMPLES];
timmey9 51:43143a3fc2d7 11
timmey9 51:43143a3fc2d7 12
timmey9 45:d591d138cdeb 13
timmey9 51:43143a3fc2d7 14 /* DMA0 and DMA1 are triggered by ADC0 and ADC1 (which are triggered
timmey9 51:43143a3fc2d7 15 * by the PDB). However, DMA2 is triggered directly by the PDB. This
timmey9 51:43143a3fc2d7 16 * is becuase DMA2 is reading FTM2, which cannot trigger the DMA. */
timmey9 45:d591d138cdeb 17 void dma_init()
timmey9 34:44cc9b76a507 18 {
timmey9 34:44cc9b76a507 19 // Enable clock for DMAMUX and DMA
timmey9 34:44cc9b76a507 20 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
timmey9 45:d591d138cdeb 21 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
timmey9 46:a015ebf4663b 22 SIM_SCGC6 |= SIM_SCGC6_FTM2_MASK; // make sure clock is enabled for FTM2
timmey9 34:44cc9b76a507 23
timmey9 45:d591d138cdeb 24 // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
timmey9 45:d591d138cdeb 25 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
timmey9 45:d591d138cdeb 26 DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
timmey9 48:29f14bc30ba6 27 DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(48); // Set trigger source to PDB (Don't set DMA Trig Enable because that is for the PIT)
timmey9 51:43143a3fc2d7 28 /* Source number Source module
timmey9 48:29f14bc30ba6 29 40 ADC0
timmey9 48:29f14bc30ba6 30 41 ADC1
timmey9 51:43143a3fc2d7 31 48 PDB
timmey9 46:a015ebf4663b 32 */
timmey9 36:07d8a3143967 33
timmey9 36:07d8a3143967 34
timmey9 34:44cc9b76a507 35 // Enable request signal for channel 0
timmey9 36:07d8a3143967 36 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK | DMA_ERQ_ERQ2_MASK;
timmey9 45:d591d138cdeb 37
timmey9 45:d591d138cdeb 38 // select round-robin arbitration priority
timmey9 45:d591d138cdeb 39 DMA_CR |= DMA_CR_ERCA_MASK;
timmey9 45:d591d138cdeb 40
timmey9 36:07d8a3143967 41 // Set memory address for source and destination for DMA0, DMA1, and DMA2
timmey9 48:29f14bc30ba6 42 DMA_TCD0_SADDR = (uint32_t) &ADC0_RB;
timmey9 45:d591d138cdeb 43 DMA_TCD0_DADDR = (uint32_t) sample_array0;
timmey9 50:33524a27e08c 44 DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
timmey9 45:d591d138cdeb 45 DMA_TCD1_DADDR = (uint32_t) sample_array1;
timmey9 45:d591d138cdeb 46 DMA_TCD2_SADDR = (uint32_t) &FTM2_CNT;
timmey9 45:d591d138cdeb 47 DMA_TCD2_DADDR = (uint32_t) angle_array;
timmey9 36:07d8a3143967 48
timmey9 34:44cc9b76a507 49 // Set an offset for source and destination address
timmey9 34:44cc9b76a507 50 DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 34:44cc9b76a507 51 DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 52 DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 53 DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 54 DMA_TCD2_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 55 DMA_TCD2_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 34:44cc9b76a507 56
timmey9 34:44cc9b76a507 57 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 58 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 59 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 60 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 61
timmey9 34:44cc9b76a507 62 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 63 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 64 DMA_TCD1_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 65 DMA_TCD2_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 66
timmey9 34:44cc9b76a507 67 // Current major iteration count (a single iteration of 5 bytes)
timmey9 45:d591d138cdeb 68 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 69 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 45:d591d138cdeb 70 DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 71 DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 45:d591d138cdeb 72 DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 73 DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 34:44cc9b76a507 74
timmey9 34:44cc9b76a507 75 // Adjustment value used to restore the source and destiny address to the initial value
timmey9 45:d591d138cdeb 76 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
timmey9 45:d591d138cdeb 77
timmey9 44:41c262caf898 78 DMA_TCD0_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 79 DMA_TCD0_DLASTSGA = -len*2; // Destination address adjustment
timmey9 44:41c262caf898 80 DMA_TCD1_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 81 DMA_TCD1_DLASTSGA = -len*2; // Destination address adjustment
timmey9 44:41c262caf898 82 DMA_TCD2_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 83 DMA_TCD2_DLASTSGA = -len*2; // Destination address adjustment
timmey9 34:44cc9b76a507 84
timmey9 34:44cc9b76a507 85 // Setup control and status register
timmey9 34:44cc9b76a507 86 DMA_TCD0_CSR = 0;
timmey9 36:07d8a3143967 87 DMA_TCD1_CSR = 0;
timmey9 46:a015ebf4663b 88 DMA_TCD2_CSR = 0;
timmey9 51:43143a3fc2d7 89 }
timmey9 51:43143a3fc2d7 90
timmey9 51:43143a3fc2d7 91 void dma_reset() {
timmey9 51:43143a3fc2d7 92 // Set memory address for destinations back to the beginning
timmey9 51:43143a3fc2d7 93 dma_init();
timmey9 51:43143a3fc2d7 94 }
timmey9 51:43143a3fc2d7 95
timmey9 51:43143a3fc2d7 96
timmey9 51:43143a3fc2d7 97
timmey9 51:43143a3fc2d7 98
timmey9 51:43143a3fc2d7 99 /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
timmey9 50:33524a27e08c 100 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
timmey9 50:33524a27e08c 101 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
timmey9 50:33524a27e08c 102 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
timmey9 50:33524a27e08c 103 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
timmey9 50:33524a27e08c 104 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
timmey9 50:33524a27e08c 105 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
timmey9 50:33524a27e08c 106 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
timmey9 50:33524a27e08c 107 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
timmey9 50:33524a27e08c 108 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
timmey9 50:33524a27e08c 109 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
timmey9 50:33524a27e08c 110 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
timmey9 50:33524a27e08c 111 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
timmey9 50:33524a27e08c 112 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
timmey9 51:43143a3fc2d7 113 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/