Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

dma.cpp@40:bd6d8c35e822, 2015-01-30 (annotated)

Committer:
timmey9
Date:
Fri Jan 30 06:16:39 2015 +0000
Revision:
40:bd6d8c35e822
Parent:
39:82dc3daecf32
Child:
41:3e0623d81b9a
ADC and DMA working.  Start and stop of ADC/DMA is also working.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 34:44cc9b76a507 1 /*
timmey9 34:44cc9b76a507 2 * dma.c
timmey9 34:44cc9b76a507 3 *
timmey9 34:44cc9b76a507 4 * Created on: Nov 25, 2014
timmey9 34:44cc9b76a507 5 * Author: Manuel Alejandro
timmey9 34:44cc9b76a507 6 */
timmey9 34:44cc9b76a507 7 #include "dma.h"
timmey9 34:44cc9b76a507 8
timmey9 34:44cc9b76a507 9 /* dma_init()
timmey9 34:44cc9b76a507 10 * Initializes the DMA module to read the ADC results every time a conversion has
timmey9 34:44cc9b76a507 11 * finished and stores its value in a buffer
timmey9 34:44cc9b76a507 12 *
timmey9 36:07d8a3143967 13 * @array0 = destination where DMA0 writes
timmey9 36:07d8a3143967 14 * @array1 = destination where DMA1 writes
timmey9 36:07d8a3143967 15 * @array2 = destination where DMA2 writes
timmey9 36:07d8a3143967 16 * @len = the length of array1 and array2, and the number of reads the DMA completes
timmey9 34:44cc9b76a507 17 * */
timmey9 34:44cc9b76a507 18
timmey9 40:bd6d8c35e822 19 void dma_init(int len)
timmey9 34:44cc9b76a507 20 {
timmey9 40:bd6d8c35e822 21
timmey9 36:07d8a3143967 22 // select round-robin arbitration priority
timmey9 36:07d8a3143967 23 DMA_CR |= DMA_CR_ERCA_MASK;
timmey9 36:07d8a3143967 24
timmey9 34:44cc9b76a507 25 // Enable clock for DMAMUX and DMA
timmey9 34:44cc9b76a507 26 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
timmey9 34:44cc9b76a507 27 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
timmey9 34:44cc9b76a507 28
timmey9 34:44cc9b76a507 29 // Enable Channel 0 and set ADC0 as DMA request source
timmey9 36:07d8a3143967 30 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // see page 95 of user manual
timmey9 36:07d8a3143967 31 DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41);
timmey9 37:8bdc71f3e874 32 //DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK |
timmey9 36:07d8a3143967 33
timmey9 36:07d8a3143967 34
timmey9 34:44cc9b76a507 35 // Enable request signal for channel 0
timmey9 36:07d8a3143967 36 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK | DMA_ERQ_ERQ2_MASK;
timmey9 34:44cc9b76a507 37
timmey9 36:07d8a3143967 38 // Set memory address for source and destination for DMA0, DMA1, and DMA2
timmey9 34:44cc9b76a507 39 DMA_TCD0_SADDR = (uint32_t)&ADC0_RA;
timmey9 40:bd6d8c35e822 40 DMA_TCD0_DADDR = (uint32_t) sample_array1;
timmey9 36:07d8a3143967 41 DMA_TCD1_SADDR = (uint32_t)&ADC1_RA;
timmey9 40:bd6d8c35e822 42 DMA_TCD1_DADDR = (uint32_t) sample_array2;
timmey9 36:07d8a3143967 43 DMA_TCD2_SADDR = (uint32_t)&rotary_count;
timmey9 40:bd6d8c35e822 44 DMA_TCD2_DADDR = (uint32_t) angle_array;
timmey9 36:07d8a3143967 45
timmey9 34:44cc9b76a507 46 // Set an offset for source and destination address
timmey9 34:44cc9b76a507 47 DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 34:44cc9b76a507 48 DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 49 DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 50 DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 51 DMA_TCD2_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 52 DMA_TCD2_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 34:44cc9b76a507 53
timmey9 34:44cc9b76a507 54 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 55 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 56 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 57 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 58
timmey9 34:44cc9b76a507 59 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 60 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 61 DMA_TCD1_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 62 DMA_TCD2_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 63
timmey9 34:44cc9b76a507 64 // Current major iteration count (a single iteration of 5 bytes)
timmey9 35:df40c4566826 65 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 35:df40c4566826 66 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 36:07d8a3143967 67 DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 36:07d8a3143967 68 DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 36:07d8a3143967 69 DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 36:07d8a3143967 70 DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 34:44cc9b76a507 71
timmey9 34:44cc9b76a507 72 // Adjustment value used to restore the source and destiny address to the initial value
timmey9 36:07d8a3143967 73 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the address of 'array0')
timmey9 34:44cc9b76a507 74 DMA_TCD0_SLAST = 0x00; // Source address adjustment
timmey9 35:df40c4566826 75 DMA_TCD0_DLASTSGA = -(len*2); // Destination address adjustment
timmey9 36:07d8a3143967 76 DMA_TCD1_SLAST = 0x00; // Source address adjustment
timmey9 36:07d8a3143967 77 DMA_TCD1_DLASTSGA = -(len*2); // Destination address adjustment
timmey9 36:07d8a3143967 78 DMA_TCD2_SLAST = 0x00; // Source address adjustment
timmey9 36:07d8a3143967 79 DMA_TCD2_DLASTSGA = -(len*2); // Destination address adjustment
timmey9 34:44cc9b76a507 80
timmey9 34:44cc9b76a507 81 // Setup control and status register
timmey9 34:44cc9b76a507 82 DMA_TCD0_CSR = 0;
timmey9 36:07d8a3143967 83 DMA_TCD1_CSR = 0;
timmey9 36:07d8a3143967 84 DMA_TCD2_CSR = 1;
timmey9 39:82dc3daecf32 85
timmey9 40:bd6d8c35e822 86 /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
timmey9 39:82dc3daecf32 87 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
timmey9 39:82dc3daecf32 88 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
timmey9 39:82dc3daecf32 89 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
timmey9 39:82dc3daecf32 90 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
timmey9 39:82dc3daecf32 91 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
timmey9 39:82dc3daecf32 92 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
timmey9 39:82dc3daecf32 93 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
timmey9 39:82dc3daecf32 94 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
timmey9 39:82dc3daecf32 95 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
timmey9 39:82dc3daecf32 96 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
timmey9 39:82dc3daecf32 97 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
timmey9 39:82dc3daecf32 98 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
timmey9 39:82dc3daecf32 99 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
timmey9 40:bd6d8c35e822 100 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/
timmey9 34:44cc9b76a507 101 }
timmey9 40:bd6d8c35e822 102
timmey9 40:bd6d8c35e822 103 void reset_dma() {
timmey9 40:bd6d8c35e822 104 // Set memory address for destinations back to the beginning
timmey9 40:bd6d8c35e822 105 DMA_TCD0_DADDR = (uint32_t) sample_array1;
timmey9 40:bd6d8c35e822 106 DMA_TCD1_DADDR = (uint32_t) sample_array2;
timmey9 40:bd6d8c35e822 107 DMA_TCD2_DADDR = (uint32_t) angle_array;
timmey9 40:bd6d8c35e822 108 }