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MODDMA.h@6:40d38be4bb59, 2010-11-23 (annotated)
- Committer:
- AjK
- Date:
- Tue Nov 23 21:34:21 2010 +0000
- Revision:
- 6:40d38be4bb59
- Parent:
- 5:c39b22fa0c60
- Child:
- 7:347110c7aefc
1.3
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AjK | 0:c409efd8df78 | 1 | /* |
AjK | 0:c409efd8df78 | 2 | Copyright (c) 2010 Andy Kirkham |
AjK | 0:c409efd8df78 | 3 | |
AjK | 0:c409efd8df78 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy |
AjK | 0:c409efd8df78 | 5 | of this software and associated documentation files (the "Software"), to deal |
AjK | 0:c409efd8df78 | 6 | in the Software without restriction, including without limitation the rights |
AjK | 0:c409efd8df78 | 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
AjK | 0:c409efd8df78 | 8 | copies of the Software, and to permit persons to whom the Software is |
AjK | 0:c409efd8df78 | 9 | furnished to do so, subject to the following conditions: |
AjK | 0:c409efd8df78 | 10 | |
AjK | 0:c409efd8df78 | 11 | The above copyright notice and this permission notice shall be included in |
AjK | 0:c409efd8df78 | 12 | all copies or substantial portions of the Software. |
AjK | 0:c409efd8df78 | 13 | |
AjK | 0:c409efd8df78 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
AjK | 0:c409efd8df78 | 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
AjK | 0:c409efd8df78 | 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
AjK | 0:c409efd8df78 | 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
AjK | 0:c409efd8df78 | 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
AjK | 0:c409efd8df78 | 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
AjK | 0:c409efd8df78 | 20 | THE SOFTWARE. |
AjK | 0:c409efd8df78 | 21 | |
AjK | 0:c409efd8df78 | 22 | @file MODDMA.h |
AjK | 0:c409efd8df78 | 23 | @purpose Adds DMA controller and multiple transfer configurations |
AjK | 6:40d38be4bb59 | 24 | @version see ChangeLog.c |
AjK | 0:c409efd8df78 | 25 | @date Nov 2010 |
AjK | 0:c409efd8df78 | 26 | @author Andy Kirkham |
AjK | 0:c409efd8df78 | 27 | */ |
AjK | 0:c409efd8df78 | 28 | |
AjK | 0:c409efd8df78 | 29 | #ifndef MODDMA_H |
AjK | 0:c409efd8df78 | 30 | #define MODDMA_H |
AjK | 0:c409efd8df78 | 31 | |
AjK | 3:f61c089ca882 | 32 | /** @defgroup API The MODDMA API */ |
AjK | 0:c409efd8df78 | 33 | /** @defgroup MISC Misc MODSERIAL functions */ |
AjK | 0:c409efd8df78 | 34 | /** @defgroup INTERNALS MODSERIAL Internals */ |
AjK | 0:c409efd8df78 | 35 | |
AjK | 0:c409efd8df78 | 36 | #include "mbed.h" |
AjK | 0:c409efd8df78 | 37 | |
AjK | 0:c409efd8df78 | 38 | namespace AjK { |
AjK | 0:c409efd8df78 | 39 | |
AjK | 0:c409efd8df78 | 40 | /** |
AjK | 1:9700b9455cbf | 41 | * @brief The MODDMA configuration system |
AjK | 0:c409efd8df78 | 42 | * @author Andy Kirkham |
AjK | 1:9700b9455cbf | 43 | * @see http://mbed.org/cookbook/MODDMA_Config |
AjK | 1:9700b9455cbf | 44 | * @see MODDMA |
AjK | 0:c409efd8df78 | 45 | * @see API |
AjK | 0:c409efd8df78 | 46 | * |
AjK | 1:9700b9455cbf | 47 | * <b>MODDMA_Config</b> defines a configuration that can be passed to the MODDMA controller |
AjK | 1:9700b9455cbf | 48 | * instance to perform a GPDMA data transfer. |
AjK | 0:c409efd8df78 | 49 | */ |
AjK | 0:c409efd8df78 | 50 | class MODDMA_Config { |
AjK | 0:c409efd8df78 | 51 | protected: |
AjK | 0:c409efd8df78 | 52 | |
AjK | 0:c409efd8df78 | 53 | // ***************************************** |
AjK | 0:c409efd8df78 | 54 | // From GPDMA by NXP MCU SW Application Team |
AjK | 0:c409efd8df78 | 55 | // ***************************************** |
AjK | 0:c409efd8df78 | 56 | |
AjK | 0:c409efd8df78 | 57 | uint32_t ChannelNum; //!< DMA channel number, should be in range from 0 to 7. |
AjK | 0:c409efd8df78 | 58 | uint32_t TransferSize; //!< Length/Size of transfer |
AjK | 0:c409efd8df78 | 59 | uint32_t TransferWidth; //!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_m2m only |
AjK | 0:c409efd8df78 | 60 | uint32_t SrcMemAddr; //!< Physical Src Addr, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::m2p |
AjK | 0:c409efd8df78 | 61 | uint32_t DstMemAddr; //!< Physical Destination Address, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::p2m |
AjK | 0:c409efd8df78 | 62 | uint32_t TransferType; //!< Transfer Type |
AjK | 0:c409efd8df78 | 63 | uint32_t SrcConn; //!< Peripheral Source Connection type, used in case TransferType is chosen as |
AjK | 0:c409efd8df78 | 64 | uint32_t DstConn; //!< Peripheral Destination Connection type, used in case TransferType is chosen as |
AjK | 0:c409efd8df78 | 65 | uint32_t DMALLI; //!< Linker List Item structure data address if there's no Linker List, set as '0' |
AjK | 0:c409efd8df78 | 66 | |
AjK | 0:c409efd8df78 | 67 | // Mbed specifics. |
AjK | 0:c409efd8df78 | 68 | |
AjK | 0:c409efd8df78 | 69 | public: |
AjK | 0:c409efd8df78 | 70 | |
AjK | 0:c409efd8df78 | 71 | MODDMA_Config() { |
AjK | 0:c409efd8df78 | 72 | isrIntTCStat = new FunctionPointer; |
AjK | 0:c409efd8df78 | 73 | isrIntErrStat = new FunctionPointer; |
AjK | 0:c409efd8df78 | 74 | ChannelNum = 0xFFFF; |
AjK | 0:c409efd8df78 | 75 | TransferSize = 0; |
AjK | 0:c409efd8df78 | 76 | TransferWidth = 0; |
AjK | 0:c409efd8df78 | 77 | SrcMemAddr = 0; |
AjK | 0:c409efd8df78 | 78 | DstMemAddr = 0; |
AjK | 0:c409efd8df78 | 79 | TransferType = 0; |
AjK | 0:c409efd8df78 | 80 | SrcConn = 0; |
AjK | 0:c409efd8df78 | 81 | DstConn = 0; |
AjK | 0:c409efd8df78 | 82 | DMALLI = 0; |
AjK | 0:c409efd8df78 | 83 | } |
AjK | 0:c409efd8df78 | 84 | |
AjK | 0:c409efd8df78 | 85 | ~MODDMA_Config() { |
AjK | 0:c409efd8df78 | 86 | delete(isrIntTCStat); |
AjK | 0:c409efd8df78 | 87 | delete(isrIntErrStat); |
AjK | 0:c409efd8df78 | 88 | } |
AjK | 0:c409efd8df78 | 89 | |
AjK | 0:c409efd8df78 | 90 | class MODDMA_Config * channelNum(uint32_t n) { ChannelNum = n & 0x7; return this; } |
AjK | 0:c409efd8df78 | 91 | class MODDMA_Config * transferSize(uint32_t n) { TransferSize = n; return this; } |
AjK | 0:c409efd8df78 | 92 | class MODDMA_Config * transferWidth(uint32_t n) { TransferWidth = n; return this; } |
AjK | 0:c409efd8df78 | 93 | class MODDMA_Config * srcMemAddr(uint32_t n) { SrcMemAddr = n; return this; } |
AjK | 0:c409efd8df78 | 94 | class MODDMA_Config * dstMemAddr(uint32_t n) { DstMemAddr = n; return this; } |
AjK | 0:c409efd8df78 | 95 | class MODDMA_Config * transferType(uint32_t n) { TransferType = n; return this; } |
AjK | 0:c409efd8df78 | 96 | class MODDMA_Config * srcConn(uint32_t n) { SrcConn = n; return this; } |
AjK | 0:c409efd8df78 | 97 | class MODDMA_Config * dstConn(uint32_t n) { DstConn = n; return this; } |
AjK | 0:c409efd8df78 | 98 | class MODDMA_Config * dmaLLI(uint32_t n) { DMALLI = n; return this; } |
AjK | 0:c409efd8df78 | 99 | |
AjK | 0:c409efd8df78 | 100 | uint32_t channelNum(void) { return ChannelNum; } |
AjK | 0:c409efd8df78 | 101 | uint32_t transferSize(void) { return TransferSize; } |
AjK | 0:c409efd8df78 | 102 | uint32_t transferWidth(void) { return TransferWidth; } |
AjK | 0:c409efd8df78 | 103 | uint32_t srcMemAddr(void) { return SrcMemAddr; } |
AjK | 0:c409efd8df78 | 104 | uint32_t dstMemAddr(void) { return DstMemAddr; } |
AjK | 0:c409efd8df78 | 105 | uint32_t transferType(void) { return TransferType; } |
AjK | 0:c409efd8df78 | 106 | uint32_t srcConn(void) { return SrcConn; } |
AjK | 0:c409efd8df78 | 107 | uint32_t dstConn(void) { return DstConn; } |
AjK | 0:c409efd8df78 | 108 | uint32_t dmaLLI(void) { return DMALLI; } |
AjK | 5:c39b22fa0c60 | 109 | |
AjK | 5:c39b22fa0c60 | 110 | /** |
AjK | 5:c39b22fa0c60 | 111 | * Attach a callback to the TC IRQ configuration. |
AjK | 5:c39b22fa0c60 | 112 | * |
AjK | 5:c39b22fa0c60 | 113 | * @param fptr A function pointer to call |
AjK | 5:c39b22fa0c60 | 114 | * @return this |
AjK | 5:c39b22fa0c60 | 115 | */ |
AjK | 5:c39b22fa0c60 | 116 | class MODDMA_Config * attach_tc(void (*fptr)(void)) { |
AjK | 5:c39b22fa0c60 | 117 | isrIntTCStat->attach(fptr); |
AjK | 5:c39b22fa0c60 | 118 | return this; |
AjK | 5:c39b22fa0c60 | 119 | } |
AjK | 0:c409efd8df78 | 120 | |
AjK | 5:c39b22fa0c60 | 121 | /** |
AjK | 5:c39b22fa0c60 | 122 | * Attach a callback to the ERR IRQ configuration. |
AjK | 5:c39b22fa0c60 | 123 | * |
AjK | 5:c39b22fa0c60 | 124 | * @param fptr A function pointer to call |
AjK | 5:c39b22fa0c60 | 125 | * @return this |
AjK | 5:c39b22fa0c60 | 126 | */ |
AjK | 5:c39b22fa0c60 | 127 | class MODDMA_Config * attach_err(void (*fptr)(void)) { |
AjK | 5:c39b22fa0c60 | 128 | isrIntErrStat->attach(fptr); |
AjK | 5:c39b22fa0c60 | 129 | return this; |
AjK | 5:c39b22fa0c60 | 130 | } |
AjK | 5:c39b22fa0c60 | 131 | |
AjK | 5:c39b22fa0c60 | 132 | /** |
AjK | 5:c39b22fa0c60 | 133 | * Attach a callback to the TC IRQ configuration. |
AjK | 5:c39b22fa0c60 | 134 | * |
AjK | 5:c39b22fa0c60 | 135 | * @param tptr A template pointer to the calling object |
AjK | 5:c39b22fa0c60 | 136 | * @param mptr A method pointer within the object to call. |
AjK | 5:c39b22fa0c60 | 137 | * @return this |
AjK | 5:c39b22fa0c60 | 138 | */ |
AjK | 5:c39b22fa0c60 | 139 | template<typename T> |
AjK | 5:c39b22fa0c60 | 140 | class MODDMA_Config * attach_tc(T* tptr, void (T::*mptr)(void)) { |
AjK | 5:c39b22fa0c60 | 141 | if((mptr != NULL) && (tptr != NULL)) { |
AjK | 5:c39b22fa0c60 | 142 | isrIntTCStat->attach(tptr, mptr); |
AjK | 5:c39b22fa0c60 | 143 | } |
AjK | 5:c39b22fa0c60 | 144 | return this; |
AjK | 5:c39b22fa0c60 | 145 | } |
AjK | 5:c39b22fa0c60 | 146 | |
AjK | 5:c39b22fa0c60 | 147 | /** |
AjK | 5:c39b22fa0c60 | 148 | * Attach a callback to the ERR IRQ configuration. |
AjK | 5:c39b22fa0c60 | 149 | * |
AjK | 5:c39b22fa0c60 | 150 | * @param tptr A template pointer to the calling object |
AjK | 5:c39b22fa0c60 | 151 | * @param mptr A method pointer within the object to call. |
AjK | 5:c39b22fa0c60 | 152 | * @return this |
AjK | 5:c39b22fa0c60 | 153 | */ |
AjK | 5:c39b22fa0c60 | 154 | template<typename T> |
AjK | 5:c39b22fa0c60 | 155 | class MODDMA_Config * attach_err(T* tptr, void (T::*mptr)(void)) { |
AjK | 5:c39b22fa0c60 | 156 | if((mptr != NULL) && (tptr != NULL)) { |
AjK | 5:c39b22fa0c60 | 157 | isrIntErrStat->attach(tptr, mptr); |
AjK | 5:c39b22fa0c60 | 158 | } |
AjK | 5:c39b22fa0c60 | 159 | return this; |
AjK | 5:c39b22fa0c60 | 160 | } |
AjK | 0:c409efd8df78 | 161 | FunctionPointer *isrIntTCStat; |
AjK | 0:c409efd8df78 | 162 | FunctionPointer *isrIntErrStat; |
AjK | 0:c409efd8df78 | 163 | }; |
AjK | 0:c409efd8df78 | 164 | |
AjK | 6:40d38be4bb59 | 165 | /** |
AjK | 6:40d38be4bb59 | 166 | * @brief The MODDMA configuration system (linked list items) |
AjK | 6:40d38be4bb59 | 167 | * @author Andy Kirkham |
AjK | 6:40d38be4bb59 | 168 | * @see http://mbed.org/cookbook/MODDMA_Config |
AjK | 6:40d38be4bb59 | 169 | * @see MODDMA |
AjK | 6:40d38be4bb59 | 170 | * @see MODDMA_Config |
AjK | 6:40d38be4bb59 | 171 | * @see API |
AjK | 6:40d38be4bb59 | 172 | */ |
AjK | 6:40d38be4bb59 | 173 | class MODDMA_LLI { |
AjK | 6:40d38be4bb59 | 174 | public: |
AjK | 6:40d38be4bb59 | 175 | class MODDMA_LLI *srcAddr(uint32_t n) { SrcAddr = n; return this; } |
AjK | 6:40d38be4bb59 | 176 | class MODDMA_LLI *dstAddr(uint32_t n) { DstAddr = n; return this; } |
AjK | 6:40d38be4bb59 | 177 | class MODDMA_LLI *nextLLI(uint32_t n) { NextLLI = n; return this; } |
AjK | 6:40d38be4bb59 | 178 | class MODDMA_LLI *control(uint32_t n) { Control = n; return this; } |
AjK | 6:40d38be4bb59 | 179 | uint32_t srcAddr(void) { return SrcAddr; } |
AjK | 6:40d38be4bb59 | 180 | uint32_t dstAddr(void) { return DstAddr; } |
AjK | 6:40d38be4bb59 | 181 | uint32_t nextLLI(void) { return NextLLI; } |
AjK | 6:40d38be4bb59 | 182 | uint32_t control(void) { return Control; } |
AjK | 6:40d38be4bb59 | 183 | protected: |
AjK | 0:c409efd8df78 | 184 | uint32_t SrcAddr; //!< Source Address |
AjK | 0:c409efd8df78 | 185 | uint32_t DstAddr; //!< Destination address |
AjK | 0:c409efd8df78 | 186 | uint32_t NextLLI; //!< Next LLI address, otherwise set to '0' |
AjK | 0:c409efd8df78 | 187 | uint32_t Control; //!< GPDMA Control of this LLI |
AjK | 6:40d38be4bb59 | 188 | }; |
AjK | 6:40d38be4bb59 | 189 | |
AjK | 0:c409efd8df78 | 190 | |
AjK | 1:9700b9455cbf | 191 | |
AjK | 1:9700b9455cbf | 192 | /** |
AjK | 1:9700b9455cbf | 193 | * @brief MODDMA GPDMA Controller |
AjK | 0:c409efd8df78 | 194 | * @author Andy Kirkham |
AjK | 1:9700b9455cbf | 195 | * @see http://mbed.org/cookbook/MODDMA |
AjK | 1:9700b9455cbf | 196 | * @see example1.cpp |
AjK | 0:c409efd8df78 | 197 | * @see API |
AjK | 0:c409efd8df78 | 198 | * |
AjK | 1:9700b9455cbf | 199 | * <b>MODDMA</b> defines a GPDMA controller and multiple DMA configurations that allow for DMA |
AjK | 0:c409efd8df78 | 200 | * transfers from memory to memory, memory to peripheral or peripheral to memory. |
AjK | 1:9700b9455cbf | 201 | * |
AjK | 3:f61c089ca882 | 202 | * At the heart of the library is the MODDMA class that defines a single instance controller that |
AjK | 1:9700b9455cbf | 203 | * manages all the GPDMA hardware registers and interrupts. The controller can accept multiple |
AjK | 3:f61c089ca882 | 204 | * configurations that define the channel transfers. Each configuration specifies the source and |
AjK | 3:f61c089ca882 | 205 | * destination information and other associated parts to maintain the transfer process. |
AjK | 1:9700b9455cbf | 206 | * |
AjK | 1:9700b9455cbf | 207 | * Standard example: |
AjK | 1:9700b9455cbf | 208 | * @code |
AjK | 1:9700b9455cbf | 209 | * #include "mbed.h" |
AjK | 1:9700b9455cbf | 210 | * #include "MODDMA.h" |
AjK | 1:9700b9455cbf | 211 | * |
AjK | 1:9700b9455cbf | 212 | * DigitalOut led1(LED1); |
AjK | 1:9700b9455cbf | 213 | * Serial pc(USBTX, USBRX); // tx, rx |
AjK | 1:9700b9455cbf | 214 | * MODDMA dma; |
AjK | 1:9700b9455cbf | 215 | * |
AjK | 1:9700b9455cbf | 216 | * int main() { |
AjK | 1:9700b9455cbf | 217 | * |
AjK | 1:9700b9455cbf | 218 | * // Create a string buffer to send directly to a Uart/Serial |
AjK | 1:9700b9455cbf | 219 | * char s[] = "***DMA*** ABCDEFGHIJKLMNOPQRSTUVWXYZ ***DMA***"; |
AjK | 1:9700b9455cbf | 220 | * |
AjK | 1:9700b9455cbf | 221 | * // Create a transfer configuarion |
AjK | 1:9700b9455cbf | 222 | * MODDMA_Config *config = new MODDMA_Config; |
AjK | 1:9700b9455cbf | 223 | * |
AjK | 1:9700b9455cbf | 224 | * // Provide a "minimal" setup for demo purposes. |
AjK | 1:9700b9455cbf | 225 | * config |
AjK | 1:9700b9455cbf | 226 | * ->channelNum ( MODDMA::Channel_0 ) // The DMA channel to use. |
AjK | 1:9700b9455cbf | 227 | * ->srcMemAddr ( (uint32_t) &s ) // A pointer to the buffer to send. |
AjK | 1:9700b9455cbf | 228 | * ->transferSize ( sizeof(s) ) // The size of that buffer. |
AjK | 3:f61c089ca882 | 229 | * ->transferType ( MODDMA::m2p ) // Source is memory, destination is peripheral |
AjK | 1:9700b9455cbf | 230 | * ->dstConn ( MODDMA::UART0_Tx ) // Specifically, peripheral is Uart0 TX (USBTX, USBRX) |
AjK | 1:9700b9455cbf | 231 | * ; // config end. |
AjK | 1:9700b9455cbf | 232 | * |
AjK | 1:9700b9455cbf | 233 | * // Pass the configuration to the MODDMA controller. |
AjK | 1:9700b9455cbf | 234 | * dma.Setup( config ); |
AjK | 1:9700b9455cbf | 235 | * |
AjK | 1:9700b9455cbf | 236 | * // Enable the channel and begin transfer. |
AjK | 1:9700b9455cbf | 237 | * dma.Enable( config->channelNum() ); |
AjK | 1:9700b9455cbf | 238 | * |
AjK | 1:9700b9455cbf | 239 | * while(1) { |
AjK | 1:9700b9455cbf | 240 | * led1 = !led1; |
AjK | 1:9700b9455cbf | 241 | * wait(0.25); |
AjK | 1:9700b9455cbf | 242 | * } |
AjK | 1:9700b9455cbf | 243 | * } |
AjK | 1:9700b9455cbf | 244 | * @endcode |
AjK | 0:c409efd8df78 | 245 | */ |
AjK | 0:c409efd8df78 | 246 | class MODDMA |
AjK | 0:c409efd8df78 | 247 | { |
AjK | 0:c409efd8df78 | 248 | public: |
AjK | 0:c409efd8df78 | 249 | |
AjK | 0:c409efd8df78 | 250 | //! Channel definitions. |
AjK | 0:c409efd8df78 | 251 | enum CHANNELS { |
AjK | 0:c409efd8df78 | 252 | Channel_0 = 0 /*!< Channel 0 */ |
AjK | 0:c409efd8df78 | 253 | , Channel_1 /*!< Channel 1 */ |
AjK | 0:c409efd8df78 | 254 | , Channel_2 /*!< Channel 2 */ |
AjK | 0:c409efd8df78 | 255 | , Channel_3 /*!< Channel 3 */ |
AjK | 0:c409efd8df78 | 256 | , Channel_4 /*!< Channel 4 */ |
AjK | 0:c409efd8df78 | 257 | , Channel_5 /*!< Channel 5 */ |
AjK | 0:c409efd8df78 | 258 | , Channel_6 /*!< Channel 6 */ |
AjK | 0:c409efd8df78 | 259 | , Channel_7 /*!< Channel 7 */ |
AjK | 0:c409efd8df78 | 260 | }; |
AjK | 0:c409efd8df78 | 261 | |
AjK | 0:c409efd8df78 | 262 | //! Interrupt callback types. |
AjK | 0:c409efd8df78 | 263 | enum IrqType_t { |
AjK | 0:c409efd8df78 | 264 | TcIrq = 0 /*!< Terminal Count interrupt */ |
AjK | 0:c409efd8df78 | 265 | , ErrIrq /*!< Error interrupt */ |
AjK | 0:c409efd8df78 | 266 | }; |
AjK | 0:c409efd8df78 | 267 | |
AjK | 0:c409efd8df78 | 268 | //! Return status codes. |
AjK | 0:c409efd8df78 | 269 | enum Status { |
AjK | 0:c409efd8df78 | 270 | Ok = 0 /*!< Ok, suceeded */ |
AjK | 0:c409efd8df78 | 271 | , Error = -1 /*!< General error */ |
AjK | 0:c409efd8df78 | 272 | , ErrChInUse = -2 /*!< Specific error, channel in use */ |
AjK | 0:c409efd8df78 | 273 | }; |
AjK | 0:c409efd8df78 | 274 | |
AjK | 0:c409efd8df78 | 275 | //! DMA Connection number definitions |
AjK | 0:c409efd8df78 | 276 | enum GPDMA_CONNECTION { |
AjK | 0:c409efd8df78 | 277 | SSP0_Tx = 0UL /*!< SSP0 Tx */ |
AjK | 0:c409efd8df78 | 278 | , SSP0_Rx = 1UL /*!< SSP0 Rx */ |
AjK | 0:c409efd8df78 | 279 | , SSP1_Tx = 2UL /*!< SSP1 Tx */ |
AjK | 0:c409efd8df78 | 280 | , SSP1_Rx = 3UL /*!< SSP1 Rx */ |
AjK | 0:c409efd8df78 | 281 | , ADC = 4UL /*!< ADC */ |
AjK | 0:c409efd8df78 | 282 | , I2S_Channel_0 = 5UL /*!< I2S channel 0 */ |
AjK | 0:c409efd8df78 | 283 | , I2S_Channel_1 = 6UL /*!< I2S channel 1 */ |
AjK | 0:c409efd8df78 | 284 | , DAC = 7UL /*!< DAC */ |
AjK | 0:c409efd8df78 | 285 | , UART0_Tx = 8UL /*!< UART0 Tx */ |
AjK | 0:c409efd8df78 | 286 | , UART0_Rx = 9UL /*!< UART0 Rx */ |
AjK | 0:c409efd8df78 | 287 | , UART1_Tx = 10UL /*!< UART1 Tx */ |
AjK | 0:c409efd8df78 | 288 | , UART1_Rx = 11UL /*!< UART1 Rx */ |
AjK | 0:c409efd8df78 | 289 | , UART2_Tx = 12UL /*!< UART2 Tx */ |
AjK | 0:c409efd8df78 | 290 | , UART2_Rx = 13UL /*!< UART2 Rx */ |
AjK | 0:c409efd8df78 | 291 | , UART3_Tx = 14UL /*!< UART3 Tx */ |
AjK | 0:c409efd8df78 | 292 | , UART3_Rx = 15UL /*!< UART3 Rx */ |
AjK | 0:c409efd8df78 | 293 | , MAT0_0 = 16UL /*!< MAT0.0 */ |
AjK | 0:c409efd8df78 | 294 | , MAT0_1 = 17UL /*!< MAT0.1 */ |
AjK | 0:c409efd8df78 | 295 | , MAT1_0 = 18UL /*!< MAT1.0 */ |
AjK | 0:c409efd8df78 | 296 | , MAT1_1 = 19UL /*!< MAT1.1 */ |
AjK | 0:c409efd8df78 | 297 | , MAT2_0 = 20UL /**< MAT2.0 */ |
AjK | 0:c409efd8df78 | 298 | , MAT2_1 = 21UL /*!< MAT2.1 */ |
AjK | 0:c409efd8df78 | 299 | , MAT3_0 = 22UL /*!< MAT3.0 */ |
AjK | 0:c409efd8df78 | 300 | , MAT3_1 = 23UL /*!< MAT3.1 */ |
AjK | 0:c409efd8df78 | 301 | }; |
AjK | 0:c409efd8df78 | 302 | |
AjK | 0:c409efd8df78 | 303 | //! GPDMA Transfer type definitions |
AjK | 0:c409efd8df78 | 304 | enum GPDMA_TRANSFERTYPE { |
AjK | 0:c409efd8df78 | 305 | m2m = 0UL /*!< Memory to memory - DMA control */ |
AjK | 0:c409efd8df78 | 306 | , m2p = 1UL /*!< Memory to peripheral - DMA control */ |
AjK | 0:c409efd8df78 | 307 | , p2m = 2UL /*!< Peripheral to memory - DMA control */ |
AjK | 0:c409efd8df78 | 308 | , p2p = 3UL /*!< Src peripheral to dest peripheral - DMA control */ |
AjK | 0:c409efd8df78 | 309 | }; |
AjK | 0:c409efd8df78 | 310 | |
AjK | 0:c409efd8df78 | 311 | //! Burst size in Source and Destination definitions */ |
AjK | 0:c409efd8df78 | 312 | enum GPDMA_BSIZE { |
AjK | 0:c409efd8df78 | 313 | _1 = 0UL /*!< Burst size = 1 */ |
AjK | 0:c409efd8df78 | 314 | , _4 = 1UL /*!< Burst size = 4 */ |
AjK | 0:c409efd8df78 | 315 | , _8 = 2UL /*!< Burst size = 8 */ |
AjK | 0:c409efd8df78 | 316 | , _16 = 3UL /*!< Burst size = 16 */ |
AjK | 0:c409efd8df78 | 317 | , _32 = 4UL /*!< Burst size = 32 */ |
AjK | 0:c409efd8df78 | 318 | , _64 = 5UL /*!< Burst size = 64 */ |
AjK | 0:c409efd8df78 | 319 | , _128 = 6UL /*!< Burst size = 128 */ |
AjK | 0:c409efd8df78 | 320 | , _256 = 7UL /*!< Burst size = 256 */ |
AjK | 0:c409efd8df78 | 321 | }; |
AjK | 0:c409efd8df78 | 322 | |
AjK | 0:c409efd8df78 | 323 | //! Width in Src transfer width and Dest transfer width definitions */ |
AjK | 0:c409efd8df78 | 324 | enum GPDMA_WIDTH { |
AjK | 0:c409efd8df78 | 325 | byte = 0UL /*!< Width = 1 byte */ |
AjK | 0:c409efd8df78 | 326 | , halfword = 1UL /*!< Width = 2 bytes */ |
AjK | 0:c409efd8df78 | 327 | , word = 2UL /*!< Width = 4 bytes */ |
AjK | 0:c409efd8df78 | 328 | }; |
AjK | 0:c409efd8df78 | 329 | |
AjK | 0:c409efd8df78 | 330 | //! DMA Request Select Mode definitions. */ |
AjK | 0:c409efd8df78 | 331 | enum GPDMA_REQSEL { |
AjK | 0:c409efd8df78 | 332 | uart = 0UL /*!< UART TX/RX is selected */ |
AjK | 0:c409efd8df78 | 333 | , timer = 1UL /*!< Timer match is selected */ |
AjK | 0:c409efd8df78 | 334 | }; |
AjK | 0:c409efd8df78 | 335 | |
AjK | 0:c409efd8df78 | 336 | //! GPDMA Control register bits. |
AjK | 0:c409efd8df78 | 337 | enum Config { |
AjK | 0:c409efd8df78 | 338 | _E = 1 /*!< DMA Controller enable */ |
AjK | 0:c409efd8df78 | 339 | , _M = 2 /*!< AHB Master endianness configuration */ |
AjK | 0:c409efd8df78 | 340 | }; |
AjK | 0:c409efd8df78 | 341 | |
AjK | 0:c409efd8df78 | 342 | //! GPDMA Channel config register bits. |
AjK | 0:c409efd8df78 | 343 | enum CConfig { |
AjK | 0:c409efd8df78 | 344 | _CE = (1UL << 0) /*!< Channel enable */ |
AjK | 0:c409efd8df78 | 345 | , _IE = (1UL << 14) /*!< Interrupt error mask */ |
AjK | 0:c409efd8df78 | 346 | , _ITC = (1UL << 15) /*!< Terminal count interrupt mask */ |
AjK | 0:c409efd8df78 | 347 | , _L = (1UL << 16) /*!< Lock */ |
AjK | 0:c409efd8df78 | 348 | , _A = (1UL << 17) /*!< Active */ |
AjK | 0:c409efd8df78 | 349 | , _H = (1UL << 18) /*!< Halt */ |
AjK | 0:c409efd8df78 | 350 | }; |
AjK | 0:c409efd8df78 | 351 | |
AjK | 0:c409efd8df78 | 352 | /** |
AjK | 0:c409efd8df78 | 353 | * The MODDMA constructor is used to initialise the DMA controller object. |
AjK | 0:c409efd8df78 | 354 | */ |
AjK | 0:c409efd8df78 | 355 | MODDMA() { init(true); } |
AjK | 0:c409efd8df78 | 356 | |
AjK | 0:c409efd8df78 | 357 | /** |
AjK | 0:c409efd8df78 | 358 | * The MODDMA destructor. |
AjK | 0:c409efd8df78 | 359 | */ |
AjK | 0:c409efd8df78 | 360 | ~MODDMA() {} |
AjK | 0:c409efd8df78 | 361 | |
AjK | 0:c409efd8df78 | 362 | /** |
AjK | 0:c409efd8df78 | 363 | * Used to setup the DMA controller to prepare for a data transfer. |
AjK | 0:c409efd8df78 | 364 | * |
AjK | 3:f61c089ca882 | 365 | * @ingroup API |
AjK | 6:40d38be4bb59 | 366 | * @param isConstructorCalling Set true when called from teh constructor |
AjK | 6:40d38be4bb59 | 367 | * @param |
AjK | 6:40d38be4bb59 | 368 | */ |
AjK | 6:40d38be4bb59 | 369 | void init(bool isConstructorCalling, int Channels = 0xFF, int Tc = 0xFF, int Err = 0xFF); |
AjK | 6:40d38be4bb59 | 370 | |
AjK | 6:40d38be4bb59 | 371 | /** |
AjK | 6:40d38be4bb59 | 372 | * Used to setup the DMA controller to prepare for a data transfer. |
AjK | 6:40d38be4bb59 | 373 | * |
AjK | 6:40d38be4bb59 | 374 | * @ingroup API |
AjK | 0:c409efd8df78 | 375 | * @param c A pointer to an instance of MODDMA_Config to setup. |
AjK | 0:c409efd8df78 | 376 | */ |
AjK | 0:c409efd8df78 | 377 | Status Setup(MODDMA_Config *c); |
AjK | 0:c409efd8df78 | 378 | |
AjK | 0:c409efd8df78 | 379 | /** |
AjK | 0:c409efd8df78 | 380 | * Enable and begin data transfer. |
AjK | 0:c409efd8df78 | 381 | * |
AjK | 3:f61c089ca882 | 382 | * @ingroup API |
AjK | 0:c409efd8df78 | 383 | * @param ChannelNumber Type CHANNELS, the channel number to enable |
AjK | 0:c409efd8df78 | 384 | */ |
AjK | 0:c409efd8df78 | 385 | void Enable(CHANNELS ChannelNumber); |
AjK | 0:c409efd8df78 | 386 | |
AjK | 0:c409efd8df78 | 387 | /** |
AjK | 0:c409efd8df78 | 388 | * Enable and begin data transfer (overloaded function) |
AjK | 0:c409efd8df78 | 389 | * |
AjK | 3:f61c089ca882 | 390 | * @ingroup API |
AjK | 0:c409efd8df78 | 391 | * @param ChannelNumber Type uin32_t, the channel number to enable |
AjK | 0:c409efd8df78 | 392 | */ |
AjK | 0:c409efd8df78 | 393 | void Enable(uint32_t ChannelNumber) { Enable((CHANNELS)(ChannelNumber & 0x7)); } |
AjK | 0:c409efd8df78 | 394 | |
AjK | 0:c409efd8df78 | 395 | /** |
AjK | 0:c409efd8df78 | 396 | * Disable a channel and end data transfer. |
AjK | 0:c409efd8df78 | 397 | * |
AjK | 3:f61c089ca882 | 398 | * @ingroup API |
AjK | 0:c409efd8df78 | 399 | * @param ChannelNumber Type CHANNELS, the channel number to enable |
AjK | 0:c409efd8df78 | 400 | */ |
AjK | 0:c409efd8df78 | 401 | void Disable(CHANNELS ChannelNumber); |
AjK | 0:c409efd8df78 | 402 | |
AjK | 0:c409efd8df78 | 403 | /** |
AjK | 0:c409efd8df78 | 404 | * Disable a channel and end data transfer (overloaded function) |
AjK | 0:c409efd8df78 | 405 | * |
AjK | 3:f61c089ca882 | 406 | * @ingroup API |
AjK | 0:c409efd8df78 | 407 | * @param ChannelNumber Type uin32_t, the channel number to disable |
AjK | 0:c409efd8df78 | 408 | */ |
AjK | 0:c409efd8df78 | 409 | void Disable(uint32_t ChannelNumber) { Disable((CHANNELS)(ChannelNumber & 0x7)); } |
AjK | 0:c409efd8df78 | 410 | |
AjK | 0:c409efd8df78 | 411 | /** |
AjK | 0:c409efd8df78 | 412 | * Is the specified channel enabled? |
AjK | 0:c409efd8df78 | 413 | * |
AjK | 3:f61c089ca882 | 414 | * @ingroup API |
AjK | 0:c409efd8df78 | 415 | * @param ChannelNumber Type CHANNELS, the channel number to test |
AjK | 0:c409efd8df78 | 416 | * @return bool true if enabled, false otherwise. |
AjK | 0:c409efd8df78 | 417 | */ |
AjK | 0:c409efd8df78 | 418 | bool Enabled(CHANNELS ChannelNumber); |
AjK | 0:c409efd8df78 | 419 | |
AjK | 0:c409efd8df78 | 420 | /** |
AjK | 0:c409efd8df78 | 421 | * Is the specified channel enabled? (overloaded function) |
AjK | 0:c409efd8df78 | 422 | * |
AjK | 3:f61c089ca882 | 423 | * @ingroup API |
AjK | 0:c409efd8df78 | 424 | * @param ChannelNumber Type uin32_t, the channel number to test |
AjK | 0:c409efd8df78 | 425 | * @return bool true if enabled, false otherwise. |
AjK | 0:c409efd8df78 | 426 | */ |
AjK | 4:67f327b9278e | 427 | bool Enabled(uint32_t ChannelNumber) { return Enabled((CHANNELS)(ChannelNumber & 0x7)); } |
AjK | 0:c409efd8df78 | 428 | |
AjK | 0:c409efd8df78 | 429 | __INLINE uint32_t IntStat(uint32_t n) { return (1UL << n) & 0xFF; } |
AjK | 0:c409efd8df78 | 430 | __INLINE uint32_t IntTCStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; } |
AjK | 0:c409efd8df78 | 431 | __INLINE uint32_t IntTCClear_Ch(uint32_t n) { return (1UL << n) & 0xFF; } |
AjK | 0:c409efd8df78 | 432 | __INLINE uint32_t IntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; } |
AjK | 0:c409efd8df78 | 433 | __INLINE uint32_t IntErrClr_Ch(uint32_t n) { return (1UL << n) & 0xFF; } |
AjK | 0:c409efd8df78 | 434 | __INLINE uint32_t RawIntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; } |
AjK | 0:c409efd8df78 | 435 | __INLINE uint32_t EnbldChns_Ch(uint32_t n) { return (1UL << n) & 0xFF; } |
AjK | 0:c409efd8df78 | 436 | __INLINE uint32_t SoftBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; } |
AjK | 0:c409efd8df78 | 437 | __INLINE uint32_t SoftSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; } |
AjK | 0:c409efd8df78 | 438 | __INLINE uint32_t SoftLBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; } |
AjK | 0:c409efd8df78 | 439 | __INLINE uint32_t SoftLSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; } |
AjK | 0:c409efd8df78 | 440 | __INLINE uint32_t Sync_Src(uint32_t n) { return (1UL << n) & 0xFFFF; } |
AjK | 0:c409efd8df78 | 441 | __INLINE uint32_t ReqSel_Input(uint32_t n) { return (1UL << (n - 8)) & 0xFF; } |
AjK | 0:c409efd8df78 | 442 | |
AjK | 0:c409efd8df78 | 443 | |
AjK | 0:c409efd8df78 | 444 | __INLINE uint32_t CxControl_TransferSize(uint32_t n) { return (n & 0xFFF) << 0; } |
AjK | 0:c409efd8df78 | 445 | __INLINE uint32_t CxControl_SBSize(uint32_t n) { return (n & 0x7) << 12; } |
AjK | 0:c409efd8df78 | 446 | __INLINE uint32_t CxControl_DBSize(uint32_t n) { return (n & 0x7) << 15; } |
AjK | 0:c409efd8df78 | 447 | __INLINE uint32_t CxControl_SWidth(uint32_t n) { return (n & 0x7) << 18; } |
AjK | 0:c409efd8df78 | 448 | __INLINE uint32_t CxControl_DWidth(uint32_t n) { return (n & 0x7) << 21; } |
AjK | 0:c409efd8df78 | 449 | __INLINE uint32_t CxControl_SI() { return (1UL << 26); } |
AjK | 0:c409efd8df78 | 450 | __INLINE uint32_t CxControl_DI() { return (1UL << 27); } |
AjK | 0:c409efd8df78 | 451 | __INLINE uint32_t CxControl_Prot1() { return (1UL << 28); } |
AjK | 0:c409efd8df78 | 452 | __INLINE uint32_t CxControl_Prot2() { return (1UL << 29); } |
AjK | 0:c409efd8df78 | 453 | __INLINE uint32_t CxControl_Prot3() { return (1UL << 30); } |
AjK | 0:c409efd8df78 | 454 | __INLINE uint32_t CxControl_I() { return (1UL << 31); } |
AjK | 0:c409efd8df78 | 455 | __INLINE uint32_t CxControl_E() { return (1UL << 0); } |
AjK | 0:c409efd8df78 | 456 | __INLINE uint32_t CxConfig_SrcPeripheral(uint32_t n) { return (n & 0x1F) << 1; } |
AjK | 0:c409efd8df78 | 457 | __INLINE uint32_t CxConfig_DestPeripheral(uint32_t n) { return (n & 0x1F) << 6; } |
AjK | 0:c409efd8df78 | 458 | __INLINE uint32_t CxConfig_TransferType(uint32_t n) { return (n & 0x7) << 11; } |
AjK | 0:c409efd8df78 | 459 | __INLINE uint32_t CxConfig_IE() { return (1UL << 14); } |
AjK | 0:c409efd8df78 | 460 | __INLINE uint32_t CxConfig_ITC() { return (1UL << 15); } |
AjK | 0:c409efd8df78 | 461 | __INLINE uint32_t CxConfig_L() { return (1UL << 16); } |
AjK | 0:c409efd8df78 | 462 | __INLINE uint32_t CxConfig_A() { return (1UL << 17); } |
AjK | 0:c409efd8df78 | 463 | __INLINE uint32_t CxConfig_H() { return (1UL << 18); } |
AjK | 0:c409efd8df78 | 464 | |
AjK | 0:c409efd8df78 | 465 | /** |
AjK | 0:c409efd8df78 | 466 | * A store for up to 8 (8 channels) of configurations. |
AjK | 0:c409efd8df78 | 467 | * @see MODDMA_Config |
AjK | 0:c409efd8df78 | 468 | */ |
AjK | 0:c409efd8df78 | 469 | MODDMA_Config *setups[8]; |
AjK | 0:c409efd8df78 | 470 | |
AjK | 0:c409efd8df78 | 471 | /** |
AjK | 0:c409efd8df78 | 472 | * Get a pointer to the current configuration the ISR is servicing. |
AjK | 0:c409efd8df78 | 473 | * |
AjK | 3:f61c089ca882 | 474 | * @ingroup API |
AjK | 0:c409efd8df78 | 475 | * @return MODDMA_Config * A pointer to the setup the ISR is currently servicing. |
AjK | 0:c409efd8df78 | 476 | */ |
AjK | 0:c409efd8df78 | 477 | MODDMA_Config *getConfig(void) { return setups[IrqProcessingChannel]; } |
AjK | 0:c409efd8df78 | 478 | |
AjK | 0:c409efd8df78 | 479 | /** |
AjK | 0:c409efd8df78 | 480 | * Set which channel the ISR is currently servicing. |
AjK | 0:c409efd8df78 | 481 | * |
AjK | 0:c409efd8df78 | 482 | * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS *** |
AjK | 0:c409efd8df78 | 483 | * |
AjK | 0:c409efd8df78 | 484 | * Must be public so the extern "C" ISR can use it. |
AjK | 0:c409efd8df78 | 485 | */ |
AjK | 0:c409efd8df78 | 486 | void setIrqProcessingChannel(CHANNELS n) { IrqProcessingChannel = n; } |
AjK | 0:c409efd8df78 | 487 | |
AjK | 0:c409efd8df78 | 488 | /** |
AjK | 0:c409efd8df78 | 489 | * Gets which channel the ISR is currently servicing. |
AjK | 0:c409efd8df78 | 490 | * |
AjK | 3:f61c089ca882 | 491 | * @ingroup API |
AjK | 0:c409efd8df78 | 492 | * @return CHANNELS The current channel the ISR is servicing. |
AjK | 0:c409efd8df78 | 493 | */ |
AjK | 0:c409efd8df78 | 494 | CHANNELS irqProcessingChannel(void) { return IrqProcessingChannel; } |
AjK | 0:c409efd8df78 | 495 | |
AjK | 0:c409efd8df78 | 496 | /** |
AjK | 0:c409efd8df78 | 497 | * Sets which type of IRQ the ISR is making a callback for. |
AjK | 0:c409efd8df78 | 498 | * |
AjK | 0:c409efd8df78 | 499 | * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS *** |
AjK | 0:c409efd8df78 | 500 | * |
AjK | 0:c409efd8df78 | 501 | * Must be public so the extern "C" ISR can use it. |
AjK | 0:c409efd8df78 | 502 | */ |
AjK | 0:c409efd8df78 | 503 | void setIrqType(IrqType_t n) { IrqType = n; } |
AjK | 0:c409efd8df78 | 504 | |
AjK | 0:c409efd8df78 | 505 | /** |
AjK | 0:c409efd8df78 | 506 | * Get which type of IRQ the ISR is calling you about, |
AjK | 0:c409efd8df78 | 507 | * terminal count or error. |
AjK | 0:c409efd8df78 | 508 | */ |
AjK | 0:c409efd8df78 | 509 | IrqType_t irqType(void) { return IrqType; } |
AjK | 0:c409efd8df78 | 510 | |
AjK | 0:c409efd8df78 | 511 | /** |
AjK | 0:c409efd8df78 | 512 | * Clear the interrupt after handling. |
AjK | 0:c409efd8df78 | 513 | * |
AjK | 0:c409efd8df78 | 514 | * @param CHANNELS The channel the IQR occured on. |
AjK | 0:c409efd8df78 | 515 | */ |
AjK | 0:c409efd8df78 | 516 | void clearTcIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); } |
AjK | 0:c409efd8df78 | 517 | |
AjK | 0:c409efd8df78 | 518 | /** |
AjK | 0:c409efd8df78 | 519 | * Clear the interrupt the ISR is currently handing.. |
AjK | 0:c409efd8df78 | 520 | */ |
AjK | 0:c409efd8df78 | 521 | void clearTcIrq(void) { clearTcIrq( IrqProcessingChannel ); } |
AjK | 0:c409efd8df78 | 522 | |
AjK | 0:c409efd8df78 | 523 | /** |
AjK | 0:c409efd8df78 | 524 | * Clear the error interrupt after handling. |
AjK | 0:c409efd8df78 | 525 | * |
AjK | 3:f61c089ca882 | 526 | * @ingroup API |
AjK | 0:c409efd8df78 | 527 | * @param CHANNELS The channel the IQR occured on. |
AjK | 0:c409efd8df78 | 528 | */ |
AjK | 0:c409efd8df78 | 529 | void clearErrIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); } |
AjK | 0:c409efd8df78 | 530 | |
AjK | 0:c409efd8df78 | 531 | /** |
AjK | 0:c409efd8df78 | 532 | * Clear the error interrupt the ISR is currently handing. |
AjK | 3:f61c089ca882 | 533 | * @ingroup API |
AjK | 0:c409efd8df78 | 534 | */ |
AjK | 0:c409efd8df78 | 535 | void clearErrIrq(void) { clearErrIrq( IrqProcessingChannel ); } |
AjK | 0:c409efd8df78 | 536 | |
AjK | 0:c409efd8df78 | 537 | /** |
AjK | 0:c409efd8df78 | 538 | * Is the supplied channel currently active? |
AjK | 0:c409efd8df78 | 539 | * |
AjK | 3:f61c089ca882 | 540 | * @ingroup API |
AjK | 0:c409efd8df78 | 541 | * @param CHANNELS The channel to inquire about. |
AjK | 0:c409efd8df78 | 542 | * @return bool true if active, false otherwise. |
AjK | 0:c409efd8df78 | 543 | */ |
AjK | 0:c409efd8df78 | 544 | bool isActive(CHANNELS ChannelNumber); |
AjK | 0:c409efd8df78 | 545 | |
AjK | 0:c409efd8df78 | 546 | /** |
AjK | 0:c409efd8df78 | 547 | * Halt the supplied channel. |
AjK | 0:c409efd8df78 | 548 | * |
AjK | 3:f61c089ca882 | 549 | * @ingroup API |
AjK | 0:c409efd8df78 | 550 | * @param CHANNELS The channel to halt. |
AjK | 0:c409efd8df78 | 551 | */ |
AjK | 0:c409efd8df78 | 552 | void haltChannel(CHANNELS ChannelNumber); |
AjK | 0:c409efd8df78 | 553 | |
AjK | 0:c409efd8df78 | 554 | /** |
AjK | 0:c409efd8df78 | 555 | * Wait for channel transfer to complete and then halt. |
AjK | 0:c409efd8df78 | 556 | * |
AjK | 3:f61c089ca882 | 557 | * @ingroup API |
AjK | 0:c409efd8df78 | 558 | * @param CHANNELS The channel to wait for then halt. |
AjK | 0:c409efd8df78 | 559 | */ |
AjK | 0:c409efd8df78 | 560 | void haltAndWaitChannelComplete(CHANNELS n) { haltChannel(n); while (isActive(n)); } |
AjK | 0:c409efd8df78 | 561 | |
AjK | 0:c409efd8df78 | 562 | /** |
AjK | 5:c39b22fa0c60 | 563 | * Attach a callback to the TC IRQ controller. |
AjK | 5:c39b22fa0c60 | 564 | * |
AjK | 5:c39b22fa0c60 | 565 | * @ingroup API |
AjK | 5:c39b22fa0c60 | 566 | * @param fptr A function pointer to call |
AjK | 5:c39b22fa0c60 | 567 | * @return this |
AjK | 5:c39b22fa0c60 | 568 | */ |
AjK | 5:c39b22fa0c60 | 569 | void attach_tc(void (*fptr)(void)) { |
AjK | 5:c39b22fa0c60 | 570 | isrIntTCStat.attach(fptr); |
AjK | 5:c39b22fa0c60 | 571 | } |
AjK | 5:c39b22fa0c60 | 572 | |
AjK | 5:c39b22fa0c60 | 573 | /** |
AjK | 5:c39b22fa0c60 | 574 | * Attach a callback to the TC IRQ controller. |
AjK | 5:c39b22fa0c60 | 575 | * |
AjK | 5:c39b22fa0c60 | 576 | * @ingroup API |
AjK | 5:c39b22fa0c60 | 577 | * @param tptr A template pointer to the calling object |
AjK | 5:c39b22fa0c60 | 578 | * @param mptr A method pointer within the object to call. |
AjK | 5:c39b22fa0c60 | 579 | * @return this |
AjK | 5:c39b22fa0c60 | 580 | */ |
AjK | 5:c39b22fa0c60 | 581 | template<typename T> |
AjK | 6:40d38be4bb59 | 582 | void attach_tc(T* tptr, void (T::*mptr)(void)) { |
AjK | 5:c39b22fa0c60 | 583 | if((mptr != NULL) && (tptr != NULL)) { |
AjK | 5:c39b22fa0c60 | 584 | isrIntTCStat.attach(tptr, mptr); |
AjK | 6:40d38be4bb59 | 585 | } |
AjK | 5:c39b22fa0c60 | 586 | } |
AjK | 5:c39b22fa0c60 | 587 | |
AjK | 5:c39b22fa0c60 | 588 | /** |
AjK | 0:c409efd8df78 | 589 | * The MODDMA controllers terminal count interrupt callback. |
AjK | 0:c409efd8df78 | 590 | */ |
AjK | 0:c409efd8df78 | 591 | FunctionPointer isrIntTCStat; |
AjK | 0:c409efd8df78 | 592 | |
AjK | 0:c409efd8df78 | 593 | /** |
AjK | 5:c39b22fa0c60 | 594 | * Attach a callback to the ERR IRQ controller. |
AjK | 5:c39b22fa0c60 | 595 | * |
AjK | 5:c39b22fa0c60 | 596 | * @ingroup API |
AjK | 5:c39b22fa0c60 | 597 | * @param fptr A function pointer to call |
AjK | 5:c39b22fa0c60 | 598 | * @return this |
AjK | 5:c39b22fa0c60 | 599 | */ |
AjK | 5:c39b22fa0c60 | 600 | void attach_err(void (*fptr)(void)) { |
AjK | 6:40d38be4bb59 | 601 | isrIntErrStat.attach(fptr); |
AjK | 5:c39b22fa0c60 | 602 | } |
AjK | 5:c39b22fa0c60 | 603 | |
AjK | 5:c39b22fa0c60 | 604 | /** |
AjK | 5:c39b22fa0c60 | 605 | * Attach a callback to the ERR IRQ controller. |
AjK | 5:c39b22fa0c60 | 606 | * |
AjK | 5:c39b22fa0c60 | 607 | * @ingroup API |
AjK | 5:c39b22fa0c60 | 608 | * @param tptr A template pointer to the calling object |
AjK | 5:c39b22fa0c60 | 609 | * @param mptr A method pointer within the object to call. |
AjK | 5:c39b22fa0c60 | 610 | * @return this |
AjK | 5:c39b22fa0c60 | 611 | */ |
AjK | 5:c39b22fa0c60 | 612 | template<typename T> |
AjK | 6:40d38be4bb59 | 613 | void attach_err(T* tptr, void (T::*mptr)(void)) { |
AjK | 5:c39b22fa0c60 | 614 | if((mptr != NULL) && (tptr != NULL)) { |
AjK | 5:c39b22fa0c60 | 615 | isrIntErrStat.attach(tptr, mptr); |
AjK | 5:c39b22fa0c60 | 616 | } |
AjK | 5:c39b22fa0c60 | 617 | } |
AjK | 5:c39b22fa0c60 | 618 | |
AjK | 5:c39b22fa0c60 | 619 | /** |
AjK | 6:40d38be4bb59 | 620 | * Get the Linked List index regsiter for the requested channel. |
AjK | 6:40d38be4bb59 | 621 | * |
AjK | 6:40d38be4bb59 | 622 | * @param channelNum The channel number. |
AjK | 6:40d38be4bb59 | 623 | * @return uint32_t The valie of the DMACCLLI register |
AjK | 6:40d38be4bb59 | 624 | */ |
AjK | 6:40d38be4bb59 | 625 | uint32_t lli(int channelNum) { |
AjK | 6:40d38be4bb59 | 626 | LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( channelNum & 0x7 ); |
AjK | 6:40d38be4bb59 | 627 | return pChannel->DMACCLLI; |
AjK | 6:40d38be4bb59 | 628 | } |
AjK | 6:40d38be4bb59 | 629 | |
AjK | 6:40d38be4bb59 | 630 | /** |
AjK | 0:c409efd8df78 | 631 | * The MODDMA controllers error interrupt callback. |
AjK | 0:c409efd8df78 | 632 | */ |
AjK | 0:c409efd8df78 | 633 | FunctionPointer isrIntErrStat; |
AjK | 0:c409efd8df78 | 634 | |
AjK | 0:c409efd8df78 | 635 | protected: |
AjK | 6:40d38be4bb59 | 636 | |
AjK | 0:c409efd8df78 | 637 | // Data LUTs. |
AjK | 0:c409efd8df78 | 638 | uint32_t LUTPerAddr(int n); |
AjK | 0:c409efd8df78 | 639 | uint8_t LUTPerBurst(int n); |
AjK | 0:c409efd8df78 | 640 | uint8_t LUTPerWid(int n); |
AjK | 0:c409efd8df78 | 641 | uint32_t Channel_p(int channel); |
AjK | 0:c409efd8df78 | 642 | |
AjK | 0:c409efd8df78 | 643 | CHANNELS IrqProcessingChannel; |
AjK | 0:c409efd8df78 | 644 | |
AjK | 0:c409efd8df78 | 645 | IrqType_t IrqType; |
AjK | 0:c409efd8df78 | 646 | }; |
AjK | 0:c409efd8df78 | 647 | |
AjK | 0:c409efd8df78 | 648 | }; // namespace AjK ends. |
AjK | 0:c409efd8df78 | 649 | |
AjK | 0:c409efd8df78 | 650 | using namespace AjK; |
AjK | 0:c409efd8df78 | 651 | |
AjK | 0:c409efd8df78 | 652 | #endif |