Andrew Boyson / oldheating

Central Heating controller using the real time clock, PHY module for internet, 1-wire interface for temperature sensors, a system log and a configuration file

Dependencies:   net 1-wire lpc1768 crypto clock web fram log

/media/uploads/andrewboyson/heating.sch

/media/uploads/andrewboyson/heating.brd

/media/uploads/andrewboyson/eagle.epf

fram/spi.c@105:1899f7ed17ec, 2021-02-23 (annotated)

Committer:
andrewboyson
Date:
Tue Feb 23 20:35:07 2021 +0000
Revision:
105:1899f7ed17ec
Parent:
13:2ca12dd42e91 
Added ability to set the minimum flow rate and removed the correction to delta T relative to speed. Adding the round circuit time and linked to speed. Next task is to linearize the flow.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andrewboyson 5:82197a6997fd 1 #include "gpio.h"
andrewboyson 0:3c04f4b47041 2 #include "log.h"
andrewboyson 0:3c04f4b47041 3
andrewboyson 5:82197a6997fd 4 #define CS_DIR FIO0DIR(6)
andrewboyson 5:82197a6997fd 5 #define CS_SET FIO0SET(6)
andrewboyson 5:82197a6997fd 6 #define CS_CLR FIO0CLR(6)
andrewboyson 5:82197a6997fd 7
andrewboyson 5:82197a6997fd 8 //SSP1
andrewboyson 5:82197a6997fd 9 #define CR0 (*((volatile unsigned *) 0x40030000))
andrewboyson 5:82197a6997fd 10 #define CR1 (*((volatile unsigned *) 0x40030004))
andrewboyson 5:82197a6997fd 11 #define DR (*((volatile unsigned *) 0x40030008))
andrewboyson 5:82197a6997fd 12 #define SR (*((volatile unsigned *) 0x4003000C))
andrewboyson 5:82197a6997fd 13 #define CPSR (*((volatile unsigned *) 0x40030010))
andrewboyson 0:3c04f4b47041 14
andrewboyson 0:3c04f4b47041 15 void SpiInit(void)
andrewboyson 5:82197a6997fd 16 {
andrewboyson 0:3c04f4b47041 17 //Configure
andrewboyson 5:82197a6997fd 18 CR0 |= 7 << 0; //3:0 8 bit transfer
andrewboyson 5:82197a6997fd 19 CR0 |= 0 << 4; //5:4 SPI
andrewboyson 5:82197a6997fd 20 CR0 |= 0 << 6; //7:6 Mode 0
andrewboyson 5:82197a6997fd 21 CR0 |= 0 << 8; //divide by 1
andrewboyson 0:3c04f4b47041 22
andrewboyson 0:3c04f4b47041 23 //Set prescaler bps = PCLK / PS ==> PS = PCLK / bps ==> PS = 96/16 = 6
andrewboyson 5:82197a6997fd 24 CPSR = 6; //Bit 0 must be 0. 6 ==> 16 bps which is within the 20MHz allowed by the FRAM
andrewboyson 0:3c04f4b47041 25
andrewboyson 0:3c04f4b47041 26 //Select the function of the ssel pin: P0.6
andrewboyson 5:82197a6997fd 27 CS_SET; //Deselect the output == CS = 1
andrewboyson 5:82197a6997fd 28 CS_DIR = 1; //Set the direction to 1 == output
andrewboyson 0:3c04f4b47041 29
andrewboyson 0:3c04f4b47041 30 //Enable operation
andrewboyson 5:82197a6997fd 31 CR1 |= 2; //Enable the SSP controller
andrewboyson 0:3c04f4b47041 32 }
andrewboyson 0:3c04f4b47041 33 void SpiChipSelect(int value)
andrewboyson 0:3c04f4b47041 34 {
andrewboyson 5:82197a6997fd 35 if (value) CS_SET;
andrewboyson 5:82197a6997fd 36 else CS_CLR;
andrewboyson 0:3c04f4b47041 37 }
andrewboyson 0:3c04f4b47041 38 void SpiWrite(char byte)
andrewboyson 0:3c04f4b47041 39 {
andrewboyson 5:82197a6997fd 40 DR = byte; //This loads the next frame in the TX FIFO
andrewboyson 0:3c04f4b47041 41 }
andrewboyson 0:3c04f4b47041 42 int SpiBusy(void)
andrewboyson 0:3c04f4b47041 43 {
andrewboyson 5:82197a6997fd 44 return SR & 0x10; //bit 4 is BSY. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
andrewboyson 0:3c04f4b47041 45 }
andrewboyson 0:3c04f4b47041 46 char SpiRead(void)
andrewboyson 0:3c04f4b47041 47 {
andrewboyson 5:82197a6997fd 48 return DR & 0xFF; //This reads the oldest frame in the RX FIFO
andrewboyson 0:3c04f4b47041 49 }
andrewboyson 0:3c04f4b47041 50 char SpiTransfer(char byte)
andrewboyson 0:3c04f4b47041 51 {
andrewboyson 0:3c04f4b47041 52 SpiWrite(byte);
andrewboyson 0:3c04f4b47041 53 while(SpiBusy()) /*spin until not busy, at 16 bits per us or 2 bytes per us should be only 48 operations*/;
andrewboyson 0:3c04f4b47041 54 return SpiRead();
andrewboyson 0:3c04f4b47041 55 }