Akifumi Takahashi / SwArr16MOSFET

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Dependents:   Interference_Simple

PMRC16ch.cpp@20:26972de3cf90, 2018-06-28 (annotated)

Committer:
aktk
Date:
Thu Jun 28 08:49:54 2018 +0000
Revision:
20:26972de3cf90
Parent:
18:049283936e3f
Child:
21:fa067e2a30f2
modified type of some methods: char -> void, type of getState(): char -> uint32_t

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aktk 15:56703876e914 1 #include "PMRC16ch.h"
aktk 15:56703876e914 2 // A constractor whose arguments have all default value
aktk 15:56703876e914 3 // is a default constractor.
aktk 15:56703876e914 4 PMRC16ch::PMRC16ch():
aktk 15:56703876e914 5 m_num_ch(16),
aktk 15:56703876e914 6 m_SCK(DigitalOut(p11)),
aktk 15:56703876e914 7 m_CLR(DigitalOut(p12)),
aktk 15:56703876e914 8 m_RCK(DigitalOut(p13)),
aktk 15:56703876e914 9 m_SER(DigitalOut(p14)),
aktk 15:56703876e914 10 m_OUT(DigitalIn(p10))
aktk 15:56703876e914 11 {
aktk 15:56703876e914 12 init();
aktk 15:56703876e914 13 }
aktk 15:56703876e914 14
aktk 15:56703876e914 15 PMRC16ch::PMRC16ch(
aktk 15:56703876e914 16 uint8_t arg_num_ch,
aktk 15:56703876e914 17 PinName arg_SCK,
aktk 15:56703876e914 18 PinName arg_CLR,
aktk 15:56703876e914 19 PinName arg_RCK,
aktk 15:56703876e914 20 PinName arg_SER,
aktk 15:56703876e914 21 PinName arg_OUT
aktk 15:56703876e914 22 ):
aktk 15:56703876e914 23 m_num_ch(arg_num_ch),
aktk 15:56703876e914 24 m_SCK(DigitalOut(arg_SCK)),
aktk 15:56703876e914 25 m_CLR(DigitalOut(arg_CLR)),
aktk 15:56703876e914 26 m_RCK(DigitalOut(arg_RCK)),
aktk 15:56703876e914 27 m_SER(DigitalOut(arg_SER)),
aktk 15:56703876e914 28 m_OUT(DigitalIn(arg_OUT))
aktk 15:56703876e914 29 {
aktk 15:56703876e914 30 init();
aktk 15:56703876e914 31 }
aktk 15:56703876e914 32
aktk 15:56703876e914 33 void PMRC16ch::init()
aktk 15:56703876e914 34 {
aktk 15:56703876e914 35 m_CLR = 1;
aktk 15:56703876e914 36 m_SCK = m_RCK = 0;
aktk 18:049283936e3f 37 //reset shiftresister
aktk 18:049283936e3f 38 m_CLR = 0;
aktk 18:049283936e3f 39 update();
aktk 18:049283936e3f 40 //enable insertion data to SR
aktk 18:049283936e3f 41 m_CLR = 1;
aktk 18:049283936e3f 42 m_PMRC_state = ALLHiZ;
aktk 15:56703876e914 43 m_PMRC_POL = Cathodic;
aktk 15:56703876e914 44 }
aktk 15:56703876e914 45
aktk 20:26972de3cf90 46 void PMRC16ch::allGround()
aktk 15:56703876e914 47 {
aktk 17:08a68860396b 48 if (m_PMRC_state == ALLGROUND) return 1;
aktk 15:56703876e914 49 sweep();
aktk 15:56703876e914 50 upload();
aktk 15:56703876e914 51 }
aktk 15:56703876e914 52
aktk 20:26972de3cf90 53 void PMRC16ch::allHiZ()
aktk 15:56703876e914 54 {
aktk 20:26972de3cf90 55 //reset shiftresister
aktk 20:26972de3cf90 56 m_CLR = 0;
aktk 20:26972de3cf90 57 update();
aktk 20:26972de3cf90 58 //enable insertion data to SR
aktk 20:26972de3cf90 59 m_CLR = 1;
aktk 20:26972de3cf90 60 upload();
aktk 20:26972de3cf90 61 }
aktk 15:56703876e914 62
aktk 20:26972de3cf90 63 void PMRC16ch::setCh(char arg_state, Polarity arg_POL)
aktk 15:56703876e914 64 {
aktk 16:e81a30a098dd 65 m_PMRC_POL = arg_POL;
aktk 15:56703876e914 66 int8_t num_of_shift = arg_state - static_cast<int8_t>(m_PMRC_state);
aktk 15:56703876e914 67
aktk 15:56703876e914 68 if( num_of_shift < 0 )
aktk 15:56703876e914 69 sweep();
aktk 15:56703876e914 70
aktk 17:08a68860396b 71 if( m_PMRC_state == ALLGROUND ) {
aktk 15:56703876e914 72 setStimbits();
aktk 15:56703876e914 73 num_of_shift = static_cast<char>(arg_state - 1);
aktk 15:56703876e914 74 }
aktk 15:56703876e914 75 shiftby(num_of_shift);
aktk 15:56703876e914 76 upload();
aktk 15:56703876e914 77
aktk 15:56703876e914 78 return static_cast<char>(m_PMRC_state = static_cast<State>(arg_state));
aktk 15:56703876e914 79 }
aktk 15:56703876e914 80
aktk 15:56703876e914 81 void PMRC16ch::setBits(const uint32_t bits, int num_of_bits, Polarity arg_POL)
aktk 15:56703876e914 82 {
aktk 16:e81a30a098dd 83 m_PMRC_POL = arg_POL;
aktk 15:56703876e914 84 //reset shiftresister
aktk 15:56703876e914 85 m_CLR = 0;
aktk 15:56703876e914 86 update();
aktk 15:56703876e914 87 //enable insertion data to SR
aktk 15:56703876e914 88 m_CLR = 1;
aktk 15:56703876e914 89 for(int i = 0; i < num_of_bits; i++){
aktk 16:e81a30a098dd 90 m_SER = (((bits >> i) & 0b0001) ^ m_PMRC_POL); //XOR Polarity
aktk 15:56703876e914 91 update();
aktk 15:56703876e914 92 }
aktk 15:56703876e914 93 upload();
aktk 15:56703876e914 94 }
aktk 15:56703876e914 95
aktk 15:56703876e914 96 void PMRC16ch::sweep()
aktk 15:56703876e914 97 {
aktk 15:56703876e914 98 int num_of_shift = (16 + 1) - static_cast<int>(m_PMRC_state);
aktk 15:56703876e914 99
aktk 15:56703876e914 100 shiftby(num_of_shift);
aktk 17:08a68860396b 101 m_PMRC_state = ALLGROUND;
aktk 15:56703876e914 102 }
aktk 15:56703876e914 103
aktk 15:56703876e914 104 void PMRC16ch::shiftby(int arg_num)
aktk 15:56703876e914 105 {
aktk 15:56703876e914 106 for(int i = 0; i < arg_num; i++) {
aktk 16:e81a30a098dd 107 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 108 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 109 update();
aktk 16:e81a30a098dd 110 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 111 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 112 update();
aktk 15:56703876e914 113 }
aktk 15:56703876e914 114 m_PMRC_state = static_cast<State>((static_cast<int>(m_PMRC_state) + arg_num) % (16 + 1));
aktk 15:56703876e914 115 }
aktk 15:56703876e914 116
aktk 15:56703876e914 117 void PMRC16ch::setStimbits()
aktk 15:56703876e914 118 {
aktk 16:e81a30a098dd 119 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 120 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 121 update();
aktk 16:e81a30a098dd 122 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 123 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 124 update();
aktk 15:56703876e914 125 m_PMRC_state = CH1;
aktk 15:56703876e914 126 }
aktk 15:56703876e914 127 void PMRC16ch::update()
aktk 15:56703876e914 128 {
aktk 15:56703876e914 129 //Shift-resister Clock update
aktk 15:56703876e914 130 m_SCK = 1;
aktk 15:56703876e914 131 m_SCK = 1;
aktk 15:56703876e914 132 m_SCK = 0;
aktk 15:56703876e914 133 m_SCK = 0;
aktk 15:56703876e914 134 }
aktk 15:56703876e914 135 void PMRC16ch::upload()
aktk 15:56703876e914 136 {
aktk 15:56703876e914 137 //FF Clock Update
aktk 15:56703876e914 138 m_RCK = 1;
aktk 15:56703876e914 139 m_RCK = 1;
aktk 15:56703876e914 140 m_RCK = 0;
aktk 15:56703876e914 141 m_RCK = 0;
aktk 15:56703876e914 142 }