Akifumi Takahashi / PMRC16ch

Library to use my Photo MOS Relays Circuit having 16 or less channels.

Fork of PMRC4ch by Akifumi Takahashi

PMRC16ch.cpp@44:20a890fe5f83, 2019-10-29 (annotated)

Committer:
aktk
Date:
Tue Oct 29 02:43:14 2019 +0000
Revision:
44:20a890fe5f83
Parent:
43:03e875137433
Child:
47:a097e670a983
Modified setTwin(..) to return when called to set to the same channel.;; Modified some summations to logical summations;; Modified for-condition in setBits(..) so that the lib can be used when not 16 channels;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aktk 21:fa067e2a30f2 1
aktk 15:56703876e914 2 #include "PMRC16ch.h"
aktk 21:fa067e2a30f2 3 const uint32_t PMRC16ch::m_statearray[] = {
aktk 21:fa067e2a30f2 4 ALLGROUND, CH1, CH2, CH3, CH4, CH5, CH6, CH7, CH8, CH9,
aktk 21:fa067e2a30f2 5 CH10, CH11, CH12, CH13, CH14, CH15, CH16, ALLHiZ
aktk 21:fa067e2a30f2 6 };
aktk 15:56703876e914 7 // A constractor whose arguments have all default value
aktk 15:56703876e914 8 // is a default constractor.
aktk 15:56703876e914 9 PMRC16ch::PMRC16ch():
aktk 15:56703876e914 10 m_num_ch(16),
aktk 15:56703876e914 11 m_SCK(DigitalOut(p11)),
aktk 15:56703876e914 12 m_CLR(DigitalOut(p12)),
aktk 15:56703876e914 13 m_RCK(DigitalOut(p13)),
aktk 15:56703876e914 14 m_SER(DigitalOut(p14)),
aktk 15:56703876e914 15 m_OUT(DigitalIn(p10))
aktk 15:56703876e914 16 {
aktk 15:56703876e914 17 init();
aktk 15:56703876e914 18 }
aktk 21:fa067e2a30f2 19 PMRC16ch::PMRC16ch(
aktk 21:fa067e2a30f2 20 uint8_t arg_num_ch
aktk 21:fa067e2a30f2 21 ):
aktk 21:fa067e2a30f2 22 m_num_ch(arg_num_ch),
aktk 21:fa067e2a30f2 23 m_SCK(DigitalOut(p11)),
aktk 21:fa067e2a30f2 24 m_CLR(DigitalOut(p12)),
aktk 21:fa067e2a30f2 25 m_RCK(DigitalOut(p13)),
aktk 21:fa067e2a30f2 26 m_SER(DigitalOut(p14)),
aktk 21:fa067e2a30f2 27 m_OUT(DigitalIn(p10))
aktk 21:fa067e2a30f2 28 {
aktk 21:fa067e2a30f2 29 init();
aktk 21:fa067e2a30f2 30 }
aktk 21:fa067e2a30f2 31
aktk 15:56703876e914 32
aktk 15:56703876e914 33 PMRC16ch::PMRC16ch(
aktk 15:56703876e914 34 uint8_t arg_num_ch,
aktk 15:56703876e914 35 PinName arg_SCK,
aktk 15:56703876e914 36 PinName arg_CLR,
aktk 15:56703876e914 37 PinName arg_RCK,
aktk 15:56703876e914 38 PinName arg_SER,
aktk 15:56703876e914 39 PinName arg_OUT
aktk 15:56703876e914 40 ):
aktk 15:56703876e914 41 m_num_ch(arg_num_ch),
aktk 15:56703876e914 42 m_SCK(DigitalOut(arg_SCK)),
aktk 15:56703876e914 43 m_CLR(DigitalOut(arg_CLR)),
aktk 15:56703876e914 44 m_RCK(DigitalOut(arg_RCK)),
aktk 15:56703876e914 45 m_SER(DigitalOut(arg_SER)),
aktk 15:56703876e914 46 m_OUT(DigitalIn(arg_OUT))
aktk 15:56703876e914 47 {
aktk 15:56703876e914 48 init();
aktk 15:56703876e914 49 }
aktk 42:a827fe9166b5 50 // ----------------------------------------------------------------------------
aktk 15:56703876e914 51 void PMRC16ch::init()
aktk 15:56703876e914 52 {
aktk 15:56703876e914 53 m_CLR = 1;
aktk 15:56703876e914 54 m_SCK = m_RCK = 0;
aktk 21:fa067e2a30f2 55 allHiZ();
aktk 21:fa067e2a30f2 56 m_PMRC_mode = TWIN_ELECTRODES;
aktk 15:56703876e914 57 m_PMRC_POL = Cathodic;
aktk 15:56703876e914 58 }
aktk 15:56703876e914 59
aktk 20:26972de3cf90 60 void PMRC16ch::allGround()
aktk 15:56703876e914 61 {
aktk 21:fa067e2a30f2 62 if (m_PMRC_state == ALLGROUND) return;
aktk 15:56703876e914 63 sweep();
aktk 15:56703876e914 64 upload();
aktk 21:fa067e2a30f2 65 m_PMRC_state = ALLGROUND;
aktk 21:fa067e2a30f2 66 m_pos_stim = 0;
aktk 15:56703876e914 67 }
aktk 15:56703876e914 68
aktk 20:26972de3cf90 69 void PMRC16ch::allHiZ()
aktk 15:56703876e914 70 {
aktk 20:26972de3cf90 71 //reset shiftresister
aktk 20:26972de3cf90 72 m_CLR = 0;
aktk 20:26972de3cf90 73 update();
aktk 20:26972de3cf90 74 //enable insertion data to SR
aktk 20:26972de3cf90 75 m_CLR = 1;
aktk 20:26972de3cf90 76 upload();
aktk 21:fa067e2a30f2 77 m_PMRC_state = ALLHiZ;
aktk 21:fa067e2a30f2 78 m_pos_stim = 0;
aktk 21:fa067e2a30f2 79 }
aktk 42:a827fe9166b5 80 // ----------------------------------------------------------------------------
aktk 21:fa067e2a30f2 81 void PMRC16ch::setTwin(char arg_stim_ch, char arg_ref_ch)
aktk 21:fa067e2a30f2 82 {
aktk 44:20a890fe5f83 83 uint32_t l_state = m_PMRC_state;
aktk 44:20a890fe5f83 84 m_PMRC_state = m_statearray[arg_stim_ch] | (m_statearray[arg_ref_ch] >> 1);
aktk 44:20a890fe5f83 85 if(l_state == m_PMRC_state) return;
aktk 44:20a890fe5f83 86
aktk 21:fa067e2a30f2 87 m_PMRC_mode = TWIN_ELECTRODES;
aktk 21:fa067e2a30f2 88 setBits(m_PMRC_state);
aktk 21:fa067e2a30f2 89 upload();
aktk 21:fa067e2a30f2 90 m_pos_stim = arg_stim_ch;
aktk 20:26972de3cf90 91 }
aktk 15:56703876e914 92
aktk 42:a827fe9166b5 93 void PMRC16ch::setTrio(char arg_stim_ch, char arg_ref_ch1, char arg_ref_ch2)
aktk 42:a827fe9166b5 94 {
aktk 42:a827fe9166b5 95 m_PMRC_mode = TWIN_ELECTRODES;
aktk 42:a827fe9166b5 96 m_PMRC_state = m_statearray[arg_stim_ch]
aktk 44:20a890fe5f83 97 | (m_statearray[arg_ref_ch1] >> 1)
aktk 44:20a890fe5f83 98 | (m_statearray[arg_ref_ch2] >> 1);
aktk 42:a827fe9166b5 99 setBits(m_PMRC_state);
aktk 42:a827fe9166b5 100 upload();
aktk 42:a827fe9166b5 101 m_pos_stim = arg_stim_ch;
aktk 42:a827fe9166b5 102 }
aktk 42:a827fe9166b5 103
aktk 21:fa067e2a30f2 104 void PMRC16ch::setOvsO(char arg_ch)
aktk 15:56703876e914 105 {
aktk 21:fa067e2a30f2 106 int8_t num_of_shift;
aktk 15:56703876e914 107
aktk 21:fa067e2a30f2 108 num_of_shift = arg_ch - m_pos_stim;
aktk 21:fa067e2a30f2 109 // m_PMRC_mode == ONE_VS_THEOTHERS && m_pos_stim == 0
aktk 21:fa067e2a30f2 110 // => m_PMRC_state == ALLGROUND
aktk 21:fa067e2a30f2 111 if( num_of_shift < 0 || m_pos_stim == 0 || m_PMRC_mode != ONE_VS_THEOTHERS) {
aktk 15:56703876e914 112 sweep();
aktk 15:56703876e914 113 setStimbits();
aktk 21:fa067e2a30f2 114 num_of_shift = arg_ch - 1;
aktk 15:56703876e914 115 }
aktk 15:56703876e914 116 shiftby(num_of_shift);
aktk 21:fa067e2a30f2 117 m_PMRC_mode = ONE_VS_THEOTHERS;
aktk 44:20a890fe5f83 118 m_PMRC_state = ALLGROUND | m_statearray[arg_ch];
aktk 21:fa067e2a30f2 119
aktk 15:56703876e914 120 upload();
aktk 21:fa067e2a30f2 121 m_pos_stim = arg_ch;
aktk 15:56703876e914 122 }
aktk 15:56703876e914 123
aktk 42:a827fe9166b5 124 // ----------------------------------------------------------------------------
aktk 15:56703876e914 125
aktk 15:56703876e914 126 void PMRC16ch::sweep()
aktk 15:56703876e914 127 {
aktk 21:fa067e2a30f2 128 uint32_t num_shift;
aktk 15:56703876e914 129
aktk 21:fa067e2a30f2 130 if(m_PMRC_mode != ONE_VS_THEOTHERS || m_PMRC_state == ALLHiZ) {
aktk 21:fa067e2a30f2 131 num_shift = m_num_ch;
aktk 21:fa067e2a30f2 132 } else if(m_PMRC_mode == ONE_VS_THEOTHERS) {
aktk 21:fa067e2a30f2 133 num_shift = m_num_ch - (m_pos_stim - 1);
aktk 21:fa067e2a30f2 134 }
aktk 21:fa067e2a30f2 135 shiftby(num_shift);
aktk 15:56703876e914 136 }
aktk 15:56703876e914 137
aktk 15:56703876e914 138 void PMRC16ch::shiftby(int arg_num)
aktk 15:56703876e914 139 {
aktk 15:56703876e914 140 for(int i = 0; i < arg_num; i++) {
aktk 16:e81a30a098dd 141 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 142 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 143 update();
aktk 16:e81a30a098dd 144 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 145 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 146 update();
aktk 15:56703876e914 147 }
aktk 15:56703876e914 148 }
aktk 15:56703876e914 149
aktk 15:56703876e914 150 void PMRC16ch::setStimbits()
aktk 15:56703876e914 151 {
aktk 16:e81a30a098dd 152 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 153 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 154 update();
aktk 16:e81a30a098dd 155 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 156 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 157 update();
aktk 15:56703876e914 158 m_PMRC_state = CH1;
aktk 15:56703876e914 159 }
aktk 21:fa067e2a30f2 160
aktk 21:fa067e2a30f2 161 void PMRC16ch::setBits(const uint32_t arg_bits)
aktk 21:fa067e2a30f2 162 {
aktk 42:a827fe9166b5 163 /* arg_bits: 0b xx xx xx xx ... xx xx xx
aktk 42:a827fe9166b5 164 * ch1 <- ->ch[m_num_ch]
aktk 42:a827fe9166b5 165 */
aktk 42:a827fe9166b5 166
aktk 21:fa067e2a30f2 167 uint8_t tmp_bit[2];
aktk 21:fa067e2a30f2 168 //reset shiftresister
aktk 21:fa067e2a30f2 169 m_CLR = 0;
aktk 21:fa067e2a30f2 170 update();
aktk 21:fa067e2a30f2 171 //enable insertion data to SR
aktk 21:fa067e2a30f2 172 m_CLR = 1;
aktk 44:20a890fe5f83 173 for(int i = 16 - m_num_ch; i < 16; i++) {
aktk 21:fa067e2a30f2 174 tmp_bit[0] = 0b01 & (arg_bits >> (2 * i));
aktk 21:fa067e2a30f2 175 tmp_bit[1] = 0b01 & (arg_bits >> (2 * i + 1));
aktk 21:fa067e2a30f2 176 // if the chan. is not HiZ meaning Hi or Lw
aktk 44:20a890fe5f83 177 if(tmp_bit[0] | tmp_bit[1] == 0b01) {
aktk 21:fa067e2a30f2 178 m_SER = (tmp_bit[0] ^ m_PMRC_POL); //XOR Polarity
aktk 21:fa067e2a30f2 179 update();
aktk 21:fa067e2a30f2 180 m_SER = (tmp_bit[1] ^ m_PMRC_POL); //XOR Polarity
aktk 21:fa067e2a30f2 181 update();
aktk 21:fa067e2a30f2 182 } else {
aktk 21:fa067e2a30f2 183 m_SER = (tmp_bit[0]);
aktk 21:fa067e2a30f2 184 update();
aktk 21:fa067e2a30f2 185 m_SER = (tmp_bit[1]);
aktk 21:fa067e2a30f2 186 update();
aktk 21:fa067e2a30f2 187 }
aktk 21:fa067e2a30f2 188 }
aktk 21:fa067e2a30f2 189 }
aktk 42:a827fe9166b5 190 // ----------------------------------------------------------------------------
aktk 15:56703876e914 191 void PMRC16ch::update()
aktk 15:56703876e914 192 {
aktk 15:56703876e914 193 //Shift-resister Clock update
aktk 15:56703876e914 194 m_SCK = 1;
aktk 15:56703876e914 195 m_SCK = 1;
aktk 15:56703876e914 196 m_SCK = 0;
aktk 15:56703876e914 197 m_SCK = 0;
aktk 15:56703876e914 198 }
aktk 15:56703876e914 199 void PMRC16ch::upload()
aktk 15:56703876e914 200 {
aktk 15:56703876e914 201 //FF Clock Update
aktk 15:56703876e914 202 m_RCK = 1;
aktk 15:56703876e914 203 m_RCK = 1;
aktk 15:56703876e914 204 m_RCK = 0;
aktk 15:56703876e914 205 m_RCK = 0;
aktk 15:56703876e914 206 }