Zbigniew Druzbacki / Mbed 2 deprecated SPI_Slave

SPI slave program to enable communication between the FPGA and the STM32L432 board.

Dependencies:   mbed

DMA_SPI.cpp@12:3e7da86a49ff, 2019-03-25 (annotated)

Committer:
Zbyszek
Date:
Mon Mar 25 02:15:44 2019 +0000
Revision:
12:3e7da86a49ff
Parent:
11:366f1186c121
Child:
13:c7e8e277f884
Publishing the code so far

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zbyszek 8:e87027349167 1 #include "mbed.h"
Zbyszek 8:e87027349167 2 #include "DMA_SPI.h"
Zbyszek 8:e87027349167 3
Zbyszek 9:9ed9dffd602a 4 int16_t data_to_transmit[12];
Zbyszek 9:9ed9dffd602a 5 int16_t received_data[12];
Zbyszek 11:366f1186c121 6
Zbyszek 11:366f1186c121 7
Zbyszek 11:366f1186c121 8 int16_t SampleFIFO[10][12];
Zbyszek 11:366f1186c121 9 extern int pointerOS = 0;
Zbyszek 11:366f1186c121 10 extern int pointerNS = 0;
Zbyszek 11:366f1186c121 11 extern int pointerFS = 0;
Zbyszek 11:366f1186c121 12 extern char newDataFlag = 0;
Zbyszek 11:366f1186c121 13
Zbyszek 9:9ed9dffd602a 14
Zbyszek 9:9ed9dffd602a 15 void SPI_DMA_init() {
Zbyszek 11:366f1186c121 16
Zbyszek 9:9ed9dffd602a 17
Zbyszek 9:9ed9dffd602a 18 //Deinitialise
Zbyszek 9:9ed9dffd602a 19 SPI_DMA_SLAVE_deinit();
Zbyszek 9:9ed9dffd602a 20 deinitDMA();
Zbyszek 9:9ed9dffd602a 21
Zbyszek 9:9ed9dffd602a 22 //Initialise
Zbyszek 9:9ed9dffd602a 23 initDMA();
Zbyszek 9:9ed9dffd602a 24 SPI_DMA_SLAVE_init();
Zbyszek 9:9ed9dffd602a 25
Zbyszek 9:9ed9dffd602a 26 //Start DMA communication
Zbyszek 9:9ed9dffd602a 27 startCommunication();
Zbyszek 9:9ed9dffd602a 28 }
Zbyszek 9:9ed9dffd602a 29
Zbyszek 9:9ed9dffd602a 30 /* Starting DMA communication according to STM32L432 Reference Manual p1317-p1318*/
Zbyszek 9:9ed9dffd602a 31 void startCommunication() {
Zbyszek 9:9ed9dffd602a 32
Zbyszek 9:9ed9dffd602a 33 SET_SPI1_CR2_RXDMAEN_BIT(); //Enable RX DMA buffer
Zbyszek 9:9ed9dffd602a 34 DMA1_CH3_ENABLE(); //Enable DMA channel 3
Zbyszek 9:9ed9dffd602a 35 DMA1_CH2_ENABLE(); //Enable DMA channel 2
Zbyszek 9:9ed9dffd602a 36 SET_SPI1_CR2_TXDMAEN_BIT(); //Enable TX DMA buffer
Zbyszek 9:9ed9dffd602a 37 SPI1_ENABLE(); //SPI module enabled
Zbyszek 9:9ed9dffd602a 38 }
Zbyszek 9:9ed9dffd602a 39
Zbyszek 9:9ed9dffd602a 40
Zbyszek 9:9ed9dffd602a 41 //====================================================DEINITIALISE=========================================================================
Zbyszek 9:9ed9dffd602a 42 void SPI_DMA_SLAVE_deinit() {
Zbyszek 9:9ed9dffd602a 43 //Disable the clocks
Zbyszek 9:9ed9dffd602a 44 //RCC->AHB2ENR &= ~(RCC_AHB2ENR_GPIOAEN);
Zbyszek 9:9ed9dffd602a 45 //RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN);
Zbyszek 9:9ed9dffd602a 46 //Clear pin settings
Zbyszek 11:366f1186c121 47
Zbyszek 9:9ed9dffd602a 48
Zbyszek 9:9ed9dffd602a 49 GPIOA->MODER&=~( //clear GPIOB
Zbyszek 9:9ed9dffd602a 50 (3u<<(2*SCK_slave))
Zbyszek 9:9ed9dffd602a 51 |(3u<<(2*MISO_slave))
Zbyszek 9:9ed9dffd602a 52 |(3u<<(2*MOSI_slave))
Zbyszek 11:366f1186c121 53 |(3u<<(2*4))
Zbyszek 9:9ed9dffd602a 54 );
Zbyszek 11:366f1186c121 55
Zbyszek 11:366f1186c121 56
Zbyszek 11:366f1186c121 57 GPIOB->MODER &= ~(2u<<0);
Zbyszek 11:366f1186c121 58
Zbyszek 9:9ed9dffd602a 59 GPIOA->AFR[0]&=~( //clear alternate function selector bits
Zbyszek 9:9ed9dffd602a 60 (0x0f<<(4*SCK_slave))
Zbyszek 9:9ed9dffd602a 61 |(0x0f<<(4*MISO_slave))
Zbyszek 9:9ed9dffd602a 62 |(15u<<(4*MOSI_slave))
Zbyszek 11:366f1186c121 63 //|(15u<<(2*4)) //Thhis is why the UART was not working
Zbyszek 9:9ed9dffd602a 64 );
Zbyszek 11:366f1186c121 65
Zbyszek 11:366f1186c121 66 GPIOB->AFR[0] &= ~(15u<<(4*0));
Zbyszek 9:9ed9dffd602a 67
Zbyszek 9:9ed9dffd602a 68 //Clear SPI bits
Zbyszek 9:9ed9dffd602a 69 SPI1_DISABLE();
Zbyszek 9:9ed9dffd602a 70 CLEAR_SPI1_CR1_MSTR_BIT();
Zbyszek 9:9ed9dffd602a 71 CLEAR_SPI1_CR1_BR_BITS();
Zbyszek 9:9ed9dffd602a 72 CLEAR_SPI1_CR1_SSM_BIT();
Zbyszek 9:9ed9dffd602a 73 CLEAR_SPI1_CR1_SSI_BIT();
Zbyszek 9:9ed9dffd602a 74 CLEAR_SPI1_CR1_CPOL_BIT();
Zbyszek 9:9ed9dffd602a 75 CLEAR_SPI1_CR1_CPHA_BIT();
Zbyszek 9:9ed9dffd602a 76
Zbyszek 9:9ed9dffd602a 77
Zbyszek 9:9ed9dffd602a 78 CLEAR_SPI1_CR2_DS_BITS();
Zbyszek 9:9ed9dffd602a 79 CLEAR_SPI1_CR2_RXDMAEN_BIT();
Zbyszek 9:9ed9dffd602a 80 CLEAR_SPI1_CR2_TXDMAEN_BIT();
Zbyszek 9:9ed9dffd602a 81 CLEAR_SPI1_CR2_RXEIE_BIT();
Zbyszek 9:9ed9dffd602a 82 CLEAR_SPI1_CR2_TXEIE_BIT();
Zbyszek 9:9ed9dffd602a 83
Zbyszek 9:9ed9dffd602a 84 CLEAR_SPI1_CR1_CRC_BIT();
Zbyszek 9:9ed9dffd602a 85
Zbyszek 9:9ed9dffd602a 86 RCC->APB2RSTR |= RCC_APB2RSTR_SPI1RST;
Zbyszek 9:9ed9dffd602a 87 RCC->APB2RSTR &= ~RCC_APB2RSTR_SPI1RST;
Zbyszek 9:9ed9dffd602a 88 }
Zbyszek 9:9ed9dffd602a 89
Zbyszek 9:9ed9dffd602a 90 void deinitDMA() {
Zbyszek 9:9ed9dffd602a 91 //RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN); //Disable the DMA1 clock
Zbyszek 9:9ed9dffd602a 92 RCC->AHB1RSTR |= RCC_AHB1RSTR_DMA1RST;
Zbyszek 9:9ed9dffd602a 93 RCC->AHB1RSTR &= ~RCC_AHB1RSTR_DMA1RST;
Zbyszek 9:9ed9dffd602a 94
Zbyszek 9:9ed9dffd602a 95 //Disable channels
Zbyszek 9:9ed9dffd602a 96 DMA1_CH2_DISABLE();
Zbyszek 9:9ed9dffd602a 97 DMA1_CH3_DISABLE();
Zbyszek 9:9ed9dffd602a 98
Zbyszek 9:9ed9dffd602a 99 CLEAR_DMA1_SPI1RX_CSELR_BITS(); //deselect SPI1_Rx on DMA1 Channel 2
Zbyszek 9:9ed9dffd602a 100 CLEAR_DMA1_SPI1TX_CSELR_BITS(); //deselect SPI1_Tx on DMA1 Channel 3
Zbyszek 9:9ed9dffd602a 101
Zbyszek 9:9ed9dffd602a 102
Zbyszek 9:9ed9dffd602a 103 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 104 //Clear configuration bits
Zbyszek 9:9ed9dffd602a 105 CLEAR_DMA1_CH2_CCR_DIR_BIT();
Zbyszek 9:9ed9dffd602a 106 CLEAR_DMA1_CH2_CCR_PSIZE_BITS();
Zbyszek 9:9ed9dffd602a 107 CLEAR_DMA1_CH2_CCR_MSIZE_BITS();
Zbyszek 9:9ed9dffd602a 108 CLEAR_DMA1_CH2_CCR_MINC_BIT();
Zbyszek 9:9ed9dffd602a 109 CLEAR_DMA1_CH2_CCR_PINC_BIT();
Zbyszek 9:9ed9dffd602a 110 CLEAR_DMA1_CH2_CCR_TCIE_BIT();
Zbyszek 9:9ed9dffd602a 111 CLEAR_DMA1_CH2_CCR_CIRC_BIT();
Zbyszek 9:9ed9dffd602a 112 CLEAR_DMA1_CH2_CCR_MEM2MEM_BIT();
Zbyszek 9:9ed9dffd602a 113 CLEAR_DMA1_CH2_CCR_PL_BITS();
Zbyszek 9:9ed9dffd602a 114 CLEAR_DMA1_CH2_CCR_TEIE_BIT();
Zbyszek 9:9ed9dffd602a 115
Zbyszek 9:9ed9dffd602a 116 CLEAR_DMA1_CH2_CNDTR_BITS();
Zbyszek 9:9ed9dffd602a 117 CLEAR_DMA1_CH2_CPAR_BITS();
Zbyszek 9:9ed9dffd602a 118 CLEAR_DMA1_CH2_CMAR_BITS();
Zbyszek 9:9ed9dffd602a 119 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 120
Zbyszek 9:9ed9dffd602a 121 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 9:9ed9dffd602a 122 //Clear configuration bits
Zbyszek 9:9ed9dffd602a 123 CLEAR_DMA1_CH3_CCR_DIR_BIT();
Zbyszek 9:9ed9dffd602a 124 CLEAR_DMA1_CH3_CCR_PSIZE_BITS();
Zbyszek 9:9ed9dffd602a 125 CLEAR_DMA1_CH3_CCR_MSIZE_BITS();
Zbyszek 9:9ed9dffd602a 126 CLEAR_DMA1_CH3_CCR_MINC_BIT();
Zbyszek 9:9ed9dffd602a 127 CLEAR_DMA1_CH3_CCR_PINC_BIT();
Zbyszek 9:9ed9dffd602a 128 CLEAR_DMA1_CH3_CCR_TCIE_BIT();
Zbyszek 9:9ed9dffd602a 129 CLEAR_DMA1_CH3_CCR_CIRC_BIT();
Zbyszek 9:9ed9dffd602a 130 CLEAR_DMA1_CH3_CCR_MEM2MEM_BIT();
Zbyszek 9:9ed9dffd602a 131 CLEAR_DMA1_CH3_CCR_PL_BITS();
Zbyszek 9:9ed9dffd602a 132 CLEAR_DMA1_CH3_CCR_TEIE_BIT();
Zbyszek 9:9ed9dffd602a 133
Zbyszek 9:9ed9dffd602a 134 CLEAR_DMA1_CH3_CNDTR_BITS();
Zbyszek 9:9ed9dffd602a 135 CLEAR_DMA1_CH3_CPAR_BITS();
Zbyszek 9:9ed9dffd602a 136 CLEAR_DMA1_CH3_CMAR_BITS();
Zbyszek 9:9ed9dffd602a 137
Zbyszek 9:9ed9dffd602a 138 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 9:9ed9dffd602a 139
Zbyszek 9:9ed9dffd602a 140 NVIC->ISER[0]&= ~(1u<<12); //Disable DMA1 channel 2 interrupt
Zbyszek 9:9ed9dffd602a 141 NVIC->ISER[0]&= ~(1u<<13); //Disable DMA1 channel 3 interrupt
Zbyszek 9:9ed9dffd602a 142
Zbyszek 9:9ed9dffd602a 143 }
Zbyszek 9:9ed9dffd602a 144 //====================================================DEINITIALISE=========================================================================
Zbyszek 9:9ed9dffd602a 145
Zbyszek 9:9ed9dffd602a 146
Zbyszek 9:9ed9dffd602a 147
Zbyszek 9:9ed9dffd602a 148 void SPI_DMA_SLAVE_init() {
Zbyszek 11:366f1186c121 149 RCC->AHB2ENR|= (RCC_AHB2ENR_GPIOAEN); //GPIO A clock enable
Zbyszek 11:366f1186c121 150 RCC->AHB2ENR |= (RCC_AHB2ENR_GPIOBEN);
Zbyszek 9:9ed9dffd602a 151 RCC->APB2ENR|=RCC_APB2ENR_SPI1EN; //Enable SPI1 Clock
Zbyszek 9:9ed9dffd602a 152
Zbyszek 9:9ed9dffd602a 153 //SET SCK, MISO, MOSI and CS pins
Zbyszek 9:9ed9dffd602a 154 GPIOA->MODER|=(
Zbyszek 9:9ed9dffd602a 155 (2u<<(2*SCK_slave))
Zbyszek 9:9ed9dffd602a 156 |(2u<<(2*MISO_slave))
Zbyszek 9:9ed9dffd602a 157 |(2u<<(2*MOSI_slave))
Zbyszek 11:366f1186c121 158 //|(2u<<(2*4))
Zbyszek 9:9ed9dffd602a 159 );
Zbyszek 11:366f1186c121 160 //Set PB_0 to alternate function
Zbyszek 11:366f1186c121 161 GPIOB->MODER |= (2u<<0);
Zbyszek 9:9ed9dffd602a 162
Zbyszek 9:9ed9dffd602a 163 //SET pins to function as SPI pins
Zbyszek 9:9ed9dffd602a 164 GPIOA->AFR[0]|=(
Zbyszek 9:9ed9dffd602a 165 (5u<<(4*SCK_slave))
Zbyszek 9:9ed9dffd602a 166 |(5u<<(4*MISO_slave))
Zbyszek 9:9ed9dffd602a 167 |(5u<<(4*MOSI_slave))
Zbyszek 11:366f1186c121 168 //|(5u<<(4*4))
Zbyszek 9:9ed9dffd602a 169 );
Zbyszek 11:366f1186c121 170
Zbyszek 11:366f1186c121 171 //Select SPI1_SSEL alternate function
Zbyszek 11:366f1186c121 172 GPIOB->AFR[0] |= (5u<<(4*0));
Zbyszek 9:9ed9dffd602a 173
Zbyszek 9:9ed9dffd602a 174 SET_SPI1_CR1_BR_BITS(); //baud rate bits set 1/16 giving 1MHz SCK frequency
Zbyszek 9:9ed9dffd602a 175 SET_SPI1_CR1_CPOL_BIT(); //CPOL = 1
Zbyszek 9:9ed9dffd602a 176 SET_SPI1_CR1_CPHA_BIT(); //CPHA = 1
Zbyszek 9:9ed9dffd602a 177
Zbyszek 9:9ed9dffd602a 178
Zbyszek 9:9ed9dffd602a 179 SET_SPI1_CR2_DS_BITS(); //Data Size = 16 bits
Zbyszek 11:366f1186c121 180 // SET_SPI1_CR2_RXDMAEN_BIT(); //Rx buffer DMA enable
Zbyszek 11:366f1186c121 181 // SET_SPI1_CR2_TXDMAEN_BIT(); //Tx buffer DMA enable
Zbyszek 9:9ed9dffd602a 182
Zbyszek 9:9ed9dffd602a 183
Zbyszek 9:9ed9dffd602a 184 }
Zbyszek 9:9ed9dffd602a 185
Zbyszek 9:9ed9dffd602a 186
Zbyszek 8:e87027349167 187
Zbyszek 8:e87027349167 188 void initDMA() {
Zbyszek 9:9ed9dffd602a 189 RCC->AHB1ENR|= (RCC_AHB1ENR_DMA1EN); //Enable the DMA1 clock
Zbyszek 9:9ed9dffd602a 190
Zbyszek 9:9ed9dffd602a 191 DMA1_CH2_DISABLE(); //Disable DMA channel 2
Zbyszek 9:9ed9dffd602a 192 DMA1_CH3_DISABLE(); //Disable DMA channel 3
Zbyszek 8:e87027349167 193
Zbyszek 9:9ed9dffd602a 194 SET_DMA1_SPI1RX_CSELR_BITS(); //Select SPI1_Rx on DMA1 Channel 2
Zbyszek 9:9ed9dffd602a 195 SET_DMA1_SPI1TX_CSELR_BITS(); //Select SPI1_Tx on DMA1 Channel 3
Zbyszek 8:e87027349167 196
Zbyszek 9:9ed9dffd602a 197 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 198 CLEAR_DMA1_CH2_CCR_DIR_BIT(); //Peripheral->Memory
Zbyszek 9:9ed9dffd602a 199 SET_DMA1_CH2_CCR_PSIZE_BITS(); //16 bits
Zbyszek 9:9ed9dffd602a 200 SET_DMA1_CH2_CCR_MSIZE_BITS(); //16 bits
Zbyszek 11:366f1186c121 201 SET_DMA1_CH2_CCR_MINC_BIT(); //Memory increment mode
Zbyszek 9:9ed9dffd602a 202 //SET_DMA1_CH2_CCR_PINC_BIT(); //Peripheral increment mode
Zbyszek 9:9ed9dffd602a 203 SET_DMA1_CH2_CCR_TCIE_BIT(); //Transfer complete interrupt enable
Zbyszek 11:366f1186c121 204 SET_DMA1_CH2_CCR_CIRC_BIT(); //Circular Buffer mode
Zbyszek 9:9ed9dffd602a 205 SET_DMA1_CH2_CCR_PL_BITS(); //Priority Level = Highest
Zbyszek 8:e87027349167 206
Zbyszek 9:9ed9dffd602a 207 DMA1_Channel2->CNDTR = 12; //number of data to transfer from the peripheral to memory.
Zbyszek 9:9ed9dffd602a 208 DMA1_Channel2->CPAR = (int32_t)&SPI1->DR; //Source Adddress = SPI data register
Zbyszek 11:366f1186c121 209 DMA1_Channel2->CMAR = (int32_t)&received_data[0]; //Destination address = received_data array
Zbyszek 9:9ed9dffd602a 210 //-----------------------------------------------Receive-----------------------------------------------------
Zbyszek 9:9ed9dffd602a 211
Zbyszek 9:9ed9dffd602a 212 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 9:9ed9dffd602a 213
Zbyszek 9:9ed9dffd602a 214 SET_DMA1_CH3_CCR_DIR_BIT(); //Memory->Peripheral
Zbyszek 9:9ed9dffd602a 215 SET_DMA1_CH3_CCR_PSIZE_BITS(); //16 bits
Zbyszek 9:9ed9dffd602a 216 SET_DMA1_CH3_CCR_MSIZE_BITS(); //16 bits
Zbyszek 9:9ed9dffd602a 217 SET_DMA1_CH3_CCR_MINC_BIT(); //Memory increment mode
Zbyszek 9:9ed9dffd602a 218 // SET_DMA1_CH3_CCR_PINC_BIT(); //Peripheral increment mode
Zbyszek 9:9ed9dffd602a 219 SET_DMA1_CH3_CCR_TCIE_BIT(); //Transfer complete interrupt enable
Zbyszek 9:9ed9dffd602a 220 SET_DMA1_CH3_CCR_CIRC_BIT(); //Circular Buffer mode
Zbyszek 9:9ed9dffd602a 221 SET_DMA1_CH3_CCR_PL_BITS(); //Priority Level = Highest
Zbyszek 9:9ed9dffd602a 222
Zbyszek 9:9ed9dffd602a 223 DMA1_Channel3->CNDTR = 12; //number of data to transfer from memory to the peripheral
Zbyszek 11:366f1186c121 224 DMA1_Channel3->CPAR = (int32_t)&SPI1->DR; //Destination address = SPI data register
Zbyszek 11:366f1186c121 225 DMA1_Channel3->CMAR = (int32_t)&data_to_transmit[0]; //Source address = data_to_transmit
Zbyszek 9:9ed9dffd602a 226 //-----------------------------------------------Transmission------------------------------------------------
Zbyszek 8:e87027349167 227
Zbyszek 8:e87027349167 228
Zbyszek 11:366f1186c121 229 NVIC->ISER[0] |= (1u<<12); //Enable DMA1 channel 2 interrupt
Zbyszek 10:5b96211275d4 230 NVIC->ISER[0] |= (1u<<13); //Enable DMA1 channel 3 interrupt
Zbyszek 11:366f1186c121 231 NVIC_EnableIRQ(DMA1_Channel2_IRQn);
Zbyszek 10:5b96211275d4 232 NVIC_EnableIRQ(DMA1_Channel3_IRQn);
Zbyszek 8:e87027349167 233
Zbyszek 8:e87027349167 234 }
Zbyszek 9:9ed9dffd602a 235
Zbyszek 9:9ed9dffd602a 236
Zbyszek 9:9ed9dffd602a 237 //Interrupt Handler for DMA1 Channel 2
Zbyszek 10:5b96211275d4 238 extern "C" void DMA1_Channel2_IRQHandler(void) {
Zbyszek 11:366f1186c121 239 uint16_t n;
Zbyszek 11:366f1186c121 240
Zbyszek 9:9ed9dffd602a 241 CLEAR_DMA1_CH2_IFCR_GFLAG(); //Clear Global Interrupt flag
Zbyszek 11:366f1186c121 242 for(int x = 0; x <= 11; x++) {
Zbyszek 11:366f1186c121 243
Zbyszek 11:366f1186c121 244 n = received_data[x];
Zbyszek 11:366f1186c121 245 n &= ~(8191); //remove first 13 bits
Zbyszek 11:366f1186c121 246 n = n >> 13; //shift by right by 13
Zbyszek 11:366f1186c121 247 SampleFIFO[pointerFS][x] = received_data[x];
Zbyszek 11:366f1186c121 248 // printf("%d \n\r", n);
Zbyszek 11:366f1186c121 249 }
Zbyszek 11:366f1186c121 250 newDataFlag = 1;
Zbyszek 9:9ed9dffd602a 251 }
Zbyszek 9:9ed9dffd602a 252
Zbyszek 9:9ed9dffd602a 253
Zbyszek 9:9ed9dffd602a 254 //Interrupt Handler for DMA1 Channel 3
Zbyszek 11:366f1186c121 255 extern "C" void DMA1_Channel3_IRQHandler(void) {
Zbyszek 10:5b96211275d4 256 if(DMA1->ISR&(1u<<9)) { //Check whteher data transmit transfer is complete
Zbyszek 10:5b96211275d4 257 //Read data from the array that stores received data
Zbyszek 12:3e7da86a49ff 258 /*
Zbyszek 11:366f1186c121 259 for(int x = 0; x <= 11; x++) {
Zbyszek 10:5b96211275d4 260 data_to_transmit[x] = x+1;
Zbyszek 10:5b96211275d4 261 }
Zbyszek 12:3e7da86a49ff 262 */
Zbyszek 10:5b96211275d4 263 CLEAR_DMA1_CH3_IFCR_GFLAG(); //Clear global channel interrupt flag for channel 3
Zbyszek 10:5b96211275d4 264 } //Clear Global Interrupt flag
Zbyszek 9:9ed9dffd602a 265 }
Zbyszek 9:9ed9dffd602a 266