Vybhav Kadaba
Minor changes to support ADMW FWv1.17.75
inc/admw1001/ADMW1001_REGISTERS.h@43:e1789b7214cf, 2020-01-07 (annotated)
- Committer:
- Vkadaba
- Date:
- Tue Jan 07 05:45:58 2020 +0000
- Revision:
- 43:e1789b7214cf
- Parent:
- 36:54e2418e7620
- Child:
- 44:94bdfaefddac
Added CycleTime units in seconds Added global scopes for .excitationState and .groundSwitch on mbed and added same on all config files
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Vkadaba | 5:0728bde67bdb | 1 | /* ================================================================================ |
| Vkadaba | 32:52445bef314d | 2 | |
| Vkadaba | 32:52445bef314d | 3 | Created by : |
| Vkadaba | 32:52445bef314d | 4 | Created on : 2019 Oct 08, 09:43 GMT Daylight Time |
| Vkadaba | 5:0728bde67bdb | 5 | |
| Vkadaba | 6:9d393a9677f4 | 6 | Project : ADMW1001_REGISTERS |
| Vkadaba | 6:9d393a9677f4 | 7 | File : ADMW1001_REGISTERS.h |
| Vkadaba | 5:0728bde67bdb | 8 | Description : Register Definitions |
| Vkadaba | 5:0728bde67bdb | 9 | |
| Vkadaba | 32:52445bef314d | 10 | !! ADI Confidential !! |
| Vkadaba | 32:52445bef314d | 11 | INTERNAL USE ONLY |
| Vkadaba | 5:0728bde67bdb | 12 | |
| Vkadaba | 6:9d393a9677f4 | 13 | Copyright (c) 2019 Analog Devices, Inc. All Rights Reserved. |
| Vkadaba | 5:0728bde67bdb | 14 | This software is proprietary and confidential to Analog Devices, Inc. and |
| Vkadaba | 5:0728bde67bdb | 15 | its licensors. |
| Vkadaba | 5:0728bde67bdb | 16 | |
| Vkadaba | 5:0728bde67bdb | 17 | This file was auto-generated. Do not make local changes to this file. |
| Vkadaba | 32:52445bef314d | 18 | |
| Vkadaba | 32:52445bef314d | 19 | Auto generation script information: |
| Vkadaba | 32:52445bef314d | 20 | Script: C:\Program Files (x86)\Yoda-19.05.01\generators\inc\genHeaders |
| Vkadaba | 32:52445bef314d | 21 | Last modified: 26-SEP-2017 |
| Vkadaba | 5:0728bde67bdb | 22 | |
| Vkadaba | 5:0728bde67bdb | 23 | ================================================================================ */ |
| Vkadaba | 5:0728bde67bdb | 24 | |
| Vkadaba | 5:0728bde67bdb | 25 | #ifndef _DEF_ADMW1001_REGISTERS_H |
| Vkadaba | 5:0728bde67bdb | 26 | #define _DEF_ADMW1001_REGISTERS_H |
| Vkadaba | 5:0728bde67bdb | 27 | |
| Vkadaba | 5:0728bde67bdb | 28 | #if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) |
| Vkadaba | 5:0728bde67bdb | 29 | #include <stdint.h> |
| Vkadaba | 5:0728bde67bdb | 30 | #endif /* _LANGUAGE_C */ |
| Vkadaba | 5:0728bde67bdb | 31 | |
| Vkadaba | 5:0728bde67bdb | 32 | #ifndef __ADI_GENERATED_DEF_HEADERS__ |
| Vkadaba | 5:0728bde67bdb | 33 | #define __ADI_GENERATED_DEF_HEADERS__ 1 |
| Vkadaba | 5:0728bde67bdb | 34 | #endif |
| Vkadaba | 5:0728bde67bdb | 35 | |
| Vkadaba | 6:9d393a9677f4 | 36 | #define __ADI_HAS_CORE__ 1 |
| Vkadaba | 6:9d393a9677f4 | 37 | #define __ADI_HAS_SPI__ 1 |
| Vkadaba | 8:2f2775c34640 | 38 | #define __ADI_HAS_ADMW_TEST__ 1 |
| Vkadaba | 5:0728bde67bdb | 39 | |
| Vkadaba | 5:0728bde67bdb | 40 | /* ============================================================================================================================ |
| Vkadaba | 5:0728bde67bdb | 41 | |
| Vkadaba | 5:0728bde67bdb | 42 | ============================================================================================================================ */ |
| Vkadaba | 5:0728bde67bdb | 43 | |
| Vkadaba | 5:0728bde67bdb | 44 | /* ============================================================================================================================ |
| Vkadaba | 6:9d393a9677f4 | 45 | SPI |
| Vkadaba | 5:0728bde67bdb | 46 | ============================================================================================================================ */ |
| Vkadaba | 32:52445bef314d | 47 | #define MOD_SPI_BASE 0x00000000 /* */ |
| Vkadaba | 32:52445bef314d | 48 | #define MOD_SPI_MASK 0x00007FFF /* */ |
| Vkadaba | 6:9d393a9677f4 | 49 | #define REG_SPI_INTERFACE_CONFIG_A_RESET 0x00000030 /* Reset Value for Interface_Config_A */ |
| Vkadaba | 6:9d393a9677f4 | 50 | #define REG_SPI_INTERFACE_CONFIG_A 0x00000000 /* SPI Interface Configuration A */ |
| Vkadaba | 6:9d393a9677f4 | 51 | #define REG_SPI_INTERFACE_CONFIG_B_RESET 0x00000000 /* Reset Value for Interface_Config_B */ |
| Vkadaba | 6:9d393a9677f4 | 52 | #define REG_SPI_INTERFACE_CONFIG_B 0x00000001 /* SPI Interface Configuration B */ |
| Vkadaba | 6:9d393a9677f4 | 53 | #define REG_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */ |
| Vkadaba | 6:9d393a9677f4 | 54 | #define REG_SPI_CHIP_TYPE 0x00000003 /* SPI Chip Type */ |
| Vkadaba | 6:9d393a9677f4 | 55 | #define REG_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */ |
| Vkadaba | 6:9d393a9677f4 | 56 | #define REG_SPI_PRODUCT_ID_L 0x00000004 /* SPI Product ID Low */ |
| Vkadaba | 6:9d393a9677f4 | 57 | #define REG_SPI_PRODUCT_ID_H_RESET 0x00000000 /* Reset Value for Product_ID_H */ |
| Vkadaba | 6:9d393a9677f4 | 58 | #define REG_SPI_PRODUCT_ID_H 0x00000005 /* SPI Product ID High */ |
| Vkadaba | 6:9d393a9677f4 | 59 | #define REG_SPI_CHIP_GRADE_RESET 0x00000000 /* Reset Value for Chip_Grade */ |
| Vkadaba | 6:9d393a9677f4 | 60 | #define REG_SPI_CHIP_GRADE 0x00000006 /* SPI Chip Grade */ |
| Vkadaba | 6:9d393a9677f4 | 61 | #define REG_SPI_SCRATCH_PAD_RESET 0x00000000 /* Reset Value for Scratch_Pad */ |
| Vkadaba | 6:9d393a9677f4 | 62 | #define REG_SPI_SCRATCH_PAD 0x0000000A /* SPI Scratch Pad */ |
| Vkadaba | 6:9d393a9677f4 | 63 | #define REG_SPI_SPI_REVISION_RESET 0x00000082 /* Reset Value for SPI_Revision */ |
| Vkadaba | 6:9d393a9677f4 | 64 | #define REG_SPI_SPI_REVISION 0x0000000B /* SPI SPI Revision */ |
| Vkadaba | 6:9d393a9677f4 | 65 | #define REG_SPI_VENDOR_L_RESET 0x00000056 /* Reset Value for Vendor_L */ |
| Vkadaba | 6:9d393a9677f4 | 66 | #define REG_SPI_VENDOR_L 0x0000000C /* SPI Vendor ID Low */ |
| Vkadaba | 6:9d393a9677f4 | 67 | #define REG_SPI_VENDOR_H_RESET 0x00000004 /* Reset Value for Vendor_H */ |
| Vkadaba | 6:9d393a9677f4 | 68 | #define REG_SPI_VENDOR_H 0x0000000D /* SPI Vendor ID High */ |
| Vkadaba | 6:9d393a9677f4 | 69 | #define REG_SPI_STREAM_MODE_RESET 0x00000000 /* Reset Value for Stream_Mode */ |
| Vkadaba | 6:9d393a9677f4 | 70 | #define REG_SPI_STREAM_MODE 0x0000000E /* SPI Stream Mode */ |
| Vkadaba | 6:9d393a9677f4 | 71 | #define REG_SPI_TRANSFER_CONFIG_RESET 0x00000000 /* Reset Value for Transfer_Config */ |
| Vkadaba | 6:9d393a9677f4 | 72 | #define REG_SPI_TRANSFER_CONFIG 0x0000000F /* SPI Transfer Config */ |
| Vkadaba | 6:9d393a9677f4 | 73 | #define REG_SPI_INTERFACE_CONFIG_C_RESET 0x00000033 /* Reset Value for Interface_Config_C */ |
| Vkadaba | 6:9d393a9677f4 | 74 | #define REG_SPI_INTERFACE_CONFIG_C 0x00000010 /* SPI Interface Configuration C */ |
| Vkadaba | 6:9d393a9677f4 | 75 | #define REG_SPI_INTERFACE_STATUS_A_RESET 0x00000000 /* Reset Value for Interface_Status_A */ |
| Vkadaba | 6:9d393a9677f4 | 76 | #define REG_SPI_INTERFACE_STATUS_A 0x00000011 /* SPI Interface Status A */ |
| Vkadaba | 5:0728bde67bdb | 77 | |
| Vkadaba | 5:0728bde67bdb | 78 | /* ============================================================================================================================ |
| Vkadaba | 6:9d393a9677f4 | 79 | SPI Register BitMasks, Positions & Enumerations |
| Vkadaba | 5:0728bde67bdb | 80 | ============================================================================================================================ */ |
| Vkadaba | 5:0728bde67bdb | 81 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 82 | SPI_INTERFACE_CONFIG_A Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 83 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 84 | #define BITP_SPI_INTERFACE_CONFIG_A_SW_RESET 7 /* First of Two of the SW_RESET Bits. */ |
| Vkadaba | 5:0728bde67bdb | 85 | #define BITP_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 5 /* Determines Sequential Addressing Behavior */ |
| Vkadaba | 32:52445bef314d | 86 | #define BITP_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4 /* Serial Data Output Pin Enable */ |
| Vkadaba | 32:52445bef314d | 87 | #define BITP_SPI_INTERFACE_CONFIG_A_SW_RESETX 0 /* Second of Two of the SW_RESET Bits. */ |
| Vkadaba | 32:52445bef314d | 88 | #define BITM_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080 /* First of Two of the SW_RESET Bits. */ |
| Vkadaba | 5:0728bde67bdb | 89 | #define BITM_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 0x00000020 /* Determines Sequential Addressing Behavior */ |
| Vkadaba | 32:52445bef314d | 90 | #define BITM_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010 /* Serial Data Output Pin Enable */ |
| Vkadaba | 32:52445bef314d | 91 | #define BITM_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001 /* Second of Two of the SW_RESET Bits. */ |
| Vkadaba | 6:9d393a9677f4 | 92 | #define ENUM_SPI_INTERFACE_CONFIG_A_DESCEND 0x00000000 /* Addr_Ascension: Address accessed is decremented by one for each data byte when streaming */ |
| Vkadaba | 6:9d393a9677f4 | 93 | #define ENUM_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020 /* Addr_Ascension: Address accessed is incremented by one for each data byte when streaming */ |
| Vkadaba | 5:0728bde67bdb | 94 | |
| Vkadaba | 5:0728bde67bdb | 95 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 96 | SPI_INTERFACE_CONFIG_B Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 97 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 98 | #define BITP_SPI_INTERFACE_CONFIG_B_SINGLE_INST 7 /* Select Streaming or Single Instruction Mode */ |
| Vkadaba | 5:0728bde67bdb | 99 | #define BITM_SPI_INTERFACE_CONFIG_B_SINGLE_INST 0x00000080 /* Select Streaming or Single Instruction Mode */ |
| Vkadaba | 5:0728bde67bdb | 100 | #define ENUM_SPI_INTERFACE_CONFIG_B_STREAMING_MODE 0x00000000 /* Single_Inst: Streaming mode is enabled */ |
| Vkadaba | 5:0728bde67bdb | 101 | #define ENUM_SPI_INTERFACE_CONFIG_B_SINGLE_INSTRUCTION_MODE 0x00000080 /* Single_Inst: Single Instruction mode is enabled */ |
| Vkadaba | 5:0728bde67bdb | 102 | |
| Vkadaba | 5:0728bde67bdb | 103 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 104 | SPI_CHIP_TYPE Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 105 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 106 | #define BITP_SPI_CHIP_TYPE_CHIP_TYPE 0 /* Precision ADC */ |
| Vkadaba | 6:9d393a9677f4 | 107 | #define BITM_SPI_CHIP_TYPE_CHIP_TYPE 0x0000000F /* Precision ADC */ |
| Vkadaba | 5:0728bde67bdb | 108 | |
| Vkadaba | 5:0728bde67bdb | 109 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 110 | SPI_PRODUCT_ID_L Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 111 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 112 | #define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 4 /* These Bits are Fixed on Die Configured for Multiple Generics */ |
| Vkadaba | 32:52445bef314d | 113 | #define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0 /* These Bits Vary on Die Configured for Multiple Generics */ |
| Vkadaba | 32:52445bef314d | 114 | #define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 0x000000F0 /* These Bits are Fixed on Die Configured for Multiple Generics */ |
| Vkadaba | 32:52445bef314d | 115 | #define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0x0000000F /* These Bits Vary on Die Configured for Multiple Generics */ |
| Vkadaba | 5:0728bde67bdb | 116 | |
| Vkadaba | 5:0728bde67bdb | 117 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 118 | SPI_PRODUCT_ID_H Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 119 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 120 | #define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0 /* These Bits are Fixed on Die Configured for Multiple Generics */ |
| Vkadaba | 32:52445bef314d | 121 | #define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0x000000FF /* These Bits are Fixed on Die Configured for Multiple Generics */ |
| Vkadaba | 5:0728bde67bdb | 122 | |
| Vkadaba | 5:0728bde67bdb | 123 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 124 | SPI_CHIP_GRADE Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 125 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 126 | #define BITP_SPI_CHIP_GRADE_GRADE 4 /* Device Performance Grade */ |
| Vkadaba | 32:52445bef314d | 127 | #define BITP_SPI_CHIP_GRADE_DEVICE_REVISION 0 /* Device Hardware Revision */ |
| Vkadaba | 32:52445bef314d | 128 | #define BITM_SPI_CHIP_GRADE_GRADE 0x000000F0 /* Device Performance Grade */ |
| Vkadaba | 32:52445bef314d | 129 | #define BITM_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F /* Device Hardware Revision */ |
| Vkadaba | 5:0728bde67bdb | 130 | |
| Vkadaba | 5:0728bde67bdb | 131 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 132 | SPI_SCRATCH_PAD Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 133 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 134 | #define BITP_SPI_SCRATCH_PAD_SCRATCH_VALUE 0 /* Software Scratchpad */ |
| Vkadaba | 6:9d393a9677f4 | 135 | #define BITM_SPI_SCRATCH_PAD_SCRATCH_VALUE 0x000000FF /* Software Scratchpad */ |
| Vkadaba | 5:0728bde67bdb | 136 | |
| Vkadaba | 5:0728bde67bdb | 137 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 138 | SPI_SPI_REVISION Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 139 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 140 | #define BITP_SPI_SPI_REVISION_SPI_TYPE 6 /* Always Reads as 0x2 */ |
| Vkadaba | 6:9d393a9677f4 | 141 | #define BITP_SPI_SPI_REVISION_VERSION 0 /* SPI Version */ |
| Vkadaba | 6:9d393a9677f4 | 142 | #define BITM_SPI_SPI_REVISION_SPI_TYPE 0x000000C0 /* Always Reads as 0x2 */ |
| Vkadaba | 6:9d393a9677f4 | 143 | #define BITM_SPI_SPI_REVISION_VERSION 0x0000003F /* SPI Version */ |
| Vkadaba | 32:52445bef314d | 144 | #define ENUM_SPI_SPI_REVISION_ADI_SPI 0x00000000 /* SPI_Type: ADI_SPI */ |
| Vkadaba | 32:52445bef314d | 145 | #define ENUM_SPI_SPI_REVISION_LPT_SPI 0x00000080 /* SPI_Type: LPT_SPI */ |
| Vkadaba | 6:9d393a9677f4 | 146 | #define ENUM_SPI_SPI_REVISION_REV1_0 0x00000002 /* Version: Revision 1.0 */ |
| Vkadaba | 5:0728bde67bdb | 147 | |
| Vkadaba | 5:0728bde67bdb | 148 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 149 | SPI_VENDOR_L Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 150 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 151 | #define BITP_SPI_VENDOR_L_VID 0 /* Analog Devices Vendor ID */ |
| Vkadaba | 6:9d393a9677f4 | 152 | #define BITM_SPI_VENDOR_L_VID 0x000000FF /* Analog Devices Vendor ID */ |
| Vkadaba | 5:0728bde67bdb | 153 | |
| Vkadaba | 5:0728bde67bdb | 154 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 155 | SPI_VENDOR_H Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 156 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 157 | #define BITP_SPI_VENDOR_H_VID 0 /* Analog Devices Vendor ID */ |
| Vkadaba | 6:9d393a9677f4 | 158 | #define BITM_SPI_VENDOR_H_VID 0x000000FF /* Analog Devices Vendor ID */ |
| Vkadaba | 5:0728bde67bdb | 159 | |
| Vkadaba | 5:0728bde67bdb | 160 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 161 | SPI_STREAM_MODE Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 162 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 163 | #define BITP_SPI_STREAM_MODE_LOOP_COUNT 0 /* Set the Data Byte Count Before Looping to Start Address */ |
| Vkadaba | 32:52445bef314d | 164 | #define BITM_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF /* Set the Data Byte Count Before Looping to Start Address */ |
| Vkadaba | 5:0728bde67bdb | 165 | |
| Vkadaba | 5:0728bde67bdb | 166 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 167 | SPI_TRANSFER_CONFIG Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 168 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 169 | #define BITP_SPI_TRANSFER_CONFIG_STREAM_MODE 1 /* When Streaming, Control Master to Slave Transfer */ |
| Vkadaba | 32:52445bef314d | 170 | #define BITM_SPI_TRANSFER_CONFIG_STREAM_MODE 0x00000002 /* When Streaming, Control Master to Slave Transfer */ |
| Vkadaba | 5:0728bde67bdb | 171 | #define ENUM_SPI_TRANSFER_CONFIG_UPDATE_ON_WRITE 0x00000000 /* Stream_Mode: Transfers after each byte/mulit-byte register */ |
| Vkadaba | 5:0728bde67bdb | 172 | #define ENUM_SPI_TRANSFER_CONFIG_UPDATE_ON_ADDRESS_LOOP 0x00000002 /* Stream_Mode: Transfers when address loops */ |
| Vkadaba | 5:0728bde67bdb | 173 | |
| Vkadaba | 5:0728bde67bdb | 174 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 175 | SPI_INTERFACE_CONFIG_C Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 176 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 177 | #define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 6 /* CRC Enable */ |
| Vkadaba | 32:52445bef314d | 178 | #define BITP_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 5 /* Multibyte Registers Must Be Read or Written in Full */ |
| Vkadaba | 32:52445bef314d | 179 | #define BITP_SPI_INTERFACE_CONFIG_C_SEND_STATUS 4 /* Sends Status in 4-Wire Mode When Enabled */ |
| Vkadaba | 5:0728bde67bdb | 180 | #define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0 /* Inverted CRC Enable */ |
| Vkadaba | 5:0728bde67bdb | 181 | #define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 0x000000C0 /* CRC Enable */ |
| Vkadaba | 32:52445bef314d | 182 | #define BITM_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 0x00000020 /* Multibyte Registers Must Be Read or Written in Full */ |
| Vkadaba | 32:52445bef314d | 183 | #define BITM_SPI_INTERFACE_CONFIG_C_SEND_STATUS 0x00000010 /* Sends Status in 4-Wire Mode When Enabled */ |
| Vkadaba | 5:0728bde67bdb | 184 | #define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0x00000003 /* Inverted CRC Enable */ |
| Vkadaba | 5:0728bde67bdb | 185 | #define ENUM_SPI_INTERFACE_CONFIG_C_DISABLED 0x00000000 /* CRC_Enable: CRC Disabled */ |
| Vkadaba | 6:9d393a9677f4 | 186 | #define ENUM_SPI_INTERFACE_CONFIG_C_ENABLED 0x00000040 /* CRC_Enable: CRC Enabled */ |
| Vkadaba | 5:0728bde67bdb | 187 | #define ENUM_SPI_INTERFACE_CONFIG_C_NORMAL_ACCESS 0x00000000 /* Strict_Register_Access: Normal mode, no access restrictions */ |
| Vkadaba | 5:0728bde67bdb | 188 | #define ENUM_SPI_INTERFACE_CONFIG_C_STRICT_ACCESS 0x00000020 /* Strict_Register_Access: Strict mode, multi-byte registers require all bytes read/written */ |
| Vkadaba | 5:0728bde67bdb | 189 | |
| Vkadaba | 5:0728bde67bdb | 190 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 191 | SPI_INTERFACE_STATUS_A Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 192 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 193 | #define BITP_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7 /* Device Not Ready for Transaction */ |
| Vkadaba | 5:0728bde67bdb | 194 | #define BITP_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 4 /* Incorrect Number of Clocks Detected in a Transaction */ |
| Vkadaba | 5:0728bde67bdb | 195 | #define BITP_SPI_INTERFACE_STATUS_A_CRC_ERROR 3 /* Invalid/No CRC Received */ |
| Vkadaba | 32:52445bef314d | 196 | #define BITP_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2 /* Write to Read Only Register Attempted */ |
| Vkadaba | 5:0728bde67bdb | 197 | #define BITP_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 1 /* Set When Fewer Than Expected Number of Bytes Read/Written */ |
| Vkadaba | 32:52445bef314d | 198 | #define BITP_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0 /* Attempt to Read/Write Nonexistent Register Address */ |
| Vkadaba | 5:0728bde67bdb | 199 | #define BITM_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 0x00000080 /* Device Not Ready for Transaction */ |
| Vkadaba | 5:0728bde67bdb | 200 | #define BITM_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 0x00000010 /* Incorrect Number of Clocks Detected in a Transaction */ |
| Vkadaba | 5:0728bde67bdb | 201 | #define BITM_SPI_INTERFACE_STATUS_A_CRC_ERROR 0x00000008 /* Invalid/No CRC Received */ |
| Vkadaba | 32:52445bef314d | 202 | #define BITM_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004 /* Write to Read Only Register Attempted */ |
| Vkadaba | 5:0728bde67bdb | 203 | #define BITM_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 0x00000002 /* Set When Fewer Than Expected Number of Bytes Read/Written */ |
| Vkadaba | 32:52445bef314d | 204 | #define BITM_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001 /* Attempt to Read/Write Nonexistent Register Address */ |
| Vkadaba | 5:0728bde67bdb | 205 | |
| Vkadaba | 5:0728bde67bdb | 206 | |
| Vkadaba | 5:0728bde67bdb | 207 | /* ============================================================================================================================ |
| Vkadaba | 32:52445bef314d | 208 | ADISENSE1000 Core Registers |
| Vkadaba | 5:0728bde67bdb | 209 | ============================================================================================================================ */ |
| Vkadaba | 5:0728bde67bdb | 210 | |
| Vkadaba | 5:0728bde67bdb | 211 | /* ============================================================================================================================ |
| Vkadaba | 6:9d393a9677f4 | 212 | CORE |
| Vkadaba | 5:0728bde67bdb | 213 | ============================================================================================================================ */ |
| Vkadaba | 32:52445bef314d | 214 | #define MOD_CORE_BASE 0x00000010 /* ADISENSE1000 Core Registers */ |
| Vkadaba | 32:52445bef314d | 215 | #define MOD_CORE_MASK 0x00007FFF /* ADISENSE1000 Core Registers */ |
| Vkadaba | 6:9d393a9677f4 | 216 | #define REG_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */ |
| Vkadaba | 32:52445bef314d | 217 | #define REG_CORE_COMMAND 0x00000014 /* CORE Special Command Register */ |
| Vkadaba | 6:9d393a9677f4 | 218 | #define REG_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */ |
| Vkadaba | 6:9d393a9677f4 | 219 | #define REG_CORE_MODE 0x00000016 /* CORE Operating Mode and DRDY Control */ |
| Vkadaba | 6:9d393a9677f4 | 220 | #define REG_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */ |
| Vkadaba | 32:52445bef314d | 221 | #define REG_CORE_POWER_CONFIG 0x00000017 /* CORE Power Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 222 | #define REG_CORE_CYCLE_CONTROL_RESET 0x00000000 /* Reset Value for Cycle_Control */ |
| Vkadaba | 6:9d393a9677f4 | 223 | #define REG_CORE_CYCLE_CONTROL 0x00000018 /* CORE Measurement Cycle */ |
| Vkadaba | 32:52445bef314d | 224 | #define REG_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */ |
| Vkadaba | 32:52445bef314d | 225 | #define REG_CORE_FIFO_NUM_CYCLES 0x0000001A /* CORE Number of Measurement Cycles to Store in FIFO */ |
| Vkadaba | 6:9d393a9677f4 | 226 | #define REG_CORE_STATUS_RESET 0x00000000 /* Reset Value for Status */ |
| Vkadaba | 6:9d393a9677f4 | 227 | #define REG_CORE_STATUS 0x00000020 /* CORE General Status */ |
| Vkadaba | 6:9d393a9677f4 | 228 | #define REG_CORE_CHANNEL_ALERT_STATUS_RESET 0x00000000 /* Reset Value for Channel_Alert_Status */ |
| Vkadaba | 6:9d393a9677f4 | 229 | #define REG_CORE_CHANNEL_ALERT_STATUS 0x00000026 /* CORE Alert Status Summary */ |
| Vkadaba | 6:9d393a9677f4 | 230 | #define REG_CORE_ALERT_DETAIL_CHn_RESET 0x00000000 /* Reset Value for Alert_Detail_Ch[n] */ |
| Vkadaba | 6:9d393a9677f4 | 231 | #define REG_CORE_ALERT_DETAIL_CH0_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH0 */ |
| Vkadaba | 6:9d393a9677f4 | 232 | #define REG_CORE_ALERT_DETAIL_CH1_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH1 */ |
| Vkadaba | 6:9d393a9677f4 | 233 | #define REG_CORE_ALERT_DETAIL_CH2_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH2 */ |
| Vkadaba | 6:9d393a9677f4 | 234 | #define REG_CORE_ALERT_DETAIL_CH3_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH3 */ |
| Vkadaba | 6:9d393a9677f4 | 235 | #define REG_CORE_ALERT_DETAIL_CH4_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH4 */ |
| Vkadaba | 6:9d393a9677f4 | 236 | #define REG_CORE_ALERT_DETAIL_CH5_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH5 */ |
| Vkadaba | 6:9d393a9677f4 | 237 | #define REG_CORE_ALERT_DETAIL_CH6_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH6 */ |
| Vkadaba | 6:9d393a9677f4 | 238 | #define REG_CORE_ALERT_DETAIL_CH7_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH7 */ |
| Vkadaba | 6:9d393a9677f4 | 239 | #define REG_CORE_ALERT_DETAIL_CH8_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH8 */ |
| Vkadaba | 6:9d393a9677f4 | 240 | #define REG_CORE_ALERT_DETAIL_CH9_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH9 */ |
| Vkadaba | 6:9d393a9677f4 | 241 | #define REG_CORE_ALERT_DETAIL_CH10_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH10 */ |
| Vkadaba | 6:9d393a9677f4 | 242 | #define REG_CORE_ALERT_DETAIL_CH11_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH11 */ |
| Vkadaba | 6:9d393a9677f4 | 243 | #define REG_CORE_ALERT_DETAIL_CH12_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH12 */ |
| Vkadaba | 32:52445bef314d | 244 | #define REG_CORE_ALERT_DETAIL_CH0 0x0000002A /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 245 | #define REG_CORE_ALERT_DETAIL_CH1 0x0000002C /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 246 | #define REG_CORE_ALERT_DETAIL_CH2 0x0000002E /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 247 | #define REG_CORE_ALERT_DETAIL_CH3 0x00000030 /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 248 | #define REG_CORE_ALERT_DETAIL_CH4 0x00000032 /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 249 | #define REG_CORE_ALERT_DETAIL_CH5 0x00000034 /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 250 | #define REG_CORE_ALERT_DETAIL_CH6 0x00000036 /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 251 | #define REG_CORE_ALERT_DETAIL_CH7 0x00000038 /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 252 | #define REG_CORE_ALERT_DETAIL_CH8 0x0000003A /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 253 | #define REG_CORE_ALERT_DETAIL_CH9 0x0000003C /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 254 | #define REG_CORE_ALERT_DETAIL_CH10 0x0000003E /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 255 | #define REG_CORE_ALERT_DETAIL_CH11 0x00000040 /* CORE Detailed Channel Error Information */ |
| Vkadaba | 32:52445bef314d | 256 | #define REG_CORE_ALERT_DETAIL_CH12 0x00000042 /* CORE Detailed Channel Error Information */ |
| Vkadaba | 6:9d393a9677f4 | 257 | #define REG_CORE_ALERT_DETAIL_CHn(i) (REG_CORE_ALERT_DETAIL_CH0 + ((i) * 2)) |
| Vkadaba | 8:2f2775c34640 | 258 | #define REG_CORE_ALERT_DETAIL_CHn_COUNT 13 |
| Vkadaba | 6:9d393a9677f4 | 259 | #define REG_CORE_ERROR_CODE_RESET 0x00000000 /* Reset Value for Error_Code */ |
| Vkadaba | 6:9d393a9677f4 | 260 | #define REG_CORE_ERROR_CODE 0x0000004C /* CORE Code Indicating Source of Error */ |
| Vkadaba | 32:52445bef314d | 261 | #define REG_CORE_EXTERNAL_REFERENCE_RESISTOR_RESET 0x447A0000 /* Reset Value for External_Reference_Resistor */ |
| Vkadaba | 32:52445bef314d | 262 | #define REG_CORE_EXTERNAL_REFERENCE_RESISTOR 0x00000050 /* CORE External Reference Resistor Value */ |
| Vkadaba | 36:54e2418e7620 | 263 | #define REG_CORE_EXTERNAL_VOLTAGE_REFERENCE_RESET 0x3F99999A /* Reset Value for External_Voltage_Reference */ |
| Vkadaba | 36:54e2418e7620 | 264 | #define REG_CORE_EXTERNAL_VOLTAGE_REFERENCE 0x00000054 /* CORE External Reference Information */ |
| Vkadaba | 6:9d393a9677f4 | 265 | #define REG_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */ |
| Vkadaba | 6:9d393a9677f4 | 266 | #define REG_CORE_DIAGNOSTICS_CONTROL 0x0000005C /* CORE Diagnostic Control */ |
| Vkadaba | 6:9d393a9677f4 | 267 | #define REG_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */ |
| Vkadaba | 6:9d393a9677f4 | 268 | #define REG_CORE_DATA_FIFO 0x00000060 /* CORE FIFO Buffer of Sensor Results */ |
| Vkadaba | 6:9d393a9677f4 | 269 | #define REG_CORE_DEBUG_CODE_RESET 0x00000000 /* Reset Value for Debug_Code */ |
| Vkadaba | 6:9d393a9677f4 | 270 | #define REG_CORE_DEBUG_CODE 0x00000064 /* CORE Additional Information on Source of Alert or Errors */ |
| Vkadaba | 32:52445bef314d | 271 | #define REG_CORE_TEST_REG_ACCESS_RESET 0x00000000 /* Reset Value for Test_Reg_Access */ |
| Vkadaba | 32:52445bef314d | 272 | #define REG_CORE_TEST_REG_ACCESS 0x0000006C /* CORE Allows Access to Test (Hidden) Registers and Features */ |
| Vkadaba | 6:9d393a9677f4 | 273 | #define REG_CORE_LUT_SELECT_RESET 0x00000000 /* Reset Value for LUT_Select */ |
| Vkadaba | 32:52445bef314d | 274 | #define REG_CORE_LUT_SELECT 0x00000070 /* CORE LUT Read/Write Strobe */ |
| Vkadaba | 6:9d393a9677f4 | 275 | #define REG_CORE_LUT_OFFSET_RESET 0x00000000 /* Reset Value for LUT_Offset */ |
| Vkadaba | 6:9d393a9677f4 | 276 | #define REG_CORE_LUT_OFFSET 0x00000072 /* CORE Offset into Selected LUT */ |
| Vkadaba | 6:9d393a9677f4 | 277 | #define REG_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */ |
| Vkadaba | 6:9d393a9677f4 | 278 | #define REG_CORE_LUT_DATA 0x00000074 /* CORE Data to Read/Write from Addressed LUT Entry */ |
| Vkadaba | 32:52445bef314d | 279 | #define REG_CORE_REVISION_RESET 0x01000000 /* Reset Value for Revision */ |
| Vkadaba | 6:9d393a9677f4 | 280 | #define REG_CORE_REVISION 0x0000008C /* CORE Hardware, Firmware Revision */ |
| Vkadaba | 6:9d393a9677f4 | 281 | #define REG_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */ |
| Vkadaba | 6:9d393a9677f4 | 282 | #define REG_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT0 */ |
| Vkadaba | 6:9d393a9677f4 | 283 | #define REG_CORE_CHANNEL_COUNT1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT1 */ |
| Vkadaba | 6:9d393a9677f4 | 284 | #define REG_CORE_CHANNEL_COUNT2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT2 */ |
| Vkadaba | 6:9d393a9677f4 | 285 | #define REG_CORE_CHANNEL_COUNT3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT3 */ |
| Vkadaba | 6:9d393a9677f4 | 286 | #define REG_CORE_CHANNEL_COUNT4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT4 */ |
| Vkadaba | 6:9d393a9677f4 | 287 | #define REG_CORE_CHANNEL_COUNT5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT5 */ |
| Vkadaba | 6:9d393a9677f4 | 288 | #define REG_CORE_CHANNEL_COUNT6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT6 */ |
| Vkadaba | 6:9d393a9677f4 | 289 | #define REG_CORE_CHANNEL_COUNT7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT7 */ |
| Vkadaba | 6:9d393a9677f4 | 290 | #define REG_CORE_CHANNEL_COUNT8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT8 */ |
| Vkadaba | 6:9d393a9677f4 | 291 | #define REG_CORE_CHANNEL_COUNT9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT9 */ |
| Vkadaba | 6:9d393a9677f4 | 292 | #define REG_CORE_CHANNEL_COUNT10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT10 */ |
| Vkadaba | 8:2f2775c34640 | 293 | #define REG_CORE_CHANNEL_COUNT11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT11 */ |
| Vkadaba | 8:2f2775c34640 | 294 | #define REG_CORE_CHANNEL_COUNT12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT12 */ |
| Vkadaba | 6:9d393a9677f4 | 295 | #define REG_CORE_CHANNEL_COUNT0 0x00000090 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 296 | #define REG_CORE_CHANNEL_COUNT1 0x000000D0 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 297 | #define REG_CORE_CHANNEL_COUNT2 0x00000110 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 298 | #define REG_CORE_CHANNEL_COUNT3 0x00000150 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 299 | #define REG_CORE_CHANNEL_COUNT4 0x00000190 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 300 | #define REG_CORE_CHANNEL_COUNT5 0x000001D0 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 301 | #define REG_CORE_CHANNEL_COUNT6 0x00000210 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 302 | #define REG_CORE_CHANNEL_COUNT7 0x00000250 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 303 | #define REG_CORE_CHANNEL_COUNT8 0x00000290 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 304 | #define REG_CORE_CHANNEL_COUNT9 0x000002D0 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 305 | #define REG_CORE_CHANNEL_COUNT10 0x00000310 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 8:2f2775c34640 | 306 | #define REG_CORE_CHANNEL_COUNT11 0x00000350 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 8:2f2775c34640 | 307 | #define REG_CORE_CHANNEL_COUNT12 0x00000390 /* CORE Number of Channel Occurrences per Measurement Cycle */ |
| Vkadaba | 6:9d393a9677f4 | 308 | #define REG_CORE_CHANNEL_COUNTn(i) (REG_CORE_CHANNEL_COUNT0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 309 | #define REG_CORE_CHANNEL_COUNTn_COUNT 13 |
| Vkadaba | 6:9d393a9677f4 | 310 | #define REG_CORE_CHANNEL_OPTIONSn_RESET 0x00000000 /* Reset Value for Channel_Options[n] */ |
| Vkadaba | 6:9d393a9677f4 | 311 | #define REG_CORE_CHANNEL_OPTIONS0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS0 */ |
| Vkadaba | 6:9d393a9677f4 | 312 | #define REG_CORE_CHANNEL_OPTIONS1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS1 */ |
| Vkadaba | 6:9d393a9677f4 | 313 | #define REG_CORE_CHANNEL_OPTIONS2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS2 */ |
| Vkadaba | 6:9d393a9677f4 | 314 | #define REG_CORE_CHANNEL_OPTIONS3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS3 */ |
| Vkadaba | 6:9d393a9677f4 | 315 | #define REG_CORE_CHANNEL_OPTIONS4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS4 */ |
| Vkadaba | 6:9d393a9677f4 | 316 | #define REG_CORE_CHANNEL_OPTIONS5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS5 */ |
| Vkadaba | 6:9d393a9677f4 | 317 | #define REG_CORE_CHANNEL_OPTIONS6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS6 */ |
| Vkadaba | 6:9d393a9677f4 | 318 | #define REG_CORE_CHANNEL_OPTIONS7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS7 */ |
| Vkadaba | 6:9d393a9677f4 | 319 | #define REG_CORE_CHANNEL_OPTIONS8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS8 */ |
| Vkadaba | 6:9d393a9677f4 | 320 | #define REG_CORE_CHANNEL_OPTIONS9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS9 */ |
| Vkadaba | 6:9d393a9677f4 | 321 | #define REG_CORE_CHANNEL_OPTIONS10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS10 */ |
| Vkadaba | 8:2f2775c34640 | 322 | #define REG_CORE_CHANNEL_OPTIONS11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS11 */ |
| Vkadaba | 8:2f2775c34640 | 323 | #define REG_CORE_CHANNEL_OPTIONS12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS12 */ |
| Vkadaba | 32:52445bef314d | 324 | #define REG_CORE_CHANNEL_OPTIONS0 0x00000091 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 325 | #define REG_CORE_CHANNEL_OPTIONS1 0x000000D1 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 326 | #define REG_CORE_CHANNEL_OPTIONS2 0x00000111 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 327 | #define REG_CORE_CHANNEL_OPTIONS3 0x00000151 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 328 | #define REG_CORE_CHANNEL_OPTIONS4 0x00000191 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 329 | #define REG_CORE_CHANNEL_OPTIONS5 0x000001D1 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 330 | #define REG_CORE_CHANNEL_OPTIONS6 0x00000211 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 331 | #define REG_CORE_CHANNEL_OPTIONS7 0x00000251 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 332 | #define REG_CORE_CHANNEL_OPTIONS8 0x00000291 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 333 | #define REG_CORE_CHANNEL_OPTIONS9 0x000002D1 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 334 | #define REG_CORE_CHANNEL_OPTIONS10 0x00000311 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 335 | #define REG_CORE_CHANNEL_OPTIONS11 0x00000351 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 32:52445bef314d | 336 | #define REG_CORE_CHANNEL_OPTIONS12 0x00000391 /* CORE Position of Channel Within Sequence */ |
| Vkadaba | 6:9d393a9677f4 | 337 | #define REG_CORE_CHANNEL_OPTIONSn(i) (REG_CORE_CHANNEL_OPTIONS0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 338 | #define REG_CORE_CHANNEL_OPTIONSn_COUNT 13 |
| Vkadaba | 6:9d393a9677f4 | 339 | #define REG_CORE_SENSOR_TYPEn_RESET 0x00000000 /* Reset Value for Sensor_Type[n] */ |
| Vkadaba | 6:9d393a9677f4 | 340 | #define REG_CORE_SENSOR_TYPE0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE0 */ |
| Vkadaba | 6:9d393a9677f4 | 341 | #define REG_CORE_SENSOR_TYPE1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE1 */ |
| Vkadaba | 6:9d393a9677f4 | 342 | #define REG_CORE_SENSOR_TYPE2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE2 */ |
| Vkadaba | 6:9d393a9677f4 | 343 | #define REG_CORE_SENSOR_TYPE3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE3 */ |
| Vkadaba | 6:9d393a9677f4 | 344 | #define REG_CORE_SENSOR_TYPE4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE4 */ |
| Vkadaba | 6:9d393a9677f4 | 345 | #define REG_CORE_SENSOR_TYPE5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE5 */ |
| Vkadaba | 6:9d393a9677f4 | 346 | #define REG_CORE_SENSOR_TYPE6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE6 */ |
| Vkadaba | 6:9d393a9677f4 | 347 | #define REG_CORE_SENSOR_TYPE7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE7 */ |
| Vkadaba | 6:9d393a9677f4 | 348 | #define REG_CORE_SENSOR_TYPE8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE8 */ |
| Vkadaba | 6:9d393a9677f4 | 349 | #define REG_CORE_SENSOR_TYPE9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE9 */ |
| Vkadaba | 6:9d393a9677f4 | 350 | #define REG_CORE_SENSOR_TYPE10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE10 */ |
| Vkadaba | 8:2f2775c34640 | 351 | #define REG_CORE_SENSOR_TYPE11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE11 */ |
| Vkadaba | 8:2f2775c34640 | 352 | #define REG_CORE_SENSOR_TYPE12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE12 */ |
| Vkadaba | 6:9d393a9677f4 | 353 | #define REG_CORE_SENSOR_TYPE0 0x00000092 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 354 | #define REG_CORE_SENSOR_TYPE1 0x000000D2 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 355 | #define REG_CORE_SENSOR_TYPE2 0x00000112 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 356 | #define REG_CORE_SENSOR_TYPE3 0x00000152 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 357 | #define REG_CORE_SENSOR_TYPE4 0x00000192 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 358 | #define REG_CORE_SENSOR_TYPE5 0x000001D2 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 359 | #define REG_CORE_SENSOR_TYPE6 0x00000212 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 360 | #define REG_CORE_SENSOR_TYPE7 0x00000252 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 361 | #define REG_CORE_SENSOR_TYPE8 0x00000292 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 362 | #define REG_CORE_SENSOR_TYPE9 0x000002D2 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 363 | #define REG_CORE_SENSOR_TYPE10 0x00000312 /* CORE Sensor Select */ |
| Vkadaba | 8:2f2775c34640 | 364 | #define REG_CORE_SENSOR_TYPE11 0x00000352 /* CORE Sensor Select */ |
| Vkadaba | 8:2f2775c34640 | 365 | #define REG_CORE_SENSOR_TYPE12 0x00000392 /* CORE Sensor Select */ |
| Vkadaba | 6:9d393a9677f4 | 366 | #define REG_CORE_SENSOR_TYPEn(i) (REG_CORE_SENSOR_TYPE0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 367 | #define REG_CORE_SENSOR_TYPEn_COUNT 13 |
| Vkadaba | 6:9d393a9677f4 | 368 | #define REG_CORE_SENSOR_DETAILSn_RESET 0x000000F0 /* Reset Value for Sensor_Details[n] */ |
| Vkadaba | 6:9d393a9677f4 | 369 | #define REG_CORE_SENSOR_DETAILS0_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS0 */ |
| Vkadaba | 6:9d393a9677f4 | 370 | #define REG_CORE_SENSOR_DETAILS1_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS1 */ |
| Vkadaba | 6:9d393a9677f4 | 371 | #define REG_CORE_SENSOR_DETAILS2_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS2 */ |
| Vkadaba | 6:9d393a9677f4 | 372 | #define REG_CORE_SENSOR_DETAILS3_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS3 */ |
| Vkadaba | 6:9d393a9677f4 | 373 | #define REG_CORE_SENSOR_DETAILS4_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS4 */ |
| Vkadaba | 6:9d393a9677f4 | 374 | #define REG_CORE_SENSOR_DETAILS5_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS5 */ |
| Vkadaba | 6:9d393a9677f4 | 375 | #define REG_CORE_SENSOR_DETAILS6_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS6 */ |
| Vkadaba | 6:9d393a9677f4 | 376 | #define REG_CORE_SENSOR_DETAILS7_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS7 */ |
| Vkadaba | 6:9d393a9677f4 | 377 | #define REG_CORE_SENSOR_DETAILS8_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS8 */ |
| Vkadaba | 6:9d393a9677f4 | 378 | #define REG_CORE_SENSOR_DETAILS9_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS9 */ |
| Vkadaba | 6:9d393a9677f4 | 379 | #define REG_CORE_SENSOR_DETAILS10_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS10 */ |
| Vkadaba | 8:2f2775c34640 | 380 | #define REG_CORE_SENSOR_DETAILS11_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS11 */ |
| Vkadaba | 8:2f2775c34640 | 381 | #define REG_CORE_SENSOR_DETAILS12_RESET 0x000000F0 /* Reset Value for REG_CORE_SENSOR_DETAILS12 */ |
| Vkadaba | 6:9d393a9677f4 | 382 | #define REG_CORE_SENSOR_DETAILS0 0x00000094 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 383 | #define REG_CORE_SENSOR_DETAILS1 0x000000D4 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 384 | #define REG_CORE_SENSOR_DETAILS2 0x00000114 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 385 | #define REG_CORE_SENSOR_DETAILS3 0x00000154 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 386 | #define REG_CORE_SENSOR_DETAILS4 0x00000194 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 387 | #define REG_CORE_SENSOR_DETAILS5 0x000001D4 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 388 | #define REG_CORE_SENSOR_DETAILS6 0x00000214 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 389 | #define REG_CORE_SENSOR_DETAILS7 0x00000254 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 390 | #define REG_CORE_SENSOR_DETAILS8 0x00000294 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 391 | #define REG_CORE_SENSOR_DETAILS9 0x000002D4 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 392 | #define REG_CORE_SENSOR_DETAILS10 0x00000314 /* CORE Sensor Details */ |
| Vkadaba | 8:2f2775c34640 | 393 | #define REG_CORE_SENSOR_DETAILS11 0x00000354 /* CORE Sensor Details */ |
| Vkadaba | 8:2f2775c34640 | 394 | #define REG_CORE_SENSOR_DETAILS12 0x00000394 /* CORE Sensor Details */ |
| Vkadaba | 6:9d393a9677f4 | 395 | #define REG_CORE_SENSOR_DETAILSn(i) (REG_CORE_SENSOR_DETAILS0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 396 | #define REG_CORE_SENSOR_DETAILSn_COUNT 13 |
| Vkadaba | 6:9d393a9677f4 | 397 | #define REG_CORE_CHANNEL_EXCITATIONn_RESET 0x00000000 /* Reset Value for Channel_Excitation[n] */ |
| Vkadaba | 6:9d393a9677f4 | 398 | #define REG_CORE_CHANNEL_EXCITATION0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION0 */ |
| Vkadaba | 6:9d393a9677f4 | 399 | #define REG_CORE_CHANNEL_EXCITATION1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION1 */ |
| Vkadaba | 6:9d393a9677f4 | 400 | #define REG_CORE_CHANNEL_EXCITATION2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION2 */ |
| Vkadaba | 6:9d393a9677f4 | 401 | #define REG_CORE_CHANNEL_EXCITATION3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION3 */ |
| Vkadaba | 6:9d393a9677f4 | 402 | #define REG_CORE_CHANNEL_EXCITATION4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION4 */ |
| Vkadaba | 6:9d393a9677f4 | 403 | #define REG_CORE_CHANNEL_EXCITATION5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION5 */ |
| Vkadaba | 6:9d393a9677f4 | 404 | #define REG_CORE_CHANNEL_EXCITATION6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION6 */ |
| Vkadaba | 6:9d393a9677f4 | 405 | #define REG_CORE_CHANNEL_EXCITATION7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION7 */ |
| Vkadaba | 6:9d393a9677f4 | 406 | #define REG_CORE_CHANNEL_EXCITATION8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION8 */ |
| Vkadaba | 6:9d393a9677f4 | 407 | #define REG_CORE_CHANNEL_EXCITATION9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION9 */ |
| Vkadaba | 6:9d393a9677f4 | 408 | #define REG_CORE_CHANNEL_EXCITATION10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION10 */ |
| Vkadaba | 8:2f2775c34640 | 409 | #define REG_CORE_CHANNEL_EXCITATION11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION11 */ |
| Vkadaba | 8:2f2775c34640 | 410 | #define REG_CORE_CHANNEL_EXCITATION12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION12 */ |
| Vkadaba | 6:9d393a9677f4 | 411 | #define REG_CORE_CHANNEL_EXCITATION0 0x00000098 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 412 | #define REG_CORE_CHANNEL_EXCITATION1 0x000000D8 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 413 | #define REG_CORE_CHANNEL_EXCITATION2 0x00000118 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 414 | #define REG_CORE_CHANNEL_EXCITATION3 0x00000158 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 415 | #define REG_CORE_CHANNEL_EXCITATION4 0x00000198 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 416 | #define REG_CORE_CHANNEL_EXCITATION5 0x000001D8 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 417 | #define REG_CORE_CHANNEL_EXCITATION6 0x00000218 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 418 | #define REG_CORE_CHANNEL_EXCITATION7 0x00000258 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 419 | #define REG_CORE_CHANNEL_EXCITATION8 0x00000298 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 420 | #define REG_CORE_CHANNEL_EXCITATION9 0x000002D8 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 421 | #define REG_CORE_CHANNEL_EXCITATION10 0x00000318 /* CORE Excitation Current */ |
| Vkadaba | 8:2f2775c34640 | 422 | #define REG_CORE_CHANNEL_EXCITATION11 0x00000358 /* CORE Excitation Current */ |
| Vkadaba | 8:2f2775c34640 | 423 | #define REG_CORE_CHANNEL_EXCITATION12 0x00000398 /* CORE Excitation Current */ |
| Vkadaba | 6:9d393a9677f4 | 424 | #define REG_CORE_CHANNEL_EXCITATIONn(i) (REG_CORE_CHANNEL_EXCITATION0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 425 | #define REG_CORE_CHANNEL_EXCITATIONn_COUNT 13 |
| Vkadaba | 6:9d393a9677f4 | 426 | #define REG_CORE_SETTLING_TIMEn_RESET 0x00000000 /* Reset Value for Settling_Time[n] */ |
| Vkadaba | 6:9d393a9677f4 | 427 | #define REG_CORE_SETTLING_TIME0_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME0 */ |
| Vkadaba | 6:9d393a9677f4 | 428 | #define REG_CORE_SETTLING_TIME1_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME1 */ |
| Vkadaba | 6:9d393a9677f4 | 429 | #define REG_CORE_SETTLING_TIME2_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME2 */ |
| Vkadaba | 6:9d393a9677f4 | 430 | #define REG_CORE_SETTLING_TIME3_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME3 */ |
| Vkadaba | 6:9d393a9677f4 | 431 | #define REG_CORE_SETTLING_TIME4_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME4 */ |
| Vkadaba | 6:9d393a9677f4 | 432 | #define REG_CORE_SETTLING_TIME5_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME5 */ |
| Vkadaba | 6:9d393a9677f4 | 433 | #define REG_CORE_SETTLING_TIME6_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME6 */ |
| Vkadaba | 6:9d393a9677f4 | 434 | #define REG_CORE_SETTLING_TIME7_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME7 */ |
| Vkadaba | 6:9d393a9677f4 | 435 | #define REG_CORE_SETTLING_TIME8_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME8 */ |
| Vkadaba | 6:9d393a9677f4 | 436 | #define REG_CORE_SETTLING_TIME9_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME9 */ |
| Vkadaba | 6:9d393a9677f4 | 437 | #define REG_CORE_SETTLING_TIME10_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME10 */ |
| Vkadaba | 8:2f2775c34640 | 438 | #define REG_CORE_SETTLING_TIME11_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME11 */ |
| Vkadaba | 8:2f2775c34640 | 439 | #define REG_CORE_SETTLING_TIME12_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME12 */ |
| Vkadaba | 6:9d393a9677f4 | 440 | #define REG_CORE_SETTLING_TIME0 0x0000009A /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 441 | #define REG_CORE_SETTLING_TIME1 0x000000DA /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 442 | #define REG_CORE_SETTLING_TIME2 0x0000011A /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 443 | #define REG_CORE_SETTLING_TIME3 0x0000015A /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 444 | #define REG_CORE_SETTLING_TIME4 0x0000019A /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 445 | #define REG_CORE_SETTLING_TIME5 0x000001DA /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 446 | #define REG_CORE_SETTLING_TIME6 0x0000021A /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 447 | #define REG_CORE_SETTLING_TIME7 0x0000025A /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 448 | #define REG_CORE_SETTLING_TIME8 0x0000029A /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 449 | #define REG_CORE_SETTLING_TIME9 0x000002DA /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 450 | #define REG_CORE_SETTLING_TIME10 0x0000031A /* CORE Settling Time */ |
| Vkadaba | 8:2f2775c34640 | 451 | #define REG_CORE_SETTLING_TIME11 0x0000035A /* CORE Settling Time */ |
| Vkadaba | 8:2f2775c34640 | 452 | #define REG_CORE_SETTLING_TIME12 0x0000039A /* CORE Settling Time */ |
| Vkadaba | 6:9d393a9677f4 | 453 | #define REG_CORE_SETTLING_TIMEn(i) (REG_CORE_SETTLING_TIME0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 454 | #define REG_CORE_SETTLING_TIMEn_COUNT 13 |
| Vkadaba | 6:9d393a9677f4 | 455 | #define REG_CORE_MEASUREMENT_SETUPn_RESET 0x00000000 /* Reset Value for Measurement_Setup[n] */ |
| Vkadaba | 6:9d393a9677f4 | 456 | #define REG_CORE_MEASUREMENT_SETUP0_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP0 */ |
| Vkadaba | 6:9d393a9677f4 | 457 | #define REG_CORE_MEASUREMENT_SETUP1_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP1 */ |
| Vkadaba | 6:9d393a9677f4 | 458 | #define REG_CORE_MEASUREMENT_SETUP2_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP2 */ |
| Vkadaba | 6:9d393a9677f4 | 459 | #define REG_CORE_MEASUREMENT_SETUP3_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP3 */ |
| Vkadaba | 6:9d393a9677f4 | 460 | #define REG_CORE_MEASUREMENT_SETUP4_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP4 */ |
| Vkadaba | 6:9d393a9677f4 | 461 | #define REG_CORE_MEASUREMENT_SETUP5_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP5 */ |
| Vkadaba | 6:9d393a9677f4 | 462 | #define REG_CORE_MEASUREMENT_SETUP6_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP6 */ |
| Vkadaba | 6:9d393a9677f4 | 463 | #define REG_CORE_MEASUREMENT_SETUP7_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP7 */ |
| Vkadaba | 6:9d393a9677f4 | 464 | #define REG_CORE_MEASUREMENT_SETUP8_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP8 */ |
| Vkadaba | 6:9d393a9677f4 | 465 | #define REG_CORE_MEASUREMENT_SETUP9_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP9 */ |
| Vkadaba | 6:9d393a9677f4 | 466 | #define REG_CORE_MEASUREMENT_SETUP10_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP10 */ |
| Vkadaba | 8:2f2775c34640 | 467 | #define REG_CORE_MEASUREMENT_SETUP11_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP11 */ |
| Vkadaba | 8:2f2775c34640 | 468 | #define REG_CORE_MEASUREMENT_SETUP12_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP12 */ |
| Vkadaba | 32:52445bef314d | 469 | #define REG_CORE_MEASUREMENT_SETUP0 0x0000009C /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 470 | #define REG_CORE_MEASUREMENT_SETUP1 0x000000DC /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 471 | #define REG_CORE_MEASUREMENT_SETUP2 0x0000011C /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 472 | #define REG_CORE_MEASUREMENT_SETUP3 0x0000015C /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 473 | #define REG_CORE_MEASUREMENT_SETUP4 0x0000019C /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 474 | #define REG_CORE_MEASUREMENT_SETUP5 0x000001DC /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 475 | #define REG_CORE_MEASUREMENT_SETUP6 0x0000021C /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 476 | #define REG_CORE_MEASUREMENT_SETUP7 0x0000025C /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 477 | #define REG_CORE_MEASUREMENT_SETUP8 0x0000029C /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 478 | #define REG_CORE_MEASUREMENT_SETUP9 0x000002DC /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 479 | #define REG_CORE_MEASUREMENT_SETUP10 0x0000031C /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 480 | #define REG_CORE_MEASUREMENT_SETUP11 0x0000035C /* CORE ADC Measurement Setup */ |
| Vkadaba | 32:52445bef314d | 481 | #define REG_CORE_MEASUREMENT_SETUP12 0x0000039C /* CORE ADC Measurement Setup */ |
| Vkadaba | 6:9d393a9677f4 | 482 | #define REG_CORE_MEASUREMENT_SETUPn(i) (REG_CORE_MEASUREMENT_SETUP0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 483 | #define REG_CORE_MEASUREMENT_SETUPn_COUNT 13 |
| Vkadaba | 32:52445bef314d | 484 | #define REG_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x7F800000 /* Reset Value for High_Threshold_Limit[n] */ |
| Vkadaba | 32:52445bef314d | 485 | #define REG_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT0 */ |
| Vkadaba | 32:52445bef314d | 486 | #define REG_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT1 */ |
| Vkadaba | 32:52445bef314d | 487 | #define REG_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT2 */ |
| Vkadaba | 32:52445bef314d | 488 | #define REG_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT3 */ |
| Vkadaba | 32:52445bef314d | 489 | #define REG_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT4 */ |
| Vkadaba | 32:52445bef314d | 490 | #define REG_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT5 */ |
| Vkadaba | 32:52445bef314d | 491 | #define REG_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT6 */ |
| Vkadaba | 32:52445bef314d | 492 | #define REG_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT7 */ |
| Vkadaba | 32:52445bef314d | 493 | #define REG_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT8 */ |
| Vkadaba | 32:52445bef314d | 494 | #define REG_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT9 */ |
| Vkadaba | 32:52445bef314d | 495 | #define REG_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT10 */ |
| Vkadaba | 32:52445bef314d | 496 | #define REG_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT11 */ |
| Vkadaba | 32:52445bef314d | 497 | #define REG_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT12 */ |
| Vkadaba | 6:9d393a9677f4 | 498 | #define REG_CORE_HIGH_THRESHOLD_LIMIT0 0x000000A0 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 499 | #define REG_CORE_HIGH_THRESHOLD_LIMIT1 0x000000E0 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 500 | #define REG_CORE_HIGH_THRESHOLD_LIMIT2 0x00000120 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 501 | #define REG_CORE_HIGH_THRESHOLD_LIMIT3 0x00000160 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 502 | #define REG_CORE_HIGH_THRESHOLD_LIMIT4 0x000001A0 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 503 | #define REG_CORE_HIGH_THRESHOLD_LIMIT5 0x000001E0 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 504 | #define REG_CORE_HIGH_THRESHOLD_LIMIT6 0x00000220 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 505 | #define REG_CORE_HIGH_THRESHOLD_LIMIT7 0x00000260 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 506 | #define REG_CORE_HIGH_THRESHOLD_LIMIT8 0x000002A0 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 507 | #define REG_CORE_HIGH_THRESHOLD_LIMIT9 0x000002E0 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 508 | #define REG_CORE_HIGH_THRESHOLD_LIMIT10 0x00000320 /* CORE High Threshold */ |
| Vkadaba | 8:2f2775c34640 | 509 | #define REG_CORE_HIGH_THRESHOLD_LIMIT11 0x00000360 /* CORE High Threshold */ |
| Vkadaba | 8:2f2775c34640 | 510 | #define REG_CORE_HIGH_THRESHOLD_LIMIT12 0x000003A0 /* CORE High Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 511 | #define REG_CORE_HIGH_THRESHOLD_LIMITn(i) (REG_CORE_HIGH_THRESHOLD_LIMIT0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 512 | #define REG_CORE_HIGH_THRESHOLD_LIMITn_COUNT 13 |
| Vkadaba | 32:52445bef314d | 513 | #define REG_CORE_LOW_THRESHOLD_LIMITn_RESET 0xFF800000 /* Reset Value for Low_Threshold_Limit[n] */ |
| Vkadaba | 32:52445bef314d | 514 | #define REG_CORE_LOW_THRESHOLD_LIMIT0_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT0 */ |
| Vkadaba | 32:52445bef314d | 515 | #define REG_CORE_LOW_THRESHOLD_LIMIT1_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT1 */ |
| Vkadaba | 32:52445bef314d | 516 | #define REG_CORE_LOW_THRESHOLD_LIMIT2_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT2 */ |
| Vkadaba | 32:52445bef314d | 517 | #define REG_CORE_LOW_THRESHOLD_LIMIT3_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT3 */ |
| Vkadaba | 32:52445bef314d | 518 | #define REG_CORE_LOW_THRESHOLD_LIMIT4_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT4 */ |
| Vkadaba | 32:52445bef314d | 519 | #define REG_CORE_LOW_THRESHOLD_LIMIT5_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT5 */ |
| Vkadaba | 32:52445bef314d | 520 | #define REG_CORE_LOW_THRESHOLD_LIMIT6_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT6 */ |
| Vkadaba | 32:52445bef314d | 521 | #define REG_CORE_LOW_THRESHOLD_LIMIT7_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT7 */ |
| Vkadaba | 32:52445bef314d | 522 | #define REG_CORE_LOW_THRESHOLD_LIMIT8_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT8 */ |
| Vkadaba | 32:52445bef314d | 523 | #define REG_CORE_LOW_THRESHOLD_LIMIT9_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT9 */ |
| Vkadaba | 32:52445bef314d | 524 | #define REG_CORE_LOW_THRESHOLD_LIMIT10_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT10 */ |
| Vkadaba | 32:52445bef314d | 525 | #define REG_CORE_LOW_THRESHOLD_LIMIT11_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT11 */ |
| Vkadaba | 32:52445bef314d | 526 | #define REG_CORE_LOW_THRESHOLD_LIMIT12_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT12 */ |
| Vkadaba | 6:9d393a9677f4 | 527 | #define REG_CORE_LOW_THRESHOLD_LIMIT0 0x000000A4 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 528 | #define REG_CORE_LOW_THRESHOLD_LIMIT1 0x000000E4 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 529 | #define REG_CORE_LOW_THRESHOLD_LIMIT2 0x00000124 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 530 | #define REG_CORE_LOW_THRESHOLD_LIMIT3 0x00000164 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 531 | #define REG_CORE_LOW_THRESHOLD_LIMIT4 0x000001A4 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 532 | #define REG_CORE_LOW_THRESHOLD_LIMIT5 0x000001E4 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 533 | #define REG_CORE_LOW_THRESHOLD_LIMIT6 0x00000224 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 534 | #define REG_CORE_LOW_THRESHOLD_LIMIT7 0x00000264 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 535 | #define REG_CORE_LOW_THRESHOLD_LIMIT8 0x000002A4 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 536 | #define REG_CORE_LOW_THRESHOLD_LIMIT9 0x000002E4 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 537 | #define REG_CORE_LOW_THRESHOLD_LIMIT10 0x00000324 /* CORE Low Threshold */ |
| Vkadaba | 8:2f2775c34640 | 538 | #define REG_CORE_LOW_THRESHOLD_LIMIT11 0x00000364 /* CORE Low Threshold */ |
| Vkadaba | 8:2f2775c34640 | 539 | #define REG_CORE_LOW_THRESHOLD_LIMIT12 0x000003A4 /* CORE Low Threshold */ |
| Vkadaba | 6:9d393a9677f4 | 540 | #define REG_CORE_LOW_THRESHOLD_LIMITn(i) (REG_CORE_LOW_THRESHOLD_LIMIT0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 541 | #define REG_CORE_LOW_THRESHOLD_LIMITn_COUNT 13 |
| Vkadaba | 6:9d393a9677f4 | 542 | #define REG_CORE_SENSOR_OFFSETn_RESET 0x00000000 /* Reset Value for Sensor_Offset[n] */ |
| Vkadaba | 6:9d393a9677f4 | 543 | #define REG_CORE_SENSOR_OFFSET0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET0 */ |
| Vkadaba | 6:9d393a9677f4 | 544 | #define REG_CORE_SENSOR_OFFSET1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET1 */ |
| Vkadaba | 6:9d393a9677f4 | 545 | #define REG_CORE_SENSOR_OFFSET2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET2 */ |
| Vkadaba | 6:9d393a9677f4 | 546 | #define REG_CORE_SENSOR_OFFSET3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET3 */ |
| Vkadaba | 6:9d393a9677f4 | 547 | #define REG_CORE_SENSOR_OFFSET4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET4 */ |
| Vkadaba | 6:9d393a9677f4 | 548 | #define REG_CORE_SENSOR_OFFSET5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET5 */ |
| Vkadaba | 6:9d393a9677f4 | 549 | #define REG_CORE_SENSOR_OFFSET6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET6 */ |
| Vkadaba | 6:9d393a9677f4 | 550 | #define REG_CORE_SENSOR_OFFSET7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET7 */ |
| Vkadaba | 6:9d393a9677f4 | 551 | #define REG_CORE_SENSOR_OFFSET8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET8 */ |
| Vkadaba | 6:9d393a9677f4 | 552 | #define REG_CORE_SENSOR_OFFSET9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET9 */ |
| Vkadaba | 6:9d393a9677f4 | 553 | #define REG_CORE_SENSOR_OFFSET10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET10 */ |
| Vkadaba | 8:2f2775c34640 | 554 | #define REG_CORE_SENSOR_OFFSET11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET11 */ |
| Vkadaba | 8:2f2775c34640 | 555 | #define REG_CORE_SENSOR_OFFSET12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_OFFSET12 */ |
| Vkadaba | 6:9d393a9677f4 | 556 | #define REG_CORE_SENSOR_OFFSET0 0x000000A8 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 557 | #define REG_CORE_SENSOR_OFFSET1 0x000000E8 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 558 | #define REG_CORE_SENSOR_OFFSET2 0x00000128 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 559 | #define REG_CORE_SENSOR_OFFSET3 0x00000168 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 560 | #define REG_CORE_SENSOR_OFFSET4 0x000001A8 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 561 | #define REG_CORE_SENSOR_OFFSET5 0x000001E8 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 562 | #define REG_CORE_SENSOR_OFFSET6 0x00000228 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 563 | #define REG_CORE_SENSOR_OFFSET7 0x00000268 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 564 | #define REG_CORE_SENSOR_OFFSET8 0x000002A8 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 565 | #define REG_CORE_SENSOR_OFFSET9 0x000002E8 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 566 | #define REG_CORE_SENSOR_OFFSET10 0x00000328 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 8:2f2775c34640 | 567 | #define REG_CORE_SENSOR_OFFSET11 0x00000368 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 8:2f2775c34640 | 568 | #define REG_CORE_SENSOR_OFFSET12 0x000003A8 /* CORE Sensor Offset Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 569 | #define REG_CORE_SENSOR_OFFSETn(i) (REG_CORE_SENSOR_OFFSET0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 570 | #define REG_CORE_SENSOR_OFFSETn_COUNT 13 |
| Vkadaba | 32:52445bef314d | 571 | #define REG_CORE_SENSOR_GAINn_RESET 0x3F800000 /* Reset Value for Sensor_Gain[n] */ |
| Vkadaba | 32:52445bef314d | 572 | #define REG_CORE_SENSOR_GAIN0_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN0 */ |
| Vkadaba | 32:52445bef314d | 573 | #define REG_CORE_SENSOR_GAIN1_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN1 */ |
| Vkadaba | 32:52445bef314d | 574 | #define REG_CORE_SENSOR_GAIN2_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN2 */ |
| Vkadaba | 32:52445bef314d | 575 | #define REG_CORE_SENSOR_GAIN3_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN3 */ |
| Vkadaba | 32:52445bef314d | 576 | #define REG_CORE_SENSOR_GAIN4_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN4 */ |
| Vkadaba | 32:52445bef314d | 577 | #define REG_CORE_SENSOR_GAIN5_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN5 */ |
| Vkadaba | 32:52445bef314d | 578 | #define REG_CORE_SENSOR_GAIN6_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN6 */ |
| Vkadaba | 32:52445bef314d | 579 | #define REG_CORE_SENSOR_GAIN7_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN7 */ |
| Vkadaba | 32:52445bef314d | 580 | #define REG_CORE_SENSOR_GAIN8_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN8 */ |
| Vkadaba | 32:52445bef314d | 581 | #define REG_CORE_SENSOR_GAIN9_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN9 */ |
| Vkadaba | 32:52445bef314d | 582 | #define REG_CORE_SENSOR_GAIN10_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN10 */ |
| Vkadaba | 32:52445bef314d | 583 | #define REG_CORE_SENSOR_GAIN11_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN11 */ |
| Vkadaba | 32:52445bef314d | 584 | #define REG_CORE_SENSOR_GAIN12_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN12 */ |
| Vkadaba | 6:9d393a9677f4 | 585 | #define REG_CORE_SENSOR_GAIN0 0x000000AC /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 586 | #define REG_CORE_SENSOR_GAIN1 0x000000EC /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 587 | #define REG_CORE_SENSOR_GAIN2 0x0000012C /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 588 | #define REG_CORE_SENSOR_GAIN3 0x0000016C /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 589 | #define REG_CORE_SENSOR_GAIN4 0x000001AC /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 590 | #define REG_CORE_SENSOR_GAIN5 0x000001EC /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 591 | #define REG_CORE_SENSOR_GAIN6 0x0000022C /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 592 | #define REG_CORE_SENSOR_GAIN7 0x0000026C /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 593 | #define REG_CORE_SENSOR_GAIN8 0x000002AC /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 594 | #define REG_CORE_SENSOR_GAIN9 0x000002EC /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 595 | #define REG_CORE_SENSOR_GAIN10 0x0000032C /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 8:2f2775c34640 | 596 | #define REG_CORE_SENSOR_GAIN11 0x0000036C /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 8:2f2775c34640 | 597 | #define REG_CORE_SENSOR_GAIN12 0x000003AC /* CORE Sensor Gain Adjustment */ |
| Vkadaba | 6:9d393a9677f4 | 598 | #define REG_CORE_SENSOR_GAINn(i) (REG_CORE_SENSOR_GAIN0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 599 | #define REG_CORE_SENSOR_GAINn_COUNT 13 |
| Vkadaba | 6:9d393a9677f4 | 600 | #define REG_CORE_CHANNEL_SKIPn_RESET 0x00000000 /* Reset Value for Channel_Skip[n] */ |
| Vkadaba | 6:9d393a9677f4 | 601 | #define REG_CORE_CHANNEL_SKIP0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP0 */ |
| Vkadaba | 6:9d393a9677f4 | 602 | #define REG_CORE_CHANNEL_SKIP1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP1 */ |
| Vkadaba | 6:9d393a9677f4 | 603 | #define REG_CORE_CHANNEL_SKIP2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP2 */ |
| Vkadaba | 6:9d393a9677f4 | 604 | #define REG_CORE_CHANNEL_SKIP3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP3 */ |
| Vkadaba | 6:9d393a9677f4 | 605 | #define REG_CORE_CHANNEL_SKIP4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP4 */ |
| Vkadaba | 6:9d393a9677f4 | 606 | #define REG_CORE_CHANNEL_SKIP5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP5 */ |
| Vkadaba | 6:9d393a9677f4 | 607 | #define REG_CORE_CHANNEL_SKIP6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP6 */ |
| Vkadaba | 6:9d393a9677f4 | 608 | #define REG_CORE_CHANNEL_SKIP7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP7 */ |
| Vkadaba | 6:9d393a9677f4 | 609 | #define REG_CORE_CHANNEL_SKIP8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP8 */ |
| Vkadaba | 6:9d393a9677f4 | 610 | #define REG_CORE_CHANNEL_SKIP9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP9 */ |
| Vkadaba | 6:9d393a9677f4 | 611 | #define REG_CORE_CHANNEL_SKIP10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP10 */ |
| Vkadaba | 8:2f2775c34640 | 612 | #define REG_CORE_CHANNEL_SKIP11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP11 */ |
| Vkadaba | 8:2f2775c34640 | 613 | #define REG_CORE_CHANNEL_SKIP12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP12 */ |
| Vkadaba | 6:9d393a9677f4 | 614 | #define REG_CORE_CHANNEL_SKIP0 0x000000B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 615 | #define REG_CORE_CHANNEL_SKIP1 0x000000F2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 616 | #define REG_CORE_CHANNEL_SKIP2 0x00000132 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 617 | #define REG_CORE_CHANNEL_SKIP3 0x00000172 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 618 | #define REG_CORE_CHANNEL_SKIP4 0x000001B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 619 | #define REG_CORE_CHANNEL_SKIP5 0x000001F2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 620 | #define REG_CORE_CHANNEL_SKIP6 0x00000232 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 621 | #define REG_CORE_CHANNEL_SKIP7 0x00000272 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 622 | #define REG_CORE_CHANNEL_SKIP8 0x000002B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 623 | #define REG_CORE_CHANNEL_SKIP9 0x000002F2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 624 | #define REG_CORE_CHANNEL_SKIP10 0x00000332 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 8:2f2775c34640 | 625 | #define REG_CORE_CHANNEL_SKIP11 0x00000372 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 8:2f2775c34640 | 626 | #define REG_CORE_CHANNEL_SKIP12 0x000003B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 627 | #define REG_CORE_CHANNEL_SKIPn(i) (REG_CORE_CHANNEL_SKIP0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 628 | #define REG_CORE_CHANNEL_SKIPn_COUNT 13 |
| Vkadaba | 5:0728bde67bdb | 629 | #define REG_CORE_DIGITAL_SENSOR_CONFIGn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Config[n] */ |
| Vkadaba | 5:0728bde67bdb | 630 | #define REG_CORE_DIGITAL_SENSOR_CONFIG0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG0 */ |
| Vkadaba | 5:0728bde67bdb | 631 | #define REG_CORE_DIGITAL_SENSOR_CONFIG1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG1 */ |
| Vkadaba | 5:0728bde67bdb | 632 | #define REG_CORE_DIGITAL_SENSOR_CONFIG2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG2 */ |
| Vkadaba | 5:0728bde67bdb | 633 | #define REG_CORE_DIGITAL_SENSOR_CONFIG3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG3 */ |
| Vkadaba | 5:0728bde67bdb | 634 | #define REG_CORE_DIGITAL_SENSOR_CONFIG4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG4 */ |
| Vkadaba | 5:0728bde67bdb | 635 | #define REG_CORE_DIGITAL_SENSOR_CONFIG5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG5 */ |
| Vkadaba | 5:0728bde67bdb | 636 | #define REG_CORE_DIGITAL_SENSOR_CONFIG6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG6 */ |
| Vkadaba | 5:0728bde67bdb | 637 | #define REG_CORE_DIGITAL_SENSOR_CONFIG7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG7 */ |
| Vkadaba | 5:0728bde67bdb | 638 | #define REG_CORE_DIGITAL_SENSOR_CONFIG8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG8 */ |
| Vkadaba | 5:0728bde67bdb | 639 | #define REG_CORE_DIGITAL_SENSOR_CONFIG9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG9 */ |
| Vkadaba | 5:0728bde67bdb | 640 | #define REG_CORE_DIGITAL_SENSOR_CONFIG10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG10 */ |
| Vkadaba | 8:2f2775c34640 | 641 | #define REG_CORE_DIGITAL_SENSOR_CONFIG11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG11 */ |
| Vkadaba | 8:2f2775c34640 | 642 | #define REG_CORE_DIGITAL_SENSOR_CONFIG12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG12 */ |
| Vkadaba | 6:9d393a9677f4 | 643 | #define REG_CORE_DIGITAL_SENSOR_CONFIG0 0x000000BC /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 644 | #define REG_CORE_DIGITAL_SENSOR_CONFIG1 0x000000FC /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 645 | #define REG_CORE_DIGITAL_SENSOR_CONFIG2 0x0000013C /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 646 | #define REG_CORE_DIGITAL_SENSOR_CONFIG3 0x0000017C /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 647 | #define REG_CORE_DIGITAL_SENSOR_CONFIG4 0x000001BC /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 648 | #define REG_CORE_DIGITAL_SENSOR_CONFIG5 0x000001FC /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 649 | #define REG_CORE_DIGITAL_SENSOR_CONFIG6 0x0000023C /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 650 | #define REG_CORE_DIGITAL_SENSOR_CONFIG7 0x0000027C /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 651 | #define REG_CORE_DIGITAL_SENSOR_CONFIG8 0x000002BC /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 652 | #define REG_CORE_DIGITAL_SENSOR_CONFIG9 0x000002FC /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 653 | #define REG_CORE_DIGITAL_SENSOR_CONFIG10 0x0000033C /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 8:2f2775c34640 | 654 | #define REG_CORE_DIGITAL_SENSOR_CONFIG11 0x0000037C /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 8:2f2775c34640 | 655 | #define REG_CORE_DIGITAL_SENSOR_CONFIG12 0x000003BC /* CORE Digital Sensor Data Coding */ |
| Vkadaba | 6:9d393a9677f4 | 656 | #define REG_CORE_DIGITAL_SENSOR_CONFIGn(i) (REG_CORE_DIGITAL_SENSOR_CONFIG0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 657 | #define REG_CORE_DIGITAL_SENSOR_CONFIGn_COUNT 13 |
| Vkadaba | 5:0728bde67bdb | 658 | #define REG_CORE_DIGITAL_SENSOR_ADDRESSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Address[n] */ |
| Vkadaba | 5:0728bde67bdb | 659 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS0 */ |
| Vkadaba | 5:0728bde67bdb | 660 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS1 */ |
| Vkadaba | 5:0728bde67bdb | 661 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS2 */ |
| Vkadaba | 5:0728bde67bdb | 662 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS3 */ |
| Vkadaba | 5:0728bde67bdb | 663 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS4 */ |
| Vkadaba | 5:0728bde67bdb | 664 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS5 */ |
| Vkadaba | 5:0728bde67bdb | 665 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS6 */ |
| Vkadaba | 5:0728bde67bdb | 666 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS7 */ |
| Vkadaba | 5:0728bde67bdb | 667 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS8 */ |
| Vkadaba | 5:0728bde67bdb | 668 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS9 */ |
| Vkadaba | 5:0728bde67bdb | 669 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS10 */ |
| Vkadaba | 8:2f2775c34640 | 670 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS11 */ |
| Vkadaba | 8:2f2775c34640 | 671 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS12 */ |
| Vkadaba | 6:9d393a9677f4 | 672 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS0 0x000000BE /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 673 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS1 0x000000FE /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 674 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS2 0x0000013E /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 675 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS3 0x0000017E /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 676 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS4 0x000001BE /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 677 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS5 0x000001FE /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 678 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS6 0x0000023E /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 679 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS7 0x0000027E /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 680 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS8 0x000002BE /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 681 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS9 0x000002FE /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 682 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS10 0x0000033E /* CORE Sensor Address */ |
| Vkadaba | 8:2f2775c34640 | 683 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS11 0x0000037E /* CORE Sensor Address */ |
| Vkadaba | 8:2f2775c34640 | 684 | #define REG_CORE_DIGITAL_SENSOR_ADDRESS12 0x000003BE /* CORE Sensor Address */ |
| Vkadaba | 6:9d393a9677f4 | 685 | #define REG_CORE_DIGITAL_SENSOR_ADDRESSn(i) (REG_CORE_DIGITAL_SENSOR_ADDRESS0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 686 | #define REG_CORE_DIGITAL_SENSOR_ADDRESSn_COUNT 13 |
| Vkadaba | 5:0728bde67bdb | 687 | #define REG_CORE_DIGITAL_SENSOR_COMMSn_RESET 0x00000006 /* Reset Value for Digital_Sensor_Comms[n] */ |
| Vkadaba | 5:0728bde67bdb | 688 | #define REG_CORE_DIGITAL_SENSOR_COMMS0_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS0 */ |
| Vkadaba | 5:0728bde67bdb | 689 | #define REG_CORE_DIGITAL_SENSOR_COMMS1_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS1 */ |
| Vkadaba | 5:0728bde67bdb | 690 | #define REG_CORE_DIGITAL_SENSOR_COMMS2_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS2 */ |
| Vkadaba | 5:0728bde67bdb | 691 | #define REG_CORE_DIGITAL_SENSOR_COMMS3_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS3 */ |
| Vkadaba | 5:0728bde67bdb | 692 | #define REG_CORE_DIGITAL_SENSOR_COMMS4_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS4 */ |
| Vkadaba | 5:0728bde67bdb | 693 | #define REG_CORE_DIGITAL_SENSOR_COMMS5_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS5 */ |
| Vkadaba | 5:0728bde67bdb | 694 | #define REG_CORE_DIGITAL_SENSOR_COMMS6_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS6 */ |
| Vkadaba | 5:0728bde67bdb | 695 | #define REG_CORE_DIGITAL_SENSOR_COMMS7_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS7 */ |
| Vkadaba | 5:0728bde67bdb | 696 | #define REG_CORE_DIGITAL_SENSOR_COMMS8_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS8 */ |
| Vkadaba | 5:0728bde67bdb | 697 | #define REG_CORE_DIGITAL_SENSOR_COMMS9_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS9 */ |
| Vkadaba | 5:0728bde67bdb | 698 | #define REG_CORE_DIGITAL_SENSOR_COMMS10_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS10 */ |
| Vkadaba | 8:2f2775c34640 | 699 | #define REG_CORE_DIGITAL_SENSOR_COMMS11_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS11 */ |
| Vkadaba | 8:2f2775c34640 | 700 | #define REG_CORE_DIGITAL_SENSOR_COMMS12_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS12 */ |
| Vkadaba | 6:9d393a9677f4 | 701 | #define REG_CORE_DIGITAL_SENSOR_COMMS0 0x000000C0 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 702 | #define REG_CORE_DIGITAL_SENSOR_COMMS1 0x00000100 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 703 | #define REG_CORE_DIGITAL_SENSOR_COMMS2 0x00000140 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 704 | #define REG_CORE_DIGITAL_SENSOR_COMMS3 0x00000180 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 705 | #define REG_CORE_DIGITAL_SENSOR_COMMS4 0x000001C0 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 706 | #define REG_CORE_DIGITAL_SENSOR_COMMS5 0x00000200 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 707 | #define REG_CORE_DIGITAL_SENSOR_COMMS6 0x00000240 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 708 | #define REG_CORE_DIGITAL_SENSOR_COMMS7 0x00000280 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 709 | #define REG_CORE_DIGITAL_SENSOR_COMMS8 0x000002C0 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 710 | #define REG_CORE_DIGITAL_SENSOR_COMMS9 0x00000300 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 711 | #define REG_CORE_DIGITAL_SENSOR_COMMS10 0x00000340 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 8:2f2775c34640 | 712 | #define REG_CORE_DIGITAL_SENSOR_COMMS11 0x00000380 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 8:2f2775c34640 | 713 | #define REG_CORE_DIGITAL_SENSOR_COMMS12 0x000003C0 /* CORE Digital Sensor Communication Clock Configuration */ |
| Vkadaba | 6:9d393a9677f4 | 714 | #define REG_CORE_DIGITAL_SENSOR_COMMSn(i) (REG_CORE_DIGITAL_SENSOR_COMMS0 + ((i) * 64)) |
| Vkadaba | 8:2f2775c34640 | 715 | #define REG_CORE_DIGITAL_SENSOR_COMMSn_COUNT 13 |
| Vkadaba | 5:0728bde67bdb | 716 | |
| Vkadaba | 5:0728bde67bdb | 717 | /* ============================================================================================================================ |
| Vkadaba | 6:9d393a9677f4 | 718 | CORE Register BitMasks, Positions & Enumerations |
| Vkadaba | 5:0728bde67bdb | 719 | ============================================================================================================================ */ |
| Vkadaba | 5:0728bde67bdb | 720 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 721 | CORE_COMMAND Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 722 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 723 | #define BITP_CORE_COMMAND_SPECIAL_COMMAND 0 /* Special Command */ |
| Vkadaba | 6:9d393a9677f4 | 724 | #define BITM_CORE_COMMAND_SPECIAL_COMMAND 0x000000FF /* Special Command */ |
| Vkadaba | 32:52445bef314d | 725 | #define ENUM_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No command */ |
| Vkadaba | 32:52445bef314d | 726 | #define ENUM_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC conversions */ |
| Vkadaba | 32:52445bef314d | 727 | #define ENUM_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start conversions with added raw ADC data */ |
| Vkadaba | 32:52445bef314d | 728 | #define ENUM_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Latch configuration. */ |
| Vkadaba | 32:52445bef314d | 729 | #define ENUM_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from flash */ |
| Vkadaba | 32:52445bef314d | 730 | #define ENUM_CORE_COMMAND_SAVE_LUT 0x00000009 /* Special_Command: Save LUT to flash */ |
| Vkadaba | 32:52445bef314d | 731 | #define ENUM_CORE_COMMAND_LOAD_CONFIG_1 0x00000018 /* Special_Command: Load registers with configuration from flash */ |
| Vkadaba | 32:52445bef314d | 732 | #define ENUM_CORE_COMMAND_SAVE_CONFIG_1 0x00000019 /* Special_Command: Store current registers to flash configuration */ |
| Vkadaba | 5:0728bde67bdb | 733 | |
| Vkadaba | 5:0728bde67bdb | 734 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 735 | CORE_MODE Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 736 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 737 | #define BITP_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY Pin */ |
| Vkadaba | 6:9d393a9677f4 | 738 | #define BITP_CORE_MODE_CONVERSION_MODE 0 /* Conversion Mode */ |
| Vkadaba | 32:52445bef314d | 739 | #define BITM_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY Pin */ |
| Vkadaba | 6:9d393a9677f4 | 740 | #define BITM_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */ |
| Vkadaba | 32:52445bef314d | 741 | #define ENUM_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data ready per conversion */ |
| Vkadaba | 32:52445bef314d | 742 | #define ENUM_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data ready per cycle */ |
| Vkadaba | 32:52445bef314d | 743 | #define ENUM_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single cycle conversion mode. A cycle is completed every time a convert command is issued */ |
| Vkadaba | 32:52445bef314d | 744 | #define ENUM_CORE_MODE_RESERVED 0x00000001 /* Conversion_Mode: Reserved for future use */ |
| Vkadaba | 32:52445bef314d | 745 | #define ENUM_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous conversion mode. A cycle is started repeatedly at time specified in cycle time */ |
| Vkadaba | 5:0728bde67bdb | 746 | |
| Vkadaba | 5:0728bde67bdb | 747 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 748 | CORE_POWER_CONFIG Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 749 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 750 | #define BITP_CORE_POWER_CONFIG_POWER_MODE_MCU 0 /* MCU Power Mode */ |
| Vkadaba | 6:9d393a9677f4 | 751 | #define BITM_CORE_POWER_CONFIG_POWER_MODE_MCU 0x00000001 /* MCU Power Mode */ |
| Vkadaba | 32:52445bef314d | 752 | #define ENUM_CORE_POWER_CONFIG_ACTIVE_MODE 0x00000000 /* Power_Mode_MCU: ADMW1001 is fully power up and ready to convert */ |
| Vkadaba | 32:52445bef314d | 753 | #define ENUM_CORE_POWER_CONFIG_HIBERNATION 0x00000001 /* Power_Mode_MCU: Lowest power mode. wakeup pin required to enter active mode. SPI powered down */ |
| Vkadaba | 5:0728bde67bdb | 754 | |
| Vkadaba | 5:0728bde67bdb | 755 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 756 | CORE_CYCLE_CONTROL Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 757 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 43:e1789b7214cf | 758 | #define BITP_CORE_CYCLE_CONTROL_PST_MEAS_EXC_CTRL 15 /* Disable Current Sources After Measurement Completes */ |
| Vkadaba | 5:0728bde67bdb | 759 | #define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 14 /* Units for Cycle Time */ |
| Vkadaba | 8:2f2775c34640 | 760 | #define BITP_CORE_CYCLE_CONTROL_VBIAS 13 /* Voltage Bias Global Enable */ |
| Vkadaba | 43:e1789b7214cf | 761 | #define BITP_CORE_CYCLE_CONTROL_GND_SW_CTRL 12 /* Ground Switch Cycle Control */ |
| Vkadaba | 32:52445bef314d | 762 | #define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Time Between Measurement Cycles */ |
| Vkadaba | 43:e1789b7214cf | 763 | #define BITM_CORE_CYCLE_CONTROL_PST_MEAS_EXC_CTRL 0x00008000 /* Disable Current Sources After Measurement Completes */ |
| Vkadaba | 32:52445bef314d | 764 | #define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x00004000 /* Units for Cycle Time */ |
| Vkadaba | 8:2f2775c34640 | 765 | #define BITM_CORE_CYCLE_CONTROL_VBIAS 0x00002000 /* Voltage Bias Global Enable */ |
| Vkadaba | 43:e1789b7214cf | 766 | #define BITM_CORE_CYCLE_CONTROL_GND_SW_CTRL 0x00001000 /* Ground Switch Cycle Control */ |
| Vkadaba | 32:52445bef314d | 767 | #define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Time Between Measurement Cycles */ |
| Vkadaba | 43:e1789b7214cf | 768 | #define ENUM_CORE_CYCLE_CONTROL_POWERCYCLE 0x00000000 |
| Vkadaba | 43:e1789b7214cf | 769 | #define ENUM_CORE_CYCLE_CONTROL_ALWAYSON 0x00008000 |
| Vkadaba | 32:52445bef314d | 770 | #define ENUM_CORE_CYCLE_CONTROL_MILLISECONDS 0x00000000 /* Cycle_Time_Units: Milli-seconds */ |
| Vkadaba | 8:2f2775c34640 | 771 | #define ENUM_CORE_CYCLE_CONTROL_SECONDS 0x00004000 /* Cycle_Time_Units: Seconds */ |
| Vkadaba | 32:52445bef314d | 772 | #define ENUM_CORE_CYCLE_CONTROL_VBIAS_DISABLE 0x00000000 /* Vbias: Vbias disabled */ |
| Vkadaba | 32:52445bef314d | 773 | #define ENUM_CORE_CYCLE_CONTROL_VBIAS_ENABLE 0x00002000 /* Vbias: Enable Vbias output for the duration of a cycle */ |
| Vkadaba | 43:e1789b7214cf | 774 | #define ENUM_CORE_CYCLE_CONTROL_CLOSE_SW 0x00000000 /* GND_SW_CTRL: Ground Switch Closed */ |
| Vkadaba | 43:e1789b7214cf | 775 | #define ENUM_CORE_CYCLE_CONTROL_CYCLE_SW 0x00001000 /* GND_SW_CTRL: Ground Switch Opens outside of measurement cycle to conserve power */ |
| Vkadaba | 32:52445bef314d | 776 | |
| Vkadaba | 32:52445bef314d | 777 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 32:52445bef314d | 778 | CORE_FIFO_NUM_CYCLES Pos/Masks Description |
| Vkadaba | 32:52445bef314d | 779 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 780 | #define BITP_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0 /* Number of Cycles to Fill the FIFO */ |
| Vkadaba | 32:52445bef314d | 781 | #define BITM_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0x000000FF /* Number of Cycles to Fill the FIFO */ |
| Vkadaba | 5:0728bde67bdb | 782 | |
| Vkadaba | 5:0728bde67bdb | 783 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 784 | CORE_STATUS Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 785 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 786 | #define BITP_CORE_STATUS_LUT_ERROR 7 /* Indicates Error with One or More Lookup Tables */ |
| Vkadaba | 32:52445bef314d | 787 | #define BITP_CORE_STATUS_DIAG_CHECKSUM_ERROR 6 /* Indicates Error on Internal Checksum Calculations */ |
| Vkadaba | 6:9d393a9677f4 | 788 | #define BITP_CORE_STATUS_FIFO_ERROR 5 /* Indicates Error with FIFO */ |
| Vkadaba | 32:52445bef314d | 789 | #define BITP_CORE_STATUS_CMD_RUNNING 4 /* Indicates Special Command Active */ |
| Vkadaba | 32:52445bef314d | 790 | #define BITP_CORE_STATUS_DRDY 3 /* Indicates New Sensor Result Available to Read */ |
| Vkadaba | 6:9d393a9677f4 | 791 | #define BITP_CORE_STATUS_ERROR 2 /* Indicates an Error */ |
| Vkadaba | 32:52445bef314d | 792 | #define BITP_CORE_STATUS_ALERT_ACTIVE 1 /* Indicates One or More Sensor Alerts Active */ |
| Vkadaba | 32:52445bef314d | 793 | #define BITP_CORE_STATUS_CONFIGURATION_ERROR 0 /* Indicates Error with Programmed Configuration */ |
| Vkadaba | 32:52445bef314d | 794 | #define BITM_CORE_STATUS_LUT_ERROR 0x00000080 /* Indicates Error with One or More Lookup Tables */ |
| Vkadaba | 32:52445bef314d | 795 | #define BITM_CORE_STATUS_DIAG_CHECKSUM_ERROR 0x00000040 /* Indicates Error on Internal Checksum Calculations */ |
| Vkadaba | 6:9d393a9677f4 | 796 | #define BITM_CORE_STATUS_FIFO_ERROR 0x00000020 /* Indicates Error with FIFO */ |
| Vkadaba | 32:52445bef314d | 797 | #define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates Special Command Active */ |
| Vkadaba | 32:52445bef314d | 798 | #define BITM_CORE_STATUS_DRDY 0x00000008 /* Indicates New Sensor Result Available to Read */ |
| Vkadaba | 6:9d393a9677f4 | 799 | #define BITM_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */ |
| Vkadaba | 32:52445bef314d | 800 | #define BITM_CORE_STATUS_ALERT_ACTIVE 0x00000002 /* Indicates One or More Sensor Alerts Active */ |
| Vkadaba | 32:52445bef314d | 801 | #define BITM_CORE_STATUS_CONFIGURATION_ERROR 0x00000001 /* Indicates Error with Programmed Configuration */ |
| Vkadaba | 5:0728bde67bdb | 802 | |
| Vkadaba | 5:0728bde67bdb | 803 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 804 | CORE_CHANNEL_ALERT_STATUS Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 805 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 806 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 12 /* Indicates Channel 12 Alert Active */ |
| Vkadaba | 32:52445bef314d | 807 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel 11 Alert Active */ |
| Vkadaba | 32:52445bef314d | 808 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel 10 Alert Active */ |
| Vkadaba | 32:52445bef314d | 809 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel 9 Alert Active */ |
| Vkadaba | 32:52445bef314d | 810 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel 8 Alert Active */ |
| Vkadaba | 32:52445bef314d | 811 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel 7 Alert Active */ |
| Vkadaba | 32:52445bef314d | 812 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel 6 Alert Active */ |
| Vkadaba | 32:52445bef314d | 813 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel 5Alert Active */ |
| Vkadaba | 32:52445bef314d | 814 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel 4 Alert Active */ |
| Vkadaba | 32:52445bef314d | 815 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel 3 Alert Active */ |
| Vkadaba | 32:52445bef314d | 816 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel 2 Alert Active */ |
| Vkadaba | 32:52445bef314d | 817 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel 1 Alert Active */ |
| Vkadaba | 32:52445bef314d | 818 | #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel 0 Alert Active */ |
| Vkadaba | 32:52445bef314d | 819 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 0x00001000 /* Indicates Channel 12 Alert Active */ |
| Vkadaba | 32:52445bef314d | 820 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel 11 Alert Active */ |
| Vkadaba | 32:52445bef314d | 821 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel 10 Alert Active */ |
| Vkadaba | 32:52445bef314d | 822 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel 9 Alert Active */ |
| Vkadaba | 32:52445bef314d | 823 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel 8 Alert Active */ |
| Vkadaba | 32:52445bef314d | 824 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel 7 Alert Active */ |
| Vkadaba | 32:52445bef314d | 825 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel 6 Alert Active */ |
| Vkadaba | 32:52445bef314d | 826 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel 5Alert Active */ |
| Vkadaba | 32:52445bef314d | 827 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel 4 Alert Active */ |
| Vkadaba | 32:52445bef314d | 828 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel 3 Alert Active */ |
| Vkadaba | 32:52445bef314d | 829 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel 2 Alert Active */ |
| Vkadaba | 32:52445bef314d | 830 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel 1 Alert Active */ |
| Vkadaba | 32:52445bef314d | 831 | #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel 0 Alert Active */ |
| Vkadaba | 5:0728bde67bdb | 832 | |
| Vkadaba | 5:0728bde67bdb | 833 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 834 | CORE_ALERT_DETAIL_CH[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 835 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 836 | #define BITP_CORE_ALERT_DETAIL_CH_SENSOR_HARDFAULT 7 /* Indicates Sensor Hard Fault */ |
| Vkadaba | 32:52445bef314d | 837 | #define BITP_CORE_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE 6 /* Indicates the ADC Input is Overrange */ |
| Vkadaba | 32:52445bef314d | 838 | #define BITP_CORE_ALERT_DETAIL_CH_CJ_HARD_FAULT 5 /* Cold Junction Hard Fault */ |
| Vkadaba | 32:52445bef314d | 839 | #define BITP_CORE_ALERT_DETAIL_CH_CJ_SOFT_FAULT 4 /* Cold Junction Soft Fault */ |
| Vkadaba | 32:52445bef314d | 840 | #define BITP_CORE_ALERT_DETAIL_CH_SENSOR_OVERRANGE 3 /* Indicates If the Sensor is Overrange */ |
| Vkadaba | 32:52445bef314d | 841 | #define BITP_CORE_ALERT_DETAIL_CH_SENSOR_UNDERRANGE 2 /* Indicates If the Sensor is Underrange */ |
| Vkadaba | 32:52445bef314d | 842 | #define BITP_CORE_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE 1 /* Indicates If the ADC is Near Overrange */ |
| Vkadaba | 32:52445bef314d | 843 | #define BITP_CORE_ALERT_DETAIL_CH_RESULT_VALID 0 /* Set If a Result is Valid */ |
| Vkadaba | 32:52445bef314d | 844 | #define BITM_CORE_ALERT_DETAIL_CH_SENSOR_HARDFAULT 0x00000080 /* Indicates Sensor Hard Fault */ |
| Vkadaba | 32:52445bef314d | 845 | #define BITM_CORE_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE 0x00000040 /* Indicates the ADC Input is Overrange */ |
| Vkadaba | 32:52445bef314d | 846 | #define BITM_CORE_ALERT_DETAIL_CH_CJ_HARD_FAULT 0x00000020 /* Cold Junction Hard Fault */ |
| Vkadaba | 32:52445bef314d | 847 | #define BITM_CORE_ALERT_DETAIL_CH_CJ_SOFT_FAULT 0x00000010 /* Cold Junction Soft Fault */ |
| Vkadaba | 32:52445bef314d | 848 | #define BITM_CORE_ALERT_DETAIL_CH_SENSOR_OVERRANGE 0x00000008 /* Indicates If the Sensor is Overrange */ |
| Vkadaba | 32:52445bef314d | 849 | #define BITM_CORE_ALERT_DETAIL_CH_SENSOR_UNDERRANGE 0x00000004 /* Indicates If the Sensor is Underrange */ |
| Vkadaba | 32:52445bef314d | 850 | #define BITM_CORE_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE 0x00000002 /* Indicates If the ADC is Near Overrange */ |
| Vkadaba | 32:52445bef314d | 851 | #define BITM_CORE_ALERT_DETAIL_CH_RESULT_VALID 0x00000001 /* Set If a Result is Valid */ |
| Vkadaba | 5:0728bde67bdb | 852 | |
| Vkadaba | 5:0728bde67bdb | 853 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 854 | CORE_ERROR_CODE Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 855 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 856 | #define BITP_CORE_ERROR_CODE_ERROR_CODE 0 /* Code Indicating Type of Error */ |
| Vkadaba | 6:9d393a9677f4 | 857 | #define BITM_CORE_ERROR_CODE_ERROR_CODE 0x0000FFFF /* Code Indicating Type of Error */ |
| Vkadaba | 5:0728bde67bdb | 858 | |
| Vkadaba | 5:0728bde67bdb | 859 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 860 | CORE_EXTERNAL_REFERENCE_RESISTOR Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 861 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 862 | #define BITP_CORE_EXTERNAL_REFERENCE_RESISTOR_EXT_REFIN1_VALUE 0 /* External Reference Resistor Value */ |
| Vkadaba | 32:52445bef314d | 863 | #define BITM_CORE_EXTERNAL_REFERENCE_RESISTOR_EXT_REFIN1_VALUE 0xFFFFFFFF /* External Reference Resistor Value */ |
| Vkadaba | 5:0728bde67bdb | 864 | |
| Vkadaba | 5:0728bde67bdb | 865 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 36:54e2418e7620 | 866 | CORE_EXTERNAL_VOLTAGE_REFERENCE Pos/Masks Description |
| Vkadaba | 36:54e2418e7620 | 867 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 36:54e2418e7620 | 868 | #define BITP_CORE_EXTERNAL_VOLTAGE_REFERENCE_EXT_REFIN2_VALUE 0 /* Reference Input Value */ |
| Vkadaba | 36:54e2418e7620 | 869 | #define BITM_CORE_EXTERNAL_VOLTAGE_REFERENCE_EXT_REFIN2_VALUE 0xFFFFFFFF /* Reference Input Value */ |
| Vkadaba | 36:54e2418e7620 | 870 | |
| Vkadaba | 36:54e2418e7620 | 871 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 872 | CORE_DIAGNOSTICS_CONTROL Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 873 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 874 | #define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 1 /* Diagnostics Open Sensor Detect Frequency */ |
| Vkadaba | 32:52445bef314d | 875 | #define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0 /* Diagnostics Measure Enable */ |
| Vkadaba | 32:52445bef314d | 876 | #define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 0x00000006 /* Diagnostics Open Sensor Detect Frequency */ |
| Vkadaba | 32:52445bef314d | 877 | #define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000001 /* Diagnostics Measure Enable */ |
| Vkadaba | 5:0728bde67bdb | 878 | #define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_OFF 0x00000000 /* Diag_OSD_Freq: No Open-Circuit Detection During Measurement */ |
| Vkadaba | 32:52445bef314d | 879 | #define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE 0x00000002 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Measurement Cycle */ |
| Vkadaba | 32:52445bef314d | 880 | #define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_10_CYCLES 0x00000004 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Ten Measurement Cycles */ |
| Vkadaba | 32:52445bef314d | 881 | #define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES 0x00000006 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */ |
| Vkadaba | 5:0728bde67bdb | 882 | |
| Vkadaba | 5:0728bde67bdb | 883 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 884 | CORE_DATA_FIFO Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 885 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 886 | #define BITP_CORE_DATA_FIFO_DATA_FIFO 0 /* FIFO Buffer of Sensor Results */ |
| Vkadaba | 32:52445bef314d | 887 | #define BITM_CORE_DATA_FIFO_DATA_FIFO 0x000000FF /* FIFO Buffer of Sensor Results */ |
| Vkadaba | 5:0728bde67bdb | 888 | |
| Vkadaba | 5:0728bde67bdb | 889 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 890 | CORE_DEBUG_CODE Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 891 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 892 | #define BITP_CORE_DEBUG_CODE_DEBUG_CODE 0 /* Additional Information on Source of Alert or Errors */ |
| Vkadaba | 32:52445bef314d | 893 | #define BITM_CORE_DEBUG_CODE_DEBUG_CODE 0xFFFFFFFF /* Additional Information on Source of Alert or Errors */ |
| Vkadaba | 5:0728bde67bdb | 894 | |
| Vkadaba | 5:0728bde67bdb | 895 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 32:52445bef314d | 896 | CORE_TEST_REG_ACCESS Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 897 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 898 | #define BITP_CORE_TEST_REG_ACCESS_TEST_ACCESS 0 /* Test Register Access. Specific Write Sequence Required */ |
| Vkadaba | 32:52445bef314d | 899 | #define BITM_CORE_TEST_REG_ACCESS_TEST_ACCESS 0x0000FFFF /* Test Register Access. Specific Write Sequence Required */ |
| Vkadaba | 5:0728bde67bdb | 900 | |
| Vkadaba | 5:0728bde67bdb | 901 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 902 | CORE_LUT_SELECT Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 903 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 904 | #define BITP_CORE_LUT_SELECT_LUT_RW 7 /* Read or Write LUT Data */ |
| Vkadaba | 6:9d393a9677f4 | 905 | #define BITM_CORE_LUT_SELECT_LUT_RW 0x00000080 /* Read or Write LUT Data */ |
| Vkadaba | 32:52445bef314d | 906 | #define ENUM_CORE_LUT_SELECT_LUT_READ 0x00000000 /* LUT_RW: Read addressed LUT data */ |
| Vkadaba | 32:52445bef314d | 907 | #define ENUM_CORE_LUT_SELECT_LUT_WRITE 0x00000080 /* LUT_RW: Write addressed LUT data */ |
| Vkadaba | 5:0728bde67bdb | 908 | |
| Vkadaba | 5:0728bde67bdb | 909 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 910 | CORE_LUT_OFFSET Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 911 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 912 | #define BITP_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into the Lookup Table */ |
| Vkadaba | 32:52445bef314d | 913 | #define BITM_CORE_LUT_OFFSET_LUT_OFFSET 0x00003FFF /* Offset into the Lookup Table */ |
| Vkadaba | 5:0728bde67bdb | 914 | |
| Vkadaba | 5:0728bde67bdb | 915 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 916 | CORE_LUT_DATA Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 917 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 918 | #define BITP_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to and Read from the Lookup Table */ |
| Vkadaba | 32:52445bef314d | 919 | #define BITM_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to and Read from the Lookup Table */ |
| Vkadaba | 5:0728bde67bdb | 920 | |
| Vkadaba | 5:0728bde67bdb | 921 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 922 | CORE_REVISION Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 923 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 924 | #define BITP_CORE_REVISION_REV_MAJOR 24 /* Major Revision Information */ |
| Vkadaba | 6:9d393a9677f4 | 925 | #define BITP_CORE_REVISION_REV_MINOR 16 /* Minor Revision Information */ |
| Vkadaba | 6:9d393a9677f4 | 926 | #define BITP_CORE_REVISION_REV_PATCH 0 /* Patch Revision Information */ |
| Vkadaba | 6:9d393a9677f4 | 927 | #define BITM_CORE_REVISION_REV_MAJOR 0xFF000000 /* Major Revision Information */ |
| Vkadaba | 6:9d393a9677f4 | 928 | #define BITM_CORE_REVISION_REV_MINOR 0x00FF0000 /* Minor Revision Information */ |
| Vkadaba | 6:9d393a9677f4 | 929 | #define BITM_CORE_REVISION_REV_PATCH 0x0000FFFF /* Patch Revision Information */ |
| Vkadaba | 5:0728bde67bdb | 930 | |
| Vkadaba | 5:0728bde67bdb | 931 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 932 | CORE_CHANNEL_COUNT[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 933 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 934 | #define BITP_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 7 /* Enable Channel in Measurement Cycle */ |
| Vkadaba | 32:52445bef314d | 935 | #define BITP_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Appears in One Cycle */ |
| Vkadaba | 5:0728bde67bdb | 936 | #define BITM_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 0x00000080 /* Enable Channel in Measurement Cycle */ |
| Vkadaba | 32:52445bef314d | 937 | #define BITM_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Appears in One Cycle */ |
| Vkadaba | 5:0728bde67bdb | 938 | |
| Vkadaba | 5:0728bde67bdb | 939 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 940 | CORE_CHANNEL_OPTIONS[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 941 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 942 | #define BITP_CORE_CHANNEL_OPTIONS_CHANNEL_PRIORITY 0 /* Indicates Priority or Position of This Channel in Sequence */ |
| Vkadaba | 5:0728bde67bdb | 943 | #define BITM_CORE_CHANNEL_OPTIONS_CHANNEL_PRIORITY 0x0000000F /* Indicates Priority or Position of This Channel in Sequence */ |
| Vkadaba | 5:0728bde67bdb | 944 | |
| Vkadaba | 5:0728bde67bdb | 945 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 946 | CORE_SENSOR_TYPE[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 947 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 948 | #define BITP_CORE_SENSOR_TYPE_SENSOR_TYPE 0 /* Sensor Type */ |
| Vkadaba | 6:9d393a9677f4 | 949 | #define BITM_CORE_SENSOR_TYPE_SENSOR_TYPE 0x00000FFF /* Sensor Type */ |
| Vkadaba | 32:52445bef314d | 950 | #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_T 0x00000000 /* Sensor_Type: Thermocouple T-Type sensor */ |
| Vkadaba | 32:52445bef314d | 951 | #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_J 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor */ |
| Vkadaba | 32:52445bef314d | 952 | #define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_K 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor */ |
| Vkadaba | 32:52445bef314d | 953 | #define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT100 0x00000020 /* Sensor_Type: RTD 2 wire PT100 sensor */ |
| Vkadaba | 32:52445bef314d | 954 | #define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT1000 0x00000021 /* Sensor_Type: RTD 2 wire PT1000 sensor */ |
| Vkadaba | 32:52445bef314d | 955 | #define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT100 0x00000040 /* Sensor_Type: RTD 3 wire PT100 sensor */ |
| Vkadaba | 32:52445bef314d | 956 | #define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT1000 0x00000041 /* Sensor_Type: RTD 3 wire PT1000 sensor */ |
| Vkadaba | 32:52445bef314d | 957 | #define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT100 0x00000060 /* Sensor_Type: RTD 4 wire PT100 sensor */ |
| Vkadaba | 32:52445bef314d | 958 | #define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT1000 0x00000061 /* Sensor_Type: RTD 4 wire PT1000 sensor */ |
| Vkadaba | 32:52445bef314d | 959 | #define ENUM_CORE_SENSOR_TYPE_BRIDGE_4W 0x000000A9 /* Sensor_Type: Bridge 4 wire sensor */ |
| Vkadaba | 32:52445bef314d | 960 | #define ENUM_CORE_SENSOR_TYPE_CUSTOM1 0x00000400 /* Sensor_Type: Custom1 */ |
| Vkadaba | 32:52445bef314d | 961 | #define ENUM_CORE_SENSOR_TYPE_I2C_HUMIDITY_B 0x00000841 /* Sensor_Type: I2C humidity sensor B */ |
| Vkadaba | 32:52445bef314d | 962 | #define ENUM_CORE_SENSOR_TYPE_SENSOR_RESERVED_1 0x00000FE0 /* Sensor_Type: RESERVED. NOT TO BE USED */ |
| Vkadaba | 32:52445bef314d | 963 | #define ENUM_CORE_SENSOR_TYPE_SENSOR_RESERVED_2 0x00000FFF /* Sensor_Type: RESERVED. NOT TO BE USED */ |
| Vkadaba | 5:0728bde67bdb | 964 | |
| Vkadaba | 5:0728bde67bdb | 965 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 966 | CORE_SENSOR_DETAILS[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 967 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 32:52445bef314d | 968 | #define BITP_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 31 /* This Bit Indicates Compensation Data Must Not Be Used */ |
| Vkadaba | 32:52445bef314d | 969 | #define BITP_CORE_SENSOR_DETAILS_RTD_CURVE 27 /* Select RTD Curve for Linearization */ |
| Vkadaba | 6:9d393a9677f4 | 970 | #define BITP_CORE_SENSOR_DETAILS_PGA_GAIN 24 /* PGA Gain */ |
| Vkadaba | 5:0728bde67bdb | 971 | #define BITP_CORE_SENSOR_DETAILS_REFERENCE_SELECT 20 /* Reference Selection */ |
| Vkadaba | 5:0728bde67bdb | 972 | #define BITP_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 17 /* Do Not Publish Channel Result */ |
| Vkadaba | 8:2f2775c34640 | 973 | #define BITP_CORE_SENSOR_DETAILS_LUT_SELECT 15 /* Lookup Table Select */ |
| Vkadaba | 32:52445bef314d | 974 | #define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel Used to Compensate the Sensor Result */ |
| Vkadaba | 5:0728bde67bdb | 975 | #define BITP_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0 /* Units of Sensor Measurement */ |
| Vkadaba | 32:52445bef314d | 976 | #define BITM_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 0x80000000 /* This Bit Indicates Compensation Data Must Not Be Used */ |
| Vkadaba | 32:52445bef314d | 977 | #define BITM_CORE_SENSOR_DETAILS_RTD_CURVE 0x18000000 /* Select RTD Curve for Linearization */ |
| Vkadaba | 6:9d393a9677f4 | 978 | #define BITM_CORE_SENSOR_DETAILS_PGA_GAIN 0x07000000 /* PGA Gain */ |
| Vkadaba | 5:0728bde67bdb | 979 | #define BITM_CORE_SENSOR_DETAILS_REFERENCE_SELECT 0x00F00000 /* Reference Selection */ |
| Vkadaba | 5:0728bde67bdb | 980 | #define BITM_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 0x00020000 /* Do Not Publish Channel Result */ |
| Vkadaba | 8:2f2775c34640 | 981 | #define BITM_CORE_SENSOR_DETAILS_LUT_SELECT 0x00018000 /* Lookup Table Select */ |
| Vkadaba | 32:52445bef314d | 982 | #define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel Used to Compensate the Sensor Result */ |
| Vkadaba | 5:0728bde67bdb | 983 | #define BITM_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0x0000000F /* Units of Sensor Measurement */ |
| Vkadaba | 32:52445bef314d | 984 | #define ENUM_CORE_SENSOR_DETAILS_EUROPEAN_CURVE 0x00000000 /* RTD_Curve: European curve */ |
| Vkadaba | 32:52445bef314d | 985 | #define ENUM_CORE_SENSOR_DETAILS_AMERICAN_CURVE 0x08000000 /* RTD_Curve: American curve */ |
| Vkadaba | 32:52445bef314d | 986 | #define ENUM_CORE_SENSOR_DETAILS_JAPANESE_CURVE 0x10000000 /* RTD_Curve: Japanese curve */ |
| Vkadaba | 32:52445bef314d | 987 | #define ENUM_CORE_SENSOR_DETAILS_ITS90_CURVE 0x18000000 /* RTD_Curve: ITS-90 curve */ |
| Vkadaba | 6:9d393a9677f4 | 988 | #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_1 0x00000000 /* PGA_Gain: Gain of 1 */ |
| Vkadaba | 6:9d393a9677f4 | 989 | #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_2 0x01000000 /* PGA_Gain: Gain of 2 */ |
| Vkadaba | 6:9d393a9677f4 | 990 | #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_4 0x02000000 /* PGA_Gain: Gain of 4 */ |
| Vkadaba | 6:9d393a9677f4 | 991 | #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_8 0x03000000 /* PGA_Gain: Gain of 8 */ |
| Vkadaba | 5:0728bde67bdb | 992 | #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_16 0x04000000 /* PGA_Gain: Gain of 16 */ |
| Vkadaba | 5:0728bde67bdb | 993 | #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_32 0x05000000 /* PGA_Gain: Gain of 32 */ |
| Vkadaba | 5:0728bde67bdb | 994 | #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_64 0x06000000 /* PGA_Gain: Gain of 64 */ |
| Vkadaba | 5:0728bde67bdb | 995 | #define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_128 0x07000000 /* PGA_Gain: Gain of 128 */ |
| Vkadaba | 6:9d393a9677f4 | 996 | #define ENUM_CORE_SENSOR_DETAILS_REF_VINT 0x00000000 /* Reference_Select: Internal voltage reference (1.2V) */ |
| Vkadaba | 32:52445bef314d | 997 | #define ENUM_CORE_SENSOR_DETAILS_REF_VEXT1 0x00100000 /* Reference_Select: External voltage reference applied to VERF+ and VREF- */ |
| Vkadaba | 32:52445bef314d | 998 | #define ENUM_CORE_SENSOR_DETAILS_REF_AVDD 0x00300000 /* Reference_Select: AVDD supply internally used as reference */ |
| Vkadaba | 32:52445bef314d | 999 | #define ENUM_CORE_SENSOR_DETAILS_LUT_DEFAULT 0x00000000 /* LUT_Select: Default lookup table for selected sensor type */ |
| Vkadaba | 32:52445bef314d | 1000 | #define ENUM_CORE_SENSOR_DETAILS_LUT_UNITY 0x00008000 /* LUT_Select: Unity lookup table. 1:1 mapping from input to output */ |
| Vkadaba | 32:52445bef314d | 1001 | #define ENUM_CORE_SENSOR_DETAILS_LUT_CUSTOM 0x00010000 /* LUT_Select: User defined custom lookup table. */ |
| Vkadaba | 8:2f2775c34640 | 1002 | #define ENUM_CORE_SENSOR_DETAILS_LUT_RESERVED 0x00018000 /* LUT_Select: Reserved */ |
| Vkadaba | 5:0728bde67bdb | 1003 | #define ENUM_CORE_SENSOR_DETAILS_UNITS_UNSPECIFIED 0x00000000 /* Measurement_Units: Not Specified */ |
| Vkadaba | 5:0728bde67bdb | 1004 | #define ENUM_CORE_SENSOR_DETAILS_UNITS_RESERVED 0x00000001 /* Measurement_Units: Reserved */ |
| Vkadaba | 6:9d393a9677f4 | 1005 | #define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGC 0x00000002 /* Measurement_Units: Degrees C */ |
| Vkadaba | 6:9d393a9677f4 | 1006 | #define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGF 0x00000003 /* Measurement_Units: Degrees F */ |
| Vkadaba | 5:0728bde67bdb | 1007 | |
| Vkadaba | 5:0728bde67bdb | 1008 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1009 | CORE_CHANNEL_EXCITATION[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1010 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 1011 | #define BITP_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0 /* Current Source Value */ |
| Vkadaba | 6:9d393a9677f4 | 1012 | #define BITM_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0x0000000F /* Current Source Value */ |
| Vkadaba | 32:52445bef314d | 1013 | #define ENUM_CORE_CHANNEL_EXCITATION_NONE 0x00000000 /* IOUT_Excitation_Current: Excitation Current Disabled */ |
| Vkadaba | 6:9d393a9677f4 | 1014 | #define ENUM_CORE_CHANNEL_EXCITATION_RESERVED 0x00000001 /* IOUT_Excitation_Current: Reserved */ |
| Vkadaba | 6:9d393a9677f4 | 1015 | #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_10UA 0x00000002 /* IOUT_Excitation_Current: 10 \mu;A */ |
| Vkadaba | 6:9d393a9677f4 | 1016 | #define ENUM_CORE_CHANNEL_EXCITATION_RESERVED2 0x00000003 /* IOUT_Excitation_Current: Reserved */ |
| Vkadaba | 6:9d393a9677f4 | 1017 | #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_50UA 0x00000004 /* IOUT_Excitation_Current: 50 \mu;A */ |
| Vkadaba | 6:9d393a9677f4 | 1018 | #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_100UA 0x00000005 /* IOUT_Excitation_Current: 100 \mu;A */ |
| Vkadaba | 6:9d393a9677f4 | 1019 | #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_250UA 0x00000006 /* IOUT_Excitation_Current: 250 \mu;A */ |
| Vkadaba | 6:9d393a9677f4 | 1020 | #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_500UA 0x00000007 /* IOUT_Excitation_Current: 500 \mu;A */ |
| Vkadaba | 6:9d393a9677f4 | 1021 | #define ENUM_CORE_CHANNEL_EXCITATION_IEXC_1000UA 0x00000008 /* IOUT_Excitation_Current: 1000 \mu;A */ |
| Vkadaba | 32:52445bef314d | 1022 | #define ENUM_CORE_CHANNEL_EXCITATION_EXTERNAL 0x0000000F /* IOUT_Excitation_Current: External current sourced */ |
| Vkadaba | 5:0728bde67bdb | 1023 | |
| Vkadaba | 5:0728bde67bdb | 1024 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1025 | CORE_SETTLING_TIME[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1026 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 1027 | #define BITP_CORE_SETTLING_TIME_SETTLING_TIME_UNITS 14 /* Units for Settling Time */ |
| Vkadaba | 5:0728bde67bdb | 1028 | #define BITP_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Settling Time to Allow When Switching to Channel */ |
| Vkadaba | 5:0728bde67bdb | 1029 | #define BITM_CORE_SETTLING_TIME_SETTLING_TIME_UNITS 0x0000C000 /* Units for Settling Time */ |
| Vkadaba | 5:0728bde67bdb | 1030 | #define BITM_CORE_SETTLING_TIME_SETTLING_TIME 0x00003FFF /* Settling Time to Allow When Switching to Channel */ |
| Vkadaba | 32:52445bef314d | 1031 | #define ENUM_CORE_SETTLING_TIME_MICROSECONDS 0x00000000 /* Settling_Time_Units: Micro-seconds */ |
| Vkadaba | 32:52445bef314d | 1032 | #define ENUM_CORE_SETTLING_TIME_MILLISECONDS 0x00004000 /* Settling_Time_Units: Milli-seconds */ |
| Vkadaba | 6:9d393a9677f4 | 1033 | #define ENUM_CORE_SETTLING_TIME_SECONDS 0x00008000 /* Settling_Time_Units: Seconds */ |
| Vkadaba | 32:52445bef314d | 1034 | #define ENUM_CORE_SETTLING_TIME_UNDEFINED 0x0000C000 /* Settling_Time_Units: Undefined */ |
| Vkadaba | 5:0728bde67bdb | 1035 | |
| Vkadaba | 5:0728bde67bdb | 1036 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1037 | CORE_MEASUREMENT_SETUP[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1038 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 8:2f2775c34640 | 1039 | #define BITP_CORE_MEASUREMENT_SETUP_BUFFER_BYPASS 15 /* Disable Buffers */ |
| Vkadaba | 6:9d393a9677f4 | 1040 | #define BITP_CORE_MEASUREMENT_SETUP_ADC_FILTER_TYPE 12 /* ADC Digital Filter Type */ |
| Vkadaba | 6:9d393a9677f4 | 1041 | #define BITP_CORE_MEASUREMENT_SETUP_CHOP_MODE 10 /* Enabled and Disable Chop Mode */ |
| Vkadaba | 6:9d393a9677f4 | 1042 | #define BITP_CORE_MEASUREMENT_SETUP_NOTCH_EN_2 8 /* Enable Notch 2 Filter Mode */ |
| Vkadaba | 32:52445bef314d | 1043 | #define BITP_CORE_MEASUREMENT_SETUP_ADC_SF 0 /* ADC Digital Filter Speed */ |
| Vkadaba | 8:2f2775c34640 | 1044 | #define BITM_CORE_MEASUREMENT_SETUP_BUFFER_BYPASS 0x00008000 /* Disable Buffers */ |
| Vkadaba | 6:9d393a9677f4 | 1045 | #define BITM_CORE_MEASUREMENT_SETUP_ADC_FILTER_TYPE 0x00001000 /* ADC Digital Filter Type */ |
| Vkadaba | 6:9d393a9677f4 | 1046 | #define BITM_CORE_MEASUREMENT_SETUP_CHOP_MODE 0x00000C00 /* Enabled and Disable Chop Mode */ |
| Vkadaba | 6:9d393a9677f4 | 1047 | #define BITM_CORE_MEASUREMENT_SETUP_NOTCH_EN_2 0x00000100 /* Enable Notch 2 Filter Mode */ |
| Vkadaba | 32:52445bef314d | 1048 | #define BITM_CORE_MEASUREMENT_SETUP_ADC_SF 0x0000007F /* ADC Digital Filter Speed */ |
| Vkadaba | 32:52445bef314d | 1049 | #define ENUM_CORE_MEASUREMENT_SETUP_BUFFERS_ENABLED 0x00000000 /* Buffer_Bypass: Input buffers enabled */ |
| Vkadaba | 32:52445bef314d | 1050 | #define ENUM_CORE_MEASUREMENT_SETUP_BUFFERS_DISABLED 0x00008000 /* Buffer_Bypass: Input buffers disabled */ |
| Vkadaba | 32:52445bef314d | 1051 | #define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC4 0x00000000 /* ADC_Filter_Type: Enabled SINC4 filter */ |
| Vkadaba | 32:52445bef314d | 1052 | #define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC3 0x00001000 /* ADC_Filter_Type: Enabled SINC3 filter */ |
| Vkadaba | 32:52445bef314d | 1053 | #define ENUM_CORE_MEASUREMENT_SETUP_DISABLE_CHOP 0x00000000 /* Chop_Mode: ADC front end chopping disabled */ |
| Vkadaba | 32:52445bef314d | 1054 | #define ENUM_CORE_MEASUREMENT_SETUP_HW_CHOP 0x00000400 /* Chop_Mode: Hardware chopping enabled */ |
| Vkadaba | 32:52445bef314d | 1055 | #define ENUM_CORE_MEASUREMENT_SETUP_SW_CHOP 0x00000800 /* Chop_Mode: SW chop enabled */ |
| Vkadaba | 32:52445bef314d | 1056 | #define ENUM_CORE_MEASUREMENT_SETUP_HW_SW_CHOP 0x00000C00 /* Chop_Mode: Hardware and software chop enabled */ |
| Vkadaba | 32:52445bef314d | 1057 | #define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_DIS 0x00000000 /* NOTCH_EN_2: Disable notch filter */ |
| Vkadaba | 32:52445bef314d | 1058 | #define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_EN 0x00000100 /* NOTCH_EN_2: Enable notch 2 filter option. */ |
| Vkadaba | 5:0728bde67bdb | 1059 | |
| Vkadaba | 5:0728bde67bdb | 1060 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1061 | CORE_HIGH_THRESHOLD_LIMIT[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1062 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 1063 | #define BITP_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0 /* Upper Limit for Sensor Alert Comparison */ |
| Vkadaba | 32:52445bef314d | 1064 | #define BITM_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0xFFFFFFFF /* Upper Limit for Sensor Alert Comparison */ |
| Vkadaba | 5:0728bde67bdb | 1065 | |
| Vkadaba | 5:0728bde67bdb | 1066 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1067 | CORE_LOW_THRESHOLD_LIMIT[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1068 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 1069 | #define BITP_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0 /* Lower Limit for Sensor Alert Comparison */ |
| Vkadaba | 32:52445bef314d | 1070 | #define BITM_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */ |
| Vkadaba | 5:0728bde67bdb | 1071 | |
| Vkadaba | 5:0728bde67bdb | 1072 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1073 | CORE_SENSOR_OFFSET[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1074 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 1075 | #define BITP_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0 /* Sensor Offset Adjustment */ |
| Vkadaba | 32:52445bef314d | 1076 | #define BITM_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0xFFFFFFFF /* Sensor Offset Adjustment */ |
| Vkadaba | 5:0728bde67bdb | 1077 | |
| Vkadaba | 5:0728bde67bdb | 1078 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1079 | CORE_SENSOR_GAIN[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1080 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 1081 | #define BITP_CORE_SENSOR_GAIN_SENSOR_GAIN 0 /* Sensor Gain Adjustment */ |
| Vkadaba | 32:52445bef314d | 1082 | #define BITM_CORE_SENSOR_GAIN_SENSOR_GAIN 0xFFFFFFFF /* Sensor Gain Adjustment */ |
| Vkadaba | 5:0728bde67bdb | 1083 | |
| Vkadaba | 5:0728bde67bdb | 1084 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1085 | CORE_CHANNEL_SKIP[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1086 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 6:9d393a9677f4 | 1087 | #define BITP_CORE_CHANNEL_SKIP_CHANNEL_SKIP 0 /* Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 6:9d393a9677f4 | 1088 | #define BITM_CORE_CHANNEL_SKIP_CHANNEL_SKIP 0x000000FF /* Indicates If Channel Will Skip Some Measurement Cycles */ |
| Vkadaba | 5:0728bde67bdb | 1089 | |
| Vkadaba | 5:0728bde67bdb | 1090 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1091 | CORE_DIGITAL_SENSOR_CONFIG[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1092 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 1093 | #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 11 /* Number of Relevant Data Bits */ |
| Vkadaba | 5:0728bde67bdb | 1094 | #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 8 /* Number of Bytes to Read from the Sensor */ |
| Vkadaba | 5:0728bde67bdb | 1095 | #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 4 /* Data Bit Offset, Relative to Alignment */ |
| Vkadaba | 5:0728bde67bdb | 1096 | #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFT_ALIGNED 3 /* Data Alignment Within the Data Frame */ |
| Vkadaba | 5:0728bde67bdb | 1097 | #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTLE_ENDIAN 2 /* Data Endianness of Sensor Result */ |
| Vkadaba | 5:0728bde67bdb | 1098 | #define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0 /* Data Encoding of Sensor Result */ |
| Vkadaba | 5:0728bde67bdb | 1099 | #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 0x0000F800 /* Number of Relevant Data Bits */ |
| Vkadaba | 5:0728bde67bdb | 1100 | #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_READ_BYTES 0x00000700 /* Number of Bytes to Read from the Sensor */ |
| Vkadaba | 5:0728bde67bdb | 1101 | #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_BIT_OFFSET 0x000000F0 /* Data Bit Offset, Relative to Alignment */ |
| Vkadaba | 5:0728bde67bdb | 1102 | #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LEFT_ALIGNED 0x00000008 /* Data Alignment Within the Data Frame */ |
| Vkadaba | 5:0728bde67bdb | 1103 | #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_LITTLE_ENDIAN 0x00000004 /* Data Endianness of Sensor Result */ |
| Vkadaba | 5:0728bde67bdb | 1104 | #define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0x00000003 /* Data Encoding of Sensor Result */ |
| Vkadaba | 5:0728bde67bdb | 1105 | #define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE 0x00000000 /* Digital_Sensor_Coding: None/Invalid */ |
| Vkadaba | 5:0728bde67bdb | 1106 | #define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR 0x00000001 /* Digital_Sensor_Coding: Unipolar */ |
| Vkadaba | 32:52445bef314d | 1107 | #define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL 0x00000002 /* Digital_Sensor_Coding: Twos complement */ |
| Vkadaba | 32:52445bef314d | 1108 | #define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY 0x00000003 /* Digital_Sensor_Coding: Offset binary */ |
| Vkadaba | 5:0728bde67bdb | 1109 | |
| Vkadaba | 5:0728bde67bdb | 1110 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1111 | CORE_DIGITAL_SENSOR_ADDRESS[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1112 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 1113 | #define BITP_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0 /* I2C Address or Write Address Command for SPI Sensor */ |
| Vkadaba | 5:0728bde67bdb | 1114 | #define BITM_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0x000000FF /* I2C Address or Write Address Command for SPI Sensor */ |
| Vkadaba | 5:0728bde67bdb | 1115 | |
| Vkadaba | 5:0728bde67bdb | 1116 | /* ------------------------------------------------------------------------------------------------------------------------- |
| Vkadaba | 6:9d393a9677f4 | 1117 | CORE_DIGITAL_SENSOR_COMMS[n] Pos/Masks Description |
| Vkadaba | 5:0728bde67bdb | 1118 | ------------------------------------------------------------------------------------------------------------------------- */ |
| Vkadaba | 5:0728bde67bdb | 1119 | #define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 10 /* Configuration for Sensor SPI Protocol */ |
| Vkadaba | 5:0728bde67bdb | 1120 | #define BITP_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 5 /* Controls SCLK Frequency for I2C Sensors */ |
| Vkadaba | 5:0728bde67bdb | 1121 | #define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 1 /* Controls Clock Frequency for SPI Sensors */ |
| Vkadaba | 32:52445bef314d | 1122 | #define BITP_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0 /* Enable Digital Sensor Communications Register Parameters */ |
| Vkadaba | 5:0728bde67bdb | 1123 | #define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 0x00000C00 /* Configuration for Sensor SPI Protocol */ |
| Vkadaba | 5:0728bde67bdb | 1124 | #define BITM_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 0x00000060 /* Controls SCLK Frequency for I2C Sensors */ |
| Vkadaba | 5:0728bde67bdb | 1125 | #define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 0x0000001E /* Controls Clock Frequency for SPI Sensors */ |
| Vkadaba | 32:52445bef314d | 1126 | #define BITM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0x00000001 /* Enable Digital Sensor Communications Register Parameters */ |
| Vkadaba | 32:52445bef314d | 1127 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 0x00000000 /* SPI_Mode: Clock polarity = 0 Clock phase = 0 */ |
| Vkadaba | 32:52445bef314d | 1128 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 0x00000400 /* SPI_Mode: Clock polarity = 0 Clock phase = 1 */ |
| Vkadaba | 32:52445bef314d | 1129 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 0x00000800 /* SPI_Mode: Clock polarity = 1 Clock phase = 0 */ |
| Vkadaba | 32:52445bef314d | 1130 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 0x00000C00 /* SPI_Mode: Clock polarity = 1 Clock phase = 1 */ |
| Vkadaba | 5:0728bde67bdb | 1131 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_100K 0x00000000 /* I2C_Clock: 100kHz SCL */ |
| Vkadaba | 5:0728bde67bdb | 1132 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_400K 0x00000020 /* I2C_Clock: 400kHz SCL */ |
| Vkadaba | 5:0728bde67bdb | 1133 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 0x00000040 /* I2C_Clock: Reserved */ |
| Vkadaba | 5:0728bde67bdb | 1134 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED2 0x00000060 /* I2C_Clock: Reserved */ |
| Vkadaba | 6:9d393a9677f4 | 1135 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_8MHZ 0x00000000 /* SPI_Clock: 8MHz */ |
| Vkadaba | 6:9d393a9677f4 | 1136 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_4MHZ 0x00000002 /* SPI_Clock: 4MHz */ |
| Vkadaba | 6:9d393a9677f4 | 1137 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_2MHZ 0x00000004 /* SPI_Clock: 2MHz */ |
| Vkadaba | 6:9d393a9677f4 | 1138 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_1MHZ 0x00000006 /* SPI_Clock: 1MHz */ |
| Vkadaba | 6:9d393a9677f4 | 1139 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_500KHZ 0x00000008 /* SPI_Clock: 500kHz */ |
| Vkadaba | 6:9d393a9677f4 | 1140 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_250KHZ 0x0000000A /* SPI_Clock: 250kHz */ |
| Vkadaba | 6:9d393a9677f4 | 1141 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_125KHZ 0x0000000C /* SPI_Clock: 125kHz */ |
| Vkadaba | 6:9d393a9677f4 | 1142 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_62P5KHZ 0x0000000E /* SPI_Clock: 62.5kHz */ |
| Vkadaba | 6:9d393a9677f4 | 1143 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_31P3KHZ 0x00000010 /* SPI_Clock: 31.25kHz */ |
| Vkadaba | 6:9d393a9677f4 | 1144 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_15P6KHZ 0x00000012 /* SPI_Clock: 15.625kHz */ |
| Vkadaba | 6:9d393a9677f4 | 1145 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_7P8KHZ 0x00000014 /* SPI_Clock: 7.8kHz */ |
| Vkadaba | 6:9d393a9677f4 | 1146 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_3P9KHZ 0x00000016 /* SPI_Clock: 3.9kHz */ |
| Vkadaba | 6:9d393a9677f4 | 1147 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_1P9KHZ 0x00000018 /* SPI_Clock: 1.95kHz */ |
| Vkadaba | 8:2f2775c34640 | 1148 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_977HZ 0x0000001A /* SPI_Clock: 977Hz */ |
| Vkadaba | 6:9d393a9677f4 | 1149 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_488HZ 0x0000001C /* SPI_Clock: 488Hz */ |
| Vkadaba | 6:9d393a9677f4 | 1150 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_244HZ 0x0000001E /* SPI_Clock: 244Hz */ |
| Vkadaba | 32:52445bef314d | 1151 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT 0x00000000 /* Digital_Sensor_Comms_En: Default parameters used for digital sensor communications */ |
| Vkadaba | 32:52445bef314d | 1152 | #define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER 0x00000001 /* Digital_Sensor_Comms_En: User supplied parameters used for digital sensor communications */ |
| Vkadaba | 5:0728bde67bdb | 1153 | |
| Vkadaba | 5:0728bde67bdb | 1154 | |
| Vkadaba | 32:52445bef314d | 1155 | /* SPI Parameters */ |
| Vkadaba | 32:52445bef314d | 1156 | |
| Vkadaba | 32:52445bef314d | 1157 | /***** SPI */ |
| Vkadaba | 32:52445bef314d | 1158 | #define PARAM_SPI_SPI_STANDARD "LPT" /* A part must declare which SPI Standard it follows, either ADI or LPT */ |
| Vkadaba | 32:52445bef314d | 1159 | #define PARAM_SPI_CHIP_GRADE_VALUE 0 /* This is used to indicate speed grades/linearity. */ |
| Vkadaba | 32:52445bef314d | 1160 | #define PARAM_SPI_CHIP_REVISION_VALUE 0 /* This is used to indicate the silicon revision */ |
| Vkadaba | 32:52445bef314d | 1161 | #define PARAM_SPI_HAS_M_S_REGISTERS 0 /* If a design uses Master-Slave registers this must be set to true to enable relevant control bit fields */ |
| Vkadaba | 32:52445bef314d | 1162 | #define PARAM_SPI_M_S_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS the M-S Transfer bit field */ |
| Vkadaba | 32:52445bef314d | 1163 | #define PARAM_SPI_STREAM_MODE_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS of the stream mode transfer bit field */ |
| Vkadaba | 32:52445bef314d | 1164 | #define PARAM_SPI_MSB_AND_LSB_FIRST_SUPPORT 0 /* Determines if the parts supports MSB and LSB first options */ |
| Vkadaba | 32:52445bef314d | 1165 | #define PARAM_SPI_WIRE_MODE_SUPPORT "_4_WIRE" /* Configures which hardware SPI modes are supported */ |
| Vkadaba | 32:52445bef314d | 1166 | #define PARAM_SPI_WIRE_MODE_DEFAULT "_4_WIRE" /* Sets the default hardware SPI mode */ |
| Vkadaba | 32:52445bef314d | 1167 | #define PARAM_SPI_MULTI_IO_CHANNELS 1 /* Defines the number of SDIO pins supported by the SPI in Multi-IO Mode. Should be 1,2,4, or 8. */ |
| Vkadaba | 32:52445bef314d | 1168 | #define PARAM_SPI_LPT_STANDARD_VERSION "REV1_0" /* This is a string from the LPT_STANDARD_VERSION_OPTIONS array for the active LPT SPI Standard version */ |
| Vkadaba | 32:52445bef314d | 1169 | #define PARAM_SPI_HAS_CSB_PIN 1 /* Does the part have a csb pin? */ |
| Vkadaba | 32:52445bef314d | 1170 | #define PARAM_SPI_BUS_MODE_SUPPORT 1 /* When set to true, Bus mode is supported. */ |
| Vkadaba | 32:52445bef314d | 1171 | #define PARAM_SPI_ISOLATED_3_WIRE_SUPPORT 0 /* Does the part support the 3-wire isolate mode of operation */ |
| Vkadaba | 32:52445bef314d | 1172 | #define PARAM_SPI_DAISY_CHAIN_MODE_SUPPORT 0 /* When set to true, Daisy chain mode is supported. */ |
| Vkadaba | 32:52445bef314d | 1173 | #define PARAM_SPI_CHECK_GTE_1_MODE_SUPPORTED 1 /* This is used to check that at least mode is enabled */ |
| Vkadaba | 32:52445bef314d | 1174 | #define PARAM_SPI_INTERFACE_MODE_SWITCH "None" /* Valid options are 'None', 'HW' or 'SW' */ |
| Vkadaba | 32:52445bef314d | 1175 | #define PARAM_SPI_CRC_SUPPORT "CRC_CONFIGURABLE" /* Set to true to enable bit fields related to CRC. */ |
| Vkadaba | 32:52445bef314d | 1176 | #define PARAM_SPI_CRC_SUPPORT_ENABLED 0 /* Verilog output parameter for 'define */ |
| Vkadaba | 32:52445bef314d | 1177 | #define PARAM_SPI_CRC_SUPPORT_ENABLE 1 /* Configures if CRC features are enabled in the module */ |
| Vkadaba | 32:52445bef314d | 1178 | #define PARAM_SPI_LPT_STANDARD_VERSION_VALUE 2 /* Index value of the active LPT SPI Standard version */ |
| Vkadaba | 32:52445bef314d | 1179 | #define PARAM_SPI_ADDRESS_MODE_SUPPORT "_15_BIT" /* Configures which addressing modes are supported */ |
| Vkadaba | 32:52445bef314d | 1180 | #define PARAM_SPI_ADDRESS_MODE_DEFAULT "_15_BIT" /* Sets the default addressing mode */ |
| Vkadaba | 32:52445bef314d | 1181 | #define PARAM_SPI_ADDRESS_BUS_WIDTH 15 /* Verilog output parameter for 'define */ |
| Vkadaba | 32:52445bef314d | 1182 | #define PARAM_SPI_SLOW_IFACE_CTRL_SUPPORT 0 /* Does the part support the Slow Interface Control feature */ |
| Vkadaba | 32:52445bef314d | 1183 | #define PARAM_SPI_SOFT_RESET_0_BF_EXISTS 0 /* Used to control if the SOFT_RESET_0 bit field exists */ |
| Vkadaba | 32:52445bef314d | 1184 | #define PARAM_SPI_SOFT_RESET_1_BF_EXISTS 0 /* Used to control if the SOFT_RESET_1 bit field exists */ |
| Vkadaba | 32:52445bef314d | 1185 | #define PARAM_SPI_SEND_STATUS_SUPPORT "SEND_STATUS_CONFIGURABLE" /* Determines if and how the part supports the SEND_STATUS feature */ |
| Vkadaba | 32:52445bef314d | 1186 | #define PARAM_SPI_SEND_STATUS_SUPPORT_ENABLE 1 /* This is used to enable various send status features */ |
| Vkadaba | 32:52445bef314d | 1187 | #define PARAM_SPI_SPI_STANDARD_VERSION_VALUE 2 /* Value for SPI Standard VERSION bit field */ |
| Vkadaba | 32:52445bef314d | 1188 | #define PARAM_SPI_ENTITY_ACCESS_SUPPORT "ENTITY_ACCESS_ALWAYS" /* Configures which entity access mode(s) are supported */ |
| Vkadaba | 32:52445bef314d | 1189 | #define PARAM_SPI_ENTITY_ACCESS_SUPPORT_ENABLE 1 /* This is used to enable/disable Strict Entity Access features */ |
| Vkadaba | 32:52445bef314d | 1190 | #define PARAM_SPI_ENTITY_ACCESS_DEFAULT 1 /* Sets the default entity access mode */ |
| Vkadaba | 32:52445bef314d | 1191 | #define PARAM_SPI_CHIP_INDEX_EXISTS 0 /* Used to control if the CHIP_INDEX register and related bit field exists */ |
| Vkadaba | 32:52445bef314d | 1192 | #define PARAM_SPI_OFFSET_DEV_INDEX_EXISTS 0 /* Used to control if the OFFSET_DEV_INDEX bit field and registers exists */ |
| Vkadaba | 32:52445bef314d | 1193 | #define PARAM_SPI_DEV_INDEX_EXISTS 0 /* Used to control if the DEV_INDEX bit field and register exists */ |
| Vkadaba | 32:52445bef314d | 1194 | #define PARAM_SPI_STATUS_BIT_0_EXISTS 0 /* Sets EXIST for Status Bit 0 */ |
| Vkadaba | 32:52445bef314d | 1195 | #define PARAM_SPI_STATUS_BIT_1_EXISTS 0 /* Sets EXIST for Status Bit 1 */ |
| Vkadaba | 32:52445bef314d | 1196 | #define PARAM_SPI_STATUS_BIT_2_EXISTS 0 /* Sets EXIST for Status Bit 2 */ |
| Vkadaba | 32:52445bef314d | 1197 | #define PARAM_SPI_STATUS_BIT_3_EXISTS 0 /* Sets EXIST for Status Bit 3 */ |
| Vkadaba | 32:52445bef314d | 1198 | #define PARAM_SPI_STATUS_BIT_0_SWNAME "Status_Bit_0" /* Software Name for Status Bit 0 */ |
| Vkadaba | 32:52445bef314d | 1199 | #define PARAM_SPI_STATUS_BIT_1_SWNAME "Status_Bit_1" /* Software Name for Status Bit 1 */ |
| Vkadaba | 32:52445bef314d | 1200 | #define PARAM_SPI_STATUS_BIT_2_SWNAME "Status_Bit_2" /* Software Name for Status Bit 2 */ |
| Vkadaba | 32:52445bef314d | 1201 | #define PARAM_SPI_STATUS_BIT_3_SWNAME "Status_Bit_3" /* Software Name for Status Bit 3 */ |
| Vkadaba | 32:52445bef314d | 1202 | #define PARAM_SPI_CHIP_TYPE "P_ADC" /* This is a string that corresponds to one of the values in the CHIP_TYPE_OPTIONS array and corresponds to the type of chip being developed */ |
| Vkadaba | 32:52445bef314d | 1203 | #define PARAM_SPI_CHIP_TYPE_VALUE 7 /* Integer value corresponding to selected CHIP_TYPE, and is used as bit field enum value */ |
| Vkadaba | 32:52445bef314d | 1204 | #define PARAM_SPI_PRODUCT_ID_VALUE 32 /* This value is used to identify a specific generic. */ |
| Vkadaba | 32:52445bef314d | 1205 | #define PARAM_SPI_PRODUCT_ID_TRIM_BITS 4 /* This defines the number of PRODUCT_ID bits that can be fuse/trimmed. */ |
| Vkadaba | 32:52445bef314d | 1206 | |
| Vkadaba | 6:9d393a9677f4 | 1207 | #endif /* end ifndef _DEF_ADMW1001_REGISTERS_H */ |