Tick Tock / Mbed 2 deprecated CANary_9341

Dual CANbus monitor and instrumentation cluster supporting ILI9341 display controller

Dependencies:   SPI_TFTx2_ILI9341 TOUCH_TFTx2_ILI9341 TFT_fonts mbed

Fork of CANary by Tick Tock

PowerControl/EthernetPowerControl.cpp@189:439e113fec1c, 2014-05-17 (annotated)

Committer:
TickTock
Date:
Sat May 17 13:53:16 2014 +0000
Revision:
189:439e113fec1c
Parent:
4:8d7759f4fe7a 
renamed libraries to avoid conflict with originals

Who changed what in which revision?

UserRevisionLine numberNew contents of line
TickTock 4:8d7759f4fe7a 1 #include "EthernetPowerControl.h"
TickTock 4:8d7759f4fe7a 2
TickTock 4:8d7759f4fe7a 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
TickTock 4:8d7759f4fe7a 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
TickTock 4:8d7759f4fe7a 5 unsigned int tout;
TickTock 4:8d7759f4fe7a 6 /* Hardware MII Management for LPC176x devices. */
TickTock 4:8d7759f4fe7a 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
TickTock 4:8d7759f4fe7a 8 LPC_EMAC->MWTD = Value;
TickTock 4:8d7759f4fe7a 9
TickTock 4:8d7759f4fe7a 10 /* Wait utill operation completed */
TickTock 4:8d7759f4fe7a 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
TickTock 4:8d7759f4fe7a 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
TickTock 4:8d7759f4fe7a 13 break;
TickTock 4:8d7759f4fe7a 14 }
TickTock 4:8d7759f4fe7a 15 }
TickTock 4:8d7759f4fe7a 16 }
TickTock 4:8d7759f4fe7a 17
TickTock 4:8d7759f4fe7a 18 static unsigned short read_PHY (unsigned int PhyReg) {
TickTock 4:8d7759f4fe7a 19 /* Read a PHY register 'PhyReg'. */
TickTock 4:8d7759f4fe7a 20 unsigned int tout, val;
TickTock 4:8d7759f4fe7a 21
TickTock 4:8d7759f4fe7a 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
TickTock 4:8d7759f4fe7a 23 LPC_EMAC->MCMD = MCMD_READ;
TickTock 4:8d7759f4fe7a 24
TickTock 4:8d7759f4fe7a 25 /* Wait until operation completed */
TickTock 4:8d7759f4fe7a 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
TickTock 4:8d7759f4fe7a 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
TickTock 4:8d7759f4fe7a 28 break;
TickTock 4:8d7759f4fe7a 29 }
TickTock 4:8d7759f4fe7a 30 }
TickTock 4:8d7759f4fe7a 31 LPC_EMAC->MCMD = 0;
TickTock 4:8d7759f4fe7a 32 val = LPC_EMAC->MRDD;
TickTock 4:8d7759f4fe7a 33
TickTock 4:8d7759f4fe7a 34 return (val);
TickTock 4:8d7759f4fe7a 35 }
TickTock 4:8d7759f4fe7a 36
TickTock 4:8d7759f4fe7a 37 void EMAC_Init()
TickTock 4:8d7759f4fe7a 38 {
TickTock 4:8d7759f4fe7a 39 unsigned int tout,regv;
TickTock 4:8d7759f4fe7a 40 /* Power Up the EMAC controller. */
TickTock 4:8d7759f4fe7a 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
TickTock 4:8d7759f4fe7a 42
TickTock 4:8d7759f4fe7a 43 LPC_PINCON->PINSEL2 = 0x50150105;
TickTock 4:8d7759f4fe7a 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
TickTock 4:8d7759f4fe7a 45 LPC_PINCON->PINSEL3 |= 0x00000005;
TickTock 4:8d7759f4fe7a 46
TickTock 4:8d7759f4fe7a 47 /* Reset all EMAC internal modules. */
TickTock 4:8d7759f4fe7a 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
TickTock 4:8d7759f4fe7a 49 MAC1_SIM_RES | MAC1_SOFT_RES;
TickTock 4:8d7759f4fe7a 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
TickTock 4:8d7759f4fe7a 51
TickTock 4:8d7759f4fe7a 52 /* A short delay after reset. */
TickTock 4:8d7759f4fe7a 53 for (tout = 100; tout; tout--);
TickTock 4:8d7759f4fe7a 54
TickTock 4:8d7759f4fe7a 55 /* Initialize MAC control registers. */
TickTock 4:8d7759f4fe7a 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
TickTock 4:8d7759f4fe7a 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
TickTock 4:8d7759f4fe7a 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
TickTock 4:8d7759f4fe7a 59 LPC_EMAC->CLRT = CLRT_DEF;
TickTock 4:8d7759f4fe7a 60 LPC_EMAC->IPGR = IPGR_DEF;
TickTock 4:8d7759f4fe7a 61
TickTock 4:8d7759f4fe7a 62 /* Enable Reduced MII interface. */
TickTock 4:8d7759f4fe7a 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
TickTock 4:8d7759f4fe7a 64
TickTock 4:8d7759f4fe7a 65 /* Reset Reduced MII Logic. */
TickTock 4:8d7759f4fe7a 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
TickTock 4:8d7759f4fe7a 67 for (tout = 100; tout; tout--);
TickTock 4:8d7759f4fe7a 68 LPC_EMAC->SUPP = 0;
TickTock 4:8d7759f4fe7a 69
TickTock 4:8d7759f4fe7a 70 /* Put the DP83848C in reset mode */
TickTock 4:8d7759f4fe7a 71 write_PHY (PHY_REG_BMCR, 0x8000);
TickTock 4:8d7759f4fe7a 72
TickTock 4:8d7759f4fe7a 73 /* Wait for hardware reset to end. */
TickTock 4:8d7759f4fe7a 74 for (tout = 0; tout < 0x100000; tout++) {
TickTock 4:8d7759f4fe7a 75 regv = read_PHY (PHY_REG_BMCR);
TickTock 4:8d7759f4fe7a 76 if (!(regv & 0x8000)) {
TickTock 4:8d7759f4fe7a 77 /* Reset complete */
TickTock 4:8d7759f4fe7a 78 break;
TickTock 4:8d7759f4fe7a 79 }
TickTock 4:8d7759f4fe7a 80 }
TickTock 4:8d7759f4fe7a 81 }
TickTock 4:8d7759f4fe7a 82
TickTock 4:8d7759f4fe7a 83
TickTock 4:8d7759f4fe7a 84 void PHY_PowerDown()
TickTock 4:8d7759f4fe7a 85 {
TickTock 4:8d7759f4fe7a 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
TickTock 4:8d7759f4fe7a 87 EMAC_Init(); //init EMAC if it is not already init'd
TickTock 4:8d7759f4fe7a 88
TickTock 4:8d7759f4fe7a 89 unsigned int regv;
TickTock 4:8d7759f4fe7a 90 regv = read_PHY(PHY_REG_BMCR);
TickTock 4:8d7759f4fe7a 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
TickTock 4:8d7759f4fe7a 92 regv = read_PHY(PHY_REG_BMCR);
TickTock 4:8d7759f4fe7a 93
TickTock 4:8d7759f4fe7a 94 //shouldn't need the EMAC now.
TickTock 4:8d7759f4fe7a 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
TickTock 4:8d7759f4fe7a 96
TickTock 4:8d7759f4fe7a 97 //and turn off the PHY OSC
TickTock 4:8d7759f4fe7a 98 LPC_GPIO1->FIODIR |= 0x8000000;
TickTock 4:8d7759f4fe7a 99 LPC_GPIO1->FIOCLR = 0x8000000;
TickTock 4:8d7759f4fe7a 100 }
TickTock 4:8d7759f4fe7a 101
TickTock 4:8d7759f4fe7a 102 void PHY_PowerUp()
TickTock 4:8d7759f4fe7a 103 {
TickTock 4:8d7759f4fe7a 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
TickTock 4:8d7759f4fe7a 105 EMAC_Init(); //init EMAC if it is not already init'd
TickTock 4:8d7759f4fe7a 106
TickTock 4:8d7759f4fe7a 107 LPC_GPIO1->FIODIR |= 0x8000000;
TickTock 4:8d7759f4fe7a 108 LPC_GPIO1->FIOSET = 0x8000000;
TickTock 4:8d7759f4fe7a 109
TickTock 4:8d7759f4fe7a 110 //wait for osc to be stable
TickTock 4:8d7759f4fe7a 111 wait_ms(200);
TickTock 4:8d7759f4fe7a 112
TickTock 4:8d7759f4fe7a 113 unsigned int regv;
TickTock 4:8d7759f4fe7a 114 regv = read_PHY(PHY_REG_BMCR);
TickTock 4:8d7759f4fe7a 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
TickTock 4:8d7759f4fe7a 116 regv = read_PHY(PHY_REG_BMCR);
TickTock 4:8d7759f4fe7a 117 }
TickTock 4:8d7759f4fe7a 118
TickTock 4:8d7759f4fe7a 119 void PHY_EnergyDetect_Enable()
TickTock 4:8d7759f4fe7a 120 {
TickTock 4:8d7759f4fe7a 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
TickTock 4:8d7759f4fe7a 122 EMAC_Init(); //init EMAC if it is not already init'd
TickTock 4:8d7759f4fe7a 123
TickTock 4:8d7759f4fe7a 124 unsigned int regv;
TickTock 4:8d7759f4fe7a 125 regv = read_PHY(PHY_REG_EDCR);
TickTock 4:8d7759f4fe7a 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
TickTock 4:8d7759f4fe7a 127 regv = read_PHY(PHY_REG_EDCR);
TickTock 4:8d7759f4fe7a 128 }
TickTock 4:8d7759f4fe7a 129
TickTock 4:8d7759f4fe7a 130 void PHY_EnergyDetect_Disable()
TickTock 4:8d7759f4fe7a 131 {
TickTock 4:8d7759f4fe7a 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
TickTock 4:8d7759f4fe7a 133 EMAC_Init(); //init EMAC if it is not already init'd
TickTock 4:8d7759f4fe7a 134 unsigned int regv;
TickTock 4:8d7759f4fe7a 135 regv = read_PHY(PHY_REG_EDCR);
TickTock 4:8d7759f4fe7a 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
TickTock 4:8d7759f4fe7a 137 regv = read_PHY(PHY_REG_EDCR);
TickTock 4:8d7759f4fe7a 138 }