Erik - / SLCD

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   FRDM-KL46Z LCD rtc Demo KL46Z EE202A_HW1_MH SignalGenerator ... more

LCD_config.h@0:d04758e76d5b, 2014-01-14 (annotated)

Committer:
Sissors
Date:
Tue Jan 14 07:00:15 2014 +0000
Revision:
0:d04758e76d5b
v0.01

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 0:d04758e76d5b 1 #ifndef __LCDConfig_H_
Sissors 0:d04758e76d5b 2 #define __LCDConfig_H_
Sissors 0:d04758e76d5b 3
Sissors 0:d04758e76d5b 4 #include "FRDM-s401.h" // 4x7 segdisplay
Sissors 0:d04758e76d5b 5
Sissors 0:d04758e76d5b 6
Sissors 0:d04758e76d5b 7 #if 1 // VREF to VLL1
Sissors 0:d04758e76d5b 8 /* Following configuration is used for LCD default initialization */
Sissors 0:d04758e76d5b 9 #define _LCDRVEN (1) //
Sissors 0:d04758e76d5b 10 #define _LCDRVTRIM (8) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
Sissors 0:d04758e76d5b 11 #define _LCDCPSEL (1) // charge pump select 0 or 1
Sissors 0:d04758e76d5b 12 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
Sissors 0:d04758e76d5b 13 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
Sissors 0:d04758e76d5b 14 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
Sissors 0:d04758e76d5b 15
Sissors 0:d04758e76d5b 16 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
Sissors 0:d04758e76d5b 17 #define _LCDSUPPLY (1)
Sissors 0:d04758e76d5b 18 #define _LCDHREF (0) // 0 or 1
Sissors 0:d04758e76d5b 19 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
Sissors 0:d04758e76d5b 20 #define _LCDLCK (1) //Any number between 0 and 7
Sissors 0:d04758e76d5b 21 #define _LCDBLINKRATE (3) //Any number between 0 and 7
Sissors 0:d04758e76d5b 22
Sissors 0:d04758e76d5b 23
Sissors 0:d04758e76d5b 24 #else //VLL3 to VDD internally
Sissors 0:d04758e76d5b 25 /* Following configuration is used for LCD default initialization */
Sissors 0:d04758e76d5b 26 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
Sissors 0:d04758e76d5b 27 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
Sissors 0:d04758e76d5b 28 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
Sissors 0:d04758e76d5b 29 #define _LCDSUPPLY (0)
Sissors 0:d04758e76d5b 30 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
Sissors 0:d04758e76d5b 31 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
Sissors 0:d04758e76d5b 32 #define _LCDRVTRIM (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
Sissors 0:d04758e76d5b 33 #define _LCDHREF (0) // 0 or 1
Sissors 0:d04758e76d5b 34 #define _LCDCPSEL (1) // 0 or 1
Sissors 0:d04758e76d5b 35 #define _LCDRVEN (0) //
Sissors 0:d04758e76d5b 36 #define _LCDBLINKRATE (3) //Any number between 0 and 7
Sissors 0:d04758e76d5b 37 #define _LCDLCK (0) //Any number between 0 and 7
Sissors 0:d04758e76d5b 38
Sissors 0:d04758e76d5b 39 #endif
Sissors 0:d04758e76d5b 40
Sissors 0:d04758e76d5b 41
Sissors 0:d04758e76d5b 42
Sissors 0:d04758e76d5b 43
Sissors 0:d04758e76d5b 44 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 0 ~|~|~|~|~|~|~|~|~|~|~|~|~*/
Sissors 0:d04758e76d5b 45 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
Sissors 0:d04758e76d5b 46 #define _LCDINTENABLE (1)
Sissors 0:d04758e76d5b 47
Sissors 0:d04758e76d5b 48 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 1 ~|~|~|~|~|~|~|~|~|~|~|~|~|*/
Sissors 0:d04758e76d5b 49 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
Sissors 0:d04758e76d5b 50 #define _LCDFRAMEINTERRUPT (0) //0 Disable Frame Frequency Interrupt
Sissors 0:d04758e76d5b 51 //1 Enable an LCD interrupt that coincides with the LCD frame frequency
Sissors 0:d04758e76d5b 52 #define _LCDFULLCPLDIRIVE (0) // 0 GPIO shared with the LCD. Inputs levels and internal pullup reference to VDD
Sissors 0:d04758e76d5b 53 // 1 If VSUPPLY=11and RVEN=0. Inputs levels and internal pullup reference to VLL3
Sissors 0:d04758e76d5b 54 #define _LCDWAITMODE (0) // 0 Allows the LCD driver and charge pump to continue running during wait mode
Sissors 0:d04758e76d5b 55 // 1 Disable the LCD when the MCU goes into wait mode
Sissors 0:d04758e76d5b 56 #define _LCDSTOPMODE (0) // 0 Allows the LCD driver and charge pump to continue running during stop2 or stop3
Sissors 0:d04758e76d5b 57
Sissors 0:d04758e76d5b 58 // 1 Disable the LCD when and charge pump when the MCU goes into stop2 or stop3
Sissors 0:d04758e76d5b 59
Sissors 0:d04758e76d5b 60 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Voltage Supply Register ~|~|~|~|~|~|~|~|~|~|~|~*/
Sissors 0:d04758e76d5b 61 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
Sissors 0:d04758e76d5b 62 #define _LCDHIGHREF (0) //0 Divide input VIREG=1.0v
Sissors 0:d04758e76d5b 63 //1 Do not divide the input VIREG=1.67v
Sissors 0:d04758e76d5b 64 #define _LCDBBYPASS (0) //Determines whether the internal LCD op amp buffer is bypassed
Sissors 0:d04758e76d5b 65 //0 Buffered mode
Sissors 0:d04758e76d5b 66 //1 Unbuffered mode
Sissors 0:d04758e76d5b 67
Sissors 0:d04758e76d5b 68 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Regulated Voltage Control |~|~|~|~|~|~|~|~|~|~*/
Sissors 0:d04758e76d5b 69 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
Sissors 0:d04758e76d5b 70 #define _LCDCONTRAST (1) //Contrast by software 0 -- Disable 1-- Enable
Sissors 0:d04758e76d5b 71 #define _LVLCONTRAST (0) //Any number between 0 and 15, if the number is bigger the glass get darker
Sissors 0:d04758e76d5b 72
Sissors 0:d04758e76d5b 73 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Blink Control Register ~|~|~|~|~|~|~|~|~|~|~|~*/
Sissors 0:d04758e76d5b 74 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
Sissors 0:d04758e76d5b 75 #define _LCDBLINKCONTROL (0) //0 Disable blink mode
Sissors 0:d04758e76d5b 76 //1 Enable blink mode
Sissors 0:d04758e76d5b 77 #define _LCDALTMODE (0) //0 Normal display
Sissors 0:d04758e76d5b 78 //1 Alternate display for 4 backplanes or less the LCD backplane sequencer changes to otuput an alternate display
Sissors 0:d04758e76d5b 79 #define _LCDBLANKDISP (0) //0 Do not blank display
Sissors 0:d04758e76d5b 80 //1 Blank display if you put it in 0 the text before blank is manteined
Sissors 0:d04758e76d5b 81 #define _LCDBLINKMODE (0) //0 Display blank during the blink period
Sissors 0:d04758e76d5b 82 //1 Display alternate displat during blink period (Ignored if duty is 5 or greater)
Sissors 0:d04758e76d5b 83
Sissors 0:d04758e76d5b 84
Sissors 0:d04758e76d5b 85 //Calculated values
Sissors 0:d04758e76d5b 86 #define _LCDUSEDPINS (_LCDFRONTPLANES + _LCDBACKPLANES)
Sissors 0:d04758e76d5b 87 #define _LCDDUTY (_LCDBACKPLANES-1) //Any number between 0 and 7
Sissors 0:d04758e76d5b 88 #define LCD_WF_BASE LCD_WF3TO0
Sissors 0:d04758e76d5b 89
Sissors 0:d04758e76d5b 90 // General definitions used by the LCD library
Sissors 0:d04758e76d5b 91 #define SymbolON(LCDn,bit) *((uint8 *)&LCD_WF_BASE + LCDn) |= (1<<(bit))
Sissors 0:d04758e76d5b 92 #define SymbolOFF(LCDn,bit) *((uint8 *)&LCD_WF_BASE + LCDn) &= ~(1<<(bit))
Sissors 0:d04758e76d5b 93 //#define LCD_WF(x) *((uint8 *)&LCD_WF_BASE + x)
Sissors 0:d04758e76d5b 94
Sissors 0:d04758e76d5b 95 /*LCD Fault Detections Consts*/
Sissors 0:d04758e76d5b 96 #define FP_TYPE 0x00 // pin is a Front Plane
Sissors 0:d04758e76d5b 97 #define BP_TYPE 0x80 // pin is Back Plane
Sissors 0:d04758e76d5b 98
Sissors 0:d04758e76d5b 99 // Fault Detect Preescaler Options
Sissors 0:d04758e76d5b 100 #define FDPRS_1 0
Sissors 0:d04758e76d5b 101 #define FDPRS_2 1
Sissors 0:d04758e76d5b 102 #define FDPRS_4 2
Sissors 0:d04758e76d5b 103 #define FDPRS_8 3
Sissors 0:d04758e76d5b 104 #define FDPRS_16 4
Sissors 0:d04758e76d5b 105 #define FDPRS_32 5
Sissors 0:d04758e76d5b 106 #define FDPRS_64 6
Sissors 0:d04758e76d5b 107 #define FDPRS_128 7
Sissors 0:d04758e76d5b 108
Sissors 0:d04758e76d5b 109 // Fault Detect Sample Window Width Values
Sissors 0:d04758e76d5b 110 #define FDSWW_4 0
Sissors 0:d04758e76d5b 111 #define FDSWW_8 1
Sissors 0:d04758e76d5b 112 #define FDSWW_16 2
Sissors 0:d04758e76d5b 113 #define FDSWW_32 3
Sissors 0:d04758e76d5b 114 #define FDSWW_64 4
Sissors 0:d04758e76d5b 115 #define FDSWW_128 5
Sissors 0:d04758e76d5b 116 #define FDSWW_256 6
Sissors 0:d04758e76d5b 117 #define FDSWW_512 7
Sissors 0:d04758e76d5b 118
Sissors 0:d04758e76d5b 119 /*
Sissors 0:d04758e76d5b 120 Mask Bit definitions used f
Sissors 0:d04758e76d5b 121 */
Sissors 0:d04758e76d5b 122 #define mBIT0 1
Sissors 0:d04758e76d5b 123 #define mBIT1 2
Sissors 0:d04758e76d5b 124 #define mBIT2 4
Sissors 0:d04758e76d5b 125 #define mBIT3 8
Sissors 0:d04758e76d5b 126 #define mBIT4 16
Sissors 0:d04758e76d5b 127 #define mBIT5 32
Sissors 0:d04758e76d5b 128 #define mBIT6 64
Sissors 0:d04758e76d5b 129 #define mBIT7 128
Sissors 0:d04758e76d5b 130 #define mBIT8 256
Sissors 0:d04758e76d5b 131 #define mBIT9 512
Sissors 0:d04758e76d5b 132 #define mBIT10 1024
Sissors 0:d04758e76d5b 133 #define mBIT11 2048
Sissors 0:d04758e76d5b 134 #define mBIT12 4096
Sissors 0:d04758e76d5b 135 #define mBIT13 8192
Sissors 0:d04758e76d5b 136 #define mBIT14 16384
Sissors 0:d04758e76d5b 137 #define mBIT15 32768
Sissors 0:d04758e76d5b 138 #define mBIT16 65536
Sissors 0:d04758e76d5b 139 #define mBIT17 131072
Sissors 0:d04758e76d5b 140 #define mBIT18 262144
Sissors 0:d04758e76d5b 141 #define mBIT19 524288
Sissors 0:d04758e76d5b 142 #define mBIT20 1048576
Sissors 0:d04758e76d5b 143 #define mBIT21 2097152
Sissors 0:d04758e76d5b 144 #define mBIT22 4194304
Sissors 0:d04758e76d5b 145 #define mBIT23 8388608
Sissors 0:d04758e76d5b 146 #define mBIT24 16777216
Sissors 0:d04758e76d5b 147 #define mBIT25 33554432
Sissors 0:d04758e76d5b 148 #define mBIT26 67108864
Sissors 0:d04758e76d5b 149 #define mBIT27 134217728
Sissors 0:d04758e76d5b 150 #define mBIT28 268435456
Sissors 0:d04758e76d5b 151 #define mBIT29 536870912
Sissors 0:d04758e76d5b 152 #define mBIT30 1073741824
Sissors 0:d04758e76d5b 153 #define mBIT31 2147483648
Sissors 0:d04758e76d5b 154
Sissors 0:d04758e76d5b 155 #define mBIT32 1
Sissors 0:d04758e76d5b 156 #define mBIT33 2
Sissors 0:d04758e76d5b 157 #define mBIT34 4
Sissors 0:d04758e76d5b 158 #define mBIT35 8
Sissors 0:d04758e76d5b 159 #define mBIT36 16
Sissors 0:d04758e76d5b 160 #define mBIT37 32
Sissors 0:d04758e76d5b 161 #define mBIT38 64
Sissors 0:d04758e76d5b 162 #define mBIT39 128
Sissors 0:d04758e76d5b 163 #define mBIT40 256
Sissors 0:d04758e76d5b 164 #define mBIT41 512
Sissors 0:d04758e76d5b 165 #define mBIT42 1024
Sissors 0:d04758e76d5b 166 #define mBIT43 2048
Sissors 0:d04758e76d5b 167 #define mBIT44 4096
Sissors 0:d04758e76d5b 168 #define mBIT45 8192
Sissors 0:d04758e76d5b 169 #define mBIT46 16384
Sissors 0:d04758e76d5b 170 #define mBIT47 32768
Sissors 0:d04758e76d5b 171 #define mBIT48 65536
Sissors 0:d04758e76d5b 172 #define mBIT49 131072
Sissors 0:d04758e76d5b 173 #define mBIT50 262144
Sissors 0:d04758e76d5b 174 #define mBIT51 524288
Sissors 0:d04758e76d5b 175 #define mBIT52 1048576
Sissors 0:d04758e76d5b 176 #define mBIT53 2097152
Sissors 0:d04758e76d5b 177 #define mBIT54 4194304
Sissors 0:d04758e76d5b 178 #define mBIT55 8388608
Sissors 0:d04758e76d5b 179 #define mBIT56 16777216
Sissors 0:d04758e76d5b 180 #define mBIT57 33554432
Sissors 0:d04758e76d5b 181 #define mBIT58 67108864
Sissors 0:d04758e76d5b 182 #define mBIT59 134217728
Sissors 0:d04758e76d5b 183 #define mBIT60 268435456
Sissors 0:d04758e76d5b 184 #define mBIT61 536870912
Sissors 0:d04758e76d5b 185 #define mBIT62 1073741824
Sissors 0:d04758e76d5b 186 #define mBIT63 2147483648
Sissors 0:d04758e76d5b 187
Sissors 0:d04758e76d5b 188 #endif /* __LCDConfig_H_ */