dma_11u6x.h

00001 /*
00002  * @brief LPC11u6x DMA chip driver
00003  *
00004  * @note
00005  * Copyright(C) NXP Semiconductors, 2013
00006  * All rights reserved.
00007  *
00008  * @par
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * LPC products.  This software is supplied "AS IS" without any warranties of
00012  * any kind, and NXP Semiconductors and its licensor disclaim any and
00013  * all warranties, express or implied, including all implied warranties of
00014  * merchantability, fitness for a particular purpose and non-infringement of
00015  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00016  * or liability for the use of the software, conveys no license or rights under any
00017  * patent, copyright, mask work right, or any other intellectual property rights in
00018  * or to any products. NXP Semiconductors reserves the right to make changes
00019  * in the software without notification. NXP Semiconductors also makes no
00020  * representation or warranty that such application will be suitable for the
00021  * specified use without further testing or modification.
00022  *
00023  * @par
00024  * Permission to use, copy, modify, and distribute this software and its
00025  * documentation is hereby granted, under NXP Semiconductors' and its
00026  * licensor's relevant copyrights in the software, without fee, provided that it
00027  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00028  * copyright, permission, and disclaimer notice must appear in all copies of
00029  * this code.
00030  */
00031 
00032 #ifndef __DMA_11U6X_H_
00033 #define __DMA_11U6X_H_
00034 
00035 #include "lpc_types.h"
00036 #include "clock_11u6x.h"
00037 
00038 #ifdef __cplusplus
00039 extern "C" {
00040 #endif
00041 
00042 /** @defgroup DMA_11U6X CHIP: LPC11u6x DMA Controller driver
00043  * @ingroup CHIP_11U6X_Drivers
00044  * @{
00045  */
00046 
00047 /**
00048  * @brief DMA Controller shared registers structure
00049  */
00050 typedef struct {                    /*!< DMA shared registers structure */
00051     __IO uint32_t  ENABLESET ;       /*!< DMA Channel Enable read and Set for all DMA channels */
00052     __I  uint32_t  RESERVED0;
00053     __O  uint32_t  ENABLECLR ;       /*!< DMA Channel Enable Clear for all DMA channels */
00054     __I  uint32_t  RESERVED1;
00055     __I  uint32_t  ACTIVE ;          /*!< DMA Channel Active status for all DMA channels */
00056     __I  uint32_t  RESERVED2;
00057     __I  uint32_t  BUSY ;            /*!< DMA Channel Busy status for all DMA channels */
00058     __I  uint32_t  RESERVED3;
00059     __IO uint32_t  ERRINT ;          /*!< DMA Error Interrupt status for all DMA channels */
00060     __I  uint32_t  RESERVED4;
00061     __IO uint32_t  INTENSET ;        /*!< DMA Interrupt Enable read and Set for all DMA channels */
00062     __I  uint32_t  RESERVED5;
00063     __O  uint32_t  INTENCLR ;        /*!< DMA Interrupt Enable Clear for all DMA channels */
00064     __I  uint32_t  RESERVED6;
00065     __IO uint32_t  INTA ;            /*!< DMA Interrupt A status for all DMA channels */
00066     __I  uint32_t  RESERVED7;
00067     __IO uint32_t  INTB ;            /*!< DMA Interrupt B status for all DMA channels */
00068     __I  uint32_t  RESERVED8;
00069     __O  uint32_t  SETVALID ;        /*!< DMA Set ValidPending control bits for all DMA channels */
00070     __I  uint32_t  RESERVED9;
00071     __O  uint32_t  SETTRIG ;         /*!< DMA Set Trigger control bits for all DMA channels */
00072     __I  uint32_t  RESERVED10;
00073     __O  uint32_t  ABORT ;           /*!< DMA Channel Abort control for all DMA channels */
00074 } LPC_DMA_COMMON_T;
00075 
00076 /**
00077  * @brief DMA Controller shared registers structure
00078  */
00079 typedef struct {                    /*!< DMA channel register structure */
00080     __IO uint32_t  CFG ;             /*!< DMA Configuration register */
00081     __I  uint32_t  CTLSTAT ;         /*!< DMA Control and status register */
00082     __IO uint32_t  XFERCFG ;         /*!< DMA Transfer configuration register */
00083     __I  uint32_t  RESERVED;
00084 } LPC_DMA_CHANNEL_T;
00085 
00086 
00087 #define DMA_CH15 15
00088 
00089 /* On LPC412x, Max DMA channel is 22 */
00090 #define MAX_DMA_CHANNEL         (DMA_CH15 + 1)
00091 
00092 /**
00093  * @brief DMA Controller register block structure
00094  */
00095 typedef struct {                    /*!< DMA Structure */
00096     __IO uint32_t  CTRL ;            /*!< DMA control register */
00097     __I  uint32_t  INTSTAT ;         /*!< DMA Interrupt status register */
00098     __IO uint32_t  SRAMBASE ;        /*!< DMA SRAM address of the channel configuration table */
00099     __I  uint32_t  RESERVED2[5];
00100     LPC_DMA_COMMON_T DMACOMMON[1];  /*!< DMA shared channel (common) registers */
00101     __I  uint32_t  RESERVED0[225];
00102     LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL];   /*!< DMA channel registers */
00103 } LPC_DMA_T;
00104 
00105 /** @defgroup DMA_COMMONDRV_11U6X CHIP: LPC11u6x DMA Controller driver common functions
00106  * @{
00107  */
00108 
00109 /**
00110  * @brief   Initialize DMA controller
00111  * @param   pDMA    : The base of DMA controller on the chip
00112  * @return  Nothing
00113  */
00114 STATIC INLINE void Chip_DMA_Init(LPC_DMA_T *pDMA)
00115 {
00116     (void) pDMA;
00117     Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_DMA );
00118 }
00119 
00120 /**
00121  * @brief   De-Initialize DMA controller
00122  * @param   pDMA    : The base of DMA controller on the chip
00123  * @return  Nothing
00124  */
00125 STATIC INLINE void Chip_DMA_DeInit(LPC_DMA_T *pDMA)
00126 {
00127     (void) pDMA;
00128     Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_DMA );
00129 }
00130 
00131 /**
00132  * @brief   Enable DMA controller
00133  * @param   pDMA    : The base of DMA controller on the chip
00134  * @return  Nothing
00135  */
00136 STATIC INLINE void Chip_DMA_Enable(LPC_DMA_T *pDMA)
00137 {
00138     pDMA->CTRL  = 1;
00139 }
00140 
00141 /**
00142  * @brief   Disable DMA controller
00143  * @param   pDMA    : The base of DMA controller on the chip
00144  * @return  Nothing
00145  */
00146 STATIC INLINE void Chip_DMA_Disable(LPC_DMA_T *pDMA)
00147 {
00148     pDMA->CTRL  = 0;
00149 }
00150 
00151 /* DMA interrupt status bits (common) */
00152 #define DMA_INTSTAT_ACTIVEINT       0x2     /*!< Summarizes whether any enabled interrupts are pending */
00153 #define DMA_INTSTAT_ACTIVEERRINT    0x4     /*!< Summarizes whether any error interrupts are pending */
00154 
00155 /**
00156  * @brief   Get pending interrupt or error interrupts
00157  * @param   pDMA    : The base of DMA controller on the chip
00158  * @return  An Or'ed value of DMA_INTSTAT_* types
00159  * @note    If any DMA channels have an active interrupt or error interrupt
00160  *          pending, this functional will a common status that applies to all
00161  *          channels.
00162  */
00163 STATIC INLINE uint32_t Chip_DMA_GetIntStatus(LPC_DMA_T *pDMA)
00164 {
00165     return pDMA->INTSTAT ;
00166 }
00167 
00168 
00169 
00170 /* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase()
00171    function if a DMA SRAM table is needed. */
00172 extern DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL];
00173 
00174 /**
00175  * @brief   Set DMA controller SRAM base address
00176  * @param   pDMA    : The base of DMA controller on the chip
00177  * @param   base    : The base address where the DMA descriptors will be stored
00178  * @return  Nothing
00179  * @note    A 256 byte block of memory aligned on a 256 byte boundary must be
00180  *          provided for this function. It sets the base address used for
00181  *          DMA descriptor table (16 descriptors total that use 16 bytes each).<br>
00182  *
00183  *          A pre-defined table with correct alignment can be used for this
00184  *          function by calling Chip_DMA_SetSRAMBase(LPC_DMA, DMA_ADDR(Chip_DMA_Table));
00185  */
00186 STATIC INLINE void Chip_DMA_SetSRAMBase(LPC_DMA_T *pDMA, uint32_t base)
00187 {
00188     pDMA->SRAMBASE  = base;
00189 }
00190 
00191 /**
00192  * @brief   Returns DMA controller SRAM base address
00193  * @param   pDMA    : The base of DMA controller on the chip
00194  * @return  The base address where the DMA descriptors are stored
00195  */
00196 STATIC INLINE uint32_t Chip_DMA_GetSRAMBase(LPC_DMA_T *pDMA)
00197 {
00198     return pDMA->SRAMBASE ;
00199 }
00200 
00201 /**
00202  * @}
00203  */
00204 
00205 /** @defgroup DMA_COMMON_11U6X CHIP: LPC11u6x DMA Controller driver common channel functions
00206  * @{
00207  */
00208 
00209 /**
00210  * @brief   Enables a single DMA channel
00211  * @param   pDMA    : The base of DMA controller on the chip
00212  * @param   ch      : DMA channel ID
00213  * @return  Nothing
00214  */
00215 STATIC INLINE void Chip_DMA_EnableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00216 {
00217     pDMA->DMACOMMON [0].ENABLESET  = (1 << ch);
00218 }
00219 
00220 /**
00221  * @brief   Disables a single DMA channel
00222  * @param   pDMA    : The base of DMA controller on the chip
00223  * @param   ch      : DMA channel ID
00224  * @return  Nothing
00225  */
00226 STATIC INLINE void Chip_DMA_DisableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00227 {
00228     pDMA->DMACOMMON [0].ENABLECLR  = (1 << ch);
00229 }
00230 
00231 /**
00232  * @brief   Returns all enabled DMA channels
00233  * @param   pDMA    : The base of DMA controller on the chip
00234  * @return  An Or'ed value of all enabled DMA channels (0 - 15)
00235  * @note    A high values in bits 0 .. 15 in the return values indicates
00236  *          that the channel for that bit (bit 0 = channel 0, bit 1 -
00237  *          channel 1, etc.) is enabled. A low state is disabled.
00238  */
00239 STATIC INLINE uint32_t Chip_DMA_GetEnabledChannels(LPC_DMA_T *pDMA)
00240 {
00241     return pDMA->DMACOMMON [0].ENABLESET ;
00242 }
00243 
00244 /**
00245  * @brief   Returns all active DMA channels
00246  * @param   pDMA    : The base of DMA controller on the chip
00247  * @return  An Or'ed value of all active DMA channels (0 - 15)
00248  * @note    A high values in bits 0 .. 15 in the return values indicates
00249  *          that the channel for that bit (bit 0 = channel 0, bit 1 -
00250  *          channel 1, etc.) is active. A low state is inactive. A active
00251  *          channel indicates that a DMA operation has been started but
00252  *          not yet fully completed.
00253  */
00254 STATIC INLINE uint32_t Chip_DMA_GetActiveChannels(LPC_DMA_T *pDMA)
00255 {
00256     return pDMA->DMACOMMON [0].ACTIVE ;
00257 }
00258 
00259 /**
00260  * @brief   Returns all busy DMA channels
00261  * @param   pDMA    : The base of DMA controller on the chip
00262  * @return  An Or'ed value of all busy DMA channels (0 - 15)
00263  * @note    A high values in bits 0 .. 15 in the return values indicates
00264  *          that the channel for that bit (bit 0 = channel 0, bit 1 -
00265  *          channel 1, etc.) is busy. A low state is not busy. A DMA
00266  *          channel is considered busy when there is any operation
00267  *          related to that channel in the DMA controller�s internal
00268  *          pipeline.
00269  */
00270 STATIC INLINE uint32_t Chip_DMA_GetBusyChannels(LPC_DMA_T *pDMA)
00271 {
00272     return pDMA->DMACOMMON [0].BUSY ;
00273 }
00274 
00275 /**
00276  * @brief   Returns pending error interrupt status for all DMA channels
00277  * @param   pDMA    : The base of DMA controller on the chip
00278  * @return  An Or'ed value of all channels (0 - 15) error interrupt status
00279  * @note    A high values in bits 0 .. 15 in the return values indicates
00280  *          that the channel for that bit (bit 0 = channel 0, bit 1 -
00281  *          channel 1, etc.) has a pending error interrupt. A low state
00282  *          indicates no error interrupt.
00283  */
00284 STATIC INLINE uint32_t Chip_DMA_GetErrorIntChannels(LPC_DMA_T *pDMA)
00285 {
00286     return pDMA->DMACOMMON [0].ERRINT ;
00287 }
00288 
00289 /**
00290  * @brief   Clears a pending error interrupt status for a single DMA channel
00291  * @param   pDMA    : The base of DMA controller on the chip
00292  * @param   ch      : DMA channel ID
00293  * @return  Nothing
00294  */
00295 STATIC INLINE void Chip_DMA_ClearErrorIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00296 {
00297     pDMA->DMACOMMON [0].ERRINT  = (1 << ch);
00298 }
00299 
00300 /**
00301  * @brief   Enables a single DMA channel's interrupt used in common DMA interrupt
00302  * @param   pDMA    : The base of DMA controller on the chip
00303  * @param   ch      : DMA channel ID
00304  * @return  Nothing
00305  */
00306 STATIC INLINE void Chip_DMA_EnableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00307 {
00308     pDMA->DMACOMMON [0].INTENSET  = (1 << ch);
00309 }
00310 
00311 /**
00312  * @brief   Disables a single DMA channel's interrupt used in common DMA interrupt
00313  * @param   pDMA    : The base of DMA controller on the chip
00314  * @param   ch      : DMA channel ID
00315  * @return  Nothing
00316  */
00317 STATIC INLINE void Chip_DMA_DisableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00318 {
00319     pDMA->DMACOMMON [0].INTENCLR  = (1 << ch);
00320 }
00321 
00322 /**
00323  * @brief   Returns all enabled interrupt channels
00324  * @param   pDMA    : The base of DMA controller on the chip
00325  * @return  Nothing
00326  * @note    A high values in bits 0 .. 15 in the return values indicates
00327  *          that the channel for that bit (bit 0 = channel 0, bit 1 -
00328  *          channel 1, etc.) has an enabled interrupt for the channel.
00329  *          A low state indicates that the DMA channel will not contribute
00330  *          to the common DMA interrupt status.
00331  */
00332 STATIC INLINE uint32_t Chip_DMA_GetEnableIntChannels(LPC_DMA_T *pDMA)
00333 {
00334     return pDMA->DMACOMMON [0].INTENSET ;
00335 }
00336 
00337 /**
00338  * @brief   Returns active A interrupt status for all channels
00339  * @param   pDMA    : The base of DMA controller on the chip
00340  * @return  Nothing
00341  * @note    A high values in bits 0 .. 15 in the return values indicates
00342  *          that the channel for that bit (bit 0 = channel 0, bit 1 -
00343  *          channel 1, etc.) has an active A interrupt for the channel.
00344  *          A low state indicates that the A interrupt is not active.
00345  */
00346 STATIC INLINE uint32_t Chip_DMA_GetActiveIntAChannels(LPC_DMA_T *pDMA)
00347 {
00348     return pDMA->DMACOMMON [0].INTA ;
00349 }
00350 
00351 /**
00352  * @brief   Clears active A interrupt status for a single channel
00353  * @param   pDMA    : The base of DMA controller on the chip
00354  * @param   ch      : DMA channel ID
00355  * @return  Nothing
00356  */
00357 STATIC INLINE void Chip_DMA_ClearActiveIntAChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00358 {
00359     pDMA->DMACOMMON [0].INTA  = (1 << ch);
00360 }
00361 
00362 /**
00363  * @brief   Returns active B interrupt status for all channels
00364  * @param   pDMA    : The base of DMA controller on the chip
00365  * @return  Nothing
00366  * @note    A high values in bits 0 .. 15 in the return values indicates
00367  *          that the channel for that bit (bit 0 = channel 0, bit 1 -
00368  *          channel 1, etc.) has an active B interrupt for the channel.
00369  *          A low state indicates that the B interrupt is not active.
00370  */
00371 STATIC INLINE uint32_t Chip_DMA_GetActiveIntBChannels(LPC_DMA_T *pDMA)
00372 {
00373     return pDMA->DMACOMMON [0].INTB ;
00374 }
00375 
00376 /**
00377  * @brief   Clears active B interrupt status for a single channel
00378  * @param   pDMA    : The base of DMA controller on the chip
00379  * @param   ch      : DMA channel ID
00380  * @return  Nothing
00381  */
00382 STATIC INLINE void Chip_DMA_ClearActiveIntBChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00383 {
00384     pDMA->DMACOMMON [0].INTB  = (1 << ch);
00385 }
00386 
00387 /**
00388  * @brief   Sets the VALIDPENDING control bit for a single channel
00389  * @param   pDMA    : The base of DMA controller on the chip
00390  * @param   ch      : DMA channel ID
00391  * @return  Nothing
00392  * @note    See the User Manual for more information for what this bit does.
00393  *
00394  */
00395 STATIC INLINE void Chip_DMA_SetValidChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00396 {
00397     pDMA->DMACOMMON [0].SETVALID  = (1 << ch);
00398 }
00399 
00400 /**
00401  * @brief   Sets the TRIG bit for a single channel
00402  * @param   pDMA    : The base of DMA controller on the chip
00403  * @param   ch      : DMA channel ID
00404  * @return  Nothing
00405  * @note    See the User Manual for more information for what this bit does.
00406  */
00407 STATIC INLINE void Chip_DMA_SetTrigChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00408 {
00409     pDMA->DMACOMMON [0].SETTRIG  = (1 << ch);
00410 }
00411 
00412 /**
00413  * @brief   Aborts a DMA operation for a single channel
00414  * @param   pDMA    : The base of DMA controller on the chip
00415  * @param   ch      : DMA channel ID
00416  * @return  Nothing
00417  * @note    To abort a channel, the channel should first be disabled. Then wait
00418  *          until the channel is no longer busy by checking the corresponding
00419  *          bit in BUSY. Finally, abort the channel operation. This prevents the
00420  *          channel from restarting an incomplete operation when it is enabled
00421  *          again.
00422  */
00423 STATIC INLINE void Chip_DMA_AbortChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00424 {
00425     pDMA->DMACOMMON [0].ABORT  = (1 << ch);
00426 }
00427 
00428 /**
00429  * @}
00430  */
00431 
00432 /** @defgroup DMATRIGMUX_11U6X CHIP: LPC11u6x DMA trigger selection driver
00433  * @ingroup CHIP_11U6X_Drivers
00434  * @{
00435  */
00436 
00437 /**
00438  * @brief DMA trigger pin muxing structure
00439  */
00440 typedef struct {                    /*!< DMA trigger pin muxing register structure */
00441     __IO uint32_t  DMA_ITRIG_INMUX[MAX_DMA_CHANNEL];    /*!< Trigger input select register for DMA channels */
00442 } LPC_DMATRIGMUX_T;
00443 
00444 /* DMA triggers that can mapped to DMA channels */
00445 typedef enum {
00446     DMATRIG_ADC0_SEQA_IRQ  = 0,          /*!< ADC0 sequencer A interrupt as trigger */
00447     DMATRIG_ADC0_SEQB_IRQ ,              /*!< ADC0 sequencer B interrupt as trigger */
00448     DMATRIG_CT16B0_MAT0 ,                /*!< 16-bit counter/timer 0 interrupt as trigger */
00449     DMATRIG_CT16B1_MAT0 ,                /*!< 16-bit counter/timer 1 interrupt as trigger */
00450     DMATRIG_CT32B0_MAT0 ,                /*!< 32-bit counter/timer 0 interrupt as trigger */
00451     DMATRIG_CT32B1_MAT0 ,                /*!< 32-bit counter/timer 1 interrupt as trigger */
00452     DMATRIG_PINT0 ,                      /*!< Pin interrupt 0 as trigger */
00453     DMATRIG_PINT1 ,                      /*!< Pin interrupt 1 as trigger */
00454     DMATRIG_SCT0_DMA0 ,                  /*!< SCT 0, DMA 0 as trigger */
00455     DMATRIG_SCT0_DMA1 ,                  /*!< SCT 1, DMA 1 as trigger */
00456     DMATRIG_SCT1_DMA0 ,                  /*!< SCT 0, DMA 0 as trigger */
00457     DMATRIG_SCT1_DMA1                    /*!< SCT 1, DMA 1 as trigger */
00458 } DMA_TRIGSRC_T ;
00459 
00460 /**
00461  * @brief   Select a trigger source for a DMA channel
00462  * @param   pDMATRIG    : The base of DMA trigger setup block on the chip
00463  * @param   ch          : DMA channel ID
00464  * @param   trig        : Trigger source for the DMA channel
00465  * @return  Nothing
00466  * @note    A DMA trigger source only needs to be setup when the DMA is setup
00467  *          for hardware trigger mode (when Chip_DMA_SetupChannelConfig() is
00468  *          called with DMA_CFG_HWTRIGEN as OR'ed option).
00469  */
00470 STATIC INLINE void Chip_DMA_SetHWTrigger(LPC_DMATRIGMUX_T *pDMATRIG, DMA_CHID_T ch, DMA_TRIGSRC_T  trig)
00471 {
00472     pDMATRIG->DMA_ITRIG_INMUX [ch] = (uint32_t) trig;
00473 }
00474 
00475 /**
00476  * @}
00477  */
00478 
00479 /** @defgroup DMA_CHANNEL_11U6X CHIP: LPC11u6x DMA Controller driver channel specific functions
00480  * @{
00481  */
00482 
00483 /* Support macro for DMA_CHDESC_T */
00484 #define DMA_ADDR(addr)      ((uint32_t) (addr))
00485 
00486 /* Support definitions for setting the configuration of a DMA channel. You
00487    will need to get more information on these options from the User manual. */
00488 #define DMA_CFG_PERIPHREQEN     (1 << 0)    /*!< Enables Peripheral DMA requests */
00489 #define DMA_CFG_HWTRIGEN        (1 << 1)    /*!< Use hardware triggering via imput mux */
00490 #define DMA_CFG_TRIGPOL_LOW     (0 << 4)    /*!< Hardware trigger is active low or falling edge */
00491 #define DMA_CFG_TRIGPOL_HIGH    (1 << 4)    /*!< Hardware trigger is active high or rising edge */
00492 #define DMA_CFG_TRIGTYPE_EDGE   (0 << 5)    /*!< Hardware trigger is edge triggered */
00493 #define DMA_CFG_TRIGTYPE_LEVEL  (1 << 5)    /*!< Hardware trigger is level triggered */
00494 #define DMA_CFG_TRIGBURST_SNGL  (0 << 6)    /*!< Single transfer. Hardware trigger causes a single transfer */
00495 #define DMA_CFG_TRIGBURST_BURST (1 << 6)    /*!< Burst transfer (see UM) */
00496 #define DMA_CFG_BURSTPOWER_1    (0 << 8)    /*!< Set DMA burst size to 1 transfer */
00497 #define DMA_CFG_BURSTPOWER_2    (1 << 8)    /*!< Set DMA burst size to 2 transfers */
00498 #define DMA_CFG_BURSTPOWER_4    (2 << 8)    /*!< Set DMA burst size to 4 transfers */
00499 #define DMA_CFG_BURSTPOWER_8    (3 << 8)    /*!< Set DMA burst size to 8 transfers */
00500 #define DMA_CFG_BURSTPOWER_16   (4 << 8)    /*!< Set DMA burst size to 16 transfers */
00501 #define DMA_CFG_BURSTPOWER_32   (5 << 8)    /*!< Set DMA burst size to 32 transfers */
00502 #define DMA_CFG_BURSTPOWER_64   (6 << 8)    /*!< Set DMA burst size to 64 transfers */
00503 #define DMA_CFG_BURSTPOWER_128  (7 << 8)    /*!< Set DMA burst size to 128 transfers */
00504 #define DMA_CFG_BURSTPOWER_256  (8 << 8)    /*!< Set DMA burst size to 256 transfers */
00505 #define DMA_CFG_BURSTPOWER_512  (9 << 8)    /*!< Set DMA burst size to 512 transfers */
00506 #define DMA_CFG_BURSTPOWER_1024 (10 << 8)   /*!< Set DMA burst size to 1024 transfers */
00507 #define DMA_CFG_BURSTPOWER(n)   ((n) << 8)  /*!< Set DMA burst size to 2^n transfers, max n=10 */
00508 #define DMA_CFG_SRCBURSTWRAP    (1 << 14)   /*!< Source burst wrapping is enabled for this DMA channel */
00509 #define DMA_CFG_DSTBURSTWRAP    (1 << 15)   /*!< Destination burst wrapping is enabled for this DMA channel */
00510 #define DMA_CFG_CHPRIORITY(p)   ((p) << 16) /*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */
00511 
00512 /**
00513  * @brief   Setup a DMA channel configuration
00514  * @param   pDMA    : The base of DMA controller on the chip
00515  * @param   ch      : DMA channel ID
00516  * @param   cfg     : An Or'ed value of DMA_CFG_* values that define the channel's configuration
00517  * @return  Nothing
00518  * @note    This function sets up all configurable options for the DMA channel.
00519  *          These options are usually set once for a channel and then unchanged.<br>
00520  *
00521  *          The following example show how to configure the channel for peripheral
00522  *          DMA requests, burst transfer size of 1 (in 'transfers', not bytes),
00523  *          continuous reading of the same source address, incrementing destination
00524  *          address, and highest channel priority.<br>
00525  *          Example: Chip_DMA_SetupChannelConfig(pDMA, SSP0_RX_DMA,
00526  *              (DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_1 |
00527  *              DMA_CFG_SRCBURSTWRAP | DMA_CFG_CHPRIORITY(0)));<br>
00528  *
00529  *          The following example show how to configure the channel for an external
00530  *          trigger from the imput mux with low edge polarity, a burst transfer size of 8,
00531  *          incrementing source and destination addresses, and lowest channel
00532  *          priority.<br>
00533  *          Example: Chip_DMA_SetupChannelConfig(pDMA, DMA_CH14,
00534  *              (DMA_CFG_HWTRIGEN | DMA_CFG_TRIGPOL_LOW | DMA_CFG_TRIGTYPE_EDGE |
00535  *              DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_8 |
00536  *              DMA_CFG_CHPRIORITY(3)));<br>
00537  *
00538  *          For non-peripheral DMA triggering (DMA_CFG_HWTRIGEN definition), use the
00539  *          DMA input mux functions to configure the DMA trigger source for a DMA channel.
00540  */
00541 STATIC INLINE void Chip_DMA_SetupChannelConfig(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg)
00542 {
00543     pDMA->DMACH [ch].CFG  = cfg;
00544 }
00545 
00546 /* DMA channel control and status register definitions */
00547 #define DMA_CTLSTAT_VALIDPENDING    (1 << 0)    /*!< Valid pending flag for this channel */
00548 #define DMA_CTLSTAT_TRIG            (1 << 2)    /*!< Trigger flag. Indicates that the trigger for this channel is currently set */
00549 
00550 /**
00551  * @brief   Returns channel specific status flags
00552  * @param   pDMA    : The base of DMA controller on the chip
00553  * @param   ch      : DMA channel ID
00554  * @return  AN Or'ed value of DMA_CTLSTAT_VALIDPENDING and DMA_CTLSTAT_TRIG
00555  */
00556 STATIC INLINE uint32_t Chip_DMA_GetChannelStatus(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00557 {
00558     return pDMA->DMACH [ch].XFERCFG ;
00559 }
00560 
00561 /* DMA channel transfer configuration registers definitions */
00562 #define DMA_XFERCFG_CFGVALID        (1 << 0)    /*!< Configuration Valid flag */
00563 #define DMA_XFERCFG_RELOAD          (1 << 1)    /*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */
00564 #define DMA_XFERCFG_SWTRIG          (1 << 2)    /*!< Software Trigger */
00565 #define DMA_XFERCFG_CLRTRIG         (1 << 3)    /*!< Clear Trigger */
00566 #define DMA_XFERCFG_SETINTA         (1 << 4)    /*!< Set Interrupt flag A for this channel to fire when descriptor is complete */
00567 #define DMA_XFERCFG_SETINTB         (1 << 5)    /*!< Set Interrupt flag B for this channel to fire when descriptor is complete */
00568 #define DMA_XFERCFG_WIDTH_8         (0 << 8)    /*!< 8-bit transfers are performed */
00569 #define DMA_XFERCFG_WIDTH_16        (1 << 8)    /*!< 16-bit transfers are performed */
00570 #define DMA_XFERCFG_WIDTH_32        (2 << 8)    /*!< 32-bit transfers are performed */
00571 #define DMA_XFERCFG_SRCINC_0        (0 << 12)   /*!< DMA source address is not incremented after a transfer */
00572 #define DMA_XFERCFG_SRCINC_1        (1 << 12)   /*!< DMA source address is incremented by 1 (width) after a transfer */
00573 #define DMA_XFERCFG_SRCINC_2        (2 << 12)   /*!< DMA source address is incremented by 2 (width) after a transfer */
00574 #define DMA_XFERCFG_SRCINC_4        (3 << 12)   /*!< DMA source address is incremented by 4 (width) after a transfer */
00575 #define DMA_XFERCFG_DSTINC_0        (0 << 14)   /*!< DMA destination address is not incremented after a transfer */
00576 #define DMA_XFERCFG_DSTINC_1        (1 << 14)   /*!< DMA destination address is incremented by 1 (width) after a transfer */
00577 #define DMA_XFERCFG_DSTINC_2        (2 << 14)   /*!< DMA destination address is incremented by 2 (width) after a transfer */
00578 #define DMA_XFERCFG_DSTINC_4        (3 << 14)   /*!< DMA destination address is incremented by 4 (width) after a transfer */
00579 #define DMA_XFERCFG_XFERCOUNT(n)    ((n - 1) << 16) /*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */
00580 
00581 /**
00582  * @brief   Setup a DMA channel transfer configuration
00583  * @param   pDMA    : The base of DMA controller on the chip
00584  * @param   ch      : DMA channel ID
00585  * @param   cfg     : An Or'ed value of DMA_XFERCFG_* values that define the channel's transfer configuration
00586  * @return  Nothing
00587  * @note    This function sets up the transfer configuration for the DMA channel.<br>
00588  *
00589  *          The following example show how to configure the channel's transfer for
00590  *          multiple transfer descriptors (ie, ping-pong), interrupt 'A' trigger on
00591  *          transfer descriptor completion, 128 byte size transfers, and source and
00592  *          destination address increment.<br>
00593  *          Example: Chip_DMA_SetupChannelTransfer(pDMA, SSP0_RX_DMA,
00594  *              (DMA_XFERCFG_CFGVALID | DMA_XFERCFG_RELOAD | DMA_XFERCFG_SETINTA |
00595  *              DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_SRCINC_1 | DMA_XFERCFG_DSTINC_1 |
00596  *              DMA_XFERCFG_XFERCOUNT(128)));<br>
00597  */
00598 STATIC INLINE void Chip_DMA_SetupChannelTransfer(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg)
00599 {
00600     pDMA->DMACH [ch].XFERCFG  = cfg;
00601 }
00602 
00603 /**
00604  * @brief   Set DMA transfer register interrupt bits (safe)
00605  * @param   pDMA    : The base of DMA controller on the chip
00606  * @param   ch      : DMA channel ID
00607  * @param   mask    : Bits to set
00608  * @return  Nothing
00609  * @note    This function safely sets bits in the DMA channel specific XFERCFG
00610  *          register.
00611  */
00612 void Chip_DMA_SetTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask);
00613 
00614 /**
00615  * @brief   Clear DMA transfer register interrupt bits (safe)
00616  * @param   pDMA    : The base of DMA controller on the chip
00617  * @param   ch      : DMA channel ID
00618  * @param   mask    : Bits to clear
00619  * @return  Nothing
00620  * @note    This function safely clears bits in the DMA channel specific XFERCFG
00621  *          register.
00622  */
00623 void Chip_DMA_ClearTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask);
00624 
00625 /**
00626  * @brief   Update the transfer size in an existing DMA channel transfer configuration
00627  * @param   pDMA    : The base of DMA controller on the chip
00628  * @param   ch      : DMA channel ID
00629  * @param   trans   : Number of transfers to update the transfer configuration to (1 - 1023)
00630  * @return  Nothing
00631  */
00632 void Chip_DMA_SetupChannelTransferSize(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t trans);
00633 
00634 /**
00635  * @brief   Sets a DMA channel configuration as valid
00636  * @param   pDMA    : The base of DMA controller on the chip
00637  * @param   ch      : DMA channel ID
00638  * @return  Nothing
00639  */
00640 STATIC INLINE void Chip_DMA_SetChannelValid(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00641 {
00642     Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID);
00643 }
00644 
00645 /**
00646  * @brief   Sets a DMA channel configuration as invalid
00647  * @param   pDMA    : The base of DMA controller on the chip
00648  * @param   ch      : DMA channel ID
00649  * @return  Nothing
00650  */
00651 STATIC INLINE void Chip_DMA_SetChannelInValid(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00652 {
00653     Chip_DMA_ClearTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID);
00654 }
00655 
00656 /**
00657  * @brief   Performs a software trigger of the DMA channel
00658  * @param   pDMA    : The base of DMA controller on the chip
00659  * @param   ch      : DMA channel ID
00660  * @return  Nothing
00661  */
00662 STATIC INLINE void Chip_DMA_SWTriggerChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
00663 {
00664     Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_SWTRIG);
00665 }
00666 
00667 /**
00668  * @brief   Sets up a DMA channel with the passed DMA transfer descriptor
00669  * @param   pDMA    : The base of DMA controller on the chip
00670  * @param   ch      : DMA channel ID
00671  * @param   desc    : Pointer to DMA transfer descriptor
00672  * @return  false if the DMA channel was active, otherwise true
00673  * @note    This function will set the DMA descriptor in the SRAM table to the
00674  *          the passed descriptor. This function is only meant to be used when
00675  *          the DMA channel is not active and can be used to setup the
00676  *          initial transfer for a linked list or ping-pong buffer or just a
00677  *          single transfer without a next descriptor.<br>
00678  *
00679  *          If using this function to write the initial transfer descriptor in
00680  *          a linked list or ping-pong buffer configuration, it should contain a
00681  *          non-NULL 'next' field pointer.
00682  */
00683 bool Chip_DMA_SetupTranChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch, DMA_CHDESC_T *desc);
00684 
00685 /**
00686  * @}
00687  */
00688 
00689 /**
00690  * @}
00691  */
00692 
00693 #ifdef __cplusplus
00694 }
00695 #endif
00696 
00697 #endif /* __DMA_11U6X_H_ */
00698 
00699