dma_11u6x.c

00001 /*
00002  * @brief LPC11u6x DMA chip driver
00003  *
00004  * @note
00005  * Copyright(C) NXP Semiconductors, 2013
00006  * All rights reserved.
00007  *
00008  * @par
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * LPC products.  This software is supplied "AS IS" without any warranties of
00012  * any kind, and NXP Semiconductors and its licensor disclaim any and
00013  * all warranties, express or implied, including all implied warranties of
00014  * merchantability, fitness for a particular purpose and non-infringement of
00015  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00016  * or liability for the use of the software, conveys no license or rights under any
00017  * patent, copyright, mask work right, or any other intellectual property rights in
00018  * or to any products. NXP Semiconductors reserves the right to make changes
00019  * in the software without notification. NXP Semiconductors also makes no
00020  * representation or warranty that such application will be suitable for the
00021  * specified use without further testing or modification.
00022  *
00023  * @par
00024  * Permission to use, copy, modify, and distribute this software and its
00025  * documentation is hereby granted, under NXP Semiconductors' and its
00026  * licensor's relevant copyrights in the software, without fee, provided that it
00027  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00028  * copyright, permission, and disclaimer notice must appear in all copies of
00029  * this code.
00030  */
00031 
00032 //#include "lpc_defs.h"
00033 #include "dma_11u6x.h"
00034 
00035 #define false 0
00036 #define true 1
00037 
00038 /*****************************************************************************
00039  * Private types/enumerations/variables
00040  ****************************************************************************/
00041 
00042 /*****************************************************************************
00043  * Public types/enumerations/variables
00044  ****************************************************************************/
00045 
00046 #ifdef __cplusplus
00047 extern "C" {
00048 #endif
00049 
00050 /* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase()
00051    function if a DMA SRAM table is needed. This table is correctly aligned for
00052      the DMA controller. */
00053 #if defined(__CC_ARM)
00054 /* Keil alignement to 256 bytes */
00055 __align(256) DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL];
00056 #endif /* defined (__CC_ARM) */
00057 
00058 /* IAR support */
00059 #if defined(__ICCARM__)
00060 /* IAR EWARM alignement to 256 bytes */
00061 #pragma data_alignment=256
00062 DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL];
00063 #endif /* defined (__ICCARM__) */
00064 
00065 #if defined( __GNUC__ )
00066 /* GNU alignement to 256 bytes */
00067 DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL] __attribute__ ((aligned(256)));
00068 #endif /* defined (__GNUC__) */
00069 
00070 #ifdef __cplusplus
00071 }
00072 #endif
00073 
00074 /*****************************************************************************
00075  * Private functions
00076  ****************************************************************************/
00077 
00078 /*****************************************************************************
00079  * Public functions
00080  ****************************************************************************/
00081 
00082 /* Set DMA transfer register interrupt bits (safe) */
00083 void Chip_DMA_SetTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask)
00084 {
00085     uint32_t temp;
00086 
00087     /* Read and write values may not be the same, write 0 to
00088        undefined bits */
00089     temp = pDMA->DMACH [ch].XFERCFG  & ~0xFC000CC0;
00090 
00091     pDMA->DMACH [ch].XFERCFG  = temp | mask;
00092 }
00093 
00094 /* Clear DMA transfer register interrupt bits (safe) */
00095 void Chip_DMA_ClearTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask)
00096 {
00097     uint32_t temp;
00098 
00099     /* Read and write values may not be the same, write 0 to
00100        undefined bits */
00101     temp = pDMA->DMACH [ch].XFERCFG  & ~0xFC000CC0;
00102 
00103     pDMA->DMACH [ch].XFERCFG  = temp & ~mask;
00104 }
00105 
00106 /* Update the transfer size in an existing DMA channel transfer configuration */
00107 void Chip_DMA_SetupChannelTransferSize(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t trans)
00108 {
00109     Chip_DMA_ClearTranBits(pDMA, ch, (0x3FF << 16));
00110     Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_XFERCOUNT(trans));
00111 }
00112 
00113 /* Sets up a DMA channel with the passed DMA transfer descriptor */
00114 bool Chip_DMA_SetupTranChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch, DMA_CHDESC_T *desc)
00115 {
00116     bool good = false;
00117     DMA_CHDESC_T *pDesc = (DMA_CHDESC_T *) pDMA->SRAMBASE ;
00118 
00119     if ((Chip_DMA_GetActiveChannels(pDMA) & (1 << ch)) == 0) {
00120         /* Channel is not active, so update the descriptor */
00121        pDesc[ch] = *desc;
00122 
00123        good = true;
00124    }
00125 
00126    return good;
00127 }
00128