Ivo van Poorten
Library to access LPC17xx peripherals. It uses static inline functions, constant propagation and dead code elimination to be as fast as possible.
Dependents: Chua-VGA Wolfram-1D-VGA WolframRnd-1D-VGA Basin-VGA ... more
nvic.h@0:7a91348b4a02, 2011-07-03 (annotated)
- Committer:
- Ivop
- Date:
- Sun Jul 03 17:11:55 2011 +0000
- Revision:
- 0:7a91348b4a02
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Ivop | 0:7a91348b4a02 | 1 | /* Copyright (C) 2011 by Ivo van Poorten <ivop@euronet.nl> |
| Ivop | 0:7a91348b4a02 | 2 | * This file is licensed under the terms of the GNU Lesser |
| Ivop | 0:7a91348b4a02 | 3 | * General Public License, version 3. |
| Ivop | 0:7a91348b4a02 | 4 | */ |
| Ivop | 0:7a91348b4a02 | 5 | |
| Ivop | 0:7a91348b4a02 | 6 | #ifndef FASTLIB_NVIC_H |
| Ivop | 0:7a91348b4a02 | 7 | #define FASTLIB_NVIC_H |
| Ivop | 0:7a91348b4a02 | 8 | |
| Ivop | 0:7a91348b4a02 | 9 | #include "fastlib/common.h" |
| Ivop | 0:7a91348b4a02 | 10 | |
| Ivop | 0:7a91348b4a02 | 11 | #define FL_NVIC_ISER0 ((volatile uint32_t *) 0xE000E100) |
| Ivop | 0:7a91348b4a02 | 12 | #define FL_NVIC_ISER1 ((volatile uint32_t *) 0xE000E104) |
| Ivop | 0:7a91348b4a02 | 13 | #define FL_NVIC_ICER0 ((volatile uint32_t *) 0xE000E180) |
| Ivop | 0:7a91348b4a02 | 14 | #define FL_NVIC_ICER1 ((volatile uint32_t *) 0xE000E184) |
| Ivop | 0:7a91348b4a02 | 15 | #define FL_NVIC_ISPR0 ((volatile uint32_t *) 0xE000E200) |
| Ivop | 0:7a91348b4a02 | 16 | #define FL_NVIC_ISPR1 ((volatile uint32_t *) 0xE000E204) |
| Ivop | 0:7a91348b4a02 | 17 | #define FL_NVIC_ICPR0 ((volatile uint32_t *) 0xE000E280) |
| Ivop | 0:7a91348b4a02 | 18 | #define FL_NVIC_ICPR1 ((volatile uint32_t *) 0xE000E284) |
| Ivop | 0:7a91348b4a02 | 19 | #define FL_NVIC_IABR0 ((volatile uint32_t *) 0xE000E300) |
| Ivop | 0:7a91348b4a02 | 20 | #define FL_NVIC_IABR1 ((volatile uint32_t *) 0xE000E304) |
| Ivop | 0:7a91348b4a02 | 21 | #define FL_NVIC_IPR0 ((volatile uint32_t *) 0xE000E400) |
| Ivop | 0:7a91348b4a02 | 22 | #define FL_NVIC_IPR1 ((volatile uint32_t *) 0xE000E404) |
| Ivop | 0:7a91348b4a02 | 23 | #define FL_NVIC_IPR2 ((volatile uint32_t *) 0xE000E408) |
| Ivop | 0:7a91348b4a02 | 24 | #define FL_NVIC_IPR3 ((volatile uint32_t *) 0xE000E40C) |
| Ivop | 0:7a91348b4a02 | 25 | #define FL_NVIC_IPR4 ((volatile uint32_t *) 0xE000E410) |
| Ivop | 0:7a91348b4a02 | 26 | #define FL_NVIC_IPR5 ((volatile uint32_t *) 0xE000E414) |
| Ivop | 0:7a91348b4a02 | 27 | #define FL_NVIC_IPR6 ((volatile uint32_t *) 0xE000E418) |
| Ivop | 0:7a91348b4a02 | 28 | #define FL_NVIC_IPR7 ((volatile uint32_t *) 0xE000E41C) |
| Ivop | 0:7a91348b4a02 | 29 | #define FL_NVIC_IPR8 ((volatile uint32_t *) 0xE000E420) |
| Ivop | 0:7a91348b4a02 | 30 | #define FL_NVIC_STIR ((volatile uint32_t *) 0xE000EF00) |
| Ivop | 0:7a91348b4a02 | 31 | |
| Ivop | 0:7a91348b4a02 | 32 | #define FL_NVIC_INT_WDT 0 |
| Ivop | 0:7a91348b4a02 | 33 | #define FL_NVIC_INT_TIMER0 1 |
| Ivop | 0:7a91348b4a02 | 34 | #define FL_NVIC_INT_TIMER1 2 |
| Ivop | 0:7a91348b4a02 | 35 | #define FL_NVIC_INT_TIMER2 3 |
| Ivop | 0:7a91348b4a02 | 36 | #define FL_NVIC_INT_TIMER3 4 |
| Ivop | 0:7a91348b4a02 | 37 | #define FL_NVIC_INT_UART0 5 |
| Ivop | 0:7a91348b4a02 | 38 | #define FL_NVIC_INT_UART1 6 |
| Ivop | 0:7a91348b4a02 | 39 | #define FL_NVIC_INT_UART2 7 |
| Ivop | 0:7a91348b4a02 | 40 | #define FL_NVIC_INT_UART3 8 |
| Ivop | 0:7a91348b4a02 | 41 | #define FL_NVIC_INT_PWM 9 |
| Ivop | 0:7a91348b4a02 | 42 | #define FL_NVIC_INT_I2C0 10 |
| Ivop | 0:7a91348b4a02 | 43 | #define FL_NVIC_INT_I2C1 11 |
| Ivop | 0:7a91348b4a02 | 44 | #define FL_NVIC_INT_I2C2 12 |
| Ivop | 0:7a91348b4a02 | 45 | #define FL_NVIC_INT_SPI 13 |
| Ivop | 0:7a91348b4a02 | 46 | #define FL_NVIC_INT_SSP0 14 |
| Ivop | 0:7a91348b4a02 | 47 | #define FL_NVIC_INT_SSP1 15 |
| Ivop | 0:7a91348b4a02 | 48 | #define FL_NVIC_INT_PLL0 16 |
| Ivop | 0:7a91348b4a02 | 49 | #define FL_NVIC_INT_RTC 17 |
| Ivop | 0:7a91348b4a02 | 50 | #define FL_NVIC_INT_EINT0 18 |
| Ivop | 0:7a91348b4a02 | 51 | #define FL_NVIC_INT_EINT1 19 |
| Ivop | 0:7a91348b4a02 | 52 | #define FL_NVIC_INT_EINT2 20 |
| Ivop | 0:7a91348b4a02 | 53 | #define FL_NVIC_INT_EINT3 21 |
| Ivop | 0:7a91348b4a02 | 54 | #define FL_NVIC_INT_ADC 22 |
| Ivop | 0:7a91348b4a02 | 55 | #define FL_NVIC_INT_BOD 23 |
| Ivop | 0:7a91348b4a02 | 56 | #define FL_NVIC_INT_USB 24 |
| Ivop | 0:7a91348b4a02 | 57 | #define FL_NVIC_INT_CAN 25 |
| Ivop | 0:7a91348b4a02 | 58 | #define FL_NVIC_INT_DMA 26 |
| Ivop | 0:7a91348b4a02 | 59 | #define FL_NVIC_INT_I2S 27 |
| Ivop | 0:7a91348b4a02 | 60 | #define FL_NVIC_INT_ENET 28 |
| Ivop | 0:7a91348b4a02 | 61 | #define FL_NVIC_INT_RIT 29 |
| Ivop | 0:7a91348b4a02 | 62 | #define FL_NVIC_INT_MCPWM 30 |
| Ivop | 0:7a91348b4a02 | 63 | #define FL_NVIC_INT_QEI 31 |
| Ivop | 0:7a91348b4a02 | 64 | |
| Ivop | 0:7a91348b4a02 | 65 | #define FL_NVIC_INT_PLL1 32 |
| Ivop | 0:7a91348b4a02 | 66 | #define FL_NVIC_INT_USBACT 33 |
| Ivop | 0:7a91348b4a02 | 67 | #define FL_NVIC_INT_CANACT 34 |
| Ivop | 0:7a91348b4a02 | 68 | |
| Ivop | 0:7a91348b4a02 | 69 | #define FL_NVIC_INTERRUPT_FUNC(x, y) \ |
| Ivop | 0:7a91348b4a02 | 70 | static inline void fl_nvic_interrupt_##x(const unsigned interrupt) { \ |
| Ivop | 0:7a91348b4a02 | 71 | if (interrupt < 32) *FL_NVIC_##y##0 |= 1U<<interrupt; \ |
| Ivop | 0:7a91348b4a02 | 72 | else *FL_NVIC_##y##1 |= 1U<<(interrupt-32); \ |
| Ivop | 0:7a91348b4a02 | 73 | } \ |
| Ivop | 0:7a91348b4a02 | 74 | static inline unsigned fl_nvic_interrupt_##x##_status(const unsigned interrupt) { \ |
| Ivop | 0:7a91348b4a02 | 75 | if (interrupt < 32) return (*FL_NVIC_##y##0) & (1U<<interrupt); \ |
| Ivop | 0:7a91348b4a02 | 76 | else return (*FL_NVIC_##y##1) & (1U<<(interrupt-32)); \ |
| Ivop | 0:7a91348b4a02 | 77 | } |
| Ivop | 0:7a91348b4a02 | 78 | |
| Ivop | 0:7a91348b4a02 | 79 | FL_NVIC_INTERRUPT_FUNC(set_enable, ISER) |
| Ivop | 0:7a91348b4a02 | 80 | FL_NVIC_INTERRUPT_FUNC(clear_enable, ICER) |
| Ivop | 0:7a91348b4a02 | 81 | FL_NVIC_INTERRUPT_FUNC(set_pending, ISPR) |
| Ivop | 0:7a91348b4a02 | 82 | FL_NVIC_INTERRUPT_FUNC(clear_pending, ICPR) |
| Ivop | 0:7a91348b4a02 | 83 | |
| Ivop | 0:7a91348b4a02 | 84 | static inline unsigned fl_nvic_interrupt_active_bit_status(const unsigned interrupt) { |
| Ivop | 0:7a91348b4a02 | 85 | if (interrupt < 32) return (*FL_NVIC_IABR0) & (1U<<interrupt); |
| Ivop | 0:7a91348b4a02 | 86 | else return (*FL_NVIC_IABR1) & (1U<<(interrupt-32)); |
| Ivop | 0:7a91348b4a02 | 87 | } |
| Ivop | 0:7a91348b4a02 | 88 | |
| Ivop | 0:7a91348b4a02 | 89 | static inline void fl_nvic_interrupt_set_priority(const unsigned interrupt, const unsigned priority) { |
| Ivop | 0:7a91348b4a02 | 90 | const unsigned i = interrupt >> 3, |
| Ivop | 0:7a91348b4a02 | 91 | j = (31 <<3) << ((interrupt&3)<<3), |
| Ivop | 0:7a91348b4a02 | 92 | k = (priority<<3) << ((interrupt&3)<<3); |
| Ivop | 0:7a91348b4a02 | 93 | *(FL_NVIC_IPR0 + i) &= ~j; |
| Ivop | 0:7a91348b4a02 | 94 | *(FL_NVIC_IPR0 + i) |= k; |
| Ivop | 0:7a91348b4a02 | 95 | } |
| Ivop | 0:7a91348b4a02 | 96 | |
| Ivop | 0:7a91348b4a02 | 97 | static inline void fl_nvic_interrupt_software_trigger(const unsigned interrupt) { |
| Ivop | 0:7a91348b4a02 | 98 | *FL_NVIC_STIR = interrupt; |
| Ivop | 0:7a91348b4a02 | 99 | } |
| Ivop | 0:7a91348b4a02 | 100 | |
| Ivop | 0:7a91348b4a02 | 101 | #endif |