Hideharu Tsunemoto
MBED_LPC1768_Test Pulse msec/usec Interval Output P29/P30 & Input P21 Status Send USB Serial Log
Revision 0:47c1b6a0c166, committed 2018-05-29
- Comitter:
- H_Tsunemoto
- Date:
- Tue May 29 02:41:54 2018 +0000
- Commit message:
- Pulse On/OFF OutPut P29/P30 & Rep Input P21 Status Output USBSerial;
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/MBED_Dose_Measure_SingleCH_2CH_2Range_Ver100.uvoptx Tue May 29 02:41:54 2018 +0000 @@ -0,0 +1,24 @@ +<?xml version="1.0" encoding="utf-8"?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> + <SchemaVersion>1.0</SchemaVersion> + <Target> + <TargetName>MBED_Dose_Measure_SingleCH_2CH_2Range_Ver100</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <nTsel>11</nTsel> + <pMon>BIN\CMSIS_AGDI.dll</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>CMSIS_AGDI</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC0FE0 -FN1 -FF0lpc_iap_512 -FS000000000 -FL080000 -FP0($$Device:LPC1768$Flash/LPC_IAP_512.FLM))</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + </TargetOption> + </Target> +</ProjectOpt> \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MBED_Dose_Measure_SingleCH_2CH_2Range_Ver100.uvprojx Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,994 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+ <SchemaVersion>2.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>MBED_Dose_Measure_SingleCH_2CH_2Range_Ver100</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>LPC1768</Device>
+ <Vendor>NXP</Vendor>
+ <PackID>Keil.LPC1700_DFP.pdsc</PackID>
+ <PackURL>http://www.keil.com/pack</PackURL>
+ <Cpu></Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC0FE0 -FN1 -FF0lpc_iap_512 -FS000000000 -FL080000 -FP0($$Device:LPC1768$Flash/LPC_IAP_512.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:LPC1768$Device/Include/LPC17xx.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:LPC1768$SVD/LPC176x5x.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\BUILD\</OutputDirectory>
+ <OutputName>MBED_Dose_Measure_SingleCH_2CH_2Range_Ver100</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
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+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
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+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <BeforeMake>
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+ <CommonProperty>
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+ <CpuDll></CpuDll>
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+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
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+ <TargetDlls>
+ <CpuDll></CpuDll>
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+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\CMSIS_AGDI.dll</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
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+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
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+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>1</RvdsVP>
+ <hadIRAM2>1</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
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+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
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+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ {
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0</StartAddress>
+ <Size>0</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0</StartAddress>
+ <Size>0</Size>
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+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
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+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x2000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x1fffe000</StartAddress>
+ <Size>0x2000</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>0</interw>
+ <Optim>2</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>1</uC99>
+ <useXO>0</useXO>
+ <v6Lang>1</v6Lang>
+ <v6LangP>1</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls>-DDEVICE_RTC=1 -DDEVICE_SLEEP=1 -DTOOLCHAIN_object -DTOOLCHAIN_ARM_STD -DDEVICE_SEMIHOST=1 -DFEATURE_LWIP=1 -D__ASSERT_MSG -DTARGET_LPC1768 -DTARGET_RELEASE --no_rtti --split_sections -DDEVICE_PORTINOUT=1 -DMBED_BUILD_TIMESTAMP=1486601465.56 -D__CORTEX_M3 -DDEVICE_DEBUG_AWARENESS=1 -DTARGET_M3 -c -DDEVICE_CAN=1 -DDEVICE_PORTOUT=1 -DDEVICE_STDIO_MESSAGES=1 -DDEVICE_ANALOGOUT=1 -DARM_MATH_CM3 -DTARGET_LIKE_CORTEX_M3 -DDEVICE_ANALOGIN=1 -DDEVICE_PORTIN=1 -DTARGET_CORTEX_M -DDEVICE_ERROR_PATTERN=1 --cpu=Cortex-M3 -Ospace -DDEVICE_ETHERNET=1 -DDEVICE_I2C=1 --preinclude=mbed_config.h -DTOOLCHAIN_ARM -DDEVICE_INTERRUPTIN=1 --no_depend_system_headers -DTARGET_UVISOR_UNSUPPORTED --md -DDEVICE_PWMOUT=1 -DTARGET_LIKE_MBED --gnu --apcs=interwork -DDEVICE_SPI=1 -D__MBED__=1 -DDEVICE_SPISLAVE=1 -DDEVICE_SERIAL_FC=1 -DDEVICE_LOCALFILESYSTEM=1 -DDEVICE_SERIAL=1 -DTARGET_LPC176X -DDEVICE_I2CSLAVE=1 -D__CMSIS_RTOS -DTARGET_NXP -DTARGET_MBED_LPC1768 -D__MBED_CMSIS_RTOS_CM</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>.; MODDMA; mbed/.; mbed/LPC1768; mbed/LPC1768/ARM; </IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>0</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls>--cpreproc --cpreproc_opts=-D__ASSERT_MSG,-D__CMSIS_RTOS,-D__MBED_CMSIS_RTOS_CM,-D__CORTEX_M3,-DARM_MATH_CM3</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>0</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0</TextAddressRange>
+ <DataAddressRange>0</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile>mbed/LPC1768/ARM/LPC1768.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+
+ <Group>
+ <GroupName></GroupName>
+ <Files>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>mbed_config.h</FileName>
+ <FilePath>mbed_config.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>8</FileType>
+ <FileName>main.cpp</FileName>
+ <FilePath>main.cpp</FilePath>
+ </File>
+
+ </Files>
+ </Group>
+
+ <Group>
+ <GroupName>MODDMA</GroupName>
+ <Files>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>example1.h</FileName>
+ <FilePath>MODDMA/example1.h</FilePath>
+ </File>
+
+ <File>
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+ <FilePath>MODDMA/CONFIG.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>iomacros.h</FileName>
+ <FilePath>MODDMA/iomacros.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>example2.h</FileName>
+ <FilePath>MODDMA/example2.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>example4.h</FileName>
+ <FilePath>MODDMA/example4.h</FilePath>
+ </File>
+
+ <File>
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+ <FileName>example3.h</FileName>
+ <FilePath>MODDMA/example3.h</FilePath>
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+
+ <File>
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+ <FileName>MODDMA.h</FileName>
+ <FilePath>MODDMA/MODDMA.h</FilePath>
+ </File>
+
+ <File>
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+ <FileName>ChangeLog.c</FileName>
+ <FilePath>MODDMA/ChangeLog.c</FilePath>
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+
+ <File>
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+ <FileName>DATALUTS.cpp</FileName>
+ <FilePath>MODDMA/DATALUTS.cpp</FilePath>
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+
+ <File>
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+ <FileName>SETUP.cpp</FileName>
+ <FilePath>MODDMA/SETUP.cpp</FilePath>
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+
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+ <FilePath>MODDMA/INIT.cpp</FilePath>
+ </File>
+
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+ <FilePath>MODDMA/MODDMA.cpp</FilePath>
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+ </Files>
+ </Group>
+
+ <Group>
+ <GroupName>LPC1768</GroupName>
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+
+ <File>
+ <FileType>5</FileType>
+ <FileName>device.h</FileName>
+ <FilePath>mbed/LPC1768/device.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>gpio_object.h</FileName>
+ <FilePath>mbed/LPC1768/gpio_object.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>objects.h</FileName>
+ <FilePath>mbed/LPC1768/objects.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>system_LPC17xx.h</FileName>
+ <FilePath>mbed/LPC1768/system_LPC17xx.h</FilePath>
+ </File>
+
+ </Files>
+ </Group>
+
+ <Group>
+ <GroupName>ARM</GroupName>
+ <Files>
+
+ <File>
+ <FileType>3</FileType>
+ <FileName>cmsis_nvic.o</FileName>
+ <FilePath>mbed/LPC1768/ARM/cmsis_nvic.o</FilePath>
+ </File>
+
+ <File>
+ <FileType>3</FileType>
+ <FileName>core_cm3.o</FileName>
+ <FilePath>mbed/LPC1768/ARM/core_cm3.o</FilePath>
+ </File>
+
+ <File>
+ <FileType>3</FileType>
+ <FileName>startup_LPC17xx.o</FileName>
+ <FilePath>mbed/LPC1768/ARM/startup_LPC17xx.o</FilePath>
+ </File>
+
+ <File>
+ <FileType>3</FileType>
+ <FileName>sys.o</FileName>
+ <FilePath>mbed/LPC1768/ARM/sys.o</FilePath>
+ </File>
+
+ <File>
+ <FileType>3</FileType>
+ <FileName>system_LPC17xx.o</FileName>
+ <FilePath>mbed/LPC1768/ARM/system_LPC17xx.o</FilePath>
+ </File>
+
+ <File>
+ <FileType>4</FileType>
+ <FileName>capi.ar</FileName>
+ <FilePath>mbed/LPC1768/ARM/capi.ar</FilePath>
+ </File>
+
+ <File>
+ <FileType>4</FileType>
+ <FileName>cpp.ar</FileName>
+ <FilePath>mbed/LPC1768/ARM/cpp.ar</FilePath>
+ </File>
+
+ </Files>
+ </Group>
+
+ <Group>
+ <GroupName>mbed</GroupName>
+ <Files>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>AnalogIn.h</FileName>
+ <FilePath>mbed/AnalogIn.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>AnalogOut.h</FileName>
+ <FilePath>mbed/AnalogOut.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>BusIn.h</FileName>
+ <FilePath>mbed/BusIn.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>BusInOut.h</FileName>
+ <FilePath>mbed/BusInOut.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>BusOut.h</FileName>
+ <FilePath>mbed/BusOut.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>CAN.h</FileName>
+ <FilePath>mbed/CAN.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>DigitalIn.h</FileName>
+ <FilePath>mbed/DigitalIn.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>DigitalInOut.h</FileName>
+ <FilePath>mbed/DigitalInOut.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>DigitalOut.h</FileName>
+ <FilePath>mbed/DigitalOut.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>DirHandle.h</FileName>
+ <FilePath>mbed/DirHandle.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>Ethernet.h</FileName>
+ <FilePath>mbed/Ethernet.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>FileHandle.h</FileName>
+ <FilePath>mbed/FileHandle.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>FileSystemLike.h</FileName>
+ <FilePath>mbed/FileSystemLike.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>FunctionPointer.h</FileName>
+ <FilePath>mbed/FunctionPointer.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>I2C.h</FileName>
+ <FilePath>mbed/I2C.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>I2CSlave.h</FileName>
+ <FilePath>mbed/I2CSlave.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>InterruptIn.h</FileName>
+ <FilePath>mbed/InterruptIn.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>LocalFileSystem.h</FileName>
+ <FilePath>mbed/LocalFileSystem.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>PortIn.h</FileName>
+ <FilePath>mbed/PortIn.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>PortInOut.h</FileName>
+ <FilePath>mbed/PortInOut.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>PortOut.h</FileName>
+ <FilePath>mbed/PortOut.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>PwmOut.h</FileName>
+ <FilePath>mbed/PwmOut.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>SPI.h</FileName>
+ <FilePath>mbed/SPI.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>SPISlave.h</FileName>
+ <FilePath>mbed/SPISlave.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>Serial.h</FileName>
+ <FilePath>mbed/Serial.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>Stream.h</FileName>
+ <FilePath>mbed/Stream.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>Ticker.h</FileName>
+ <FilePath>mbed/Ticker.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>Timeout.h</FileName>
+ <FilePath>mbed/Timeout.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>Timer.h</FileName>
+ <FilePath>mbed/Timer.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>TimerEvent.h</FileName>
+ <FilePath>mbed/TimerEvent.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>analogin_api.h</FileName>
+ <FilePath>mbed/analogin_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>analogout_api.h</FileName>
+ <FilePath>mbed/analogout_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>can_api.h</FileName>
+ <FilePath>mbed/can_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>can_helper.h</FileName>
+ <FilePath>mbed/can_helper.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>error.h</FileName>
+ <FilePath>mbed/error.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>ethernet_api.h</FileName>
+ <FilePath>mbed/ethernet_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>gpio_api.h</FileName>
+ <FilePath>mbed/gpio_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>gpio_irq_api.h</FileName>
+ <FilePath>mbed/gpio_irq_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>i2c_api.h</FileName>
+ <FilePath>mbed/i2c_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>mbed.h</FileName>
+ <FilePath>mbed/mbed.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>mbed_debug.h</FileName>
+ <FilePath>mbed/mbed_debug.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>mbed_interface.h</FileName>
+ <FilePath>mbed/mbed_interface.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>pinmap.h</FileName>
+ <FilePath>mbed/pinmap.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>platform.h</FileName>
+ <FilePath>mbed/platform.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>port_api.h</FileName>
+ <FilePath>mbed/port_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>pwmout_api.h</FileName>
+ <FilePath>mbed/pwmout_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>rtc_api.h</FileName>
+ <FilePath>mbed/rtc_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>rtc_time.h</FileName>
+ <FilePath>mbed/rtc_time.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>semihost_api.h</FileName>
+ <FilePath>mbed/semihost_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>serial_api.h</FileName>
+ <FilePath>mbed/serial_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>sleep_api.h</FileName>
+ <FilePath>mbed/sleep_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>spi_api.h</FileName>
+ <FilePath>mbed/spi_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>toolchain.h</FileName>
+ <FilePath>mbed/toolchain.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>us_ticker_api.h</FileName>
+ <FilePath>mbed/us_ticker_api.h</FilePath>
+ </File>
+
+ <File>
+ <FileType>5</FileType>
+ <FileName>wait_api.h</FileName>
+ <FilePath>mbed/wait_api.h</FilePath>
+ </File>
+
+ </Files>
+ </Group>
+
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/CONFIG.h Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,95 @@
+/*
+ Copyright (c) 2010 Andy Kirkham
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+
+#ifdef NOCOMPILE
+
+#ifndef MODDMA_CONFIG_H
+#define MODDMA_CONFIG_H
+
+#include "mbed.h"
+
+namespace AjK {
+
+// Forward reference.
+class MODDMA;
+
+class MODDMA_Channel_CFG_t {
+public:
+
+ // *****************************************
+ // From GPDMA by NXP MCU SW Application Team
+ // *****************************************
+
+ uint32_t ChannelNum; //!< DMA channel number, should be in range from 0 to 7.
+ uint32_t TransferSize; //!< Length/Size of transfer
+ uint32_t TransferWidth; //!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_m2m only
+ uint32_t SrcMemAddr; //!< Physical Src Addr, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::m2p
+ uint32_t DstMemAddr; //!< Physical Destination Address, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::p2m
+ uint32_t TransferType; //!< Transfer Type
+ uint32_t SrcConn; ///!< Peripheral Source Connection type, used in case TransferType is chosen as
+ uint32_t DstConn; //!< Peripheral Destination Connection type, used in case TransferType is chosen as
+ uint32_t DMALLI; //!< Linker List Item structure data address if there's no Linker List, set as '0'
+
+ // Mbed specifics.
+
+ MODDMA_Channel_CFG_t() {
+ isrIntTCStat = new FunctionPointer;
+ isrIntErrStat = new FunctionPointer;
+ }
+
+ ~MODDMA_Channel_CFG_t() {
+ delete(isrIntTCStat);
+ delete(isrIntErrStat);
+ }
+
+ class MODDMA_Channel_CFG_t * channelNum(uint32_t n) { ChannelNum = n; return this; }
+ class MODDMA_Channel_CFG_t * transferSize(uint32_t n) { TransferSize = n; return this; }
+ class MODDMA_Channel_CFG_t * transferWidth(uint32_t n) { TransferWidth = n; return this; }
+ class MODDMA_Channel_CFG_t * srcMemAddr(uint32_t n) { SrcMemAddr = n; return this; }
+ class MODDMA_Channel_CFG_t * dstMemAddr(uint32_t n) { DstMemAddr = n; return this; }
+ class MODDMA_Channel_CFG_t * transferType(uint32_t n) { TransferType = n; return this; }
+ class MODDMA_Channel_CFG_t * srcConn(uint32_t n) { SrcConn = n; return this; }
+ class MODDMA_Channel_CFG_t * dstConn(uint32_t n) { DstConn = n; return this; }
+ class MODDMA_Channel_CFG_t * dmaLLI(uint32_t n) { DMALLI = n; return this; }
+
+ uint32_t channelNum(void) { return ChannelNum; }
+
+ FunctionPointer *isrIntTCStat;
+ FunctionPointer *isrIntErrStat;
+};
+
+/**
+ * @brief GPDMA Linker List Item structure type definition
+ */
+class GPDMA_LLI_t
+{
+public:
+ uint32_t SrcAddr; //!< Source Address
+ uint32_t DstAddr; //!< Destination address
+ uint32_t NextLLI; //!< Next LLI address, otherwise set to '0'
+ uint32_t Control; //!< GPDMA Control of this LLI
+};
+
+}; // namespace AjK ends.
+
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/MODDMA/ChangeLog.c Tue May 29 02:41:54 2018 +0000 @@ -0,0 +1,79 @@ +/* $Id:$ + +1.13- 2 Mar 2013 + + * Update RESERVED9 to DMAREQSEL in SETUP.cpp + Thanks Bryce Chee for pointing it out. + +1.12- 14 Mar 2011 + + * Added example4.h that demonstrates alternately sending + two buffers (double buffering) to the DAC. All those + people building MP3 players may find this of interest. + +1.11- 13 Mar 2011 + + * Fixed a silly typo in the documentation of example3.h + +1.10- 13 Mar 2011 + + * The rescheduling showed the timer being stopped and restarted + to perform a new scheduled grab. This was changed to show the + timer free running and the reschedules being setup. + +1.9 - 13 Mar 2011 + + * Improved example3.h to add rescheduling additional grabs + based on the timer setup. + +1.8 - 13 Mar 2011 + + * Renamed example files to .h + * Added pseudo g2m and m2g transferTypes to support GPIO + "memory moves" but triggered by peripheral timer. To + support this new operating mode added example3.h + +1.7 - 13 Mar 2011 + + * Remove the test at the beginning of the channel setup. + +1.6 - 8 Mar 2011 + + * Fixed a typo bug. Reported by Wim van der Vegt + http://mbed.org/forum/mbed/topic/1798/?page=1#comment-9845 + +1.5 - 5 Feb 2011 + + * Found a bug in the NXP library that I had copied over. + http://mbed.org/forum/mbed/topic/1798 + * Added example2.cpp to support that forum thread. + +1.4 - 23/11/2010 + + * Added some extra overloaded methods to make calling certain + userland API methods simpler. + +1.3 - 23/10/2010 + + * Added the LLI class wrapper. + * Added checking channel's LLI for non-null before auto-disable + of a channel with the ISR. + * Tested with MODSERIAL which is now natively MODDMA "aware". + MODSERIAL can now, using MODDMA, send blocks of bytes out + of it's TX port under DMA control. + +1.2 - 23/10/2010 + + * Improved the IRQ callback attachment API to make + easier attachments when creating configurations. + +1.1 - 23/10/2010 + + * Tidied up example1.cpp + * Removed some unneeded methoids that cause compiler errs. + +1.0 - 23/11/2010 + + * First release + +*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/DATALUTS.cpp Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,147 @@
+/*
+ Copyright (c) 2010 Andy Kirkham
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+
+#include "MODDMA.h"
+
+#ifndef MBED_H
+#include "mbed.h"
+#endif
+
+#ifndef MODDMA_CONFIG_H
+#include "CONFIG.h"
+#endif
+
+namespace AjK {
+
+uint32_t
+MODDMA::LUTPerAddr(int n)
+{
+ const uint32_t lut[] = {
+ (uint32_t)&LPC_SSP0->DR // SSP0 Tx
+ , (uint32_t)&LPC_SSP0->DR // SSP0 Rx
+ , (uint32_t)&LPC_SSP1->DR // SSP1 Tx
+ , (uint32_t)&LPC_SSP1->DR // SSP1 Rx
+ , (uint32_t)&LPC_ADC->ADGDR // ADC
+ , (uint32_t)&LPC_I2S->I2STXFIFO // I2S Tx
+ , (uint32_t)&LPC_I2S->I2SRXFIFO // I2S Rx
+ , (uint32_t)&LPC_DAC->DACR // DAC
+ , (uint32_t)&LPC_UART0->THR // UART0 Tx
+ , (uint32_t)&LPC_UART0->RBR // UART0 Rx
+ , (uint32_t)&LPC_UART1->THR // UART1 Tx
+ , (uint32_t)&LPC_UART1->RBR // UART1 Rx
+ , (uint32_t)&LPC_UART2->THR // UART2 Tx
+ , (uint32_t)&LPC_UART2->RBR // UART2 Rx
+ , (uint32_t)&LPC_UART3->THR // UART3 Tx
+ , (uint32_t)&LPC_UART3->RBR // UART3 Rx
+ , (uint32_t)&LPC_TIM0->MR0 // MAT0.0
+ , (uint32_t)&LPC_TIM0->MR1 // MAT0.1
+ , (uint32_t)&LPC_TIM1->MR0 // MAT1.0
+ , (uint32_t)&LPC_TIM1->MR1 // MAT1.1
+ , (uint32_t)&LPC_TIM2->MR0 // MAT2.0
+ , (uint32_t)&LPC_TIM2->MR1 // MAT2.1
+ , (uint32_t)&LPC_TIM3->MR0 // MAT3.0
+ , (uint32_t)&LPC_TIM3->MR1 // MAT3.1
+ };
+ return lut[n & 0xFF];
+}
+
+uint32_t
+MODDMA::Channel_p(int channel)
+{
+ const uint32_t lut[] = {
+ (uint32_t)LPC_GPDMACH0
+ , (uint32_t)LPC_GPDMACH1
+ , (uint32_t)LPC_GPDMACH2
+ , (uint32_t)LPC_GPDMACH3
+ , (uint32_t)LPC_GPDMACH4
+ , (uint32_t)LPC_GPDMACH5
+ , (uint32_t)LPC_GPDMACH6
+ , (uint32_t)LPC_GPDMACH7
+ };
+ return lut[channel & 0xFF];
+}
+
+uint8_t
+MODDMA::LUTPerBurst(int n)
+{
+ const uint8_t lut[] = {
+ (uint8_t)_4 // SSP0 Tx
+ , (uint8_t)_4 // SSP0 Rx
+ , (uint8_t)_4 // SSP1 Tx
+ , (uint8_t)_4 // SSP1 Rx
+ , (uint8_t)_1 // ADC
+ , (uint8_t)_32 // I2S channel 0
+ , (uint8_t)_32 // I2S channel 1
+ , (uint8_t)_1 // DAC
+ , (uint8_t)_1 // UART0 Tx
+ , (uint8_t)_1 // UART0 Rx
+ , (uint8_t)_1 // UART1 Tx
+ , (uint8_t)_1 // UART1 Rx
+ , (uint8_t)_1 // UART2 Tx
+ , (uint8_t)_1 // UART2 Rx
+ , (uint8_t)_1 // UART3 Tx
+ , (uint8_t)_1 // UART3 Rx
+ , (uint8_t)_1 // MAT0.0
+ , (uint8_t)_1 // MAT0.1
+ , (uint8_t)_1 // MAT1.0
+ , (uint8_t)_1 // MAT1.1
+ , (uint8_t)_1 // MAT2.0
+ , (uint8_t)_1 // MAT2.1
+ , (uint8_t)_1 // MAT3.0
+ , (uint8_t)_1 // MAT3.1
+ };
+ return lut[n & 0xFFF];
+}
+
+uint8_t
+MODDMA::LUTPerWid(int n)
+{
+ const uint8_t lut[] = {
+ (uint8_t)byte // SSP0 Tx
+ , (uint8_t)byte // SSP0 Rx
+ , (uint8_t)byte // SSP1 Tx
+ , (uint8_t)byte // SSP1 Rx
+ , (uint8_t)word // ADC
+ , (uint8_t)word // I2S channel 0
+ , (uint8_t)word // I2S channel 1
+ , (uint8_t)word // DAC
+ , (uint8_t)byte // UART0 Tx
+ , (uint8_t)byte // UART0 Rx
+ , (uint8_t)byte // UART1 Tx
+ , (uint8_t)byte // UART1 Rx
+ , (uint8_t)byte // UART2 Tx
+ , (uint8_t)byte // UART2 Rx
+ , (uint8_t)byte // UART3 Tx
+ , (uint8_t)byte // UART3 Rx
+ , (uint8_t)word // MAT0.0
+ , (uint8_t)word // MAT0.1
+ , (uint8_t)word // MAT1.0
+ , (uint8_t)word // MAT1.1
+ , (uint8_t)word // MAT2.0
+ , (uint8_t)word // MAT2.1
+ , (uint8_t)word // MAT3.0
+ , (uint8_t)word // MAT3.1
+ };
+ return lut[n & 0xFFF];
+}
+
+}; // namespace AjK ends
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/INIT.cpp Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,69 @@
+/*
+ Copyright (c) 2010 Andy Kirkham
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+
+#include "MODDMA.h"
+
+namespace AjK {
+
+extern uint32_t oldDMAHandler;
+extern "C" void MODDMA_IRQHandler(void);
+extern class MODDMA *moddma_p;
+
+void
+MODDMA::init(bool isConstructorCalling, int Channels, int Tc, int Err)
+{
+ if (isConstructorCalling) {
+ if (LPC_SC->PCONP & (1UL << 29)) {
+ if (LPC_GPDMA->DMACConfig & 1) {
+ error("Only one instance of MODDMA can exist.");
+ }
+ }
+ LPC_SC->PCONP |= (1UL << 29);
+ LPC_GPDMA->DMACConfig = 1;
+ moddma_p = this;
+ for (int i = 0; i < 8; i++) {
+ setups[i] = (MODDMA_Config *)NULL;
+ }
+ }
+
+ // Reset channel configuration register(s)
+ if (Channels & 0x01) LPC_GPDMACH0->DMACCConfig = 0;
+ if (Channels & 0x02) LPC_GPDMACH1->DMACCConfig = 0;
+ if (Channels & 0x04) LPC_GPDMACH2->DMACCConfig = 0;
+ if (Channels & 0x08) LPC_GPDMACH3->DMACCConfig = 0;
+ if (Channels & 0x10) LPC_GPDMACH4->DMACCConfig = 0;
+ if (Channels & 0x20) LPC_GPDMACH5->DMACCConfig = 0;
+ if (Channels & 0x40) LPC_GPDMACH6->DMACCConfig = 0;
+ if (Channels & 0x80) LPC_GPDMACH7->DMACCConfig = 0;
+
+ /* Clear DMA interrupt and error flag */
+ LPC_GPDMA->DMACIntTCClear = Tc;
+ LPC_GPDMA->DMACIntErrClr = Err;
+
+ if (isConstructorCalling) {
+ oldDMAHandler = NVIC_GetVector(DMA_IRQn);
+ NVIC_SetVector(DMA_IRQn, (uint32_t)MODDMA_IRQHandler);
+ NVIC_EnableIRQ(DMA_IRQn);
+ }
+}
+
+}; // namespace AjK ends
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/MODDMA.cpp Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,157 @@
+/*
+ Copyright (c) 2010 Andy Kirkham
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+#include "iomacros.h"
+#include "MODDMA.h"
+
+namespace AjK {
+
+// Create a "hook" for our ISR to make callbacks. Set by init()
+class MODDMA *moddma_p = (class MODDMA *)NULL;
+
+void
+MODDMA::Enable(CHANNELS ChannelNumber)
+{
+ LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );
+ pChannel->DMACCConfig |= _E;
+}
+
+bool
+MODDMA::Enabled(CHANNELS ChannelNumber)
+{
+ LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );
+ return (bool)(pChannel->DMACCConfig & _E);
+}
+
+void
+MODDMA::Disable(CHANNELS ChannelNumber)
+{
+ LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );
+ pChannel->DMACCConfig &= ~(_E);
+}
+
+bool
+MODDMA::isActive(CHANNELS ChannelNumber)
+{
+ LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );
+ return (bool)( pChannel->DMACCConfig & CxConfig_A() ) ;
+}
+
+void
+MODDMA::haltChannel(CHANNELS ChannelNumber)
+{
+ LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );
+ pChannel->DMACCConfig |= CxConfig_H();
+}
+
+uint32_t
+MODDMA::getControl(CHANNELS ChannelNumber)
+{
+ LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );
+ return pChannel->DMACCControl;
+}
+
+uint32_t oldDMAHandler = 0;
+typedef void (*MODDMA_FN)(void);
+
+extern "C" void MODDMA_IRQHandler(void) {
+ uint32_t channel_mask;
+
+ if (moddma_p == (class MODDMA *)NULL) {
+ if (oldDMAHandler) {
+ ((MODDMA_FN)oldDMAHandler)();
+ return;
+ }
+ else {
+ error("Interrupt without instance");
+ }
+ }
+
+ for (int channel_number = 0; channel_number < 8; channel_number++) {
+ channel_mask = (1UL << channel_number);
+ if (LPC_GPDMA->DMACIntStat & channel_mask) {
+ if (LPC_GPDMA->DMACIntTCStat & channel_mask) {
+ if (moddma_p->setups[channel_number] != (MODDMA_Config *)NULL) {
+ moddma_p->setIrqProcessingChannel((MODDMA::CHANNELS)channel_number);
+ moddma_p->setIrqType(MODDMA::TcIrq);
+ moddma_p->setups[channel_number]->isrIntTCStat->call();
+ moddma_p->isrIntTCStat.call();
+ // The user callback should clear the IRQ. But if they forget
+ // then the Mbed will lockup. So, check to see if the IRQ has
+ // been dismissed, if not, we will dismiss it here.
+ if (LPC_GPDMA->DMACIntTCStat & channel_mask) {
+ LPC_GPDMA->DMACIntTCClear = channel_mask;
+ }
+ // If the user has left the channel enabled, disable it.
+ // Note, we don't check Active here as it may block inside
+ // an ISR, we just shut it down immediately. If the user
+ // must wait for completion they should implement their
+ // own ISR. But only disable if the LLI linked list register
+ // is null otherwise we can crap out a series of transfers.
+ if (moddma_p->Enabled( (MODDMA::CHANNELS)channel_number )) {
+ if (moddma_p->lli( (MODDMA::CHANNELS)channel_number ) == 0 ) {
+ moddma_p->Disable( (MODDMA::CHANNELS)channel_number );
+ }
+ }
+ }
+ }
+
+ if (LPC_GPDMA->DMACIntErrStat & channel_mask) {
+ if (moddma_p->setups[channel_number] != (MODDMA_Config *)NULL) {
+ moddma_p->setIrqProcessingChannel((MODDMA::CHANNELS)channel_number);
+ moddma_p->setIrqType(MODDMA::ErrIrq);
+ moddma_p->setups[channel_number]->isrIntErrStat->call();
+ moddma_p->isrIntErrStat.call();
+ // The user callback should clear the IRQ. But if they forget
+ // then the Mbed will lockup. So, check to see if the IRQ has
+ // been dismissed, if not, we will dismiss it here.
+ if (LPC_GPDMA->DMACIntErrStat & channel_mask) {
+ LPC_GPDMA->DMACIntErrClr = channel_mask;
+ }
+ // If the user has left the channel enabled, disable it.
+ // Not, we don't check Active here as it may block inside
+ // an ISR, we just shut it down immediately. If the user
+ // must wait for completion they should implement their
+ // own ISR. But only disable if the LLI linked list register
+ // is null otherwise we can crap out a series of transfers.
+ if (moddma_p->Enabled( (MODDMA::CHANNELS)channel_number )) {
+ if (moddma_p->lli( (MODDMA::CHANNELS)channel_number ) == 0 ) {
+ moddma_p->Disable( (MODDMA::CHANNELS)channel_number );
+ }
+ }
+ }
+ }
+ }
+ }
+
+ /* IRQ should be handled by now, check to make sure. */
+ if (LPC_GPDMA->DMACIntStat) {
+ ((MODDMA_FN)oldDMAHandler)();
+ LPC_GPDMA->DMACIntTCClear = (uint32_t)0xFF; /* If not, clear anyway! */
+ }
+ if (LPC_GPDMA->DMACIntErrStat) {
+ ((MODDMA_FN)oldDMAHandler)();
+ LPC_GPDMA->DMACIntErrClr = (uint32_t)0xFF; /* If not, clear anyway! */
+ }
+}
+
+}; // namespace AjK ends
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/MODDMA.h Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,693 @@
+/*
+ Copyright (c) 2010 Andy Kirkham
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+
+ @file MODDMA.h
+ @purpose Adds DMA controller and multiple transfer configurations
+ @version see ChangeLog.c
+ @date Nov 2010
+ @author Andy Kirkham
+*/
+
+#ifndef MODDMA_H
+#define MODDMA_H
+
+/** @defgroup API The MODDMA API */
+/** @defgroup MISC Misc MODSERIAL functions */
+/** @defgroup INTERNALS MODSERIAL Internals */
+
+#include "mbed.h"
+#include "iomacros.h"
+
+namespace AjK {
+
+/**
+ * @brief The MODDMA configuration system
+ * @author Andy Kirkham
+ * @see http://mbed.org/cookbook/MODDMA_Config
+ * @see MODDMA
+ * @see API
+ *
+ * <b>MODDMA_Config</b> defines a configuration that can be passed to the MODDMA controller
+ * instance to perform a GPDMA data transfer.
+ */
+class MODDMA_Config {
+protected:
+
+ // *****************************************
+ // From GPDMA by NXP MCU SW Application Team
+ // *****************************************
+
+ uint32_t ChannelNum; //!< DMA channel number, should be in range from 0 to 7.
+ uint32_t TransferSize; //!< Length/Size of transfer
+ uint32_t TransferWidth; //!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_m2m only
+ uint32_t SrcMemAddr; //!< Physical Src Addr, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::m2p
+ uint32_t DstMemAddr; //!< Physical Destination Address, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::p2m
+ uint32_t TransferType; //!< Transfer Type
+ uint32_t SrcConn; //!< Peripheral Source Connection type, used in case TransferType is chosen as
+ uint32_t DstConn; //!< Peripheral Destination Connection type, used in case TransferType is chosen as
+ uint32_t DMALLI; //!< Linker List Item structure data address if there's no Linker List, set as '0'
+ uint32_t DMACSync; //!< DMACSync if required.
+
+ // Mbed specifics.
+
+public:
+
+ MODDMA_Config() {
+ isrIntTCStat = new FunctionPointer;
+ isrIntErrStat = new FunctionPointer;
+ ChannelNum = 0xFFFF;
+ TransferSize = 0;
+ TransferWidth = 0;
+ SrcMemAddr = 0;
+ DstMemAddr = 0;
+ TransferType = 0;
+ SrcConn = 0;
+ DstConn = 0;
+ DMALLI = 0;
+ DMACSync = 0;
+ }
+
+ ~MODDMA_Config() {
+ delete(isrIntTCStat);
+ delete(isrIntErrStat);
+ }
+
+ class MODDMA_Config * channelNum(uint32_t n) { ChannelNum = n & 0x7; return this; }
+ class MODDMA_Config * transferSize(uint32_t n) { TransferSize = n; return this; }
+ class MODDMA_Config * transferWidth(uint32_t n) { TransferWidth = n; return this; }
+ class MODDMA_Config * srcMemAddr(uint32_t n) { SrcMemAddr = n; return this; }
+ class MODDMA_Config * dstMemAddr(uint32_t n) { DstMemAddr = n; return this; }
+ class MODDMA_Config * transferType(uint32_t n) { TransferType = n; return this; }
+ class MODDMA_Config * srcConn(uint32_t n) { SrcConn = n; return this; }
+ class MODDMA_Config * dstConn(uint32_t n) { DstConn = n; return this; }
+ class MODDMA_Config * dmaLLI(uint32_t n) { DMALLI = n; return this; }
+ class MODDMA_Config * dmacSync(uint32_t n) { DMACSync = n; return this; }
+
+ uint32_t channelNum(void) { return ChannelNum; }
+ uint32_t transferSize(void) { return TransferSize; }
+ uint32_t transferWidth(void) { return TransferWidth; }
+ uint32_t srcMemAddr(void) { return SrcMemAddr; }
+ uint32_t dstMemAddr(void) { return DstMemAddr; }
+ uint32_t transferType(void) { return TransferType; }
+ uint32_t srcConn(void) { return SrcConn; }
+ uint32_t dstConn(void) { return DstConn; }
+ uint32_t dmaLLI(void) { return DMALLI; }
+ uint32_t dmacSync(void) { return DMACSync; }
+
+ /**
+ * Attach a callback to the TC IRQ configuration.
+ *
+ * @param fptr A function pointer to call
+ * @return this
+ */
+ class MODDMA_Config * attach_tc(void (*fptr)(void)) {
+ isrIntTCStat->attach(fptr);
+ return this;
+ }
+
+ /**
+ * Attach a callback to the ERR IRQ configuration.
+ *
+ * @param fptr A function pointer to call
+ * @return this
+ */
+ class MODDMA_Config * attach_err(void (*fptr)(void)) {
+ isrIntErrStat->attach(fptr);
+ return this;
+ }
+
+ /**
+ * Attach a callback to the TC IRQ configuration.
+ *
+ * @param tptr A template pointer to the calling object
+ * @param mptr A method pointer within the object to call.
+ * @return this
+ */
+ template<typename T>
+ class MODDMA_Config * attach_tc(T* tptr, void (T::*mptr)(void)) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ isrIntTCStat->attach(tptr, mptr);
+ }
+ return this;
+ }
+
+ /**
+ * Attach a callback to the ERR IRQ configuration.
+ *
+ * @param tptr A template pointer to the calling object
+ * @param mptr A method pointer within the object to call.
+ * @return this
+ */
+ template<typename T>
+ class MODDMA_Config * attach_err(T* tptr, void (T::*mptr)(void)) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ isrIntErrStat->attach(tptr, mptr);
+ }
+ return this;
+ }
+ FunctionPointer *isrIntTCStat;
+ FunctionPointer *isrIntErrStat;
+};
+
+/**
+ * @brief The MODDMA configuration system (linked list items)
+ * @author Andy Kirkham
+ * @see http://mbed.org/cookbook/MODDMA_Config
+ * @see MODDMA
+ * @see MODDMA_Config
+ * @see API
+ */
+class MODDMA_LLI {
+public:
+ class MODDMA_LLI *srcAddr(uint32_t n) { SrcAddr = n; return this; }
+ class MODDMA_LLI *dstAddr(uint32_t n) { DstAddr = n; return this; }
+ class MODDMA_LLI *nextLLI(uint32_t n) { NextLLI = n; return this; }
+ class MODDMA_LLI *control(uint32_t n) { Control = n; return this; }
+ uint32_t srcAddr(void) { return SrcAddr; }
+ uint32_t dstAddr(void) { return DstAddr; }
+ uint32_t nextLLI(void) { return NextLLI; }
+ uint32_t control(void) { return Control; }
+
+ uint32_t SrcAddr; //!< Source Address
+ uint32_t DstAddr; //!< Destination address
+ uint32_t NextLLI; //!< Next LLI address, otherwise set to '0'
+ uint32_t Control; //!< GPDMA Control of this LLI
+};
+
+
+
+ /**
+ * @brief MODDMA GPDMA Controller
+ * @author Andy Kirkham
+ * @see http://mbed.org/cookbook/MODDMA
+ * @see example1.cpp
+ * @see API
+ *
+ * <b>MODDMA</b> defines a GPDMA controller and multiple DMA configurations that allow for DMA
+ * transfers from memory to memory, memory to peripheral or peripheral to memory.
+ *
+ * At the heart of the library is the MODDMA class that defines a single instance controller that
+ * manages all the GPDMA hardware registers and interrupts. The controller can accept multiple
+ * configurations that define the channel transfers. Each configuration specifies the source and
+ * destination information and other associated parts to maintain the transfer process.
+ *
+ * Standard example:
+ * @code
+ * #include "mbed.h"
+ * #include "MODDMA.h"
+ *
+ * DigitalOut led1(LED1);
+ * Serial pc(USBTX, USBRX); // tx, rx
+ * MODDMA dma;
+ *
+ * int main() {
+ *
+ * // Create a string buffer to send directly to a Uart/Serial
+ * char s[] = "***DMA*** ABCDEFGHIJKLMNOPQRSTUVWXYZ ***DMA***";
+ *
+ * // Create a transfer configuarion
+ * MODDMA_Config *config = new MODDMA_Config;
+ *
+ * // Provide a "minimal" setup for demo purposes.
+ * config
+ * ->channelNum ( MODDMA::Channel_0 ) // The DMA channel to use.
+ * ->srcMemAddr ( (uint32_t) &s ) // A pointer to the buffer to send.
+ * ->transferSize ( sizeof(s) ) // The size of that buffer.
+ * ->transferType ( MODDMA::m2p ) // Source is memory, destination is peripheral
+ * ->dstConn ( MODDMA::UART0_Tx ) // Specifically, peripheral is Uart0 TX (USBTX, USBRX)
+ * ; // config end.
+ *
+ * // Pass the configuration to the MODDMA controller.
+ * dma.Setup( config );
+ *
+ * // Enable the channel and begin transfer.
+ * dma.Enable( config->channelNum() );
+ *
+ * while(1) {
+ * led1 = !led1;
+ * wait(0.25);
+ * }
+ * }
+ * @endcode
+ */
+class MODDMA
+{
+public:
+
+ //! Channel definitions.
+ enum CHANNELS {
+ Channel_0 = 0 /*!< Channel 0 */
+ , Channel_1 /*!< Channel 1 */
+ , Channel_2 /*!< Channel 2 */
+ , Channel_3 /*!< Channel 3 */
+ , Channel_4 /*!< Channel 4 */
+ , Channel_5 /*!< Channel 5 */
+ , Channel_6 /*!< Channel 6 */
+ , Channel_7 /*!< Channel 7 */
+ };
+
+ //! Interrupt callback types.
+ enum IrqType_t {
+ TcIrq = 0 /*!< Terminal Count interrupt */
+ , ErrIrq /*!< Error interrupt */
+ };
+
+ //! Return status codes.
+ enum Status {
+ Ok = 0 /*!< Ok, suceeded */
+ , Error = -1 /*!< General error */
+ , ErrChInUse = -2 /*!< Specific error, channel in use */
+ };
+
+ //! DMA Connection number definitions
+ enum GPDMA_CONNECTION {
+ SSP0_Tx = 0UL /*!< SSP0 Tx */
+ , SSP0_Rx = 1UL /*!< SSP0 Rx */
+ , SSP1_Tx = 2UL /*!< SSP1 Tx */
+ , SSP1_Rx = 3UL /*!< SSP1 Rx */
+ , ADC = 4UL /*!< ADC */
+ , I2S_Channel_0 = 5UL /*!< I2S channel 0 */
+ , I2S_Channel_1 = 6UL /*!< I2S channel 1 */
+ , DAC = 7UL /*!< DAC */
+ , UART0_Tx = 8UL /*!< UART0 Tx */
+ , UART0_Rx = 9UL /*!< UART0 Rx */
+ , UART1_Tx = 10UL /*!< UART1 Tx */
+ , UART1_Rx = 11UL /*!< UART1 Rx */
+ , UART2_Tx = 12UL /*!< UART2 Tx */
+ , UART2_Rx = 13UL /*!< UART2 Rx */
+ , UART3_Tx = 14UL /*!< UART3 Tx */
+ , UART3_Rx = 15UL /*!< UART3 Rx */
+ , MAT0_0 = 16UL /*!< MAT0.0 */
+ , MAT0_1 = 17UL /*!< MAT0.1 */
+ , MAT1_0 = 18UL /*!< MAT1.0 */
+ , MAT1_1 = 19UL /*!< MAT1.1 */
+ , MAT2_0 = 20UL /**< MAT2.0 */
+ , MAT2_1 = 21UL /*!< MAT2.1 */
+ , MAT3_0 = 22UL /*!< MAT3.0 */
+ , MAT3_1 = 23UL /*!< MAT3.1 */
+ };
+
+ //! GPDMA Transfer type definitions
+ enum GPDMA_TRANSFERTYPE {
+ m2m = 0UL /*!< Memory to memory - DMA control */
+ , m2p = 1UL /*!< Memory to peripheral - DMA control */
+ , p2m = 2UL /*!< Peripheral to memory - DMA control */
+ , p2p = 3UL /*!< Src peripheral to dest peripheral - DMA control */
+ , g2m = 4UL /*!< Psuedo special case for reading "peripheral GPIO" that's memory mapped. */
+ , m2g = 5UL /*!< Psuedo Special case for writing "peripheral GPIO" that's memory mapped. */
+ };
+
+ //! Burst size in Source and Destination definitions */
+ enum GPDMA_BSIZE {
+ _1 = 0UL /*!< Burst size = 1 */
+ , _4 = 1UL /*!< Burst size = 4 */
+ , _8 = 2UL /*!< Burst size = 8 */
+ , _16 = 3UL /*!< Burst size = 16 */
+ , _32 = 4UL /*!< Burst size = 32 */
+ , _64 = 5UL /*!< Burst size = 64 */
+ , _128 = 6UL /*!< Burst size = 128 */
+ , _256 = 7UL /*!< Burst size = 256 */
+ };
+
+ //! Width in Src transfer width and Dest transfer width definitions */
+ enum GPDMA_WIDTH {
+ byte = 0UL /*!< Width = 1 byte */
+ , halfword = 1UL /*!< Width = 2 bytes */
+ , word = 2UL /*!< Width = 4 bytes */
+ };
+
+ //! DMA Request Select Mode definitions. */
+ enum GPDMA_REQSEL {
+ uart = 0UL /*!< UART TX/RX is selected */
+ , timer = 1UL /*!< Timer match is selected */
+ };
+
+ //! GPDMA Control register bits.
+ enum Config {
+ _E = 1 /*!< DMA Controller enable */
+ , _M = 2 /*!< AHB Master endianness configuration */
+ };
+
+ //! GPDMA Channel config register bits.
+ enum CConfig {
+ _CE = (1UL << 0) /*!< Channel enable */
+ , _IE = (1UL << 14) /*!< Interrupt error mask */
+ , _ITC = (1UL << 15) /*!< Terminal count interrupt mask */
+ , _L = (1UL << 16) /*!< Lock */
+ , _A = (1UL << 17) /*!< Active */
+ , _H = (1UL << 18) /*!< Halt */
+ };
+
+ /**
+ * The MODDMA constructor is used to initialise the DMA controller object.
+ */
+ MODDMA() { init(true); }
+
+ /**
+ * The MODDMA destructor.
+ */
+ ~MODDMA() {}
+
+ /**
+ * Used to setup the DMA controller to prepare for a data transfer.
+ *
+ * @ingroup API
+ * @param isConstructorCalling Set true when called from teh constructor
+ * @param
+ */
+ void init(bool isConstructorCalling, int Channels = 0xFF, int Tc = 0xFF, int Err = 0xFF);
+
+ /**
+ * Used to setup and enable the DMA controller.
+ *
+ * @see Setup
+ * @see Enable
+ * @ingroup API
+ * @param c A pointer to an instance of MODDMA_Config to setup.
+ */
+ uint32_t Prepare(MODDMA_Config *c) {
+ uint32_t u = Setup(c);
+ if (u) Enable(c);
+ return u;
+ }
+
+ /**
+ * Used to setup the DMA controller to prepare for a data transfer.
+ *
+ * @ingroup API
+ * @param c A pointer to an instance of MODDMA_Config to setup.
+ */
+ uint32_t Setup(MODDMA_Config *c);
+
+ /**
+ * Enable and begin data transfer.
+ *
+ * @ingroup API
+ * @param ChannelNumber Type CHANNELS, the channel number to enable
+ */
+ void Enable(CHANNELS ChannelNumber);
+
+ /**
+ * Enable and begin data transfer (overloaded function)
+ *
+ * @ingroup API
+ * @param ChannelNumber Type uin32_t, the channel number to enable
+ */
+ void Enable(uint32_t ChannelNumber) { Enable((CHANNELS)(ChannelNumber & 0x7)); }
+
+ /**
+ * Enable and begin data transfer (overloaded function)
+ *
+ * @ingroup API
+ * @param config A pointer to teh configuration
+ */
+ void Enable(MODDMA_Config *config) { Enable( config->channelNum() ); }
+
+
+ /**
+ * Disable a channel and end data transfer.
+ *
+ * @ingroup API
+ * @param ChannelNumber Type CHANNELS, the channel number to enable
+ */
+ void Disable(CHANNELS ChannelNumber);
+
+ /**
+ * Disable a channel and end data transfer (overloaded function)
+ *
+ * @ingroup API
+ * @param ChannelNumber Type uin32_t, the channel number to disable
+ */
+ void Disable(uint32_t ChannelNumber) { Disable((CHANNELS)(ChannelNumber & 0x7)); }
+
+ /**
+ * Is the specified channel enabled?
+ *
+ * @ingroup API
+ * @param ChannelNumber Type CHANNELS, the channel number to test
+ * @return bool true if enabled, false otherwise.
+ */
+ bool Enabled(CHANNELS ChannelNumber);
+
+ /**
+ * Is the specified channel enabled? (overloaded function)
+ *
+ * @ingroup API
+ * @param ChannelNumber Type uin32_t, the channel number to test
+ * @return bool true if enabled, false otherwise.
+ */
+ bool Enabled(uint32_t ChannelNumber) { return Enabled((CHANNELS)(ChannelNumber & 0x7)); }
+
+ __INLINE uint32_t IntStat(uint32_t n) { return (1UL << n) & 0xFF; }
+ __INLINE uint32_t IntTCStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
+ __INLINE uint32_t IntTCClear_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
+ __INLINE uint32_t IntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
+ __INLINE uint32_t IntErrClr_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
+ __INLINE uint32_t RawIntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
+ __INLINE uint32_t EnbldChns_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
+ __INLINE uint32_t SoftBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
+ __INLINE uint32_t SoftSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
+ __INLINE uint32_t SoftLBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
+ __INLINE uint32_t SoftLSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
+ __INLINE uint32_t Sync_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
+ __INLINE uint32_t ReqSel_Input(uint32_t n) { return (1UL << (n - 8)) & 0xFF; }
+
+
+ __INLINE uint32_t CxControl_TransferSize(uint32_t n) { return (n & 0xFFF) << 0; }
+ __INLINE uint32_t CxControl_SBSize(uint32_t n) { return (n & 0x7) << 12; }
+ __INLINE uint32_t CxControl_DBSize(uint32_t n) { return (n & 0x7) << 15; }
+ __INLINE uint32_t CxControl_SWidth(uint32_t n) { return (n & 0x7) << 18; }
+ __INLINE uint32_t CxControl_DWidth(uint32_t n) { return (n & 0x7) << 21; }
+ __INLINE uint32_t CxControl_SI() { return (1UL << 26); }
+ __INLINE uint32_t CxControl_DI() { return (1UL << 27); }
+ __INLINE uint32_t CxControl_Prot1() { return (1UL << 28); }
+ __INLINE uint32_t CxControl_Prot2() { return (1UL << 29); }
+ __INLINE uint32_t CxControl_Prot3() { return (1UL << 30); }
+ __INLINE uint32_t CxControl_I() { return (1UL << 31); }
+ __INLINE uint32_t CxControl_E() { return (1UL << 0); }
+ __INLINE uint32_t CxConfig_SrcPeripheral(uint32_t n) { return (n & 0x1F) << 1; }
+ __INLINE uint32_t CxConfig_DestPeripheral(uint32_t n) { return (n & 0x1F) << 6; }
+ __INLINE uint32_t CxConfig_TransferType(uint32_t n) { return (n & 0x7) << 11; }
+ __INLINE uint32_t CxConfig_IE() { return (1UL << 14); }
+ __INLINE uint32_t CxConfig_ITC() { return (1UL << 15); }
+ __INLINE uint32_t CxConfig_L() { return (1UL << 16); }
+ __INLINE uint32_t CxConfig_A() { return (1UL << 17); }
+ __INLINE uint32_t CxConfig_H() { return (1UL << 18); }
+
+ /**
+ * A store for up to 8 (8 channels) of configurations.
+ * @see MODDMA_Config
+ */
+ MODDMA_Config *setups[8];
+
+ /**
+ * Get a pointer to the current configuration the ISR is servicing.
+ *
+ * @ingroup API
+ * @return MODDMA_Config * A pointer to the setup the ISR is currently servicing.
+ */
+ MODDMA_Config *getConfig(void) { return setups[IrqProcessingChannel]; }
+
+ /**
+ * Set which channel the ISR is currently servicing.
+ *
+ * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS ***
+ *
+ * Must be public so the extern "C" ISR can use it.
+ */
+ void setIrqProcessingChannel(CHANNELS n) { IrqProcessingChannel = n; }
+
+ /**
+ * Gets which channel the ISR is currently servicing.
+ *
+ * @ingroup API
+ * @return CHANNELS The current channel the ISR is servicing.
+ */
+ CHANNELS irqProcessingChannel(void) { return IrqProcessingChannel; }
+
+ /**
+ * Sets which type of IRQ the ISR is making a callback for.
+ *
+ * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS ***
+ *
+ * Must be public so the extern "C" ISR can use it.
+ */
+ void setIrqType(IrqType_t n) { IrqType = n; }
+
+ /**
+ * Get which type of IRQ the ISR is calling you about,
+ * terminal count or error.
+ */
+ IrqType_t irqType(void) { return IrqType; }
+
+ /**
+ * Clear the interrupt after handling.
+ *
+ * @param CHANNELS The channel the IQR occured on.
+ */
+ void clearTcIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); }
+
+ /**
+ * Clear the interrupt the ISR is currently handing..
+ */
+ void clearTcIrq(void) { clearTcIrq( IrqProcessingChannel ); }
+
+ /**
+ * Clear the error interrupt after handling.
+ *
+ * @ingroup API
+ * @param CHANNELS The channel the IQR occured on.
+ */
+ void clearErrIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); }
+
+ /**
+ * Clear the error interrupt the ISR is currently handing.
+ * @ingroup API
+ */
+ void clearErrIrq(void) { clearErrIrq( IrqProcessingChannel ); }
+
+ /**
+ * Is the supplied channel currently active?
+ *
+ * @ingroup API
+ * @param CHANNELS The channel to inquire about.
+ * @return bool true if active, false otherwise.
+ */
+ bool isActive(CHANNELS ChannelNumber);
+
+ /**
+ * Halt the supplied channel.
+ *
+ * @ingroup API
+ * @param CHANNELS The channel to halt.
+ */
+ void haltChannel(CHANNELS ChannelNumber);
+
+ /**
+ * get a channels control register.
+ *
+ * @ingroup API
+ * @param CHANNELS The channel to get the control register for.
+ */
+ uint32_t getControl(CHANNELS ChannelNumber);
+
+ /**
+ * Wait for channel transfer to complete and then halt.
+ *
+ * @ingroup API
+ * @param CHANNELS The channel to wait for then halt.
+ */
+ void haltAndWaitChannelComplete(CHANNELS n) { haltChannel(n); while (isActive(n)); }
+
+ /**
+ * Attach a callback to the TC IRQ controller.
+ *
+ * @ingroup API
+ * @param fptr A function pointer to call
+ * @return this
+ */
+ void attach_tc(void (*fptr)(void)) {
+ isrIntTCStat.attach(fptr);
+ }
+
+ /**
+ * Attach a callback to the TC IRQ controller.
+ *
+ * @ingroup API
+ * @param tptr A template pointer to the calling object
+ * @param mptr A method pointer within the object to call.
+ * @return this
+ */
+ template<typename T>
+ void attach_tc(T* tptr, void (T::*mptr)(void)) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ isrIntTCStat.attach(tptr, mptr);
+ }
+ }
+
+ /**
+ * The MODDMA controllers terminal count interrupt callback.
+ */
+ FunctionPointer isrIntTCStat;
+
+ /**
+ * Attach a callback to the ERR IRQ controller.
+ *
+ * @ingroup API
+ * @param fptr A function pointer to call
+ * @return this
+ */
+ void attach_err(void (*fptr)(void)) {
+ isrIntErrStat.attach(fptr);
+ }
+
+ /**
+ * Attach a callback to the ERR IRQ controller.
+ *
+ * @ingroup API
+ * @param tptr A template pointer to the calling object
+ * @param mptr A method pointer within the object to call.
+ * @return this
+ */
+ template<typename T>
+ void attach_err(T* tptr, void (T::*mptr)(void)) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ isrIntErrStat.attach(tptr, mptr);
+ }
+ }
+
+ /**
+ * Get the Linked List index regsiter for the requested channel.
+ *
+ * @param channelNum The channel number.
+ * @return uint32_t The value of the DMACCLLI register
+ */
+ uint32_t lli(CHANNELS ChannelNumber, MODDMA_LLI *set = 0) {
+ LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber & 0x7 );
+ if (set) pChannel->DMACCLLI = (uint32_t)set;
+ return pChannel->DMACCLLI;
+ }
+
+ /**
+ * The MODDMA controllers error interrupt callback.
+ */
+ FunctionPointer isrIntErrStat;
+
+ uint32_t Channel_p(int channel);
+
+protected:
+
+ // Data LUTs.
+ uint32_t LUTPerAddr(int n);
+ uint8_t LUTPerBurst(int n);
+ uint8_t LUTPerWid(int n);
+ //uint32_t Channel_p(int channel);
+
+ CHANNELS IrqProcessingChannel;
+
+ IrqType_t IrqType;
+};
+
+}; // namespace AjK ends.
+
+using namespace AjK;
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/SETUP.cpp Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,194 @@
+/*
+ Copyright (c) 2010 Andy Kirkham
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+
+#include "MODDMA.h"
+
+namespace AjK {
+
+uint32_t
+MODDMA::Setup(MODDMA_Config *config)
+{
+ LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( config->channelNum() );
+
+ setups[config->channelNum() & 0x7] = config;
+
+ // Reset the Interrupt status
+ LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );
+ LPC_GPDMA->DMACIntErrClr = IntErrClr_Ch ( config->channelNum() );
+
+ // Clear DMA configure
+ pChannel->DMACCControl = 0x00;
+ pChannel->DMACCConfig = 0x00;
+
+ // Assign Linker List Item value
+ pChannel->DMACCLLI = config->dmaLLI();
+
+ // Set value to Channel Control Registers
+ switch (config->transferType()) {
+
+ // Memory to memory
+ case m2m:
+ // Assign physical source and destination address
+ pChannel->DMACCSrcAddr = config->srcMemAddr();
+ pChannel->DMACCDestAddr = config->dstMemAddr();
+ pChannel->DMACCControl
+ = CxControl_TransferSize(config->transferSize())
+ | CxControl_SBSize(_32)
+ | CxControl_DBSize(_32)
+ | CxControl_SWidth(config->transferWidth())
+ | CxControl_DWidth(config->transferWidth())
+ | CxControl_SI()
+ | CxControl_DI()
+ | CxControl_I();
+ break;
+
+ // Memory to peripheral
+ case m2p:
+ // Assign physical source
+ pChannel->DMACCSrcAddr = config->srcMemAddr();
+ // Assign peripheral destination address
+ pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
+ pChannel->DMACCControl
+ = CxControl_TransferSize((uint32_t)config->transferSize())
+ | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn()))
+ | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
+ | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn()))
+ | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
+ | CxControl_SI()
+ | CxControl_I();
+ break;
+
+ // Peripheral to memory
+ case p2m:
+ // Assign peripheral source address
+ pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
+ // Assign memory destination address
+ pChannel->DMACCDestAddr = config->dstMemAddr();
+ pChannel->DMACCControl
+ = CxControl_TransferSize((uint32_t)config->transferSize())
+ | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
+ | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn()))
+ | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
+ | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn()))
+ | CxControl_DI()
+ | CxControl_I();
+ break;
+
+ // Peripheral to peripheral
+ case p2p:
+ // Assign peripheral source address
+ pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
+ // Assign peripheral destination address
+ pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
+ pChannel->DMACCControl
+ = CxControl_TransferSize((uint32_t)config->transferSize())
+ | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
+ | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
+ | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
+ | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
+ | CxControl_I();
+ break;
+
+ // GPIO to memory
+ case g2m:
+ // Assign GPIO source address
+ pChannel->DMACCSrcAddr = config->srcMemAddr();
+ // Assign memory destination address
+ pChannel->DMACCDestAddr = config->dstMemAddr();
+ pChannel->DMACCControl
+ = CxControl_TransferSize((uint32_t)config->transferSize())
+ | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
+ | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn()))
+ | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
+ | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn()))
+ | CxControl_DI()
+ | CxControl_I();
+ break;
+
+ // Memory to GPIO
+ case m2g:
+ // Assign physical source
+ pChannel->DMACCSrcAddr = config->srcMemAddr();
+ // Assign peripheral destination address
+ pChannel->DMACCDestAddr = config->dstMemAddr();
+ pChannel->DMACCControl
+ = CxControl_TransferSize((uint32_t)config->transferSize())
+ | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn()))
+ | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
+ | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn()))
+ | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
+ | CxControl_SI()
+ | CxControl_I();
+ break;
+
+ // Do not support any more transfer type, return ERROR
+ default:
+ return 0;
+ }
+
+ // Re-Configure DMA Request Select for source peripheral
+ if (config->srcConn() > 15) {
+ LPC_SC->DMAREQSEL |= (1 << (config->srcConn() - 16));
+ }
+ else {
+ LPC_SC->DMAREQSEL &= ~(1 << (config->srcConn() - 8));
+ }
+
+ // Re-Configure DMA Request Select for destination peripheral
+ if (config->dstConn() > 15) {
+ LPC_SC->DMAREQSEL |= (1 << (config->dstConn() - 16));
+ }
+ else {
+ LPC_SC->DMAREQSEL &= ~(1 << (config->dstConn() - 8));
+ }
+
+ // Enable DMA channels, little endian
+ LPC_GPDMA->DMACConfig = _E;
+ while (!(LPC_GPDMA->DMACConfig & _E));
+
+ // Calculate absolute value for Connection number
+ uint32_t tmp1 = config->srcConn(); tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
+ uint32_t tmp2 = config->dstConn(); tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
+
+ if (config->dmacSync()) {
+ uint32_t tmp3 = config->dmacSync(); tmp3 = ((tmp3 > 15) ? (tmp3 - 8) : tmp3);
+ LPC_GPDMA->DMACSync |= Sync_Src( tmp3 );
+ }
+
+ uint32_t tfer_type = (uint32_t)config->transferType();
+ if (tfer_type == g2m || tfer_type == m2g) {
+ tfer_type -= 2; // Adjust psuedo transferType to a real transferType.
+ }
+
+ // Configure DMA Channel, enable Error Counter and Terminate counter
+ pChannel->DMACCConfig
+ = CxConfig_IE()
+ | CxConfig_ITC()
+ | CxConfig_TransferType(tfer_type)
+ | CxConfig_SrcPeripheral(tmp1)
+ | CxConfig_DestPeripheral(tmp2);
+
+ return pChannel->DMACCControl;
+}
+
+}; // namespace AjK ends
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/example1.h Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,89 @@
+#include "mbed.h"
+#include "MODDMA.h"
+#include "MODSERIAL.h"
+
+DigitalOut led1(LED1);
+DigitalOut led2(LED2);
+DigitalOut led3(LED3);
+DigitalOut led4(LED4);
+MODDMA dma;
+MODSERIAL pc(USBTX, USBRX);
+
+// Function prototypes for IRQ callbacks.
+// See definitions following main() below.
+void dmaTCCallback(void);
+void dmaERRCallback(void);
+void TC0_callback(void);
+void ERR0_callback(void);
+
+int main() {
+ char s[] = "**DMA** ABCDEFGHIJKLMNOPQRSTUVWXYZ **DMA**";
+
+ pc.baud(PC_BAUD);
+
+ dma.attach_tc( &dmaTCCallback );
+ dma.attach_err( &dmaERRCallback );
+
+ MODDMA_Config *config = new MODDMA_Config;
+ config
+ ->channelNum ( MODDMA::Channel_0 )
+ ->srcMemAddr ( (uint32_t) &s )
+ ->dstMemAddr ( 0 )
+ ->transferSize ( sizeof(s) )
+ ->transferType ( MODDMA::m2p )
+ ->transferWidth ( 0 )
+ ->srcConn ( 0 )
+ ->dstConn ( MODDMA::UART0_Tx )
+ ->dmaLLI ( 0 )
+ ->attach_tc ( &TC0_callback )
+ ->attach_err ( &ERR0_callback )
+ ; // config end
+
+ // Setup the configuration.
+ dma.Setup(config);
+
+ //dma.Enable( MODDMA::Channel_0 );
+ //dma.Enable( config->channelNum() );
+ dma.Enable( config );
+
+ while (1) {
+ led1 = !led1;
+ wait(0.25);
+ }
+}
+
+// Main controller TC IRQ callback
+void dmaTCCallback(void) {
+ led2 = 1;
+}
+
+// Main controller ERR IRQ callback
+void dmaERRCallback(void) {
+ error("Oh no! My Mbed exploded! :( Only kidding, find the problem");
+}
+
+// Configuration callback on TC
+void TC0_callback(void) {
+ MODDMA_Config *config = dma.getConfig();
+ dma.haltAndWaitChannelComplete( (MODDMA::CHANNELS)config->channelNum());
+ dma.Disable( (MODDMA::CHANNELS)config->channelNum() );
+
+ // Configurations have two IRQ callbacks for TC and Err so you
+ // know which you are processing. However, if you want to use
+ // a single callback function you can tell what type of IRQ
+ // is being processed thus:-
+ if (dma.irqType() == MODDMA::TcIrq) {
+ led3 = 1;
+ dma.clearTcIrq();
+ }
+ if (dma.irqType() == MODDMA::ErrIrq) {
+ led4 = 1;
+ dma.clearErrIrq();
+ }
+}
+
+// Configuration cakllback on Error
+void ERR0_callback(void) {
+ error("Oh no! My Mbed exploded! :( Only kidding, find the problem");
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/example2.h Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,137 @@
+/*
+ * This example was provided to support Mbed forum thread:-
+ * http://mbed.org/forum/mbed/topic/1798
+ */
+
+#include "mbed.h"
+#include "MODDMA.h"
+
+#define SAMPLE_BUFFER_LENGTH 32
+
+DigitalOut led1(LED1);
+DigitalOut led2(LED2);
+
+MODDMA dma;
+Serial pc(USBTX, USBRX);
+
+// ISR set's this when transfer complete.
+bool dmaTransferComplete = false;
+
+// Function prototypes for IRQ callbacks.
+// See definitions following main() below.
+void TC0_callback(void);
+void ERR0_callback(void);
+
+int main() {
+
+ // Create a buffer to hold the ADC samples and clear it.
+ // Note, we are going to sample two ADC inputs so they
+ // end up in this buffer "interleaved". So you will want
+ // a buffer twice this size to a real life given sample
+ // frequency. See the printf() output for details.
+ uint32_t adcInputBuffer[SAMPLE_BUFFER_LENGTH];
+ memset(adcInputBuffer, 0, sizeof(adcInputBuffer));
+
+ // We use the ADC irq to trigger DMA and the manual says
+ // that in this case the NVIC for ADC must be disabled.
+ NVIC_DisableIRQ(ADC_IRQn);
+
+ // Power up the ADC and set PCLK
+ LPC_SC->PCONP |= (1UL << 12);
+ LPC_SC->PCLKSEL0 &= ~(3UL << 24); // PCLK = CCLK/4 96M/4 = 24MHz
+
+ // Enable the ADC, 12MHz, ADC0.0 & .1
+ LPC_ADC->ADCR = (1UL << 21) | (1UL << 8) | (3UL << 0);
+
+ // Set the pin functions to ADC
+ LPC_PINCON->PINSEL1 &= ~(3UL << 14); /* P0.23, Mbed p15. */
+ LPC_PINCON->PINSEL1 |= (1UL << 14);
+ LPC_PINCON->PINSEL1 &= ~(3UL << 16); /* P0.24, Mbed p16. */
+ LPC_PINCON->PINSEL1 |= (1UL << 16);
+
+ // Setup the serial port to print out results.
+ pc.baud(115200);
+ pc.printf("ADC with DMA example\n");
+ pc.printf("====================\n");
+
+ // Prepare an ADC configuration.
+ MODDMA_Config *conf = new MODDMA_Config;
+ conf
+ ->channelNum ( MODDMA::Channel_0 )
+ ->srcMemAddr ( 0 )
+ ->dstMemAddr ( (uint32_t)adcInputBuffer )
+ ->transferSize ( SAMPLE_BUFFER_LENGTH )
+ ->transferType ( MODDMA::p2m )
+ ->transferWidth ( MODDMA::word )
+ ->srcConn ( MODDMA::ADC )
+ ->dstConn ( 0 )
+ ->dmaLLI ( 0 )
+ ->attach_tc ( &TC0_callback )
+ ->attach_err ( &ERR0_callback )
+ ; // end conf.
+
+ // Prepare configuration.
+ dma.Setup( conf );
+
+ // Enable configuration.
+ dma.Enable( conf );
+
+ // Enable ADC irq flag (to DMA).
+ // Note, don't set the individual flags,
+ // just set the global flag.
+ LPC_ADC->ADINTEN = 0x100;
+
+ // Enable burst mode on inputs 0 and 1.
+ LPC_ADC->ADCR |= (1UL << 16);
+
+ while (1) {
+ // When transfer complete do this block.
+ if (dmaTransferComplete) {
+ delete conf; // No memory leaks, delete the configuration.
+ dmaTransferComplete = false;
+ for (int i = 0; i < SAMPLE_BUFFER_LENGTH; i++) {
+ int channel = (adcInputBuffer[i] >> 24) & 0x7;
+ int iVal = (adcInputBuffer[i] >> 4) & 0xFFF;
+ double fVal = 3.3 * (double)((double)iVal) / ((double)0x1000); // scale to 0v to 3.3v
+ pc.printf("Array index %02d : ADC input channel %d = 0x%03x %01.3f volts\n", i, channel, iVal, fVal);
+ }
+ }
+
+ // Just flash LED1 for something to do.
+ led1 = !led1;
+ wait(0.25);
+ }
+}
+
+// Configuration callback on TC
+void TC0_callback(void) {
+
+ MODDMA_Config *config = dma.getConfig();
+
+ // Disbale burst mode and switch off the IRQ flag.
+ LPC_ADC->ADCR &= ~(1UL << 16);
+ LPC_ADC->ADINTEN = 0;
+
+ // Finish the DMA cycle by shutting down the channel.
+ dma.haltAndWaitChannelComplete( (MODDMA::CHANNELS)config->channelNum());
+ dma.Disable( (MODDMA::CHANNELS)config->channelNum() );
+
+ // Tell main() while(1) loop to print the results.
+ dmaTransferComplete = true;
+
+ // Switch on LED2 to show transfer complete.
+ led2 = 1;
+
+ // Clear DMA IRQ flags.
+ if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq();
+ if (dma.irqType() == MODDMA::ErrIrq) dma.clearErrIrq();
+}
+
+// Configuration callback on Error
+void ERR0_callback(void) {
+ // Switch off burst conversions.
+ LPC_ADC->ADCR |= ~(1UL << 16);
+ LPC_ADC->ADINTEN = 0;
+ error("Oh no! My Mbed EXPLODED! :( Only kidding, go find the problem");
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/example3.h Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,131 @@
+/*
+ * Demonstrates capturing the GPIO P0.4 to P0.7 "nibble" to memory
+ * using GPDMA. The transfers from port pins to memory buffer are
+ * triggered using Timer1 MAT1.0 match compare.
+ *
+ * In this example all inputs have pullups. So with nothing connected
+ * the P0.4/7 reads as 0xF. Connecting a wire from one or more of the four
+ * inputs to ground will show up in the captured buffer sequence.
+ */
+
+#include "mbed.h"
+#include "MODDMA.h"
+#include "iomacros.h" // within MODDMA library.
+
+// How long between grabbing GPIO FIO0PIN register.
+// Value is in microseconds. (500000 is half a second).
+#define SAMPLE_PERIOD 500000
+
+#define NUM_OF_SAMPLES 5
+
+Serial pc(USBTX, USBRX);
+
+DigitalOut led1(LED1);
+DigitalOut led2(LED2);
+DigitalOut led3(LED3);
+
+uint32_t buffer[NUM_OF_SAMPLES];
+
+bool dmaTransferComplete;
+
+MODDMA dma;
+MODDMA_Config *conf;
+
+void TC0_callback(void);
+void ERR0_callback(void);
+
+int main() {
+ volatile int life_counter = 0;
+
+ // Macros defined in iomacros.h, saves messing with DigitalIn
+ p30_AS_INPUT; p30_MODE( PIN_PULLUP ); // P0.4
+ p29_AS_INPUT; p29_MODE( PIN_PULLUP ); // P0.5
+ p8_AS_INPUT; p8_MODE( PIN_PULLUP ); // P0.6
+ p7_AS_INPUT; p7_MODE( PIN_PULLUP ); // P0.7
+
+ // Clear the buffer.
+ memset(buffer, 0, sizeof(buffer));
+
+ // Setup the serial port to print out results.
+ pc.baud(115200);
+ pc.printf("Starting up...\n");
+
+ // Set-up timer1 as a periodic timer.
+ LPC_SC->PCONP |= (1UL << 2); // TIM1 On
+ LPC_SC->PCLKSEL0 |= (3UL << 4); // CCLK/8 = 12MHz
+ LPC_TIM1->PR = 11; // TC clocks at 1MHz.
+ LPC_TIM1->MCR = 2; // Reset TCR to zero on match.
+ LPC_TIM1->MR0 = SAMPLE_PERIOD;
+
+ // Prepare the GPDMA system.
+ conf = new MODDMA_Config;
+ conf
+ ->channelNum ( MODDMA::Channel_0 )
+ ->srcMemAddr ( (uint32_t)&LPC_GPIO0->FIOPIN )
+ ->dstMemAddr ( (uint32_t)&buffer[0] )
+ ->transferSize ( NUM_OF_SAMPLES )
+ ->transferType ( MODDMA::g2m ) // pseudo transfer code MODDMA understands.
+ ->transferWidth ( MODDMA::word )
+ ->srcConn ( MODDMA::MAT1_0 )
+ ->dmacSync ( MODDMA::MAT1_0 )
+ ->attach_tc ( TC0_callback )
+ ->attach_err ( ERR0_callback )
+ ; // end conf.
+
+ // Prepare configuration.
+ if (!dma.Setup( conf )) {
+ error("Doh!");
+ }
+
+ // Enable GPDMA to be ready for the TIM1 "ticks".
+ dma.Enable( conf );
+
+ // Begin.
+ LPC_TIM1->TCR = 1;
+
+ while (1) {
+ if (life_counter++ > 1000000) {
+ led1 = !led1; // Show some sort of life.
+ life_counter = 0;
+ }
+
+ if (dmaTransferComplete) {
+ dmaTransferComplete = false;
+ for (int i = 0; i < NUM_OF_SAMPLES; i++) {
+ int val = (buffer[i] >> 4) & 0xF;
+ pc.printf("Buffer index %d = 0x%x\n", i, val);
+ }
+ pc.printf("Done.\n");
+
+ // Schedule another grab.
+ if (dma.Setup( conf )) {
+ dma.Enable( conf );
+ }
+ }
+ }
+}
+
+// Configuration callback on TC
+void TC0_callback(void) {
+
+ // Just show sample sequence grab complete.
+ led3 = !led3;
+
+ // Get configuration pointer.
+ MODDMA_Config *config = dma.getConfig();
+
+ // Finish the DMA cycle by shutting down the channel.
+ dma.Disable( (MODDMA::CHANNELS)config->channelNum() );
+
+ // Tell main() while(1) loop to print the results.
+ dmaTransferComplete = true;
+
+ // Clear DMA IRQ flags.
+ if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq();
+ if (dma.irqType() == MODDMA::ErrIrq) dma.clearErrIrq();
+}
+
+// Configuration callback on Error
+void ERR0_callback(void) {
+ error("Oh no! My Mbed EXPLODED! :( Only kidding, go find the problem");
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MODDMA/example4.h Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,156 @@
+/*
+ * Demonstrates sending a buffer repeatedly to the DAC using DMA.
+ * Connect an oscilloscope to Mbed pin 18. This example doesn't
+ * output anything else (nothing on any serial ports).
+ */
+#include "mbed.h"
+#include "MODDMA.h"
+
+// Make the buffer size match the number of degrees
+// in a circle since we are going to output a sinewave.
+#define BUFFER_SIZE 360
+
+// Set DAC output power mode.
+#define DAC_POWER_MODE (1 << 16)
+
+DigitalOut led1(LED1);
+DigitalOut led3(LED3);
+DigitalOut led4(LED4);
+
+int buffer[2][BUFFER_SIZE];
+
+AnalogOut signal(p18);
+
+MODDMA dma;
+MODDMA_Config *conf0, *conf1;
+
+void TC0_callback(void);
+void ERR0_callback(void);
+
+void TC1_callback(void);
+void ERR1_callback(void);
+
+int main() {
+ volatile int life_counter = 0;
+
+ // Create a sinewave buffer for testing.
+ for (int i = 0; i <= 90; i++) buffer[0][i] = (512 * sin(3.14159/180.0 * i)) + 512;
+ for (int i = 91; i <= 180; i++) buffer[0][i] = buffer[0][180 - i];
+ for (int i = 181; i <= 270; i++) buffer[0][i] = 512 - (buffer[0][i - 180] - 512);
+ for (int i = 271; i < 360; i++) buffer[0][i] = 512 - (buffer[0][360 - i] - 512);
+
+ // Adjust the sinewave buffer for use with DAC hardware.
+ for (int i = 0; i < 360; i++) {
+ buffer[0][i] = DAC_POWER_MODE | ((buffer[0][i] << 6) & 0xFFC0);
+ buffer[1][i] = buffer[0][i]; // Just create a copy of buffer0 to continue sinewave.
+ }
+
+ // Prepare the GPDMA system for buffer0.
+ conf0 = new MODDMA_Config;
+ conf0
+ ->channelNum ( MODDMA::Channel_0 )
+ ->srcMemAddr ( (uint32_t) &buffer[0] )
+ ->dstMemAddr ( MODDMA::DAC )
+ ->transferSize ( 360 )
+ ->transferType ( MODDMA::m2p )
+ ->dstConn ( MODDMA::DAC )
+ ->attach_tc ( &TC0_callback )
+ ->attach_err ( &ERR0_callback )
+ ; // config end
+
+
+ // Prepare the GPDMA system for buffer1.
+ conf1 = new MODDMA_Config;
+ conf1
+ ->channelNum ( MODDMA::Channel_1 )
+ ->srcMemAddr ( (uint32_t) &buffer[1] )
+ ->dstMemAddr ( MODDMA::DAC )
+ ->transferSize ( 360 )
+ ->transferType ( MODDMA::m2p )
+ ->dstConn ( MODDMA::DAC )
+ ->attach_tc ( &TC1_callback )
+ ->attach_err ( &ERR1_callback )
+ ; // config end
+
+
+ // Calculating the transfer frequency:
+ // By default, the Mbed library sets the PCLK_DAC clock value
+ // to 24MHz. One complete sinewave cycle in each buffer is 360
+ // points long. So, for a 1Hz wave we would need to transfer 360
+ // values per second. That would be 24000000/360 which is approx
+ // 66,666. But that's no good! The count val is only 16bits in size
+ // so bare this in mind. If you need to go slower you will need to
+ // alter PCLK_DAC from CCLK/4 to CCLK/8.
+ // For our demo we are going to have the sinewave run at 1kHz.
+ // That's 24000000/360000 which is approx 66. Experimentation
+ // however showed 65 to get closer to 1kHz (on my Mbed and scope
+ // at least).
+ LPC_DAC->DACCNTVAL = 65; // 6500 for 10Hz
+
+ // Prepare first configuration.
+ if (!dma.Prepare( conf0 )) {
+ error("Doh!");
+ }
+
+ // Begin (enable DMA and counter). Note, don't enable
+ // DBLBUF_ENA as we are using DMA double buffering.
+ LPC_DAC->DACCTRL |= (3UL << 2);
+
+ while (1) {
+ // There's not a lot to do as DMA and interrupts are
+ // now handling the buffer transfers. So we'll just
+ // flash led1 to show the Mbed is alive and kicking.
+ if (life_counter++ > 1000000) {
+ led1 = !led1; // Show some sort of life.
+ life_counter = 0;
+ }
+ }
+}
+
+// Configuration callback on TC
+void TC0_callback(void) {
+
+ // Just show sending buffer0 complete.
+ led3 = !led3;
+
+ // Get configuration pointer.
+ MODDMA_Config *config = dma.getConfig();
+
+ // Finish the DMA cycle by shutting down the channel.
+ dma.Disable( (MODDMA::CHANNELS)config->channelNum() );
+
+ // Swap to buffer1
+ dma.Prepare( conf1 );
+
+ // Clear DMA IRQ flags.
+ if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq();
+}
+
+// Configuration callback on Error
+void ERR0_callback(void) {
+ error("Oh no! My Mbed EXPLODED! :( Only kidding, go find the problem");
+}
+
+// Configuration callback on TC
+void TC1_callback(void) {
+
+ // Just show sending buffer1 complete.
+ led4 = !led4;
+
+ // Get configuration pointer.
+ MODDMA_Config *config = dma.getConfig();
+
+ // Finish the DMA cycle by shutting down the channel.
+ dma.Disable( (MODDMA::CHANNELS)config->channelNum() );
+
+ // Swap to buffer0
+ dma.Prepare( conf0 );
+
+ // Clear DMA IRQ flags.
+ if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq();
+}
+
+// Configuration callback on Error
+void ERR1_callback(void) {
+ error("Oh no! My Mbed EXPLODED! :( Only kidding, go find the problem");
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/MODDMA/iomacros.h Tue May 29 02:41:54 2018 +0000 @@ -0,0 +1,418 @@ +/* + Copyright (c) 2011 Andy Kirkham + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. +*/ + +#ifndef IOMACROS_H +#define IOMACROS_H + +#ifndef __LPC17xx_H__ +#include "LPC17xx.h" +#endif + +#define PIN_PULLUP 0UL +#define PIN_REPEAT 1UL +#define PIN_NONE 2UL +#define PIN_PULLDOWN 3UL + +/* p5 is P0.9 */ +#define p5_SEL_MASK ~(3UL << 18) +#define p5_SET_MASK (1UL << 9) +#define p5_CLR_MASK ~(p5_SET_MASK) +#define p5_AS_OUTPUT LPC_PINCON->PINSEL0&=p5_SEL_MASK;LPC_GPIO0->FIODIR|=p5_SET_MASK +#define p5_AS_INPUT LPC_GPIO0->FIOMASK &= p5_CLR_MASK; +#define p5_SET LPC_GPIO0->FIOSET = p5_SET_MASK +#define p5_CLR LPC_GPIO0->FIOCLR = p5_SET_MASK +#define p5_IS_SET (bool)(LPC_GPIO0->FIOPIN & p5_SET_MASK) +#define p5_IS_CLR !(p5_IS_SET) +#define p5_MODE(x) LPC_PINCON->PINMODE0&=p5_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<18) + +/* p6 is P0.8 */ +#define p6_SEL_MASK ~(3UL << 16) +#define p6_SET_MASK (1UL << 8) +#define p6_CLR_MASK ~(p6_SET_MASK) +#define p6_AS_OUTPUT LPC_PINCON->PINSEL0&=p6_SEL_MASK;LPC_GPIO0->FIODIR|=p6-SET_MASK +#define p6_AS_INPUT LPC_GPIO0->FIOMASK &= p6_CLR_MASK; +#define p6_SET LPC_GPIO0->FIOSET = p6_SET_MASK +#define p6_CLR LPC_GPIO0->FIOCLR = p6_SET_MASK +#define p6_IS_SET (bool)(LPC_GPIO0->FIOPIN & p6_SET_MASK) +#define p6_IS_CLR !(p6_IS_SET) +#define p6_MODE(x) LPC_PINCON->PINMODE0&=p6_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<16) + +/* p7 is P0.7 */ +#define p7_SEL_MASK ~(3UL << 14) +#define p7_SET_MASK (1UL << 7) +#define p7_CLR_MASK ~(p7_SET_MASK) +#define p7_AS_OUTPUT LPC_PINCON->PINSEL0&=p7_SEL_MASK;LPC_GPIO0->FIODIR|=p7_SET_MASK +#define p7_AS_INPUT LPC_GPIO0->FIOMASK &= p7_CLR_MASK; +#define p7_SET LPC_GPIO0->FIOSET = p7_SET_MASK +#define p7_CLR LPC_GPIO0->FIOCLR = p7_SET_MASK +#define p7_IS_SET (bool)(LPC_GPIO0->FIOPIN & p7_SET_MASK) +#define p7_IS_CLR !(p7_IS_SET) +#define p7_MODE(x) LPC_PINCON->PINMODE0&=p7_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<14) + +/* p8 is P0.6 */ +#define p8_SEL_MASK ~(3UL << 12) +#define p8_SET_MASK (1UL << 6) +#define p8_CLR_MASK ~(p8_SET_MASK) +#define p8_AS_OUTPUT LPC_PINCON->PINSEL0&=p8_SEL_MASK;LPC_GPIO0->FIODIR|=p8_SET_MASK +#define p8_AS_INPUT LPC_GPIO0->FIOMASK &= p8_CLR_MASK; +#define p8_SET LPC_GPIO0->FIOSET = p8_SET_MASK +#define p8_CLR LPC_GPIO0->FIOCLR = p8_SET_MASK +#define p8_IS_SET (bool)(LPC_GPIO0->FIOPIN & p8_SET_MASK) +#define p8_IS_CLR !(p8_IS_SET) +#define p8_MODE(x) LPC_PINCON->PINMODE0&=p8_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<12) + +/* p9 is P0.0 */ +#define p9_SEL_MASK ~(3UL << 0) +#define p9_SET_MASK (1UL << 0) +#define p9_CLR_MASK ~(p9_SET_MASK) +#define p9_AS_OUTPUT LPC_PINCON->PINSEL0&=p9_SEL_MASK;LPC_GPIO0->FIODIR|=p9_SET_MASK +#define p9_AS_INPUT LPC_GPIO0->FIOMASK &= p9_CLR_MASK; +#define p9_SET LPC_GPIO0->FIOSET = p9_SET_MASK +#define p9_CLR LPC_GPIO0->FIOCLR = p9_SET_MASK +#define p9_IS_SET (bool)(LPC_GPIO0->FIOPIN & p9_SET_MASK) +#define p9_IS_CLR !(p9_IS_SET) +#define p9_MODE(x) LPC_PINCON->PINMODE0&=p9_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<0) + +/* p10 is P0.1 */ +#define p10_SEL_MASK ~(3UL << 2) +#define p10_SET_MASK (1UL << 1) +#define p10_CLR_MASK ~(p10_SET_MASK) +#define p10_AS_OUTPUT LPC_PINCON->PINSEL0&=p10_SEL_MASK;LPC_GPIO0->FIODIR|=p10_SET_MASK +#define p10_AS_INPUT LPC_GPIO0->FIOMASK &= p10_CLR_MASK; +#define p10_SET LPC_GPIO0->FIOSET = p10_SET_MASK +#define p10_CLR LPC_GPIO0->FIOCLR = p10_SET_MASK +#define p10_IS_SET (bool)(LPC_GPIO0->FIOPIN & p10_SET_MASK) +#define p10_IS_CLR !(p10_IS_SET) +#define p10_MODE(x) LPC_PINCON->PINMODE0&=p10_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<2) + +/* p11 is P0.18 */ +#define p11_SEL_MASK ~(3UL << 4) +#define p11_SET_MASK (1UL << 18) +#define p11_CLR_MASK ~(p11_SET_MASK) +#define p11_AS_OUTPUT LPC_PINCON->PINSEL1&=p11_SEL_MASK;LPC_GPIO0->FIODIR|=p11_SET_MASK +#define p11_AS_INPUT LPC_GPIO0->FIOMASK &= p11_CLR_MASK; +#define p11_SET LPC_GPIO0->FIOSET = p11_SET_MASK +#define p11_CLR LPC_GPIO0->FIOCLR = p11_SET_MASK +#define p11_IS_SET (bool)(LPC_GPIO0->FIOPIN & p11_SET_MASK) +#define p11_IS_CLR !(p11_IS_SET) +#define p11_MODE(x) LPC_PINCON->PINMODE1&=p11_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<4) + +/* p12 is P0.17 */ +#define p12_SEL_MASK ~(3UL << 2) +#define p12_SET_MASK (1UL << 17) +#define p12_CLR_MASK ~(p12_SET_MASK) +#define p12_AS_OUTPUT LPC_PINCON->PINSEL1&=p12_SEL_MASK;LPC_GPIO0->FIODIR|=p12_SET_MASK +#define p12_AS_INPUT LPC_GPIO0->FIOMASK &= p12_CLR_MASK; +#define p12_SET LPC_GPIO0->FIOSET = p12_SET_MASK +#define p12_CLR LPC_GPIO0->FIOCLR = p12_SET_MASK +#define p12_IS_SET (bool)(LPC_GPIO0->FIOPIN & p12_SET_MASK) +#define p12_IS_CLR !(p12_IS_SET) +#define p12_MODE(x) LPC_PINCON->PINMODE1&=p12_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<2) + +/* p13 is P0.15 */ +#define p13_SEL_MASK ~(3UL << 30) +#define p13_SET_MASK (1UL << 15) +#define p13_CLR_MASK ~(p13_SET_MASK) +#define p13_AS_OUTPUT LPC_PINCON->PINSEL0&=p13_SEL_MASK;LPC_GPIO0->FIODIR|=p13_SET_MASK +#define p13_AS_INPUT LPC_GPIO0->FIOMASK &= p13_CLR_MASK; +#define p13_SET LPC_GPIO0->FIOSET = p13_SET_MASK +#define p13_CLR LPC_GPIO0->FIOCLR = p13_SET_MASK +#define p13_IS_SET (bool)(LPC_GPIO0->FIOPIN & p13_SET_MASK) +#define p13_IS_CLR !(p13_IS_SET) +#define p13_MODE(x) LPC_PINCON->PINMODE0&=p13_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<30) + +/* p14 is P0.16 */ +#define p14_SEL_MASK ~(3UL << 0) +#define p14_SET_MASK (1UL << 16) +#define p14_CLR_MASK ~(p14_SET_MASK) +#define p14_AS_OUTPUT LPC_PINCON->PINSEL1&=p14_SEL_MASK;LPC_GPIO0->FIODIR|=p14_SET_MASK +#define p14_AS_INPUT LPC_GPIO0->FIOMASK &= p14_CLR_MASK; +#define p14_SET LPC_GPIO0->FIOSET = p14_SET_MASK +#define p14_CLR LPC_GPIO0->FIOCLR = p14_SET_MASK +#define p14_IS_SET (bool)(LPC_GPIO0->FIOPIN & p14_SET_MASK) +#define p14_IS_CLR !(p14_IS_SET) +#define p14_MODE(x) LPC_PINCON->PINMODE1&=p14_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<0) + +/* p15 is P0.23 */ +#define p15_SEL_MASK ~(3UL << 14) +#define p15_SET_MASK (1UL << 23) +#define p15_CLR_MASK ~(p15_SET_MASK) +#define p15_AS_OUTPUT LPC_PINCON->PINSEL1&=p15_SEL_MASK;LPC_GPIO0->FIODIR|=p15_SET_MASK +#define p15_AS_INPUT LPC_GPIO0->FIOMASK &= p15_CLR_MASK; +#define p15_SET LPC_GPIO0->FIOSET = p15_SET_MASK +#define p15_CLR LPC_GPIO0->FIOCLR = p15_SET_MASK +#define p15_IS_SET (bool)(LPC_GPIO0->FIOPIN & p15_SET_MASK) +#define p15_IS_CLR !(p15_IS_SET) +#define p15_MODE(x) LPC_PINCON->PINMODE1&=p15_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<14) + +/* p16 is P0.24 */ +#define p16_SEL_MASK ~(3UL << 16) +#define p16_SET_MASK (1UL << 24) +#define p16_CLR_MASK ~(p16_SET_MASK) +#define p16_AS_OUTPUT LPC_PINCON->PINSEL1&=p16_SEL_MASK;LPC_GPIO0->FIODIR|=p16_SET_MASK +#define p16_AS_INPUT LPC_GPIO0->FIOMASK &= p16_CLR_MASK; +#define p16_SET LPC_GPIO0->FIOSET = p16_SET_MASK +#define p16_CLR LPC_GPIO0->FIOCLR = p16_SET_MASK +#define p16_IS_SET (bool)(LPC_GPIO0->FIOPIN & p16_SET_MASK) +#define p16_IS_CLR !(p16_IS_SET) +#define p16_MODE(x) LPC_PINCON->PINMODE1&=p16_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<16) + +/* p17 is P0.25 */ +#define p17_SEL_MASK ~(3UL << 18) +#define p17_SET_MASK (1UL << 25) +#define p17_CLR_MASK ~(p17_SET_MASK) +#define p17_AS_OUTPUT LPC_PINCON->PINSEL1&=p17_SEL_MASK;LPC_GPIO0->FIODIR|=p17_SET_MASK +#define p17_AS_INPUT LPC_GPIO0->FIOMASK &= p17_CLR_MASK; +#define p17_SET LPC_GPIO0->FIOSET = p17_SET_MASK +#define p17_CLR LPC_GPIO0->FIOCLR = p17_SET_MASK +#define p17_IS_SET (bool)(LPC_GPIO0->FIOPIN & p17_SET_MASK) +#define p17_IS_CLR !(p17_IS_SET) +#define p17_MODE(x) LPC_PINCON->PINMODE1&=p17_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<18) + +/* p18 is P0.26 */ +#define p18_SEL_MASK ~(3UL << 20) +#define p18_SET_MASK (1UL << 26) +#define p18_CLR_MASK ~(p18_SET_MASK) +#define p18_AS_OUTPUT LPC_PINCON->PINSEL1&=p18_SEL_MASK;LPC_GPIO0->FIODIR|=p18_SET_MASK +#define p18_AS_INPUT LPC_GPIO0->FIOMASK &= p18_CLR_MASK; +#define p18_SET LPC_GPIO0->FIOSET = p18_SET_MASK +#define p18_CLR LPC_GPIO0->FIOCLR = p18_SET_MASK +#define p18_IS_SET (bool)(LPC_GPIO0->FIOPIN & p18_SET_MASK) +#define p18_IS_CLR !(p18_IS_SET) +#define p18_MODE(x) LPC_PINCON->PINMODE1&=p18_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<20) + +/* p19 is P1.30 */ +#define p19_SEL_MASK ~(3UL << 28) +#define p19_SET_MASK (1UL << 30) +#define p19_AS_OUTPUT LPC_PINCON->PINSEL3&=p19_SEL_MASK;LPC_GPIO1->FIODIR|=p19_SET_MASK +#define p19_AS_INPUT LPC_GPIO1->FIOMASK &= p19_CLR_MASK; +#define p19_SET LPC_GPIO1->FIOSET = p19_SET_MASK +#define p19_CLR LPC_GPIO1->FIOCLR = p19_SET_MASK +#define p19_IS_SET (bool)(LPC_GPIO1->FIOPIN & p19_SET_MASK) +#define p19_IS_CLR !(p19_IS_SET) +#define p19_MODE(x) LPC_PINCON->PINMODE3&=p19_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<28) + +/* p20 is P1.31 */ +#define p20_SEL_MASK ~(3UL << 30) +#define p20_SET_MASK (1UL << 31) +#define p20_CLR_MASK ~(p20_SET_MASK) +#define p20_AS_OUTPUT LPC_PINCON->PINSEL3&=p20_SEL_MASK;LPC_GPIO1->FIODIR|=p20_SET_MASK +#define p20_AS_INPUT LPC_GPIO1->FIOMASK &= p20_CLR_MASK; +#define p20_SET LPC_GPIO1->FIOSET = p20_SET_MASK +#define p20_CLR LPC_GPIO1->FIOCLR = p20_SET_MASK +#define p20_IS_SET (bool)(LPC_GPIO1->FIOPIN & p20_SET_MASK) +#define p20_IS_CLR !(p20_IS_SET) +#define p20_MODE(x) LPC_PINCON->PINMODE3&=p20_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<30) + +/* p21 is P2.5 */ +#define p21_SEL_MASK ~(3UL << 10) +#define p21_SET_MASK (1UL << 5) +#define p21_CLR_MASK ~(p21_SET_MASK) +#define p21_AS_OUTPUT LPC_PINCON->PINSEL4&=p21_SEL_MASK;LPC_GPIO2->FIODIR|=p21_SET_MASK +#define p21_AS_INPUT LPC_GPIO2->FIOMASK &= p21_CLR_MASK; +#define p21_SET LPC_GPIO2->FIOSET = p21_SET_MASK +#define p21_CLR LPC_GPIO2->FIOCLR = p21_SET_MASK +#define p21_IS_SET (bool)(LPC_GPIO2->FIOPIN & p21_SET_MASK) +#define p21_IS_CLR !(p21_IS_SET) +#define p21_TOGGLE p21_IS_SET?p21_CLR:p21_SET +#define p21_MODE(x) LPC_PINCON->PINMODE4&=p21_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<10) + +/* p22 is P2.4 */ +#define p22_SEL_MASK ~(3UL << 8) +#define p22_SET_MASK (1UL << 4) +#define p22_CLR_MASK ~(p22_SET_MASK) +#define p22_AS_OUTPUT LPC_PINCON->PINSEL4&=p22_SEL_MASK;LPC_GPIO2->FIODIR|=p22_SET_MASK +#define p22_AS_INPUT LPC_GPIO2->FIOMASK &= p22_CLR_MASK; +#define p22_SET LPC_GPIO2->FIOSET = p22_SET_MASK +#define p22_CLR LPC_GPIO2->FIOCLR = p22_SET_MASK +#define p22_IS_SET (bool)(LPC_GPIO2->FIOPIN & p22_SET_MASK) +#define p22_IS_CLR !(p22_IS_SET) +#define p22_TOGGLE p22_IS_SET?p22_CLR:p22_SET +#define p22_MODE(x) LPC_PINCON->PINMODE4&=p22_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<8) + +/* p23 is P2.3 */ +#define p23_SEL_MASK ~(3UL << 6) +#define p23_SET_MASK (1UL << 3) +#define p23_CLR_MASK ~(p23_SET_MASK) +#define p23_AS_OUTPUT LPC_PINCON->PINSEL4&=p23_SEL_MASK;LPC_GPIO2->FIODIR|=p23_SET_MASK +#define p23_AS_INPUT LPC_GPIO2->FIOMASK &= p23_CLR_MASK; +#define p23_SET LPC_GPIO2->FIOSET = p23_SET_MASK +#define p23_CLR LPC_GPIO2->FIOCLR = p23_SET_MASK +#define p23_IS_SET (bool)(LPC_GPIO2->FIOPIN & p23_SET_MASK) +#define p23_IS_CLR !(p23_IS_SET) +#define p23_TOGGLE p23_IS_SET?p23_CLR:p23_SET +#define p23_MODE(x) LPC_PINCON->PINMODE4&=p23_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<6) + +/* p24 is P2.2 */ +#define p24_SEL_MASK ~(3UL << 4) +#define p24_SET_MASK (1UL << 2) +#define p24_CLR_MASK ~(p24_SET_MASK) +#define p24_AS_OUTPUT LPC_PINCON->PINSEL4&=p24_SEL_MASK;LPC_GPIO2->FIODIR|=p24_SET_MASK +#define p24_AS_INPUT LPC_GPIO2->FIOMASK &= p24_CLR_MASK; +#define p24_SET LPC_GPIO2->FIOSET = p24_SET_MASK +#define p24_CLR LPC_GPIO2->FIOCLR = p24_SET_MASK +#define p24_IS_SET (bool)(LPC_GPIO2->FIOPIN & p24_SET_MASK) +#define p24_IS_CLR !(p24_IS_SET) +#define p24_TOGGLE p24_IS_SET?p24_CLR:p24_SET +#define p24_MODE(x) LPC_PINCON->PINMODE4&=p24_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<4) + +/* p25 is P2.1 */ +#define p25_SEL_MASK ~(3UL << 2) +#define p25_SET_MASK (1UL << 1) +#define p25_CLR_MASK ~(p25_SET_MASK) +#define p25_AS_OUTPUT LPC_PINCON->PINSEL4&=p25_SEL_MASK;LPC_GPIO2->FIODIR|=p25_SET_MASK +#define p25_AS_INPUT LPC_GPIO2->FIOMASK &= p25_CLR_MASK; +#define p25_SET LPC_GPIO2->FIOSET = p25_SET_MASK +#define p25_CLR LPC_GPIO2->FIOCLR = p25_SET_MASK +#define p25_IS_SET (bool)(LPC_GPIO2->FIOPIN & p25_SET_MASK) +#define p25_IS_CLR !(p25_IS_SET) +#define p25_MODE(x) LPC_PINCON->PINMODE4&=p25_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<2) + +/* p26 is P2.0 */ +#define p26_SEL_MASK ~(3UL << 0) +#define p26_SET_MASK (1UL << 0) +#define p26_CLR_MASK ~(p26_SET_MASK) +#define p26_AS_OUTPUT LPC_PINCON->PINSEL4&=p26_SEL_MASK;LPC_GPIO2->FIODIR|=p26_SET_MASK +#define p26_AS_INPUT LPC_GPIO2->FIOMASK &= p26_CLR_MASK; +#define p26_SET LPC_GPIO2->FIOSET = p26_SET_MASK +#define p26_CLR LPC_GPIO2->FIOCLR = p26_SET_MASK +#define p26_IS_SET (bool)(LPC_GPIO2->FIOPIN & p26_SET_MASK) +#define p26_IS_CLR !(p26_IS_SET) +#define p26_MODE(x) LPC_PINCON->PINMODE4&=p26_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<0) + +/* p27 is P0.11 */ +#define p27_SEL_MASK ~(3UL << 22) +#define p27_SET_MASK (1UL << 11) +#define p27_CLR_MASK ~(p27_SET_MASK) +#define p27_AS_OUTPUT LPC_PINCON->PINSEL0&=p27_SEL_MASK;LPC_GPIO0->FIODIR|=p27_SET_MASK +#define p27_AS_INPUT LPC_GPIO0->FIOMASK &= p27_CLR_MASK; +#define p27_SET LPC_GPIO0->FIOSET = p27_SET_MASK +#define p27_CLR LPC_GPIO0->FIOCLR = p27_SET_MASK +#define p27_IS_SET (bool)(LPC_GPIO0->FIOPIN & p27_SET_MASK) +#define p27_IS_CLR !(p27_IS_SET) +#define p27_MODE(x) LPC_PINCON->PINMODE0&=p27_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<22) + +/* p28 is P0.10 */ +#define p28_SEL_MASK ~(3UL << 20) +#define p28_SET_MASK (1UL << 10) +#define p28_CLR_MASK ~(p28_SET_MASK) +#define p28_AS_OUTPUT LPC_PINCON->PINSEL0&=p28_SEL_MASK;LPC_GPIO0->FIODIR|=p28_SET_MASK +#define p28_AS_INPUT LPC_GPIO0->FIOMASK &= p28_CLR_MASK; +#define p28_SET LPC_GPIO0->FIOSET = p28_SET_MASK +#define p28_CLR LPC_GPIO0->FIOCLR = p28_SET_MASK +#define p28_IS_SET (bool)(LPC_GPIO0->FIOPIN & p28_SET_MASK) +#define p28_IS_CLR !(p28_IS_SET) +#define p28_MODE(x) LPC_PINCON->PINMODE0&=p28_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<20) + +/* p29 is P0.5 */ +#define p29_SEL_MASK ~(3UL << 10) +#define p29_SET_MASK (1UL << 5) +#define p29_CLR_MASK ~(p29_SET_MASK) +#define p29_AS_OUTPUT LPC_PINCON->PINSEL0&=p29_SEL_MASK;LPC_GPIO0->FIODIR|=p29_SET_MASK +#define p29_AS_INPUT LPC_GPIO0->FIOMASK &= p29_CLR_MASK; +#define p29_SET LPC_GPIO0->FIOSET = p29_SET_MASK +#define p29_CLR LPC_GPIO0->FIOCLR = p29_SET_MASK +#define p29_IS_SET (bool)(LPC_GPIO0->FIOPIN & p29_SET_MASK) +#define p29_IS_CLR !(p29_IS_SET) +#define p29_TOGGLE p29_IS_SET?p29_CLR:p29_SET +#define p29_MODE(x) LPC_PINCON->PINMODE0&=p29_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<10) + +/* p30 is P0.4 */ +#define p30_SEL_MASK ~(3UL << 8) +#define p30_SET_MASK (1UL << 4) +#define p30_CLR_MASK ~(p30_SET_MASK) +#define p30_AS_OUTPUT LPC_PINCON->PINSEL0&=p30_SEL_MASK;LPC_GPIO0->FIODIR|=p30_SET_MASK +#define p30_AS_INPUT LPC_GPIO0->FIOMASK &= p30_CLR_MASK; +#define p30_SET LPC_GPIO0->FIOSET = p30_SET_MASK +#define p30_CLR LPC_GPIO0->FIOCLR = p30_SET_MASK +#define p30_IS_SET (bool)(LPC_GPIO0->FIOPIN & p30_SET_MASK) +#define p30_IS_CLR !(p30_IS_SET) +#define p30_MODE(x) LPC_PINCON->PINMODE0&=p30_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<8) + +/* The following definitions are for the four Mbed LEDs. + LED1 = P1.18 + LED2 = P1.20 + LED3 = P1.21 + LED4 = P1.23 */ + +#define P1_18_SEL_MASK ~(3UL << 4) +#define P1_18_SET_MASK (1UL << 18) +#define P1_18_CLR_MASK ~(P1_18_SET_MASK) +#define P1_18_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_18_SEL_MASK;LPC_GPIO1->FIODIR|=P1_18_SET_MASK +#define P1_18_AS_INPUT LPC_GPIO1->FIOMASK &= P1_18_CLR_MASK; +#define P1_18_SET LPC_GPIO1->FIOSET = P1_18_SET_MASK +#define P1_18_CLR LPC_GPIO1->FIOCLR = P1_18_SET_MASK +#define P1_18_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_18_SET_MASK) +#define P1_18_IS_CLR !(P1_18_IS_SET) +#define LED1_USE P1_18_AS_OUTPUT;P1_18_AS_INPUT +#define LED1_ON P1_18_SET +#define LED1_OFF P1_18_CLR +#define LED1_IS_ON P1_18_IS_SET +#define LED1_TOGGLE P1_18_IS_SET?LED1_OFF:LED1_ON + +#define P1_20_SEL_MASK ~(3UL << 8) +#define P1_20_SET_MASK (1UL << 20) +#define P1_20_CLR_MASK ~(P1_20_SET_MASK) +#define P1_20_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_20_SEL_MASK;LPC_GPIO1->FIODIR|=P1_20_SET_MASK +#define P1_20_AS_INPUT LPC_GPIO1->FIOMASK &= P1_20_CLR_MASK; +#define P1_20_SET LPC_GPIO1->FIOSET = P1_20_SET_MASK +#define P1_20_CLR LPC_GPIO1->FIOCLR = P1_20_SET_MASK +#define P1_20_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_20_SET_MASK) +#define P1_20_IS_CLR !(P1_20_IS_SET) +#define LED2_USE P1_20_AS_OUTPUT;P1_20_AS_INPUT +#define LED2_ON P1_20_SET +#define LED2_OFF P1_20_CLR +#define LED2_IS_ON P1_20_IS_SET +#define LED2_TOGGLE P1_20_IS_SET?LED2_OFF:LED2_ON + +#define P1_21_SEL_MASK ~(3UL << 10) +#define P1_21_SET_MASK (1UL << 21) +#define P1_21_CLR_MASK ~(P1_21_SET_MASK) +#define P1_21_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_21_SEL_MASK;LPC_GPIO1->FIODIR|=P1_21_SET_MASK +#define P1_21_AS_INPUT LPC_GPIO1->FIOMASK &= P1_21_CLR_MASK; +#define P1_21_SET LPC_GPIO1->FIOSET = P1_21_SET_MASK +#define P1_21_CLR LPC_GPIO1->FIOCLR = P1_21_SET_MASK +#define P1_21_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_21_SET_MASK) +#define P1_21_IS_CLR !(P1_21_IS_SET) +#define LED3_USE P1_21_AS_OUTPUT;P1_21_AS_INPUT +#define LED3_ON P1_21_SET +#define LED3_OFF P1_21_CLR +#define LED3_IS_ON P1_21_IS_SET +#define LED3_TOGGLE P1_21_IS_SET?LED3_OFF:LED3_ON + +#define P1_23_SEL_MASK ~(3UL << 14) +#define P1_23_SET_MASK (1UL << 23) +#define P1_23_CLR_MASK ~(P1_23_SET_MASK) +#define P1_23_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_23_SEL_MASK;LPC_GPIO1->FIODIR|=P1_23_SET_MASK +#define P1_23_AS_INPUT LPC_GPIO1->FIOMASK &= P1_23_CLR_MASK; +#define P1_23_SET LPC_GPIO1->FIOSET = P1_23_SET_MASK +#define P1_23_CLR LPC_GPIO1->FIOCLR = P1_23_SET_MASK +#define P1_23_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_23_SET_MASK) +#define P1_23_IS_CLR !(P1_23_IS_SET) +#define LED4_USE P1_23_AS_OUTPUT;P1_23_AS_INPUT +#define LED4_ON P1_23_SET +#define LED4_OFF P1_23_CLR +#define LED4_IS_ON P1_23_IS_SET +#define LED4_TOGGLE P1_23_IS_SET?LED4_OFF:LED4_ON + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp Tue May 29 02:41:54 2018 +0000
@@ -0,0 +1,1638 @@
+/////////////////////////////////////////////////////////////////////
+// MBED Pulse Test OutPut / Input Checkfor RIX/TRIX //
+// copy from SingleCH Dose Measure //
+/// Since 2018.05.08 H.Tsunemoto //
+// Pulse Output X-ray Off P30
+/////////////////////////////////////////////////////////////////////
+
+#include "mbed.h"
+#include "stdio.h"
+#include "math.h"
+#include "LPC17xx.h"
+// Serial TX & RX interrupt loopback test using formatted IO - sprintf and sscanf
+// Connect TX to RX (p9 to p10)
+// or can also use USB and type back in the number printed out in a terminal window
+// Sends out ASCII numbers in a loop and reads them back
+// Since 2013.08.
+// If not the same number LED4 goes on
+// LED1 and LED2 ADC
+// LED3 changing indicate main loop running
+
+//-------------------------------------//
+// --- MBED I/O Asign declaration --- //
+//-------------------------------------//
+// Serial Port Asign P9:TX P10:RX
+Serial device(USBTX, USBRX); // tx, rx //Serial device(p9, p10); // tx, rx
+// ADC Port Asign P15: ad_ch1 P16 = ad_ch2
+// 2017.02.08 H.Tsunemoto
+AnalogIn ad_ch1(p20); // AD CH1 P19 MBED ADC Input
+AnalogIn ad_ch2(p19); // AD CH2 P20 MBED ADC Input
+//AnalogIn ad_ch3(p17); //AD CH2
+AnalogOut dac_output(p18);
+//DigitalOut POut_CH1_Rng(p21); // Pout CH1 Range Select
+//DigitalOut POut_CH2_Rng(p22); // Pout CH2 Range Select
+DigitalOut POut_P30_Pulse(p30); // Pout CH2 Range Select
+DigitalOut POut_P29_Pulse(p29); // Pout CH2 Range Select
+DigitalIn PInp_P21_Port(p21); // Port I/O Status Input
+
+// Can also use USB and type back in the number printed out in a terminal window
+// Serial monitor_device(USBTX, USBRX);
+DigitalOut led1(LED1); // ADC Active
+DigitalOut led2(LED2); // ADC Input Cycle
+DigitalOut led3(LED3); // Main Loop Cycle
+DigitalOut led4(LED4); // DAC Active
+BusOut leds(LED4,LED3,LED2,LED1); //LED
+
+#define Debug_LED_Active 1
+#define Debug_LED_Disable 0
+int i_LED_Active = Debug_LED_Disable;
+//---- ADC Interrupt Timer -----//
+int main_loop_count = 0;
+Ticker ADC_Timer;
+Timer t;
+
+//-------- ADC Measure Mode Parameter declaration --------//
+typedef struct st_PulseW_param{
+ int i_sample_interval; // DAC Output Pattern
+ int i_usec_Pulse_width;
+ int i_usec_Pulse_Interval;
+ int i_usec_Pulse_RepCnt;
+ int i_msec_Pulse_width;
+ int i_msec_Pulse_Interval;
+ int i_msec_Pulse_RepCnt;
+ int i_PulseTestEnable;
+ int i_msec_Pulse_OnOffWait;
+ int i_CH2_Range;
+ }ST_PulseW_PARAM;
+
+ST_PulseW_PARAM st_p_test_mode_param;
+
+//-------- ADC Measure Mode Parameter Default Set --------//
+const ST_PulseW_PARAM const_PulseTest_Param_Default=
+{
+ 1000 //i_sample_int=1000 microS
+ ,5 // Pulse Width Default 1usec
+ ,500 // Pulse Interval Default 100usec
+ ,100 // Pulse Repeat Count
+ ,10 // i_msec_Pulse_width Default 1msec
+ ,1000 // i_msec_Pulse_width Default 100msec
+ ,100 // i_msec_Pulse_RepCnt
+ ,0 // Pulse Trase Log Enable Default Disable
+ ,50000 // i_msec_Pulse_OnOffWait Default 5000msec
+ ,0
+ };
+void adc_param_init();
+
+
+
+
+//--------------------------------//
+// --- Serial Communication --- //
+//--------------------------------//
+void Tx_interrupt();
+void Rx_interrupt();
+void send_line();
+int read_line(); // Return Rec CHAR Count 2013.08.08 Tsunemoto Append
+
+
+
+//---------- H.Tsunemoto Scince 2013.08.08 ---------//
+//-----------------------------------------------------------//
+//--------- Timer Innterrupt For DAC Control ---------------//
+//-----------------------------------------------------------//
+int timer_count=0;
+int timer_1Sec=0;
+
+bool b_PulseTestStatus = false; // Pulse Test STatus
+#define P_TESTMode_Nop 0
+#define P_TESTMode_1SHOT_OFF 1
+#define P_TESTMode_1SHOT_ON 2
+#define P_TESTMode_Ntimes_OFF 3
+#define P_TESTMode_Ntimes_ON 4
+#define P_TESTMode_Ntimes_ONOFF 5
+
+unsigned int ui_PulseTestMode = P_TESTMode_Nop; // Pulse Test Mode
+
+#define P_TESTSEQ_Nop 0 // Test Start
+#define P_TESTSEQ_START 1 // Test Start
+#define P_TESTSEQ_ON 2 // Test ON ONOFFCHeck P29 ON
+#define P_TESTSEQ_OFF 3 // Test OFF ONOFFCHeck P29 OFF
+#define P_TESTSEQ_End 4 // Test END
+#define P_TESTSEQ_ONOFF_P30_ON 5 // Test ONOFFCHeck P30 ON
+#define P_TESTSEQ_ONOFF_P30_OFF 6 // Test ONOFFCHeck P30 OFF
+
+unsigned int ui_PulseTestSequence = P_TESTSEQ_Nop; // Sequence Status
+
+unsigned int ui_Pulse_ON_Cnt = 0;
+unsigned int ui_Pulse_Interval_Cnt = 0;
+unsigned int ui_Pulse_Test_Cycle_Cnt = 0;
+unsigned int ui_TestTimeCount =0;
+unsigned int ui_PulseAfter_Count =0;
+int i_PortP21_Stat =1;
+int i_PortP21_Stat_New =0;
+int i_PortP21_Stat_Ave[3] ={0,0,0};
+
+
+unsigned int ui_Main_Serial_Delay = 0;
+#define MAIN_TEST_STAT_NOP 0
+#define MAIN_TEST_STAT_START 1
+#define MAIN_TEST_STAT_END 2
+#define MAIN_TEST_STAT_CNT 3
+unsigned int ui_Main_Test_Status = MAIN_TEST_STAT_NOP;
+char c_TEST_msg[32];
+
+
+//void TIMER0_IRQHandler(void);
+void timer0_init(void);
+//--------- New Append Function ---------//
+
+void Ser_Command_Input();
+//////////////////////////////////////////////////////////////////////////////////
+//------------ Command Check & Set Function ---------------------------------//
+//------------ usec Short Pulse Test ---------------//
+void com_Check_usecPulseA(int i_RecCharCount);
+void com_Check_usecPulseUP1(int i_RecCharCount);
+void com_Check_usecPulseUPN(int i_RecCharCount);
+void com_Check_usecPulseB(int i_RecCharCount);
+void com_Check_usecPulseUX1(int i_RecCharCount);
+void com_Check_usecPulseUXN(int i_RecCharCount);
+void com_Check_usecUPW(int i_RecCharCount);
+void com_Check_usecUPI(int i_RecCharCount);
+void com_Check_usecUPC(int i_RecCharCount);
+//------------ ｍsec Pulse Test （Normal)---------------//
+//bool com_Check_msecPulseA(int i_RecCharCount);
+void com_Check_msecPulseMP1(int i_RecCharCount);
+void com_Check_msecPulseMPN(int i_RecCharCount);
+//bool com_Check_msecPulseB(int i_RecCharCount);
+void com_Check_msecPulseMX1(int i_RecCharCount);
+void com_Check_msecPulseMXN(int i_RecCharCount);
+void com_Check_msecPulseMTN(int i_RecCharCount);
+void com_Check_msecPulseMTW(int i_RecCharCount);
+void com_Check_msecMPW(int i_RecCharCount);
+void com_Check_msecMPI(int i_RecCharCount);
+void com_Check_msecMPC(int i_RecCharCount);
+void com_Check_msecMPT(int i_RecCharCount);
+//bool com_Check_usecPRC(int i_RecCharCount);
+/// ADC No.1 "SMP 1000" ADC Sample Rate 2 - 1000 msec
+bool com_Check_SMP(int i_RecCharCount);
+/// ADC No.4 "START" ADC Sample Start
+bool com_Check_START(int i_RecCharCount);
+// ADC No.5 "STOP" ADC Sample Stop
+bool com_Check_STOP(int i_RecCharCount);
+// ADC No.6 // "STAT?"
+void com_ADC_Table_Param_Send();
+// ADC No.7 // "LED0" LED Ena
+bool com_Check_LED(int i_RecCharCount);
+//----------------------------------------------------------------//
+
+// Circular buffers for serial TX and RX data - used by interrupt routines
+const int ser_buffer_size = 255;
+// might need to increase buffer size for high baud rates
+char tx_buffer[ser_buffer_size];
+char rx_buffer[ser_buffer_size];
+// Circular buffer pointers
+// volatile makes read-modify-write atomic
+volatile int tx_in=0;
+volatile int tx_out=0;
+volatile int rx_in=0;
+volatile int rx_out=0;
+// Line buffers for sprintf and sscanf
+char tx_line[80];
+char rx_line[80];
+//--- 2013.08.08 Tsunemoto ------//
+//-- rx Data Cr Rec Counter
+volatile int rx_cr_Rec = 0;
+//
+
+/////////////////////////////////////////////////////////////////
+// <<<< Main Function >>>> //
+/////////////////////////////////////////////////////////////////
+// ---------------------------------------------------------------//
+// main test program
+int main() {
+ // Serial Speed Set
+ device.baud(115200);
+
+// Setup a serial interrupt function to receive data
+ device.attach(&Rx_interrupt, Serial::RxIrq);
+// Setup a serial interrupt function to transmit data
+ device.attach(&Tx_interrupt, Serial::TxIrq);
+ POut_P30_Pulse.write(0);
+ POut_P29_Pulse.write(0);
+
+// Formatted IO test using send and receive serial interrupts
+// Timer 0 Interrupt Initial Set //
+ timer0_init();
+ timer_count = 0;
+
+//--- ADC Measurement Control Parameter Initial Set ---//
+ adc_param_init();
+ // PInp_P21 Port Status Initial Set
+ while (i_PortP21_Stat != i_PortP21_Stat_New)
+ {
+
+ i_PortP21_Stat_Ave[0] = i_PortP21_Stat_Ave[1];
+ i_PortP21_Stat_Ave[1] = i_PortP21_Stat_Ave[2];
+ i_PortP21_Stat_Ave[2] = PInp_P21_Port.read();
+ if((i_PortP21_Stat_Ave[0] == i_PortP21_Stat_Ave[1])
+ && (i_PortP21_Stat_Ave[0] == i_PortP21_Stat_Ave[2])){
+ i_PortP21_Stat_New = i_PortP21_Stat_Ave[0];
+ i_PortP21_Stat = i_PortP21_Stat_New;
+ }
+
+ }
+//--- DAC Control Parameter Init --- //
+ // dac1_param_init();
+// -- Main Loop -- //
+ while (1) {
+ if(i_LED_Active == Debug_LED_Active){
+ led3 = (led3+1) & 1;
+ }
+ if(st_p_test_mode_param.i_PulseTestEnable >0){
+ led4 =1;
+ i_PortP21_Stat_Ave[0] = i_PortP21_Stat_Ave[1];
+ i_PortP21_Stat_Ave[1] = i_PortP21_Stat_Ave[2];
+ i_PortP21_Stat_Ave[2] = PInp_P21_Port.read();
+ if((i_PortP21_Stat_Ave[0] == i_PortP21_Stat_Ave[1])
+ && (i_PortP21_Stat_Ave[0] == i_PortP21_Stat_Ave[2])){
+ i_PortP21_Stat_New = i_PortP21_Stat_Ave[0];
+ }
+ if((ui_Main_Serial_Delay == 0) && (tx_in == tx_out)){
+ if(i_PortP21_Stat != i_PortP21_Stat_New){
+ i_PortP21_Stat = i_PortP21_Stat_New;
+// i_num = ( st_p_test_mode_param.st_p_test_mode_param.i_PulseTestEnable ) ;
+ sprintf(tx_line,"C:,%4d,P:,%4d,P21=,%1d\r\n"
+ ,ui_TestTimeCount,ui_PulseAfter_Count,i_PortP21_Stat);
+ send_line();
+ ui_Main_Serial_Delay=10; // Send Check 1.0msec Delay
+ }
+ if(ui_Main_Test_Status != MAIN_TEST_STAT_NOP){
+ ui_Main_Test_Status = MAIN_TEST_STAT_NOP;
+ if(c_TEST_msg[0] >0){
+ sprintf(tx_line,"%s\r\n",c_TEST_msg);
+ send_line();
+ // c_TEST_msg[0]=0;
+ }
+ ui_Main_Serial_Delay=10; // Send Check 1.0msec Delay
+ }
+ }
+ led4 =0;
+ }
+ // if (i_adc_ActiveMode_status != ActiveMode_ADC_Sample_Stop){
+
+ // ad_sample_send();// --- ADC Sample & Serial Data Out --- //
+ // }
+ if(rx_cr_Rec != 0){
+ Ser_Command_Input();
+ }
+ /* main_loop_count++;
+ if(main_loop_count>=100000){
+ led3 = (led3+1) & 1;
+ main_loop_count = 0;
+ }
+*/ /////////////////////////////////
+ }
+}
+
+
+//-------------------------------------------------------//
+// ADC Measurement Parameter Initial Set //
+// 2013.08.14 H.Tsunemoto
+//typedef struct st_PulseW_param{
+// int i_sample_interval; // DAC Output Pattern
+// float f_trigger_level;
+// unsigned short us_trigger_level; // (3.3f/1023) * f_trigger_level (Image)
+// int i_pre_trig_point;
+// int i_usec_Pulse_end_time;
+//}ST_PulseW_PARAM;
+//
+//ST_PulseW_PARAM st_p_test_mode_param;
+//-------------------------------------------------------//
+void adc_param_init()
+{
+ st_p_test_mode_param.i_sample_interval = const_PulseTest_Param_Default.i_sample_interval;
+
+ st_p_test_mode_param.i_usec_Pulse_width = const_PulseTest_Param_Default.i_usec_Pulse_width;
+ st_p_test_mode_param.i_usec_Pulse_Interval = const_PulseTest_Param_Default.i_usec_Pulse_Interval;
+ st_p_test_mode_param.i_usec_Pulse_RepCnt = const_PulseTest_Param_Default.i_usec_Pulse_RepCnt;
+
+ st_p_test_mode_param.i_msec_Pulse_width = const_PulseTest_Param_Default.i_msec_Pulse_width;
+ st_p_test_mode_param.i_msec_Pulse_Interval = const_PulseTest_Param_Default.i_msec_Pulse_Interval;
+ st_p_test_mode_param.i_msec_Pulse_RepCnt = const_PulseTest_Param_Default.i_msec_Pulse_RepCnt;
+ st_p_test_mode_param.i_msec_Pulse_OnOffWait = const_PulseTest_Param_Default.i_msec_Pulse_OnOffWait;
+ st_p_test_mode_param.i_PulseTestEnable = const_PulseTest_Param_Default.i_PulseTestEnable;
+
+ /*
+ int i_sample_interval; // DAC Output Pattern
+ int i_usec_Pulse_width;
+ int i_usec_Pulse_Interval;
+ int i_usec_Pulse_RepCnt;
+ int i_msec_Pulse_width;
+ int i_msec_Pulse_Interval;
+ int i_msec_Pulse_RepCnt;
+ int i_PulseTestEnable;
+ int i_msec_Pulse_OnOffWait;
+ int i_CH2_Range;
+
+ */
+}
+///////////////////////////////////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////////////////////////////
+// --- 0.1msec Interrupt Timer Pulse Test Sequence --- //
+// #define P_TESTMode_OFF 0
+// #define P_TESTMode_1SHOT_OFF 1
+// #define P_TESTMode_1SHOT_ON 2
+// #define P_TESTMode_Ntimes_OFF 3
+// #define P_TESTMode_Ntimes_ON 4
+// unsigned int ui_PulseTestMode = P_TESTMode_OFF; // Pulse Test Mode
+//
+// #define P_TESTSEQ_Nop 0 // Test Start
+// #define P_TESTSEQ_START 1 // Test Start
+// #define P_TESTSEQ_ON 2 // Test Start
+// #define P_TESTSEQ_OFF 3 // Test Start
+// #define P_TESTSEQ_End 4 // Test Start
+// unsigned int ui_PulseTestSequence = P_TESTSEQ_Nop; // Sequence Status
+// unsigned int ui_Pulse_ON_Cnt = 0;
+// unsigned int ui_Pulse_Interval_Cnt = 0;
+// unsigned int ui_Pulse_Test_Cycle_Cnt = 0;
+/////////////////////////////////////////////////////////
+void PulseTestSequence(void)
+{
+ /////////////////////////////////////////////////////////
+ ////////// ------------------------- //////////////
+ ////////// Pulse Test Sequence //////////////
+ ////////// ------------------------- //////////////
+ /////////////////////////////////////////////////////////
+ switch (ui_PulseTestMode){
+ case P_TESTMode_Nop:
+ break;
+ /////////////////////////////////////////////////////////
+ ////////// -------------------------- //////////////
+ ////////// -- XRay OFF 1Shot -- //////////////
+ ////////// -------------------------- //////////////
+ /////////////////////////////////////////////////////////
+ case P_TESTMode_1SHOT_OFF:
+ // ----------- X ray OFF 1Shot Test ----------//
+ switch (ui_PulseTestSequence){
+ case P_TESTSEQ_Nop:
+ break;
+ case P_TESTSEQ_START:
+// sprintf(c_TEST_msg,"START,P30,P1Shot\n");
+// ui_Main_Test_Status = MAIN_TEST_STAT_START;
+ POut_P30_Pulse.write(1);
+ // i_PortP21_Stat = PInp_P21_Port.read();
+ ui_PulseAfter_Count =0;
+ ui_TestTimeCount=1;
+ ui_PulseTestSequence = P_TESTSEQ_ON;
+ ui_Pulse_ON_Cnt = st_p_test_mode_param.i_msec_Pulse_width;
+ break;
+ case P_TESTSEQ_ON:
+ if(ui_Pulse_ON_Cnt >0){
+ ui_Pulse_ON_Cnt--;
+ }
+ else{
+ POut_P30_Pulse.write(0);
+ ui_PulseTestSequence = P_TESTSEQ_End;
+ sprintf(c_TEST_msg,"END,P30,P1Shot\n");
+ ui_Main_Test_Status = MAIN_TEST_STAT_END;
+ }
+ break;
+ case P_TESTSEQ_End:
+ break;
+ default:
+ break;
+ }
+ //--------------------------------------------------//
+ break;
+ /////////////////////////////////////////////////////////
+ ////////// -------------------------- //////////////
+ ////////// -- XRay ON(P29) 1Shot -- //////////////
+ ////////// -------------------------- //////////////
+ /////////////////////////////////////////////////////////
+ case P_TESTMode_1SHOT_ON:
+ // ----------- X ray OFF 1Shot Test ----------//
+ switch (ui_PulseTestSequence){
+ case P_TESTSEQ_Nop:
+ break;
+ case P_TESTSEQ_START:
+// sprintf(c_TEST_msg,"START,P29,P1Shot\n");
+// ui_Main_Test_Status = MAIN_TEST_STAT_START;
+ POut_P29_Pulse.write(1);
+// i_PortP21_Stat = PInp_P21_Port.read();
+ ui_PulseAfter_Count =0;
+ ui_TestTimeCount++;
+
+ ui_PulseTestSequence = P_TESTSEQ_ON;
+ ui_Pulse_ON_Cnt = st_p_test_mode_param.i_msec_Pulse_width;
+ break;
+ case P_TESTSEQ_ON:
+ if(ui_Pulse_ON_Cnt >0){
+ ui_Pulse_ON_Cnt--;
+ }
+ else{
+ POut_P29_Pulse.write(0);
+ ui_PulseTestSequence = P_TESTSEQ_End;
+ sprintf(c_TEST_msg,"END,P29,P1Shot\n");
+ ui_Main_Test_Status = MAIN_TEST_STAT_END;
+ }
+ break;
+ case P_TESTSEQ_End:
+ break;
+ default:
+ break;
+ }
+ //--------------------------------------------------//
+ break;
+ /////////////////////////////////////////////////////////
+ ////////// -------------------------------------- //////////////
+ ////////// -- XRay OFF(P30) N Times Test -- //////////////
+ ////////// -------------------------------------- //////////////
+ /////////////////////////////////////////////////////////
+ case P_TESTMode_Ntimes_OFF:
+ // ----------- X ray OFF Cycle N Test ----------//
+ switch (ui_PulseTestSequence){
+ case P_TESTSEQ_Nop:
+ break;
+ case P_TESTSEQ_START:
+// sprintf(c_TEST_msg,"START,P30,PN:,%4d,Times\n",st_p_test_mode_param.i_msec_Pulse_RepCnt);
+// ui_Main_Test_Status = MAIN_TEST_STAT_START;
+ ui_TestTimeCount=1;
+ sprintf(c_TEST_msg,"TEST_N,%4d,OFF\n",ui_TestTimeCount);
+ ui_Main_Test_Status = MAIN_TEST_STAT_CNT;
+ POut_P30_Pulse.write(1);
+ // i_PortP21_Stat = PInp_P21_Port.read();
+ ui_PulseAfter_Count =0;
+ ui_PulseTestSequence = P_TESTSEQ_ON;
+ ui_Pulse_ON_Cnt = st_p_test_mode_param.i_msec_Pulse_width;
+ if(st_p_test_mode_param.i_msec_Pulse_RepCnt > 0){
+ ui_Pulse_Test_Cycle_Cnt = st_p_test_mode_param.i_msec_Pulse_RepCnt-1;
+ }
+ else{
+ ui_Pulse_Test_Cycle_Cnt = 0;
+ }
+ break;
+ case P_TESTSEQ_ON:
+ if(ui_Pulse_ON_Cnt >0){
+ ui_Pulse_ON_Cnt--;
+ }
+ else{
+ POut_P30_Pulse.write(0);
+
+ if(ui_Pulse_Test_Cycle_Cnt >0){
+ ui_Pulse_Test_Cycle_Cnt--;
+ ui_Pulse_Interval_Cnt = st_p_test_mode_param.i_msec_Pulse_Interval;
+ ui_PulseTestSequence = P_TESTSEQ_OFF;
+ }
+ else{
+ ui_PulseTestSequence = P_TESTSEQ_End;
+ sprintf(c_TEST_msg,"END,P30,PN:\n");
+ ui_Main_Test_Status = MAIN_TEST_STAT_END;
+ }
+ }
+ break;
+ case P_TESTSEQ_OFF:
+ if(ui_Pulse_Interval_Cnt >0){
+ ui_Pulse_Interval_Cnt--;
+ }
+ else{
+ ui_TestTimeCount++;
+ sprintf(c_TEST_msg,"TEST_N,%4d,OFF\n",ui_TestTimeCount);
+ ui_Main_Test_Status = MAIN_TEST_STAT_CNT;
+ POut_P30_Pulse.write(1);
+ // i_PortP21_Stat = PInp_P21_Port.read();
+ ui_PulseAfter_Count =0;
+ ui_Pulse_ON_Cnt = st_p_test_mode_param.i_msec_Pulse_width;
+ ui_PulseTestSequence = P_TESTSEQ_ON;
+ }
+ break;
+ case P_TESTSEQ_End:
+ break;
+ default:
+ break;
+ }
+ //--------------------------------------------------//
+ break;
+ /////////////////////////////////////////////////////////
+ ////////// -------------------------------------- //////////////
+ ////////// -- XRay ON(P29) N Times Test -- //////////////
+ ////////// -------------------------------------- //////////////
+ /////////////////////////////////////////////////////////
+ case P_TESTMode_Ntimes_ON:
+ // ----------- X ray OFF Cycle N Test ----------//
+ switch (ui_PulseTestSequence){
+ case P_TESTSEQ_Nop:
+ break;
+ case P_TESTSEQ_START:
+ ui_TestTimeCount=1;
+ sprintf(c_TEST_msg,"TEST_N,%4d,ON\n",ui_TestTimeCount);
+ ui_Main_Test_Status = MAIN_TEST_STAT_CNT;
+ // sprintf(c_TEST_msg,"START,P29,PN:,%4d,Times\n",st_p_test_mode_param.i_msec_Pulse_RepCnt);
+ // ui_Main_Test_Status = MAIN_TEST_STAT_START;
+ POut_P29_Pulse.write(1);
+// i_PortP21_Stat = PInp_P21_Port.read();
+ ui_PulseAfter_Count =0;
+ ui_PulseTestSequence = P_TESTSEQ_ON;
+ ui_Pulse_ON_Cnt = st_p_test_mode_param.i_msec_Pulse_width;
+ if(st_p_test_mode_param.i_msec_Pulse_RepCnt > 0){
+ ui_Pulse_Test_Cycle_Cnt = st_p_test_mode_param.i_msec_Pulse_RepCnt-1;
+ }
+ else{
+ ui_Pulse_Test_Cycle_Cnt = 0;
+ }
+ break;
+ case P_TESTSEQ_ON:
+ if(ui_Pulse_ON_Cnt >0){
+ ui_Pulse_ON_Cnt--;
+ }
+ else{
+ POut_P29_Pulse.write(0);
+ // ui_TestTimeCount++;
+ if(ui_Pulse_Test_Cycle_Cnt >0){
+ ui_Pulse_Test_Cycle_Cnt--;
+ ui_Pulse_Interval_Cnt = st_p_test_mode_param.i_msec_Pulse_Interval;
+ ui_PulseTestSequence = P_TESTSEQ_OFF;
+ }
+ else{
+ ui_PulseTestSequence = P_TESTSEQ_End;
+ sprintf(c_TEST_msg,"END,P29,PN:\n");
+ ui_Main_Test_Status = MAIN_TEST_STAT_END;
+ }
+ }
+ break;
+ case P_TESTSEQ_OFF:
+ if(ui_Pulse_Interval_Cnt >0){
+ ui_Pulse_Interval_Cnt--;
+ }
+ else{
+ ui_TestTimeCount++;
+ sprintf(c_TEST_msg,"TEST_N,%4d,ON\n",ui_TestTimeCount);
+ ui_Main_Test_Status = MAIN_TEST_STAT_CNT;
+ POut_P29_Pulse.write(1);
+ // i_PortP21_Stat = PInp_P21_Port.read();
+ ui_PulseAfter_Count =0;
+ ui_Pulse_ON_Cnt = st_p_test_mode_param.i_msec_Pulse_width;
+ ui_PulseTestSequence = P_TESTSEQ_ON;
+ }
+ break;
+ case P_TESTSEQ_End:
+ break;
+ default:
+ break;
+ }
+ //--------------------------------------------------//
+ break;
+ ////////////////////////////////////////////////////////////////////////////////
+ ////////// ------------------------------------------------ //////////////
+ ////////// -- XRay ON/OFF (P29 & P30) N Times Test -- //////////////
+ ////////// ------------------------------------------------ //////////////
+ ////////////////////////////////////////////////////////////////////////////////
+ case P_TESTMode_Ntimes_ONOFF:
+ // ----------- X ray OFF Cycle N Test ----------//
+ switch (ui_PulseTestSequence){
+ case P_TESTSEQ_Nop:
+ break;
+ case P_TESTSEQ_START:
+// sprintf(c_TEST_msg,"START,ONOFF_P29_30,PN:,%4d,Times\n",st_p_test_mode_param.i_msec_Pulse_RepCnt);
+// ui_Main_Test_Status = MAIN_TEST_STAT_START;
+ ui_TestTimeCount=1;
+ sprintf(c_TEST_msg,"TEST_N,%4d,ON\n",ui_TestTimeCount);
+ ui_Main_Test_Status = MAIN_TEST_STAT_CNT;
+ POut_P29_Pulse.write(1);
+ // i_PortP21_Stat = PInp_P21_Port.read();
+ ui_PulseAfter_Count =0;
+ ui_PulseTestSequence = P_TESTSEQ_ON;
+ ui_Pulse_ON_Cnt = st_p_test_mode_param.i_msec_Pulse_width;
+ if(st_p_test_mode_param.i_msec_Pulse_RepCnt > 0){
+ ui_Pulse_Test_Cycle_Cnt = st_p_test_mode_param.i_msec_Pulse_RepCnt-1;
+ }
+ else{
+ ui_Pulse_Test_Cycle_Cnt = 0;
+ }
+ break;
+ case P_TESTSEQ_ON:
+ if(ui_Pulse_ON_Cnt >0){
+ ui_Pulse_ON_Cnt--;
+ }
+ else{
+ POut_P29_Pulse.write(0);
+ ui_Pulse_Interval_Cnt = st_p_test_mode_param.i_msec_Pulse_Interval;
+ ui_PulseTestSequence = P_TESTSEQ_OFF;
+ }
+ break;
+ case P_TESTSEQ_OFF:
+ if(ui_Pulse_Interval_Cnt >0){
+ ui_Pulse_Interval_Cnt--;
+ }
+ else{
+ sprintf(c_TEST_msg,"TEST_N,%4d,OFF\n",ui_TestTimeCount);
+ ui_Main_Test_Status = MAIN_TEST_STAT_CNT;
+ POut_P30_Pulse.write(1);
+ // i_PortP21_Stat = PInp_P21_Port.read();
+ ui_PulseAfter_Count =0;
+ ui_Pulse_ON_Cnt = st_p_test_mode_param.i_msec_Pulse_width;
+ ui_PulseTestSequence = P_TESTSEQ_ONOFF_P30_ON;
+ }
+ break;
+ case P_TESTSEQ_ONOFF_P30_ON:
+ if(ui_Pulse_ON_Cnt >0){
+ ui_Pulse_ON_Cnt--;
+ }
+ else{
+ POut_P30_Pulse.write(0);
+
+ // ui_TestTimeCount++;
+ if(ui_Pulse_Test_Cycle_Cnt >0){
+ ui_Pulse_Test_Cycle_Cnt--;
+ ui_Pulse_Interval_Cnt = st_p_test_mode_param.i_msec_Pulse_OnOffWait;
+ ui_PulseTestSequence = P_TESTSEQ_ONOFF_P30_OFF;
+ }
+ else{
+ ui_PulseTestSequence = P_TESTSEQ_End;
+ sprintf(c_TEST_msg,"END,ONOFF_P29_30:\n");
+ ui_Main_Test_Status = MAIN_TEST_STAT_END;
+ }
+ }
+ break;
+ case P_TESTSEQ_ONOFF_P30_OFF:
+ if(ui_Pulse_Interval_Cnt >0){
+ ui_Pulse_Interval_Cnt--;
+ }
+ else{
+ ui_TestTimeCount++;
+ sprintf(c_TEST_msg,"TEST_N,%4d,ON\n",ui_TestTimeCount);
+ ui_Main_Test_Status = MAIN_TEST_STAT_CNT;
+ POut_P29_Pulse.write(1);
+ // i_PortP21_Stat = PInp_P21_Port.read();
+ ui_PulseAfter_Count =0;
+ ui_Pulse_ON_Cnt = st_p_test_mode_param.i_msec_Pulse_width;
+ ui_PulseTestSequence = P_TESTSEQ_ON;
+ }
+ break;
+ case P_TESTSEQ_End:
+ break;
+ default:
+ break;
+ }
+ //--------------------------------------------------//
+ break;
+ default: //
+ break;
+
+
+ }
+}
+//------------------------------------------------------------------------------//
+//----- DAC Control Function
+// H.Tsunemoto Scince 2013.08.09
+// int i_pattern; // DAC Output Pattern
+// float f_pulse_high;
+// float f_pulse_low;
+// int i_usec_Pulse_width;
+// int i_usec_Pulse_interval;
+// int i_Total_time;
+//
+//------------------------------------------------------------------------------//
+//
+//------------------------------------------------------------------------//
+// Timer Interrupt Routine
+//
+//------------------------------------------------------------------------//
+extern "C" void TIMER0_IRQHandler (void)
+{
+ if((LPC_TIM0->IR & 0x01) == 0x01) // if MR0 interrupt, proceed
+ {
+ if(i_LED_Active == Debug_LED_Active){
+ led2 =1;
+ }
+ LPC_TIM0->IR |= 1 << 0; // Clear MR0 interrupt flag
+ timer_count++; //increment timer_count
+ if(timer_count >= 10000){
+ timer_count = 0;
+ timer_1Sec++;
+ }
+ if(ui_PulseTestMode != P_TESTMode_Nop){
+ ui_PulseAfter_Count ++;
+ PulseTestSequence();
+ if(ui_Main_Serial_Delay>0){
+ ui_Main_Serial_Delay--;
+ }
+ }
+ if(i_LED_Active == Debug_LED_Active){
+ led2 =0;
+ }
+ }
+}
+
+void timer0_init(void)
+{
+ LPC_SC->PCONP |=1<1; //timer0 power on
+ // 2013.08.09 H.Tsunemoto 100mSec => 0.1mSec Change
+ //LPC_TIM0->MR0 = 2398000; //100 msec
+ LPC_TIM0->MR0 = 2398; //0.1 msec
+
+ LPC_TIM0->MCR = 3; //interrupt and reset control
+ //3 = Interrupt & reset timer0 on match
+ //1 = Interrupt only, no reset of timer0
+ NVIC_EnableIRQ(TIMER0_IRQn); //enable timer0 interrupt
+ LPC_TIM0->TCR = 1; //enable Timer0
+ // pc.printf("Done timer_init\n\r");
+}
+
+//------------------------------------------------------------------//
+//----- Serial rx Commmand Input & Parameter Set Function -----//
+// Tsunemoto Since 2016.05.20 //
+// ADC No.1 "SMP 1000" ADC Sample Rate 2 - 1000 msec
+// ADC No.2 "RNA 0" ADC CH1 Range 0 / 1
+// ADC No.3 "RNB 1" ADC CH2 Range 0 / 1
+// ADC No.4 "START" ADC Sample Start
+// ADC No.5 "STOP" ADC Sample Stop
+// ADC No.6 // "?"
+
+//------------------------------------------------------------------//
+void Ser_Command_Input()
+{
+ int i_RecCharCount;
+// int b_CommadERR = 0;
+
+ while(rx_cr_Rec != 0){
+ // Read a line from the large rx buffer from rx interrupt routine
+
+ if(rx_in != rx_out){
+ i_RecCharCount = read_line();
+ // b_CommadERR = 0;
+ if(i_RecCharCount != 0){
+//////////////////////////////////////////
+// else{
+ switch(rx_line[0]){
+ // Header "M" Pulse Test Command
+ // ---- msec Pulse Test Command ---- //
+ case 'm':
+ case 'M':
+ switch(rx_line[1]){
+ // Header "MP" Pulse Test Command
+ case 'P':
+ case 'p':
+ if((rx_line[2] == 'W') ){
+ com_Check_msecMPW( i_RecCharCount);
+ }
+ else if((rx_line[2] == 'I') ){
+ com_Check_msecMPI( i_RecCharCount);
+ }
+ else if((rx_line[2] == 'C')){
+ com_Check_msecMPC( i_RecCharCount);
+ }
+ else if((rx_line[2] == 'T')){
+ com_Check_msecMPT( i_RecCharCount);
+ }
+ break;
+ // Header "MF" Pulse Test Command
+ case 'f':
+ case 'F':
+ if((rx_line[2] == 'N')){
+ com_Check_msecPulseMPN( i_RecCharCount);
+ }
+ else if((rx_line[2] == '1')){
+ com_Check_msecPulseMP1( i_RecCharCount);
+ }
+ break;
+ // Header "MX" ADC Control Command
+ case 'X':
+ case 'x':
+ if((rx_line[2] == 'N') ){
+ com_Check_msecPulseMXN( i_RecCharCount);
+ }
+ else if((rx_line[2] == '1') ){
+ com_Check_msecPulseMX1( i_RecCharCount);
+ }
+ break;
+ // Header "MF" Pulse Test Command
+ case 't':
+ case 'T':
+ if((rx_line[2] == 'N')){
+ com_Check_msecPulseMTN( i_RecCharCount);
+ }
+ else if((rx_line[2] == 'W')){
+ com_Check_msecPulseMTW( i_RecCharCount);
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ // ---- usec Short Pulse Test Command ---- //
+ case 'u':
+ case 'U':
+ switch(rx_line[1]){
+ case 'P':
+ case 'p':
+ if((rx_line[2] == 'W') ){
+ com_Check_usecUPW(i_RecCharCount);
+ }
+ else if((rx_line[2] == 'I') ){
+ com_Check_usecUPI(i_RecCharCount);
+ }
+ else if((rx_line[2] == 'C')){
+ com_Check_usecUPC(i_RecCharCount);
+ }
+ break;
+ case 'f':
+ case 'F':
+ if((rx_line[2] == 'N')){
+ com_Check_usecPulseUPN(i_RecCharCount);
+ }
+ else if((rx_line[2] == '1')){
+ com_Check_usecPulseUP1(i_RecCharCount);
+ }
+ else{
+ com_Check_usecPulseA(i_RecCharCount);
+ }
+ break;
+ // Header "A" ADC Control Command
+ case 'X':
+ case 'x':
+ if((rx_line[2] == 'N') ){
+ com_Check_usecPulseUXN( i_RecCharCount);
+ }
+ else if((rx_line[2] == '1') ){
+ com_Check_usecPulseUX1( i_RecCharCount);
+ }
+ else{
+ com_Check_usecPulseB(i_RecCharCount);
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case 'S':
+ if(i_RecCharCount == 1){
+// i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Busy;
+// Start_ADC();
+ }
+ else if (rx_line[1] == 'T'){
+ //case 'T':
+ if((rx_line[2] == 'A') && (rx_line[3] == 'R') && (rx_line[4] == 'T')){
+ // i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Busy;
+ // Start_ADC();
+
+ }
+ else if((rx_line[2] == 'O') && (rx_line[3] == 'P') ){
+ // i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Stop;
+ // ADC_Stop();
+ }
+ else if ((rx_line[2] == '?')){ //{ "ST?"
+ com_ADC_Table_Param_Send();
+ }
+ else if ( (rx_line[2] == 'A')&& (rx_line[3] == '?')){ //{ "STA?"
+ com_ADC_Table_Param_Send();
+ }
+ else if ( (rx_line[2] == 'A')&& (rx_line[3] == 'T')&& (rx_line[4] == '?')){ //{ "STAT?"
+ com_ADC_Table_Param_Send();
+ }
+ else{
+ // b_CommadERR = 1;
+ }
+ //break;
+ }
+ else if((rx_line[1] == 'M') && (rx_line[2] == 'P')){
+ com_Check_SMP( i_RecCharCount);
+ }
+ else if (rx_line[1] == '?'){ //{ case '?':
+ com_ADC_Table_Param_Send();
+ //break;
+ }
+ else{
+ //default:
+// b_CommadERR = 1;
+ //break;
+ }
+ break;
+ case 'T': // "T?" Timer Interrupt Counter Repry
+ if (rx_line[1]=='?'){
+ sprintf(tx_line,"Timer=%d[S}+%d[x0.1mSec] \r\n",timer_1Sec,timer_count);
+ // Copy tx line buffer to large tx buffer for tx interrupt routine
+ send_line();
+
+ }
+ else if(rx_line[1]=='C'){
+ timer_1Sec = timer_count = 0;
+ }
+ else{
+ // b_CommadERR = 1;
+ }
+ break;
+
+ case '?':
+ if(i_RecCharCount == 1){
+ com_ADC_Table_Param_Send();
+ }
+ else{
+ // b_CommadERR = 1;
+ }
+ break;
+ //break;
+ case 'E':
+ if(i_RecCharCount == 1){
+ // i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Stop;
+ // ADC_Stop();
+ }
+ else{
+ // b_CommadERR = 1;
+ }
+ break;
+ case 'L':
+ if((rx_line[1] == 'E') && (rx_line[2] == 'D') ){
+ com_Check_LED(i_RecCharCount);
+ }
+ else{
+ }
+ default:
+// b_CommadERR = 1;
+ break;
+
+ }
+ }
+// if(rx_line[0] >= 0x20){
+// if(b_CommadERR == 0){
+// sprintf(tx_line,"ACK%d \r\n",rx_cr_Rec);
+// // Copy tx line buffer to large tx buffer for tx interrupt routine
+// send_line();
+// }
+// else{
+// sprintf(tx_line,"ERR%d \r\n",rx_cr_Rec);
+// // Copy tx line buffer to large tx buffer for tx interrupt routine
+// send_line();
+// }
+// }
+ rx_cr_Rec--;
+ }
+ else{
+ rx_cr_Rec = 0;
+ break;
+ }
+ }
+}
+
+//////------------------------------------------------------------------------------/////
+//////--------------- usec Short Pulse Test Command ---------------------/////
+//////------------------------------------------------------------------------------/////
+
+
+//////////////////////////////////////////////////////////////////////////////////
+//------------ Command Check & Set Function ---------------------------------//
+// Input :i_RecCharCount :Command Stringth Length //
+// rx_line[80] :(Global) Rec Data Stringth //
+// Return :bool b_CommadERR 0= ACK //
+// 1= ERR //
+//////////////////////////////////////////////////////////////////////////////////
+void com_Check_usecPulseA(int i_RecCharCount)
+{
+// bool b_CommadERR=0;
+ // int i_num=2;
+ int i_count = st_p_test_mode_param.i_sample_interval;
+ int i;
+ if(i_count == 0){
+ POut_P30_Pulse.write(1);
+ POut_P30_Pulse.write(0);
+ }
+ else{
+ POut_P30_Pulse.write(0);
+ for(i=0;i<i_count;i++){
+ POut_P30_Pulse.write(1);
+ }
+ POut_P30_Pulse.write(0);
+ }
+// return(b_CommadERR);
+}
+void com_Check_usecPulseUP1(int i_RecCharCount)
+{
+ // bool b_CommadERR=0;
+ // int i_num=2;
+ int i_count = st_p_test_mode_param.i_usec_Pulse_width;
+ int i;
+ if(i_count == 0){
+ POut_P30_Pulse.write(1);
+ POut_P30_Pulse.write(0);
+ }
+ else{
+ POut_P30_Pulse.write(0);
+ for(i=0;i<i_count;i++){
+ POut_P30_Pulse.write(1);
+ }
+ POut_P30_Pulse.write(0);
+ }
+// return(b_CommadERR);
+}
+
+void com_Check_usecPulseUPN(int i_RecCharCount)
+{
+ // bool b_CommadERR=0;
+ // int i_num=2;
+ int i_PluseWidth = st_p_test_mode_param.i_usec_Pulse_width;
+ int i_usec_PulseInt = st_p_test_mode_param.i_usec_Pulse_Interval;
+ int i_count = st_p_test_mode_param.i_usec_Pulse_RepCnt;
+ if(i_count<0) {
+ i_count = 1;
+ }
+ /*
+ int i_usec_Pulse_width;
+ int i_usec_Pulse_Interval;
+ int i_usec_Pulse_RepCnt;
+
+ */
+ int i,k;
+ for (k=0;k< i_count;k++){
+ if(i_PluseWidth == 0){
+ POut_P30_Pulse.write(1);
+ POut_P30_Pulse.write(0);
+ }
+ else{
+ POut_P30_Pulse.write(0);
+ for(i=0;i<i_PluseWidth;i++){
+ POut_P30_Pulse.write(1);
+ }
+ POut_P30_Pulse.write(0);
+ }
+ if(i_usec_PulseInt == 0){
+ POut_P30_Pulse.write(0);
+ POut_P30_Pulse.write(0);
+ }
+ else{
+ POut_P30_Pulse.write(0);
+ for(i=0;i<i_usec_PulseInt;i++){
+ POut_P30_Pulse.write(0);
+ }
+ POut_P30_Pulse.write(0);
+ }
+
+ }
+// return(b_CommadERR);
+}
+void com_Check_usecPulseB(int i_RecCharCount)
+{
+ // bool b_CommadERR=0;
+ // int i_num=2;
+ int i_count = st_p_test_mode_param.i_sample_interval;
+ int i;
+ if(i_count == 0){
+ POut_P29_Pulse.write(1);
+ POut_P29_Pulse.write(0);
+ }
+ else{
+ POut_P29_Pulse.write(0);
+ for(i=0;i<i_count;i++){
+ POut_P29_Pulse.write(1);
+ }
+ POut_P29_Pulse.write(0);
+ }
+// return(b_CommadERR);
+}
+void com_Check_usecPulseUX1(int i_RecCharCount)
+{
+ // bool b_CommadERR=0;
+ // int i_num=2;
+ int i_count = st_p_test_mode_param.i_usec_Pulse_width;
+ int i;
+ if(i_count == 0){
+ POut_P29_Pulse.write(1);
+ POut_P29_Pulse.write(0);
+ }
+ else{
+ POut_P29_Pulse.write(0);
+ for(i=0;i<i_count;i++){
+ POut_P29_Pulse.write(1);
+ }
+ POut_P29_Pulse.write(0);
+ }
+ // return(b_CommadERR);
+}
+void com_Check_usecPulseUXN(int i_RecCharCount)
+{
+// bool b_CommadERR=0;
+ // int i_num=2;
+ // int i_count = st_p_test_mode_param.i_sample_interval;
+ int i_PluseWidth = st_p_test_mode_param.i_usec_Pulse_width;
+ int i_usec_PulseInt = st_p_test_mode_param.i_usec_Pulse_Interval;
+ int i_count = st_p_test_mode_param.i_usec_Pulse_RepCnt;
+ if(i_count<0) {
+ i_count = 1;
+ }
+ int i,k;
+ for (k=0;k< i_count;k++){
+ if(i_PluseWidth == 0){
+ POut_P29_Pulse.write(1);
+ POut_P29_Pulse.write(0);
+ }
+ else{
+ POut_P29_Pulse.write(0);
+ for(i=0;i<i_PluseWidth;i++){
+ POut_P29_Pulse.write(1);
+ }
+ POut_P29_Pulse.write(0);
+ }
+ if(i_usec_PulseInt == 0){
+ POut_P29_Pulse.write(0);
+ POut_P29_Pulse.write(0);
+ }
+ else{
+ POut_P29_Pulse.write(0);
+ for(i=0;i<i_usec_PulseInt;i++){
+ POut_P29_Pulse.write(0);
+ }
+ POut_P29_Pulse.write(0);
+ }
+ }
+ // return(b_CommadERR);
+}
+
+//------------------------------------------------------------------------------//
+// ADC No.02 "PAW xxxx Pulse WidthCount Set //
+//#define ADC_SAMPLE_RATE_MIN 2
+//#define ADC_SAMPLE_RATE_MAX 1000
+//int st_p_test_mode_param.i_sample_interval = 200; // ADC Sample Rate 5 - 20000(20.0mSec)
+//------------------------------------------------------------------------------//
+void com_Check_usecUPW(int i_RecCharCount)
+{
+//bool b_CommadERR=0;
+int i_num=2;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+// b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ st_p_test_mode_param.i_usec_Pulse_width = (int)( i_num);
+
+ }
+ // return(b_CommadERR);
+ }
+//------------------------------------------------------------------------------//
+// ADC No.03 "PIW xxxx Pulse Interval Count Set //
+//#define ADC_SAMPLE_RATE_MIN 2
+//#define ADC_SAMPLE_RATE_MAX 1000
+//int st_p_test_mode_param.i_sample_interval = 200; // ADC Sample Rate 5 - 20000(20.0mSec)
+//------------------------------------------------------------------------------//
+void com_Check_usecUPI(int i_RecCharCount)
+{
+//bool b_CommadERR=0;
+int i_num=2;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+ // b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ st_p_test_mode_param.i_usec_Pulse_Interval = (int)( i_num);
+
+ }
+ // return(b_CommadERR);
+ }
+//------------------------------------------------------------------------------//
+// ADC No.04 "PRC xxxx Pulse Repeat Count Set //
+//#define ADC_SAMPLE_RATE_MIN 2
+//#define ADC_SAMPLE_RATE_MAX 1000
+//int st_p_test_mode_param.i_sample_interval = 200; // ADC Sample Rate 5 - 20000(20.0mSec)
+//------------------------------------------------------------------------------//
+void com_Check_usecUPC(int i_RecCharCount)
+{
+//bool b_CommadERR=0;
+int i_num=2;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+ // b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ st_p_test_mode_param.i_usec_Pulse_RepCnt = (int)( i_num);
+
+ }
+ // return(b_CommadERR);
+ }
+//////------------------------------------------------------------------------------/////
+//////--------------- ↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑ ---------------------/////
+//////------------------------------------------------------------------------------/////
+
+//////------------------------------------------------------------------------------/////
+//////--------------- msec Pulse Test Command ---------------------/////
+//////------------------------------------------------------------------------------/////
+
+
+//////////////////////////////////////////////////////////////////////////////////
+//------------ Command Check & Set Function ---------------------------------//
+// Input :i_RecCharCount :Command Stringth Length //
+// rx_line[80] :(Global) Rec Data Stringth //
+// Return :bool b_CommadERR 0= ACK //
+// 1= ERR //
+//////////////////////////////////////////////////////////////////////////////////
+void com_Check_msecPulseMP1(int i_RecCharCount)
+{
+ // bool b_CommadERR=0;
+ // sprintf(c_TEST_msg,"START,P30,P1Shot\n");
+ // ui_Main_Test_Status = MAIN_TEST_STAT_START;
+ sprintf(tx_line,"START,P30,P1Shot\r\n");
+ send_line();
+ ui_PulseTestMode = P_TESTMode_Nop;
+ ui_PulseTestSequence = P_TESTSEQ_START;
+ ui_PulseTestMode = P_TESTMode_1SHOT_OFF;
+// return(b_CommadERR);
+}
+
+void com_Check_msecPulseMPN(int i_RecCharCount)
+{
+// bool b_CommadERR=0;
+ sprintf(tx_line,"START_N,%4d,Times,OFF_P30\n",st_p_test_mode_param.i_msec_Pulse_RepCnt);
+ send_line();
+ // ui_Main_Test_Status = MAIN_TEST_STAT_START;
+ ui_PulseTestMode = P_TESTMode_Nop;
+ ui_PulseTestSequence = P_TESTSEQ_START;
+ ui_PulseTestMode = P_TESTMode_Ntimes_OFF;
+// return(b_CommadERR);
+}
+void com_Check_msecPulseMX1(int i_RecCharCount)
+{
+// bool b_CommadERR=0;
+ sprintf(tx_line,"START,P29,P1Shot\r\n");
+ send_line();
+ ui_PulseTestMode = P_TESTMode_Nop;
+ ui_PulseTestSequence = P_TESTSEQ_START;
+ ui_PulseTestMode = P_TESTMode_1SHOT_ON;
+ // return(b_CommadERR);
+}
+void com_Check_msecPulseMXN(int i_RecCharCount)
+{
+ // bool b_CommadERR=0;
+ sprintf(tx_line,"START_N,%4d,Times,ON_P29\n",st_p_test_mode_param.i_msec_Pulse_RepCnt);
+ send_line();
+ ui_PulseTestMode = P_TESTMode_Nop;
+ ui_PulseTestSequence = P_TESTSEQ_START;
+ ui_PulseTestMode = P_TESTMode_Ntimes_ON;
+ // return(b_CommadERR);
+}
+void com_Check_msecPulseMTN(int i_RecCharCount)
+{
+ // bool b_CommadERR=0;
+ sprintf(tx_line,"START,%4d,Times,ONOFF_P29_30\n",st_p_test_mode_param.i_msec_Pulse_RepCnt);
+ send_line();
+ ui_PulseTestMode = P_TESTMode_Nop;
+ ui_PulseTestSequence = P_TESTSEQ_START;
+ ui_PulseTestMode = P_TESTMode_Ntimes_ONOFF;
+ // return(b_CommadERR);
+}
+
+void com_Check_msecPulseMTW(int i_RecCharCount)
+{
+int i_num=2;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+ // b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ st_p_test_mode_param.i_msec_Pulse_OnOffWait = (int)( i_num);
+
+ }
+// return(b_CommadERR);
+ }
+//------------------------------------------------------------------------------//
+// ADC No.02 "PAW xxxx Pulse WidthCount Set //
+//#define ADC_SAMPLE_RATE_MIN 2
+//#define ADC_SAMPLE_RATE_MAX 1000
+//int st_p_test_mode_param.i_sample_interval = 200; // ADC Sample Rate 5 - 20000(20.0mSec)
+//------------------------------------------------------------------------------//
+void com_Check_msecMPW(int i_RecCharCount)
+{
+int i_num=2;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+ // b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ st_p_test_mode_param.i_msec_Pulse_width = (int)( i_num);
+
+ }
+// return(b_CommadERR);
+ }
+//------------------------------------------------------------------------------//
+// ADC No.03 "PIW xxxx Pulse Interval Count Set //
+//#define ADC_SAMPLE_RATE_MIN 2
+//#define ADC_SAMPLE_RATE_MAX 1000
+//int st_p_test_mode_param.i_sample_interval = 200; // ADC Sample Rate 5 - 20000(20.0mSec)
+//------------------------------------------------------------------------------//
+void com_Check_msecMPI(int i_RecCharCount)
+{
+//bool b_CommadERR=0;
+int i_num=2;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+ // b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ st_p_test_mode_param.i_msec_Pulse_Interval = (int)( i_num);
+
+ }
+ // return(b_CommadERR);
+ }
+//------------------------------------------------------------------------------//
+// ADC No.04 "PRC xxxx Pulse Repeat Count Set //
+//#define ADC_SAMPLE_RATE_MIN 2
+//#define ADC_SAMPLE_RATE_MAX 1000
+//int st_p_test_mode_param.i_sample_interval = 200; // ADC Sample Rate 5 - 20000(20.0mSec)
+//------------------------------------------------------------------------------//
+void com_Check_msecMPC(int i_RecCharCount)
+{
+//bool b_CommadERR=0;
+int i_num=2;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+ // b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ st_p_test_mode_param.i_msec_Pulse_RepCnt = (int)( i_num);
+
+ }
+ // return(b_CommadERR);
+ }
+//------------------------------------------------------------------------------//
+// ADC No.04 "PRC xxxx Pulse Repeat Count Set //
+//#define ADC_SAMPLE_RATE_MIN 2
+//#define ADC_SAMPLE_RATE_MAX 1000
+//int st_p_test_mode_param.i_sample_interval = 200; // ADC Sample Rate 5 - 20000(20.0mSec)
+//------------------------------------------------------------------------------//
+void com_Check_msecMPT(int i_RecCharCount)
+{
+//bool b_CommadERR=0;
+int i_num=2;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+ // b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ if(i_num >0){
+ st_p_test_mode_param.i_PulseTestEnable = 1;
+ }
+ else{
+ st_p_test_mode_param.i_PulseTestEnable = 0;
+ }
+
+ }
+ // return(b_CommadERR);
+ }
+//////------------------------------------------------------------------------------/////
+//////--------------- ↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑ ---------------------/////
+//////------------------------------------------------------------------------------/////
+
+//------------------------------------------------------------------------------//
+// ADC No.1 "SMP xxxx ADC Sample Interval Set //
+//#define ADC_SAMPLE_RATE_MIN 2
+//#define ADC_SAMPLE_RATE_MAX 1000
+//int st_p_test_mode_param.i_sample_interval = 200; // ADC Sample Rate 5 - 20000(20.0mSec)
+//------------------------------------------------------------------------------//
+bool com_Check_SMP(int i_RecCharCount)
+{
+bool b_CommadERR=0;
+int i_num=2;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+ b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ st_p_test_mode_param.i_sample_interval = (int)( i_num);
+
+ }
+ return(b_CommadERR);
+ }
+//------------------------------------------------------------------------------//
+// ADC No.5 "A?" DAC Parameter Repry //
+//typedef struct st_PulseW_param{
+// int i_sample_interval; // DAC Output Pattern
+// float f_trigger_level;
+// us_trigger_level;
+// int i_pre_trig_point;
+// int i_usec_Pulse_end_time;
+//}ST_PulseW_PARAM;
+//
+//ST_PulseW_PARAM st_p_test_mode_param;
+//
+//------------------------------------------------------------------------------//
+void com_ADC_Table_Param_Send()
+{
+int i_num;
+//bool b_CommadERR=0;
+
+ // 2017.02.22 for Single CH Only CH0 <=> CH1 Exchange
+ sprintf(tx_line,"Pulse Out Check MBED\r\n"); // 2017.02.22 for Single CH Only CH0 P,20,21 CH1= P19,22
+ //2016.06.21 for MBED Dose Measure 2CH_2Range Title & Ver Send Append
+ // sprintf(tx_line,"MBED Dose Measure Ver0.45\r\n"); // 2016.06.21 for Max.Min Detect Remove & Title&Software Ver Reply Append
+ send_line();
+
+ // i_num = ( st_p_test_mode_param.i_sample_interval ) ;
+ // sprintf(tx_line,"SMP %4d[= x 0.2usec]\r\n",i_num);
+ // send_line();
+ // sprintf(tx_line," \r\n",i_num);
+ // send_line();
+ sprintf(tx_line,"msec Pulse Test Command & Parameter \r\n");
+ send_line();
+ i_num = ( st_p_test_mode_param.i_PulseTestEnable ) ;
+ sprintf(tx_line," MPT: %1d[= P21 Reply Check ]\r\n",i_num);
+ send_line();
+
+ sprintf(tx_line," MF1:P30 MX1:P29 Pulse 1shot PW=MPW x0.1msec PulseOut\r\n");
+ send_line();
+ sprintf(tx_line," MFN: P30 MXN: P29 Pulse Out Repeat\r\n");
+ send_line();
+ sprintf(tx_line," MTN: ON/OFF P29&30 Repeat Check \r\n");
+ send_line();
+ sprintf(tx_line," Pulse Width :MPW %4d[= x 0.1msec]\r\n",st_p_test_mode_param.i_msec_Pulse_width);
+ send_line();
+ sprintf(tx_line," Pulse Interval :MPI %4d[= x 0.1msec]\r\n",st_p_test_mode_param.i_msec_Pulse_Interval);
+ send_line();
+ sprintf(tx_line," Pulse Repeat Count :MPC %4d Count \r\n",st_p_test_mode_param.i_msec_Pulse_RepCnt);
+ send_line();
+ sprintf(tx_line," OFF-ONP30-P29Wait :MTW %4d Count \r\n",st_p_test_mode_param.i_msec_Pulse_OnOffWait);
+ send_line();
+
+ sprintf(tx_line,"for Debug Test \r\n");
+ send_line();
+
+ sprintf(tx_line,"usec Short Pulse Test Command & Parameter \r\n");
+ send_line();
+ sprintf(tx_line," UF1:P30 UX1:P29 Pulse 1shot PW=UPW x0.2usec PulseOut\r\n");
+ send_line();
+ sprintf(tx_line," UFN: P30 UXN: P29 Pulse Out Repeat n\r\n");
+ send_line();
+ sprintf(tx_line," Pulse Width :UPW %4d[= x 0.2usec]\r\n",st_p_test_mode_param.i_usec_Pulse_width);
+ send_line();
+ sprintf(tx_line," Pulse Interval :UPI %4d[= x 0.2usec]\r\n",st_p_test_mode_param.i_usec_Pulse_Interval);
+ send_line();
+ sprintf(tx_line," Pulse Repeat Count :UPC %4d Count \r\n",st_p_test_mode_param.i_usec_Pulse_RepCnt);
+ send_line();
+ // return(b_CommadERR);
+
+ // for Debug
+
+}
+//------------------------------------------------------------------------------//
+// ADC No.7 "LED 1" Devug LED Active 0 / 1
+//------------------------------------------------------------------------------//
+bool com_Check_LED(int i_RecCharCount)
+{
+bool b_CommadERR=0;
+int i_num=0;
+char *pt_comRec;
+
+ if(i_RecCharCount < 4){
+ b_CommadERR = 1;
+ }
+ else{
+ pt_comRec = (char *)&rx_line[3];
+ i_num = atoi(pt_comRec);
+ if(i_num == 0){
+ i_LED_Active = Debug_LED_Disable; // Disable
+ led1=led2=led3=led4=0;
+ }
+ else if(i_num == 1){
+ i_LED_Active = Debug_LED_Active; // Debug LED Active
+ led1=led2=led3=led4=0;
+ }
+ else{
+ b_CommadERR = 1;
+ }
+ }
+ return(b_CommadERR);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////
+
+
+//------------------------------------------------------------------------------//
+//------------------------------------------------------------------------------//
+//----- Serial tx/rx Communication
+//------------------------------------------------------------------------------//
+// Copy tx line buffer to large tx buffer for tx interrupt routine
+void send_line() {
+ int i;
+ char temp_char;
+ bool empty;
+ i = 0;
+// Start Critical Section - don't interrupt while changing global buffer variables
+ NVIC_DisableIRQ(UART1_IRQn);
+ empty = (tx_in == tx_out);
+ while ((i==0) || (tx_line[i-1] != '\n')) {
+// Wait if buffer full
+ if (((tx_in + 1) % ser_buffer_size) == tx_out) {
+// End Critical Section - need to let interrupt routine empty buffer by sending
+ NVIC_EnableIRQ(UART1_IRQn);
+ while (((tx_in + 1) % ser_buffer_size) == tx_out) {
+ }
+// Start Critical Section - don't interrupt while changing global buffer variables
+ NVIC_DisableIRQ(UART1_IRQn);
+ }
+ tx_buffer[tx_in] = tx_line[i];
+ i++;
+ tx_in = (tx_in + 1) % ser_buffer_size;
+ }
+ if (device.writeable() && (empty)) {
+ temp_char = tx_buffer[tx_out];
+ tx_out = (tx_out + 1) % ser_buffer_size;
+// Send first character to start tx interrupts, if stopped
+ device.putc(temp_char);
+ }
+// End Critical Section
+ NVIC_EnableIRQ(UART1_IRQn);
+ return;
+}
+
+// Read a line from the large rx buffer from rx interrupt routine
+// 2013.08.08 H.Tsunemoto
+// Append Return Chear Number
+int read_line(){
+//void read_line() {
+ int i;
+ i = 0;
+ // Start Critical Section - don't interrupt while changing global buffer variables
+ NVIC_DisableIRQ(UART1_IRQn);
+ while(rx_in != rx_out){
+ rx_line[i] = rx_buffer[rx_out];
+ rx_out = (rx_out + 1) % ser_buffer_size;
+ if((rx_line[i] == '\r') || (rx_line[i] == '\n')){
+ break;
+ }
+ i++;
+
+ }
+ rx_line[i] = 0;
+// End Critical Section
+ NVIC_EnableIRQ(UART1_IRQn);
+ return(i);
+}
+
+// Interupt Routine to read in data from serial port
+void Rx_interrupt() {
+ // led1=1;
+// Loop just in case more than one character is in UART's receive FIFO buffer
+// Stop if buffer full
+ while ((device.readable()) || (((rx_in + 1) % ser_buffer_size) == rx_out)) {
+ rx_buffer[rx_in] = device.getc();
+// Uncomment to Echo to USB serial to watch data flow
+// monitor_device.putc(rx_buffer[rx_in]);
+ //-------- 2016.05.23 Tsunemoto --------------//
+ //-------- 小文字 ＝＞ 大文字 変換-------------//
+ if((rx_buffer[rx_in] >= 'a') && (rx_buffer[rx_in] <= 'z')){
+ rx_buffer[rx_in] -= 0x20; // 'a'0x62 => 'A'0x42
+ }
+ //------- 2013.08.08 Tsunemoto ------------//
+ // -- Char CR Rec Counter ----//
+ if((rx_buffer[rx_in]== '\r') || (rx_buffer[rx_in]== '\n')){
+ //led2 = 1;
+ rx_cr_Rec ++;
+ }
+ //----------------------------//
+ rx_in = (rx_in + 1) % ser_buffer_size;
+ }
+// led1=0;
+ return;
+}
+
+// Interupt Routine to write out data to serial port
+void Tx_interrupt() {
+ //led2=1;
+// Loop to fill more than one character in UART's transmit FIFO buffer
+// Stop if buffer empty
+ while ((device.writeable()) && (tx_in != tx_out)) {
+ device.putc(tx_buffer[tx_out]);
+ tx_out = (tx_out + 1) % ser_buffer_size;
+ if(i_LED_Active == Debug_LED_Active){
+ led1 = 1;
+ led1 = 0;
+ }
+ }
+ //led2=0;
+ return;
+}
+//----------------------------------------------------------------------------------//
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed.bld Tue May 29 02:41:54 2018 +0000 @@ -0,0 +1,1 @@ +http://mbed.org/users/mbed_official/code/mbed/builds/63cdd78b2dc1 \ No newline at end of file