Hideharu Tsunemoto / Mbed 2 deprecated MBED_TestPulse_Xray_Cont_20180517

MBED_LPC1768_Test Pulse msec/usec Interval Output P29/P30 & Input P21 Status Send USB Serial Log

Dependencies:   mbed

MODDMA/SETUP.cpp@0:47c1b6a0c166, 2018-05-29 (annotated)

Committer:
H_Tsunemoto
Date:
Tue May 29 02:41:54 2018 +0000
Revision:
0:47c1b6a0c166
Pulse On/OFF OutPut P29/P30 & Rep Input P21 Status Output USBSerial;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
H_Tsunemoto 0:47c1b6a0c166 1 /*
H_Tsunemoto 0:47c1b6a0c166 2 Copyright (c) 2010 Andy Kirkham
H_Tsunemoto 0:47c1b6a0c166 3
H_Tsunemoto 0:47c1b6a0c166 4 Permission is hereby granted, free of charge, to any person obtaining a copy
H_Tsunemoto 0:47c1b6a0c166 5 of this software and associated documentation files (the "Software"), to deal
H_Tsunemoto 0:47c1b6a0c166 6 in the Software without restriction, including without limitation the rights
H_Tsunemoto 0:47c1b6a0c166 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
H_Tsunemoto 0:47c1b6a0c166 8 copies of the Software, and to permit persons to whom the Software is
H_Tsunemoto 0:47c1b6a0c166 9 furnished to do so, subject to the following conditions:
H_Tsunemoto 0:47c1b6a0c166 10
H_Tsunemoto 0:47c1b6a0c166 11 The above copyright notice and this permission notice shall be included in
H_Tsunemoto 0:47c1b6a0c166 12 all copies or substantial portions of the Software.
H_Tsunemoto 0:47c1b6a0c166 13
H_Tsunemoto 0:47c1b6a0c166 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
H_Tsunemoto 0:47c1b6a0c166 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
H_Tsunemoto 0:47c1b6a0c166 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
H_Tsunemoto 0:47c1b6a0c166 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
H_Tsunemoto 0:47c1b6a0c166 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
H_Tsunemoto 0:47c1b6a0c166 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
H_Tsunemoto 0:47c1b6a0c166 20 THE SOFTWARE.
H_Tsunemoto 0:47c1b6a0c166 21 */
H_Tsunemoto 0:47c1b6a0c166 22
H_Tsunemoto 0:47c1b6a0c166 23 #include "MODDMA.h"
H_Tsunemoto 0:47c1b6a0c166 24
H_Tsunemoto 0:47c1b6a0c166 25 namespace AjK {
H_Tsunemoto 0:47c1b6a0c166 26
H_Tsunemoto 0:47c1b6a0c166 27 uint32_t
H_Tsunemoto 0:47c1b6a0c166 28 MODDMA::Setup(MODDMA_Config *config)
H_Tsunemoto 0:47c1b6a0c166 29 {
H_Tsunemoto 0:47c1b6a0c166 30 LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( config->channelNum() );
H_Tsunemoto 0:47c1b6a0c166 31
H_Tsunemoto 0:47c1b6a0c166 32 setups[config->channelNum() & 0x7] = config;
H_Tsunemoto 0:47c1b6a0c166 33
H_Tsunemoto 0:47c1b6a0c166 34 // Reset the Interrupt status
H_Tsunemoto 0:47c1b6a0c166 35 LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );
H_Tsunemoto 0:47c1b6a0c166 36 LPC_GPDMA->DMACIntErrClr = IntErrClr_Ch ( config->channelNum() );
H_Tsunemoto 0:47c1b6a0c166 37
H_Tsunemoto 0:47c1b6a0c166 38 // Clear DMA configure
H_Tsunemoto 0:47c1b6a0c166 39 pChannel->DMACCControl = 0x00;
H_Tsunemoto 0:47c1b6a0c166 40 pChannel->DMACCConfig = 0x00;
H_Tsunemoto 0:47c1b6a0c166 41
H_Tsunemoto 0:47c1b6a0c166 42 // Assign Linker List Item value
H_Tsunemoto 0:47c1b6a0c166 43 pChannel->DMACCLLI = config->dmaLLI();
H_Tsunemoto 0:47c1b6a0c166 44
H_Tsunemoto 0:47c1b6a0c166 45 // Set value to Channel Control Registers
H_Tsunemoto 0:47c1b6a0c166 46 switch (config->transferType()) {
H_Tsunemoto 0:47c1b6a0c166 47
H_Tsunemoto 0:47c1b6a0c166 48 // Memory to memory
H_Tsunemoto 0:47c1b6a0c166 49 case m2m:
H_Tsunemoto 0:47c1b6a0c166 50 // Assign physical source and destination address
H_Tsunemoto 0:47c1b6a0c166 51 pChannel->DMACCSrcAddr = config->srcMemAddr();
H_Tsunemoto 0:47c1b6a0c166 52 pChannel->DMACCDestAddr = config->dstMemAddr();
H_Tsunemoto 0:47c1b6a0c166 53 pChannel->DMACCControl
H_Tsunemoto 0:47c1b6a0c166 54 = CxControl_TransferSize(config->transferSize())
H_Tsunemoto 0:47c1b6a0c166 55 | CxControl_SBSize(_32)
H_Tsunemoto 0:47c1b6a0c166 56 | CxControl_DBSize(_32)
H_Tsunemoto 0:47c1b6a0c166 57 | CxControl_SWidth(config->transferWidth())
H_Tsunemoto 0:47c1b6a0c166 58 | CxControl_DWidth(config->transferWidth())
H_Tsunemoto 0:47c1b6a0c166 59 | CxControl_SI()
H_Tsunemoto 0:47c1b6a0c166 60 | CxControl_DI()
H_Tsunemoto 0:47c1b6a0c166 61 | CxControl_I();
H_Tsunemoto 0:47c1b6a0c166 62 break;
H_Tsunemoto 0:47c1b6a0c166 63
H_Tsunemoto 0:47c1b6a0c166 64 // Memory to peripheral
H_Tsunemoto 0:47c1b6a0c166 65 case m2p:
H_Tsunemoto 0:47c1b6a0c166 66 // Assign physical source
H_Tsunemoto 0:47c1b6a0c166 67 pChannel->DMACCSrcAddr = config->srcMemAddr();
H_Tsunemoto 0:47c1b6a0c166 68 // Assign peripheral destination address
H_Tsunemoto 0:47c1b6a0c166 69 pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
H_Tsunemoto 0:47c1b6a0c166 70 pChannel->DMACCControl
H_Tsunemoto 0:47c1b6a0c166 71 = CxControl_TransferSize((uint32_t)config->transferSize())
H_Tsunemoto 0:47c1b6a0c166 72 | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 73 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 74 | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 75 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 76 | CxControl_SI()
H_Tsunemoto 0:47c1b6a0c166 77 | CxControl_I();
H_Tsunemoto 0:47c1b6a0c166 78 break;
H_Tsunemoto 0:47c1b6a0c166 79
H_Tsunemoto 0:47c1b6a0c166 80 // Peripheral to memory
H_Tsunemoto 0:47c1b6a0c166 81 case p2m:
H_Tsunemoto 0:47c1b6a0c166 82 // Assign peripheral source address
H_Tsunemoto 0:47c1b6a0c166 83 pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
H_Tsunemoto 0:47c1b6a0c166 84 // Assign memory destination address
H_Tsunemoto 0:47c1b6a0c166 85 pChannel->DMACCDestAddr = config->dstMemAddr();
H_Tsunemoto 0:47c1b6a0c166 86 pChannel->DMACCControl
H_Tsunemoto 0:47c1b6a0c166 87 = CxControl_TransferSize((uint32_t)config->transferSize())
H_Tsunemoto 0:47c1b6a0c166 88 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 89 | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 90 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 91 | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 92 | CxControl_DI()
H_Tsunemoto 0:47c1b6a0c166 93 | CxControl_I();
H_Tsunemoto 0:47c1b6a0c166 94 break;
H_Tsunemoto 0:47c1b6a0c166 95
H_Tsunemoto 0:47c1b6a0c166 96 // Peripheral to peripheral
H_Tsunemoto 0:47c1b6a0c166 97 case p2p:
H_Tsunemoto 0:47c1b6a0c166 98 // Assign peripheral source address
H_Tsunemoto 0:47c1b6a0c166 99 pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
H_Tsunemoto 0:47c1b6a0c166 100 // Assign peripheral destination address
H_Tsunemoto 0:47c1b6a0c166 101 pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
H_Tsunemoto 0:47c1b6a0c166 102 pChannel->DMACCControl
H_Tsunemoto 0:47c1b6a0c166 103 = CxControl_TransferSize((uint32_t)config->transferSize())
H_Tsunemoto 0:47c1b6a0c166 104 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 105 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 106 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 107 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 108 | CxControl_I();
H_Tsunemoto 0:47c1b6a0c166 109 break;
H_Tsunemoto 0:47c1b6a0c166 110
H_Tsunemoto 0:47c1b6a0c166 111 // GPIO to memory
H_Tsunemoto 0:47c1b6a0c166 112 case g2m:
H_Tsunemoto 0:47c1b6a0c166 113 // Assign GPIO source address
H_Tsunemoto 0:47c1b6a0c166 114 pChannel->DMACCSrcAddr = config->srcMemAddr();
H_Tsunemoto 0:47c1b6a0c166 115 // Assign memory destination address
H_Tsunemoto 0:47c1b6a0c166 116 pChannel->DMACCDestAddr = config->dstMemAddr();
H_Tsunemoto 0:47c1b6a0c166 117 pChannel->DMACCControl
H_Tsunemoto 0:47c1b6a0c166 118 = CxControl_TransferSize((uint32_t)config->transferSize())
H_Tsunemoto 0:47c1b6a0c166 119 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 120 | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 121 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 122 | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn()))
H_Tsunemoto 0:47c1b6a0c166 123 | CxControl_DI()
H_Tsunemoto 0:47c1b6a0c166 124 | CxControl_I();
H_Tsunemoto 0:47c1b6a0c166 125 break;
H_Tsunemoto 0:47c1b6a0c166 126
H_Tsunemoto 0:47c1b6a0c166 127 // Memory to GPIO
H_Tsunemoto 0:47c1b6a0c166 128 case m2g:
H_Tsunemoto 0:47c1b6a0c166 129 // Assign physical source
H_Tsunemoto 0:47c1b6a0c166 130 pChannel->DMACCSrcAddr = config->srcMemAddr();
H_Tsunemoto 0:47c1b6a0c166 131 // Assign peripheral destination address
H_Tsunemoto 0:47c1b6a0c166 132 pChannel->DMACCDestAddr = config->dstMemAddr();
H_Tsunemoto 0:47c1b6a0c166 133 pChannel->DMACCControl
H_Tsunemoto 0:47c1b6a0c166 134 = CxControl_TransferSize((uint32_t)config->transferSize())
H_Tsunemoto 0:47c1b6a0c166 135 | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 136 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 137 | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 138 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
H_Tsunemoto 0:47c1b6a0c166 139 | CxControl_SI()
H_Tsunemoto 0:47c1b6a0c166 140 | CxControl_I();
H_Tsunemoto 0:47c1b6a0c166 141 break;
H_Tsunemoto 0:47c1b6a0c166 142
H_Tsunemoto 0:47c1b6a0c166 143 // Do not support any more transfer type, return ERROR
H_Tsunemoto 0:47c1b6a0c166 144 default:
H_Tsunemoto 0:47c1b6a0c166 145 return 0;
H_Tsunemoto 0:47c1b6a0c166 146 }
H_Tsunemoto 0:47c1b6a0c166 147
H_Tsunemoto 0:47c1b6a0c166 148 // Re-Configure DMA Request Select for source peripheral
H_Tsunemoto 0:47c1b6a0c166 149 if (config->srcConn() > 15) {
H_Tsunemoto 0:47c1b6a0c166 150 LPC_SC->DMAREQSEL |= (1 << (config->srcConn() - 16));
H_Tsunemoto 0:47c1b6a0c166 151 }
H_Tsunemoto 0:47c1b6a0c166 152 else {
H_Tsunemoto 0:47c1b6a0c166 153 LPC_SC->DMAREQSEL &= ~(1 << (config->srcConn() - 8));
H_Tsunemoto 0:47c1b6a0c166 154 }
H_Tsunemoto 0:47c1b6a0c166 155
H_Tsunemoto 0:47c1b6a0c166 156 // Re-Configure DMA Request Select for destination peripheral
H_Tsunemoto 0:47c1b6a0c166 157 if (config->dstConn() > 15) {
H_Tsunemoto 0:47c1b6a0c166 158 LPC_SC->DMAREQSEL |= (1 << (config->dstConn() - 16));
H_Tsunemoto 0:47c1b6a0c166 159 }
H_Tsunemoto 0:47c1b6a0c166 160 else {
H_Tsunemoto 0:47c1b6a0c166 161 LPC_SC->DMAREQSEL &= ~(1 << (config->dstConn() - 8));
H_Tsunemoto 0:47c1b6a0c166 162 }
H_Tsunemoto 0:47c1b6a0c166 163
H_Tsunemoto 0:47c1b6a0c166 164 // Enable DMA channels, little endian
H_Tsunemoto 0:47c1b6a0c166 165 LPC_GPDMA->DMACConfig = _E;
H_Tsunemoto 0:47c1b6a0c166 166 while (!(LPC_GPDMA->DMACConfig & _E));
H_Tsunemoto 0:47c1b6a0c166 167
H_Tsunemoto 0:47c1b6a0c166 168 // Calculate absolute value for Connection number
H_Tsunemoto 0:47c1b6a0c166 169 uint32_t tmp1 = config->srcConn(); tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
H_Tsunemoto 0:47c1b6a0c166 170 uint32_t tmp2 = config->dstConn(); tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
H_Tsunemoto 0:47c1b6a0c166 171
H_Tsunemoto 0:47c1b6a0c166 172 if (config->dmacSync()) {
H_Tsunemoto 0:47c1b6a0c166 173 uint32_t tmp3 = config->dmacSync(); tmp3 = ((tmp3 > 15) ? (tmp3 - 8) : tmp3);
H_Tsunemoto 0:47c1b6a0c166 174 LPC_GPDMA->DMACSync |= Sync_Src( tmp3 );
H_Tsunemoto 0:47c1b6a0c166 175 }
H_Tsunemoto 0:47c1b6a0c166 176
H_Tsunemoto 0:47c1b6a0c166 177 uint32_t tfer_type = (uint32_t)config->transferType();
H_Tsunemoto 0:47c1b6a0c166 178 if (tfer_type == g2m || tfer_type == m2g) {
H_Tsunemoto 0:47c1b6a0c166 179 tfer_type -= 2; // Adjust psuedo transferType to a real transferType.
H_Tsunemoto 0:47c1b6a0c166 180 }
H_Tsunemoto 0:47c1b6a0c166 181
H_Tsunemoto 0:47c1b6a0c166 182 // Configure DMA Channel, enable Error Counter and Terminate counter
H_Tsunemoto 0:47c1b6a0c166 183 pChannel->DMACCConfig
H_Tsunemoto 0:47c1b6a0c166 184 = CxConfig_IE()
H_Tsunemoto 0:47c1b6a0c166 185 | CxConfig_ITC()
H_Tsunemoto 0:47c1b6a0c166 186 | CxConfig_TransferType(tfer_type)
H_Tsunemoto 0:47c1b6a0c166 187 | CxConfig_SrcPeripheral(tmp1)
H_Tsunemoto 0:47c1b6a0c166 188 | CxConfig_DestPeripheral(tmp2);
H_Tsunemoto 0:47c1b6a0c166 189
H_Tsunemoto 0:47c1b6a0c166 190 return pChannel->DMACCControl;
H_Tsunemoto 0:47c1b6a0c166 191 }
H_Tsunemoto 0:47c1b6a0c166 192
H_Tsunemoto 0:47c1b6a0c166 193 }; // namespace AjK ends
H_Tsunemoto 0:47c1b6a0c166 194