Hideharu Tsunemoto / Mbed 2 deprecated MBED_TestPulse_Xray_Cont_20180517

MBED_LPC1768_Test Pulse msec/usec Interval Output P29/P30 & Input P21 Status Send USB Serial Log

Dependencies:   mbed

MODDMA/DATALUTS.cpp@0:47c1b6a0c166, 2018-05-29 (annotated)

Committer:
H_Tsunemoto
Date:
Tue May 29 02:41:54 2018 +0000
Revision:
0:47c1b6a0c166
Pulse On/OFF OutPut P29/P30 & Rep Input P21 Status Output USBSerial;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
H_Tsunemoto 0:47c1b6a0c166 1 /*
H_Tsunemoto 0:47c1b6a0c166 2 Copyright (c) 2010 Andy Kirkham
H_Tsunemoto 0:47c1b6a0c166 3
H_Tsunemoto 0:47c1b6a0c166 4 Permission is hereby granted, free of charge, to any person obtaining a copy
H_Tsunemoto 0:47c1b6a0c166 5 of this software and associated documentation files (the "Software"), to deal
H_Tsunemoto 0:47c1b6a0c166 6 in the Software without restriction, including without limitation the rights
H_Tsunemoto 0:47c1b6a0c166 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
H_Tsunemoto 0:47c1b6a0c166 8 copies of the Software, and to permit persons to whom the Software is
H_Tsunemoto 0:47c1b6a0c166 9 furnished to do so, subject to the following conditions:
H_Tsunemoto 0:47c1b6a0c166 10
H_Tsunemoto 0:47c1b6a0c166 11 The above copyright notice and this permission notice shall be included in
H_Tsunemoto 0:47c1b6a0c166 12 all copies or substantial portions of the Software.
H_Tsunemoto 0:47c1b6a0c166 13
H_Tsunemoto 0:47c1b6a0c166 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
H_Tsunemoto 0:47c1b6a0c166 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
H_Tsunemoto 0:47c1b6a0c166 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
H_Tsunemoto 0:47c1b6a0c166 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
H_Tsunemoto 0:47c1b6a0c166 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
H_Tsunemoto 0:47c1b6a0c166 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
H_Tsunemoto 0:47c1b6a0c166 20 THE SOFTWARE.
H_Tsunemoto 0:47c1b6a0c166 21 */
H_Tsunemoto 0:47c1b6a0c166 22
H_Tsunemoto 0:47c1b6a0c166 23 #include "MODDMA.h"
H_Tsunemoto 0:47c1b6a0c166 24
H_Tsunemoto 0:47c1b6a0c166 25 #ifndef MBED_H
H_Tsunemoto 0:47c1b6a0c166 26 #include "mbed.h"
H_Tsunemoto 0:47c1b6a0c166 27 #endif
H_Tsunemoto 0:47c1b6a0c166 28
H_Tsunemoto 0:47c1b6a0c166 29 #ifndef MODDMA_CONFIG_H
H_Tsunemoto 0:47c1b6a0c166 30 #include "CONFIG.h"
H_Tsunemoto 0:47c1b6a0c166 31 #endif
H_Tsunemoto 0:47c1b6a0c166 32
H_Tsunemoto 0:47c1b6a0c166 33 namespace AjK {
H_Tsunemoto 0:47c1b6a0c166 34
H_Tsunemoto 0:47c1b6a0c166 35 uint32_t
H_Tsunemoto 0:47c1b6a0c166 36 MODDMA::LUTPerAddr(int n)
H_Tsunemoto 0:47c1b6a0c166 37 {
H_Tsunemoto 0:47c1b6a0c166 38 const uint32_t lut[] = {
H_Tsunemoto 0:47c1b6a0c166 39 (uint32_t)&LPC_SSP0->DR // SSP0 Tx
H_Tsunemoto 0:47c1b6a0c166 40 , (uint32_t)&LPC_SSP0->DR // SSP0 Rx
H_Tsunemoto 0:47c1b6a0c166 41 , (uint32_t)&LPC_SSP1->DR // SSP1 Tx
H_Tsunemoto 0:47c1b6a0c166 42 , (uint32_t)&LPC_SSP1->DR // SSP1 Rx
H_Tsunemoto 0:47c1b6a0c166 43 , (uint32_t)&LPC_ADC->ADGDR // ADC
H_Tsunemoto 0:47c1b6a0c166 44 , (uint32_t)&LPC_I2S->I2STXFIFO // I2S Tx
H_Tsunemoto 0:47c1b6a0c166 45 , (uint32_t)&LPC_I2S->I2SRXFIFO // I2S Rx
H_Tsunemoto 0:47c1b6a0c166 46 , (uint32_t)&LPC_DAC->DACR // DAC
H_Tsunemoto 0:47c1b6a0c166 47 , (uint32_t)&LPC_UART0->THR // UART0 Tx
H_Tsunemoto 0:47c1b6a0c166 48 , (uint32_t)&LPC_UART0->RBR // UART0 Rx
H_Tsunemoto 0:47c1b6a0c166 49 , (uint32_t)&LPC_UART1->THR // UART1 Tx
H_Tsunemoto 0:47c1b6a0c166 50 , (uint32_t)&LPC_UART1->RBR // UART1 Rx
H_Tsunemoto 0:47c1b6a0c166 51 , (uint32_t)&LPC_UART2->THR // UART2 Tx
H_Tsunemoto 0:47c1b6a0c166 52 , (uint32_t)&LPC_UART2->RBR // UART2 Rx
H_Tsunemoto 0:47c1b6a0c166 53 , (uint32_t)&LPC_UART3->THR // UART3 Tx
H_Tsunemoto 0:47c1b6a0c166 54 , (uint32_t)&LPC_UART3->RBR // UART3 Rx
H_Tsunemoto 0:47c1b6a0c166 55 , (uint32_t)&LPC_TIM0->MR0 // MAT0.0
H_Tsunemoto 0:47c1b6a0c166 56 , (uint32_t)&LPC_TIM0->MR1 // MAT0.1
H_Tsunemoto 0:47c1b6a0c166 57 , (uint32_t)&LPC_TIM1->MR0 // MAT1.0
H_Tsunemoto 0:47c1b6a0c166 58 , (uint32_t)&LPC_TIM1->MR1 // MAT1.1
H_Tsunemoto 0:47c1b6a0c166 59 , (uint32_t)&LPC_TIM2->MR0 // MAT2.0
H_Tsunemoto 0:47c1b6a0c166 60 , (uint32_t)&LPC_TIM2->MR1 // MAT2.1
H_Tsunemoto 0:47c1b6a0c166 61 , (uint32_t)&LPC_TIM3->MR0 // MAT3.0
H_Tsunemoto 0:47c1b6a0c166 62 , (uint32_t)&LPC_TIM3->MR1 // MAT3.1
H_Tsunemoto 0:47c1b6a0c166 63 };
H_Tsunemoto 0:47c1b6a0c166 64 return lut[n & 0xFF];
H_Tsunemoto 0:47c1b6a0c166 65 }
H_Tsunemoto 0:47c1b6a0c166 66
H_Tsunemoto 0:47c1b6a0c166 67 uint32_t
H_Tsunemoto 0:47c1b6a0c166 68 MODDMA::Channel_p(int channel)
H_Tsunemoto 0:47c1b6a0c166 69 {
H_Tsunemoto 0:47c1b6a0c166 70 const uint32_t lut[] = {
H_Tsunemoto 0:47c1b6a0c166 71 (uint32_t)LPC_GPDMACH0
H_Tsunemoto 0:47c1b6a0c166 72 , (uint32_t)LPC_GPDMACH1
H_Tsunemoto 0:47c1b6a0c166 73 , (uint32_t)LPC_GPDMACH2
H_Tsunemoto 0:47c1b6a0c166 74 , (uint32_t)LPC_GPDMACH3
H_Tsunemoto 0:47c1b6a0c166 75 , (uint32_t)LPC_GPDMACH4
H_Tsunemoto 0:47c1b6a0c166 76 , (uint32_t)LPC_GPDMACH5
H_Tsunemoto 0:47c1b6a0c166 77 , (uint32_t)LPC_GPDMACH6
H_Tsunemoto 0:47c1b6a0c166 78 , (uint32_t)LPC_GPDMACH7
H_Tsunemoto 0:47c1b6a0c166 79 };
H_Tsunemoto 0:47c1b6a0c166 80 return lut[channel & 0xFF];
H_Tsunemoto 0:47c1b6a0c166 81 }
H_Tsunemoto 0:47c1b6a0c166 82
H_Tsunemoto 0:47c1b6a0c166 83 uint8_t
H_Tsunemoto 0:47c1b6a0c166 84 MODDMA::LUTPerBurst(int n)
H_Tsunemoto 0:47c1b6a0c166 85 {
H_Tsunemoto 0:47c1b6a0c166 86 const uint8_t lut[] = {
H_Tsunemoto 0:47c1b6a0c166 87 (uint8_t)_4 // SSP0 Tx
H_Tsunemoto 0:47c1b6a0c166 88 , (uint8_t)_4 // SSP0 Rx
H_Tsunemoto 0:47c1b6a0c166 89 , (uint8_t)_4 // SSP1 Tx
H_Tsunemoto 0:47c1b6a0c166 90 , (uint8_t)_4 // SSP1 Rx
H_Tsunemoto 0:47c1b6a0c166 91 , (uint8_t)_1 // ADC
H_Tsunemoto 0:47c1b6a0c166 92 , (uint8_t)_32 // I2S channel 0
H_Tsunemoto 0:47c1b6a0c166 93 , (uint8_t)_32 // I2S channel 1
H_Tsunemoto 0:47c1b6a0c166 94 , (uint8_t)_1 // DAC
H_Tsunemoto 0:47c1b6a0c166 95 , (uint8_t)_1 // UART0 Tx
H_Tsunemoto 0:47c1b6a0c166 96 , (uint8_t)_1 // UART0 Rx
H_Tsunemoto 0:47c1b6a0c166 97 , (uint8_t)_1 // UART1 Tx
H_Tsunemoto 0:47c1b6a0c166 98 , (uint8_t)_1 // UART1 Rx
H_Tsunemoto 0:47c1b6a0c166 99 , (uint8_t)_1 // UART2 Tx
H_Tsunemoto 0:47c1b6a0c166 100 , (uint8_t)_1 // UART2 Rx
H_Tsunemoto 0:47c1b6a0c166 101 , (uint8_t)_1 // UART3 Tx
H_Tsunemoto 0:47c1b6a0c166 102 , (uint8_t)_1 // UART3 Rx
H_Tsunemoto 0:47c1b6a0c166 103 , (uint8_t)_1 // MAT0.0
H_Tsunemoto 0:47c1b6a0c166 104 , (uint8_t)_1 // MAT0.1
H_Tsunemoto 0:47c1b6a0c166 105 , (uint8_t)_1 // MAT1.0
H_Tsunemoto 0:47c1b6a0c166 106 , (uint8_t)_1 // MAT1.1
H_Tsunemoto 0:47c1b6a0c166 107 , (uint8_t)_1 // MAT2.0
H_Tsunemoto 0:47c1b6a0c166 108 , (uint8_t)_1 // MAT2.1
H_Tsunemoto 0:47c1b6a0c166 109 , (uint8_t)_1 // MAT3.0
H_Tsunemoto 0:47c1b6a0c166 110 , (uint8_t)_1 // MAT3.1
H_Tsunemoto 0:47c1b6a0c166 111 };
H_Tsunemoto 0:47c1b6a0c166 112 return lut[n & 0xFFF];
H_Tsunemoto 0:47c1b6a0c166 113 }
H_Tsunemoto 0:47c1b6a0c166 114
H_Tsunemoto 0:47c1b6a0c166 115 uint8_t
H_Tsunemoto 0:47c1b6a0c166 116 MODDMA::LUTPerWid(int n)
H_Tsunemoto 0:47c1b6a0c166 117 {
H_Tsunemoto 0:47c1b6a0c166 118 const uint8_t lut[] = {
H_Tsunemoto 0:47c1b6a0c166 119 (uint8_t)byte // SSP0 Tx
H_Tsunemoto 0:47c1b6a0c166 120 , (uint8_t)byte // SSP0 Rx
H_Tsunemoto 0:47c1b6a0c166 121 , (uint8_t)byte // SSP1 Tx
H_Tsunemoto 0:47c1b6a0c166 122 , (uint8_t)byte // SSP1 Rx
H_Tsunemoto 0:47c1b6a0c166 123 , (uint8_t)word // ADC
H_Tsunemoto 0:47c1b6a0c166 124 , (uint8_t)word // I2S channel 0
H_Tsunemoto 0:47c1b6a0c166 125 , (uint8_t)word // I2S channel 1
H_Tsunemoto 0:47c1b6a0c166 126 , (uint8_t)word // DAC
H_Tsunemoto 0:47c1b6a0c166 127 , (uint8_t)byte // UART0 Tx
H_Tsunemoto 0:47c1b6a0c166 128 , (uint8_t)byte // UART0 Rx
H_Tsunemoto 0:47c1b6a0c166 129 , (uint8_t)byte // UART1 Tx
H_Tsunemoto 0:47c1b6a0c166 130 , (uint8_t)byte // UART1 Rx
H_Tsunemoto 0:47c1b6a0c166 131 , (uint8_t)byte // UART2 Tx
H_Tsunemoto 0:47c1b6a0c166 132 , (uint8_t)byte // UART2 Rx
H_Tsunemoto 0:47c1b6a0c166 133 , (uint8_t)byte // UART3 Tx
H_Tsunemoto 0:47c1b6a0c166 134 , (uint8_t)byte // UART3 Rx
H_Tsunemoto 0:47c1b6a0c166 135 , (uint8_t)word // MAT0.0
H_Tsunemoto 0:47c1b6a0c166 136 , (uint8_t)word // MAT0.1
H_Tsunemoto 0:47c1b6a0c166 137 , (uint8_t)word // MAT1.0
H_Tsunemoto 0:47c1b6a0c166 138 , (uint8_t)word // MAT1.1
H_Tsunemoto 0:47c1b6a0c166 139 , (uint8_t)word // MAT2.0
H_Tsunemoto 0:47c1b6a0c166 140 , (uint8_t)word // MAT2.1
H_Tsunemoto 0:47c1b6a0c166 141 , (uint8_t)word // MAT3.0
H_Tsunemoto 0:47c1b6a0c166 142 , (uint8_t)word // MAT3.1
H_Tsunemoto 0:47c1b6a0c166 143 };
H_Tsunemoto 0:47c1b6a0c166 144 return lut[n & 0xFFF];
H_Tsunemoto 0:47c1b6a0c166 145 }
H_Tsunemoto 0:47c1b6a0c166 146
H_Tsunemoto 0:47c1b6a0c166 147 }; // namespace AjK ends