Hideharu Tsunemoto / Mbed 2 deprecated MBED_TestPulse_Xray_Cont_20180517

MBED_LPC1768_Test Pulse msec/usec Interval Output P29/P30 & Input P21 Status Send USB Serial Log

Dependencies:   mbed

MODDMA/iomacros.h@0:47c1b6a0c166, 2018-05-29 (annotated)

Committer:
H_Tsunemoto
Date:
Tue May 29 02:41:54 2018 +0000
Revision:
0:47c1b6a0c166
Pulse On/OFF OutPut P29/P30 & Rep Input P21 Status Output USBSerial;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
H_Tsunemoto 0:47c1b6a0c166 1 /*
H_Tsunemoto 0:47c1b6a0c166 2 Copyright (c) 2011 Andy Kirkham
H_Tsunemoto 0:47c1b6a0c166 3
H_Tsunemoto 0:47c1b6a0c166 4 Permission is hereby granted, free of charge, to any person obtaining a copy
H_Tsunemoto 0:47c1b6a0c166 5 of this software and associated documentation files (the "Software"), to deal
H_Tsunemoto 0:47c1b6a0c166 6 in the Software without restriction, including without limitation the rights
H_Tsunemoto 0:47c1b6a0c166 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
H_Tsunemoto 0:47c1b6a0c166 8 copies of the Software, and to permit persons to whom the Software is
H_Tsunemoto 0:47c1b6a0c166 9 furnished to do so, subject to the following conditions:
H_Tsunemoto 0:47c1b6a0c166 10
H_Tsunemoto 0:47c1b6a0c166 11 The above copyright notice and this permission notice shall be included in
H_Tsunemoto 0:47c1b6a0c166 12 all copies or substantial portions of the Software.
H_Tsunemoto 0:47c1b6a0c166 13
H_Tsunemoto 0:47c1b6a0c166 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
H_Tsunemoto 0:47c1b6a0c166 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
H_Tsunemoto 0:47c1b6a0c166 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
H_Tsunemoto 0:47c1b6a0c166 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
H_Tsunemoto 0:47c1b6a0c166 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
H_Tsunemoto 0:47c1b6a0c166 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
H_Tsunemoto 0:47c1b6a0c166 20 THE SOFTWARE.
H_Tsunemoto 0:47c1b6a0c166 21 */
H_Tsunemoto 0:47c1b6a0c166 22
H_Tsunemoto 0:47c1b6a0c166 23 #ifndef IOMACROS_H
H_Tsunemoto 0:47c1b6a0c166 24 #define IOMACROS_H
H_Tsunemoto 0:47c1b6a0c166 25
H_Tsunemoto 0:47c1b6a0c166 26 #ifndef __LPC17xx_H__
H_Tsunemoto 0:47c1b6a0c166 27 #include "LPC17xx.h"
H_Tsunemoto 0:47c1b6a0c166 28 #endif
H_Tsunemoto 0:47c1b6a0c166 29
H_Tsunemoto 0:47c1b6a0c166 30 #define PIN_PULLUP 0UL
H_Tsunemoto 0:47c1b6a0c166 31 #define PIN_REPEAT 1UL
H_Tsunemoto 0:47c1b6a0c166 32 #define PIN_NONE 2UL
H_Tsunemoto 0:47c1b6a0c166 33 #define PIN_PULLDOWN 3UL
H_Tsunemoto 0:47c1b6a0c166 34
H_Tsunemoto 0:47c1b6a0c166 35 /* p5 is P0.9 */
H_Tsunemoto 0:47c1b6a0c166 36 #define p5_SEL_MASK ~(3UL << 18)
H_Tsunemoto 0:47c1b6a0c166 37 #define p5_SET_MASK (1UL << 9)
H_Tsunemoto 0:47c1b6a0c166 38 #define p5_CLR_MASK ~(p5_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 39 #define p5_AS_OUTPUT LPC_PINCON->PINSEL0&=p5_SEL_MASK;LPC_GPIO0->FIODIR|=p5_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 40 #define p5_AS_INPUT LPC_GPIO0->FIOMASK &= p5_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 41 #define p5_SET LPC_GPIO0->FIOSET = p5_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 42 #define p5_CLR LPC_GPIO0->FIOCLR = p5_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 43 #define p5_IS_SET (bool)(LPC_GPIO0->FIOPIN & p5_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 44 #define p5_IS_CLR !(p5_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 45 #define p5_MODE(x) LPC_PINCON->PINMODE0&=p5_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<18)
H_Tsunemoto 0:47c1b6a0c166 46
H_Tsunemoto 0:47c1b6a0c166 47 /* p6 is P0.8 */
H_Tsunemoto 0:47c1b6a0c166 48 #define p6_SEL_MASK ~(3UL << 16)
H_Tsunemoto 0:47c1b6a0c166 49 #define p6_SET_MASK (1UL << 8)
H_Tsunemoto 0:47c1b6a0c166 50 #define p6_CLR_MASK ~(p6_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 51 #define p6_AS_OUTPUT LPC_PINCON->PINSEL0&=p6_SEL_MASK;LPC_GPIO0->FIODIR|=p6-SET_MASK
H_Tsunemoto 0:47c1b6a0c166 52 #define p6_AS_INPUT LPC_GPIO0->FIOMASK &= p6_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 53 #define p6_SET LPC_GPIO0->FIOSET = p6_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 54 #define p6_CLR LPC_GPIO0->FIOCLR = p6_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 55 #define p6_IS_SET (bool)(LPC_GPIO0->FIOPIN & p6_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 56 #define p6_IS_CLR !(p6_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 57 #define p6_MODE(x) LPC_PINCON->PINMODE0&=p6_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<16)
H_Tsunemoto 0:47c1b6a0c166 58
H_Tsunemoto 0:47c1b6a0c166 59 /* p7 is P0.7 */
H_Tsunemoto 0:47c1b6a0c166 60 #define p7_SEL_MASK ~(3UL << 14)
H_Tsunemoto 0:47c1b6a0c166 61 #define p7_SET_MASK (1UL << 7)
H_Tsunemoto 0:47c1b6a0c166 62 #define p7_CLR_MASK ~(p7_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 63 #define p7_AS_OUTPUT LPC_PINCON->PINSEL0&=p7_SEL_MASK;LPC_GPIO0->FIODIR|=p7_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 64 #define p7_AS_INPUT LPC_GPIO0->FIOMASK &= p7_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 65 #define p7_SET LPC_GPIO0->FIOSET = p7_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 66 #define p7_CLR LPC_GPIO0->FIOCLR = p7_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 67 #define p7_IS_SET (bool)(LPC_GPIO0->FIOPIN & p7_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 68 #define p7_IS_CLR !(p7_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 69 #define p7_MODE(x) LPC_PINCON->PINMODE0&=p7_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<14)
H_Tsunemoto 0:47c1b6a0c166 70
H_Tsunemoto 0:47c1b6a0c166 71 /* p8 is P0.6 */
H_Tsunemoto 0:47c1b6a0c166 72 #define p8_SEL_MASK ~(3UL << 12)
H_Tsunemoto 0:47c1b6a0c166 73 #define p8_SET_MASK (1UL << 6)
H_Tsunemoto 0:47c1b6a0c166 74 #define p8_CLR_MASK ~(p8_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 75 #define p8_AS_OUTPUT LPC_PINCON->PINSEL0&=p8_SEL_MASK;LPC_GPIO0->FIODIR|=p8_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 76 #define p8_AS_INPUT LPC_GPIO0->FIOMASK &= p8_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 77 #define p8_SET LPC_GPIO0->FIOSET = p8_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 78 #define p8_CLR LPC_GPIO0->FIOCLR = p8_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 79 #define p8_IS_SET (bool)(LPC_GPIO0->FIOPIN & p8_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 80 #define p8_IS_CLR !(p8_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 81 #define p8_MODE(x) LPC_PINCON->PINMODE0&=p8_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<12)
H_Tsunemoto 0:47c1b6a0c166 82
H_Tsunemoto 0:47c1b6a0c166 83 /* p9 is P0.0 */
H_Tsunemoto 0:47c1b6a0c166 84 #define p9_SEL_MASK ~(3UL << 0)
H_Tsunemoto 0:47c1b6a0c166 85 #define p9_SET_MASK (1UL << 0)
H_Tsunemoto 0:47c1b6a0c166 86 #define p9_CLR_MASK ~(p9_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 87 #define p9_AS_OUTPUT LPC_PINCON->PINSEL0&=p9_SEL_MASK;LPC_GPIO0->FIODIR|=p9_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 88 #define p9_AS_INPUT LPC_GPIO0->FIOMASK &= p9_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 89 #define p9_SET LPC_GPIO0->FIOSET = p9_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 90 #define p9_CLR LPC_GPIO0->FIOCLR = p9_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 91 #define p9_IS_SET (bool)(LPC_GPIO0->FIOPIN & p9_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 92 #define p9_IS_CLR !(p9_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 93 #define p9_MODE(x) LPC_PINCON->PINMODE0&=p9_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<0)
H_Tsunemoto 0:47c1b6a0c166 94
H_Tsunemoto 0:47c1b6a0c166 95 /* p10 is P0.1 */
H_Tsunemoto 0:47c1b6a0c166 96 #define p10_SEL_MASK ~(3UL << 2)
H_Tsunemoto 0:47c1b6a0c166 97 #define p10_SET_MASK (1UL << 1)
H_Tsunemoto 0:47c1b6a0c166 98 #define p10_CLR_MASK ~(p10_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 99 #define p10_AS_OUTPUT LPC_PINCON->PINSEL0&=p10_SEL_MASK;LPC_GPIO0->FIODIR|=p10_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 100 #define p10_AS_INPUT LPC_GPIO0->FIOMASK &= p10_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 101 #define p10_SET LPC_GPIO0->FIOSET = p10_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 102 #define p10_CLR LPC_GPIO0->FIOCLR = p10_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 103 #define p10_IS_SET (bool)(LPC_GPIO0->FIOPIN & p10_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 104 #define p10_IS_CLR !(p10_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 105 #define p10_MODE(x) LPC_PINCON->PINMODE0&=p10_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<2)
H_Tsunemoto 0:47c1b6a0c166 106
H_Tsunemoto 0:47c1b6a0c166 107 /* p11 is P0.18 */
H_Tsunemoto 0:47c1b6a0c166 108 #define p11_SEL_MASK ~(3UL << 4)
H_Tsunemoto 0:47c1b6a0c166 109 #define p11_SET_MASK (1UL << 18)
H_Tsunemoto 0:47c1b6a0c166 110 #define p11_CLR_MASK ~(p11_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 111 #define p11_AS_OUTPUT LPC_PINCON->PINSEL1&=p11_SEL_MASK;LPC_GPIO0->FIODIR|=p11_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 112 #define p11_AS_INPUT LPC_GPIO0->FIOMASK &= p11_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 113 #define p11_SET LPC_GPIO0->FIOSET = p11_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 114 #define p11_CLR LPC_GPIO0->FIOCLR = p11_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 115 #define p11_IS_SET (bool)(LPC_GPIO0->FIOPIN & p11_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 116 #define p11_IS_CLR !(p11_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 117 #define p11_MODE(x) LPC_PINCON->PINMODE1&=p11_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<4)
H_Tsunemoto 0:47c1b6a0c166 118
H_Tsunemoto 0:47c1b6a0c166 119 /* p12 is P0.17 */
H_Tsunemoto 0:47c1b6a0c166 120 #define p12_SEL_MASK ~(3UL << 2)
H_Tsunemoto 0:47c1b6a0c166 121 #define p12_SET_MASK (1UL << 17)
H_Tsunemoto 0:47c1b6a0c166 122 #define p12_CLR_MASK ~(p12_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 123 #define p12_AS_OUTPUT LPC_PINCON->PINSEL1&=p12_SEL_MASK;LPC_GPIO0->FIODIR|=p12_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 124 #define p12_AS_INPUT LPC_GPIO0->FIOMASK &= p12_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 125 #define p12_SET LPC_GPIO0->FIOSET = p12_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 126 #define p12_CLR LPC_GPIO0->FIOCLR = p12_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 127 #define p12_IS_SET (bool)(LPC_GPIO0->FIOPIN & p12_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 128 #define p12_IS_CLR !(p12_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 129 #define p12_MODE(x) LPC_PINCON->PINMODE1&=p12_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<2)
H_Tsunemoto 0:47c1b6a0c166 130
H_Tsunemoto 0:47c1b6a0c166 131 /* p13 is P0.15 */
H_Tsunemoto 0:47c1b6a0c166 132 #define p13_SEL_MASK ~(3UL << 30)
H_Tsunemoto 0:47c1b6a0c166 133 #define p13_SET_MASK (1UL << 15)
H_Tsunemoto 0:47c1b6a0c166 134 #define p13_CLR_MASK ~(p13_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 135 #define p13_AS_OUTPUT LPC_PINCON->PINSEL0&=p13_SEL_MASK;LPC_GPIO0->FIODIR|=p13_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 136 #define p13_AS_INPUT LPC_GPIO0->FIOMASK &= p13_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 137 #define p13_SET LPC_GPIO0->FIOSET = p13_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 138 #define p13_CLR LPC_GPIO0->FIOCLR = p13_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 139 #define p13_IS_SET (bool)(LPC_GPIO0->FIOPIN & p13_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 140 #define p13_IS_CLR !(p13_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 141 #define p13_MODE(x) LPC_PINCON->PINMODE0&=p13_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<30)
H_Tsunemoto 0:47c1b6a0c166 142
H_Tsunemoto 0:47c1b6a0c166 143 /* p14 is P0.16 */
H_Tsunemoto 0:47c1b6a0c166 144 #define p14_SEL_MASK ~(3UL << 0)
H_Tsunemoto 0:47c1b6a0c166 145 #define p14_SET_MASK (1UL << 16)
H_Tsunemoto 0:47c1b6a0c166 146 #define p14_CLR_MASK ~(p14_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 147 #define p14_AS_OUTPUT LPC_PINCON->PINSEL1&=p14_SEL_MASK;LPC_GPIO0->FIODIR|=p14_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 148 #define p14_AS_INPUT LPC_GPIO0->FIOMASK &= p14_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 149 #define p14_SET LPC_GPIO0->FIOSET = p14_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 150 #define p14_CLR LPC_GPIO0->FIOCLR = p14_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 151 #define p14_IS_SET (bool)(LPC_GPIO0->FIOPIN & p14_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 152 #define p14_IS_CLR !(p14_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 153 #define p14_MODE(x) LPC_PINCON->PINMODE1&=p14_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<0)
H_Tsunemoto 0:47c1b6a0c166 154
H_Tsunemoto 0:47c1b6a0c166 155 /* p15 is P0.23 */
H_Tsunemoto 0:47c1b6a0c166 156 #define p15_SEL_MASK ~(3UL << 14)
H_Tsunemoto 0:47c1b6a0c166 157 #define p15_SET_MASK (1UL << 23)
H_Tsunemoto 0:47c1b6a0c166 158 #define p15_CLR_MASK ~(p15_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 159 #define p15_AS_OUTPUT LPC_PINCON->PINSEL1&=p15_SEL_MASK;LPC_GPIO0->FIODIR|=p15_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 160 #define p15_AS_INPUT LPC_GPIO0->FIOMASK &= p15_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 161 #define p15_SET LPC_GPIO0->FIOSET = p15_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 162 #define p15_CLR LPC_GPIO0->FIOCLR = p15_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 163 #define p15_IS_SET (bool)(LPC_GPIO0->FIOPIN & p15_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 164 #define p15_IS_CLR !(p15_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 165 #define p15_MODE(x) LPC_PINCON->PINMODE1&=p15_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<14)
H_Tsunemoto 0:47c1b6a0c166 166
H_Tsunemoto 0:47c1b6a0c166 167 /* p16 is P0.24 */
H_Tsunemoto 0:47c1b6a0c166 168 #define p16_SEL_MASK ~(3UL << 16)
H_Tsunemoto 0:47c1b6a0c166 169 #define p16_SET_MASK (1UL << 24)
H_Tsunemoto 0:47c1b6a0c166 170 #define p16_CLR_MASK ~(p16_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 171 #define p16_AS_OUTPUT LPC_PINCON->PINSEL1&=p16_SEL_MASK;LPC_GPIO0->FIODIR|=p16_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 172 #define p16_AS_INPUT LPC_GPIO0->FIOMASK &= p16_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 173 #define p16_SET LPC_GPIO0->FIOSET = p16_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 174 #define p16_CLR LPC_GPIO0->FIOCLR = p16_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 175 #define p16_IS_SET (bool)(LPC_GPIO0->FIOPIN & p16_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 176 #define p16_IS_CLR !(p16_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 177 #define p16_MODE(x) LPC_PINCON->PINMODE1&=p16_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<16)
H_Tsunemoto 0:47c1b6a0c166 178
H_Tsunemoto 0:47c1b6a0c166 179 /* p17 is P0.25 */
H_Tsunemoto 0:47c1b6a0c166 180 #define p17_SEL_MASK ~(3UL << 18)
H_Tsunemoto 0:47c1b6a0c166 181 #define p17_SET_MASK (1UL << 25)
H_Tsunemoto 0:47c1b6a0c166 182 #define p17_CLR_MASK ~(p17_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 183 #define p17_AS_OUTPUT LPC_PINCON->PINSEL1&=p17_SEL_MASK;LPC_GPIO0->FIODIR|=p17_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 184 #define p17_AS_INPUT LPC_GPIO0->FIOMASK &= p17_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 185 #define p17_SET LPC_GPIO0->FIOSET = p17_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 186 #define p17_CLR LPC_GPIO0->FIOCLR = p17_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 187 #define p17_IS_SET (bool)(LPC_GPIO0->FIOPIN & p17_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 188 #define p17_IS_CLR !(p17_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 189 #define p17_MODE(x) LPC_PINCON->PINMODE1&=p17_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<18)
H_Tsunemoto 0:47c1b6a0c166 190
H_Tsunemoto 0:47c1b6a0c166 191 /* p18 is P0.26 */
H_Tsunemoto 0:47c1b6a0c166 192 #define p18_SEL_MASK ~(3UL << 20)
H_Tsunemoto 0:47c1b6a0c166 193 #define p18_SET_MASK (1UL << 26)
H_Tsunemoto 0:47c1b6a0c166 194 #define p18_CLR_MASK ~(p18_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 195 #define p18_AS_OUTPUT LPC_PINCON->PINSEL1&=p18_SEL_MASK;LPC_GPIO0->FIODIR|=p18_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 196 #define p18_AS_INPUT LPC_GPIO0->FIOMASK &= p18_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 197 #define p18_SET LPC_GPIO0->FIOSET = p18_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 198 #define p18_CLR LPC_GPIO0->FIOCLR = p18_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 199 #define p18_IS_SET (bool)(LPC_GPIO0->FIOPIN & p18_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 200 #define p18_IS_CLR !(p18_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 201 #define p18_MODE(x) LPC_PINCON->PINMODE1&=p18_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<20)
H_Tsunemoto 0:47c1b6a0c166 202
H_Tsunemoto 0:47c1b6a0c166 203 /* p19 is P1.30 */
H_Tsunemoto 0:47c1b6a0c166 204 #define p19_SEL_MASK ~(3UL << 28)
H_Tsunemoto 0:47c1b6a0c166 205 #define p19_SET_MASK (1UL << 30)
H_Tsunemoto 0:47c1b6a0c166 206 #define p19_AS_OUTPUT LPC_PINCON->PINSEL3&=p19_SEL_MASK;LPC_GPIO1->FIODIR|=p19_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 207 #define p19_AS_INPUT LPC_GPIO1->FIOMASK &= p19_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 208 #define p19_SET LPC_GPIO1->FIOSET = p19_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 209 #define p19_CLR LPC_GPIO1->FIOCLR = p19_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 210 #define p19_IS_SET (bool)(LPC_GPIO1->FIOPIN & p19_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 211 #define p19_IS_CLR !(p19_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 212 #define p19_MODE(x) LPC_PINCON->PINMODE3&=p19_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<28)
H_Tsunemoto 0:47c1b6a0c166 213
H_Tsunemoto 0:47c1b6a0c166 214 /* p20 is P1.31 */
H_Tsunemoto 0:47c1b6a0c166 215 #define p20_SEL_MASK ~(3UL << 30)
H_Tsunemoto 0:47c1b6a0c166 216 #define p20_SET_MASK (1UL << 31)
H_Tsunemoto 0:47c1b6a0c166 217 #define p20_CLR_MASK ~(p20_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 218 #define p20_AS_OUTPUT LPC_PINCON->PINSEL3&=p20_SEL_MASK;LPC_GPIO1->FIODIR|=p20_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 219 #define p20_AS_INPUT LPC_GPIO1->FIOMASK &= p20_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 220 #define p20_SET LPC_GPIO1->FIOSET = p20_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 221 #define p20_CLR LPC_GPIO1->FIOCLR = p20_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 222 #define p20_IS_SET (bool)(LPC_GPIO1->FIOPIN & p20_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 223 #define p20_IS_CLR !(p20_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 224 #define p20_MODE(x) LPC_PINCON->PINMODE3&=p20_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<30)
H_Tsunemoto 0:47c1b6a0c166 225
H_Tsunemoto 0:47c1b6a0c166 226 /* p21 is P2.5 */
H_Tsunemoto 0:47c1b6a0c166 227 #define p21_SEL_MASK ~(3UL << 10)
H_Tsunemoto 0:47c1b6a0c166 228 #define p21_SET_MASK (1UL << 5)
H_Tsunemoto 0:47c1b6a0c166 229 #define p21_CLR_MASK ~(p21_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 230 #define p21_AS_OUTPUT LPC_PINCON->PINSEL4&=p21_SEL_MASK;LPC_GPIO2->FIODIR|=p21_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 231 #define p21_AS_INPUT LPC_GPIO2->FIOMASK &= p21_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 232 #define p21_SET LPC_GPIO2->FIOSET = p21_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 233 #define p21_CLR LPC_GPIO2->FIOCLR = p21_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 234 #define p21_IS_SET (bool)(LPC_GPIO2->FIOPIN & p21_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 235 #define p21_IS_CLR !(p21_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 236 #define p21_TOGGLE p21_IS_SET?p21_CLR:p21_SET
H_Tsunemoto 0:47c1b6a0c166 237 #define p21_MODE(x) LPC_PINCON->PINMODE4&=p21_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<10)
H_Tsunemoto 0:47c1b6a0c166 238
H_Tsunemoto 0:47c1b6a0c166 239 /* p22 is P2.4 */
H_Tsunemoto 0:47c1b6a0c166 240 #define p22_SEL_MASK ~(3UL << 8)
H_Tsunemoto 0:47c1b6a0c166 241 #define p22_SET_MASK (1UL << 4)
H_Tsunemoto 0:47c1b6a0c166 242 #define p22_CLR_MASK ~(p22_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 243 #define p22_AS_OUTPUT LPC_PINCON->PINSEL4&=p22_SEL_MASK;LPC_GPIO2->FIODIR|=p22_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 244 #define p22_AS_INPUT LPC_GPIO2->FIOMASK &= p22_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 245 #define p22_SET LPC_GPIO2->FIOSET = p22_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 246 #define p22_CLR LPC_GPIO2->FIOCLR = p22_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 247 #define p22_IS_SET (bool)(LPC_GPIO2->FIOPIN & p22_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 248 #define p22_IS_CLR !(p22_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 249 #define p22_TOGGLE p22_IS_SET?p22_CLR:p22_SET
H_Tsunemoto 0:47c1b6a0c166 250 #define p22_MODE(x) LPC_PINCON->PINMODE4&=p22_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<8)
H_Tsunemoto 0:47c1b6a0c166 251
H_Tsunemoto 0:47c1b6a0c166 252 /* p23 is P2.3 */
H_Tsunemoto 0:47c1b6a0c166 253 #define p23_SEL_MASK ~(3UL << 6)
H_Tsunemoto 0:47c1b6a0c166 254 #define p23_SET_MASK (1UL << 3)
H_Tsunemoto 0:47c1b6a0c166 255 #define p23_CLR_MASK ~(p23_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 256 #define p23_AS_OUTPUT LPC_PINCON->PINSEL4&=p23_SEL_MASK;LPC_GPIO2->FIODIR|=p23_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 257 #define p23_AS_INPUT LPC_GPIO2->FIOMASK &= p23_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 258 #define p23_SET LPC_GPIO2->FIOSET = p23_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 259 #define p23_CLR LPC_GPIO2->FIOCLR = p23_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 260 #define p23_IS_SET (bool)(LPC_GPIO2->FIOPIN & p23_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 261 #define p23_IS_CLR !(p23_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 262 #define p23_TOGGLE p23_IS_SET?p23_CLR:p23_SET
H_Tsunemoto 0:47c1b6a0c166 263 #define p23_MODE(x) LPC_PINCON->PINMODE4&=p23_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<6)
H_Tsunemoto 0:47c1b6a0c166 264
H_Tsunemoto 0:47c1b6a0c166 265 /* p24 is P2.2 */
H_Tsunemoto 0:47c1b6a0c166 266 #define p24_SEL_MASK ~(3UL << 4)
H_Tsunemoto 0:47c1b6a0c166 267 #define p24_SET_MASK (1UL << 2)
H_Tsunemoto 0:47c1b6a0c166 268 #define p24_CLR_MASK ~(p24_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 269 #define p24_AS_OUTPUT LPC_PINCON->PINSEL4&=p24_SEL_MASK;LPC_GPIO2->FIODIR|=p24_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 270 #define p24_AS_INPUT LPC_GPIO2->FIOMASK &= p24_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 271 #define p24_SET LPC_GPIO2->FIOSET = p24_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 272 #define p24_CLR LPC_GPIO2->FIOCLR = p24_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 273 #define p24_IS_SET (bool)(LPC_GPIO2->FIOPIN & p24_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 274 #define p24_IS_CLR !(p24_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 275 #define p24_TOGGLE p24_IS_SET?p24_CLR:p24_SET
H_Tsunemoto 0:47c1b6a0c166 276 #define p24_MODE(x) LPC_PINCON->PINMODE4&=p24_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<4)
H_Tsunemoto 0:47c1b6a0c166 277
H_Tsunemoto 0:47c1b6a0c166 278 /* p25 is P2.1 */
H_Tsunemoto 0:47c1b6a0c166 279 #define p25_SEL_MASK ~(3UL << 2)
H_Tsunemoto 0:47c1b6a0c166 280 #define p25_SET_MASK (1UL << 1)
H_Tsunemoto 0:47c1b6a0c166 281 #define p25_CLR_MASK ~(p25_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 282 #define p25_AS_OUTPUT LPC_PINCON->PINSEL4&=p25_SEL_MASK;LPC_GPIO2->FIODIR|=p25_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 283 #define p25_AS_INPUT LPC_GPIO2->FIOMASK &= p25_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 284 #define p25_SET LPC_GPIO2->FIOSET = p25_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 285 #define p25_CLR LPC_GPIO2->FIOCLR = p25_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 286 #define p25_IS_SET (bool)(LPC_GPIO2->FIOPIN & p25_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 287 #define p25_IS_CLR !(p25_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 288 #define p25_MODE(x) LPC_PINCON->PINMODE4&=p25_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<2)
H_Tsunemoto 0:47c1b6a0c166 289
H_Tsunemoto 0:47c1b6a0c166 290 /* p26 is P2.0 */
H_Tsunemoto 0:47c1b6a0c166 291 #define p26_SEL_MASK ~(3UL << 0)
H_Tsunemoto 0:47c1b6a0c166 292 #define p26_SET_MASK (1UL << 0)
H_Tsunemoto 0:47c1b6a0c166 293 #define p26_CLR_MASK ~(p26_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 294 #define p26_AS_OUTPUT LPC_PINCON->PINSEL4&=p26_SEL_MASK;LPC_GPIO2->FIODIR|=p26_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 295 #define p26_AS_INPUT LPC_GPIO2->FIOMASK &= p26_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 296 #define p26_SET LPC_GPIO2->FIOSET = p26_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 297 #define p26_CLR LPC_GPIO2->FIOCLR = p26_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 298 #define p26_IS_SET (bool)(LPC_GPIO2->FIOPIN & p26_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 299 #define p26_IS_CLR !(p26_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 300 #define p26_MODE(x) LPC_PINCON->PINMODE4&=p26_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<0)
H_Tsunemoto 0:47c1b6a0c166 301
H_Tsunemoto 0:47c1b6a0c166 302 /* p27 is P0.11 */
H_Tsunemoto 0:47c1b6a0c166 303 #define p27_SEL_MASK ~(3UL << 22)
H_Tsunemoto 0:47c1b6a0c166 304 #define p27_SET_MASK (1UL << 11)
H_Tsunemoto 0:47c1b6a0c166 305 #define p27_CLR_MASK ~(p27_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 306 #define p27_AS_OUTPUT LPC_PINCON->PINSEL0&=p27_SEL_MASK;LPC_GPIO0->FIODIR|=p27_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 307 #define p27_AS_INPUT LPC_GPIO0->FIOMASK &= p27_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 308 #define p27_SET LPC_GPIO0->FIOSET = p27_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 309 #define p27_CLR LPC_GPIO0->FIOCLR = p27_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 310 #define p27_IS_SET (bool)(LPC_GPIO0->FIOPIN & p27_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 311 #define p27_IS_CLR !(p27_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 312 #define p27_MODE(x) LPC_PINCON->PINMODE0&=p27_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<22)
H_Tsunemoto 0:47c1b6a0c166 313
H_Tsunemoto 0:47c1b6a0c166 314 /* p28 is P0.10 */
H_Tsunemoto 0:47c1b6a0c166 315 #define p28_SEL_MASK ~(3UL << 20)
H_Tsunemoto 0:47c1b6a0c166 316 #define p28_SET_MASK (1UL << 10)
H_Tsunemoto 0:47c1b6a0c166 317 #define p28_CLR_MASK ~(p28_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 318 #define p28_AS_OUTPUT LPC_PINCON->PINSEL0&=p28_SEL_MASK;LPC_GPIO0->FIODIR|=p28_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 319 #define p28_AS_INPUT LPC_GPIO0->FIOMASK &= p28_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 320 #define p28_SET LPC_GPIO0->FIOSET = p28_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 321 #define p28_CLR LPC_GPIO0->FIOCLR = p28_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 322 #define p28_IS_SET (bool)(LPC_GPIO0->FIOPIN & p28_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 323 #define p28_IS_CLR !(p28_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 324 #define p28_MODE(x) LPC_PINCON->PINMODE0&=p28_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<20)
H_Tsunemoto 0:47c1b6a0c166 325
H_Tsunemoto 0:47c1b6a0c166 326 /* p29 is P0.5 */
H_Tsunemoto 0:47c1b6a0c166 327 #define p29_SEL_MASK ~(3UL << 10)
H_Tsunemoto 0:47c1b6a0c166 328 #define p29_SET_MASK (1UL << 5)
H_Tsunemoto 0:47c1b6a0c166 329 #define p29_CLR_MASK ~(p29_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 330 #define p29_AS_OUTPUT LPC_PINCON->PINSEL0&=p29_SEL_MASK;LPC_GPIO0->FIODIR|=p29_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 331 #define p29_AS_INPUT LPC_GPIO0->FIOMASK &= p29_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 332 #define p29_SET LPC_GPIO0->FIOSET = p29_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 333 #define p29_CLR LPC_GPIO0->FIOCLR = p29_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 334 #define p29_IS_SET (bool)(LPC_GPIO0->FIOPIN & p29_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 335 #define p29_IS_CLR !(p29_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 336 #define p29_TOGGLE p29_IS_SET?p29_CLR:p29_SET
H_Tsunemoto 0:47c1b6a0c166 337 #define p29_MODE(x) LPC_PINCON->PINMODE0&=p29_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<10)
H_Tsunemoto 0:47c1b6a0c166 338
H_Tsunemoto 0:47c1b6a0c166 339 /* p30 is P0.4 */
H_Tsunemoto 0:47c1b6a0c166 340 #define p30_SEL_MASK ~(3UL << 8)
H_Tsunemoto 0:47c1b6a0c166 341 #define p30_SET_MASK (1UL << 4)
H_Tsunemoto 0:47c1b6a0c166 342 #define p30_CLR_MASK ~(p30_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 343 #define p30_AS_OUTPUT LPC_PINCON->PINSEL0&=p30_SEL_MASK;LPC_GPIO0->FIODIR|=p30_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 344 #define p30_AS_INPUT LPC_GPIO0->FIOMASK &= p30_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 345 #define p30_SET LPC_GPIO0->FIOSET = p30_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 346 #define p30_CLR LPC_GPIO0->FIOCLR = p30_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 347 #define p30_IS_SET (bool)(LPC_GPIO0->FIOPIN & p30_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 348 #define p30_IS_CLR !(p30_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 349 #define p30_MODE(x) LPC_PINCON->PINMODE0&=p30_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<8)
H_Tsunemoto 0:47c1b6a0c166 350
H_Tsunemoto 0:47c1b6a0c166 351 /* The following definitions are for the four Mbed LEDs.
H_Tsunemoto 0:47c1b6a0c166 352 LED1 = P1.18
H_Tsunemoto 0:47c1b6a0c166 353 LED2 = P1.20
H_Tsunemoto 0:47c1b6a0c166 354 LED3 = P1.21
H_Tsunemoto 0:47c1b6a0c166 355 LED4 = P1.23 */
H_Tsunemoto 0:47c1b6a0c166 356
H_Tsunemoto 0:47c1b6a0c166 357 #define P1_18_SEL_MASK ~(3UL << 4)
H_Tsunemoto 0:47c1b6a0c166 358 #define P1_18_SET_MASK (1UL << 18)
H_Tsunemoto 0:47c1b6a0c166 359 #define P1_18_CLR_MASK ~(P1_18_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 360 #define P1_18_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_18_SEL_MASK;LPC_GPIO1->FIODIR|=P1_18_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 361 #define P1_18_AS_INPUT LPC_GPIO1->FIOMASK &= P1_18_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 362 #define P1_18_SET LPC_GPIO1->FIOSET = P1_18_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 363 #define P1_18_CLR LPC_GPIO1->FIOCLR = P1_18_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 364 #define P1_18_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_18_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 365 #define P1_18_IS_CLR !(P1_18_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 366 #define LED1_USE P1_18_AS_OUTPUT;P1_18_AS_INPUT
H_Tsunemoto 0:47c1b6a0c166 367 #define LED1_ON P1_18_SET
H_Tsunemoto 0:47c1b6a0c166 368 #define LED1_OFF P1_18_CLR
H_Tsunemoto 0:47c1b6a0c166 369 #define LED1_IS_ON P1_18_IS_SET
H_Tsunemoto 0:47c1b6a0c166 370 #define LED1_TOGGLE P1_18_IS_SET?LED1_OFF:LED1_ON
H_Tsunemoto 0:47c1b6a0c166 371
H_Tsunemoto 0:47c1b6a0c166 372 #define P1_20_SEL_MASK ~(3UL << 8)
H_Tsunemoto 0:47c1b6a0c166 373 #define P1_20_SET_MASK (1UL << 20)
H_Tsunemoto 0:47c1b6a0c166 374 #define P1_20_CLR_MASK ~(P1_20_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 375 #define P1_20_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_20_SEL_MASK;LPC_GPIO1->FIODIR|=P1_20_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 376 #define P1_20_AS_INPUT LPC_GPIO1->FIOMASK &= P1_20_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 377 #define P1_20_SET LPC_GPIO1->FIOSET = P1_20_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 378 #define P1_20_CLR LPC_GPIO1->FIOCLR = P1_20_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 379 #define P1_20_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_20_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 380 #define P1_20_IS_CLR !(P1_20_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 381 #define LED2_USE P1_20_AS_OUTPUT;P1_20_AS_INPUT
H_Tsunemoto 0:47c1b6a0c166 382 #define LED2_ON P1_20_SET
H_Tsunemoto 0:47c1b6a0c166 383 #define LED2_OFF P1_20_CLR
H_Tsunemoto 0:47c1b6a0c166 384 #define LED2_IS_ON P1_20_IS_SET
H_Tsunemoto 0:47c1b6a0c166 385 #define LED2_TOGGLE P1_20_IS_SET?LED2_OFF:LED2_ON
H_Tsunemoto 0:47c1b6a0c166 386
H_Tsunemoto 0:47c1b6a0c166 387 #define P1_21_SEL_MASK ~(3UL << 10)
H_Tsunemoto 0:47c1b6a0c166 388 #define P1_21_SET_MASK (1UL << 21)
H_Tsunemoto 0:47c1b6a0c166 389 #define P1_21_CLR_MASK ~(P1_21_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 390 #define P1_21_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_21_SEL_MASK;LPC_GPIO1->FIODIR|=P1_21_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 391 #define P1_21_AS_INPUT LPC_GPIO1->FIOMASK &= P1_21_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 392 #define P1_21_SET LPC_GPIO1->FIOSET = P1_21_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 393 #define P1_21_CLR LPC_GPIO1->FIOCLR = P1_21_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 394 #define P1_21_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_21_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 395 #define P1_21_IS_CLR !(P1_21_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 396 #define LED3_USE P1_21_AS_OUTPUT;P1_21_AS_INPUT
H_Tsunemoto 0:47c1b6a0c166 397 #define LED3_ON P1_21_SET
H_Tsunemoto 0:47c1b6a0c166 398 #define LED3_OFF P1_21_CLR
H_Tsunemoto 0:47c1b6a0c166 399 #define LED3_IS_ON P1_21_IS_SET
H_Tsunemoto 0:47c1b6a0c166 400 #define LED3_TOGGLE P1_21_IS_SET?LED3_OFF:LED3_ON
H_Tsunemoto 0:47c1b6a0c166 401
H_Tsunemoto 0:47c1b6a0c166 402 #define P1_23_SEL_MASK ~(3UL << 14)
H_Tsunemoto 0:47c1b6a0c166 403 #define P1_23_SET_MASK (1UL << 23)
H_Tsunemoto 0:47c1b6a0c166 404 #define P1_23_CLR_MASK ~(P1_23_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 405 #define P1_23_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_23_SEL_MASK;LPC_GPIO1->FIODIR|=P1_23_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 406 #define P1_23_AS_INPUT LPC_GPIO1->FIOMASK &= P1_23_CLR_MASK;
H_Tsunemoto 0:47c1b6a0c166 407 #define P1_23_SET LPC_GPIO1->FIOSET = P1_23_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 408 #define P1_23_CLR LPC_GPIO1->FIOCLR = P1_23_SET_MASK
H_Tsunemoto 0:47c1b6a0c166 409 #define P1_23_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_23_SET_MASK)
H_Tsunemoto 0:47c1b6a0c166 410 #define P1_23_IS_CLR !(P1_23_IS_SET)
H_Tsunemoto 0:47c1b6a0c166 411 #define LED4_USE P1_23_AS_OUTPUT;P1_23_AS_INPUT
H_Tsunemoto 0:47c1b6a0c166 412 #define LED4_ON P1_23_SET
H_Tsunemoto 0:47c1b6a0c166 413 #define LED4_OFF P1_23_CLR
H_Tsunemoto 0:47c1b6a0c166 414 #define LED4_IS_ON P1_23_IS_SET
H_Tsunemoto 0:47c1b6a0c166 415 #define LED4_TOGGLE P1_23_IS_SET?LED4_OFF:LED4_ON
H_Tsunemoto 0:47c1b6a0c166 416
H_Tsunemoto 0:47c1b6a0c166 417 #endif
H_Tsunemoto 0:47c1b6a0c166 418