John Karatka / mbed

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targets/TARGET_STM/i2c_api.c@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
178:d650f5d4c87a 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /* mbed Microcontroller Library
<> 153:fa9ff456f731 2 *******************************************************************************
<> 153:fa9ff456f731 3 * Copyright (c) 2015, STMicroelectronics
<> 153:fa9ff456f731 4 * All rights reserved.
<> 153:fa9ff456f731 5 *
<> 153:fa9ff456f731 6 * Redistribution and use in source and binary forms, with or without
<> 153:fa9ff456f731 7 * modification, are permitted provided that the following conditions are met:
<> 153:fa9ff456f731 8 *
<> 153:fa9ff456f731 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 153:fa9ff456f731 10 * this list of conditions and the following disclaimer.
<> 153:fa9ff456f731 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 153:fa9ff456f731 12 * this list of conditions and the following disclaimer in the documentation
<> 153:fa9ff456f731 13 * and/or other materials provided with the distribution.
<> 153:fa9ff456f731 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 153:fa9ff456f731 15 * may be used to endorse or promote products derived from this software
<> 153:fa9ff456f731 16 * without specific prior written permission.
<> 153:fa9ff456f731 17 *
<> 153:fa9ff456f731 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 153:fa9ff456f731 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 153:fa9ff456f731 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 153:fa9ff456f731 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 153:fa9ff456f731 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 153:fa9ff456f731 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 153:fa9ff456f731 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 153:fa9ff456f731 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 153:fa9ff456f731 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 153:fa9ff456f731 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 153:fa9ff456f731 28 *******************************************************************************
<> 153:fa9ff456f731 29 */
<> 153:fa9ff456f731 30
<> 153:fa9ff456f731 31
<> 153:fa9ff456f731 32 #include "mbed_assert.h"
<> 153:fa9ff456f731 33 #include "i2c_api.h"
<> 160:d5399cc887bb 34 #include "platform/mbed_wait_api.h"
<> 153:fa9ff456f731 35
<> 153:fa9ff456f731 36 #if DEVICE_I2C
<> 153:fa9ff456f731 37
<> 153:fa9ff456f731 38 #include "cmsis.h"
<> 153:fa9ff456f731 39 #include "pinmap.h"
<> 153:fa9ff456f731 40 #include "PeripheralPins.h"
<> 153:fa9ff456f731 41 #include "i2c_device.h" // family specific defines
<> 153:fa9ff456f731 42
<> 153:fa9ff456f731 43 #ifndef DEBUG_STDIO
<> 153:fa9ff456f731 44 # define DEBUG_STDIO 0
<> 153:fa9ff456f731 45 #endif
<> 153:fa9ff456f731 46
<> 153:fa9ff456f731 47 #if DEBUG_STDIO
<> 153:fa9ff456f731 48 # include <stdio.h>
<> 153:fa9ff456f731 49 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
<> 153:fa9ff456f731 50 #else
<> 153:fa9ff456f731 51 # define DEBUG_PRINTF(...) {}
<> 153:fa9ff456f731 52 #endif
<> 153:fa9ff456f731 53
<> 153:fa9ff456f731 54 #if DEVICE_I2C_ASYNCH
<> 153:fa9ff456f731 55 #define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
<> 153:fa9ff456f731 56 #else
<> 153:fa9ff456f731 57 #define I2C_S(obj) (struct i2c_s *) (obj)
<> 153:fa9ff456f731 58 #endif
<> 153:fa9ff456f731 59
<> 153:fa9ff456f731 60 /* Family specific description for I2C */
<> 153:fa9ff456f731 61 #define I2C_NUM (5)
<> 153:fa9ff456f731 62 static I2C_HandleTypeDef* i2c_handles[I2C_NUM];
<> 153:fa9ff456f731 63
<> 153:fa9ff456f731 64 /* Timeout values are based on core clock and I2C clock.
<> 153:fa9ff456f731 65 The BYTE_TIMEOUT is computed as twice the number of cycles it would
<> 153:fa9ff456f731 66 take to send 10 bits over I2C. Most Flags should take less than that.
<> 153:fa9ff456f731 67 This is for immediate FLAG or ACK check.
<> 153:fa9ff456f731 68 */
<> 153:fa9ff456f731 69 #define BYTE_TIMEOUT ((SystemCoreClock / obj_s->hz) * 2 * 10)
<> 153:fa9ff456f731 70 /* Timeout values based on I2C clock.
<> 153:fa9ff456f731 71 The BYTE_TIMEOUT_US is computed as 3x the time in us it would
<> 153:fa9ff456f731 72 take to send 10 bits over I2C. Most Flags should take less than that.
<> 153:fa9ff456f731 73 This is for complete transfers check.
<> 153:fa9ff456f731 74 */
<> 153:fa9ff456f731 75 #define BYTE_TIMEOUT_US ((SystemCoreClock / obj_s->hz) * 3 * 10)
<> 153:fa9ff456f731 76 /* Timeout values for flags and events waiting loops. These timeouts are
<> 153:fa9ff456f731 77 not based on accurate values, they just guarantee that the application will
<> 153:fa9ff456f731 78 not remain stuck if the I2C communication is corrupted.
<> 153:fa9ff456f731 79 */
<> 153:fa9ff456f731 80 #define FLAG_TIMEOUT ((int)0x1000)
<> 153:fa9ff456f731 81
<> 153:fa9ff456f731 82 /* GENERIC INIT and HELPERS FUNCTIONS */
<> 153:fa9ff456f731 83
<> 153:fa9ff456f731 84 #if defined(I2C1_BASE)
<> 153:fa9ff456f731 85 static void i2c1_irq(void)
<> 153:fa9ff456f731 86 {
<> 153:fa9ff456f731 87 I2C_HandleTypeDef * handle = i2c_handles[0];
<> 153:fa9ff456f731 88 HAL_I2C_EV_IRQHandler(handle);
<> 153:fa9ff456f731 89 HAL_I2C_ER_IRQHandler(handle);
<> 153:fa9ff456f731 90 }
<> 153:fa9ff456f731 91 #endif
<> 153:fa9ff456f731 92 #if defined(I2C2_BASE)
<> 153:fa9ff456f731 93 static void i2c2_irq(void)
<> 153:fa9ff456f731 94 {
<> 153:fa9ff456f731 95 I2C_HandleTypeDef * handle = i2c_handles[1];
<> 153:fa9ff456f731 96 HAL_I2C_EV_IRQHandler(handle);
<> 153:fa9ff456f731 97 HAL_I2C_ER_IRQHandler(handle);
<> 153:fa9ff456f731 98 }
<> 153:fa9ff456f731 99 #endif
<> 153:fa9ff456f731 100 #if defined(I2C3_BASE)
<> 153:fa9ff456f731 101 static void i2c3_irq(void)
<> 153:fa9ff456f731 102 {
<> 153:fa9ff456f731 103 I2C_HandleTypeDef * handle = i2c_handles[2];
<> 153:fa9ff456f731 104 HAL_I2C_EV_IRQHandler(handle);
<> 153:fa9ff456f731 105 HAL_I2C_ER_IRQHandler(handle);
<> 153:fa9ff456f731 106 }
<> 153:fa9ff456f731 107 #endif
<> 153:fa9ff456f731 108 #if defined(I2C4_BASE)
<> 153:fa9ff456f731 109 static void i2c4_irq(void)
<> 153:fa9ff456f731 110 {
<> 153:fa9ff456f731 111 I2C_HandleTypeDef * handle = i2c_handles[3];
<> 153:fa9ff456f731 112 HAL_I2C_EV_IRQHandler(handle);
<> 153:fa9ff456f731 113 HAL_I2C_ER_IRQHandler(handle);
<> 153:fa9ff456f731 114 }
<> 153:fa9ff456f731 115 #endif
<> 153:fa9ff456f731 116 #if defined(FMPI2C1_BASE)
<> 153:fa9ff456f731 117 static void i2c5_irq(void)
<> 153:fa9ff456f731 118 {
<> 153:fa9ff456f731 119 I2C_HandleTypeDef * handle = i2c_handles[4];
<> 153:fa9ff456f731 120 HAL_I2C_EV_IRQHandler(handle);
<> 153:fa9ff456f731 121 HAL_I2C_ER_IRQHandler(handle);
<> 153:fa9ff456f731 122 }
<> 153:fa9ff456f731 123 #endif
<> 153:fa9ff456f731 124
<> 153:fa9ff456f731 125 void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) {
<> 153:fa9ff456f731 126 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 127 IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
<> 153:fa9ff456f731 128 IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
<> 153:fa9ff456f731 129 /* default prio in master case is set to 2 */
<> 153:fa9ff456f731 130 uint32_t prio = 2;
<> 153:fa9ff456f731 131
<> 153:fa9ff456f731 132 /* Set up ITs using IRQ and handler tables */
<> 153:fa9ff456f731 133 NVIC_SetVector(irq_event_n, handler);
<> 153:fa9ff456f731 134 NVIC_SetVector(irq_error_n, handler);
<> 153:fa9ff456f731 135
<> 153:fa9ff456f731 136 #if DEVICE_I2CSLAVE
<> 153:fa9ff456f731 137 /* Set higher priority to slave device than master.
<> 153:fa9ff456f731 138 * In case a device makes use of both master and slave, the
<> 153:fa9ff456f731 139 * slave needs higher responsiveness.
<> 153:fa9ff456f731 140 */
<> 153:fa9ff456f731 141 if (obj_s->slave) {
<> 153:fa9ff456f731 142 prio = 1;
<> 153:fa9ff456f731 143 }
<> 153:fa9ff456f731 144 #endif
<> 153:fa9ff456f731 145
<> 153:fa9ff456f731 146 NVIC_SetPriority(irq_event_n, prio);
<> 153:fa9ff456f731 147 NVIC_SetPriority(irq_error_n, prio);
<> 153:fa9ff456f731 148 NVIC_EnableIRQ(irq_event_n);
<> 153:fa9ff456f731 149 NVIC_EnableIRQ(irq_error_n);
<> 153:fa9ff456f731 150 }
<> 153:fa9ff456f731 151
<> 153:fa9ff456f731 152 void i2c_ev_err_disable(i2c_t *obj) {
<> 153:fa9ff456f731 153 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 154 IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
<> 153:fa9ff456f731 155 IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
<> 153:fa9ff456f731 156
<> 153:fa9ff456f731 157 HAL_NVIC_DisableIRQ(irq_event_n);
<> 153:fa9ff456f731 158 HAL_NVIC_DisableIRQ(irq_error_n);
<> 153:fa9ff456f731 159 }
<> 153:fa9ff456f731 160
<> 153:fa9ff456f731 161 uint32_t i2c_get_irq_handler(i2c_t *obj)
<> 153:fa9ff456f731 162 {
<> 153:fa9ff456f731 163 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 164 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 165 uint32_t handler = 0;
<> 153:fa9ff456f731 166
<> 153:fa9ff456f731 167 switch (obj_s->index) {
<> 153:fa9ff456f731 168 #if defined(I2C1_BASE)
<> 153:fa9ff456f731 169 case 0:
<> 153:fa9ff456f731 170 handler = (uint32_t)&i2c1_irq;
<> 153:fa9ff456f731 171 break;
<> 153:fa9ff456f731 172 #endif
<> 153:fa9ff456f731 173 #if defined(I2C2_BASE)
<> 153:fa9ff456f731 174 case 1:
<> 153:fa9ff456f731 175 handler = (uint32_t)&i2c2_irq;
<> 153:fa9ff456f731 176 break;
<> 153:fa9ff456f731 177 #endif
<> 153:fa9ff456f731 178 #if defined(I2C3_BASE)
<> 153:fa9ff456f731 179 case 2:
<> 153:fa9ff456f731 180 handler = (uint32_t)&i2c3_irq;
<> 153:fa9ff456f731 181 break;
<> 153:fa9ff456f731 182 #endif
<> 153:fa9ff456f731 183 #if defined(I2C4_BASE)
<> 153:fa9ff456f731 184 case 3:
<> 153:fa9ff456f731 185 handler = (uint32_t)&i2c4_irq;
<> 153:fa9ff456f731 186 break;
<> 153:fa9ff456f731 187 #endif
<> 153:fa9ff456f731 188 #if defined(FMPI2C1_BASE)
<> 153:fa9ff456f731 189 case 4:
<> 153:fa9ff456f731 190 handler = (uint32_t)&i2c5_irq;
<> 153:fa9ff456f731 191 break;
<> 153:fa9ff456f731 192 #endif
<> 153:fa9ff456f731 193 }
<> 153:fa9ff456f731 194
<> 153:fa9ff456f731 195 i2c_handles[obj_s->index] = handle;
<> 153:fa9ff456f731 196 return handler;
<> 153:fa9ff456f731 197 }
<> 153:fa9ff456f731 198
<> 153:fa9ff456f731 199 void i2c_hw_reset(i2c_t *obj) {
<> 153:fa9ff456f731 200 int timeout;
<> 153:fa9ff456f731 201 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 202 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 203
<> 153:fa9ff456f731 204 handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
<> 153:fa9ff456f731 205
<> 153:fa9ff456f731 206 // wait before reset
<> 153:fa9ff456f731 207 timeout = BYTE_TIMEOUT;
<> 153:fa9ff456f731 208 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
<> 153:fa9ff456f731 209 #if defined I2C1_BASE
<> 153:fa9ff456f731 210 if (obj_s->i2c == I2C_1) {
<> 153:fa9ff456f731 211 __HAL_RCC_I2C1_FORCE_RESET();
<> 153:fa9ff456f731 212 __HAL_RCC_I2C1_RELEASE_RESET();
<> 153:fa9ff456f731 213 }
<> 153:fa9ff456f731 214 #endif
<> 153:fa9ff456f731 215 #if defined I2C2_BASE
<> 153:fa9ff456f731 216 if (obj_s->i2c == I2C_2) {
<> 153:fa9ff456f731 217 __HAL_RCC_I2C2_FORCE_RESET();
<> 153:fa9ff456f731 218 __HAL_RCC_I2C2_RELEASE_RESET();
<> 153:fa9ff456f731 219 }
<> 153:fa9ff456f731 220 #endif
<> 153:fa9ff456f731 221 #if defined I2C3_BASE
<> 153:fa9ff456f731 222 if (obj_s->i2c == I2C_3) {
<> 153:fa9ff456f731 223 __HAL_RCC_I2C3_FORCE_RESET();
<> 153:fa9ff456f731 224 __HAL_RCC_I2C3_RELEASE_RESET();
<> 153:fa9ff456f731 225 }
<> 153:fa9ff456f731 226 #endif
<> 153:fa9ff456f731 227 #if defined I2C4_BASE
<> 153:fa9ff456f731 228 if (obj_s->i2c == I2C_4) {
<> 153:fa9ff456f731 229 __HAL_RCC_I2C4_FORCE_RESET();
<> 153:fa9ff456f731 230 __HAL_RCC_I2C4_RELEASE_RESET();
<> 153:fa9ff456f731 231 }
<> 153:fa9ff456f731 232 #endif
<> 153:fa9ff456f731 233 #if defined FMPI2C1_BASE
<> 153:fa9ff456f731 234 if (obj_s->i2c == FMPI2C_1) {
<> 153:fa9ff456f731 235 __HAL_RCC_FMPI2C1_FORCE_RESET();
<> 153:fa9ff456f731 236 __HAL_RCC_FMPI2C1_RELEASE_RESET();
<> 153:fa9ff456f731 237 }
<> 153:fa9ff456f731 238 #endif
<> 153:fa9ff456f731 239 }
<> 153:fa9ff456f731 240
Kojto 158:b23ee177fd68 241 void i2c_sw_reset(i2c_t *obj)
Kojto 158:b23ee177fd68 242 {
Kojto 158:b23ee177fd68 243 struct i2c_s *obj_s = I2C_S(obj);
Kojto 158:b23ee177fd68 244 I2C_HandleTypeDef *handle = &(obj_s->handle);
Kojto 158:b23ee177fd68 245 /* SW reset procedure:
Kojto 158:b23ee177fd68 246 * PE must be kept low during at least 3 APB clock cycles
Kojto 158:b23ee177fd68 247 * in order to perform the software reset.
Kojto 158:b23ee177fd68 248 * This is ensured by writing the following software sequence:
Kojto 158:b23ee177fd68 249 * - Write PE=0
Kojto 158:b23ee177fd68 250 * - Check PE=0
Kojto 158:b23ee177fd68 251 * - Write PE=1.
Kojto 158:b23ee177fd68 252 */
Kojto 158:b23ee177fd68 253 handle->Instance->CR1 &= ~I2C_CR1_PE;
Kojto 158:b23ee177fd68 254 while(handle->Instance->CR1 & I2C_CR1_PE);
Kojto 158:b23ee177fd68 255 handle->Instance->CR1 |= I2C_CR1_PE;
Kojto 158:b23ee177fd68 256 }
Kojto 158:b23ee177fd68 257
<> 153:fa9ff456f731 258 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
<> 153:fa9ff456f731 259
<> 153:fa9ff456f731 260 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 261
<> 153:fa9ff456f731 262 // Determine the I2C to use
<> 153:fa9ff456f731 263 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
<> 153:fa9ff456f731 264 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
<> 153:fa9ff456f731 265 obj_s->sda = sda;
<> 153:fa9ff456f731 266 obj_s->scl = scl;
<> 153:fa9ff456f731 267
<> 153:fa9ff456f731 268 obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
<> 153:fa9ff456f731 269 MBED_ASSERT(obj_s->i2c != (I2CName)NC);
<> 153:fa9ff456f731 270
<> 153:fa9ff456f731 271 #if defined I2C1_BASE
<> 153:fa9ff456f731 272 // Enable I2C1 clock and pinout if not done
<> 153:fa9ff456f731 273 if (obj_s->i2c == I2C_1) {
<> 153:fa9ff456f731 274 obj_s->index = 0;
<> 153:fa9ff456f731 275 __HAL_RCC_I2C1_CLK_ENABLE();
<> 153:fa9ff456f731 276 // Configure I2C pins
<> 153:fa9ff456f731 277 obj_s->event_i2cIRQ = I2C1_EV_IRQn;
<> 153:fa9ff456f731 278 obj_s->error_i2cIRQ = I2C1_ER_IRQn;
<> 153:fa9ff456f731 279 }
<> 153:fa9ff456f731 280 #endif
<> 153:fa9ff456f731 281 #if defined I2C2_BASE
<> 153:fa9ff456f731 282 // Enable I2C2 clock and pinout if not done
<> 153:fa9ff456f731 283 if (obj_s->i2c == I2C_2) {
<> 153:fa9ff456f731 284 obj_s->index = 1;
<> 153:fa9ff456f731 285 __HAL_RCC_I2C2_CLK_ENABLE();
<> 153:fa9ff456f731 286 obj_s->event_i2cIRQ = I2C2_EV_IRQn;
<> 153:fa9ff456f731 287 obj_s->error_i2cIRQ = I2C2_ER_IRQn;
<> 153:fa9ff456f731 288 }
<> 153:fa9ff456f731 289 #endif
<> 153:fa9ff456f731 290 #if defined I2C3_BASE
<> 153:fa9ff456f731 291 // Enable I2C3 clock and pinout if not done
<> 153:fa9ff456f731 292 if (obj_s->i2c == I2C_3) {
<> 153:fa9ff456f731 293 obj_s->index = 2;
<> 153:fa9ff456f731 294 __HAL_RCC_I2C3_CLK_ENABLE();
<> 153:fa9ff456f731 295 obj_s->event_i2cIRQ = I2C3_EV_IRQn;
<> 153:fa9ff456f731 296 obj_s->error_i2cIRQ = I2C3_ER_IRQn;
<> 153:fa9ff456f731 297 }
<> 153:fa9ff456f731 298 #endif
<> 153:fa9ff456f731 299 #if defined I2C4_BASE
<> 153:fa9ff456f731 300 // Enable I2C3 clock and pinout if not done
<> 153:fa9ff456f731 301 if (obj_s->i2c == I2C_4) {
<> 153:fa9ff456f731 302 obj_s->index = 3;
<> 153:fa9ff456f731 303 __HAL_RCC_I2C4_CLK_ENABLE();
<> 153:fa9ff456f731 304 obj_s->event_i2cIRQ = I2C4_EV_IRQn;
<> 153:fa9ff456f731 305 obj_s->error_i2cIRQ = I2C4_ER_IRQn;
<> 153:fa9ff456f731 306 }
<> 153:fa9ff456f731 307 #endif
<> 153:fa9ff456f731 308 #if defined FMPI2C1_BASE
<> 153:fa9ff456f731 309 // Enable I2C3 clock and pinout if not done
<> 153:fa9ff456f731 310 if (obj_s->i2c == FMPI2C_1) {
<> 153:fa9ff456f731 311 obj_s->index = 4;
<> 153:fa9ff456f731 312 __HAL_RCC_FMPI2C1_CLK_ENABLE();
<> 153:fa9ff456f731 313 obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
<> 153:fa9ff456f731 314 obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
<> 153:fa9ff456f731 315 }
<> 153:fa9ff456f731 316 #endif
<> 153:fa9ff456f731 317
Anna Bridge 181:96ed750bd169 318 // Configure I2C pins
Anna Bridge 181:96ed750bd169 319 pinmap_pinout(sda, PinMap_I2C_SDA);
Anna Bridge 181:96ed750bd169 320 pinmap_pinout(scl, PinMap_I2C_SCL);
Anna Bridge 181:96ed750bd169 321 pin_mode(sda, OpenDrainNoPull);
Anna Bridge 181:96ed750bd169 322 pin_mode(scl, OpenDrainNoPull);
Anna Bridge 181:96ed750bd169 323
<> 153:fa9ff456f731 324 // I2C configuration
<> 153:fa9ff456f731 325 // Default hz value used for timeout computation
<> 153:fa9ff456f731 326 if(!obj_s->hz)
<> 153:fa9ff456f731 327 obj_s->hz = 100000; // 100 kHz per default
<> 153:fa9ff456f731 328
<> 153:fa9ff456f731 329 // Reset to clear pending flags if any
<> 153:fa9ff456f731 330 i2c_hw_reset(obj);
<> 153:fa9ff456f731 331 i2c_frequency(obj, obj_s->hz );
<> 153:fa9ff456f731 332
<> 153:fa9ff456f731 333 #if DEVICE_I2CSLAVE
<> 153:fa9ff456f731 334 // I2C master by default
<> 153:fa9ff456f731 335 obj_s->slave = 0;
<> 153:fa9ff456f731 336 obj_s->pending_slave_tx_master_rx = 0;
<> 153:fa9ff456f731 337 obj_s->pending_slave_rx_maxter_tx = 0;
<> 153:fa9ff456f731 338 #endif
<> 153:fa9ff456f731 339
<> 153:fa9ff456f731 340 // I2C Xfer operation init
<> 153:fa9ff456f731 341 obj_s->event = 0;
<> 153:fa9ff456f731 342 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
<> 156:95d6b41a828b 343 #ifdef I2C_IP_VERSION_V2
<> 156:95d6b41a828b 344 obj_s->pending_start = 0;
<> 156:95d6b41a828b 345 #endif
<> 153:fa9ff456f731 346 }
<> 153:fa9ff456f731 347
<> 153:fa9ff456f731 348 void i2c_frequency(i2c_t *obj, int hz)
<> 153:fa9ff456f731 349 {
<> 153:fa9ff456f731 350 int timeout;
<> 153:fa9ff456f731 351 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 352 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 353
<> 153:fa9ff456f731 354 // wait before init
<> 153:fa9ff456f731 355 timeout = BYTE_TIMEOUT;
<> 153:fa9ff456f731 356 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
<> 153:fa9ff456f731 357
<> 153:fa9ff456f731 358 #ifdef I2C_IP_VERSION_V1
<> 153:fa9ff456f731 359 handle->Init.ClockSpeed = hz;
<> 153:fa9ff456f731 360 handle->Init.DutyCycle = I2C_DUTYCYCLE_2;
<> 153:fa9ff456f731 361 #endif
<> 153:fa9ff456f731 362 #ifdef I2C_IP_VERSION_V2
<> 153:fa9ff456f731 363 /* Only predefined timing for below frequencies are supported */
<> 153:fa9ff456f731 364 MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
<> 153:fa9ff456f731 365 handle->Init.Timing = get_i2c_timing(hz);
<> 153:fa9ff456f731 366
<> 153:fa9ff456f731 367 // Enable the Fast Mode Plus capability
<> 153:fa9ff456f731 368 if (hz == 1000000) {
<> 153:fa9ff456f731 369 #if defined(I2C1_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C1)
<> 153:fa9ff456f731 370 if (obj_s->i2c == I2C_1) {
<> 156:95d6b41a828b 371 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
<> 153:fa9ff456f731 372 }
<> 153:fa9ff456f731 373 #endif
<> 153:fa9ff456f731 374 #if defined(I2C2_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C2)
<> 153:fa9ff456f731 375 if (obj_s->i2c == I2C_2) {
<> 156:95d6b41a828b 376 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C2);
<> 153:fa9ff456f731 377 }
<> 153:fa9ff456f731 378 #endif
<> 153:fa9ff456f731 379 #if defined(I2C3_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C3)
<> 153:fa9ff456f731 380 if (obj_s->i2c == I2C_3) {
<> 156:95d6b41a828b 381 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3);
<> 153:fa9ff456f731 382 }
<> 153:fa9ff456f731 383 #endif
<> 153:fa9ff456f731 384 #if defined(I2C4_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C4)
<> 153:fa9ff456f731 385 if (obj_s->i2c == I2C_4) {
<> 156:95d6b41a828b 386 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C4);
<> 153:fa9ff456f731 387 }
<> 153:fa9ff456f731 388 #endif
<> 153:fa9ff456f731 389 }
<> 153:fa9ff456f731 390 #endif //I2C_IP_VERSION_V2
<> 153:fa9ff456f731 391
<> 153:fa9ff456f731 392 /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
<> 153:fa9ff456f731 393 #if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)
<> 153:fa9ff456f731 394 if (obj_s->i2c == I2C_1) {
<> 153:fa9ff456f731 395 __HAL_RCC_I2C1_CONFIG(I2CAPI_I2C1_CLKSRC);
<> 153:fa9ff456f731 396 }
<> 153:fa9ff456f731 397 #endif
<> 153:fa9ff456f731 398 #if defined(I2C2_BASE) && defined(__HAL_RCC_I2C2_CONFIG)
<> 153:fa9ff456f731 399 if (obj_s->i2c == I2C_2) {
<> 153:fa9ff456f731 400 __HAL_RCC_I2C2_CONFIG(I2CAPI_I2C2_CLKSRC);
<> 153:fa9ff456f731 401 }
<> 153:fa9ff456f731 402 #endif
<> 153:fa9ff456f731 403 #if defined(I2C3_BASE) && defined(__HAL_RCC_I2C3_CONFIG)
<> 153:fa9ff456f731 404 if (obj_s->i2c == I2C_3) {
<> 153:fa9ff456f731 405 __HAL_RCC_I2C3_CONFIG(I2CAPI_I2C3_CLKSRC);
<> 153:fa9ff456f731 406 }
<> 153:fa9ff456f731 407 #endif
<> 153:fa9ff456f731 408 #if defined(I2C4_BASE) && defined(__HAL_RCC_I2C4_CONFIG)
<> 153:fa9ff456f731 409 if (obj_s->i2c == I2C_4) {
<> 153:fa9ff456f731 410 __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
<> 153:fa9ff456f731 411 }
<> 153:fa9ff456f731 412 #endif
<> 153:fa9ff456f731 413
<> 153:fa9ff456f731 414 #ifdef I2C_ANALOGFILTER_ENABLE
<> 153:fa9ff456f731 415 /* Enable the Analog I2C Filter */
Anna Bridge 181:96ed750bd169 416 HAL_I2CEx_ConfigAnalogFilter(handle,I2C_ANALOGFILTER_ENABLE);
<> 153:fa9ff456f731 417 #endif
<> 153:fa9ff456f731 418
<> 153:fa9ff456f731 419 // I2C configuration
<> 153:fa9ff456f731 420 handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
AnnaBridge 165:e614a9f1c9e2 421 handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
AnnaBridge 165:e614a9f1c9e2 422 handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
AnnaBridge 165:e614a9f1c9e2 423 handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
<> 153:fa9ff456f731 424 handle->Init.OwnAddress1 = 0;
<> 153:fa9ff456f731 425 handle->Init.OwnAddress2 = 0;
<> 153:fa9ff456f731 426 HAL_I2C_Init(handle);
<> 153:fa9ff456f731 427
<> 153:fa9ff456f731 428 /* store frequency for timeout computation */
<> 153:fa9ff456f731 429 obj_s->hz = hz;
<> 153:fa9ff456f731 430 }
<> 153:fa9ff456f731 431
<> 153:fa9ff456f731 432 i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){
<> 153:fa9ff456f731 433 /* Aim of the function is to get i2c_s pointer using hi2c pointer */
<> 153:fa9ff456f731 434 /* Highly inspired from magical linux kernel's "container_of" */
<> 153:fa9ff456f731 435 /* (which was not directly used since not compatible with IAR toolchain) */
<> 153:fa9ff456f731 436 struct i2c_s *obj_s;
<> 153:fa9ff456f731 437 i2c_t *obj;
<> 153:fa9ff456f731 438
<> 153:fa9ff456f731 439 obj_s = (struct i2c_s *)( (char *)hi2c - offsetof(struct i2c_s,handle));
<> 153:fa9ff456f731 440 obj = (i2c_t *)( (char *)obj_s - offsetof(i2c_t,i2c));
<> 153:fa9ff456f731 441
<> 153:fa9ff456f731 442 return (obj);
<> 153:fa9ff456f731 443 }
<> 153:fa9ff456f731 444
<> 156:95d6b41a828b 445 void i2c_reset(i2c_t *obj) {
<> 156:95d6b41a828b 446 struct i2c_s *obj_s = I2C_S(obj);
<> 156:95d6b41a828b 447 /* As recommended in i2c_api.h, mainly send stop */
<> 156:95d6b41a828b 448 i2c_stop(obj);
<> 156:95d6b41a828b 449 /* then re-init */
<> 156:95d6b41a828b 450 i2c_init(obj, obj_s->sda, obj_s->scl);
<> 156:95d6b41a828b 451 }
<> 156:95d6b41a828b 452
<> 153:fa9ff456f731 453 /*
<> 153:fa9ff456f731 454 * UNITARY APIS.
<> 153:fa9ff456f731 455 * For very basic operations, direct registers access is needed
<> 153:fa9ff456f731 456 * There are 2 different IPs version that need to be supported
<> 153:fa9ff456f731 457 */
<> 153:fa9ff456f731 458 #ifdef I2C_IP_VERSION_V1
<> 153:fa9ff456f731 459 int i2c_start(i2c_t *obj) {
<> 153:fa9ff456f731 460
<> 153:fa9ff456f731 461 int timeout;
<> 153:fa9ff456f731 462 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 463 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 464
<> 153:fa9ff456f731 465 // Clear Acknowledge failure flag
<> 153:fa9ff456f731 466 __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
<> 153:fa9ff456f731 467
<> 153:fa9ff456f731 468 // Wait the STOP condition has been previously correctly sent
<> 153:fa9ff456f731 469 // This timeout can be avoid in some specific cases by simply clearing the STOP bit
<> 153:fa9ff456f731 470 timeout = FLAG_TIMEOUT;
<> 153:fa9ff456f731 471 while ((handle->Instance->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) {
<> 153:fa9ff456f731 472 if ((timeout--) == 0) {
<> 153:fa9ff456f731 473 return 1;
<> 153:fa9ff456f731 474 }
<> 153:fa9ff456f731 475 }
<> 153:fa9ff456f731 476
<> 153:fa9ff456f731 477 // Generate the START condition
<> 153:fa9ff456f731 478 handle->Instance->CR1 |= I2C_CR1_START;
<> 153:fa9ff456f731 479
<> 153:fa9ff456f731 480 // Wait the START condition has been correctly sent
<> 153:fa9ff456f731 481 timeout = FLAG_TIMEOUT;
<> 153:fa9ff456f731 482 while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
<> 153:fa9ff456f731 483 if ((timeout--) == 0) {
<> 153:fa9ff456f731 484 return 1;
<> 153:fa9ff456f731 485 }
<> 153:fa9ff456f731 486 }
<> 153:fa9ff456f731 487
<> 153:fa9ff456f731 488 return 0;
<> 153:fa9ff456f731 489 }
<> 153:fa9ff456f731 490
<> 153:fa9ff456f731 491 int i2c_stop(i2c_t *obj) {
<> 153:fa9ff456f731 492 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 493 I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
<> 153:fa9ff456f731 494
<> 153:fa9ff456f731 495 // Generate the STOP condition
<> 153:fa9ff456f731 496 i2c->CR1 |= I2C_CR1_STOP;
<> 153:fa9ff456f731 497
<> 154:37f96f9d4de2 498 /* In case of mixed usage of the APIs (unitary + SYNC)
Kojto 158:b23ee177fd68 499 * re-init HAL state
<> 154:37f96f9d4de2 500 */
<> 154:37f96f9d4de2 501 if(obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME)
<> 154:37f96f9d4de2 502 i2c_init(obj, obj_s->sda, obj_s->scl);
<> 154:37f96f9d4de2 503
<> 153:fa9ff456f731 504 return 0;
<> 153:fa9ff456f731 505 }
<> 153:fa9ff456f731 506
<> 153:fa9ff456f731 507 int i2c_byte_read(i2c_t *obj, int last) {
<> 153:fa9ff456f731 508
<> 153:fa9ff456f731 509 int timeout;
<> 153:fa9ff456f731 510 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 511 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 512
<> 153:fa9ff456f731 513 if (last) {
<> 153:fa9ff456f731 514 // Don't acknowledge the last byte
<> 153:fa9ff456f731 515 handle->Instance->CR1 &= ~I2C_CR1_ACK;
<> 153:fa9ff456f731 516 } else {
<> 153:fa9ff456f731 517 // Acknowledge the byte
<> 153:fa9ff456f731 518 handle->Instance->CR1 |= I2C_CR1_ACK;
<> 153:fa9ff456f731 519 }
<> 153:fa9ff456f731 520
<> 153:fa9ff456f731 521 // Wait until the byte is received
<> 153:fa9ff456f731 522 timeout = FLAG_TIMEOUT;
<> 153:fa9ff456f731 523 while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
<> 153:fa9ff456f731 524 if ((timeout--) == 0) {
<> 153:fa9ff456f731 525 return -1;
<> 153:fa9ff456f731 526 }
<> 153:fa9ff456f731 527 }
<> 153:fa9ff456f731 528
<> 153:fa9ff456f731 529 return (int)handle->Instance->DR;
<> 153:fa9ff456f731 530 }
<> 153:fa9ff456f731 531
<> 153:fa9ff456f731 532 int i2c_byte_write(i2c_t *obj, int data) {
<> 153:fa9ff456f731 533
<> 153:fa9ff456f731 534 int timeout;
<> 153:fa9ff456f731 535 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 536 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 537
<> 153:fa9ff456f731 538 handle->Instance->DR = (uint8_t)data;
<> 153:fa9ff456f731 539
<> 153:fa9ff456f731 540 // Wait until the byte (might be the address) is transmitted
<> 153:fa9ff456f731 541 timeout = FLAG_TIMEOUT;
<> 153:fa9ff456f731 542 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
<> 153:fa9ff456f731 543 (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
<> 153:fa9ff456f731 544 (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) {
<> 153:fa9ff456f731 545 if ((timeout--) == 0) {
<> 156:95d6b41a828b 546 return 2;
<> 153:fa9ff456f731 547 }
<> 153:fa9ff456f731 548 }
<> 153:fa9ff456f731 549
<> 153:fa9ff456f731 550 if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET)
<> 153:fa9ff456f731 551 {
<> 153:fa9ff456f731 552 __HAL_I2C_CLEAR_ADDRFLAG(handle);
<> 153:fa9ff456f731 553 }
<> 153:fa9ff456f731 554
<> 153:fa9ff456f731 555 return 1;
<> 153:fa9ff456f731 556 }
<> 153:fa9ff456f731 557 #endif //I2C_IP_VERSION_V1
<> 153:fa9ff456f731 558 #ifdef I2C_IP_VERSION_V2
<> 156:95d6b41a828b 559
<> 153:fa9ff456f731 560 int i2c_start(i2c_t *obj) {
<> 153:fa9ff456f731 561 struct i2c_s *obj_s = I2C_S(obj);
<> 156:95d6b41a828b 562 /* This I2C IP doesn't */
<> 156:95d6b41a828b 563 obj_s->pending_start = 1;
<> 153:fa9ff456f731 564 return 0;
<> 153:fa9ff456f731 565 }
<> 153:fa9ff456f731 566
<> 153:fa9ff456f731 567 int i2c_stop(i2c_t *obj) {
<> 153:fa9ff456f731 568 struct i2c_s *obj_s = I2C_S(obj);
<> 156:95d6b41a828b 569 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 156:95d6b41a828b 570 int timeout = FLAG_TIMEOUT;
<> 156:95d6b41a828b 571 #if DEVICE_I2CSLAVE
<> 156:95d6b41a828b 572 if (obj_s->slave) {
<> 156:95d6b41a828b 573 /* re-init slave when stop is requested */
<> 156:95d6b41a828b 574 i2c_init(obj, obj_s->sda, obj_s->scl);
<> 156:95d6b41a828b 575 return 0;
<> 156:95d6b41a828b 576 }
<> 156:95d6b41a828b 577 #endif
<> 156:95d6b41a828b 578 // Disable reload mode
<> 156:95d6b41a828b 579 handle->Instance->CR2 &= (uint32_t)~I2C_CR2_RELOAD;
<> 156:95d6b41a828b 580 // Generate the STOP condition
<> 156:95d6b41a828b 581 handle->Instance->CR2 |= I2C_CR2_STOP;
<> 153:fa9ff456f731 582
<> 156:95d6b41a828b 583 timeout = FLAG_TIMEOUT;
<> 156:95d6b41a828b 584 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_STOPF)) {
<> 156:95d6b41a828b 585 if ((timeout--) == 0) {
<> 156:95d6b41a828b 586 return I2C_ERROR_BUS_BUSY;
<> 156:95d6b41a828b 587 }
<> 156:95d6b41a828b 588 }
<> 156:95d6b41a828b 589
<> 156:95d6b41a828b 590 /* Clear STOP Flag */
<> 156:95d6b41a828b 591 __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_STOPF);
<> 156:95d6b41a828b 592
<> 156:95d6b41a828b 593 /* Erase slave address, this wiil be used as a marker
<> 156:95d6b41a828b 594 * to know when we need to prepare next start */
<> 156:95d6b41a828b 595 handle->Instance->CR2 &= ~I2C_CR2_SADD;
<> 156:95d6b41a828b 596
Kojto 158:b23ee177fd68 597 /*
Kojto 158:b23ee177fd68 598 * V2 IP is meant for automatic STOP, not user STOP
Kojto 158:b23ee177fd68 599 * SW reset the IP state machine before next transaction
Kojto 158:b23ee177fd68 600 */
Kojto 158:b23ee177fd68 601 i2c_sw_reset(obj);
Kojto 158:b23ee177fd68 602
<> 156:95d6b41a828b 603 /* In case of mixed usage of the APIs (unitary + SYNC)
Kojto 158:b23ee177fd68 604 * re-init HAL state */
<> 156:95d6b41a828b 605 if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
<> 156:95d6b41a828b 606 i2c_init(obj, obj_s->sda, obj_s->scl);
<> 156:95d6b41a828b 607 }
<> 153:fa9ff456f731 608
<> 153:fa9ff456f731 609 return 0;
<> 153:fa9ff456f731 610 }
<> 153:fa9ff456f731 611
<> 153:fa9ff456f731 612 int i2c_byte_read(i2c_t *obj, int last) {
<> 153:fa9ff456f731 613 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 614 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 156:95d6b41a828b 615 int timeout = FLAG_TIMEOUT;
<> 156:95d6b41a828b 616 uint32_t tmpreg = handle->Instance->CR2;
<> 156:95d6b41a828b 617 char data;
<> 156:95d6b41a828b 618 #if DEVICE_I2CSLAVE
<> 156:95d6b41a828b 619 if (obj_s->slave) {
<> 156:95d6b41a828b 620 return i2c_slave_read(obj, &data, 1);
<> 156:95d6b41a828b 621 }
<> 156:95d6b41a828b 622 #endif
<> 156:95d6b41a828b 623 /* Then send data when there's room in the TX fifo */
<> 156:95d6b41a828b 624 if ((tmpreg & I2C_CR2_RELOAD) != 0) {
<> 156:95d6b41a828b 625 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
<> 156:95d6b41a828b 626 if ((timeout--) == 0) {
<> 156:95d6b41a828b 627 DEBUG_PRINTF("timeout in byte_read\r\n");
<> 156:95d6b41a828b 628 return -1;
<> 156:95d6b41a828b 629 }
<> 156:95d6b41a828b 630 }
<> 156:95d6b41a828b 631 }
<> 153:fa9ff456f731 632
<> 157:ff67d9f36b67 633 /* Enable reload mode as we don't know how many bytes will be sent */
<> 157:ff67d9f36b67 634 /* and set transfer size to 1 */
<> 157:ff67d9f36b67 635 tmpreg |= I2C_CR2_RELOAD | (I2C_CR2_NBYTES & (1 << 16));
<> 156:95d6b41a828b 636 /* Set the prepared configuration */
<> 156:95d6b41a828b 637 handle->Instance->CR2 = tmpreg;
<> 156:95d6b41a828b 638
<> 153:fa9ff456f731 639 timeout = FLAG_TIMEOUT;
<> 156:95d6b41a828b 640 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE)) {
<> 153:fa9ff456f731 641 if ((timeout--) == 0) {
<> 153:fa9ff456f731 642 return -1;
<> 153:fa9ff456f731 643 }
<> 153:fa9ff456f731 644 }
<> 153:fa9ff456f731 645
<> 156:95d6b41a828b 646 /* Then Get Byte */
<> 156:95d6b41a828b 647 data = handle->Instance->RXDR;
<> 156:95d6b41a828b 648
<> 156:95d6b41a828b 649 if (last) {
<> 156:95d6b41a828b 650 /* Disable Address Acknowledge */
<> 156:95d6b41a828b 651 handle->Instance->CR2 |= I2C_CR2_NACK;
<> 156:95d6b41a828b 652 }
<> 156:95d6b41a828b 653
<> 156:95d6b41a828b 654 return data;
<> 153:fa9ff456f731 655 }
<> 153:fa9ff456f731 656
<> 153:fa9ff456f731 657 int i2c_byte_write(i2c_t *obj, int data) {
<> 153:fa9ff456f731 658 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 659 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 156:95d6b41a828b 660 int timeout = FLAG_TIMEOUT;
<> 156:95d6b41a828b 661 uint32_t tmpreg = handle->Instance->CR2;
<> 156:95d6b41a828b 662 #if DEVICE_I2CSLAVE
<> 156:95d6b41a828b 663 if (obj_s->slave) {
<> 156:95d6b41a828b 664 return i2c_slave_write(obj, (char *) &data, 1);
<> 156:95d6b41a828b 665 }
<> 156:95d6b41a828b 666 #endif
<> 156:95d6b41a828b 667 if (obj_s->pending_start) {
<> 156:95d6b41a828b 668 obj_s->pending_start = 0;
<> 156:95d6b41a828b 669 //* First byte after the start is the address */
<> 156:95d6b41a828b 670 tmpreg |= (uint32_t)((uint32_t)data & I2C_CR2_SADD);
<> 156:95d6b41a828b 671 if (data & 0x01) {
<> 156:95d6b41a828b 672 tmpreg |= I2C_CR2_START | I2C_CR2_RD_WRN;
<> 156:95d6b41a828b 673 } else {
<> 156:95d6b41a828b 674 tmpreg |= I2C_CR2_START;
<> 156:95d6b41a828b 675 tmpreg &= ~I2C_CR2_RD_WRN;
<> 156:95d6b41a828b 676 }
<> 156:95d6b41a828b 677 /* Disable reload first to use it later */
<> 156:95d6b41a828b 678 tmpreg &= ~I2C_CR2_RELOAD;
<> 156:95d6b41a828b 679 /* Disable Autoend */
<> 156:95d6b41a828b 680 tmpreg &= ~I2C_CR2_AUTOEND;
<> 156:95d6b41a828b 681 /* Do not set any transfer size for now */
<> 156:95d6b41a828b 682 tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
<> 156:95d6b41a828b 683 /* Set the prepared configuration */
<> 156:95d6b41a828b 684 handle->Instance->CR2 = tmpreg;
<> 156:95d6b41a828b 685 } else {
<> 156:95d6b41a828b 686 /* Set the prepared configuration */
<> 156:95d6b41a828b 687 tmpreg = handle->Instance->CR2;
<> 153:fa9ff456f731 688
<> 156:95d6b41a828b 689 /* Then send data when there's room in the TX fifo */
<> 156:95d6b41a828b 690 if ((tmpreg & I2C_CR2_RELOAD) != 0) {
<> 156:95d6b41a828b 691 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
<> 156:95d6b41a828b 692 if ((timeout--) == 0) {
<> 156:95d6b41a828b 693 DEBUG_PRINTF("timeout in byte_write\r\n");
<> 156:95d6b41a828b 694 return 2;
<> 156:95d6b41a828b 695 }
<> 156:95d6b41a828b 696 }
<> 153:fa9ff456f731 697 }
<> 156:95d6b41a828b 698 /* Enable reload mode as we don't know how many bytes will eb sent */
<> 156:95d6b41a828b 699 tmpreg |= I2C_CR2_RELOAD;
<> 156:95d6b41a828b 700 /* Set transfer size to 1 */
<> 156:95d6b41a828b 701 tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
<> 156:95d6b41a828b 702 /* Set the prepared configuration */
<> 156:95d6b41a828b 703 handle->Instance->CR2 = tmpreg;
<> 156:95d6b41a828b 704 /* Prepare next write */
<> 156:95d6b41a828b 705 timeout = FLAG_TIMEOUT;
<> 156:95d6b41a828b 706 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE)) {
<> 156:95d6b41a828b 707 if ((timeout--) == 0) {
<> 156:95d6b41a828b 708 return 2;
<> 156:95d6b41a828b 709 }
<> 156:95d6b41a828b 710 }
<> 156:95d6b41a828b 711 /* Write byte */
<> 156:95d6b41a828b 712 handle->Instance->TXDR = data;
<> 153:fa9ff456f731 713 }
<> 153:fa9ff456f731 714
<> 153:fa9ff456f731 715 return 1;
<> 153:fa9ff456f731 716 }
<> 153:fa9ff456f731 717 #endif //I2C_IP_VERSION_V2
<> 153:fa9ff456f731 718
<> 153:fa9ff456f731 719 /*
<> 153:fa9ff456f731 720 * SYNC APIS
<> 153:fa9ff456f731 721 */
<> 154:37f96f9d4de2 722 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
<> 154:37f96f9d4de2 723 struct i2c_s *obj_s = I2C_S(obj);
<> 154:37f96f9d4de2 724 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 154:37f96f9d4de2 725 int count = I2C_ERROR_BUS_BUSY, ret = 0;
<> 154:37f96f9d4de2 726 uint32_t timeout = 0;
<> 154:37f96f9d4de2 727
AnnaBridge 178:d650f5d4c87a 728 // Trick to remove compiler warning "left and right operands are identical" in some cases
AnnaBridge 178:d650f5d4c87a 729 uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
AnnaBridge 178:d650f5d4c87a 730 uint32_t op2 = I2C_LAST_FRAME;
AnnaBridge 178:d650f5d4c87a 731 if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
<> 154:37f96f9d4de2 732 if (stop)
<> 154:37f96f9d4de2 733 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
<> 154:37f96f9d4de2 734 else
<> 154:37f96f9d4de2 735 obj_s->XferOperation = I2C_FIRST_FRAME;
<> 154:37f96f9d4de2 736 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
<> 154:37f96f9d4de2 737 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
<> 154:37f96f9d4de2 738 if (stop)
<> 154:37f96f9d4de2 739 obj_s->XferOperation = I2C_LAST_FRAME;
<> 154:37f96f9d4de2 740 else
<> 154:37f96f9d4de2 741 obj_s->XferOperation = I2C_NEXT_FRAME;
<> 154:37f96f9d4de2 742 }
<> 154:37f96f9d4de2 743
<> 154:37f96f9d4de2 744 obj_s->event = 0;
<> 154:37f96f9d4de2 745
<> 154:37f96f9d4de2 746 /* Activate default IRQ handlers for sync mode
<> 154:37f96f9d4de2 747 * which would be overwritten in async mode
<> 154:37f96f9d4de2 748 */
<> 154:37f96f9d4de2 749 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
<> 154:37f96f9d4de2 750
<> 154:37f96f9d4de2 751 ret = HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
<> 154:37f96f9d4de2 752
<> 154:37f96f9d4de2 753 if(ret == HAL_OK) {
<> 154:37f96f9d4de2 754 timeout = BYTE_TIMEOUT_US * (length + 1);
<> 154:37f96f9d4de2 755 /* transfer started : wait completion or timeout */
<> 154:37f96f9d4de2 756 while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
<> 154:37f96f9d4de2 757 wait_us(1);
<> 154:37f96f9d4de2 758 }
<> 154:37f96f9d4de2 759
<> 154:37f96f9d4de2 760 i2c_ev_err_disable(obj);
<> 154:37f96f9d4de2 761
<> 154:37f96f9d4de2 762 if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
<> 154:37f96f9d4de2 763 DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n");
<> 154:37f96f9d4de2 764 /* re-init IP to try and get back in a working state */
<> 154:37f96f9d4de2 765 i2c_init(obj, obj_s->sda, obj_s->scl);
<> 154:37f96f9d4de2 766 } else {
<> 154:37f96f9d4de2 767 count = length;
<> 154:37f96f9d4de2 768 }
<> 154:37f96f9d4de2 769 } else {
<> 154:37f96f9d4de2 770 DEBUG_PRINTF("ERROR in i2c_read:%d\r\n", ret);
<> 154:37f96f9d4de2 771 }
<> 154:37f96f9d4de2 772
<> 154:37f96f9d4de2 773 return count;
<> 154:37f96f9d4de2 774 }
<> 154:37f96f9d4de2 775
<> 153:fa9ff456f731 776 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
<> 153:fa9ff456f731 777 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 778 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 154:37f96f9d4de2 779 int count = I2C_ERROR_BUS_BUSY, ret = 0;
<> 153:fa9ff456f731 780 uint32_t timeout = 0;
<> 153:fa9ff456f731 781
AnnaBridge 178:d650f5d4c87a 782 // Trick to remove compiler warning "left and right operands are identical" in some cases
AnnaBridge 178:d650f5d4c87a 783 uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
AnnaBridge 178:d650f5d4c87a 784 uint32_t op2 = I2C_LAST_FRAME;
AnnaBridge 178:d650f5d4c87a 785 if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
<> 153:fa9ff456f731 786 if (stop)
<> 153:fa9ff456f731 787 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
<> 153:fa9ff456f731 788 else
<> 153:fa9ff456f731 789 obj_s->XferOperation = I2C_FIRST_FRAME;
<> 153:fa9ff456f731 790 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
<> 153:fa9ff456f731 791 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
<> 153:fa9ff456f731 792 if (stop)
<> 153:fa9ff456f731 793 obj_s->XferOperation = I2C_LAST_FRAME;
<> 153:fa9ff456f731 794 else
<> 153:fa9ff456f731 795 obj_s->XferOperation = I2C_NEXT_FRAME;
<> 153:fa9ff456f731 796 }
<> 153:fa9ff456f731 797
<> 153:fa9ff456f731 798 obj_s->event = 0;
<> 153:fa9ff456f731 799
<> 153:fa9ff456f731 800 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
<> 153:fa9ff456f731 801
<> 153:fa9ff456f731 802 ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
<> 153:fa9ff456f731 803
<> 153:fa9ff456f731 804 if(ret == HAL_OK) {
<> 154:37f96f9d4de2 805 timeout = BYTE_TIMEOUT_US * (length + 1);
<> 153:fa9ff456f731 806 /* transfer started : wait completion or timeout */
<> 153:fa9ff456f731 807 while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
<> 153:fa9ff456f731 808 wait_us(1);
<> 153:fa9ff456f731 809 }
<> 153:fa9ff456f731 810
<> 153:fa9ff456f731 811 i2c_ev_err_disable(obj);
<> 153:fa9ff456f731 812
<> 153:fa9ff456f731 813 if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
<> 153:fa9ff456f731 814 DEBUG_PRINTF(" TIMEOUT or error in i2c_write\r\n");
<> 153:fa9ff456f731 815 /* re-init IP to try and get back in a working state */
<> 153:fa9ff456f731 816 i2c_init(obj, obj_s->sda, obj_s->scl);
<> 153:fa9ff456f731 817 } else {
<> 153:fa9ff456f731 818 count = length;
<> 153:fa9ff456f731 819 }
<> 153:fa9ff456f731 820 } else {
<> 153:fa9ff456f731 821 DEBUG_PRINTF("ERROR in i2c_read\r\n");
<> 153:fa9ff456f731 822 }
<> 153:fa9ff456f731 823
<> 153:fa9ff456f731 824 return count;
<> 153:fa9ff456f731 825 }
<> 153:fa9ff456f731 826
<> 153:fa9ff456f731 827 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){
<> 153:fa9ff456f731 828 /* Get object ptr based on handler ptr */
<> 153:fa9ff456f731 829 i2c_t *obj = get_i2c_obj(hi2c);
<> 153:fa9ff456f731 830 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 831
<> 153:fa9ff456f731 832 #if DEVICE_I2C_ASYNCH
<> 153:fa9ff456f731 833 /* Handle potential Tx/Rx use case */
<> 153:fa9ff456f731 834 if ((obj->tx_buff.length) && (obj->rx_buff.length)) {
<> 153:fa9ff456f731 835 if (obj_s->stop) {
<> 153:fa9ff456f731 836 obj_s->XferOperation = I2C_LAST_FRAME;
<> 153:fa9ff456f731 837 } else {
<> 153:fa9ff456f731 838 obj_s->XferOperation = I2C_NEXT_FRAME;
<> 153:fa9ff456f731 839 }
<> 153:fa9ff456f731 840
<> 153:fa9ff456f731 841 HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t*)obj->rx_buff.buffer , obj->rx_buff.length, obj_s->XferOperation);
<> 153:fa9ff456f731 842 }
<> 153:fa9ff456f731 843 else
<> 153:fa9ff456f731 844 #endif
<> 153:fa9ff456f731 845 {
<> 153:fa9ff456f731 846 /* Set event flag */
<> 153:fa9ff456f731 847 obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
<> 153:fa9ff456f731 848 }
<> 153:fa9ff456f731 849 }
<> 153:fa9ff456f731 850
<> 153:fa9ff456f731 851 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c){
<> 153:fa9ff456f731 852 /* Get object ptr based on handler ptr */
<> 153:fa9ff456f731 853 i2c_t *obj = get_i2c_obj(hi2c);
<> 153:fa9ff456f731 854 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 855
<> 153:fa9ff456f731 856 /* Set event flag */
<> 153:fa9ff456f731 857 obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
<> 153:fa9ff456f731 858 }
<> 153:fa9ff456f731 859
<> 153:fa9ff456f731 860 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){
<> 153:fa9ff456f731 861 /* Get object ptr based on handler ptr */
<> 153:fa9ff456f731 862 i2c_t *obj = get_i2c_obj(hi2c);
<> 153:fa9ff456f731 863 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 864 #if DEVICE_I2CSLAVE
<> 153:fa9ff456f731 865 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 866 uint32_t address = 0;
<> 153:fa9ff456f731 867 /* Store address to handle it after reset */
<> 153:fa9ff456f731 868 if(obj_s->slave)
<> 153:fa9ff456f731 869 address = handle->Init.OwnAddress1;
<> 153:fa9ff456f731 870 #endif
<> 153:fa9ff456f731 871
<> 153:fa9ff456f731 872 DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index);
<> 153:fa9ff456f731 873
<> 153:fa9ff456f731 874 /* re-init IP to try and get back in a working state */
<> 153:fa9ff456f731 875 i2c_init(obj, obj_s->sda, obj_s->scl);
<> 153:fa9ff456f731 876
<> 153:fa9ff456f731 877 #if DEVICE_I2CSLAVE
<> 153:fa9ff456f731 878 /* restore slave address */
<> 162:e13f6fdb2ac4 879 if (address != 0) {
<> 162:e13f6fdb2ac4 880 obj_s->slave = 1;
<> 162:e13f6fdb2ac4 881 i2c_slave_address(obj, 0, address, 0);
<> 162:e13f6fdb2ac4 882 }
<> 153:fa9ff456f731 883 #endif
<> 153:fa9ff456f731 884
<> 153:fa9ff456f731 885 /* Keep Set event flag */
<> 153:fa9ff456f731 886 obj_s->event = I2C_EVENT_ERROR;
<> 153:fa9ff456f731 887 }
<> 153:fa9ff456f731 888
<> 153:fa9ff456f731 889 #if DEVICE_I2CSLAVE
<> 153:fa9ff456f731 890 /* SLAVE API FUNCTIONS */
<> 153:fa9ff456f731 891 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
<> 153:fa9ff456f731 892 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 893 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 894
<> 153:fa9ff456f731 895 // I2C configuration
<> 153:fa9ff456f731 896 handle->Init.OwnAddress1 = address;
<> 153:fa9ff456f731 897 HAL_I2C_Init(handle);
<> 153:fa9ff456f731 898
<> 153:fa9ff456f731 899 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
<> 153:fa9ff456f731 900
<> 153:fa9ff456f731 901 HAL_I2C_EnableListen_IT(handle);
<> 153:fa9ff456f731 902 }
<> 153:fa9ff456f731 903
<> 153:fa9ff456f731 904 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
<> 153:fa9ff456f731 905
<> 153:fa9ff456f731 906 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 907 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 908
<> 153:fa9ff456f731 909 if (enable_slave) {
<> 153:fa9ff456f731 910 obj_s->slave = 1;
<> 153:fa9ff456f731 911 HAL_I2C_EnableListen_IT(handle);
<> 153:fa9ff456f731 912 } else {
<> 153:fa9ff456f731 913 obj_s->slave = 0;
<> 153:fa9ff456f731 914 HAL_I2C_DisableListen_IT(handle);
<> 153:fa9ff456f731 915 }
<> 153:fa9ff456f731 916 }
<> 153:fa9ff456f731 917
<> 153:fa9ff456f731 918 // See I2CSlave.h
<> 153:fa9ff456f731 919 #define NoData 0 // the slave has not been addressed
<> 153:fa9ff456f731 920 #define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
<> 153:fa9ff456f731 921 #define WriteGeneral 2 // the master is writing to all slave
<> 153:fa9ff456f731 922 #define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
<> 153:fa9ff456f731 923
<> 153:fa9ff456f731 924
<> 153:fa9ff456f731 925 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) {
<> 153:fa9ff456f731 926 /* Get object ptr based on handler ptr */
<> 153:fa9ff456f731 927 i2c_t *obj = get_i2c_obj(hi2c);
<> 153:fa9ff456f731 928 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 929
<> 153:fa9ff456f731 930 /* Transfer direction in HAL is from Master point of view */
<> 153:fa9ff456f731 931 if(TransferDirection == I2C_DIRECTION_RECEIVE) {
<> 153:fa9ff456f731 932 obj_s->pending_slave_tx_master_rx = 1;
<> 153:fa9ff456f731 933 }
<> 153:fa9ff456f731 934
<> 153:fa9ff456f731 935 if(TransferDirection == I2C_DIRECTION_TRANSMIT) {
<> 153:fa9ff456f731 936 obj_s->pending_slave_rx_maxter_tx = 1;
<> 153:fa9ff456f731 937 }
<> 153:fa9ff456f731 938 }
<> 153:fa9ff456f731 939
<> 153:fa9ff456f731 940 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle){
<> 153:fa9ff456f731 941 /* Get object ptr based on handler ptr */
<> 153:fa9ff456f731 942 i2c_t *obj = get_i2c_obj(I2cHandle);
<> 153:fa9ff456f731 943 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 944 obj_s->pending_slave_tx_master_rx = 0;
<> 153:fa9ff456f731 945 }
<> 153:fa9ff456f731 946
<> 153:fa9ff456f731 947 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle){
<> 153:fa9ff456f731 948 /* Get object ptr based on handler ptr */
<> 153:fa9ff456f731 949 i2c_t *obj = get_i2c_obj(I2cHandle);
<> 153:fa9ff456f731 950 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 951 obj_s->pending_slave_rx_maxter_tx = 0;
<> 153:fa9ff456f731 952 }
<> 153:fa9ff456f731 953
<> 153:fa9ff456f731 954 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
<> 153:fa9ff456f731 955 {
<> 153:fa9ff456f731 956 /* restart listening for master requests */
<> 153:fa9ff456f731 957 HAL_I2C_EnableListen_IT(hi2c);
<> 153:fa9ff456f731 958 }
<> 153:fa9ff456f731 959
<> 153:fa9ff456f731 960 int i2c_slave_receive(i2c_t *obj) {
<> 153:fa9ff456f731 961
<> 153:fa9ff456f731 962 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 963 int retValue = NoData;
<> 153:fa9ff456f731 964
<> 153:fa9ff456f731 965 if(obj_s->pending_slave_rx_maxter_tx) {
<> 153:fa9ff456f731 966 retValue = WriteAddressed;
<> 153:fa9ff456f731 967 }
<> 153:fa9ff456f731 968
<> 153:fa9ff456f731 969 if(obj_s->pending_slave_tx_master_rx) {
<> 153:fa9ff456f731 970 retValue = ReadAddressed;
<> 153:fa9ff456f731 971 }
<> 153:fa9ff456f731 972
<> 153:fa9ff456f731 973 return (retValue);
<> 153:fa9ff456f731 974 }
<> 153:fa9ff456f731 975
<> 153:fa9ff456f731 976 int i2c_slave_read(i2c_t *obj, char *data, int length) {
<> 153:fa9ff456f731 977 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 978 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 979 int count = 0;
<> 153:fa9ff456f731 980 int ret = 0;
<> 153:fa9ff456f731 981 uint32_t timeout = 0;
<> 153:fa9ff456f731 982
<> 153:fa9ff456f731 983 /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
<> 153:fa9ff456f731 984 ret = HAL_I2C_Slave_Sequential_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
<> 153:fa9ff456f731 985
<> 153:fa9ff456f731 986 if(ret == HAL_OK) {
<> 154:37f96f9d4de2 987 timeout = BYTE_TIMEOUT_US * (length + 1);
<> 153:fa9ff456f731 988 while(obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) {
<> 153:fa9ff456f731 989 wait_us(1);
<> 153:fa9ff456f731 990 }
<> 153:fa9ff456f731 991
<> 153:fa9ff456f731 992 if(timeout != 0) {
<> 153:fa9ff456f731 993 count = length;
<> 153:fa9ff456f731 994 } else {
<> 153:fa9ff456f731 995 DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n");
<> 153:fa9ff456f731 996 }
<> 153:fa9ff456f731 997 }
<> 153:fa9ff456f731 998 return count;
<> 153:fa9ff456f731 999 }
<> 153:fa9ff456f731 1000
<> 153:fa9ff456f731 1001 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
<> 153:fa9ff456f731 1002 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 1003 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 1004 int count = 0;
<> 153:fa9ff456f731 1005 int ret = 0;
<> 153:fa9ff456f731 1006 uint32_t timeout = 0;
<> 153:fa9ff456f731 1007
<> 153:fa9ff456f731 1008 /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
<> 153:fa9ff456f731 1009 ret = HAL_I2C_Slave_Sequential_Transmit_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
<> 153:fa9ff456f731 1010
<> 153:fa9ff456f731 1011 if(ret == HAL_OK) {
<> 154:37f96f9d4de2 1012 timeout = BYTE_TIMEOUT_US * (length + 1);
<> 153:fa9ff456f731 1013 while(obj_s->pending_slave_tx_master_rx && (--timeout != 0)) {
<> 153:fa9ff456f731 1014 wait_us(1);
<> 153:fa9ff456f731 1015 }
<> 153:fa9ff456f731 1016
<> 153:fa9ff456f731 1017 if(timeout != 0) {
<> 153:fa9ff456f731 1018 count = length;
<> 153:fa9ff456f731 1019 } else {
<> 153:fa9ff456f731 1020 DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n");
<> 153:fa9ff456f731 1021 }
<> 153:fa9ff456f731 1022 }
<> 153:fa9ff456f731 1023
<> 153:fa9ff456f731 1024 return count;
<> 153:fa9ff456f731 1025 }
<> 153:fa9ff456f731 1026 #endif // DEVICE_I2CSLAVE
<> 153:fa9ff456f731 1027
<> 153:fa9ff456f731 1028 #if DEVICE_I2C_ASYNCH
<> 153:fa9ff456f731 1029 /* ASYNCH MASTER API FUNCTIONS */
<> 153:fa9ff456f731 1030 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){
<> 153:fa9ff456f731 1031 /* Get object ptr based on handler ptr */
<> 153:fa9ff456f731 1032 i2c_t *obj = get_i2c_obj(hi2c);
<> 153:fa9ff456f731 1033 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 1034 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 1035
<> 153:fa9ff456f731 1036 /* Disable IT. Not always done before calling macro */
<> 153:fa9ff456f731 1037 __HAL_I2C_DISABLE_IT(handle, I2C_IT_ALL);
<> 153:fa9ff456f731 1038 i2c_ev_err_disable(obj);
<> 153:fa9ff456f731 1039
<> 153:fa9ff456f731 1040 /* Set event flag */
<> 153:fa9ff456f731 1041 obj_s->event = I2C_EVENT_ERROR;
<> 153:fa9ff456f731 1042 }
<> 153:fa9ff456f731 1043
<> 153:fa9ff456f731 1044 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) {
<> 153:fa9ff456f731 1045
<> 153:fa9ff456f731 1046 // TODO: DMA usage is currently ignored by this way
<> 153:fa9ff456f731 1047 (void) hint;
<> 153:fa9ff456f731 1048
<> 153:fa9ff456f731 1049 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 1050 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 1051
<> 153:fa9ff456f731 1052 /* Update object */
<> 153:fa9ff456f731 1053 obj->tx_buff.buffer = (void *)tx;
<> 153:fa9ff456f731 1054 obj->tx_buff.length = tx_length;
<> 153:fa9ff456f731 1055 obj->tx_buff.pos = 0;
<> 153:fa9ff456f731 1056 obj->tx_buff.width = 8;
<> 153:fa9ff456f731 1057
<> 153:fa9ff456f731 1058 obj->rx_buff.buffer = (void *)rx;
<> 153:fa9ff456f731 1059 obj->rx_buff.length = rx_length;
<> 153:fa9ff456f731 1060 obj->rx_buff.pos = SIZE_MAX;
<> 153:fa9ff456f731 1061 obj->rx_buff.width = 8;
<> 153:fa9ff456f731 1062
<> 153:fa9ff456f731 1063 obj_s->available_events = event;
<> 153:fa9ff456f731 1064 obj_s->event = 0;
<> 153:fa9ff456f731 1065 obj_s->address = address;
<> 153:fa9ff456f731 1066 obj_s->stop = stop;
<> 153:fa9ff456f731 1067
<> 153:fa9ff456f731 1068 i2c_ev_err_enable(obj, handler);
<> 153:fa9ff456f731 1069
<> 153:fa9ff456f731 1070 /* Set operation step depending if stop sending required or not */
<> 153:fa9ff456f731 1071 if ((tx_length && !rx_length) || (!tx_length && rx_length)) {
AnnaBridge 178:d650f5d4c87a 1072 // Trick to remove compiler warning "left and right operands are identical" in some cases
AnnaBridge 178:d650f5d4c87a 1073 uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
AnnaBridge 178:d650f5d4c87a 1074 uint32_t op2 = I2C_LAST_FRAME;
AnnaBridge 178:d650f5d4c87a 1075 if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
<> 153:fa9ff456f731 1076 if (stop)
<> 153:fa9ff456f731 1077 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
<> 153:fa9ff456f731 1078 else
<> 153:fa9ff456f731 1079 obj_s->XferOperation = I2C_FIRST_FRAME;
<> 153:fa9ff456f731 1080 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
<> 153:fa9ff456f731 1081 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
<> 153:fa9ff456f731 1082 if (stop)
<> 153:fa9ff456f731 1083 obj_s->XferOperation = I2C_LAST_FRAME;
<> 153:fa9ff456f731 1084 else
<> 153:fa9ff456f731 1085 obj_s->XferOperation = I2C_NEXT_FRAME;
<> 153:fa9ff456f731 1086 }
<> 153:fa9ff456f731 1087
<> 153:fa9ff456f731 1088 if (tx_length > 0) {
<> 153:fa9ff456f731 1089 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, obj_s->XferOperation);
<> 153:fa9ff456f731 1090 }
<> 153:fa9ff456f731 1091 if (rx_length > 0) {
<> 153:fa9ff456f731 1092 HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t*)rx, rx_length, obj_s->XferOperation);
<> 153:fa9ff456f731 1093 }
<> 153:fa9ff456f731 1094 }
<> 153:fa9ff456f731 1095 else if (tx_length && rx_length) {
<> 153:fa9ff456f731 1096 /* Two steps operation, don't modify XferOperation, keep it for next step */
AnnaBridge 178:d650f5d4c87a 1097 // Trick to remove compiler warning "left and right operands are identical" in some cases
AnnaBridge 178:d650f5d4c87a 1098 uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
AnnaBridge 178:d650f5d4c87a 1099 uint32_t op2 = I2C_LAST_FRAME;
AnnaBridge 178:d650f5d4c87a 1100 if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
<> 153:fa9ff456f731 1101 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_FIRST_FRAME);
<> 153:fa9ff456f731 1102 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
<> 153:fa9ff456f731 1103 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
<> 153:fa9ff456f731 1104 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_NEXT_FRAME);
<> 153:fa9ff456f731 1105 }
<> 153:fa9ff456f731 1106 }
<> 153:fa9ff456f731 1107 }
<> 153:fa9ff456f731 1108
<> 153:fa9ff456f731 1109
<> 153:fa9ff456f731 1110 uint32_t i2c_irq_handler_asynch(i2c_t *obj) {
<> 153:fa9ff456f731 1111
<> 153:fa9ff456f731 1112 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 1113 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 1114
<> 153:fa9ff456f731 1115 HAL_I2C_EV_IRQHandler(handle);
<> 153:fa9ff456f731 1116 HAL_I2C_ER_IRQHandler(handle);
<> 153:fa9ff456f731 1117
<> 153:fa9ff456f731 1118 /* Return I2C event status */
<> 153:fa9ff456f731 1119 return (obj_s->event & obj_s->available_events);
<> 153:fa9ff456f731 1120 }
<> 153:fa9ff456f731 1121
<> 153:fa9ff456f731 1122 uint8_t i2c_active(i2c_t *obj) {
<> 153:fa9ff456f731 1123
<> 153:fa9ff456f731 1124 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 1125 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 1126
<> 153:fa9ff456f731 1127 if (handle->State == HAL_I2C_STATE_READY) {
<> 153:fa9ff456f731 1128 return 0;
<> 153:fa9ff456f731 1129 }
<> 153:fa9ff456f731 1130 else {
<> 153:fa9ff456f731 1131 return 1;
<> 153:fa9ff456f731 1132 }
<> 153:fa9ff456f731 1133 }
<> 153:fa9ff456f731 1134
<> 153:fa9ff456f731 1135 void i2c_abort_asynch(i2c_t *obj) {
<> 153:fa9ff456f731 1136
<> 153:fa9ff456f731 1137 struct i2c_s *obj_s = I2C_S(obj);
<> 153:fa9ff456f731 1138 I2C_HandleTypeDef *handle = &(obj_s->handle);
<> 153:fa9ff456f731 1139
<> 153:fa9ff456f731 1140 /* Abort HAL requires DevAddress, but is not used. Use Dummy */
<> 153:fa9ff456f731 1141 uint16_t Dummy_DevAddress = 0x00;
<> 153:fa9ff456f731 1142
<> 153:fa9ff456f731 1143 HAL_I2C_Master_Abort_IT(handle, Dummy_DevAddress);
<> 153:fa9ff456f731 1144 }
<> 153:fa9ff456f731 1145
<> 153:fa9ff456f731 1146 #endif // DEVICE_I2C_ASYNCH
<> 153:fa9ff456f731 1147
<> 153:fa9ff456f731 1148 #endif // DEVICE_I2C