Caroline BONHOMME / Mbed 2 deprecated ProjetRFID

projet rfid

Dependencies:   BSP_DISCO_F429ZI LCD_DISCO_F429ZI mbed

MFRC522.h@0:7321514266d7, 2018-03-15 (annotated)

Committer:
Carobon
Date:
Thu Mar 15 08:50:12 2018 +0000
Revision:
0:7321514266d7
STM32RC522

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Carobon 0:7321514266d7 1 /**
Carobon 0:7321514266d7 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
Carobon 0:7321514266d7 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
Carobon 0:7321514266d7 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
Carobon 0:7321514266d7 5 * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
Carobon 0:7321514266d7 6 * Ported to mbed by Martin Olejar, Dec, 2013
Carobon 0:7321514266d7 7 *
Carobon 0:7321514266d7 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
Carobon 0:7321514266d7 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
Carobon 0:7321514266d7 10 *
Carobon 0:7321514266d7 11 * There are three hardware components involved:
Carobon 0:7321514266d7 12 * 1) The micro controller: An Arduino
Carobon 0:7321514266d7 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
Carobon 0:7321514266d7 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
Carobon 0:7321514266d7 15 *
Carobon 0:7321514266d7 16 * The microcontroller and card reader uses SPI for communication.
Carobon 0:7321514266d7 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
Carobon 0:7321514266d7 18 *
Carobon 0:7321514266d7 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
Carobon 0:7321514266d7 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
Carobon 0:7321514266d7 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
Carobon 0:7321514266d7 22 * Details are found in chapter 6, Type A: Initialization and anticollision.
Carobon 0:7321514266d7 23 *
Carobon 0:7321514266d7 24 * If only the PICC UID is wanted, the above documents has all the needed information.
Carobon 0:7321514266d7 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
Carobon 0:7321514266d7 26 * The MIFARE Classic chips and protocol is described in the datasheets:
Carobon 0:7321514266d7 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
Carobon 0:7321514266d7 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
Carobon 0:7321514266d7 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
Carobon 0:7321514266d7 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
Carobon 0:7321514266d7 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
Carobon 0:7321514266d7 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
Carobon 0:7321514266d7 33 *
Carobon 0:7321514266d7 34 * MIFARE Classic 1K (MF1S503x):
Carobon 0:7321514266d7 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
Carobon 0:7321514266d7 36 * The blocks are numbered 0-63.
Carobon 0:7321514266d7 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
Carobon 0:7321514266d7 38 * Bytes 0-5: Key A
Carobon 0:7321514266d7 39 * Bytes 6-8: Access Bits
Carobon 0:7321514266d7 40 * Bytes 9: User data
Carobon 0:7321514266d7 41 * Bytes 10-15: Key B (or user data)
Carobon 0:7321514266d7 42 * Block 0 is read only manufacturer data.
Carobon 0:7321514266d7 43 * To access a block, an authentication using a key from the block's sector must be performed first.
Carobon 0:7321514266d7 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
Carobon 0:7321514266d7 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
Carobon 0:7321514266d7 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
Carobon 0:7321514266d7 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
Carobon 0:7321514266d7 48 * MIFARE Classic 4K (MF1S703x):
Carobon 0:7321514266d7 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
Carobon 0:7321514266d7 50 * The blocks are numbered 0-255.
Carobon 0:7321514266d7 51 * The last block in each sector is the Sector Trailer like above.
Carobon 0:7321514266d7 52 * MIFARE Classic Mini (MF1 IC S20):
Carobon 0:7321514266d7 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
Carobon 0:7321514266d7 54 * The blocks are numbered 0-19.
Carobon 0:7321514266d7 55 * The last block in each sector is the Sector Trailer like above.
Carobon 0:7321514266d7 56 *
Carobon 0:7321514266d7 57 * MIFARE Ultralight (MF0ICU1):
Carobon 0:7321514266d7 58 * Has 16 pages of 4 bytes = 64 bytes.
Carobon 0:7321514266d7 59 * Pages 0 + 1 is used for the 7-byte UID.
Carobon 0:7321514266d7 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
Carobon 0:7321514266d7 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
Carobon 0:7321514266d7 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
Carobon 0:7321514266d7 63 * MIFARE Ultralight C (MF0ICU2):
Carobon 0:7321514266d7 64 * Has 48 pages of 4 bytes = 64 bytes.
Carobon 0:7321514266d7 65 * Pages 0 + 1 is used for the 7-byte UID.
Carobon 0:7321514266d7 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
Carobon 0:7321514266d7 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
Carobon 0:7321514266d7 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
Carobon 0:7321514266d7 69 * Page 40 Lock bytes
Carobon 0:7321514266d7 70 * Page 41 16 bit one way counter
Carobon 0:7321514266d7 71 * Pages 42-43 Authentication configuration
Carobon 0:7321514266d7 72 * Pages 44-47 Authentication key
Carobon 0:7321514266d7 73 */
Carobon 0:7321514266d7 74 #ifndef MFRC522_h
Carobon 0:7321514266d7 75 #define MFRC522_h
Carobon 0:7321514266d7 76
Carobon 0:7321514266d7 77 #include "mbed.h"
Carobon 0:7321514266d7 78
Carobon 0:7321514266d7 79 /**
Carobon 0:7321514266d7 80 * MFRC522 example
Carobon 0:7321514266d7 81 *
Carobon 0:7321514266d7 82 * @code
Carobon 0:7321514266d7 83 * #include "mbed.h"
Carobon 0:7321514266d7 84 * #include "MFRC522.h"
Carobon 0:7321514266d7 85 *
Carobon 0:7321514266d7 86 * //KL25Z Pins for MFRC522 SPI interface
Carobon 0:7321514266d7 87 * #define SPI_MOSI PTC6
Carobon 0:7321514266d7 88 * #define SPI_MISO PTC7
Carobon 0:7321514266d7 89 * #define SPI_SCLK PTC5
Carobon 0:7321514266d7 90 * #define SPI_CS PTC4
Carobon 0:7321514266d7 91 * // KL25Z Pin for MFRC522 reset
Carobon 0:7321514266d7 92 * #define MF_RESET PTC3
Carobon 0:7321514266d7 93 * // KL25Z Pins for Debug UART port
Carobon 0:7321514266d7 94 * #define UART_RX PTA1
Carobon 0:7321514266d7 95 * #define UART_TX PTA2
Carobon 0:7321514266d7 96 *
Carobon 0:7321514266d7 97 * DigitalOut LedRed (LED_RED);
Carobon 0:7321514266d7 98 * DigitalOut LedGreen (LED_GREEN);
Carobon 0:7321514266d7 99 *
Carobon 0:7321514266d7 100 * Serial DebugUART(UART_TX, UART_RX);
Carobon 0:7321514266d7 101 * MFRC522 RfChip (SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS, MF_RESET);
Carobon 0:7321514266d7 102 *
Carobon 0:7321514266d7 103 * int main(void) {
Carobon 0:7321514266d7 104 * // Set debug UART speed
Carobon 0:7321514266d7 105 * DebugUART.baud(115200);
Carobon 0:7321514266d7 106 *
Carobon 0:7321514266d7 107 * // Init. RC522 Chip
Carobon 0:7321514266d7 108 * RfChip.PCD_Init();
Carobon 0:7321514266d7 109 *
Carobon 0:7321514266d7 110 * while (true) {
Carobon 0:7321514266d7 111 * LedRed = 1;
Carobon 0:7321514266d7 112 * LedGreen = 1;
Carobon 0:7321514266d7 113 *
Carobon 0:7321514266d7 114 * // Look for new cards
Carobon 0:7321514266d7 115 * if ( ! RfChip.PICC_IsNewCardPresent())
Carobon 0:7321514266d7 116 * {
Carobon 0:7321514266d7 117 * wait_ms(500);
Carobon 0:7321514266d7 118 * continue;
Carobon 0:7321514266d7 119 * }
Carobon 0:7321514266d7 120 *
Carobon 0:7321514266d7 121 * LedRed = 0;
Carobon 0:7321514266d7 122 *
Carobon 0:7321514266d7 123 * // Select one of the cards
Carobon 0:7321514266d7 124 * if ( ! RfChip.PICC_ReadCardSerial())
Carobon 0:7321514266d7 125 * {
Carobon 0:7321514266d7 126 * wait_ms(500);
Carobon 0:7321514266d7 127 * continue;
Carobon 0:7321514266d7 128 * }
Carobon 0:7321514266d7 129 *
Carobon 0:7321514266d7 130 * LedRed = 1;
Carobon 0:7321514266d7 131 * LedGreen = 0;
Carobon 0:7321514266d7 132 *
Carobon 0:7321514266d7 133 * // Print Card UID
Carobon 0:7321514266d7 134 * printf("Card UID: ");
Carobon 0:7321514266d7 135 * for (uint8_t i = 0; i < RfChip.uid.size; i++)
Carobon 0:7321514266d7 136 * {
Carobon 0:7321514266d7 137 * printf(" %X02", RfChip.uid.uidByte[i]);
Carobon 0:7321514266d7 138 * }
Carobon 0:7321514266d7 139 * printf("\n\r");
Carobon 0:7321514266d7 140 *
Carobon 0:7321514266d7 141 * // Print Card type
Carobon 0:7321514266d7 142 * uint8_t piccType = RfChip.PICC_GetType(RfChip.uid.sak);
Carobon 0:7321514266d7 143 * printf("PICC Type: %s \n\r", RfChip.PICC_GetTypeName(piccType));
Carobon 0:7321514266d7 144 * wait_ms(1000);
Carobon 0:7321514266d7 145 * }
Carobon 0:7321514266d7 146 * }
Carobon 0:7321514266d7 147 * @endcode
Carobon 0:7321514266d7 148 */
Carobon 0:7321514266d7 149
Carobon 0:7321514266d7 150 class MFRC522 {
Carobon 0:7321514266d7 151 public:
Carobon 0:7321514266d7 152
Carobon 0:7321514266d7 153 /**
Carobon 0:7321514266d7 154 * MFRC522 registers (described in chapter 9 of the datasheet).
Carobon 0:7321514266d7 155 * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
Carobon 0:7321514266d7 156 */
Carobon 0:7321514266d7 157 enum PCD_Register {
Carobon 0:7321514266d7 158 // Page 0: Command and status
Carobon 0:7321514266d7 159 // 0x00 // reserved for future use
Carobon 0:7321514266d7 160 CommandReg = 0x01 << 1, // starts and stops command execution
Carobon 0:7321514266d7 161 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
Carobon 0:7321514266d7 162 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
Carobon 0:7321514266d7 163 ComIrqReg = 0x04 << 1, // interrupt request bits
Carobon 0:7321514266d7 164 DivIrqReg = 0x05 << 1, // interrupt request bits
Carobon 0:7321514266d7 165 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
Carobon 0:7321514266d7 166 Status1Reg = 0x07 << 1, // communication status bits
Carobon 0:7321514266d7 167 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
Carobon 0:7321514266d7 168 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
Carobon 0:7321514266d7 169 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
Carobon 0:7321514266d7 170 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
Carobon 0:7321514266d7 171 ControlReg = 0x0C << 1, // miscellaneous control registers
Carobon 0:7321514266d7 172 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
Carobon 0:7321514266d7 173 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
Carobon 0:7321514266d7 174 // 0x0F // reserved for future use
Carobon 0:7321514266d7 175
Carobon 0:7321514266d7 176 // Page 1:Command
Carobon 0:7321514266d7 177 // 0x10 // reserved for future use
Carobon 0:7321514266d7 178 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
Carobon 0:7321514266d7 179 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
Carobon 0:7321514266d7 180 RxModeReg = 0x13 << 1, // defines reception data rate and framing
Carobon 0:7321514266d7 181 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
Carobon 0:7321514266d7 182 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
Carobon 0:7321514266d7 183 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
Carobon 0:7321514266d7 184 RxSelReg = 0x17 << 1, // selects internal receiver settings
Carobon 0:7321514266d7 185 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
Carobon 0:7321514266d7 186 DemodReg = 0x19 << 1, // defines demodulator settings
Carobon 0:7321514266d7 187 // 0x1A // reserved for future use
Carobon 0:7321514266d7 188 // 0x1B // reserved for future use
Carobon 0:7321514266d7 189 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
Carobon 0:7321514266d7 190 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
Carobon 0:7321514266d7 191 // 0x1E // reserved for future use
Carobon 0:7321514266d7 192 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
Carobon 0:7321514266d7 193
Carobon 0:7321514266d7 194 // Page 2: Configuration
Carobon 0:7321514266d7 195 // 0x20 // reserved for future use
Carobon 0:7321514266d7 196 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
Carobon 0:7321514266d7 197 CRCResultRegL = 0x22 << 1,
Carobon 0:7321514266d7 198 // 0x23 // reserved for future use
Carobon 0:7321514266d7 199 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
Carobon 0:7321514266d7 200 // 0x25 // reserved for future use
Carobon 0:7321514266d7 201 RFCfgReg = 0x26 << 1, // configures the receiver gain
Carobon 0:7321514266d7 202 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
Carobon 0:7321514266d7 203 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
Carobon 0:7321514266d7 204 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
Carobon 0:7321514266d7 205 TModeReg = 0x2A << 1, // defines settings for the internal timer
Carobon 0:7321514266d7 206 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
Carobon 0:7321514266d7 207 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
Carobon 0:7321514266d7 208 TReloadRegL = 0x2D << 1,
Carobon 0:7321514266d7 209 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
Carobon 0:7321514266d7 210 TCntValueRegL = 0x2F << 1,
Carobon 0:7321514266d7 211
Carobon 0:7321514266d7 212 // Page 3:Test Registers
Carobon 0:7321514266d7 213 // 0x30 // reserved for future use
Carobon 0:7321514266d7 214 TestSel1Reg = 0x31 << 1, // general test signal configuration
Carobon 0:7321514266d7 215 TestSel2Reg = 0x32 << 1, // general test signal configuration
Carobon 0:7321514266d7 216 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
Carobon 0:7321514266d7 217 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
Carobon 0:7321514266d7 218 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
Carobon 0:7321514266d7 219 AutoTestReg = 0x36 << 1, // controls the digital self test
Carobon 0:7321514266d7 220 VersionReg = 0x37 << 1, // shows the software version
Carobon 0:7321514266d7 221 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
Carobon 0:7321514266d7 222 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
Carobon 0:7321514266d7 223 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
Carobon 0:7321514266d7 224 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
Carobon 0:7321514266d7 225 // 0x3C // reserved for production tests
Carobon 0:7321514266d7 226 // 0x3D // reserved for production tests
Carobon 0:7321514266d7 227 // 0x3E // reserved for production tests
Carobon 0:7321514266d7 228 // 0x3F // reserved for production tests
Carobon 0:7321514266d7 229 };
Carobon 0:7321514266d7 230
Carobon 0:7321514266d7 231 // MFRC522 commands Described in chapter 10 of the datasheet.
Carobon 0:7321514266d7 232 enum PCD_Command {
Carobon 0:7321514266d7 233 PCD_Idle = 0x00, // no action, cancels current command execution
Carobon 0:7321514266d7 234 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
Carobon 0:7321514266d7 235 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
Carobon 0:7321514266d7 236 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
Carobon 0:7321514266d7 237 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
Carobon 0:7321514266d7 238 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
Carobon 0:7321514266d7 239 PCD_Receive = 0x08, // activates the receiver circuits
Carobon 0:7321514266d7 240 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
Carobon 0:7321514266d7 241 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
Carobon 0:7321514266d7 242 PCD_SoftReset = 0x0F // resets the MFRC522
Carobon 0:7321514266d7 243 };
Carobon 0:7321514266d7 244
Carobon 0:7321514266d7 245 // Commands sent to the PICC.
Carobon 0:7321514266d7 246 enum PICC_Command {
Carobon 0:7321514266d7 247 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
Carobon 0:7321514266d7 248 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
Carobon 0:7321514266d7 249 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
Carobon 0:7321514266d7 250 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
Carobon 0:7321514266d7 251 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
Carobon 0:7321514266d7 252 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
Carobon 0:7321514266d7 253 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
Carobon 0:7321514266d7 254 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
Carobon 0:7321514266d7 255
Carobon 0:7321514266d7 256 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
Carobon 0:7321514266d7 257 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
Carobon 0:7321514266d7 258 // The read/write commands can also be used for MIFARE Ultralight.
Carobon 0:7321514266d7 259 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
Carobon 0:7321514266d7 260 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
Carobon 0:7321514266d7 261 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
Carobon 0:7321514266d7 262 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
Carobon 0:7321514266d7 263 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
Carobon 0:7321514266d7 264 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
Carobon 0:7321514266d7 265 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
Carobon 0:7321514266d7 266 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
Carobon 0:7321514266d7 267
Carobon 0:7321514266d7 268 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
Carobon 0:7321514266d7 269 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
Carobon 0:7321514266d7 270 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
Carobon 0:7321514266d7 271 };
Carobon 0:7321514266d7 272
Carobon 0:7321514266d7 273 // MIFARE constants that does not fit anywhere else
Carobon 0:7321514266d7 274 enum MIFARE_Misc {
Carobon 0:7321514266d7 275 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
Carobon 0:7321514266d7 276 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
Carobon 0:7321514266d7 277 };
Carobon 0:7321514266d7 278
Carobon 0:7321514266d7 279 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
Carobon 0:7321514266d7 280 enum PICC_Type {
Carobon 0:7321514266d7 281 PICC_TYPE_UNKNOWN = 0,
Carobon 0:7321514266d7 282 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
Carobon 0:7321514266d7 283 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
Carobon 0:7321514266d7 284 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
Carobon 0:7321514266d7 285 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
Carobon 0:7321514266d7 286 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
Carobon 0:7321514266d7 287 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
Carobon 0:7321514266d7 288 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
Carobon 0:7321514266d7 289 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
Carobon 0:7321514266d7 290 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
Carobon 0:7321514266d7 291 };
Carobon 0:7321514266d7 292
Carobon 0:7321514266d7 293 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
Carobon 0:7321514266d7 294 enum StatusCode {
Carobon 0:7321514266d7 295 STATUS_OK = 1, // Success
Carobon 0:7321514266d7 296 STATUS_ERROR = 2, // Error in communication
Carobon 0:7321514266d7 297 STATUS_COLLISION = 3, // Collision detected
Carobon 0:7321514266d7 298 STATUS_TIMEOUT = 4, // Timeout in communication.
Carobon 0:7321514266d7 299 STATUS_NO_ROOM = 5, // A buffer is not big enough.
Carobon 0:7321514266d7 300 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
Carobon 0:7321514266d7 301 STATUS_INVALID = 7, // Invalid argument.
Carobon 0:7321514266d7 302 STATUS_CRC_WRONG = 8, // The CRC_A does not match
Carobon 0:7321514266d7 303 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
Carobon 0:7321514266d7 304 };
Carobon 0:7321514266d7 305
Carobon 0:7321514266d7 306 // A struct used for passing the UID of a PICC.
Carobon 0:7321514266d7 307 typedef struct {
Carobon 0:7321514266d7 308 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
Carobon 0:7321514266d7 309 uint8_t uidByte[10];
Carobon 0:7321514266d7 310 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
Carobon 0:7321514266d7 311 } Uid;
Carobon 0:7321514266d7 312
Carobon 0:7321514266d7 313 // A struct used for passing a MIFARE Crypto1 key
Carobon 0:7321514266d7 314 typedef struct {
Carobon 0:7321514266d7 315 uint8_t keyByte[MF_KEY_SIZE];
Carobon 0:7321514266d7 316 } MIFARE_Key;
Carobon 0:7321514266d7 317
Carobon 0:7321514266d7 318 // Member variables
Carobon 0:7321514266d7 319 Uid uid; // Used by PICC_ReadCardSerial().
Carobon 0:7321514266d7 320
Carobon 0:7321514266d7 321 // Size of the MFRC522 FIFO
Carobon 0:7321514266d7 322 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
Carobon 0:7321514266d7 323
Carobon 0:7321514266d7 324 /**
Carobon 0:7321514266d7 325 * MFRC522 constructor
Carobon 0:7321514266d7 326 *
Carobon 0:7321514266d7 327 * @param mosi SPI MOSI pin
Carobon 0:7321514266d7 328 * @param miso SPI MISO pin
Carobon 0:7321514266d7 329 * @param sclk SPI SCLK pin
Carobon 0:7321514266d7 330 * @param cs SPI CS pin
Carobon 0:7321514266d7 331 * @param reset Reset pin
Carobon 0:7321514266d7 332 */
Carobon 0:7321514266d7 333 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
Carobon 0:7321514266d7 334
Carobon 0:7321514266d7 335 /**
Carobon 0:7321514266d7 336 * MFRC522 destructor
Carobon 0:7321514266d7 337 */
Carobon 0:7321514266d7 338 ~MFRC522();
Carobon 0:7321514266d7 339
Carobon 0:7321514266d7 340
Carobon 0:7321514266d7 341 // ************************************************************************************
Carobon 0:7321514266d7 342 //! @name Functions for manipulating the MFRC522
Carobon 0:7321514266d7 343 // ************************************************************************************
Carobon 0:7321514266d7 344 //@{
Carobon 0:7321514266d7 345
Carobon 0:7321514266d7 346 /**
Carobon 0:7321514266d7 347 * Initializes the MFRC522 chip.
Carobon 0:7321514266d7 348 */
Carobon 0:7321514266d7 349 void PCD_Init (void);
Carobon 0:7321514266d7 350
Carobon 0:7321514266d7 351 /**
Carobon 0:7321514266d7 352 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
Carobon 0:7321514266d7 353 */
Carobon 0:7321514266d7 354 void PCD_Reset (void);
Carobon 0:7321514266d7 355
Carobon 0:7321514266d7 356 /**
Carobon 0:7321514266d7 357 * Turns the antenna on by enabling pins TX1 and TX2.
Carobon 0:7321514266d7 358 * After a reset these pins disabled.
Carobon 0:7321514266d7 359 */
Carobon 0:7321514266d7 360 void PCD_AntennaOn (void);
Carobon 0:7321514266d7 361
Carobon 0:7321514266d7 362 /**
Carobon 0:7321514266d7 363 * Writes a byte to the specified register in the MFRC522 chip.
Carobon 0:7321514266d7 364 * The interface is described in the datasheet section 8.1.2.
Carobon 0:7321514266d7 365 *
Carobon 0:7321514266d7 366 * @param reg The register to write to. One of the PCD_Register enums.
Carobon 0:7321514266d7 367 * @param value The value to write.
Carobon 0:7321514266d7 368 */
Carobon 0:7321514266d7 369 void PCD_WriteRegister (uint8_t reg, uint8_t value);
Carobon 0:7321514266d7 370
Carobon 0:7321514266d7 371 /**
Carobon 0:7321514266d7 372 * Writes a number of bytes to the specified register in the MFRC522 chip.
Carobon 0:7321514266d7 373 * The interface is described in the datasheet section 8.1.2.
Carobon 0:7321514266d7 374 *
Carobon 0:7321514266d7 375 * @param reg The register to write to. One of the PCD_Register enums.
Carobon 0:7321514266d7 376 * @param count The number of bytes to write to the register
Carobon 0:7321514266d7 377 * @param values The values to write. Byte array.
Carobon 0:7321514266d7 378 */
Carobon 0:7321514266d7 379 void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
Carobon 0:7321514266d7 380
Carobon 0:7321514266d7 381 /**
Carobon 0:7321514266d7 382 * Reads a byte from the specified register in the MFRC522 chip.
Carobon 0:7321514266d7 383 * The interface is described in the datasheet section 8.1.2.
Carobon 0:7321514266d7 384 *
Carobon 0:7321514266d7 385 * @param reg The register to read from. One of the PCD_Register enums.
Carobon 0:7321514266d7 386 * @returns Register value
Carobon 0:7321514266d7 387 */
Carobon 0:7321514266d7 388 uint8_t PCD_ReadRegister (uint8_t reg);
Carobon 0:7321514266d7 389
Carobon 0:7321514266d7 390 /**
Carobon 0:7321514266d7 391 * Reads a number of bytes from the specified register in the MFRC522 chip.
Carobon 0:7321514266d7 392 * The interface is described in the datasheet section 8.1.2.
Carobon 0:7321514266d7 393 *
Carobon 0:7321514266d7 394 * @param reg The register to read from. One of the PCD_Register enums.
Carobon 0:7321514266d7 395 * @param count The number of bytes to read.
Carobon 0:7321514266d7 396 * @param values Byte array to store the values in.
Carobon 0:7321514266d7 397 * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
Carobon 0:7321514266d7 398 */
Carobon 0:7321514266d7 399 void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
Carobon 0:7321514266d7 400
Carobon 0:7321514266d7 401 /**
Carobon 0:7321514266d7 402 * Sets the bits given in mask in register reg.
Carobon 0:7321514266d7 403 *
Carobon 0:7321514266d7 404 * @param reg The register to update. One of the PCD_Register enums.
Carobon 0:7321514266d7 405 * @param mask The bits to set.
Carobon 0:7321514266d7 406 */
Carobon 0:7321514266d7 407 void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
Carobon 0:7321514266d7 408
Carobon 0:7321514266d7 409 /**
Carobon 0:7321514266d7 410 * Clears the bits given in mask from register reg.
Carobon 0:7321514266d7 411 *
Carobon 0:7321514266d7 412 * @param reg The register to update. One of the PCD_Register enums.
Carobon 0:7321514266d7 413 * @param mask The bits to clear.
Carobon 0:7321514266d7 414 */
Carobon 0:7321514266d7 415 void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
Carobon 0:7321514266d7 416
Carobon 0:7321514266d7 417 /**
Carobon 0:7321514266d7 418 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
Carobon 0:7321514266d7 419 *
Carobon 0:7321514266d7 420 * @param data Pointer to the data to transfer to the FIFO for CRC calculation.
Carobon 0:7321514266d7 421 * @param length The number of bytes to transfer.
Carobon 0:7321514266d7 422 * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
Carobon 0:7321514266d7 423 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 424 */
Carobon 0:7321514266d7 425 uint8_t PCD_CalculateCRC (uint8_t *data, uint8_t length, uint8_t *result);
Carobon 0:7321514266d7 426
Carobon 0:7321514266d7 427 /**
Carobon 0:7321514266d7 428 * Executes the Transceive command.
Carobon 0:7321514266d7 429 * CRC validation can only be done if backData and backLen are specified.
Carobon 0:7321514266d7 430 *
Carobon 0:7321514266d7 431 * @param sendData Pointer to the data to transfer to the FIFO.
Carobon 0:7321514266d7 432 * @param sendLen Number of bytes to transfer to the FIFO.
Carobon 0:7321514266d7 433 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
Carobon 0:7321514266d7 434 * @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
Carobon 0:7321514266d7 435 * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
Carobon 0:7321514266d7 436 * @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
Carobon 0:7321514266d7 437 * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
Carobon 0:7321514266d7 438 *
Carobon 0:7321514266d7 439 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 440 */
Carobon 0:7321514266d7 441 uint8_t PCD_TransceiveData (uint8_t *sendData,
Carobon 0:7321514266d7 442 uint8_t sendLen,
Carobon 0:7321514266d7 443 uint8_t *backData,
Carobon 0:7321514266d7 444 uint8_t *backLen,
Carobon 0:7321514266d7 445 uint8_t *validBits = NULL,
Carobon 0:7321514266d7 446 uint8_t rxAlign = 0,
Carobon 0:7321514266d7 447 bool checkCRC = false);
Carobon 0:7321514266d7 448
Carobon 0:7321514266d7 449
Carobon 0:7321514266d7 450 /**
Carobon 0:7321514266d7 451 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
Carobon 0:7321514266d7 452 * CRC validation can only be done if backData and backLen are specified.
Carobon 0:7321514266d7 453 *
Carobon 0:7321514266d7 454 * @param command The command to execute. One of the PCD_Command enums.
Carobon 0:7321514266d7 455 * @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
Carobon 0:7321514266d7 456 * @param sendData Pointer to the data to transfer to the FIFO.
Carobon 0:7321514266d7 457 * @param sendLen Number of bytes to transfer to the FIFO.
Carobon 0:7321514266d7 458 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
Carobon 0:7321514266d7 459 * @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
Carobon 0:7321514266d7 460 * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
Carobon 0:7321514266d7 461 * @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
Carobon 0:7321514266d7 462 * @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
Carobon 0:7321514266d7 463 *
Carobon 0:7321514266d7 464 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 465 */
Carobon 0:7321514266d7 466 uint8_t PCD_CommunicateWithPICC(uint8_t command,
Carobon 0:7321514266d7 467 uint8_t waitIRq,
Carobon 0:7321514266d7 468 uint8_t *sendData,
Carobon 0:7321514266d7 469 uint8_t sendLen,
Carobon 0:7321514266d7 470 uint8_t *backData = NULL,
Carobon 0:7321514266d7 471 uint8_t *backLen = NULL,
Carobon 0:7321514266d7 472 uint8_t *validBits = NULL,
Carobon 0:7321514266d7 473 uint8_t rxAlign = 0,
Carobon 0:7321514266d7 474 bool checkCRC = false);
Carobon 0:7321514266d7 475
Carobon 0:7321514266d7 476 /**
Carobon 0:7321514266d7 477 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
Carobon 0:7321514266d7 478 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Carobon 0:7321514266d7 479 *
Carobon 0:7321514266d7 480 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
Carobon 0:7321514266d7 481 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
Carobon 0:7321514266d7 482 *
Carobon 0:7321514266d7 483 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 484 */
Carobon 0:7321514266d7 485 uint8_t PICC_RequestA (uint8_t *bufferATQA, uint8_t *bufferSize);
Carobon 0:7321514266d7 486
Carobon 0:7321514266d7 487 /**
Carobon 0:7321514266d7 488 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
Carobon 0:7321514266d7 489 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Carobon 0:7321514266d7 490 *
Carobon 0:7321514266d7 491 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
Carobon 0:7321514266d7 492 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
Carobon 0:7321514266d7 493 *
Carobon 0:7321514266d7 494 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 495 */
Carobon 0:7321514266d7 496 uint8_t PICC_WakeupA (uint8_t *bufferATQA, uint8_t *bufferSize);
Carobon 0:7321514266d7 497
Carobon 0:7321514266d7 498 /**
Carobon 0:7321514266d7 499 * Transmits REQA or WUPA commands.
Carobon 0:7321514266d7 500 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Carobon 0:7321514266d7 501 *
Carobon 0:7321514266d7 502 * @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
Carobon 0:7321514266d7 503 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
Carobon 0:7321514266d7 504 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
Carobon 0:7321514266d7 505 *
Carobon 0:7321514266d7 506 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 507 */
Carobon 0:7321514266d7 508 uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
Carobon 0:7321514266d7 509
Carobon 0:7321514266d7 510 /**
Carobon 0:7321514266d7 511 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
Carobon 0:7321514266d7 512 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
Carobon 0:7321514266d7 513 * On success:
Carobon 0:7321514266d7 514 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
Carobon 0:7321514266d7 515 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
Carobon 0:7321514266d7 516 *
Carobon 0:7321514266d7 517 * A PICC UID consists of 4, 7 or 10 bytes.
Carobon 0:7321514266d7 518 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
Carobon 0:7321514266d7 519 *
Carobon 0:7321514266d7 520 * UID size Number of UID bytes Cascade levels Example of PICC
Carobon 0:7321514266d7 521 * ======== =================== ============== ===============
Carobon 0:7321514266d7 522 * single 4 1 MIFARE Classic
Carobon 0:7321514266d7 523 * double 7 2 MIFARE Ultralight
Carobon 0:7321514266d7 524 * triple 10 3 Not currently in use?
Carobon 0:7321514266d7 525 *
Carobon 0:7321514266d7 526 *
Carobon 0:7321514266d7 527 * @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
Carobon 0:7321514266d7 528 * @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
Carobon 0:7321514266d7 529 *
Carobon 0:7321514266d7 530 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 531 */
Carobon 0:7321514266d7 532 uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
Carobon 0:7321514266d7 533
Carobon 0:7321514266d7 534 /**
Carobon 0:7321514266d7 535 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
Carobon 0:7321514266d7 536 *
Carobon 0:7321514266d7 537 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 538 */
Carobon 0:7321514266d7 539 uint8_t PICC_HaltA (void);
Carobon 0:7321514266d7 540
Carobon 0:7321514266d7 541 // ************************************************************************************
Carobon 0:7321514266d7 542 //@}
Carobon 0:7321514266d7 543
Carobon 0:7321514266d7 544
Carobon 0:7321514266d7 545 // ************************************************************************************
Carobon 0:7321514266d7 546 //! @name Functions for communicating with MIFARE PICCs
Carobon 0:7321514266d7 547 // ************************************************************************************
Carobon 0:7321514266d7 548 //@{
Carobon 0:7321514266d7 549
Carobon 0:7321514266d7 550 /**
Carobon 0:7321514266d7 551 * Executes the MFRC522 MFAuthent command.
Carobon 0:7321514266d7 552 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
Carobon 0:7321514266d7 553 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
Carobon 0:7321514266d7 554 * For use with MIFARE Classic PICCs.
Carobon 0:7321514266d7 555 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
Carobon 0:7321514266d7 556 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
Carobon 0:7321514266d7 557 *
Carobon 0:7321514266d7 558 * All keys are set to FFFFFFFFFFFFh at chip delivery.
Carobon 0:7321514266d7 559 *
Carobon 0:7321514266d7 560 * @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
Carobon 0:7321514266d7 561 * @param blockAddr The block number. See numbering in the comments in the .h file.
Carobon 0:7321514266d7 562 * @param key Pointer to the Crypteo1 key to use (6 bytes)
Carobon 0:7321514266d7 563 * @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
Carobon 0:7321514266d7 564 *
Carobon 0:7321514266d7 565 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
Carobon 0:7321514266d7 566 */
Carobon 0:7321514266d7 567 uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
Carobon 0:7321514266d7 568
Carobon 0:7321514266d7 569 /**
Carobon 0:7321514266d7 570 * Used to exit the PCD from its authenticated state.
Carobon 0:7321514266d7 571 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
Carobon 0:7321514266d7 572 */
Carobon 0:7321514266d7 573 void PCD_StopCrypto1 (void);
Carobon 0:7321514266d7 574
Carobon 0:7321514266d7 575 /**
Carobon 0:7321514266d7 576 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
Carobon 0:7321514266d7 577 *
Carobon 0:7321514266d7 578 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
Carobon 0:7321514266d7 579 *
Carobon 0:7321514266d7 580 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
Carobon 0:7321514266d7 581 * The MF0ICU1 returns a NAK for higher addresses.
Carobon 0:7321514266d7 582 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
Carobon 0:7321514266d7 583 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
Carobon 0:7321514266d7 584 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
Carobon 0:7321514266d7 585 *
Carobon 0:7321514266d7 586 * The buffer must be at least 18 bytes because a CRC_A is also returned.
Carobon 0:7321514266d7 587 * Checks the CRC_A before returning STATUS_OK.
Carobon 0:7321514266d7 588 *
Carobon 0:7321514266d7 589 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
Carobon 0:7321514266d7 590 * @param buffer The buffer to store the data in
Carobon 0:7321514266d7 591 * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
Carobon 0:7321514266d7 592 *
Carobon 0:7321514266d7 593 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 594 */
Carobon 0:7321514266d7 595 uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
Carobon 0:7321514266d7 596
Carobon 0:7321514266d7 597 /**
Carobon 0:7321514266d7 598 * Writes 16 bytes to the active PICC.
Carobon 0:7321514266d7 599 *
Carobon 0:7321514266d7 600 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
Carobon 0:7321514266d7 601 *
Carobon 0:7321514266d7 602 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
Carobon 0:7321514266d7 603 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
Carobon 0:7321514266d7 604 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
Carobon 0:7321514266d7 605 *
Carobon 0:7321514266d7 606 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
Carobon 0:7321514266d7 607 * @param buffer The 16 bytes to write to the PICC
Carobon 0:7321514266d7 608 * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
Carobon 0:7321514266d7 609 *
Carobon 0:7321514266d7 610 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 611 */
Carobon 0:7321514266d7 612 uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
Carobon 0:7321514266d7 613
Carobon 0:7321514266d7 614 /**
Carobon 0:7321514266d7 615 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
Carobon 0:7321514266d7 616 *
Carobon 0:7321514266d7 617 * @param page The page (2-15) to write to.
Carobon 0:7321514266d7 618 * @param buffer The 4 bytes to write to the PICC
Carobon 0:7321514266d7 619 * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
Carobon 0:7321514266d7 620 *
Carobon 0:7321514266d7 621 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 622 */
Carobon 0:7321514266d7 623 uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
Carobon 0:7321514266d7 624
Carobon 0:7321514266d7 625 /**
Carobon 0:7321514266d7 626 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
Carobon 0:7321514266d7 627 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
Carobon 0:7321514266d7 628 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
Carobon 0:7321514266d7 629 * Use MIFARE_Transfer() to store the result in a block.
Carobon 0:7321514266d7 630 *
Carobon 0:7321514266d7 631 * @param blockAddr The block (0-0xff) number.
Carobon 0:7321514266d7 632 * @param delta This number is subtracted from the value of block blockAddr.
Carobon 0:7321514266d7 633 *
Carobon 0:7321514266d7 634 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 635 */
Carobon 0:7321514266d7 636 uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
Carobon 0:7321514266d7 637
Carobon 0:7321514266d7 638 /**
Carobon 0:7321514266d7 639 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
Carobon 0:7321514266d7 640 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
Carobon 0:7321514266d7 641 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
Carobon 0:7321514266d7 642 * Use MIFARE_Transfer() to store the result in a block.
Carobon 0:7321514266d7 643 *
Carobon 0:7321514266d7 644 * @param blockAddr The block (0-0xff) number.
Carobon 0:7321514266d7 645 * @param delta This number is added to the value of block blockAddr.
Carobon 0:7321514266d7 646 *
Carobon 0:7321514266d7 647 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 648 */
Carobon 0:7321514266d7 649 uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
Carobon 0:7321514266d7 650
Carobon 0:7321514266d7 651 /**
Carobon 0:7321514266d7 652 * MIFARE Restore copies the value of the addressed block into a volatile memory.
Carobon 0:7321514266d7 653 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
Carobon 0:7321514266d7 654 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
Carobon 0:7321514266d7 655 * Use MIFARE_Transfer() to store the result in a block.
Carobon 0:7321514266d7 656 *
Carobon 0:7321514266d7 657 * @param blockAddr The block (0-0xff) number.
Carobon 0:7321514266d7 658 *
Carobon 0:7321514266d7 659 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 660 */
Carobon 0:7321514266d7 661 uint8_t MIFARE_Restore (uint8_t blockAddr);
Carobon 0:7321514266d7 662
Carobon 0:7321514266d7 663 /**
Carobon 0:7321514266d7 664 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
Carobon 0:7321514266d7 665 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
Carobon 0:7321514266d7 666 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
Carobon 0:7321514266d7 667 *
Carobon 0:7321514266d7 668 * @param blockAddr The block (0-0xff) number.
Carobon 0:7321514266d7 669 *
Carobon 0:7321514266d7 670 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 671 */
Carobon 0:7321514266d7 672 uint8_t MIFARE_Transfer (uint8_t blockAddr);
Carobon 0:7321514266d7 673
Carobon 0:7321514266d7 674 // ************************************************************************************
Carobon 0:7321514266d7 675 //@}
Carobon 0:7321514266d7 676
Carobon 0:7321514266d7 677
Carobon 0:7321514266d7 678 // ************************************************************************************
Carobon 0:7321514266d7 679 //! @name Support functions
Carobon 0:7321514266d7 680 // ************************************************************************************
Carobon 0:7321514266d7 681 //@{
Carobon 0:7321514266d7 682
Carobon 0:7321514266d7 683 /**
Carobon 0:7321514266d7 684 * Wrapper for MIFARE protocol communication.
Carobon 0:7321514266d7 685 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
Carobon 0:7321514266d7 686 *
Carobon 0:7321514266d7 687 * @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
Carobon 0:7321514266d7 688 * @param sendLen Number of bytes in sendData.
Carobon 0:7321514266d7 689 * @param acceptTimeout True => A timeout is also success
Carobon 0:7321514266d7 690 *
Carobon 0:7321514266d7 691 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 692 */
Carobon 0:7321514266d7 693 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
Carobon 0:7321514266d7 694
Carobon 0:7321514266d7 695 /**
Carobon 0:7321514266d7 696 * Translates the SAK (Select Acknowledge) to a PICC type.
Carobon 0:7321514266d7 697 *
Carobon 0:7321514266d7 698 * @param sak The SAK byte returned from PICC_Select().
Carobon 0:7321514266d7 699 *
Carobon 0:7321514266d7 700 * @return PICC_Type
Carobon 0:7321514266d7 701 */
Carobon 0:7321514266d7 702 uint8_t PICC_GetType (uint8_t sak);
Carobon 0:7321514266d7 703
Carobon 0:7321514266d7 704 /**
Carobon 0:7321514266d7 705 * Returns a string pointer to the PICC type name.
Carobon 0:7321514266d7 706 *
Carobon 0:7321514266d7 707 * @param type One of the PICC_Type enums.
Carobon 0:7321514266d7 708 *
Carobon 0:7321514266d7 709 * @return A string pointer to the PICC type name.
Carobon 0:7321514266d7 710 */
Carobon 0:7321514266d7 711 char* PICC_GetTypeName (uint8_t type);
Carobon 0:7321514266d7 712
Carobon 0:7321514266d7 713 /**
Carobon 0:7321514266d7 714 * Returns a string pointer to a status code name.
Carobon 0:7321514266d7 715 *
Carobon 0:7321514266d7 716 * @param code One of the StatusCode enums.
Carobon 0:7321514266d7 717 *
Carobon 0:7321514266d7 718 * @return A string pointer to a status code name.
Carobon 0:7321514266d7 719 */
Carobon 0:7321514266d7 720 char* GetStatusCodeName (uint8_t code);
Carobon 0:7321514266d7 721
Carobon 0:7321514266d7 722 /**
Carobon 0:7321514266d7 723 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
Carobon 0:7321514266d7 724 *
Carobon 0:7321514266d7 725 * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
Carobon 0:7321514266d7 726 * @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
Carobon 0:7321514266d7 727 * @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
Carobon 0:7321514266d7 728 * @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
Carobon 0:7321514266d7 729 * @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
Carobon 0:7321514266d7 730 */
Carobon 0:7321514266d7 731 void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
Carobon 0:7321514266d7 732 uint8_t g0,
Carobon 0:7321514266d7 733 uint8_t g1,
Carobon 0:7321514266d7 734 uint8_t g2,
Carobon 0:7321514266d7 735 uint8_t g3);
Carobon 0:7321514266d7 736
Carobon 0:7321514266d7 737 // ************************************************************************************
Carobon 0:7321514266d7 738 //@}
Carobon 0:7321514266d7 739
Carobon 0:7321514266d7 740
Carobon 0:7321514266d7 741 // ************************************************************************************
Carobon 0:7321514266d7 742 //! @name Convenience functions - does not add extra functionality
Carobon 0:7321514266d7 743 // ************************************************************************************
Carobon 0:7321514266d7 744 //@{
Carobon 0:7321514266d7 745
Carobon 0:7321514266d7 746 /**
Carobon 0:7321514266d7 747 * Returns true if a PICC responds to PICC_CMD_REQA.
Carobon 0:7321514266d7 748 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
Carobon 0:7321514266d7 749 *
Carobon 0:7321514266d7 750 * @return bool
Carobon 0:7321514266d7 751 */
Carobon 0:7321514266d7 752 bool PICC_IsNewCardPresent(void);
Carobon 0:7321514266d7 753
Carobon 0:7321514266d7 754 /**
Carobon 0:7321514266d7 755 * Simple wrapper around PICC_Select.
Carobon 0:7321514266d7 756 * Returns true if a UID could be read.
Carobon 0:7321514266d7 757 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
Carobon 0:7321514266d7 758 * The read UID is available in the class variable uid.
Carobon 0:7321514266d7 759 *
Carobon 0:7321514266d7 760 * @return bool
Carobon 0:7321514266d7 761 */
Carobon 0:7321514266d7 762 bool PICC_ReadCardSerial (void);
Carobon 0:7321514266d7 763
Carobon 0:7321514266d7 764 // ************************************************************************************
Carobon 0:7321514266d7 765 //@}
Carobon 0:7321514266d7 766
Carobon 0:7321514266d7 767
Carobon 0:7321514266d7 768 private:
Carobon 0:7321514266d7 769 SPI m_SPI;
Carobon 0:7321514266d7 770 DigitalOut m_CS;
Carobon 0:7321514266d7 771 DigitalOut m_RESET;
Carobon 0:7321514266d7 772
Carobon 0:7321514266d7 773 /**
Carobon 0:7321514266d7 774 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
Carobon 0:7321514266d7 775 *
Carobon 0:7321514266d7 776 * @param command The command to use
Carobon 0:7321514266d7 777 * @param blockAddr The block (0-0xff) number.
Carobon 0:7321514266d7 778 * @param data The data to transfer in step 2
Carobon 0:7321514266d7 779 *
Carobon 0:7321514266d7 780 * @return STATUS_OK on success, STATUS_??? otherwise.
Carobon 0:7321514266d7 781 */
Carobon 0:7321514266d7 782 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
Carobon 0:7321514266d7 783 };
Carobon 0:7321514266d7 784
Carobon 0:7321514266d7 785 #endif