Caroline BONHOMME / Mbed 2 deprecated ProjetRFID

projet rfid

Dependencies:   BSP_DISCO_F429ZI LCD_DISCO_F429ZI mbed

MFRC522.cpp@0:7321514266d7, 2018-03-15 (annotated)

Committer:
Carobon
Date:
Thu Mar 15 08:50:12 2018 +0000
Revision:
0:7321514266d7
STM32RC522

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Carobon 0:7321514266d7 1 /*
Carobon 0:7321514266d7 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
Carobon 0:7321514266d7 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
Carobon 0:7321514266d7 4 * Released into the public domain.
Carobon 0:7321514266d7 5 */
Carobon 0:7321514266d7 6
Carobon 0:7321514266d7 7 #include "MFRC522.h"
Carobon 0:7321514266d7 8
Carobon 0:7321514266d7 9 static const char* const _TypeNamePICC[] =
Carobon 0:7321514266d7 10 {
Carobon 0:7321514266d7 11 "Unknown type",
Carobon 0:7321514266d7 12 "PICC compliant with ISO/IEC 14443-4",
Carobon 0:7321514266d7 13 "PICC compliant with ISO/IEC 18092 (NFC)",
Carobon 0:7321514266d7 14 "MIFARE Mini, 320 bytes",
Carobon 0:7321514266d7 15 "MIFARE 1KB",
Carobon 0:7321514266d7 16 "MIFARE 4KB",
Carobon 0:7321514266d7 17 "MIFARE Ultralight or Ultralight C",
Carobon 0:7321514266d7 18 "MIFARE Plus",
Carobon 0:7321514266d7 19 "MIFARE TNP3XXX",
Carobon 0:7321514266d7 20
Carobon 0:7321514266d7 21 /* not complete UID */
Carobon 0:7321514266d7 22 "SAK indicates UID is not complete"
Carobon 0:7321514266d7 23 };
Carobon 0:7321514266d7 24
Carobon 0:7321514266d7 25 static const char* const _ErrorMessage[] =
Carobon 0:7321514266d7 26 {
Carobon 0:7321514266d7 27 "Unknown error",
Carobon 0:7321514266d7 28 "Success",
Carobon 0:7321514266d7 29 "Error in communication",
Carobon 0:7321514266d7 30 "Collision detected",
Carobon 0:7321514266d7 31 "Timeout in communication",
Carobon 0:7321514266d7 32 "A buffer is not big enough",
Carobon 0:7321514266d7 33 "Internal error in the code, should not happen",
Carobon 0:7321514266d7 34 "Invalid argument",
Carobon 0:7321514266d7 35 "The CRC_A does not match",
Carobon 0:7321514266d7 36 "A MIFARE PICC responded with NAK"
Carobon 0:7321514266d7 37 };
Carobon 0:7321514266d7 38
Carobon 0:7321514266d7 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
Carobon 0:7321514266d7 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
Carobon 0:7321514266d7 41
Carobon 0:7321514266d7 42 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 43 // Functions for setting up the driver
Carobon 0:7321514266d7 44 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 45
Carobon 0:7321514266d7 46 /**
Carobon 0:7321514266d7 47 * Constructor.
Carobon 0:7321514266d7 48 * Prepares the output pins.
Carobon 0:7321514266d7 49 */
Carobon 0:7321514266d7 50 MFRC522::MFRC522(PinName mosi,
Carobon 0:7321514266d7 51 PinName miso,
Carobon 0:7321514266d7 52 PinName sclk,
Carobon 0:7321514266d7 53 PinName cs,
Carobon 0:7321514266d7 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
Carobon 0:7321514266d7 55 {
Carobon 0:7321514266d7 56 /* Configure SPI bus */
Carobon 0:7321514266d7 57 m_SPI.format(8, 0);
Carobon 0:7321514266d7 58 m_SPI.frequency(8000000);
Carobon 0:7321514266d7 59
Carobon 0:7321514266d7 60 /* Release SPI-CS pin */
Carobon 0:7321514266d7 61 m_CS = 1;
Carobon 0:7321514266d7 62
Carobon 0:7321514266d7 63 /* Release RESET pin */
Carobon 0:7321514266d7 64 m_RESET = 1;
Carobon 0:7321514266d7 65 } // End constructor
Carobon 0:7321514266d7 66
Carobon 0:7321514266d7 67
Carobon 0:7321514266d7 68 /**
Carobon 0:7321514266d7 69 * Destructor.
Carobon 0:7321514266d7 70 */
Carobon 0:7321514266d7 71 MFRC522::~MFRC522()
Carobon 0:7321514266d7 72 {
Carobon 0:7321514266d7 73
Carobon 0:7321514266d7 74 }
Carobon 0:7321514266d7 75
Carobon 0:7321514266d7 76
Carobon 0:7321514266d7 77 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 78 // Basic interface functions for communicating with the MFRC522
Carobon 0:7321514266d7 79 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 80
Carobon 0:7321514266d7 81 /**
Carobon 0:7321514266d7 82 * Writes a byte to the specified register in the MFRC522 chip.
Carobon 0:7321514266d7 83 * The interface is described in the datasheet section 8.1.2.
Carobon 0:7321514266d7 84 */
Carobon 0:7321514266d7 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
Carobon 0:7321514266d7 86 {
Carobon 0:7321514266d7 87 m_CS = 0; /* Select SPI Chip MFRC522 */
Carobon 0:7321514266d7 88
Carobon 0:7321514266d7 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
Carobon 0:7321514266d7 90 (void) m_SPI.write(reg & 0x7E);
Carobon 0:7321514266d7 91 (void) m_SPI.write(value);
Carobon 0:7321514266d7 92
Carobon 0:7321514266d7 93 m_CS = 1; /* Release SPI Chip MFRC522 */
Carobon 0:7321514266d7 94 } // End PCD_WriteRegister()
Carobon 0:7321514266d7 95
Carobon 0:7321514266d7 96 /**
Carobon 0:7321514266d7 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
Carobon 0:7321514266d7 98 * The interface is described in the datasheet section 8.1.2.
Carobon 0:7321514266d7 99 */
Carobon 0:7321514266d7 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
Carobon 0:7321514266d7 101 {
Carobon 0:7321514266d7 102 m_CS = 0; /* Select SPI Chip MFRC522 */
Carobon 0:7321514266d7 103
Carobon 0:7321514266d7 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
Carobon 0:7321514266d7 105 (void) m_SPI.write(reg & 0x7E);
Carobon 0:7321514266d7 106 for (uint8_t index = 0; index < count; index++)
Carobon 0:7321514266d7 107 {
Carobon 0:7321514266d7 108 (void) m_SPI.write(values[index]);
Carobon 0:7321514266d7 109 }
Carobon 0:7321514266d7 110
Carobon 0:7321514266d7 111 m_CS = 1; /* Release SPI Chip MFRC522 */
Carobon 0:7321514266d7 112 } // End PCD_WriteRegister()
Carobon 0:7321514266d7 113
Carobon 0:7321514266d7 114 /**
Carobon 0:7321514266d7 115 * Reads a byte from the specified register in the MFRC522 chip.
Carobon 0:7321514266d7 116 * The interface is described in the datasheet section 8.1.2.
Carobon 0:7321514266d7 117 */
Carobon 0:7321514266d7 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
Carobon 0:7321514266d7 119 {
Carobon 0:7321514266d7 120 uint8_t value;
Carobon 0:7321514266d7 121 m_CS = 0; /* Select SPI Chip MFRC522 */
Carobon 0:7321514266d7 122
Carobon 0:7321514266d7 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
Carobon 0:7321514266d7 124 (void) m_SPI.write(0x80 | reg);
Carobon 0:7321514266d7 125
Carobon 0:7321514266d7 126 // Read the value back. Send 0 to stop reading.
Carobon 0:7321514266d7 127 value = m_SPI.write(0);
Carobon 0:7321514266d7 128
Carobon 0:7321514266d7 129 m_CS = 1; /* Release SPI Chip MFRC522 */
Carobon 0:7321514266d7 130
Carobon 0:7321514266d7 131 return value;
Carobon 0:7321514266d7 132 } // End PCD_ReadRegister()
Carobon 0:7321514266d7 133
Carobon 0:7321514266d7 134 /**
Carobon 0:7321514266d7 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
Carobon 0:7321514266d7 136 * The interface is described in the datasheet section 8.1.2.
Carobon 0:7321514266d7 137 */
Carobon 0:7321514266d7 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
Carobon 0:7321514266d7 139 {
Carobon 0:7321514266d7 140 if (count == 0) { return; }
Carobon 0:7321514266d7 141
Carobon 0:7321514266d7 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
Carobon 0:7321514266d7 143 uint8_t index = 0; // Index in values array.
Carobon 0:7321514266d7 144
Carobon 0:7321514266d7 145 m_CS = 0; /* Select SPI Chip MFRC522 */
Carobon 0:7321514266d7 146 count--; // One read is performed outside of the loop
Carobon 0:7321514266d7 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
Carobon 0:7321514266d7 148
Carobon 0:7321514266d7 149 while (index < count)
Carobon 0:7321514266d7 150 {
Carobon 0:7321514266d7 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
Carobon 0:7321514266d7 152 {
Carobon 0:7321514266d7 153 // Create bit mask for bit positions rxAlign..7
Carobon 0:7321514266d7 154 uint8_t mask = 0;
Carobon 0:7321514266d7 155 for (uint8_t i = rxAlign; i <= 7; i++)
Carobon 0:7321514266d7 156 {
Carobon 0:7321514266d7 157 mask |= (1 << i);
Carobon 0:7321514266d7 158 }
Carobon 0:7321514266d7 159
Carobon 0:7321514266d7 160 // Read value and tell that we want to read the same address again.
Carobon 0:7321514266d7 161 uint8_t value = m_SPI.write(address);
Carobon 0:7321514266d7 162
Carobon 0:7321514266d7 163 // Apply mask to both current value of values[0] and the new data in value.
Carobon 0:7321514266d7 164 values[0] = (values[index] & ~mask) | (value & mask);
Carobon 0:7321514266d7 165 }
Carobon 0:7321514266d7 166 else
Carobon 0:7321514266d7 167 {
Carobon 0:7321514266d7 168 // Read value and tell that we want to read the same address again.
Carobon 0:7321514266d7 169 values[index] = m_SPI.write(address);
Carobon 0:7321514266d7 170 }
Carobon 0:7321514266d7 171
Carobon 0:7321514266d7 172 index++;
Carobon 0:7321514266d7 173 }
Carobon 0:7321514266d7 174
Carobon 0:7321514266d7 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
Carobon 0:7321514266d7 176
Carobon 0:7321514266d7 177 m_CS = 1; /* Release SPI Chip MFRC522 */
Carobon 0:7321514266d7 178 } // End PCD_ReadRegister()
Carobon 0:7321514266d7 179
Carobon 0:7321514266d7 180 /**
Carobon 0:7321514266d7 181 * Sets the bits given in mask in register reg.
Carobon 0:7321514266d7 182 */
Carobon 0:7321514266d7 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
Carobon 0:7321514266d7 184 {
Carobon 0:7321514266d7 185 uint8_t tmp = PCD_ReadRegister(reg);
Carobon 0:7321514266d7 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
Carobon 0:7321514266d7 187 } // End PCD_SetRegisterBitMask()
Carobon 0:7321514266d7 188
Carobon 0:7321514266d7 189 /**
Carobon 0:7321514266d7 190 * Clears the bits given in mask from register reg.
Carobon 0:7321514266d7 191 */
Carobon 0:7321514266d7 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
Carobon 0:7321514266d7 193 {
Carobon 0:7321514266d7 194 uint8_t tmp = PCD_ReadRegister(reg);
Carobon 0:7321514266d7 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
Carobon 0:7321514266d7 196 } // End PCD_ClearRegisterBitMask()
Carobon 0:7321514266d7 197
Carobon 0:7321514266d7 198
Carobon 0:7321514266d7 199 /**
Carobon 0:7321514266d7 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
Carobon 0:7321514266d7 201 */
Carobon 0:7321514266d7 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
Carobon 0:7321514266d7 203 {
Carobon 0:7321514266d7 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
Carobon 0:7321514266d7 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
Carobon 0:7321514266d7 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
Carobon 0:7321514266d7 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
Carobon 0:7321514266d7 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
Carobon 0:7321514266d7 209
Carobon 0:7321514266d7 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
Carobon 0:7321514266d7 211 uint16_t i = 5000;
Carobon 0:7321514266d7 212 uint8_t n;
Carobon 0:7321514266d7 213 while (1)
Carobon 0:7321514266d7 214 {
Carobon 0:7321514266d7 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
Carobon 0:7321514266d7 216 if (n & 0x04)
Carobon 0:7321514266d7 217 {
Carobon 0:7321514266d7 218 // CRCIRq bit set - calculation done
Carobon 0:7321514266d7 219 break;
Carobon 0:7321514266d7 220 }
Carobon 0:7321514266d7 221
Carobon 0:7321514266d7 222 if (--i == 0)
Carobon 0:7321514266d7 223 {
Carobon 0:7321514266d7 224 // The emergency break. We will eventually terminate on this one after 89ms.
Carobon 0:7321514266d7 225 // Communication with the MFRC522 might be down.
Carobon 0:7321514266d7 226 return STATUS_TIMEOUT;
Carobon 0:7321514266d7 227 }
Carobon 0:7321514266d7 228 }
Carobon 0:7321514266d7 229
Carobon 0:7321514266d7 230 // Stop calculating CRC for new content in the FIFO.
Carobon 0:7321514266d7 231 PCD_WriteRegister(CommandReg, PCD_Idle);
Carobon 0:7321514266d7 232
Carobon 0:7321514266d7 233 // Transfer the result from the registers to the result buffer
Carobon 0:7321514266d7 234 result[0] = PCD_ReadRegister(CRCResultRegL);
Carobon 0:7321514266d7 235 result[1] = PCD_ReadRegister(CRCResultRegH);
Carobon 0:7321514266d7 236 return STATUS_OK;
Carobon 0:7321514266d7 237 } // End PCD_CalculateCRC()
Carobon 0:7321514266d7 238
Carobon 0:7321514266d7 239
Carobon 0:7321514266d7 240 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 241 // Functions for manipulating the MFRC522
Carobon 0:7321514266d7 242 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 243
Carobon 0:7321514266d7 244 /**
Carobon 0:7321514266d7 245 * Initializes the MFRC522 chip.
Carobon 0:7321514266d7 246 */
Carobon 0:7321514266d7 247 void MFRC522::PCD_Init()
Carobon 0:7321514266d7 248 {
Carobon 0:7321514266d7 249 /* Reset MFRC522 */
Carobon 0:7321514266d7 250 m_RESET = 0;
Carobon 0:7321514266d7 251 wait_ms(10);
Carobon 0:7321514266d7 252 m_RESET = 1;
Carobon 0:7321514266d7 253
Carobon 0:7321514266d7 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
Carobon 0:7321514266d7 255 wait_ms(50);
Carobon 0:7321514266d7 256
Carobon 0:7321514266d7 257 // When communicating with a PICC we need a timeout if something goes wrong.
Carobon 0:7321514266d7 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
Carobon 0:7321514266d7 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
Carobon 0:7321514266d7 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
Carobon 0:7321514266d7 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
Carobon 0:7321514266d7 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
Carobon 0:7321514266d7 263 PCD_WriteRegister(TReloadRegL, 0xE8);
Carobon 0:7321514266d7 264
Carobon 0:7321514266d7 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
Carobon 0:7321514266d7 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
Carobon 0:7321514266d7 267
Carobon 0:7321514266d7 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
Carobon 0:7321514266d7 269
Carobon 0:7321514266d7 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
Carobon 0:7321514266d7 271 } // End PCD_Init()
Carobon 0:7321514266d7 272
Carobon 0:7321514266d7 273 /**
Carobon 0:7321514266d7 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
Carobon 0:7321514266d7 275 */
Carobon 0:7321514266d7 276 void MFRC522::PCD_Reset()
Carobon 0:7321514266d7 277 {
Carobon 0:7321514266d7 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
Carobon 0:7321514266d7 279 // The datasheet does not mention how long the SoftRest command takes to complete.
Carobon 0:7321514266d7 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
Carobon 0:7321514266d7 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
Carobon 0:7321514266d7 282 wait_ms(50);
Carobon 0:7321514266d7 283
Carobon 0:7321514266d7 284 // Wait for the PowerDown bit in CommandReg to be cleared
Carobon 0:7321514266d7 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
Carobon 0:7321514266d7 286 {
Carobon 0:7321514266d7 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
Carobon 0:7321514266d7 288 }
Carobon 0:7321514266d7 289 } // End PCD_Reset()
Carobon 0:7321514266d7 290
Carobon 0:7321514266d7 291 /**
Carobon 0:7321514266d7 292 * Turns the antenna on by enabling pins TX1 and TX2.
Carobon 0:7321514266d7 293 * After a reset these pins disabled.
Carobon 0:7321514266d7 294 */
Carobon 0:7321514266d7 295 void MFRC522::PCD_AntennaOn()
Carobon 0:7321514266d7 296 {
Carobon 0:7321514266d7 297 uint8_t value = PCD_ReadRegister(TxControlReg);
Carobon 0:7321514266d7 298 if ((value & 0x03) != 0x03)
Carobon 0:7321514266d7 299 {
Carobon 0:7321514266d7 300 PCD_WriteRegister(TxControlReg, value | 0x03);
Carobon 0:7321514266d7 301 }
Carobon 0:7321514266d7 302 } // End PCD_AntennaOn()
Carobon 0:7321514266d7 303
Carobon 0:7321514266d7 304 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 305 // Functions for communicating with PICCs
Carobon 0:7321514266d7 306 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 307
Carobon 0:7321514266d7 308 /**
Carobon 0:7321514266d7 309 * Executes the Transceive command.
Carobon 0:7321514266d7 310 * CRC validation can only be done if backData and backLen are specified.
Carobon 0:7321514266d7 311 */
Carobon 0:7321514266d7 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
Carobon 0:7321514266d7 313 uint8_t sendLen,
Carobon 0:7321514266d7 314 uint8_t *backData,
Carobon 0:7321514266d7 315 uint8_t *backLen,
Carobon 0:7321514266d7 316 uint8_t *validBits,
Carobon 0:7321514266d7 317 uint8_t rxAlign,
Carobon 0:7321514266d7 318 bool checkCRC)
Carobon 0:7321514266d7 319 {
Carobon 0:7321514266d7 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
Carobon 0:7321514266d7 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
Carobon 0:7321514266d7 322 } // End PCD_TransceiveData()
Carobon 0:7321514266d7 323
Carobon 0:7321514266d7 324 /**
Carobon 0:7321514266d7 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
Carobon 0:7321514266d7 326 * CRC validation can only be done if backData and backLen are specified.
Carobon 0:7321514266d7 327 */
Carobon 0:7321514266d7 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
Carobon 0:7321514266d7 329 uint8_t waitIRq,
Carobon 0:7321514266d7 330 uint8_t *sendData,
Carobon 0:7321514266d7 331 uint8_t sendLen,
Carobon 0:7321514266d7 332 uint8_t *backData,
Carobon 0:7321514266d7 333 uint8_t *backLen,
Carobon 0:7321514266d7 334 uint8_t *validBits,
Carobon 0:7321514266d7 335 uint8_t rxAlign,
Carobon 0:7321514266d7 336 bool checkCRC)
Carobon 0:7321514266d7 337 {
Carobon 0:7321514266d7 338 uint8_t n, _validBits = 0;
Carobon 0:7321514266d7 339 uint32_t i;
Carobon 0:7321514266d7 340
Carobon 0:7321514266d7 341 // Prepare values for BitFramingReg
Carobon 0:7321514266d7 342 uint8_t txLastBits = validBits ? *validBits : 0;
Carobon 0:7321514266d7 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
Carobon 0:7321514266d7 344
Carobon 0:7321514266d7 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
Carobon 0:7321514266d7 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
Carobon 0:7321514266d7 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
Carobon 0:7321514266d7 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
Carobon 0:7321514266d7 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
Carobon 0:7321514266d7 350 PCD_WriteRegister(CommandReg, command); // Execute the command
Carobon 0:7321514266d7 351 if (command == PCD_Transceive)
Carobon 0:7321514266d7 352 {
Carobon 0:7321514266d7 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
Carobon 0:7321514266d7 354 }
Carobon 0:7321514266d7 355
Carobon 0:7321514266d7 356 // Wait for the command to complete.
Carobon 0:7321514266d7 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
Carobon 0:7321514266d7 358 // Each iteration of the do-while-loop takes 17.86us.
Carobon 0:7321514266d7 359 i = 2000;
Carobon 0:7321514266d7 360 while (1)
Carobon 0:7321514266d7 361 {
Carobon 0:7321514266d7 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
Carobon 0:7321514266d7 363 if (n & waitIRq)
Carobon 0:7321514266d7 364 { // One of the interrupts that signal success has been set.
Carobon 0:7321514266d7 365 break;
Carobon 0:7321514266d7 366 }
Carobon 0:7321514266d7 367
Carobon 0:7321514266d7 368 if (n & 0x01)
Carobon 0:7321514266d7 369 { // Timer interrupt - nothing received in 25ms
Carobon 0:7321514266d7 370 return STATUS_TIMEOUT;
Carobon 0:7321514266d7 371 }
Carobon 0:7321514266d7 372
Carobon 0:7321514266d7 373 if (--i == 0)
Carobon 0:7321514266d7 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
Carobon 0:7321514266d7 375 return STATUS_TIMEOUT;
Carobon 0:7321514266d7 376 }
Carobon 0:7321514266d7 377 }
Carobon 0:7321514266d7 378
Carobon 0:7321514266d7 379 // Stop now if any errors except collisions were detected.
Carobon 0:7321514266d7 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
Carobon 0:7321514266d7 381 if (errorRegValue & 0x13)
Carobon 0:7321514266d7 382 { // BufferOvfl ParityErr ProtocolErr
Carobon 0:7321514266d7 383 return STATUS_ERROR;
Carobon 0:7321514266d7 384 }
Carobon 0:7321514266d7 385
Carobon 0:7321514266d7 386 // If the caller wants data back, get it from the MFRC522.
Carobon 0:7321514266d7 387 if (backData && backLen)
Carobon 0:7321514266d7 388 {
Carobon 0:7321514266d7 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
Carobon 0:7321514266d7 390 if (n > *backLen)
Carobon 0:7321514266d7 391 {
Carobon 0:7321514266d7 392 return STATUS_NO_ROOM;
Carobon 0:7321514266d7 393 }
Carobon 0:7321514266d7 394
Carobon 0:7321514266d7 395 *backLen = n; // Number of bytes returned
Carobon 0:7321514266d7 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
Carobon 0:7321514266d7 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
Carobon 0:7321514266d7 398 if (validBits)
Carobon 0:7321514266d7 399 {
Carobon 0:7321514266d7 400 *validBits = _validBits;
Carobon 0:7321514266d7 401 }
Carobon 0:7321514266d7 402 }
Carobon 0:7321514266d7 403
Carobon 0:7321514266d7 404 // Tell about collisions
Carobon 0:7321514266d7 405 if (errorRegValue & 0x08)
Carobon 0:7321514266d7 406 { // CollErr
Carobon 0:7321514266d7 407 return STATUS_COLLISION;
Carobon 0:7321514266d7 408 }
Carobon 0:7321514266d7 409
Carobon 0:7321514266d7 410 // Perform CRC_A validation if requested.
Carobon 0:7321514266d7 411 if (backData && backLen && checkCRC)
Carobon 0:7321514266d7 412 {
Carobon 0:7321514266d7 413 // In this case a MIFARE Classic NAK is not OK.
Carobon 0:7321514266d7 414 if ((*backLen == 1) && (_validBits == 4))
Carobon 0:7321514266d7 415 {
Carobon 0:7321514266d7 416 return STATUS_MIFARE_NACK;
Carobon 0:7321514266d7 417 }
Carobon 0:7321514266d7 418
Carobon 0:7321514266d7 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
Carobon 0:7321514266d7 420 if ((*backLen < 2) || (_validBits != 0))
Carobon 0:7321514266d7 421 {
Carobon 0:7321514266d7 422 return STATUS_CRC_WRONG;
Carobon 0:7321514266d7 423 }
Carobon 0:7321514266d7 424
Carobon 0:7321514266d7 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
Carobon 0:7321514266d7 426 uint8_t controlBuffer[2];
Carobon 0:7321514266d7 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
Carobon 0:7321514266d7 428 if (n != STATUS_OK)
Carobon 0:7321514266d7 429 {
Carobon 0:7321514266d7 430 return n;
Carobon 0:7321514266d7 431 }
Carobon 0:7321514266d7 432
Carobon 0:7321514266d7 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
Carobon 0:7321514266d7 434 {
Carobon 0:7321514266d7 435 return STATUS_CRC_WRONG;
Carobon 0:7321514266d7 436 }
Carobon 0:7321514266d7 437 }
Carobon 0:7321514266d7 438
Carobon 0:7321514266d7 439 return STATUS_OK;
Carobon 0:7321514266d7 440 } // End PCD_CommunicateWithPICC()
Carobon 0:7321514266d7 441
Carobon 0:7321514266d7 442 /*
Carobon 0:7321514266d7 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
Carobon 0:7321514266d7 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Carobon 0:7321514266d7 445 */
Carobon 0:7321514266d7 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
Carobon 0:7321514266d7 447 {
Carobon 0:7321514266d7 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
Carobon 0:7321514266d7 449 } // End PICC_RequestA()
Carobon 0:7321514266d7 450
Carobon 0:7321514266d7 451 /**
Carobon 0:7321514266d7 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
Carobon 0:7321514266d7 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Carobon 0:7321514266d7 454 */
Carobon 0:7321514266d7 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
Carobon 0:7321514266d7 456 {
Carobon 0:7321514266d7 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
Carobon 0:7321514266d7 458 } // End PICC_WakeupA()
Carobon 0:7321514266d7 459
Carobon 0:7321514266d7 460 /*
Carobon 0:7321514266d7 461 * Transmits REQA or WUPA commands.
Carobon 0:7321514266d7 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
Carobon 0:7321514266d7 463 */
Carobon 0:7321514266d7 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
Carobon 0:7321514266d7 465 {
Carobon 0:7321514266d7 466 uint8_t validBits;
Carobon 0:7321514266d7 467 uint8_t status;
Carobon 0:7321514266d7 468
Carobon 0:7321514266d7 469 if (bufferATQA == NULL || *bufferSize < 2)
Carobon 0:7321514266d7 470 { // The ATQA response is 2 bytes long.
Carobon 0:7321514266d7 471 return STATUS_NO_ROOM;
Carobon 0:7321514266d7 472 }
Carobon 0:7321514266d7 473
Carobon 0:7321514266d7 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
Carobon 0:7321514266d7 475 PCD_ClrRegisterBits(CollReg, 0x80);
Carobon 0:7321514266d7 476
Carobon 0:7321514266d7 477 // For REQA and WUPA we need the short frame format
Carobon 0:7321514266d7 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
Carobon 0:7321514266d7 479 validBits = 7;
Carobon 0:7321514266d7 480
Carobon 0:7321514266d7 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
Carobon 0:7321514266d7 482 if (status != STATUS_OK)
Carobon 0:7321514266d7 483 {
Carobon 0:7321514266d7 484 return status;
Carobon 0:7321514266d7 485 }
Carobon 0:7321514266d7 486
Carobon 0:7321514266d7 487 if ((*bufferSize != 2) || (validBits != 0))
Carobon 0:7321514266d7 488 { // ATQA must be exactly 16 bits.
Carobon 0:7321514266d7 489 return STATUS_ERROR;
Carobon 0:7321514266d7 490 }
Carobon 0:7321514266d7 491
Carobon 0:7321514266d7 492 return STATUS_OK;
Carobon 0:7321514266d7 493 } // End PICC_REQA_or_WUPA()
Carobon 0:7321514266d7 494
Carobon 0:7321514266d7 495 /*
Carobon 0:7321514266d7 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
Carobon 0:7321514266d7 497 */
Carobon 0:7321514266d7 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
Carobon 0:7321514266d7 499 {
Carobon 0:7321514266d7 500 bool uidComplete;
Carobon 0:7321514266d7 501 bool selectDone;
Carobon 0:7321514266d7 502 bool useCascadeTag;
Carobon 0:7321514266d7 503 uint8_t cascadeLevel = 1;
Carobon 0:7321514266d7 504 uint8_t result;
Carobon 0:7321514266d7 505 uint8_t count;
Carobon 0:7321514266d7 506 uint8_t index;
Carobon 0:7321514266d7 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
Carobon 0:7321514266d7 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
Carobon 0:7321514266d7 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
Carobon 0:7321514266d7 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
Carobon 0:7321514266d7 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
Carobon 0:7321514266d7 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
Carobon 0:7321514266d7 513 uint8_t *responseBuffer;
Carobon 0:7321514266d7 514 uint8_t responseLength;
Carobon 0:7321514266d7 515
Carobon 0:7321514266d7 516 // Description of buffer structure:
Carobon 0:7321514266d7 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
Carobon 0:7321514266d7 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
Carobon 0:7321514266d7 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
Carobon 0:7321514266d7 520 // Byte 3: UID-data
Carobon 0:7321514266d7 521 // Byte 4: UID-data
Carobon 0:7321514266d7 522 // Byte 5: UID-data
Carobon 0:7321514266d7 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
Carobon 0:7321514266d7 524 // Byte 7: CRC_A
Carobon 0:7321514266d7 525 // Byte 8: CRC_A
Carobon 0:7321514266d7 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
Carobon 0:7321514266d7 527 //
Carobon 0:7321514266d7 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
Carobon 0:7321514266d7 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
Carobon 0:7321514266d7 530 // ======== ============= ===== ===== ===== =====
Carobon 0:7321514266d7 531 // 4 bytes 1 uid0 uid1 uid2 uid3
Carobon 0:7321514266d7 532 // 7 bytes 1 CT uid0 uid1 uid2
Carobon 0:7321514266d7 533 // 2 uid3 uid4 uid5 uid6
Carobon 0:7321514266d7 534 // 10 bytes 1 CT uid0 uid1 uid2
Carobon 0:7321514266d7 535 // 2 CT uid3 uid4 uid5
Carobon 0:7321514266d7 536 // 3 uid6 uid7 uid8 uid9
Carobon 0:7321514266d7 537
Carobon 0:7321514266d7 538 // Sanity checks
Carobon 0:7321514266d7 539 if (validBits > 80)
Carobon 0:7321514266d7 540 {
Carobon 0:7321514266d7 541 return STATUS_INVALID;
Carobon 0:7321514266d7 542 }
Carobon 0:7321514266d7 543
Carobon 0:7321514266d7 544 // Prepare MFRC522
Carobon 0:7321514266d7 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
Carobon 0:7321514266d7 546 PCD_ClrRegisterBits(CollReg, 0x80);
Carobon 0:7321514266d7 547
Carobon 0:7321514266d7 548 // Repeat Cascade Level loop until we have a complete UID.
Carobon 0:7321514266d7 549 uidComplete = false;
Carobon 0:7321514266d7 550 while ( ! uidComplete)
Carobon 0:7321514266d7 551 {
Carobon 0:7321514266d7 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
Carobon 0:7321514266d7 553 switch (cascadeLevel)
Carobon 0:7321514266d7 554 {
Carobon 0:7321514266d7 555 case 1:
Carobon 0:7321514266d7 556 buffer[0] = PICC_CMD_SEL_CL1;
Carobon 0:7321514266d7 557 uidIndex = 0;
Carobon 0:7321514266d7 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
Carobon 0:7321514266d7 559 break;
Carobon 0:7321514266d7 560
Carobon 0:7321514266d7 561 case 2:
Carobon 0:7321514266d7 562 buffer[0] = PICC_CMD_SEL_CL2;
Carobon 0:7321514266d7 563 uidIndex = 3;
Carobon 0:7321514266d7 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
Carobon 0:7321514266d7 565 break;
Carobon 0:7321514266d7 566
Carobon 0:7321514266d7 567 case 3:
Carobon 0:7321514266d7 568 buffer[0] = PICC_CMD_SEL_CL3;
Carobon 0:7321514266d7 569 uidIndex = 6;
Carobon 0:7321514266d7 570 useCascadeTag = false; // Never used in CL3.
Carobon 0:7321514266d7 571 break;
Carobon 0:7321514266d7 572
Carobon 0:7321514266d7 573 default:
Carobon 0:7321514266d7 574 return STATUS_INTERNAL_ERROR;
Carobon 0:7321514266d7 575 //break;
Carobon 0:7321514266d7 576 }
Carobon 0:7321514266d7 577
Carobon 0:7321514266d7 578 // How many UID bits are known in this Cascade Level?
Carobon 0:7321514266d7 579 if(validBits > (8 * uidIndex))
Carobon 0:7321514266d7 580 {
Carobon 0:7321514266d7 581 currentLevelKnownBits = validBits - (8 * uidIndex);
Carobon 0:7321514266d7 582 }
Carobon 0:7321514266d7 583 else
Carobon 0:7321514266d7 584 {
Carobon 0:7321514266d7 585 currentLevelKnownBits = 0;
Carobon 0:7321514266d7 586 }
Carobon 0:7321514266d7 587
Carobon 0:7321514266d7 588 // Copy the known bits from uid->uidByte[] to buffer[]
Carobon 0:7321514266d7 589 index = 2; // destination index in buffer[]
Carobon 0:7321514266d7 590 if (useCascadeTag)
Carobon 0:7321514266d7 591 {
Carobon 0:7321514266d7 592 buffer[index++] = PICC_CMD_CT;
Carobon 0:7321514266d7 593 }
Carobon 0:7321514266d7 594
Carobon 0:7321514266d7 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
Carobon 0:7321514266d7 596 if (bytesToCopy)
Carobon 0:7321514266d7 597 {
Carobon 0:7321514266d7 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
Carobon 0:7321514266d7 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
Carobon 0:7321514266d7 600 if (bytesToCopy > maxBytes)
Carobon 0:7321514266d7 601 {
Carobon 0:7321514266d7 602 bytesToCopy = maxBytes;
Carobon 0:7321514266d7 603 }
Carobon 0:7321514266d7 604
Carobon 0:7321514266d7 605 for (count = 0; count < bytesToCopy; count++)
Carobon 0:7321514266d7 606 {
Carobon 0:7321514266d7 607 buffer[index++] = uid->uidByte[uidIndex + count];
Carobon 0:7321514266d7 608 }
Carobon 0:7321514266d7 609 }
Carobon 0:7321514266d7 610
Carobon 0:7321514266d7 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
Carobon 0:7321514266d7 612 if (useCascadeTag)
Carobon 0:7321514266d7 613 {
Carobon 0:7321514266d7 614 currentLevelKnownBits += 8;
Carobon 0:7321514266d7 615 }
Carobon 0:7321514266d7 616
Carobon 0:7321514266d7 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
Carobon 0:7321514266d7 618 selectDone = false;
Carobon 0:7321514266d7 619 while ( ! selectDone)
Carobon 0:7321514266d7 620 {
Carobon 0:7321514266d7 621 // Find out how many bits and bytes to send and receive.
Carobon 0:7321514266d7 622 if (currentLevelKnownBits >= 32)
Carobon 0:7321514266d7 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
Carobon 0:7321514266d7 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
Carobon 0:7321514266d7 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
Carobon 0:7321514266d7 626
Carobon 0:7321514266d7 627 // Calulate BCC - Block Check Character
Carobon 0:7321514266d7 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
Carobon 0:7321514266d7 629
Carobon 0:7321514266d7 630 // Calculate CRC_A
Carobon 0:7321514266d7 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
Carobon 0:7321514266d7 632 if (result != STATUS_OK)
Carobon 0:7321514266d7 633 {
Carobon 0:7321514266d7 634 return result;
Carobon 0:7321514266d7 635 }
Carobon 0:7321514266d7 636
Carobon 0:7321514266d7 637 txLastBits = 0; // 0 => All 8 bits are valid.
Carobon 0:7321514266d7 638 bufferUsed = 9;
Carobon 0:7321514266d7 639
Carobon 0:7321514266d7 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
Carobon 0:7321514266d7 641 responseBuffer = &buffer[6];
Carobon 0:7321514266d7 642 responseLength = 3;
Carobon 0:7321514266d7 643 }
Carobon 0:7321514266d7 644 else
Carobon 0:7321514266d7 645 { // This is an ANTICOLLISION.
Carobon 0:7321514266d7 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
Carobon 0:7321514266d7 647 txLastBits = currentLevelKnownBits % 8;
Carobon 0:7321514266d7 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
Carobon 0:7321514266d7 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
Carobon 0:7321514266d7 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
Carobon 0:7321514266d7 651 bufferUsed = index + (txLastBits ? 1 : 0);
Carobon 0:7321514266d7 652
Carobon 0:7321514266d7 653 // Store response in the unused part of buffer
Carobon 0:7321514266d7 654 responseBuffer = &buffer[index];
Carobon 0:7321514266d7 655 responseLength = sizeof(buffer) - index;
Carobon 0:7321514266d7 656 }
Carobon 0:7321514266d7 657
Carobon 0:7321514266d7 658 // Set bit adjustments
Carobon 0:7321514266d7 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
Carobon 0:7321514266d7 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
Carobon 0:7321514266d7 661
Carobon 0:7321514266d7 662 // Transmit the buffer and receive the response.
Carobon 0:7321514266d7 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
Carobon 0:7321514266d7 664 if (result == STATUS_COLLISION)
Carobon 0:7321514266d7 665 { // More than one PICC in the field => collision.
Carobon 0:7321514266d7 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
Carobon 0:7321514266d7 667 if (result & 0x20)
Carobon 0:7321514266d7 668 { // CollPosNotValid
Carobon 0:7321514266d7 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
Carobon 0:7321514266d7 670 }
Carobon 0:7321514266d7 671
Carobon 0:7321514266d7 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
Carobon 0:7321514266d7 673 if (collisionPos == 0)
Carobon 0:7321514266d7 674 {
Carobon 0:7321514266d7 675 collisionPos = 32;
Carobon 0:7321514266d7 676 }
Carobon 0:7321514266d7 677
Carobon 0:7321514266d7 678 if (collisionPos <= currentLevelKnownBits)
Carobon 0:7321514266d7 679 { // No progress - should not happen
Carobon 0:7321514266d7 680 return STATUS_INTERNAL_ERROR;
Carobon 0:7321514266d7 681 }
Carobon 0:7321514266d7 682
Carobon 0:7321514266d7 683 // Choose the PICC with the bit set.
Carobon 0:7321514266d7 684 currentLevelKnownBits = collisionPos;
Carobon 0:7321514266d7 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
Carobon 0:7321514266d7 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
Carobon 0:7321514266d7 687 buffer[index] |= (1 << count);
Carobon 0:7321514266d7 688 }
Carobon 0:7321514266d7 689 else if (result != STATUS_OK)
Carobon 0:7321514266d7 690 {
Carobon 0:7321514266d7 691 return result;
Carobon 0:7321514266d7 692 }
Carobon 0:7321514266d7 693 else
Carobon 0:7321514266d7 694 { // STATUS_OK
Carobon 0:7321514266d7 695 if (currentLevelKnownBits >= 32)
Carobon 0:7321514266d7 696 { // This was a SELECT.
Carobon 0:7321514266d7 697 selectDone = true; // No more anticollision
Carobon 0:7321514266d7 698 // We continue below outside the while.
Carobon 0:7321514266d7 699 }
Carobon 0:7321514266d7 700 else
Carobon 0:7321514266d7 701 { // This was an ANTICOLLISION.
Carobon 0:7321514266d7 702 // We now have all 32 bits of the UID in this Cascade Level
Carobon 0:7321514266d7 703 currentLevelKnownBits = 32;
Carobon 0:7321514266d7 704 // Run loop again to do the SELECT.
Carobon 0:7321514266d7 705 }
Carobon 0:7321514266d7 706 }
Carobon 0:7321514266d7 707 } // End of while ( ! selectDone)
Carobon 0:7321514266d7 708
Carobon 0:7321514266d7 709 // We do not check the CBB - it was constructed by us above.
Carobon 0:7321514266d7 710
Carobon 0:7321514266d7 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
Carobon 0:7321514266d7 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
Carobon 0:7321514266d7 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
Carobon 0:7321514266d7 714 for (count = 0; count < bytesToCopy; count++)
Carobon 0:7321514266d7 715 {
Carobon 0:7321514266d7 716 uid->uidByte[uidIndex + count] = buffer[index++];
Carobon 0:7321514266d7 717 }
Carobon 0:7321514266d7 718
Carobon 0:7321514266d7 719 // Check response SAK (Select Acknowledge)
Carobon 0:7321514266d7 720 if (responseLength != 3 || txLastBits != 0)
Carobon 0:7321514266d7 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
Carobon 0:7321514266d7 722 return STATUS_ERROR;
Carobon 0:7321514266d7 723 }
Carobon 0:7321514266d7 724
Carobon 0:7321514266d7 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
Carobon 0:7321514266d7 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
Carobon 0:7321514266d7 727 if (result != STATUS_OK)
Carobon 0:7321514266d7 728 {
Carobon 0:7321514266d7 729 return result;
Carobon 0:7321514266d7 730 }
Carobon 0:7321514266d7 731
Carobon 0:7321514266d7 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
Carobon 0:7321514266d7 733 {
Carobon 0:7321514266d7 734 return STATUS_CRC_WRONG;
Carobon 0:7321514266d7 735 }
Carobon 0:7321514266d7 736
Carobon 0:7321514266d7 737 if (responseBuffer[0] & 0x04)
Carobon 0:7321514266d7 738 { // Cascade bit set - UID not complete yes
Carobon 0:7321514266d7 739 cascadeLevel++;
Carobon 0:7321514266d7 740 }
Carobon 0:7321514266d7 741 else
Carobon 0:7321514266d7 742 {
Carobon 0:7321514266d7 743 uidComplete = true;
Carobon 0:7321514266d7 744 uid->sak = responseBuffer[0];
Carobon 0:7321514266d7 745 }
Carobon 0:7321514266d7 746 } // End of while ( ! uidComplete)
Carobon 0:7321514266d7 747
Carobon 0:7321514266d7 748 // Set correct uid->size
Carobon 0:7321514266d7 749 uid->size = 3 * cascadeLevel + 1;
Carobon 0:7321514266d7 750
Carobon 0:7321514266d7 751 return STATUS_OK;
Carobon 0:7321514266d7 752 } // End PICC_Select()
Carobon 0:7321514266d7 753
Carobon 0:7321514266d7 754 /*
Carobon 0:7321514266d7 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
Carobon 0:7321514266d7 756 */
Carobon 0:7321514266d7 757 uint8_t MFRC522::PICC_HaltA()
Carobon 0:7321514266d7 758 {
Carobon 0:7321514266d7 759 uint8_t result;
Carobon 0:7321514266d7 760 uint8_t buffer[4];
Carobon 0:7321514266d7 761
Carobon 0:7321514266d7 762 // Build command buffer
Carobon 0:7321514266d7 763 buffer[0] = PICC_CMD_HLTA;
Carobon 0:7321514266d7 764 buffer[1] = 0;
Carobon 0:7321514266d7 765
Carobon 0:7321514266d7 766 // Calculate CRC_A
Carobon 0:7321514266d7 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
Carobon 0:7321514266d7 768 if (result == STATUS_OK)
Carobon 0:7321514266d7 769 {
Carobon 0:7321514266d7 770 // Send the command.
Carobon 0:7321514266d7 771 // The standard says:
Carobon 0:7321514266d7 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
Carobon 0:7321514266d7 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
Carobon 0:7321514266d7 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
Carobon 0:7321514266d7 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
Carobon 0:7321514266d7 776 if (result == STATUS_TIMEOUT)
Carobon 0:7321514266d7 777 {
Carobon 0:7321514266d7 778 result = STATUS_OK;
Carobon 0:7321514266d7 779 }
Carobon 0:7321514266d7 780 else if (result == STATUS_OK)
Carobon 0:7321514266d7 781 { // That is ironically NOT ok in this case ;-)
Carobon 0:7321514266d7 782 result = STATUS_ERROR;
Carobon 0:7321514266d7 783 }
Carobon 0:7321514266d7 784 }
Carobon 0:7321514266d7 785
Carobon 0:7321514266d7 786 return result;
Carobon 0:7321514266d7 787 } // End PICC_HaltA()
Carobon 0:7321514266d7 788
Carobon 0:7321514266d7 789
Carobon 0:7321514266d7 790 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 791 // Functions for communicating with MIFARE PICCs
Carobon 0:7321514266d7 792 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 793
Carobon 0:7321514266d7 794 /*
Carobon 0:7321514266d7 795 * Executes the MFRC522 MFAuthent command.
Carobon 0:7321514266d7 796 */
Carobon 0:7321514266d7 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
Carobon 0:7321514266d7 798 {
Carobon 0:7321514266d7 799 uint8_t i, waitIRq = 0x10; // IdleIRq
Carobon 0:7321514266d7 800
Carobon 0:7321514266d7 801 // Build command buffer
Carobon 0:7321514266d7 802 uint8_t sendData[12];
Carobon 0:7321514266d7 803 sendData[0] = command;
Carobon 0:7321514266d7 804 sendData[1] = blockAddr;
Carobon 0:7321514266d7 805
Carobon 0:7321514266d7 806 for (i = 0; i < MF_KEY_SIZE; i++)
Carobon 0:7321514266d7 807 { // 6 key bytes
Carobon 0:7321514266d7 808 sendData[2+i] = key->keyByte[i];
Carobon 0:7321514266d7 809 }
Carobon 0:7321514266d7 810
Carobon 0:7321514266d7 811 for (i = 0; i < 4; i++)
Carobon 0:7321514266d7 812 { // The first 4 bytes of the UID
Carobon 0:7321514266d7 813 sendData[8+i] = uid->uidByte[i];
Carobon 0:7321514266d7 814 }
Carobon 0:7321514266d7 815
Carobon 0:7321514266d7 816 // Start the authentication.
Carobon 0:7321514266d7 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
Carobon 0:7321514266d7 818 } // End PCD_Authenticate()
Carobon 0:7321514266d7 819
Carobon 0:7321514266d7 820 /*
Carobon 0:7321514266d7 821 * Used to exit the PCD from its authenticated state.
Carobon 0:7321514266d7 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
Carobon 0:7321514266d7 823 */
Carobon 0:7321514266d7 824 void MFRC522::PCD_StopCrypto1()
Carobon 0:7321514266d7 825 {
Carobon 0:7321514266d7 826 // Clear MFCrypto1On bit
Carobon 0:7321514266d7 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
Carobon 0:7321514266d7 828 } // End PCD_StopCrypto1()
Carobon 0:7321514266d7 829
Carobon 0:7321514266d7 830 /*
Carobon 0:7321514266d7 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
Carobon 0:7321514266d7 832 */
Carobon 0:7321514266d7 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
Carobon 0:7321514266d7 834 {
Carobon 0:7321514266d7 835 uint8_t result = STATUS_NO_ROOM;
Carobon 0:7321514266d7 836
Carobon 0:7321514266d7 837 // Sanity check
Carobon 0:7321514266d7 838 if ((buffer == NULL) || (*bufferSize < 18))
Carobon 0:7321514266d7 839 {
Carobon 0:7321514266d7 840 return result;
Carobon 0:7321514266d7 841 }
Carobon 0:7321514266d7 842
Carobon 0:7321514266d7 843 // Build command buffer
Carobon 0:7321514266d7 844 buffer[0] = PICC_CMD_MF_READ;
Carobon 0:7321514266d7 845 buffer[1] = blockAddr;
Carobon 0:7321514266d7 846
Carobon 0:7321514266d7 847 // Calculate CRC_A
Carobon 0:7321514266d7 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
Carobon 0:7321514266d7 849 if (result != STATUS_OK)
Carobon 0:7321514266d7 850 {
Carobon 0:7321514266d7 851 return result;
Carobon 0:7321514266d7 852 }
Carobon 0:7321514266d7 853
Carobon 0:7321514266d7 854 // Transmit the buffer and receive the response, validate CRC_A.
Carobon 0:7321514266d7 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
Carobon 0:7321514266d7 856 } // End MIFARE_Read()
Carobon 0:7321514266d7 857
Carobon 0:7321514266d7 858 /*
Carobon 0:7321514266d7 859 * Writes 16 bytes to the active PICC.
Carobon 0:7321514266d7 860 */
Carobon 0:7321514266d7 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
Carobon 0:7321514266d7 862 {
Carobon 0:7321514266d7 863 uint8_t result;
Carobon 0:7321514266d7 864
Carobon 0:7321514266d7 865 // Sanity check
Carobon 0:7321514266d7 866 if (buffer == NULL || bufferSize < 16)
Carobon 0:7321514266d7 867 {
Carobon 0:7321514266d7 868 return STATUS_INVALID;
Carobon 0:7321514266d7 869 }
Carobon 0:7321514266d7 870
Carobon 0:7321514266d7 871 // Mifare Classic protocol requires two communications to perform a write.
Carobon 0:7321514266d7 872 // Step 1: Tell the PICC we want to write to block blockAddr.
Carobon 0:7321514266d7 873 uint8_t cmdBuffer[2];
Carobon 0:7321514266d7 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
Carobon 0:7321514266d7 875 cmdBuffer[1] = blockAddr;
Carobon 0:7321514266d7 876 // Adds CRC_A and checks that the response is MF_ACK.
Carobon 0:7321514266d7 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
Carobon 0:7321514266d7 878 if (result != STATUS_OK)
Carobon 0:7321514266d7 879 {
Carobon 0:7321514266d7 880 return result;
Carobon 0:7321514266d7 881 }
Carobon 0:7321514266d7 882
Carobon 0:7321514266d7 883 // Step 2: Transfer the data
Carobon 0:7321514266d7 884 // Adds CRC_A and checks that the response is MF_ACK.
Carobon 0:7321514266d7 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
Carobon 0:7321514266d7 886 if (result != STATUS_OK)
Carobon 0:7321514266d7 887 {
Carobon 0:7321514266d7 888 return result;
Carobon 0:7321514266d7 889 }
Carobon 0:7321514266d7 890
Carobon 0:7321514266d7 891 return STATUS_OK;
Carobon 0:7321514266d7 892 } // End MIFARE_Write()
Carobon 0:7321514266d7 893
Carobon 0:7321514266d7 894 /*
Carobon 0:7321514266d7 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
Carobon 0:7321514266d7 896 */
Carobon 0:7321514266d7 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
Carobon 0:7321514266d7 898 {
Carobon 0:7321514266d7 899 uint8_t result;
Carobon 0:7321514266d7 900
Carobon 0:7321514266d7 901 // Sanity check
Carobon 0:7321514266d7 902 if (buffer == NULL || bufferSize < 4)
Carobon 0:7321514266d7 903 {
Carobon 0:7321514266d7 904 return STATUS_INVALID;
Carobon 0:7321514266d7 905 }
Carobon 0:7321514266d7 906
Carobon 0:7321514266d7 907 // Build commmand buffer
Carobon 0:7321514266d7 908 uint8_t cmdBuffer[6];
Carobon 0:7321514266d7 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
Carobon 0:7321514266d7 910 cmdBuffer[1] = page;
Carobon 0:7321514266d7 911 memcpy(&cmdBuffer[2], buffer, 4);
Carobon 0:7321514266d7 912
Carobon 0:7321514266d7 913 // Perform the write
Carobon 0:7321514266d7 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
Carobon 0:7321514266d7 915 if (result != STATUS_OK)
Carobon 0:7321514266d7 916 {
Carobon 0:7321514266d7 917 return result;
Carobon 0:7321514266d7 918 }
Carobon 0:7321514266d7 919
Carobon 0:7321514266d7 920 return STATUS_OK;
Carobon 0:7321514266d7 921 } // End MIFARE_Ultralight_Write()
Carobon 0:7321514266d7 922
Carobon 0:7321514266d7 923 /*
Carobon 0:7321514266d7 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
Carobon 0:7321514266d7 925 */
Carobon 0:7321514266d7 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
Carobon 0:7321514266d7 927 {
Carobon 0:7321514266d7 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
Carobon 0:7321514266d7 929 } // End MIFARE_Decrement()
Carobon 0:7321514266d7 930
Carobon 0:7321514266d7 931 /*
Carobon 0:7321514266d7 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
Carobon 0:7321514266d7 933 */
Carobon 0:7321514266d7 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
Carobon 0:7321514266d7 935 {
Carobon 0:7321514266d7 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
Carobon 0:7321514266d7 937 } // End MIFARE_Increment()
Carobon 0:7321514266d7 938
Carobon 0:7321514266d7 939 /**
Carobon 0:7321514266d7 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
Carobon 0:7321514266d7 941 */
Carobon 0:7321514266d7 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
Carobon 0:7321514266d7 943 {
Carobon 0:7321514266d7 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
Carobon 0:7321514266d7 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
Carobon 0:7321514266d7 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
Carobon 0:7321514266d7 947 } // End MIFARE_Restore()
Carobon 0:7321514266d7 948
Carobon 0:7321514266d7 949 /*
Carobon 0:7321514266d7 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
Carobon 0:7321514266d7 951 */
Carobon 0:7321514266d7 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
Carobon 0:7321514266d7 953 {
Carobon 0:7321514266d7 954 uint8_t result;
Carobon 0:7321514266d7 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
Carobon 0:7321514266d7 956
Carobon 0:7321514266d7 957 // Step 1: Tell the PICC the command and block address
Carobon 0:7321514266d7 958 cmdBuffer[0] = command;
Carobon 0:7321514266d7 959 cmdBuffer[1] = blockAddr;
Carobon 0:7321514266d7 960
Carobon 0:7321514266d7 961 // Adds CRC_A and checks that the response is MF_ACK.
Carobon 0:7321514266d7 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
Carobon 0:7321514266d7 963 if (result != STATUS_OK)
Carobon 0:7321514266d7 964 {
Carobon 0:7321514266d7 965 return result;
Carobon 0:7321514266d7 966 }
Carobon 0:7321514266d7 967
Carobon 0:7321514266d7 968 // Step 2: Transfer the data
Carobon 0:7321514266d7 969 // Adds CRC_A and accept timeout as success.
Carobon 0:7321514266d7 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
Carobon 0:7321514266d7 971 if (result != STATUS_OK)
Carobon 0:7321514266d7 972 {
Carobon 0:7321514266d7 973 return result;
Carobon 0:7321514266d7 974 }
Carobon 0:7321514266d7 975
Carobon 0:7321514266d7 976 return STATUS_OK;
Carobon 0:7321514266d7 977 } // End MIFARE_TwoStepHelper()
Carobon 0:7321514266d7 978
Carobon 0:7321514266d7 979 /*
Carobon 0:7321514266d7 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
Carobon 0:7321514266d7 981 */
Carobon 0:7321514266d7 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
Carobon 0:7321514266d7 983 {
Carobon 0:7321514266d7 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
Carobon 0:7321514266d7 985
Carobon 0:7321514266d7 986 // Tell the PICC we want to transfer the result into block blockAddr.
Carobon 0:7321514266d7 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
Carobon 0:7321514266d7 988 cmdBuffer[1] = blockAddr;
Carobon 0:7321514266d7 989
Carobon 0:7321514266d7 990 // Adds CRC_A and checks that the response is MF_ACK.
Carobon 0:7321514266d7 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
Carobon 0:7321514266d7 992 } // End MIFARE_Transfer()
Carobon 0:7321514266d7 993
Carobon 0:7321514266d7 994
Carobon 0:7321514266d7 995 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 996 // Support functions
Carobon 0:7321514266d7 997 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 998
Carobon 0:7321514266d7 999 /*
Carobon 0:7321514266d7 1000 * Wrapper for MIFARE protocol communication.
Carobon 0:7321514266d7 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
Carobon 0:7321514266d7 1002 */
Carobon 0:7321514266d7 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
Carobon 0:7321514266d7 1004 {
Carobon 0:7321514266d7 1005 uint8_t result;
Carobon 0:7321514266d7 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
Carobon 0:7321514266d7 1007
Carobon 0:7321514266d7 1008 // Sanity check
Carobon 0:7321514266d7 1009 if (sendData == NULL || sendLen > 16)
Carobon 0:7321514266d7 1010 {
Carobon 0:7321514266d7 1011 return STATUS_INVALID;
Carobon 0:7321514266d7 1012 }
Carobon 0:7321514266d7 1013
Carobon 0:7321514266d7 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
Carobon 0:7321514266d7 1015 memcpy(cmdBuffer, sendData, sendLen);
Carobon 0:7321514266d7 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
Carobon 0:7321514266d7 1017 if (result != STATUS_OK)
Carobon 0:7321514266d7 1018 {
Carobon 0:7321514266d7 1019 return result;
Carobon 0:7321514266d7 1020 }
Carobon 0:7321514266d7 1021
Carobon 0:7321514266d7 1022 sendLen += 2;
Carobon 0:7321514266d7 1023
Carobon 0:7321514266d7 1024 // Transceive the data, store the reply in cmdBuffer[]
Carobon 0:7321514266d7 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
Carobon 0:7321514266d7 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
Carobon 0:7321514266d7 1027 uint8_t validBits = 0;
Carobon 0:7321514266d7 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
Carobon 0:7321514266d7 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
Carobon 0:7321514266d7 1030 {
Carobon 0:7321514266d7 1031 return STATUS_OK;
Carobon 0:7321514266d7 1032 }
Carobon 0:7321514266d7 1033
Carobon 0:7321514266d7 1034 if (result != STATUS_OK)
Carobon 0:7321514266d7 1035 {
Carobon 0:7321514266d7 1036 return result;
Carobon 0:7321514266d7 1037 }
Carobon 0:7321514266d7 1038
Carobon 0:7321514266d7 1039 // The PICC must reply with a 4 bit ACK
Carobon 0:7321514266d7 1040 if (cmdBufferSize != 1 || validBits != 4)
Carobon 0:7321514266d7 1041 {
Carobon 0:7321514266d7 1042 return STATUS_ERROR;
Carobon 0:7321514266d7 1043 }
Carobon 0:7321514266d7 1044
Carobon 0:7321514266d7 1045 if (cmdBuffer[0] != MF_ACK)
Carobon 0:7321514266d7 1046 {
Carobon 0:7321514266d7 1047 return STATUS_MIFARE_NACK;
Carobon 0:7321514266d7 1048 }
Carobon 0:7321514266d7 1049
Carobon 0:7321514266d7 1050 return STATUS_OK;
Carobon 0:7321514266d7 1051 } // End PCD_MIFARE_Transceive()
Carobon 0:7321514266d7 1052
Carobon 0:7321514266d7 1053
Carobon 0:7321514266d7 1054 /*
Carobon 0:7321514266d7 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
Carobon 0:7321514266d7 1056 */
Carobon 0:7321514266d7 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
Carobon 0:7321514266d7 1058 {
Carobon 0:7321514266d7 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
Carobon 0:7321514266d7 1060
Carobon 0:7321514266d7 1061 if (sak & 0x04)
Carobon 0:7321514266d7 1062 { // UID not complete
Carobon 0:7321514266d7 1063 retType = PICC_TYPE_NOT_COMPLETE;
Carobon 0:7321514266d7 1064 }
Carobon 0:7321514266d7 1065 else
Carobon 0:7321514266d7 1066 {
Carobon 0:7321514266d7 1067 switch (sak)
Carobon 0:7321514266d7 1068 {
Carobon 0:7321514266d7 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
Carobon 0:7321514266d7 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
Carobon 0:7321514266d7 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
Carobon 0:7321514266d7 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
Carobon 0:7321514266d7 1073 case 0x10:
Carobon 0:7321514266d7 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
Carobon 0:7321514266d7 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
Carobon 0:7321514266d7 1076 default:
Carobon 0:7321514266d7 1077 if (sak & 0x20)
Carobon 0:7321514266d7 1078 {
Carobon 0:7321514266d7 1079 retType = PICC_TYPE_ISO_14443_4;
Carobon 0:7321514266d7 1080 }
Carobon 0:7321514266d7 1081 else if (sak & 0x40)
Carobon 0:7321514266d7 1082 {
Carobon 0:7321514266d7 1083 retType = PICC_TYPE_ISO_18092;
Carobon 0:7321514266d7 1084 }
Carobon 0:7321514266d7 1085 break;
Carobon 0:7321514266d7 1086 }
Carobon 0:7321514266d7 1087 }
Carobon 0:7321514266d7 1088
Carobon 0:7321514266d7 1089 return (retType);
Carobon 0:7321514266d7 1090 } // End PICC_GetType()
Carobon 0:7321514266d7 1091
Carobon 0:7321514266d7 1092 /*
Carobon 0:7321514266d7 1093 * Returns a string pointer to the PICC type name.
Carobon 0:7321514266d7 1094 */
Carobon 0:7321514266d7 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
Carobon 0:7321514266d7 1096 {
Carobon 0:7321514266d7 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
Carobon 0:7321514266d7 1098 {
Carobon 0:7321514266d7 1099 piccType = MFRC522_MaxPICCs - 1;
Carobon 0:7321514266d7 1100 }
Carobon 0:7321514266d7 1101
Carobon 0:7321514266d7 1102 return((char *) _TypeNamePICC[piccType]);
Carobon 0:7321514266d7 1103 } // End PICC_GetTypeName()
Carobon 0:7321514266d7 1104
Carobon 0:7321514266d7 1105 /*
Carobon 0:7321514266d7 1106 * Returns a string pointer to a status code name.
Carobon 0:7321514266d7 1107 */
Carobon 0:7321514266d7 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
Carobon 0:7321514266d7 1109 {
Carobon 0:7321514266d7 1110 return((char *) _ErrorMessage[code]);
Carobon 0:7321514266d7 1111 } // End GetStatusCodeName()
Carobon 0:7321514266d7 1112
Carobon 0:7321514266d7 1113 /*
Carobon 0:7321514266d7 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
Carobon 0:7321514266d7 1115 */
Carobon 0:7321514266d7 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
Carobon 0:7321514266d7 1117 uint8_t g0,
Carobon 0:7321514266d7 1118 uint8_t g1,
Carobon 0:7321514266d7 1119 uint8_t g2,
Carobon 0:7321514266d7 1120 uint8_t g3)
Carobon 0:7321514266d7 1121 {
Carobon 0:7321514266d7 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
Carobon 0:7321514266d7 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
Carobon 0:7321514266d7 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
Carobon 0:7321514266d7 1125
Carobon 0:7321514266d7 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
Carobon 0:7321514266d7 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
Carobon 0:7321514266d7 1128 accessBitBuffer[2] = c3 << 4 | c2;
Carobon 0:7321514266d7 1129 } // End MIFARE_SetAccessBits()
Carobon 0:7321514266d7 1130
Carobon 0:7321514266d7 1131 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 1132 // Convenience functions - does not add extra functionality
Carobon 0:7321514266d7 1133 /////////////////////////////////////////////////////////////////////////////////////
Carobon 0:7321514266d7 1134
Carobon 0:7321514266d7 1135 /*
Carobon 0:7321514266d7 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
Carobon 0:7321514266d7 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
Carobon 0:7321514266d7 1138 */
Carobon 0:7321514266d7 1139 bool MFRC522::PICC_IsNewCardPresent(void)
Carobon 0:7321514266d7 1140 {
Carobon 0:7321514266d7 1141 uint8_t bufferATQA[2];
Carobon 0:7321514266d7 1142 uint8_t bufferSize = sizeof(bufferATQA);
Carobon 0:7321514266d7 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
Carobon 0:7321514266d7 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
Carobon 0:7321514266d7 1145 } // End PICC_IsNewCardPresent()
Carobon 0:7321514266d7 1146
Carobon 0:7321514266d7 1147 /*
Carobon 0:7321514266d7 1148 * Simple wrapper around PICC_Select.
Carobon 0:7321514266d7 1149 */
Carobon 0:7321514266d7 1150 bool MFRC522::PICC_ReadCardSerial(void)
Carobon 0:7321514266d7 1151 {
Carobon 0:7321514266d7 1152 uint8_t result = PICC_Select(&uid);
Carobon 0:7321514266d7 1153 return (result == STATUS_OK);
Carobon 0:7321514266d7 1154 } // End PICC_ReadCardSerial()