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sx1272/sx1272-hal.cpp@2:cd1093b6676f, 2016-02-17 (annotated)

Committer:
GregCr
Date:
Wed Feb 17 09:17:18 2016 +0000
Revision:
2:cd1093b6676f
Parent:
1:b0372ef620d0
Child:
4:90bd79f1b458
Child:
7:b988b60083a1
update for SX1272MB2xAS

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: -
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272-hal.h"
mluis 0:45c4f0364ca4 16
GregCr 2:cd1093b6676f 17 const RadioRegisters_t SX1272MB2xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
mluis 0:45c4f0364ca4 18
GregCr 2:cd1093b6676f 19 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events,
mluis 0:45c4f0364ca4 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
mluis 0:45c4f0364ca4 22 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 23 PinName rfSwitchCntr1, PinName rfSwitchCntr2 )
dudmuck 1:b0372ef620d0 24 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 25 PinName txctl, PinName rxctl )
mluis 0:45c4f0364ca4 26 #else
mluis 0:45c4f0364ca4 27 PinName antSwitch )
mluis 0:45c4f0364ca4 28 #endif
mluis 0:45c4f0364ca4 29 : SX1272( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
mluis 0:45c4f0364ca4 30 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 31 RfSwitchCntr1( rfSwitchCntr1 ),
mluis 0:45c4f0364ca4 32 RfSwitchCntr2( rfSwitchCntr2 ),
dudmuck 1:b0372ef620d0 33 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 34 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 35 TxCtl ( txctl ),
dudmuck 1:b0372ef620d0 36 RxCtl ( rxctl )
mluis 0:45c4f0364ca4 37 #else
mluis 0:45c4f0364ca4 38 AntSwitch( antSwitch ),
mluis 0:45c4f0364ca4 39 #if( defined ( TARGET_NUCLEO_L152RE ) )
dudmuck 1:b0372ef620d0 40 Fake( D8 )
mluis 0:45c4f0364ca4 41 #else
mluis 0:45c4f0364ca4 42 Fake( A3 )
mluis 0:45c4f0364ca4 43 #endif
mluis 0:45c4f0364ca4 44 #endif
mluis 0:45c4f0364ca4 45 {
mluis 0:45c4f0364ca4 46 this->RadioEvents = events;
mluis 0:45c4f0364ca4 47
mluis 0:45c4f0364ca4 48 Reset( );
mluis 0:45c4f0364ca4 49
mluis 0:45c4f0364ca4 50 IoInit( );
mluis 0:45c4f0364ca4 51
mluis 0:45c4f0364ca4 52 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 53
mluis 0:45c4f0364ca4 54 IoIrqInit( dioIrq );
mluis 0:45c4f0364ca4 55
mluis 0:45c4f0364ca4 56 RadioRegistersInit( );
mluis 0:45c4f0364ca4 57
mluis 0:45c4f0364ca4 58 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 59
mluis 0:45c4f0364ca4 60 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 61 }
mluis 0:45c4f0364ca4 62
GregCr 2:cd1093b6676f 63 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events )
mluis 0:45c4f0364ca4 64 #if defined ( TARGET_NUCLEO_L152RE )
mluis 0:45c4f0364ca4 65 : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
mluis 0:45c4f0364ca4 66 AntSwitch( A4 ),
mluis 0:45c4f0364ca4 67 Fake( D8 )
mluis 0:45c4f0364ca4 68 #elif defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 69 : SX1272( events, PB_15, PB_14, PB_13, PB_12, PC_2, PC_6, PC_10, PC_11, PC_8, PC_9, PC_12 ),
mluis 0:45c4f0364ca4 70 RfSwitchCntr1( PC_4 ),
mluis 0:45c4f0364ca4 71 RfSwitchCntr2( PC_13 ),
mluis 0:45c4f0364ca4 72 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 73 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 74 : SX1272( events, LORA_MOSI, LORA_MISO, LORA_SCK, LORA_NSS, LORA_RESET, LORA_DIO0, LORA_DIO1, LORA_DIO2, LORA_DIO3, LORA_DIO4, LORA_DIO5 ),
dudmuck 1:b0372ef620d0 75 TxCtl( LORA_TXCTL ),
dudmuck 1:b0372ef620d0 76 RxCtl( LORA_RXCTL )
mluis 0:45c4f0364ca4 77 #else
mluis 0:45c4f0364ca4 78 : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 0:45c4f0364ca4 79 AntSwitch( A4 ),
mluis 0:45c4f0364ca4 80 Fake( A3 )
mluis 0:45c4f0364ca4 81 #endif
mluis 0:45c4f0364ca4 82 {
mluis 0:45c4f0364ca4 83 this->RadioEvents = events;
mluis 0:45c4f0364ca4 84
mluis 0:45c4f0364ca4 85 Reset( );
mluis 0:45c4f0364ca4 86
mluis 0:45c4f0364ca4 87 boardConnected = UNKNOWN;
mluis 0:45c4f0364ca4 88
mluis 0:45c4f0364ca4 89 DetectBoardType( );
mluis 0:45c4f0364ca4 90
mluis 0:45c4f0364ca4 91 IoInit( );
mluis 0:45c4f0364ca4 92
mluis 0:45c4f0364ca4 93 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 94 IoIrqInit( dioIrq );
mluis 0:45c4f0364ca4 95
mluis 0:45c4f0364ca4 96 RadioRegistersInit( );
mluis 0:45c4f0364ca4 97
mluis 0:45c4f0364ca4 98 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 99
mluis 0:45c4f0364ca4 100 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 101 }
mluis 0:45c4f0364ca4 102
mluis 0:45c4f0364ca4 103 //-------------------------------------------------------------------------
mluis 0:45c4f0364ca4 104 // Board relative functions
mluis 0:45c4f0364ca4 105 //-------------------------------------------------------------------------
GregCr 2:cd1093b6676f 106 uint8_t SX1272MB2xAS::DetectBoardType( void )
mluis 0:45c4f0364ca4 107 {
mluis 0:45c4f0364ca4 108 if( boardConnected == UNKNOWN )
mluis 0:45c4f0364ca4 109 {
mluis 0:45c4f0364ca4 110 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 111 boardConnected = NA_MOTE_72;
dudmuck 1:b0372ef620d0 112 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 113 boardConnected = MDOT_F411RE;
mluis 0:45c4f0364ca4 114 #else
mluis 0:45c4f0364ca4 115 this->AntSwitch.input( );
mluis 0:45c4f0364ca4 116 wait_ms( 1 );
mluis 0:45c4f0364ca4 117 if( this->AntSwitch == 1 )
mluis 0:45c4f0364ca4 118 {
mluis 0:45c4f0364ca4 119 boardConnected = SX1272MB1DCS;
mluis 0:45c4f0364ca4 120 }
mluis 0:45c4f0364ca4 121 else
mluis 0:45c4f0364ca4 122 {
GregCr 2:cd1093b6676f 123 boardConnected = SX1272MB2XAS;
mluis 0:45c4f0364ca4 124 }
mluis 0:45c4f0364ca4 125 this->AntSwitch.output( );
mluis 0:45c4f0364ca4 126 wait_ms( 1 );
mluis 0:45c4f0364ca4 127 #endif
mluis 0:45c4f0364ca4 128 }
mluis 0:45c4f0364ca4 129 return ( boardConnected );
mluis 0:45c4f0364ca4 130 }
mluis 0:45c4f0364ca4 131
GregCr 2:cd1093b6676f 132 void SX1272MB2xAS::IoInit( void )
mluis 0:45c4f0364ca4 133 {
mluis 0:45c4f0364ca4 134 AntSwInit( );
mluis 0:45c4f0364ca4 135 SpiInit( );
mluis 0:45c4f0364ca4 136 }
mluis 0:45c4f0364ca4 137
GregCr 2:cd1093b6676f 138 void SX1272MB2xAS::RadioRegistersInit( )
mluis 0:45c4f0364ca4 139 {
mluis 0:45c4f0364ca4 140 uint8_t i = 0;
mluis 0:45c4f0364ca4 141 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
mluis 0:45c4f0364ca4 142 {
mluis 0:45c4f0364ca4 143 SetModem( RadioRegsInit[i].Modem );
mluis 0:45c4f0364ca4 144 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
mluis 0:45c4f0364ca4 145 }
mluis 0:45c4f0364ca4 146 }
mluis 0:45c4f0364ca4 147
GregCr 2:cd1093b6676f 148 void SX1272MB2xAS::SpiInit( void )
mluis 0:45c4f0364ca4 149 {
mluis 0:45c4f0364ca4 150 nss = 1;
mluis 0:45c4f0364ca4 151 spi.format( 8,0 );
mluis 0:45c4f0364ca4 152 uint32_t frequencyToSet = 8000000;
dudmuck 1:b0372ef620d0 153 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) || defined ( TARGET_MTS_MDOT_F411RE ) )
mluis 0:45c4f0364ca4 154 spi.frequency( frequencyToSet );
mluis 0:45c4f0364ca4 155 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
mluis 0:45c4f0364ca4 156 spi.frequency( frequencyToSet * 2 );
mluis 0:45c4f0364ca4 157 #else
mluis 0:45c4f0364ca4 158 #warning "Check the board's SPI frequency"
mluis 0:45c4f0364ca4 159 #endif
mluis 0:45c4f0364ca4 160 wait(0.1);
mluis 0:45c4f0364ca4 161 }
mluis 0:45c4f0364ca4 162
GregCr 2:cd1093b6676f 163 void SX1272MB2xAS::IoIrqInit( DioIrqHandler *irqHandlers )
mluis 0:45c4f0364ca4 164 {
mluis 0:45c4f0364ca4 165 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) )
mluis 0:45c4f0364ca4 166 dio0.mode( PullDown );
mluis 0:45c4f0364ca4 167 dio1.mode( PullDown );
mluis 0:45c4f0364ca4 168 dio2.mode( PullDown );
mluis 0:45c4f0364ca4 169 dio3.mode( PullDown );
mluis 0:45c4f0364ca4 170 dio4.mode( PullDown );
mluis 0:45c4f0364ca4 171 #endif
GregCr 2:cd1093b6676f 172 dio0.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[0] ) );
GregCr 2:cd1093b6676f 173 dio1.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[1] ) );
GregCr 2:cd1093b6676f 174 dio2.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[2] ) );
GregCr 2:cd1093b6676f 175 dio3.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[3] ) );
GregCr 2:cd1093b6676f 176 dio4.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[4] ) );
mluis 0:45c4f0364ca4 177 }
mluis 0:45c4f0364ca4 178
GregCr 2:cd1093b6676f 179 void SX1272MB2xAS::IoDeInit( void )
mluis 0:45c4f0364ca4 180 {
mluis 0:45c4f0364ca4 181 //nothing
mluis 0:45c4f0364ca4 182 }
mluis 0:45c4f0364ca4 183
GregCr 2:cd1093b6676f 184 uint8_t SX1272MB2xAS::GetPaSelect( uint32_t channel )
mluis 0:45c4f0364ca4 185 {
dudmuck 1:b0372ef620d0 186 if( boardConnected == SX1272MB1DCS || boardConnected == MDOT_F411RE )
mluis 0:45c4f0364ca4 187 {
mluis 0:45c4f0364ca4 188 return RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 189 }
mluis 0:45c4f0364ca4 190 else
mluis 0:45c4f0364ca4 191 {
mluis 0:45c4f0364ca4 192 return RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 193 }
mluis 0:45c4f0364ca4 194 }
mluis 0:45c4f0364ca4 195
GregCr 2:cd1093b6676f 196 void SX1272MB2xAS::SetAntSwLowPower( bool status )
mluis 0:45c4f0364ca4 197 {
mluis 0:45c4f0364ca4 198 if( isRadioActive != status )
mluis 0:45c4f0364ca4 199 {
mluis 0:45c4f0364ca4 200 isRadioActive = status;
mluis 0:45c4f0364ca4 201
mluis 0:45c4f0364ca4 202 if( status == false )
mluis 0:45c4f0364ca4 203 {
mluis 0:45c4f0364ca4 204 AntSwInit( );
mluis 0:45c4f0364ca4 205 }
mluis 0:45c4f0364ca4 206 else
mluis 0:45c4f0364ca4 207 {
mluis 0:45c4f0364ca4 208 AntSwDeInit( );
mluis 0:45c4f0364ca4 209 }
mluis 0:45c4f0364ca4 210 }
mluis 0:45c4f0364ca4 211 }
mluis 0:45c4f0364ca4 212
GregCr 2:cd1093b6676f 213 void SX1272MB2xAS::AntSwInit( void )
mluis 0:45c4f0364ca4 214 {
mluis 0:45c4f0364ca4 215 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 216 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 217 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 218 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 219 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 220 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 221 this->RxCtl = 0;
mluis 0:45c4f0364ca4 222 #else
mluis 0:45c4f0364ca4 223 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 224 #endif
mluis 0:45c4f0364ca4 225 }
mluis 0:45c4f0364ca4 226
GregCr 2:cd1093b6676f 227 void SX1272MB2xAS::AntSwDeInit( void )
mluis 0:45c4f0364ca4 228 {
mluis 0:45c4f0364ca4 229 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 230 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 231 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 232 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 233 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 234 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 235 this->RxCtl = 0;
mluis 0:45c4f0364ca4 236 #else
mluis 0:45c4f0364ca4 237 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 238 #endif
mluis 0:45c4f0364ca4 239 }
mluis 0:45c4f0364ca4 240
GregCr 2:cd1093b6676f 241 void SX1272MB2xAS::SetAntSw( uint8_t rxTx )
mluis 0:45c4f0364ca4 242 {
mluis 0:45c4f0364ca4 243 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 244 switch( this->currentOpMode )
mluis 0:45c4f0364ca4 245 {
mluis 0:45c4f0364ca4 246 case RFLR_OPMODE_TRANSMITTER:
mluis 0:45c4f0364ca4 247 if( ( Read( REG_PACONFIG ) & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 248 {
mluis 0:45c4f0364ca4 249 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 250 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 251 }
mluis 0:45c4f0364ca4 252 else
mluis 0:45c4f0364ca4 253 {
mluis 0:45c4f0364ca4 254 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 255 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 256 }
mluis 0:45c4f0364ca4 257 break;
mluis 0:45c4f0364ca4 258 case RFLR_OPMODE_RECEIVER:
mluis 0:45c4f0364ca4 259 case RFLR_OPMODE_RECEIVER_SINGLE:
mluis 0:45c4f0364ca4 260 case RFLR_OPMODE_CAD:
mluis 0:45c4f0364ca4 261 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 262 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 263 break;
mluis 0:45c4f0364ca4 264 default:
mluis 0:45c4f0364ca4 265 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 266 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 267 this->PwrAmpCntr = 0;
mluis 0:45c4f0364ca4 268 break;
mluis 0:45c4f0364ca4 269 }
dudmuck 1:b0372ef620d0 270 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 271 if( this->rxTx == rxTx )
dudmuck 1:b0372ef620d0 272 {
dudmuck 1:b0372ef620d0 273 //no need to go further
dudmuck 1:b0372ef620d0 274 return;
dudmuck 1:b0372ef620d0 275 }
dudmuck 1:b0372ef620d0 276
dudmuck 1:b0372ef620d0 277 /* SKY13350 */
dudmuck 1:b0372ef620d0 278 this->rxTx = rxTx;
dudmuck 1:b0372ef620d0 279
dudmuck 1:b0372ef620d0 280 // 1: Tx, 0: Rx
dudmuck 1:b0372ef620d0 281 if( rxTx != 0 )
dudmuck 1:b0372ef620d0 282 {
dudmuck 1:b0372ef620d0 283 this->TxCtl = 1;
dudmuck 1:b0372ef620d0 284 this->RxCtl = 0;
dudmuck 1:b0372ef620d0 285 }
dudmuck 1:b0372ef620d0 286 else
dudmuck 1:b0372ef620d0 287 {
dudmuck 1:b0372ef620d0 288 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 289 this->RxCtl = 1;
dudmuck 1:b0372ef620d0 290 }
mluis 0:45c4f0364ca4 291 #else
mluis 0:45c4f0364ca4 292 if( this->rxTx == rxTx )
mluis 0:45c4f0364ca4 293 {
mluis 0:45c4f0364ca4 294 //no need to go further
mluis 0:45c4f0364ca4 295 return;
mluis 0:45c4f0364ca4 296 }
mluis 0:45c4f0364ca4 297
mluis 0:45c4f0364ca4 298 this->rxTx = rxTx;
mluis 0:45c4f0364ca4 299
mluis 0:45c4f0364ca4 300 // 1: Tx, 0: Rx
mluis 0:45c4f0364ca4 301 if( rxTx != 0 )
mluis 0:45c4f0364ca4 302 {
mluis 0:45c4f0364ca4 303 this->AntSwitch = 1;
mluis 0:45c4f0364ca4 304 }
mluis 0:45c4f0364ca4 305 else
mluis 0:45c4f0364ca4 306 {
mluis 0:45c4f0364ca4 307 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 308 }
mluis 0:45c4f0364ca4 309 #endif
mluis 0:45c4f0364ca4 310 }
mluis 0:45c4f0364ca4 311
GregCr 2:cd1093b6676f 312 bool SX1272MB2xAS::CheckRfFrequency( uint32_t frequency )
mluis 0:45c4f0364ca4 313 {
mluis 0:45c4f0364ca4 314 //TODO: Implement check, currently all frequencies are supported
mluis 0:45c4f0364ca4 315 return true;
mluis 0:45c4f0364ca4 316 }
mluis 0:45c4f0364ca4 317
mluis 0:45c4f0364ca4 318
GregCr 2:cd1093b6676f 319 void SX1272MB2xAS::Reset( void )
mluis 0:45c4f0364ca4 320 {
mluis 0:45c4f0364ca4 321 reset.output();
mluis 0:45c4f0364ca4 322 reset = 0;
mluis 0:45c4f0364ca4 323 wait_ms( 1 );
mluis 0:45c4f0364ca4 324 reset.input();
mluis 0:45c4f0364ca4 325 wait_ms( 6 );
mluis 0:45c4f0364ca4 326 }
mluis 0:45c4f0364ca4 327
GregCr 2:cd1093b6676f 328 void SX1272MB2xAS::Write( uint8_t addr, uint8_t data )
mluis 0:45c4f0364ca4 329 {
mluis 0:45c4f0364ca4 330 Write( addr, &data, 1 );
mluis 0:45c4f0364ca4 331 }
mluis 0:45c4f0364ca4 332
GregCr 2:cd1093b6676f 333 uint8_t SX1272MB2xAS::Read( uint8_t addr )
mluis 0:45c4f0364ca4 334 {
mluis 0:45c4f0364ca4 335 uint8_t data;
mluis 0:45c4f0364ca4 336 Read( addr, &data, 1 );
mluis 0:45c4f0364ca4 337 return data;
mluis 0:45c4f0364ca4 338 }
mluis 0:45c4f0364ca4 339
GregCr 2:cd1093b6676f 340 void SX1272MB2xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 341 {
mluis 0:45c4f0364ca4 342 uint8_t i;
mluis 0:45c4f0364ca4 343
mluis 0:45c4f0364ca4 344 nss = 0;
mluis 0:45c4f0364ca4 345 spi.write( addr | 0x80 );
mluis 0:45c4f0364ca4 346 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 347 {
mluis 0:45c4f0364ca4 348 spi.write( buffer[i] );
mluis 0:45c4f0364ca4 349 }
mluis 0:45c4f0364ca4 350 nss = 1;
mluis 0:45c4f0364ca4 351 }
mluis 0:45c4f0364ca4 352
GregCr 2:cd1093b6676f 353 void SX1272MB2xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 354 {
mluis 0:45c4f0364ca4 355 uint8_t i;
mluis 0:45c4f0364ca4 356
mluis 0:45c4f0364ca4 357 nss = 0;
mluis 0:45c4f0364ca4 358 spi.write( addr & 0x7F );
mluis 0:45c4f0364ca4 359 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 360 {
mluis 0:45c4f0364ca4 361 buffer[i] = spi.write( 0 );
mluis 0:45c4f0364ca4 362 }
mluis 0:45c4f0364ca4 363 nss = 1;
mluis 0:45c4f0364ca4 364 }
mluis 0:45c4f0364ca4 365
GregCr 2:cd1093b6676f 366 void SX1272MB2xAS::WriteFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 367 {
mluis 0:45c4f0364ca4 368 Write( 0, buffer, size );
mluis 0:45c4f0364ca4 369 }
mluis 0:45c4f0364ca4 370
GregCr 2:cd1093b6676f 371 void SX1272MB2xAS::ReadFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 372 {
mluis 0:45c4f0364ca4 373 Read( 0, buffer, size );
mluis 0:45c4f0364ca4 374 }