MK64F12_fmc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_FMC_REGISTERS_H__
00088 #define __HW_FMC_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 FMC
00095  *
00096  * Flash Memory Controller
00097  *
00098  * Registers defined in this header file:
00099  * - HW_FMC_PFAPR - Flash Access Protection Register
00100  * - HW_FMC_PFB0CR - Flash Bank 0 Control Register
00101  * - HW_FMC_PFB1CR - Flash Bank 1 Control Register
00102  * - HW_FMC_TAGVDW0Sn - Cache Tag Storage
00103  * - HW_FMC_TAGVDW1Sn - Cache Tag Storage
00104  * - HW_FMC_TAGVDW2Sn - Cache Tag Storage
00105  * - HW_FMC_TAGVDW3Sn - Cache Tag Storage
00106  * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
00107  * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
00108  * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
00109  * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
00110  * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
00111  * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
00112  * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
00113  * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
00114  *
00115  * - hw_fmc_t - Struct containing all module registers.
00116  */
00117 
00118 #define HW_FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
00119 
00120 /*******************************************************************************
00121  * HW_FMC_PFAPR - Flash Access Protection Register
00122  ******************************************************************************/
00123 
00124 /*!
00125  * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
00126  *
00127  * Reset value: 0x00F8003FU
00128  */
00129 typedef union _hw_fmc_pfapr
00130 {
00131     uint32_t U;
00132     struct _hw_fmc_pfapr_bitfields
00133     {
00134         uint32_t M0AP : 2;             /*!< [1:0] Master 0 Access Protection */
00135         uint32_t M1AP : 2;             /*!< [3:2] Master 1 Access Protection */
00136         uint32_t M2AP : 2;             /*!< [5:4] Master 2 Access Protection */
00137         uint32_t M3AP : 2;             /*!< [7:6] Master 3 Access Protection */
00138         uint32_t M4AP : 2;             /*!< [9:8] Master 4 Access Protection */
00139         uint32_t M5AP : 2;             /*!< [11:10] Master 5 Access Protection */
00140         uint32_t M6AP : 2;             /*!< [13:12] Master 6 Access Protection */
00141         uint32_t M7AP : 2;             /*!< [15:14] Master 7 Access Protection */
00142         uint32_t M0PFD : 1;            /*!< [16] Master 0 Prefetch Disable */
00143         uint32_t M1PFD : 1;            /*!< [17] Master 1 Prefetch Disable */
00144         uint32_t M2PFD : 1;            /*!< [18] Master 2 Prefetch Disable */
00145         uint32_t M3PFD : 1;            /*!< [19] Master 3 Prefetch Disable */
00146         uint32_t M4PFD : 1;            /*!< [20] Master 4 Prefetch Disable */
00147         uint32_t M5PFD : 1;            /*!< [21] Master 5 Prefetch Disable */
00148         uint32_t M6PFD : 1;            /*!< [22] Master 6 Prefetch Disable */
00149         uint32_t M7PFD : 1;            /*!< [23] Master 7 Prefetch Disable */
00150         uint32_t RESERVED0 : 8;        /*!< [31:24]  */
00151     } B;
00152 } hw_fmc_pfapr_t;
00153 
00154 /*!
00155  * @name Constants and macros for entire FMC_PFAPR register
00156  */
00157 /*@{*/
00158 #define HW_FMC_PFAPR_ADDR(x)     ((x) + 0x0U)
00159 
00160 #define HW_FMC_PFAPR(x)          (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR(x))
00161 #define HW_FMC_PFAPR_RD(x)       (ADDRESS_READ(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x)))
00162 #define HW_FMC_PFAPR_WR(x, v)    (ADDRESS_WRITE(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x), v))
00163 #define HW_FMC_PFAPR_SET(x, v)   (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) |  (v)))
00164 #define HW_FMC_PFAPR_CLR(x, v)   (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) & ~(v)))
00165 #define HW_FMC_PFAPR_TOG(x, v)   (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) ^  (v)))
00166 /*@}*/
00167 
00168 /*
00169  * Constants & macros for individual FMC_PFAPR bitfields
00170  */
00171 
00172 /*!
00173  * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
00174  *
00175  * This field controls whether read and write access to the flash are allowed
00176  * based on the logical master number of the requesting crossbar switch master.
00177  *
00178  * Values:
00179  * - 00 - No access may be performed by this master
00180  * - 01 - Only read accesses may be performed by this master
00181  * - 10 - Only write accesses may be performed by this master
00182  * - 11 - Both read and write accesses may be performed by this master
00183  */
00184 /*@{*/
00185 #define BP_FMC_PFAPR_M0AP    (0U)          /*!< Bit position for FMC_PFAPR_M0AP. */
00186 #define BM_FMC_PFAPR_M0AP    (0x00000003U) /*!< Bit mask for FMC_PFAPR_M0AP. */
00187 #define BS_FMC_PFAPR_M0AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M0AP. */
00188 
00189 /*! @brief Read current value of the FMC_PFAPR_M0AP field. */
00190 #define BR_FMC_PFAPR_M0AP(x) (UNION_READ(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x), U, B.M0AP))
00191 
00192 /*! @brief Format value for bitfield FMC_PFAPR_M0AP. */
00193 #define BF_FMC_PFAPR_M0AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0AP) & BM_FMC_PFAPR_M0AP)
00194 
00195 /*! @brief Set the M0AP field to a new value. */
00196 #define BW_FMC_PFAPR_M0AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v)))
00197 /*@}*/
00198 
00199 /*!
00200  * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
00201  *
00202  * This field controls whether read and write access to the flash are allowed
00203  * based on the logical master number of the requesting crossbar switch master.
00204  *
00205  * Values:
00206  * - 00 - No access may be performed by this master
00207  * - 01 - Only read accesses may be performed by this master
00208  * - 10 - Only write accesses may be performed by this master
00209  * - 11 - Both read and write accesses may be performed by this master
00210  */
00211 /*@{*/
00212 #define BP_FMC_PFAPR_M1AP    (2U)          /*!< Bit position for FMC_PFAPR_M1AP. */
00213 #define BM_FMC_PFAPR_M1AP    (0x0000000CU) /*!< Bit mask for FMC_PFAPR_M1AP. */
00214 #define BS_FMC_PFAPR_M1AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M1AP. */
00215 
00216 /*! @brief Read current value of the FMC_PFAPR_M1AP field. */
00217 #define BR_FMC_PFAPR_M1AP(x) (UNION_READ(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x), U, B.M1AP))
00218 
00219 /*! @brief Format value for bitfield FMC_PFAPR_M1AP. */
00220 #define BF_FMC_PFAPR_M1AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1AP) & BM_FMC_PFAPR_M1AP)
00221 
00222 /*! @brief Set the M1AP field to a new value. */
00223 #define BW_FMC_PFAPR_M1AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v)))
00224 /*@}*/
00225 
00226 /*!
00227  * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
00228  *
00229  * This field controls whether read and write access to the flash are allowed
00230  * based on the logical master number of the requesting crossbar switch master.
00231  *
00232  * Values:
00233  * - 00 - No access may be performed by this master
00234  * - 01 - Only read accesses may be performed by this master
00235  * - 10 - Only write accesses may be performed by this master
00236  * - 11 - Both read and write accesses may be performed by this master
00237  */
00238 /*@{*/
00239 #define BP_FMC_PFAPR_M2AP    (4U)          /*!< Bit position for FMC_PFAPR_M2AP. */
00240 #define BM_FMC_PFAPR_M2AP    (0x00000030U) /*!< Bit mask for FMC_PFAPR_M2AP. */
00241 #define BS_FMC_PFAPR_M2AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M2AP. */
00242 
00243 /*! @brief Read current value of the FMC_PFAPR_M2AP field. */
00244 #define BR_FMC_PFAPR_M2AP(x) (UNION_READ(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x), U, B.M2AP))
00245 
00246 /*! @brief Format value for bitfield FMC_PFAPR_M2AP. */
00247 #define BF_FMC_PFAPR_M2AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2AP) & BM_FMC_PFAPR_M2AP)
00248 
00249 /*! @brief Set the M2AP field to a new value. */
00250 #define BW_FMC_PFAPR_M2AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v)))
00251 /*@}*/
00252 
00253 /*!
00254  * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
00255  *
00256  * This field controls whether read and write access to the flash are allowed
00257  * based on the logical master number of the requesting crossbar switch master.
00258  *
00259  * Values:
00260  * - 00 - No access may be performed by this master
00261  * - 01 - Only read accesses may be performed by this master
00262  * - 10 - Only write accesses may be performed by this master
00263  * - 11 - Both read and write accesses may be performed by this master
00264  */
00265 /*@{*/
00266 #define BP_FMC_PFAPR_M3AP    (6U)          /*!< Bit position for FMC_PFAPR_M3AP. */
00267 #define BM_FMC_PFAPR_M3AP    (0x000000C0U) /*!< Bit mask for FMC_PFAPR_M3AP. */
00268 #define BS_FMC_PFAPR_M3AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M3AP. */
00269 
00270 /*! @brief Read current value of the FMC_PFAPR_M3AP field. */
00271 #define BR_FMC_PFAPR_M3AP(x) (UNION_READ(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x), U, B.M3AP))
00272 
00273 /*! @brief Format value for bitfield FMC_PFAPR_M3AP. */
00274 #define BF_FMC_PFAPR_M3AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3AP) & BM_FMC_PFAPR_M3AP)
00275 
00276 /*! @brief Set the M3AP field to a new value. */
00277 #define BW_FMC_PFAPR_M3AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v)))
00278 /*@}*/
00279 
00280 /*!
00281  * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
00282  *
00283  * This field controls whether read and write access to the flash are allowed
00284  * based on the logical master number of the requesting crossbar switch master.
00285  *
00286  * Values:
00287  * - 00 - No access may be performed by this master
00288  * - 01 - Only read accesses may be performed by this master
00289  * - 10 - Only write accesses may be performed by this master
00290  * - 11 - Both read and write accesses may be performed by this master
00291  */
00292 /*@{*/
00293 #define BP_FMC_PFAPR_M4AP    (8U)          /*!< Bit position for FMC_PFAPR_M4AP. */
00294 #define BM_FMC_PFAPR_M4AP    (0x00000300U) /*!< Bit mask for FMC_PFAPR_M4AP. */
00295 #define BS_FMC_PFAPR_M4AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M4AP. */
00296 
00297 /*! @brief Read current value of the FMC_PFAPR_M4AP field. */
00298 #define BR_FMC_PFAPR_M4AP(x) (UNION_READ(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x), U, B.M4AP))
00299 
00300 /*! @brief Format value for bitfield FMC_PFAPR_M4AP. */
00301 #define BF_FMC_PFAPR_M4AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4AP) & BM_FMC_PFAPR_M4AP)
00302 
00303 /*! @brief Set the M4AP field to a new value. */
00304 #define BW_FMC_PFAPR_M4AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v)))
00305 /*@}*/
00306 
00307 /*!
00308  * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
00309  *
00310  * This field controls whether read and write access to the flash are allowed
00311  * based on the logical master number of the requesting crossbar switch master.
00312  *
00313  * Values:
00314  * - 00 - No access may be performed by this master
00315  * - 01 - Only read accesses may be performed by this master
00316  * - 10 - Only write accesses may be performed by this master
00317  * - 11 - Both read and write accesses may be performed by this master
00318  */
00319 /*@{*/
00320 #define BP_FMC_PFAPR_M5AP    (10U)         /*!< Bit position for FMC_PFAPR_M5AP. */
00321 #define BM_FMC_PFAPR_M5AP    (0x00000C00U) /*!< Bit mask for FMC_PFAPR_M5AP. */
00322 #define BS_FMC_PFAPR_M5AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M5AP. */
00323 
00324 /*! @brief Read current value of the FMC_PFAPR_M5AP field. */
00325 #define BR_FMC_PFAPR_M5AP(x) (UNION_READ(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x), U, B.M5AP))
00326 
00327 /*! @brief Format value for bitfield FMC_PFAPR_M5AP. */
00328 #define BF_FMC_PFAPR_M5AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5AP) & BM_FMC_PFAPR_M5AP)
00329 
00330 /*! @brief Set the M5AP field to a new value. */
00331 #define BW_FMC_PFAPR_M5AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v)))
00332 /*@}*/
00333 
00334 /*!
00335  * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
00336  *
00337  * This field controls whether read and write access to the flash are allowed
00338  * based on the logical master number of the requesting crossbar switch master.
00339  *
00340  * Values:
00341  * - 00 - No access may be performed by this master
00342  * - 01 - Only read accesses may be performed by this master
00343  * - 10 - Only write accesses may be performed by this master
00344  * - 11 - Both read and write accesses may be performed by this master
00345  */
00346 /*@{*/
00347 #define BP_FMC_PFAPR_M6AP    (12U)         /*!< Bit position for FMC_PFAPR_M6AP. */
00348 #define BM_FMC_PFAPR_M6AP    (0x00003000U) /*!< Bit mask for FMC_PFAPR_M6AP. */
00349 #define BS_FMC_PFAPR_M6AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M6AP. */
00350 
00351 /*! @brief Read current value of the FMC_PFAPR_M6AP field. */
00352 #define BR_FMC_PFAPR_M6AP(x) (UNION_READ(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x), U, B.M6AP))
00353 
00354 /*! @brief Format value for bitfield FMC_PFAPR_M6AP. */
00355 #define BF_FMC_PFAPR_M6AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6AP) & BM_FMC_PFAPR_M6AP)
00356 
00357 /*! @brief Set the M6AP field to a new value. */
00358 #define BW_FMC_PFAPR_M6AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v)))
00359 /*@}*/
00360 
00361 /*!
00362  * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
00363  *
00364  * This field controls whether read and write access to the flash are allowed
00365  * based on the logical master number of the requesting crossbar switch master.
00366  *
00367  * Values:
00368  * - 00 - No access may be performed by this master.
00369  * - 01 - Only read accesses may be performed by this master.
00370  * - 10 - Only write accesses may be performed by this master.
00371  * - 11 - Both read and write accesses may be performed by this master.
00372  */
00373 /*@{*/
00374 #define BP_FMC_PFAPR_M7AP    (14U)         /*!< Bit position for FMC_PFAPR_M7AP. */
00375 #define BM_FMC_PFAPR_M7AP    (0x0000C000U) /*!< Bit mask for FMC_PFAPR_M7AP. */
00376 #define BS_FMC_PFAPR_M7AP    (2U)          /*!< Bit field size in bits for FMC_PFAPR_M7AP. */
00377 
00378 /*! @brief Read current value of the FMC_PFAPR_M7AP field. */
00379 #define BR_FMC_PFAPR_M7AP(x) (UNION_READ(hw_fmc_pfapr_t, HW_FMC_PFAPR_ADDR(x), U, B.M7AP))
00380 
00381 /*! @brief Format value for bitfield FMC_PFAPR_M7AP. */
00382 #define BF_FMC_PFAPR_M7AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7AP) & BM_FMC_PFAPR_M7AP)
00383 
00384 /*! @brief Set the M7AP field to a new value. */
00385 #define BW_FMC_PFAPR_M7AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v)))
00386 /*@}*/
00387 
00388 /*!
00389  * @name Register FMC_PFAPR, field M0PFD[16] (RW)
00390  *
00391  * These bits control whether prefetching is enabled based on the logical number
00392  * of the requesting crossbar switch master. This field is further qualified by
00393  * the PFBnCR[BxDPE,BxIPE] bits.
00394  *
00395  * Values:
00396  * - 0 - Prefetching for this master is enabled.
00397  * - 1 - Prefetching for this master is disabled.
00398  */
00399 /*@{*/
00400 #define BP_FMC_PFAPR_M0PFD   (16U)         /*!< Bit position for FMC_PFAPR_M0PFD. */
00401 #define BM_FMC_PFAPR_M0PFD   (0x00010000U) /*!< Bit mask for FMC_PFAPR_M0PFD. */
00402 #define BS_FMC_PFAPR_M0PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M0PFD. */
00403 
00404 /*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
00405 #define BR_FMC_PFAPR_M0PFD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD)))
00406 
00407 /*! @brief Format value for bitfield FMC_PFAPR_M0PFD. */
00408 #define BF_FMC_PFAPR_M0PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0PFD) & BM_FMC_PFAPR_M0PFD)
00409 
00410 /*! @brief Set the M0PFD field to a new value. */
00411 #define BW_FMC_PFAPR_M0PFD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD), v))
00412 /*@}*/
00413 
00414 /*!
00415  * @name Register FMC_PFAPR, field M1PFD[17] (RW)
00416  *
00417  * These bits control whether prefetching is enabled based on the logical number
00418  * of the requesting crossbar switch master. This field is further qualified by
00419  * the PFBnCR[BxDPE,BxIPE] bits.
00420  *
00421  * Values:
00422  * - 0 - Prefetching for this master is enabled.
00423  * - 1 - Prefetching for this master is disabled.
00424  */
00425 /*@{*/
00426 #define BP_FMC_PFAPR_M1PFD   (17U)         /*!< Bit position for FMC_PFAPR_M1PFD. */
00427 #define BM_FMC_PFAPR_M1PFD   (0x00020000U) /*!< Bit mask for FMC_PFAPR_M1PFD. */
00428 #define BS_FMC_PFAPR_M1PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M1PFD. */
00429 
00430 /*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
00431 #define BR_FMC_PFAPR_M1PFD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD)))
00432 
00433 /*! @brief Format value for bitfield FMC_PFAPR_M1PFD. */
00434 #define BF_FMC_PFAPR_M1PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1PFD) & BM_FMC_PFAPR_M1PFD)
00435 
00436 /*! @brief Set the M1PFD field to a new value. */
00437 #define BW_FMC_PFAPR_M1PFD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD), v))
00438 /*@}*/
00439 
00440 /*!
00441  * @name Register FMC_PFAPR, field M2PFD[18] (RW)
00442  *
00443  * These bits control whether prefetching is enabled based on the logical number
00444  * of the requesting crossbar switch master. This field is further qualified by
00445  * the PFBnCR[BxDPE,BxIPE] bits.
00446  *
00447  * Values:
00448  * - 0 - Prefetching for this master is enabled.
00449  * - 1 - Prefetching for this master is disabled.
00450  */
00451 /*@{*/
00452 #define BP_FMC_PFAPR_M2PFD   (18U)         /*!< Bit position for FMC_PFAPR_M2PFD. */
00453 #define BM_FMC_PFAPR_M2PFD   (0x00040000U) /*!< Bit mask for FMC_PFAPR_M2PFD. */
00454 #define BS_FMC_PFAPR_M2PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M2PFD. */
00455 
00456 /*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
00457 #define BR_FMC_PFAPR_M2PFD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD)))
00458 
00459 /*! @brief Format value for bitfield FMC_PFAPR_M2PFD. */
00460 #define BF_FMC_PFAPR_M2PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2PFD) & BM_FMC_PFAPR_M2PFD)
00461 
00462 /*! @brief Set the M2PFD field to a new value. */
00463 #define BW_FMC_PFAPR_M2PFD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD), v))
00464 /*@}*/
00465 
00466 /*!
00467  * @name Register FMC_PFAPR, field M3PFD[19] (RW)
00468  *
00469  * These bits control whether prefetching is enabled based on the logical number
00470  * of the requesting crossbar switch master. This field is further qualified by
00471  * the PFBnCR[BxDPE,BxIPE] bits.
00472  *
00473  * Values:
00474  * - 0 - Prefetching for this master is enabled.
00475  * - 1 - Prefetching for this master is disabled.
00476  */
00477 /*@{*/
00478 #define BP_FMC_PFAPR_M3PFD   (19U)         /*!< Bit position for FMC_PFAPR_M3PFD. */
00479 #define BM_FMC_PFAPR_M3PFD   (0x00080000U) /*!< Bit mask for FMC_PFAPR_M3PFD. */
00480 #define BS_FMC_PFAPR_M3PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M3PFD. */
00481 
00482 /*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
00483 #define BR_FMC_PFAPR_M3PFD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD)))
00484 
00485 /*! @brief Format value for bitfield FMC_PFAPR_M3PFD. */
00486 #define BF_FMC_PFAPR_M3PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3PFD) & BM_FMC_PFAPR_M3PFD)
00487 
00488 /*! @brief Set the M3PFD field to a new value. */
00489 #define BW_FMC_PFAPR_M3PFD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD), v))
00490 /*@}*/
00491 
00492 /*!
00493  * @name Register FMC_PFAPR, field M4PFD[20] (RW)
00494  *
00495  * These bits control whether prefetching is enabled based on the logical number
00496  * of the requesting crossbar switch master. This field is further qualified by
00497  * the PFBnCR[BxDPE,BxIPE] bits.
00498  *
00499  * Values:
00500  * - 0 - Prefetching for this master is enabled.
00501  * - 1 - Prefetching for this master is disabled.
00502  */
00503 /*@{*/
00504 #define BP_FMC_PFAPR_M4PFD   (20U)         /*!< Bit position for FMC_PFAPR_M4PFD. */
00505 #define BM_FMC_PFAPR_M4PFD   (0x00100000U) /*!< Bit mask for FMC_PFAPR_M4PFD. */
00506 #define BS_FMC_PFAPR_M4PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M4PFD. */
00507 
00508 /*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
00509 #define BR_FMC_PFAPR_M4PFD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD)))
00510 
00511 /*! @brief Format value for bitfield FMC_PFAPR_M4PFD. */
00512 #define BF_FMC_PFAPR_M4PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4PFD) & BM_FMC_PFAPR_M4PFD)
00513 
00514 /*! @brief Set the M4PFD field to a new value. */
00515 #define BW_FMC_PFAPR_M4PFD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD), v))
00516 /*@}*/
00517 
00518 /*!
00519  * @name Register FMC_PFAPR, field M5PFD[21] (RW)
00520  *
00521  * These bits control whether prefetching is enabled based on the logical number
00522  * of the requesting crossbar switch master. This field is further qualified by
00523  * the PFBnCR[BxDPE,BxIPE] bits.
00524  *
00525  * Values:
00526  * - 0 - Prefetching for this master is enabled.
00527  * - 1 - Prefetching for this master is disabled.
00528  */
00529 /*@{*/
00530 #define BP_FMC_PFAPR_M5PFD   (21U)         /*!< Bit position for FMC_PFAPR_M5PFD. */
00531 #define BM_FMC_PFAPR_M5PFD   (0x00200000U) /*!< Bit mask for FMC_PFAPR_M5PFD. */
00532 #define BS_FMC_PFAPR_M5PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M5PFD. */
00533 
00534 /*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
00535 #define BR_FMC_PFAPR_M5PFD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD)))
00536 
00537 /*! @brief Format value for bitfield FMC_PFAPR_M5PFD. */
00538 #define BF_FMC_PFAPR_M5PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5PFD) & BM_FMC_PFAPR_M5PFD)
00539 
00540 /*! @brief Set the M5PFD field to a new value. */
00541 #define BW_FMC_PFAPR_M5PFD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD), v))
00542 /*@}*/
00543 
00544 /*!
00545  * @name Register FMC_PFAPR, field M6PFD[22] (RW)
00546  *
00547  * These bits control whether prefetching is enabled based on the logical number
00548  * of the requesting crossbar switch master. This field is further qualified by
00549  * the PFBnCR[BxDPE,BxIPE] bits.
00550  *
00551  * Values:
00552  * - 0 - Prefetching for this master is enabled.
00553  * - 1 - Prefetching for this master is disabled.
00554  */
00555 /*@{*/
00556 #define BP_FMC_PFAPR_M6PFD   (22U)         /*!< Bit position for FMC_PFAPR_M6PFD. */
00557 #define BM_FMC_PFAPR_M6PFD   (0x00400000U) /*!< Bit mask for FMC_PFAPR_M6PFD. */
00558 #define BS_FMC_PFAPR_M6PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M6PFD. */
00559 
00560 /*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
00561 #define BR_FMC_PFAPR_M6PFD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD)))
00562 
00563 /*! @brief Format value for bitfield FMC_PFAPR_M6PFD. */
00564 #define BF_FMC_PFAPR_M6PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6PFD) & BM_FMC_PFAPR_M6PFD)
00565 
00566 /*! @brief Set the M6PFD field to a new value. */
00567 #define BW_FMC_PFAPR_M6PFD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD), v))
00568 /*@}*/
00569 
00570 /*!
00571  * @name Register FMC_PFAPR, field M7PFD[23] (RW)
00572  *
00573  * These bits control whether prefetching is enabled based on the logical number
00574  * of the requesting crossbar switch master. This field is further qualified by
00575  * the PFBnCR[BxDPE,BxIPE] bits.
00576  *
00577  * Values:
00578  * - 0 - Prefetching for this master is enabled.
00579  * - 1 - Prefetching for this master is disabled.
00580  */
00581 /*@{*/
00582 #define BP_FMC_PFAPR_M7PFD   (23U)         /*!< Bit position for FMC_PFAPR_M7PFD. */
00583 #define BM_FMC_PFAPR_M7PFD   (0x00800000U) /*!< Bit mask for FMC_PFAPR_M7PFD. */
00584 #define BS_FMC_PFAPR_M7PFD   (1U)          /*!< Bit field size in bits for FMC_PFAPR_M7PFD. */
00585 
00586 /*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
00587 #define BR_FMC_PFAPR_M7PFD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD)))
00588 
00589 /*! @brief Format value for bitfield FMC_PFAPR_M7PFD. */
00590 #define BF_FMC_PFAPR_M7PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7PFD) & BM_FMC_PFAPR_M7PFD)
00591 
00592 /*! @brief Set the M7PFD field to a new value. */
00593 #define BW_FMC_PFAPR_M7PFD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD), v))
00594 /*@}*/
00595 
00596 /*******************************************************************************
00597  * HW_FMC_PFB0CR - Flash Bank 0 Control Register
00598  ******************************************************************************/
00599 
00600 /*!
00601  * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW)
00602  *
00603  * Reset value: 0x3004001FU
00604  */
00605 typedef union _hw_fmc_pfb0cr
00606 {
00607     uint32_t U;
00608     struct _hw_fmc_pfb0cr_bitfields
00609     {
00610         uint32_t B0SEBE : 1;           /*!< [0] Bank 0 Single Entry Buffer Enable */
00611         uint32_t B0IPE : 1;            /*!< [1] Bank 0 Instruction Prefetch Enable */
00612         uint32_t B0DPE : 1;            /*!< [2] Bank 0 Data Prefetch Enable */
00613         uint32_t B0ICE : 1;            /*!< [3] Bank 0 Instruction Cache Enable */
00614         uint32_t B0DCE : 1;            /*!< [4] Bank 0 Data Cache Enable */
00615         uint32_t CRC : 3;              /*!< [7:5] Cache Replacement Control */
00616         uint32_t RESERVED0 : 9;        /*!< [16:8]  */
00617         uint32_t B0MW : 2;             /*!< [18:17] Bank 0 Memory Width */
00618         uint32_t S_B_INV : 1;          /*!< [19] Invalidate Prefetch Speculation
00619                                         * Buffer */
00620         uint32_t CINV_WAY : 4;         /*!< [23:20] Cache Invalidate Way x */
00621         uint32_t CLCK_WAY : 4;         /*!< [27:24] Cache Lock Way x */
00622         uint32_t B0RWSC : 4;           /*!< [31:28] Bank 0 Read Wait State Control */
00623     } B;
00624 } hw_fmc_pfb0cr_t;
00625 
00626 /*!
00627  * @name Constants and macros for entire FMC_PFB0CR register
00628  */
00629 /*@{*/
00630 #define HW_FMC_PFB0CR_ADDR(x)    ((x) + 0x4U)
00631 
00632 #define HW_FMC_PFB0CR(x)         (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR(x))
00633 #define HW_FMC_PFB0CR_RD(x)      (ADDRESS_READ(hw_fmc_pfb0cr_t, HW_FMC_PFB0CR_ADDR(x)))
00634 #define HW_FMC_PFB0CR_WR(x, v)   (ADDRESS_WRITE(hw_fmc_pfb0cr_t, HW_FMC_PFB0CR_ADDR(x), v))
00635 #define HW_FMC_PFB0CR_SET(x, v)  (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) |  (v)))
00636 #define HW_FMC_PFB0CR_CLR(x, v)  (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) & ~(v)))
00637 #define HW_FMC_PFB0CR_TOG(x, v)  (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) ^  (v)))
00638 /*@}*/
00639 
00640 /*
00641  * Constants & macros for individual FMC_PFB0CR bitfields
00642  */
00643 
00644 /*!
00645  * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
00646  *
00647  * This bit controls whether the single entry page buffer is enabled in response
00648  * to flash read accesses. Its operation is independent from bank 1's cache. A
00649  * high-to-low transition of this enable forces the page buffer to be invalidated.
00650  *
00651  * Values:
00652  * - 0 - Single entry buffer is disabled.
00653  * - 1 - Single entry buffer is enabled.
00654  */
00655 /*@{*/
00656 #define BP_FMC_PFB0CR_B0SEBE (0U)          /*!< Bit position for FMC_PFB0CR_B0SEBE. */
00657 #define BM_FMC_PFB0CR_B0SEBE (0x00000001U) /*!< Bit mask for FMC_PFB0CR_B0SEBE. */
00658 #define BS_FMC_PFB0CR_B0SEBE (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0SEBE. */
00659 
00660 /*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
00661 #define BR_FMC_PFB0CR_B0SEBE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE)))
00662 
00663 /*! @brief Format value for bitfield FMC_PFB0CR_B0SEBE. */
00664 #define BF_FMC_PFB0CR_B0SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0SEBE) & BM_FMC_PFB0CR_B0SEBE)
00665 
00666 /*! @brief Set the B0SEBE field to a new value. */
00667 #define BW_FMC_PFB0CR_B0SEBE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE), v))
00668 /*@}*/
00669 
00670 /*!
00671  * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
00672  *
00673  * This bit controls whether prefetches (or speculative accesses) are initiated
00674  * in response to instruction fetches.
00675  *
00676  * Values:
00677  * - 0 - Do not prefetch in response to instruction fetches.
00678  * - 1 - Enable prefetches in response to instruction fetches.
00679  */
00680 /*@{*/
00681 #define BP_FMC_PFB0CR_B0IPE  (1U)          /*!< Bit position for FMC_PFB0CR_B0IPE. */
00682 #define BM_FMC_PFB0CR_B0IPE  (0x00000002U) /*!< Bit mask for FMC_PFB0CR_B0IPE. */
00683 #define BS_FMC_PFB0CR_B0IPE  (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0IPE. */
00684 
00685 /*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
00686 #define BR_FMC_PFB0CR_B0IPE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE)))
00687 
00688 /*! @brief Format value for bitfield FMC_PFB0CR_B0IPE. */
00689 #define BF_FMC_PFB0CR_B0IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0IPE) & BM_FMC_PFB0CR_B0IPE)
00690 
00691 /*! @brief Set the B0IPE field to a new value. */
00692 #define BW_FMC_PFB0CR_B0IPE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE), v))
00693 /*@}*/
00694 
00695 /*!
00696  * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
00697  *
00698  * This bit controls whether prefetches (or speculative accesses) are initiated
00699  * in response to data references.
00700  *
00701  * Values:
00702  * - 0 - Do not prefetch in response to data references.
00703  * - 1 - Enable prefetches in response to data references.
00704  */
00705 /*@{*/
00706 #define BP_FMC_PFB0CR_B0DPE  (2U)          /*!< Bit position for FMC_PFB0CR_B0DPE. */
00707 #define BM_FMC_PFB0CR_B0DPE  (0x00000004U) /*!< Bit mask for FMC_PFB0CR_B0DPE. */
00708 #define BS_FMC_PFB0CR_B0DPE  (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0DPE. */
00709 
00710 /*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
00711 #define BR_FMC_PFB0CR_B0DPE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE)))
00712 
00713 /*! @brief Format value for bitfield FMC_PFB0CR_B0DPE. */
00714 #define BF_FMC_PFB0CR_B0DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DPE) & BM_FMC_PFB0CR_B0DPE)
00715 
00716 /*! @brief Set the B0DPE field to a new value. */
00717 #define BW_FMC_PFB0CR_B0DPE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE), v))
00718 /*@}*/
00719 
00720 /*!
00721  * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
00722  *
00723  * This bit controls whether instruction fetches are loaded into the cache.
00724  *
00725  * Values:
00726  * - 0 - Do not cache instruction fetches.
00727  * - 1 - Cache instruction fetches.
00728  */
00729 /*@{*/
00730 #define BP_FMC_PFB0CR_B0ICE  (3U)          /*!< Bit position for FMC_PFB0CR_B0ICE. */
00731 #define BM_FMC_PFB0CR_B0ICE  (0x00000008U) /*!< Bit mask for FMC_PFB0CR_B0ICE. */
00732 #define BS_FMC_PFB0CR_B0ICE  (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0ICE. */
00733 
00734 /*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
00735 #define BR_FMC_PFB0CR_B0ICE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE)))
00736 
00737 /*! @brief Format value for bitfield FMC_PFB0CR_B0ICE. */
00738 #define BF_FMC_PFB0CR_B0ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0ICE) & BM_FMC_PFB0CR_B0ICE)
00739 
00740 /*! @brief Set the B0ICE field to a new value. */
00741 #define BW_FMC_PFB0CR_B0ICE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE), v))
00742 /*@}*/
00743 
00744 /*!
00745  * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
00746  *
00747  * This bit controls whether data references are loaded into the cache.
00748  *
00749  * Values:
00750  * - 0 - Do not cache data references.
00751  * - 1 - Cache data references.
00752  */
00753 /*@{*/
00754 #define BP_FMC_PFB0CR_B0DCE  (4U)          /*!< Bit position for FMC_PFB0CR_B0DCE. */
00755 #define BM_FMC_PFB0CR_B0DCE  (0x00000010U) /*!< Bit mask for FMC_PFB0CR_B0DCE. */
00756 #define BS_FMC_PFB0CR_B0DCE  (1U)          /*!< Bit field size in bits for FMC_PFB0CR_B0DCE. */
00757 
00758 /*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
00759 #define BR_FMC_PFB0CR_B0DCE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE)))
00760 
00761 /*! @brief Format value for bitfield FMC_PFB0CR_B0DCE. */
00762 #define BF_FMC_PFB0CR_B0DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DCE) & BM_FMC_PFB0CR_B0DCE)
00763 
00764 /*! @brief Set the B0DCE field to a new value. */
00765 #define BW_FMC_PFB0CR_B0DCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE), v))
00766 /*@}*/
00767 
00768 /*!
00769  * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
00770  *
00771  * This 3-bit field defines the replacement algorithm for accesses that are
00772  * cached.
00773  *
00774  * Values:
00775  * - 000 - LRU replacement algorithm per set across all four ways
00776  * - 001 - Reserved
00777  * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
00778  * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
00779  * - 1xx - Reserved
00780  */
00781 /*@{*/
00782 #define BP_FMC_PFB0CR_CRC    (5U)          /*!< Bit position for FMC_PFB0CR_CRC. */
00783 #define BM_FMC_PFB0CR_CRC    (0x000000E0U) /*!< Bit mask for FMC_PFB0CR_CRC. */
00784 #define BS_FMC_PFB0CR_CRC    (3U)          /*!< Bit field size in bits for FMC_PFB0CR_CRC. */
00785 
00786 /*! @brief Read current value of the FMC_PFB0CR_CRC field. */
00787 #define BR_FMC_PFB0CR_CRC(x) (UNION_READ(hw_fmc_pfb0cr_t, HW_FMC_PFB0CR_ADDR(x), U, B.CRC))
00788 
00789 /*! @brief Format value for bitfield FMC_PFB0CR_CRC. */
00790 #define BF_FMC_PFB0CR_CRC(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CRC) & BM_FMC_PFB0CR_CRC)
00791 
00792 /*! @brief Set the CRC field to a new value. */
00793 #define BW_FMC_PFB0CR_CRC(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v)))
00794 /*@}*/
00795 
00796 /*!
00797  * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
00798  *
00799  * This read-only field defines the width of the bank 0 memory.
00800  *
00801  * Values:
00802  * - 00 - 32 bits
00803  * - 01 - 64 bits
00804  * - 10 - 128 bits
00805  * - 11 - Reserved
00806  */
00807 /*@{*/
00808 #define BP_FMC_PFB0CR_B0MW   (17U)         /*!< Bit position for FMC_PFB0CR_B0MW. */
00809 #define BM_FMC_PFB0CR_B0MW   (0x00060000U) /*!< Bit mask for FMC_PFB0CR_B0MW. */
00810 #define BS_FMC_PFB0CR_B0MW   (2U)          /*!< Bit field size in bits for FMC_PFB0CR_B0MW. */
00811 
00812 /*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
00813 #define BR_FMC_PFB0CR_B0MW(x) (UNION_READ(hw_fmc_pfb0cr_t, HW_FMC_PFB0CR_ADDR(x), U, B.B0MW))
00814 /*@}*/
00815 
00816 /*!
00817  * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
00818  *
00819  * This bit determines if the FMC's prefetch speculation buffer and the single
00820  * entry page buffer are to be invalidated (cleared). When this bit is written,
00821  * the speculation buffer and single entry buffer are immediately cleared. This bit
00822  * always reads as zero.
00823  *
00824  * Values:
00825  * - 0 - Speculation buffer and single entry buffer are not affected.
00826  * - 1 - Invalidate (clear) speculation buffer and single entry buffer.
00827  */
00828 /*@{*/
00829 #define BP_FMC_PFB0CR_S_B_INV (19U)        /*!< Bit position for FMC_PFB0CR_S_B_INV. */
00830 #define BM_FMC_PFB0CR_S_B_INV (0x00080000U) /*!< Bit mask for FMC_PFB0CR_S_B_INV. */
00831 #define BS_FMC_PFB0CR_S_B_INV (1U)         /*!< Bit field size in bits for FMC_PFB0CR_S_B_INV. */
00832 
00833 /*! @brief Format value for bitfield FMC_PFB0CR_S_B_INV. */
00834 #define BF_FMC_PFB0CR_S_B_INV(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_S_B_INV) & BM_FMC_PFB0CR_S_B_INV)
00835 
00836 /*! @brief Set the S_B_INV field to a new value. */
00837 #define BW_FMC_PFB0CR_S_B_INV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_S_B_INV), v))
00838 /*@}*/
00839 
00840 /*!
00841  * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
00842  *
00843  * These bits determine if the given cache way is to be invalidated (cleared).
00844  * When a bit within this field is written, the corresponding cache way is
00845  * immediately invalidated: the way's tag, data, and valid contents are cleared. This
00846  * field always reads as zero. Cache invalidation takes precedence over locking.
00847  * The cache is invalidated by system reset. System software is required to
00848  * maintain memory coherency when any segment of the flash memory is programmed or
00849  * erased. Accordingly, cache invalidations must occur after a programming or erase
00850  * event is completed and before the new memory image is accessed. The bit setting
00851  * definitions are for each bit in the field.
00852  *
00853  * Values:
00854  * - 0 - No cache way invalidation for the corresponding cache
00855  * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
00856  *     and vld bits of ways selected
00857  */
00858 /*@{*/
00859 #define BP_FMC_PFB0CR_CINV_WAY (20U)       /*!< Bit position for FMC_PFB0CR_CINV_WAY. */
00860 #define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) /*!< Bit mask for FMC_PFB0CR_CINV_WAY. */
00861 #define BS_FMC_PFB0CR_CINV_WAY (4U)        /*!< Bit field size in bits for FMC_PFB0CR_CINV_WAY. */
00862 
00863 /*! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY. */
00864 #define BF_FMC_PFB0CR_CINV_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CINV_WAY) & BM_FMC_PFB0CR_CINV_WAY)
00865 
00866 /*! @brief Set the CINV_WAY field to a new value. */
00867 #define BW_FMC_PFB0CR_CINV_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v)))
00868 /*@}*/
00869 
00870 /*!
00871  * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
00872  *
00873  * These bits determine if the given cache way is locked such that its contents
00874  * will not be displaced by future misses. The bit setting definitions are for
00875  * each bit in the field.
00876  *
00877  * Values:
00878  * - 0 - Cache way is unlocked and may be displaced
00879  * - 1 - Cache way is locked and its contents are not displaced
00880  */
00881 /*@{*/
00882 #define BP_FMC_PFB0CR_CLCK_WAY (24U)       /*!< Bit position for FMC_PFB0CR_CLCK_WAY. */
00883 #define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) /*!< Bit mask for FMC_PFB0CR_CLCK_WAY. */
00884 #define BS_FMC_PFB0CR_CLCK_WAY (4U)        /*!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY. */
00885 
00886 /*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
00887 #define BR_FMC_PFB0CR_CLCK_WAY(x) (UNION_READ(hw_fmc_pfb0cr_t, HW_FMC_PFB0CR_ADDR(x), U, B.CLCK_WAY))
00888 
00889 /*! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY. */
00890 #define BF_FMC_PFB0CR_CLCK_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CLCK_WAY) & BM_FMC_PFB0CR_CLCK_WAY)
00891 
00892 /*! @brief Set the CLCK_WAY field to a new value. */
00893 #define BW_FMC_PFB0CR_CLCK_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v)))
00894 /*@}*/
00895 
00896 /*!
00897  * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
00898  *
00899  * This read-only field defines the number of wait states required to access the
00900  * bank 0 flash memory. The relationship between the read access time of the
00901  * flash array (expressed in system clock cycles) and RWSC is defined as: Access
00902  * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
00903  * this value based on the ratio of the system clock speed to the flash clock
00904  * speed. For example, when this ratio is 4:1, the field's value is 3h.
00905  */
00906 /*@{*/
00907 #define BP_FMC_PFB0CR_B0RWSC (28U)         /*!< Bit position for FMC_PFB0CR_B0RWSC. */
00908 #define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB0CR_B0RWSC. */
00909 #define BS_FMC_PFB0CR_B0RWSC (4U)          /*!< Bit field size in bits for FMC_PFB0CR_B0RWSC. */
00910 
00911 /*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
00912 #define BR_FMC_PFB0CR_B0RWSC(x) (UNION_READ(hw_fmc_pfb0cr_t, HW_FMC_PFB0CR_ADDR(x), U, B.B0RWSC))
00913 /*@}*/
00914 
00915 /*******************************************************************************
00916  * HW_FMC_PFB1CR - Flash Bank 1 Control Register
00917  ******************************************************************************/
00918 
00919 /*!
00920  * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW)
00921  *
00922  * Reset value: 0x3004001FU
00923  *
00924  * This register has a format similar to that for PFB0CR, except it controls the
00925  * operation of flash bank 1, and the "global" cache control fields are empty.
00926  */
00927 typedef union _hw_fmc_pfb1cr
00928 {
00929     uint32_t U;
00930     struct _hw_fmc_pfb1cr_bitfields
00931     {
00932         uint32_t B1SEBE : 1;           /*!< [0] Bank 1 Single Entry Buffer Enable */
00933         uint32_t B1IPE : 1;            /*!< [1] Bank 1 Instruction Prefetch Enable */
00934         uint32_t B1DPE : 1;            /*!< [2] Bank 1 Data Prefetch Enable */
00935         uint32_t B1ICE : 1;            /*!< [3] Bank 1 Instruction Cache Enable */
00936         uint32_t B1DCE : 1;            /*!< [4] Bank 1 Data Cache Enable */
00937         uint32_t RESERVED0 : 12;       /*!< [16:5]  */
00938         uint32_t B1MW : 2;             /*!< [18:17] Bank 1 Memory Width */
00939         uint32_t RESERVED1 : 9;        /*!< [27:19]  */
00940         uint32_t B1RWSC : 4;           /*!< [31:28] Bank 1 Read Wait State Control */
00941     } B;
00942 } hw_fmc_pfb1cr_t;
00943 
00944 /*!
00945  * @name Constants and macros for entire FMC_PFB1CR register
00946  */
00947 /*@{*/
00948 #define HW_FMC_PFB1CR_ADDR(x)    ((x) + 0x8U)
00949 
00950 #define HW_FMC_PFB1CR(x)         (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR(x))
00951 #define HW_FMC_PFB1CR_RD(x)      (ADDRESS_READ(hw_fmc_pfb1cr_t, HW_FMC_PFB1CR_ADDR(x)))
00952 #define HW_FMC_PFB1CR_WR(x, v)   (ADDRESS_WRITE(hw_fmc_pfb1cr_t, HW_FMC_PFB1CR_ADDR(x), v))
00953 #define HW_FMC_PFB1CR_SET(x, v)  (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) |  (v)))
00954 #define HW_FMC_PFB1CR_CLR(x, v)  (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) & ~(v)))
00955 #define HW_FMC_PFB1CR_TOG(x, v)  (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) ^  (v)))
00956 /*@}*/
00957 
00958 /*
00959  * Constants & macros for individual FMC_PFB1CR bitfields
00960  */
00961 
00962 /*!
00963  * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
00964  *
00965  * This bit controls whether the single entry buffer is enabled in response to
00966  * flash read accesses. Its operation is independent from bank 0's cache. A
00967  * high-to-low transition of this enable forces the page buffer to be invalidated.
00968  *
00969  * Values:
00970  * - 0 - Single entry buffer is disabled.
00971  * - 1 - Single entry buffer is enabled.
00972  */
00973 /*@{*/
00974 #define BP_FMC_PFB1CR_B1SEBE (0U)          /*!< Bit position for FMC_PFB1CR_B1SEBE. */
00975 #define BM_FMC_PFB1CR_B1SEBE (0x00000001U) /*!< Bit mask for FMC_PFB1CR_B1SEBE. */
00976 #define BS_FMC_PFB1CR_B1SEBE (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1SEBE. */
00977 
00978 /*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
00979 #define BR_FMC_PFB1CR_B1SEBE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE)))
00980 
00981 /*! @brief Format value for bitfield FMC_PFB1CR_B1SEBE. */
00982 #define BF_FMC_PFB1CR_B1SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1SEBE) & BM_FMC_PFB1CR_B1SEBE)
00983 
00984 /*! @brief Set the B1SEBE field to a new value. */
00985 #define BW_FMC_PFB1CR_B1SEBE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE), v))
00986 /*@}*/
00987 
00988 /*!
00989  * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
00990  *
00991  * This bit controls whether prefetches (or speculative accesses) are initiated
00992  * in response to instruction fetches.
00993  *
00994  * Values:
00995  * - 0 - Do not prefetch in response to instruction fetches.
00996  * - 1 - Enable prefetches in response to instruction fetches.
00997  */
00998 /*@{*/
00999 #define BP_FMC_PFB1CR_B1IPE  (1U)          /*!< Bit position for FMC_PFB1CR_B1IPE. */
01000 #define BM_FMC_PFB1CR_B1IPE  (0x00000002U) /*!< Bit mask for FMC_PFB1CR_B1IPE. */
01001 #define BS_FMC_PFB1CR_B1IPE  (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1IPE. */
01002 
01003 /*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
01004 #define BR_FMC_PFB1CR_B1IPE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE)))
01005 
01006 /*! @brief Format value for bitfield FMC_PFB1CR_B1IPE. */
01007 #define BF_FMC_PFB1CR_B1IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1IPE) & BM_FMC_PFB1CR_B1IPE)
01008 
01009 /*! @brief Set the B1IPE field to a new value. */
01010 #define BW_FMC_PFB1CR_B1IPE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE), v))
01011 /*@}*/
01012 
01013 /*!
01014  * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
01015  *
01016  * This bit controls whether prefetches (or speculative accesses) are initiated
01017  * in response to data references.
01018  *
01019  * Values:
01020  * - 0 - Do not prefetch in response to data references.
01021  * - 1 - Enable prefetches in response to data references.
01022  */
01023 /*@{*/
01024 #define BP_FMC_PFB1CR_B1DPE  (2U)          /*!< Bit position for FMC_PFB1CR_B1DPE. */
01025 #define BM_FMC_PFB1CR_B1DPE  (0x00000004U) /*!< Bit mask for FMC_PFB1CR_B1DPE. */
01026 #define BS_FMC_PFB1CR_B1DPE  (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1DPE. */
01027 
01028 /*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
01029 #define BR_FMC_PFB1CR_B1DPE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE)))
01030 
01031 /*! @brief Format value for bitfield FMC_PFB1CR_B1DPE. */
01032 #define BF_FMC_PFB1CR_B1DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DPE) & BM_FMC_PFB1CR_B1DPE)
01033 
01034 /*! @brief Set the B1DPE field to a new value. */
01035 #define BW_FMC_PFB1CR_B1DPE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE), v))
01036 /*@}*/
01037 
01038 /*!
01039  * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
01040  *
01041  * This bit controls whether instruction fetches are loaded into the cache.
01042  *
01043  * Values:
01044  * - 0 - Do not cache instruction fetches.
01045  * - 1 - Cache instruction fetches.
01046  */
01047 /*@{*/
01048 #define BP_FMC_PFB1CR_B1ICE  (3U)          /*!< Bit position for FMC_PFB1CR_B1ICE. */
01049 #define BM_FMC_PFB1CR_B1ICE  (0x00000008U) /*!< Bit mask for FMC_PFB1CR_B1ICE. */
01050 #define BS_FMC_PFB1CR_B1ICE  (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1ICE. */
01051 
01052 /*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
01053 #define BR_FMC_PFB1CR_B1ICE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE)))
01054 
01055 /*! @brief Format value for bitfield FMC_PFB1CR_B1ICE. */
01056 #define BF_FMC_PFB1CR_B1ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1ICE) & BM_FMC_PFB1CR_B1ICE)
01057 
01058 /*! @brief Set the B1ICE field to a new value. */
01059 #define BW_FMC_PFB1CR_B1ICE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE), v))
01060 /*@}*/
01061 
01062 /*!
01063  * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
01064  *
01065  * This bit controls whether data references are loaded into the cache.
01066  *
01067  * Values:
01068  * - 0 - Do not cache data references.
01069  * - 1 - Cache data references.
01070  */
01071 /*@{*/
01072 #define BP_FMC_PFB1CR_B1DCE  (4U)          /*!< Bit position for FMC_PFB1CR_B1DCE. */
01073 #define BM_FMC_PFB1CR_B1DCE  (0x00000010U) /*!< Bit mask for FMC_PFB1CR_B1DCE. */
01074 #define BS_FMC_PFB1CR_B1DCE  (1U)          /*!< Bit field size in bits for FMC_PFB1CR_B1DCE. */
01075 
01076 /*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
01077 #define BR_FMC_PFB1CR_B1DCE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE)))
01078 
01079 /*! @brief Format value for bitfield FMC_PFB1CR_B1DCE. */
01080 #define BF_FMC_PFB1CR_B1DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DCE) & BM_FMC_PFB1CR_B1DCE)
01081 
01082 /*! @brief Set the B1DCE field to a new value. */
01083 #define BW_FMC_PFB1CR_B1DCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE), v))
01084 /*@}*/
01085 
01086 /*!
01087  * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
01088  *
01089  * This read-only field defines the width of the bank 1 memory.
01090  *
01091  * Values:
01092  * - 00 - 32 bits
01093  * - 01 - 64 bits
01094  * - 10 - 128 bits
01095  * - 11 - Reserved
01096  */
01097 /*@{*/
01098 #define BP_FMC_PFB1CR_B1MW   (17U)         /*!< Bit position for FMC_PFB1CR_B1MW. */
01099 #define BM_FMC_PFB1CR_B1MW   (0x00060000U) /*!< Bit mask for FMC_PFB1CR_B1MW. */
01100 #define BS_FMC_PFB1CR_B1MW   (2U)          /*!< Bit field size in bits for FMC_PFB1CR_B1MW. */
01101 
01102 /*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
01103 #define BR_FMC_PFB1CR_B1MW(x) (UNION_READ(hw_fmc_pfb1cr_t, HW_FMC_PFB1CR_ADDR(x), U, B.B1MW))
01104 /*@}*/
01105 
01106 /*!
01107  * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
01108  *
01109  * This read-only field defines the number of wait states required to access the
01110  * bank 1 flash memory. The relationship between the read access time of the
01111  * flash array (expressed in system clock cycles) and RWSC is defined as: Access
01112  * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
01113  * this value based on the ratio of the system clock speed to the flash clock
01114  * speed. For example, when this ratio is 4:1, the field's value is 3h.
01115  */
01116 /*@{*/
01117 #define BP_FMC_PFB1CR_B1RWSC (28U)         /*!< Bit position for FMC_PFB1CR_B1RWSC. */
01118 #define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB1CR_B1RWSC. */
01119 #define BS_FMC_PFB1CR_B1RWSC (4U)          /*!< Bit field size in bits for FMC_PFB1CR_B1RWSC. */
01120 
01121 /*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
01122 #define BR_FMC_PFB1CR_B1RWSC(x) (UNION_READ(hw_fmc_pfb1cr_t, HW_FMC_PFB1CR_ADDR(x), U, B.B1RWSC))
01123 /*@}*/
01124 
01125 /*******************************************************************************
01126  * HW_FMC_TAGVDW0Sn - Cache Tag Storage
01127  ******************************************************************************/
01128 
01129 /*!
01130  * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
01131  *
01132  * Reset value: 0x00000000U
01133  *
01134  * The cache is a 4-way, set-associative cache with 4 sets. The ways are
01135  * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
01136  * denotes the set. This section represents tag/vld information for all sets in the
01137  * indicated way.
01138  */
01139 typedef union _hw_fmc_tagvdw0sn
01140 {
01141     uint32_t U;
01142     struct _hw_fmc_tagvdw0sn_bitfields
01143     {
01144         uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
01145         uint32_t RESERVED0 : 4;        /*!< [4:1]  */
01146         uint32_t tag : 14;             /*!< [18:5] 14-bit tag for cache entry */
01147         uint32_t RESERVED1 : 13;       /*!< [31:19]  */
01148     } B;
01149 } hw_fmc_tagvdw0sn_t;
01150 
01151 /*!
01152  * @name Constants and macros for entire FMC_TAGVDW0Sn register
01153  */
01154 /*@{*/
01155 #define HW_FMC_TAGVDW0Sn_COUNT (4U)
01156 
01157 #define HW_FMC_TAGVDW0Sn_ADDR(x, n) ((x) + 0x100U + (0x4U * (n)))
01158 
01159 #define HW_FMC_TAGVDW0Sn(x, n)   (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(x, n))
01160 #define HW_FMC_TAGVDW0Sn_RD(x, n) (ADDRESS_READ(hw_fmc_tagvdw0sn_t, HW_FMC_TAGVDW0Sn_ADDR(x, n)))
01161 #define HW_FMC_TAGVDW0Sn_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_tagvdw0sn_t, HW_FMC_TAGVDW0Sn_ADDR(x, n), v))
01162 #define HW_FMC_TAGVDW0Sn_SET(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) |  (v)))
01163 #define HW_FMC_TAGVDW0Sn_CLR(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) & ~(v)))
01164 #define HW_FMC_TAGVDW0Sn_TOG(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) ^  (v)))
01165 /*@}*/
01166 
01167 /*
01168  * Constants & macros for individual FMC_TAGVDW0Sn bitfields
01169  */
01170 
01171 /*!
01172  * @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
01173  */
01174 /*@{*/
01175 #define BP_FMC_TAGVDW0Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW0Sn_valid. */
01176 #define BM_FMC_TAGVDW0Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW0Sn_valid. */
01177 #define BS_FMC_TAGVDW0Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW0Sn_valid. */
01178 
01179 /*! @brief Read current value of the FMC_TAGVDW0Sn_valid field. */
01180 #define BR_FMC_TAGVDW0Sn_valid(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid)))
01181 
01182 /*! @brief Format value for bitfield FMC_TAGVDW0Sn_valid. */
01183 #define BF_FMC_TAGVDW0Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_valid) & BM_FMC_TAGVDW0Sn_valid)
01184 
01185 /*! @brief Set the valid field to a new value. */
01186 #define BW_FMC_TAGVDW0Sn_valid(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid), v))
01187 /*@}*/
01188 
01189 /*!
01190  * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW)
01191  */
01192 /*@{*/
01193 #define BP_FMC_TAGVDW0Sn_tag (5U)          /*!< Bit position for FMC_TAGVDW0Sn_tag. */
01194 #define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW0Sn_tag. */
01195 #define BS_FMC_TAGVDW0Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW0Sn_tag. */
01196 
01197 /*! @brief Read current value of the FMC_TAGVDW0Sn_tag field. */
01198 #define BR_FMC_TAGVDW0Sn_tag(x, n) (UNION_READ(hw_fmc_tagvdw0sn_t, HW_FMC_TAGVDW0Sn_ADDR(x, n), U, B.tag))
01199 
01200 /*! @brief Format value for bitfield FMC_TAGVDW0Sn_tag. */
01201 #define BF_FMC_TAGVDW0Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_tag) & BM_FMC_TAGVDW0Sn_tag)
01202 
01203 /*! @brief Set the tag field to a new value. */
01204 #define BW_FMC_TAGVDW0Sn_tag(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, (HW_FMC_TAGVDW0Sn_RD(x, n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v)))
01205 /*@}*/
01206 
01207 /*******************************************************************************
01208  * HW_FMC_TAGVDW1Sn - Cache Tag Storage
01209  ******************************************************************************/
01210 
01211 /*!
01212  * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
01213  *
01214  * Reset value: 0x00000000U
01215  *
01216  * The cache is a 4-way, set-associative cache with 4 sets. The ways are
01217  * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
01218  * denotes the set. This section represents tag/vld information for all sets in the
01219  * indicated way.
01220  */
01221 typedef union _hw_fmc_tagvdw1sn
01222 {
01223     uint32_t U;
01224     struct _hw_fmc_tagvdw1sn_bitfields
01225     {
01226         uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
01227         uint32_t RESERVED0 : 4;        /*!< [4:1]  */
01228         uint32_t tag : 14;             /*!< [18:5] 14-bit tag for cache entry */
01229         uint32_t RESERVED1 : 13;       /*!< [31:19]  */
01230     } B;
01231 } hw_fmc_tagvdw1sn_t;
01232 
01233 /*!
01234  * @name Constants and macros for entire FMC_TAGVDW1Sn register
01235  */
01236 /*@{*/
01237 #define HW_FMC_TAGVDW1Sn_COUNT (4U)
01238 
01239 #define HW_FMC_TAGVDW1Sn_ADDR(x, n) ((x) + 0x110U + (0x4U * (n)))
01240 
01241 #define HW_FMC_TAGVDW1Sn(x, n)   (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(x, n))
01242 #define HW_FMC_TAGVDW1Sn_RD(x, n) (ADDRESS_READ(hw_fmc_tagvdw1sn_t, HW_FMC_TAGVDW1Sn_ADDR(x, n)))
01243 #define HW_FMC_TAGVDW1Sn_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_tagvdw1sn_t, HW_FMC_TAGVDW1Sn_ADDR(x, n), v))
01244 #define HW_FMC_TAGVDW1Sn_SET(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) |  (v)))
01245 #define HW_FMC_TAGVDW1Sn_CLR(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) & ~(v)))
01246 #define HW_FMC_TAGVDW1Sn_TOG(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) ^  (v)))
01247 /*@}*/
01248 
01249 /*
01250  * Constants & macros for individual FMC_TAGVDW1Sn bitfields
01251  */
01252 
01253 /*!
01254  * @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
01255  */
01256 /*@{*/
01257 #define BP_FMC_TAGVDW1Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW1Sn_valid. */
01258 #define BM_FMC_TAGVDW1Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW1Sn_valid. */
01259 #define BS_FMC_TAGVDW1Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW1Sn_valid. */
01260 
01261 /*! @brief Read current value of the FMC_TAGVDW1Sn_valid field. */
01262 #define BR_FMC_TAGVDW1Sn_valid(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid)))
01263 
01264 /*! @brief Format value for bitfield FMC_TAGVDW1Sn_valid. */
01265 #define BF_FMC_TAGVDW1Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_valid) & BM_FMC_TAGVDW1Sn_valid)
01266 
01267 /*! @brief Set the valid field to a new value. */
01268 #define BW_FMC_TAGVDW1Sn_valid(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid), v))
01269 /*@}*/
01270 
01271 /*!
01272  * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW)
01273  */
01274 /*@{*/
01275 #define BP_FMC_TAGVDW1Sn_tag (5U)          /*!< Bit position for FMC_TAGVDW1Sn_tag. */
01276 #define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW1Sn_tag. */
01277 #define BS_FMC_TAGVDW1Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW1Sn_tag. */
01278 
01279 /*! @brief Read current value of the FMC_TAGVDW1Sn_tag field. */
01280 #define BR_FMC_TAGVDW1Sn_tag(x, n) (UNION_READ(hw_fmc_tagvdw1sn_t, HW_FMC_TAGVDW1Sn_ADDR(x, n), U, B.tag))
01281 
01282 /*! @brief Format value for bitfield FMC_TAGVDW1Sn_tag. */
01283 #define BF_FMC_TAGVDW1Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_tag) & BM_FMC_TAGVDW1Sn_tag)
01284 
01285 /*! @brief Set the tag field to a new value. */
01286 #define BW_FMC_TAGVDW1Sn_tag(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, (HW_FMC_TAGVDW1Sn_RD(x, n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v)))
01287 /*@}*/
01288 
01289 /*******************************************************************************
01290  * HW_FMC_TAGVDW2Sn - Cache Tag Storage
01291  ******************************************************************************/
01292 
01293 /*!
01294  * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
01295  *
01296  * Reset value: 0x00000000U
01297  *
01298  * The cache is a 4-way, set-associative cache with 4 sets. The ways are
01299  * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
01300  * denotes the set. This section represents tag/vld information for all sets in the
01301  * indicated way.
01302  */
01303 typedef union _hw_fmc_tagvdw2sn
01304 {
01305     uint32_t U;
01306     struct _hw_fmc_tagvdw2sn_bitfields
01307     {
01308         uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
01309         uint32_t RESERVED0 : 4;        /*!< [4:1]  */
01310         uint32_t tag : 14;             /*!< [18:5] 14-bit tag for cache entry */
01311         uint32_t RESERVED1 : 13;       /*!< [31:19]  */
01312     } B;
01313 } hw_fmc_tagvdw2sn_t;
01314 
01315 /*!
01316  * @name Constants and macros for entire FMC_TAGVDW2Sn register
01317  */
01318 /*@{*/
01319 #define HW_FMC_TAGVDW2Sn_COUNT (4U)
01320 
01321 #define HW_FMC_TAGVDW2Sn_ADDR(x, n) ((x) + 0x120U + (0x4U * (n)))
01322 
01323 #define HW_FMC_TAGVDW2Sn(x, n)   (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(x, n))
01324 #define HW_FMC_TAGVDW2Sn_RD(x, n) (ADDRESS_READ(hw_fmc_tagvdw2sn_t, HW_FMC_TAGVDW2Sn_ADDR(x, n)))
01325 #define HW_FMC_TAGVDW2Sn_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_tagvdw2sn_t, HW_FMC_TAGVDW2Sn_ADDR(x, n), v))
01326 #define HW_FMC_TAGVDW2Sn_SET(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) |  (v)))
01327 #define HW_FMC_TAGVDW2Sn_CLR(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) & ~(v)))
01328 #define HW_FMC_TAGVDW2Sn_TOG(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) ^  (v)))
01329 /*@}*/
01330 
01331 /*
01332  * Constants & macros for individual FMC_TAGVDW2Sn bitfields
01333  */
01334 
01335 /*!
01336  * @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
01337  */
01338 /*@{*/
01339 #define BP_FMC_TAGVDW2Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW2Sn_valid. */
01340 #define BM_FMC_TAGVDW2Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW2Sn_valid. */
01341 #define BS_FMC_TAGVDW2Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW2Sn_valid. */
01342 
01343 /*! @brief Read current value of the FMC_TAGVDW2Sn_valid field. */
01344 #define BR_FMC_TAGVDW2Sn_valid(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid)))
01345 
01346 /*! @brief Format value for bitfield FMC_TAGVDW2Sn_valid. */
01347 #define BF_FMC_TAGVDW2Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_valid) & BM_FMC_TAGVDW2Sn_valid)
01348 
01349 /*! @brief Set the valid field to a new value. */
01350 #define BW_FMC_TAGVDW2Sn_valid(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid), v))
01351 /*@}*/
01352 
01353 /*!
01354  * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW)
01355  */
01356 /*@{*/
01357 #define BP_FMC_TAGVDW2Sn_tag (5U)          /*!< Bit position for FMC_TAGVDW2Sn_tag. */
01358 #define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW2Sn_tag. */
01359 #define BS_FMC_TAGVDW2Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW2Sn_tag. */
01360 
01361 /*! @brief Read current value of the FMC_TAGVDW2Sn_tag field. */
01362 #define BR_FMC_TAGVDW2Sn_tag(x, n) (UNION_READ(hw_fmc_tagvdw2sn_t, HW_FMC_TAGVDW2Sn_ADDR(x, n), U, B.tag))
01363 
01364 /*! @brief Format value for bitfield FMC_TAGVDW2Sn_tag. */
01365 #define BF_FMC_TAGVDW2Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_tag) & BM_FMC_TAGVDW2Sn_tag)
01366 
01367 /*! @brief Set the tag field to a new value. */
01368 #define BW_FMC_TAGVDW2Sn_tag(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, (HW_FMC_TAGVDW2Sn_RD(x, n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v)))
01369 /*@}*/
01370 
01371 /*******************************************************************************
01372  * HW_FMC_TAGVDW3Sn - Cache Tag Storage
01373  ******************************************************************************/
01374 
01375 /*!
01376  * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
01377  *
01378  * Reset value: 0x00000000U
01379  *
01380  * The cache is a 4-way, set-associative cache with 4 sets. The ways are
01381  * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
01382  * denotes the set. This section represents tag/vld information for all sets in the
01383  * indicated way.
01384  */
01385 typedef union _hw_fmc_tagvdw3sn
01386 {
01387     uint32_t U;
01388     struct _hw_fmc_tagvdw3sn_bitfields
01389     {
01390         uint32_t valid : 1;            /*!< [0] 1-bit valid for cache entry */
01391         uint32_t RESERVED0 : 4;        /*!< [4:1]  */
01392         uint32_t tag : 14;             /*!< [18:5] 14-bit tag for cache entry */
01393         uint32_t RESERVED1 : 13;       /*!< [31:19]  */
01394     } B;
01395 } hw_fmc_tagvdw3sn_t;
01396 
01397 /*!
01398  * @name Constants and macros for entire FMC_TAGVDW3Sn register
01399  */
01400 /*@{*/
01401 #define HW_FMC_TAGVDW3Sn_COUNT (4U)
01402 
01403 #define HW_FMC_TAGVDW3Sn_ADDR(x, n) ((x) + 0x130U + (0x4U * (n)))
01404 
01405 #define HW_FMC_TAGVDW3Sn(x, n)   (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(x, n))
01406 #define HW_FMC_TAGVDW3Sn_RD(x, n) (ADDRESS_READ(hw_fmc_tagvdw3sn_t, HW_FMC_TAGVDW3Sn_ADDR(x, n)))
01407 #define HW_FMC_TAGVDW3Sn_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_tagvdw3sn_t, HW_FMC_TAGVDW3Sn_ADDR(x, n), v))
01408 #define HW_FMC_TAGVDW3Sn_SET(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) |  (v)))
01409 #define HW_FMC_TAGVDW3Sn_CLR(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) & ~(v)))
01410 #define HW_FMC_TAGVDW3Sn_TOG(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) ^  (v)))
01411 /*@}*/
01412 
01413 /*
01414  * Constants & macros for individual FMC_TAGVDW3Sn bitfields
01415  */
01416 
01417 /*!
01418  * @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
01419  */
01420 /*@{*/
01421 #define BP_FMC_TAGVDW3Sn_valid (0U)        /*!< Bit position for FMC_TAGVDW3Sn_valid. */
01422 #define BM_FMC_TAGVDW3Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW3Sn_valid. */
01423 #define BS_FMC_TAGVDW3Sn_valid (1U)        /*!< Bit field size in bits for FMC_TAGVDW3Sn_valid. */
01424 
01425 /*! @brief Read current value of the FMC_TAGVDW3Sn_valid field. */
01426 #define BR_FMC_TAGVDW3Sn_valid(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid)))
01427 
01428 /*! @brief Format value for bitfield FMC_TAGVDW3Sn_valid. */
01429 #define BF_FMC_TAGVDW3Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_valid) & BM_FMC_TAGVDW3Sn_valid)
01430 
01431 /*! @brief Set the valid field to a new value. */
01432 #define BW_FMC_TAGVDW3Sn_valid(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid), v))
01433 /*@}*/
01434 
01435 /*!
01436  * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW)
01437  */
01438 /*@{*/
01439 #define BP_FMC_TAGVDW3Sn_tag (5U)          /*!< Bit position for FMC_TAGVDW3Sn_tag. */
01440 #define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW3Sn_tag. */
01441 #define BS_FMC_TAGVDW3Sn_tag (14U)         /*!< Bit field size in bits for FMC_TAGVDW3Sn_tag. */
01442 
01443 /*! @brief Read current value of the FMC_TAGVDW3Sn_tag field. */
01444 #define BR_FMC_TAGVDW3Sn_tag(x, n) (UNION_READ(hw_fmc_tagvdw3sn_t, HW_FMC_TAGVDW3Sn_ADDR(x, n), U, B.tag))
01445 
01446 /*! @brief Format value for bitfield FMC_TAGVDW3Sn_tag. */
01447 #define BF_FMC_TAGVDW3Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_tag) & BM_FMC_TAGVDW3Sn_tag)
01448 
01449 /*! @brief Set the tag field to a new value. */
01450 #define BW_FMC_TAGVDW3Sn_tag(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, (HW_FMC_TAGVDW3Sn_RD(x, n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v)))
01451 /*@}*/
01452 
01453 /*******************************************************************************
01454  * HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
01455  ******************************************************************************/
01456 
01457 /*!
01458  * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW)
01459  *
01460  * Reset value: 0x00000000U
01461  *
01462  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01463  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01464  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01465  * lower word, respectively. This section represents data for the upper word (bits
01466  * [63:32]) of all sets in the indicated way.
01467  */
01468 typedef union _hw_fmc_dataw0snu
01469 {
01470     uint32_t U;
01471     struct _hw_fmc_dataw0snu_bitfields
01472     {
01473         uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
01474     } B;
01475 } hw_fmc_dataw0snu_t;
01476 
01477 /*!
01478  * @name Constants and macros for entire FMC_DATAW0SnU register
01479  */
01480 /*@{*/
01481 #define HW_FMC_DATAW0SnU_COUNT (4U)
01482 
01483 #define HW_FMC_DATAW0SnU_ADDR(x, n) ((x) + 0x200U + (0x8U * (n)))
01484 
01485 #define HW_FMC_DATAW0SnU(x, n)   (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(x, n))
01486 #define HW_FMC_DATAW0SnU_RD(x, n) (ADDRESS_READ(hw_fmc_dataw0snu_t, HW_FMC_DATAW0SnU_ADDR(x, n)))
01487 #define HW_FMC_DATAW0SnU_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_dataw0snu_t, HW_FMC_DATAW0SnU_ADDR(x, n), v))
01488 #define HW_FMC_DATAW0SnU_SET(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) |  (v)))
01489 #define HW_FMC_DATAW0SnU_CLR(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) & ~(v)))
01490 #define HW_FMC_DATAW0SnU_TOG(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) ^  (v)))
01491 /*@}*/
01492 
01493 /*
01494  * Constants & macros for individual FMC_DATAW0SnU bitfields
01495  */
01496 
01497 /*!
01498  * @name Register FMC_DATAW0SnU, field data[31:0] (RW)
01499  */
01500 /*@{*/
01501 #define BP_FMC_DATAW0SnU_data (0U)         /*!< Bit position for FMC_DATAW0SnU_data. */
01502 #define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnU_data. */
01503 #define BS_FMC_DATAW0SnU_data (32U)        /*!< Bit field size in bits for FMC_DATAW0SnU_data. */
01504 
01505 /*! @brief Read current value of the FMC_DATAW0SnU_data field. */
01506 #define BR_FMC_DATAW0SnU_data(x, n) (HW_FMC_DATAW0SnU(x, n).U)
01507 
01508 /*! @brief Format value for bitfield FMC_DATAW0SnU_data. */
01509 #define BF_FMC_DATAW0SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnU_data) & BM_FMC_DATAW0SnU_data)
01510 
01511 /*! @brief Set the data field to a new value. */
01512 #define BW_FMC_DATAW0SnU_data(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, v))
01513 /*@}*/
01514 /*******************************************************************************
01515  * HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
01516  ******************************************************************************/
01517 
01518 /*!
01519  * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW)
01520  *
01521  * Reset value: 0x00000000U
01522  *
01523  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01524  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01525  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01526  * lower word, respectively. This section represents data for the lower word (bits
01527  * [31:0]) of all sets in the indicated way.
01528  */
01529 typedef union _hw_fmc_dataw0snl
01530 {
01531     uint32_t U;
01532     struct _hw_fmc_dataw0snl_bitfields
01533     {
01534         uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
01535     } B;
01536 } hw_fmc_dataw0snl_t;
01537 
01538 /*!
01539  * @name Constants and macros for entire FMC_DATAW0SnL register
01540  */
01541 /*@{*/
01542 #define HW_FMC_DATAW0SnL_COUNT (4U)
01543 
01544 #define HW_FMC_DATAW0SnL_ADDR(x, n) ((x) + 0x204U + (0x8U * (n)))
01545 
01546 #define HW_FMC_DATAW0SnL(x, n)   (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(x, n))
01547 #define HW_FMC_DATAW0SnL_RD(x, n) (ADDRESS_READ(hw_fmc_dataw0snl_t, HW_FMC_DATAW0SnL_ADDR(x, n)))
01548 #define HW_FMC_DATAW0SnL_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_dataw0snl_t, HW_FMC_DATAW0SnL_ADDR(x, n), v))
01549 #define HW_FMC_DATAW0SnL_SET(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) |  (v)))
01550 #define HW_FMC_DATAW0SnL_CLR(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) & ~(v)))
01551 #define HW_FMC_DATAW0SnL_TOG(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) ^  (v)))
01552 /*@}*/
01553 
01554 /*
01555  * Constants & macros for individual FMC_DATAW0SnL bitfields
01556  */
01557 
01558 /*!
01559  * @name Register FMC_DATAW0SnL, field data[31:0] (RW)
01560  */
01561 /*@{*/
01562 #define BP_FMC_DATAW0SnL_data (0U)         /*!< Bit position for FMC_DATAW0SnL_data. */
01563 #define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnL_data. */
01564 #define BS_FMC_DATAW0SnL_data (32U)        /*!< Bit field size in bits for FMC_DATAW0SnL_data. */
01565 
01566 /*! @brief Read current value of the FMC_DATAW0SnL_data field. */
01567 #define BR_FMC_DATAW0SnL_data(x, n) (HW_FMC_DATAW0SnL(x, n).U)
01568 
01569 /*! @brief Format value for bitfield FMC_DATAW0SnL_data. */
01570 #define BF_FMC_DATAW0SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnL_data) & BM_FMC_DATAW0SnL_data)
01571 
01572 /*! @brief Set the data field to a new value. */
01573 #define BW_FMC_DATAW0SnL_data(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, v))
01574 /*@}*/
01575 
01576 /*******************************************************************************
01577  * HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
01578  ******************************************************************************/
01579 
01580 /*!
01581  * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW)
01582  *
01583  * Reset value: 0x00000000U
01584  *
01585  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01586  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01587  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01588  * lower word, respectively. This section represents data for the upper word (bits
01589  * [63:32]) of all sets in the indicated way.
01590  */
01591 typedef union _hw_fmc_dataw1snu
01592 {
01593     uint32_t U;
01594     struct _hw_fmc_dataw1snu_bitfields
01595     {
01596         uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
01597     } B;
01598 } hw_fmc_dataw1snu_t;
01599 
01600 /*!
01601  * @name Constants and macros for entire FMC_DATAW1SnU register
01602  */
01603 /*@{*/
01604 #define HW_FMC_DATAW1SnU_COUNT (4U)
01605 
01606 #define HW_FMC_DATAW1SnU_ADDR(x, n) ((x) + 0x220U + (0x8U * (n)))
01607 
01608 #define HW_FMC_DATAW1SnU(x, n)   (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(x, n))
01609 #define HW_FMC_DATAW1SnU_RD(x, n) (ADDRESS_READ(hw_fmc_dataw1snu_t, HW_FMC_DATAW1SnU_ADDR(x, n)))
01610 #define HW_FMC_DATAW1SnU_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_dataw1snu_t, HW_FMC_DATAW1SnU_ADDR(x, n), v))
01611 #define HW_FMC_DATAW1SnU_SET(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) |  (v)))
01612 #define HW_FMC_DATAW1SnU_CLR(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) & ~(v)))
01613 #define HW_FMC_DATAW1SnU_TOG(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) ^  (v)))
01614 /*@}*/
01615 
01616 /*
01617  * Constants & macros for individual FMC_DATAW1SnU bitfields
01618  */
01619 
01620 /*!
01621  * @name Register FMC_DATAW1SnU, field data[31:0] (RW)
01622  */
01623 /*@{*/
01624 #define BP_FMC_DATAW1SnU_data (0U)         /*!< Bit position for FMC_DATAW1SnU_data. */
01625 #define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnU_data. */
01626 #define BS_FMC_DATAW1SnU_data (32U)        /*!< Bit field size in bits for FMC_DATAW1SnU_data. */
01627 
01628 /*! @brief Read current value of the FMC_DATAW1SnU_data field. */
01629 #define BR_FMC_DATAW1SnU_data(x, n) (HW_FMC_DATAW1SnU(x, n).U)
01630 
01631 /*! @brief Format value for bitfield FMC_DATAW1SnU_data. */
01632 #define BF_FMC_DATAW1SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnU_data) & BM_FMC_DATAW1SnU_data)
01633 
01634 /*! @brief Set the data field to a new value. */
01635 #define BW_FMC_DATAW1SnU_data(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, v))
01636 /*@}*/
01637 /*******************************************************************************
01638  * HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
01639  ******************************************************************************/
01640 
01641 /*!
01642  * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW)
01643  *
01644  * Reset value: 0x00000000U
01645  *
01646  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01647  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01648  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01649  * lower word, respectively. This section represents data for the lower word (bits
01650  * [31:0]) of all sets in the indicated way.
01651  */
01652 typedef union _hw_fmc_dataw1snl
01653 {
01654     uint32_t U;
01655     struct _hw_fmc_dataw1snl_bitfields
01656     {
01657         uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
01658     } B;
01659 } hw_fmc_dataw1snl_t;
01660 
01661 /*!
01662  * @name Constants and macros for entire FMC_DATAW1SnL register
01663  */
01664 /*@{*/
01665 #define HW_FMC_DATAW1SnL_COUNT (4U)
01666 
01667 #define HW_FMC_DATAW1SnL_ADDR(x, n) ((x) + 0x224U + (0x8U * (n)))
01668 
01669 #define HW_FMC_DATAW1SnL(x, n)   (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(x, n))
01670 #define HW_FMC_DATAW1SnL_RD(x, n) (ADDRESS_READ(hw_fmc_dataw1snl_t, HW_FMC_DATAW1SnL_ADDR(x, n)))
01671 #define HW_FMC_DATAW1SnL_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_dataw1snl_t, HW_FMC_DATAW1SnL_ADDR(x, n), v))
01672 #define HW_FMC_DATAW1SnL_SET(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) |  (v)))
01673 #define HW_FMC_DATAW1SnL_CLR(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) & ~(v)))
01674 #define HW_FMC_DATAW1SnL_TOG(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) ^  (v)))
01675 /*@}*/
01676 
01677 /*
01678  * Constants & macros for individual FMC_DATAW1SnL bitfields
01679  */
01680 
01681 /*!
01682  * @name Register FMC_DATAW1SnL, field data[31:0] (RW)
01683  */
01684 /*@{*/
01685 #define BP_FMC_DATAW1SnL_data (0U)         /*!< Bit position for FMC_DATAW1SnL_data. */
01686 #define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnL_data. */
01687 #define BS_FMC_DATAW1SnL_data (32U)        /*!< Bit field size in bits for FMC_DATAW1SnL_data. */
01688 
01689 /*! @brief Read current value of the FMC_DATAW1SnL_data field. */
01690 #define BR_FMC_DATAW1SnL_data(x, n) (HW_FMC_DATAW1SnL(x, n).U)
01691 
01692 /*! @brief Format value for bitfield FMC_DATAW1SnL_data. */
01693 #define BF_FMC_DATAW1SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnL_data) & BM_FMC_DATAW1SnL_data)
01694 
01695 /*! @brief Set the data field to a new value. */
01696 #define BW_FMC_DATAW1SnL_data(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, v))
01697 /*@}*/
01698 
01699 /*******************************************************************************
01700  * HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
01701  ******************************************************************************/
01702 
01703 /*!
01704  * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW)
01705  *
01706  * Reset value: 0x00000000U
01707  *
01708  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01709  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01710  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01711  * lower word, respectively. This section represents data for the upper word (bits
01712  * [63:32]) of all sets in the indicated way.
01713  */
01714 typedef union _hw_fmc_dataw2snu
01715 {
01716     uint32_t U;
01717     struct _hw_fmc_dataw2snu_bitfields
01718     {
01719         uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
01720     } B;
01721 } hw_fmc_dataw2snu_t;
01722 
01723 /*!
01724  * @name Constants and macros for entire FMC_DATAW2SnU register
01725  */
01726 /*@{*/
01727 #define HW_FMC_DATAW2SnU_COUNT (4U)
01728 
01729 #define HW_FMC_DATAW2SnU_ADDR(x, n) ((x) + 0x240U + (0x8U * (n)))
01730 
01731 #define HW_FMC_DATAW2SnU(x, n)   (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(x, n))
01732 #define HW_FMC_DATAW2SnU_RD(x, n) (ADDRESS_READ(hw_fmc_dataw2snu_t, HW_FMC_DATAW2SnU_ADDR(x, n)))
01733 #define HW_FMC_DATAW2SnU_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_dataw2snu_t, HW_FMC_DATAW2SnU_ADDR(x, n), v))
01734 #define HW_FMC_DATAW2SnU_SET(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) |  (v)))
01735 #define HW_FMC_DATAW2SnU_CLR(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) & ~(v)))
01736 #define HW_FMC_DATAW2SnU_TOG(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) ^  (v)))
01737 /*@}*/
01738 
01739 /*
01740  * Constants & macros for individual FMC_DATAW2SnU bitfields
01741  */
01742 
01743 /*!
01744  * @name Register FMC_DATAW2SnU, field data[31:0] (RW)
01745  */
01746 /*@{*/
01747 #define BP_FMC_DATAW2SnU_data (0U)         /*!< Bit position for FMC_DATAW2SnU_data. */
01748 #define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnU_data. */
01749 #define BS_FMC_DATAW2SnU_data (32U)        /*!< Bit field size in bits for FMC_DATAW2SnU_data. */
01750 
01751 /*! @brief Read current value of the FMC_DATAW2SnU_data field. */
01752 #define BR_FMC_DATAW2SnU_data(x, n) (HW_FMC_DATAW2SnU(x, n).U)
01753 
01754 /*! @brief Format value for bitfield FMC_DATAW2SnU_data. */
01755 #define BF_FMC_DATAW2SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnU_data) & BM_FMC_DATAW2SnU_data)
01756 
01757 /*! @brief Set the data field to a new value. */
01758 #define BW_FMC_DATAW2SnU_data(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, v))
01759 /*@}*/
01760 /*******************************************************************************
01761  * HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
01762  ******************************************************************************/
01763 
01764 /*!
01765  * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW)
01766  *
01767  * Reset value: 0x00000000U
01768  *
01769  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01770  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01771  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01772  * lower word, respectively. This section represents data for the lower word (bits
01773  * [31:0]) of all sets in the indicated way.
01774  */
01775 typedef union _hw_fmc_dataw2snl
01776 {
01777     uint32_t U;
01778     struct _hw_fmc_dataw2snl_bitfields
01779     {
01780         uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
01781     } B;
01782 } hw_fmc_dataw2snl_t;
01783 
01784 /*!
01785  * @name Constants and macros for entire FMC_DATAW2SnL register
01786  */
01787 /*@{*/
01788 #define HW_FMC_DATAW2SnL_COUNT (4U)
01789 
01790 #define HW_FMC_DATAW2SnL_ADDR(x, n) ((x) + 0x244U + (0x8U * (n)))
01791 
01792 #define HW_FMC_DATAW2SnL(x, n)   (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(x, n))
01793 #define HW_FMC_DATAW2SnL_RD(x, n) (ADDRESS_READ(hw_fmc_dataw2snl_t, HW_FMC_DATAW2SnL_ADDR(x, n)))
01794 #define HW_FMC_DATAW2SnL_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_dataw2snl_t, HW_FMC_DATAW2SnL_ADDR(x, n), v))
01795 #define HW_FMC_DATAW2SnL_SET(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) |  (v)))
01796 #define HW_FMC_DATAW2SnL_CLR(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) & ~(v)))
01797 #define HW_FMC_DATAW2SnL_TOG(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) ^  (v)))
01798 /*@}*/
01799 
01800 /*
01801  * Constants & macros for individual FMC_DATAW2SnL bitfields
01802  */
01803 
01804 /*!
01805  * @name Register FMC_DATAW2SnL, field data[31:0] (RW)
01806  */
01807 /*@{*/
01808 #define BP_FMC_DATAW2SnL_data (0U)         /*!< Bit position for FMC_DATAW2SnL_data. */
01809 #define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnL_data. */
01810 #define BS_FMC_DATAW2SnL_data (32U)        /*!< Bit field size in bits for FMC_DATAW2SnL_data. */
01811 
01812 /*! @brief Read current value of the FMC_DATAW2SnL_data field. */
01813 #define BR_FMC_DATAW2SnL_data(x, n) (HW_FMC_DATAW2SnL(x, n).U)
01814 
01815 /*! @brief Format value for bitfield FMC_DATAW2SnL_data. */
01816 #define BF_FMC_DATAW2SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnL_data) & BM_FMC_DATAW2SnL_data)
01817 
01818 /*! @brief Set the data field to a new value. */
01819 #define BW_FMC_DATAW2SnL_data(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, v))
01820 /*@}*/
01821 
01822 /*******************************************************************************
01823  * HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
01824  ******************************************************************************/
01825 
01826 /*!
01827  * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW)
01828  *
01829  * Reset value: 0x00000000U
01830  *
01831  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01832  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01833  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01834  * lower word, respectively. This section represents data for the upper word (bits
01835  * [63:32]) of all sets in the indicated way.
01836  */
01837 typedef union _hw_fmc_dataw3snu
01838 {
01839     uint32_t U;
01840     struct _hw_fmc_dataw3snu_bitfields
01841     {
01842         uint32_t data : 32;            /*!< [31:0] Bits [63:32] of data entry */
01843     } B;
01844 } hw_fmc_dataw3snu_t;
01845 
01846 /*!
01847  * @name Constants and macros for entire FMC_DATAW3SnU register
01848  */
01849 /*@{*/
01850 #define HW_FMC_DATAW3SnU_COUNT (4U)
01851 
01852 #define HW_FMC_DATAW3SnU_ADDR(x, n) ((x) + 0x260U + (0x8U * (n)))
01853 
01854 #define HW_FMC_DATAW3SnU(x, n)   (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(x, n))
01855 #define HW_FMC_DATAW3SnU_RD(x, n) (ADDRESS_READ(hw_fmc_dataw3snu_t, HW_FMC_DATAW3SnU_ADDR(x, n)))
01856 #define HW_FMC_DATAW3SnU_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_dataw3snu_t, HW_FMC_DATAW3SnU_ADDR(x, n), v))
01857 #define HW_FMC_DATAW3SnU_SET(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) |  (v)))
01858 #define HW_FMC_DATAW3SnU_CLR(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) & ~(v)))
01859 #define HW_FMC_DATAW3SnU_TOG(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) ^  (v)))
01860 /*@}*/
01861 
01862 /*
01863  * Constants & macros for individual FMC_DATAW3SnU bitfields
01864  */
01865 
01866 /*!
01867  * @name Register FMC_DATAW3SnU, field data[31:0] (RW)
01868  */
01869 /*@{*/
01870 #define BP_FMC_DATAW3SnU_data (0U)         /*!< Bit position for FMC_DATAW3SnU_data. */
01871 #define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnU_data. */
01872 #define BS_FMC_DATAW3SnU_data (32U)        /*!< Bit field size in bits for FMC_DATAW3SnU_data. */
01873 
01874 /*! @brief Read current value of the FMC_DATAW3SnU_data field. */
01875 #define BR_FMC_DATAW3SnU_data(x, n) (HW_FMC_DATAW3SnU(x, n).U)
01876 
01877 /*! @brief Format value for bitfield FMC_DATAW3SnU_data. */
01878 #define BF_FMC_DATAW3SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnU_data) & BM_FMC_DATAW3SnU_data)
01879 
01880 /*! @brief Set the data field to a new value. */
01881 #define BW_FMC_DATAW3SnU_data(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, v))
01882 /*@}*/
01883 /*******************************************************************************
01884  * HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
01885  ******************************************************************************/
01886 
01887 /*!
01888  * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW)
01889  *
01890  * Reset value: 0x00000000U
01891  *
01892  * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
01893  * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
01894  * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
01895  * lower word, respectively. This section represents data for the lower word (bits
01896  * [31:0]) of all sets in the indicated way.
01897  */
01898 typedef union _hw_fmc_dataw3snl
01899 {
01900     uint32_t U;
01901     struct _hw_fmc_dataw3snl_bitfields
01902     {
01903         uint32_t data : 32;            /*!< [31:0] Bits [31:0] of data entry */
01904     } B;
01905 } hw_fmc_dataw3snl_t;
01906 
01907 /*!
01908  * @name Constants and macros for entire FMC_DATAW3SnL register
01909  */
01910 /*@{*/
01911 #define HW_FMC_DATAW3SnL_COUNT (4U)
01912 
01913 #define HW_FMC_DATAW3SnL_ADDR(x, n) ((x) + 0x264U + (0x8U * (n)))
01914 
01915 #define HW_FMC_DATAW3SnL(x, n)   (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(x, n))
01916 #define HW_FMC_DATAW3SnL_RD(x, n) (ADDRESS_READ(hw_fmc_dataw3snl_t, HW_FMC_DATAW3SnL_ADDR(x, n)))
01917 #define HW_FMC_DATAW3SnL_WR(x, n, v) (ADDRESS_WRITE(hw_fmc_dataw3snl_t, HW_FMC_DATAW3SnL_ADDR(x, n), v))
01918 #define HW_FMC_DATAW3SnL_SET(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) |  (v)))
01919 #define HW_FMC_DATAW3SnL_CLR(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) & ~(v)))
01920 #define HW_FMC_DATAW3SnL_TOG(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) ^  (v)))
01921 /*@}*/
01922 
01923 /*
01924  * Constants & macros for individual FMC_DATAW3SnL bitfields
01925  */
01926 
01927 /*!
01928  * @name Register FMC_DATAW3SnL, field data[31:0] (RW)
01929  */
01930 /*@{*/
01931 #define BP_FMC_DATAW3SnL_data (0U)         /*!< Bit position for FMC_DATAW3SnL_data. */
01932 #define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnL_data. */
01933 #define BS_FMC_DATAW3SnL_data (32U)        /*!< Bit field size in bits for FMC_DATAW3SnL_data. */
01934 
01935 /*! @brief Read current value of the FMC_DATAW3SnL_data field. */
01936 #define BR_FMC_DATAW3SnL_data(x, n) (HW_FMC_DATAW3SnL(x, n).U)
01937 
01938 /*! @brief Format value for bitfield FMC_DATAW3SnL_data. */
01939 #define BF_FMC_DATAW3SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnL_data) & BM_FMC_DATAW3SnL_data)
01940 
01941 /*! @brief Set the data field to a new value. */
01942 #define BW_FMC_DATAW3SnL_data(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, v))
01943 /*@}*/
01944 
01945 /*******************************************************************************
01946  * hw_fmc_t - module struct
01947  ******************************************************************************/
01948 /*!
01949  * @brief All FMC module registers.
01950  */
01951 #pragma pack(1)
01952 typedef struct _hw_fmc
01953 {
01954     __IO hw_fmc_pfapr_t PFAPR ;             /*!< [0x0] Flash Access Protection Register */
01955     __IO hw_fmc_pfb0cr_t PFB0CR ;           /*!< [0x4] Flash Bank 0 Control Register */
01956     __IO hw_fmc_pfb1cr_t PFB1CR ;           /*!< [0x8] Flash Bank 1 Control Register */
01957     uint8_t _reserved0[244];
01958     __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn [4];  /*!< [0x100] Cache Tag Storage */
01959     __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn [4];  /*!< [0x110] Cache Tag Storage */
01960     __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn [4];  /*!< [0x120] Cache Tag Storage */
01961     __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn [4];  /*!< [0x130] Cache Tag Storage */
01962     uint8_t _reserved1[192];
01963     struct {
01964         __IO hw_fmc_dataw0snu_t DATAW0SnU ; /*!< [0x200] Cache Data Storage (upper word) */
01965         __IO hw_fmc_dataw0snl_t DATAW0SnL ; /*!< [0x204] Cache Data Storage (lower word) */
01966     } DATAW0Sn[4];
01967     struct {
01968         __IO hw_fmc_dataw1snu_t DATAW1SnU ; /*!< [0x220] Cache Data Storage (upper word) */
01969         __IO hw_fmc_dataw1snl_t DATAW1SnL ; /*!< [0x224] Cache Data Storage (lower word) */
01970     } DATAW1Sn[4];
01971     struct {
01972         __IO hw_fmc_dataw2snu_t DATAW2SnU ; /*!< [0x240] Cache Data Storage (upper word) */
01973         __IO hw_fmc_dataw2snl_t DATAW2SnL ; /*!< [0x244] Cache Data Storage (lower word) */
01974     } DATAW2Sn[4];
01975     struct {
01976         __IO hw_fmc_dataw3snu_t DATAW3SnU ; /*!< [0x260] Cache Data Storage (upper word) */
01977         __IO hw_fmc_dataw3snl_t DATAW3SnL ; /*!< [0x264] Cache Data Storage (lower word) */
01978     } DATAW3Sn[4];
01979 } hw_fmc_t;
01980 #pragma pack()
01981 
01982 /*! @brief Macro to access all FMC registers. */
01983 /*! @param x FMC module instance base address. */
01984 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01985  *     use the '&' operator, like <code>&HW_FMC(FMC_BASE)</code>. */
01986 #define HW_FMC(x)      (*(hw_fmc_t *)(x))
01987 
01988 #endif /* __HW_FMC_REGISTERS_H__ */
01989 /* EOF */