pefect / Mbed 2 deprecated WizFi310_TCP_Echo_Server_Example

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DetectHumanClass/VL53L0X.h@2:8d119e9b8f5a, 2017-10-02 (annotated)

Committer:
maru536
Date:
Mon Oct 02 20:48:08 2017 +0000
Revision:
2:8d119e9b8f5a
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maru536 2:8d119e9b8f5a 1 #ifndef VL53L0X_h
maru536 2:8d119e9b8f5a 2 #define VL53L0X_h
maru536 2:8d119e9b8f5a 3
maru536 2:8d119e9b8f5a 4 #include <mbed.h>
maru536 2:8d119e9b8f5a 5
maru536 2:8d119e9b8f5a 6 class VL53L0X
maru536 2:8d119e9b8f5a 7 {
maru536 2:8d119e9b8f5a 8 public:
maru536 2:8d119e9b8f5a 9 // register addresses from API vl53l0x_device.h (ordered as listed there)
maru536 2:8d119e9b8f5a 10 enum regAddr
maru536 2:8d119e9b8f5a 11 {
maru536 2:8d119e9b8f5a 12 SYSRANGE_START = 0x00,
maru536 2:8d119e9b8f5a 13
maru536 2:8d119e9b8f5a 14 SYSTEM_THRESH_HIGH = 0x0C,
maru536 2:8d119e9b8f5a 15 SYSTEM_THRESH_LOW = 0x0E,
maru536 2:8d119e9b8f5a 16
maru536 2:8d119e9b8f5a 17 SYSTEM_SEQUENCE_CONFIG = 0x01,
maru536 2:8d119e9b8f5a 18 SYSTEM_RANGE_CONFIG = 0x09,
maru536 2:8d119e9b8f5a 19 SYSTEM_INTERMEASUREMENT_PERIOD = 0x04,
maru536 2:8d119e9b8f5a 20
maru536 2:8d119e9b8f5a 21 SYSTEM_INTERRUPT_CONFIG_GPIO = 0x0A,
maru536 2:8d119e9b8f5a 22
maru536 2:8d119e9b8f5a 23 GPIO_HV_MUX_ACTIVE_HIGH = 0x84,
maru536 2:8d119e9b8f5a 24
maru536 2:8d119e9b8f5a 25 SYSTEM_INTERRUPT_CLEAR = 0x0B,
maru536 2:8d119e9b8f5a 26
maru536 2:8d119e9b8f5a 27 RESULT_INTERRUPT_STATUS = 0x13,
maru536 2:8d119e9b8f5a 28 RESULT_RANGE_STATUS = 0x14,
maru536 2:8d119e9b8f5a 29
maru536 2:8d119e9b8f5a 30 RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN = 0xBC,
maru536 2:8d119e9b8f5a 31 RESULT_CORE_RANGING_TOTAL_EVENTS_RTN = 0xC0,
maru536 2:8d119e9b8f5a 32 RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF = 0xD0,
maru536 2:8d119e9b8f5a 33 RESULT_CORE_RANGING_TOTAL_EVENTS_REF = 0xD4,
maru536 2:8d119e9b8f5a 34 RESULT_PEAK_SIGNAL_RATE_REF = 0xB6,
maru536 2:8d119e9b8f5a 35
maru536 2:8d119e9b8f5a 36 ALGO_PART_TO_PART_RANGE_OFFSET_MM = 0x28,
maru536 2:8d119e9b8f5a 37
maru536 2:8d119e9b8f5a 38 I2C_SLAVE_DEVICE_ADDRESS = 0x8A,
maru536 2:8d119e9b8f5a 39
maru536 2:8d119e9b8f5a 40 MSRC_CONFIG_CONTROL = 0x60,
maru536 2:8d119e9b8f5a 41
maru536 2:8d119e9b8f5a 42 PRE_RANGE_CONFIG_MIN_SNR = 0x27,
maru536 2:8d119e9b8f5a 43 PRE_RANGE_CONFIG_VALID_PHASE_LOW = 0x56,
maru536 2:8d119e9b8f5a 44 PRE_RANGE_CONFIG_VALID_PHASE_HIGH = 0x57,
maru536 2:8d119e9b8f5a 45 PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT = 0x64,
maru536 2:8d119e9b8f5a 46
maru536 2:8d119e9b8f5a 47 FINAL_RANGE_CONFIG_MIN_SNR = 0x67,
maru536 2:8d119e9b8f5a 48 FINAL_RANGE_CONFIG_VALID_PHASE_LOW = 0x47,
maru536 2:8d119e9b8f5a 49 FINAL_RANGE_CONFIG_VALID_PHASE_HIGH = 0x48,
maru536 2:8d119e9b8f5a 50 FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT = 0x44,
maru536 2:8d119e9b8f5a 51
maru536 2:8d119e9b8f5a 52 PRE_RANGE_CONFIG_SIGMA_THRESH_HI = 0x61,
maru536 2:8d119e9b8f5a 53 PRE_RANGE_CONFIG_SIGMA_THRESH_LO = 0x62,
maru536 2:8d119e9b8f5a 54
maru536 2:8d119e9b8f5a 55 PRE_RANGE_CONFIG_VCSEL_PERIOD = 0x50,
maru536 2:8d119e9b8f5a 56 PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI = 0x51,
maru536 2:8d119e9b8f5a 57 PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO = 0x52,
maru536 2:8d119e9b8f5a 58
maru536 2:8d119e9b8f5a 59 SYSTEM_HISTOGRAM_BIN = 0x81,
maru536 2:8d119e9b8f5a 60 HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT = 0x33,
maru536 2:8d119e9b8f5a 61 HISTOGRAM_CONFIG_READOUT_CTRL = 0x55,
maru536 2:8d119e9b8f5a 62
maru536 2:8d119e9b8f5a 63 FINAL_RANGE_CONFIG_VCSEL_PERIOD = 0x70,
maru536 2:8d119e9b8f5a 64 FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI = 0x71,
maru536 2:8d119e9b8f5a 65 FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO = 0x72,
maru536 2:8d119e9b8f5a 66 CROSSTALK_COMPENSATION_PEAK_RATE_MCPS = 0x20,
maru536 2:8d119e9b8f5a 67
maru536 2:8d119e9b8f5a 68 MSRC_CONFIG_TIMEOUT_MACROP = 0x46,
maru536 2:8d119e9b8f5a 69
maru536 2:8d119e9b8f5a 70 SOFT_RESET_GO2_SOFT_RESET_N = 0xBF,
maru536 2:8d119e9b8f5a 71 IDENTIFICATION_MODEL_ID = 0xC0,
maru536 2:8d119e9b8f5a 72 IDENTIFICATION_REVISION_ID = 0xC2,
maru536 2:8d119e9b8f5a 73
maru536 2:8d119e9b8f5a 74 OSC_CALIBRATE_VAL = 0xF8,
maru536 2:8d119e9b8f5a 75
maru536 2:8d119e9b8f5a 76 GLOBAL_CONFIG_VCSEL_WIDTH = 0x32,
maru536 2:8d119e9b8f5a 77 GLOBAL_CONFIG_SPAD_ENABLES_REF_0 = 0xB0,
maru536 2:8d119e9b8f5a 78 GLOBAL_CONFIG_SPAD_ENABLES_REF_1 = 0xB1,
maru536 2:8d119e9b8f5a 79 GLOBAL_CONFIG_SPAD_ENABLES_REF_2 = 0xB2,
maru536 2:8d119e9b8f5a 80 GLOBAL_CONFIG_SPAD_ENABLES_REF_3 = 0xB3,
maru536 2:8d119e9b8f5a 81 GLOBAL_CONFIG_SPAD_ENABLES_REF_4 = 0xB4,
maru536 2:8d119e9b8f5a 82 GLOBAL_CONFIG_SPAD_ENABLES_REF_5 = 0xB5,
maru536 2:8d119e9b8f5a 83
maru536 2:8d119e9b8f5a 84 GLOBAL_CONFIG_REF_EN_START_SELECT = 0xB6,
maru536 2:8d119e9b8f5a 85 DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD = 0x4E,
maru536 2:8d119e9b8f5a 86 DYNAMIC_SPAD_REF_EN_START_OFFSET = 0x4F,
maru536 2:8d119e9b8f5a 87 POWER_MANAGEMENT_GO1_POWER_FORCE = 0x80,
maru536 2:8d119e9b8f5a 88
maru536 2:8d119e9b8f5a 89 VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV = 0x89,
maru536 2:8d119e9b8f5a 90
maru536 2:8d119e9b8f5a 91 ALGO_PHASECAL_LIM = 0x30,
maru536 2:8d119e9b8f5a 92 ALGO_PHASECAL_CONFIG_TIMEOUT = 0x30,
maru536 2:8d119e9b8f5a 93 };
maru536 2:8d119e9b8f5a 94
maru536 2:8d119e9b8f5a 95 enum vcselPeriodType { VcselPeriodPreRange, VcselPeriodFinalRange };
maru536 2:8d119e9b8f5a 96
maru536 2:8d119e9b8f5a 97 uint8_t last_status; // status of last I2C transmission
maru536 2:8d119e9b8f5a 98
maru536 2:8d119e9b8f5a 99 VL53L0X(I2C*, Timer*);
maru536 2:8d119e9b8f5a 100
maru536 2:8d119e9b8f5a 101 void setAddress(uint8_t new_addr);
maru536 2:8d119e9b8f5a 102 inline uint8_t getAddress(void) { return address; }
maru536 2:8d119e9b8f5a 103
maru536 2:8d119e9b8f5a 104 bool init(bool io_2v8 = true);
maru536 2:8d119e9b8f5a 105
maru536 2:8d119e9b8f5a 106 void writeReg(uint8_t reg, uint8_t value);
maru536 2:8d119e9b8f5a 107 void writeReg16Bit(uint8_t reg, uint16_t value);
maru536 2:8d119e9b8f5a 108 void writeReg32Bit(uint8_t reg, uint32_t value);
maru536 2:8d119e9b8f5a 109 uint8_t readReg(uint8_t reg);
maru536 2:8d119e9b8f5a 110 uint16_t readReg16Bit(uint8_t reg);
maru536 2:8d119e9b8f5a 111 uint32_t readReg32Bit(uint8_t reg);
maru536 2:8d119e9b8f5a 112
maru536 2:8d119e9b8f5a 113 void writeMulti(uint8_t reg, uint8_t const * src, uint8_t count);
maru536 2:8d119e9b8f5a 114 void readMulti(uint8_t reg, uint8_t * dst, uint8_t count);
maru536 2:8d119e9b8f5a 115
maru536 2:8d119e9b8f5a 116 bool setSignalRateLimit(float limit_Mcps);
maru536 2:8d119e9b8f5a 117 float getSignalRateLimit(void);
maru536 2:8d119e9b8f5a 118
maru536 2:8d119e9b8f5a 119 bool setMeasurementTimingBudget(uint32_t budget_us);
maru536 2:8d119e9b8f5a 120 uint32_t getMeasurementTimingBudget(void);
maru536 2:8d119e9b8f5a 121
maru536 2:8d119e9b8f5a 122 bool setVcselPulsePeriod(vcselPeriodType type, uint8_t period_pclks);
maru536 2:8d119e9b8f5a 123 uint8_t getVcselPulsePeriod(vcselPeriodType type);
maru536 2:8d119e9b8f5a 124
maru536 2:8d119e9b8f5a 125 void startContinuous(uint32_t period_ms = 0);
maru536 2:8d119e9b8f5a 126 void stopContinuous(void);
maru536 2:8d119e9b8f5a 127 uint16_t readRangeContinuousMillimeters(void);
maru536 2:8d119e9b8f5a 128 uint16_t readRangeSingleMillimeters(void);
maru536 2:8d119e9b8f5a 129
maru536 2:8d119e9b8f5a 130 inline void setTimeout(uint16_t timeout) { io_timeout = timeout; }
maru536 2:8d119e9b8f5a 131 inline uint16_t getTimeout(void) { return io_timeout; }
maru536 2:8d119e9b8f5a 132 bool timeoutOccurred(void);
maru536 2:8d119e9b8f5a 133
maru536 2:8d119e9b8f5a 134 private:
maru536 2:8d119e9b8f5a 135 // TCC: Target CentreCheck
maru536 2:8d119e9b8f5a 136 // MSRC: Minimum Signal Rate Check
maru536 2:8d119e9b8f5a 137 // DSS: Dynamic Spad Selection
maru536 2:8d119e9b8f5a 138
maru536 2:8d119e9b8f5a 139 struct SequenceStepEnables
maru536 2:8d119e9b8f5a 140 {
maru536 2:8d119e9b8f5a 141 bool tcc, msrc, dss, pre_range, final_range;
maru536 2:8d119e9b8f5a 142 };
maru536 2:8d119e9b8f5a 143
maru536 2:8d119e9b8f5a 144 struct SequenceStepTimeouts
maru536 2:8d119e9b8f5a 145 {
maru536 2:8d119e9b8f5a 146 uint16_t pre_range_vcsel_period_pclks, final_range_vcsel_period_pclks;
maru536 2:8d119e9b8f5a 147
maru536 2:8d119e9b8f5a 148 uint16_t msrc_dss_tcc_mclks, pre_range_mclks, final_range_mclks;
maru536 2:8d119e9b8f5a 149 uint32_t msrc_dss_tcc_us, pre_range_us, final_range_us;
maru536 2:8d119e9b8f5a 150 };
maru536 2:8d119e9b8f5a 151
maru536 2:8d119e9b8f5a 152 uint8_t address;
maru536 2:8d119e9b8f5a 153 uint16_t io_timeout;
maru536 2:8d119e9b8f5a 154 bool did_timeout;
maru536 2:8d119e9b8f5a 155 uint16_t timeout_start_ms;
maru536 2:8d119e9b8f5a 156
maru536 2:8d119e9b8f5a 157 uint8_t stop_variable; // read by init and used when starting measurement; is StopVariable field of VL53L0X_DevData_t structure in API
maru536 2:8d119e9b8f5a 158 uint32_t measurement_timing_budget_us;
maru536 2:8d119e9b8f5a 159
maru536 2:8d119e9b8f5a 160 bool getSpadInfo(uint8_t * count, bool * type_is_aperture);
maru536 2:8d119e9b8f5a 161
maru536 2:8d119e9b8f5a 162 void getSequenceStepEnables(SequenceStepEnables * enables);
maru536 2:8d119e9b8f5a 163 void getSequenceStepTimeouts(SequenceStepEnables const * enables, SequenceStepTimeouts * timeouts);
maru536 2:8d119e9b8f5a 164
maru536 2:8d119e9b8f5a 165 bool performSingleRefCalibration(uint8_t vhv_init_byte);
maru536 2:8d119e9b8f5a 166
maru536 2:8d119e9b8f5a 167 static uint16_t decodeTimeout(uint16_t value);
maru536 2:8d119e9b8f5a 168 static uint16_t encodeTimeout(uint16_t timeout_mclks);
maru536 2:8d119e9b8f5a 169 static uint32_t timeoutMclksToMicroseconds(uint16_t timeout_period_mclks, uint8_t vcsel_period_pclks);
maru536 2:8d119e9b8f5a 170 static uint32_t timeoutMicrosecondsToMclks(uint32_t timeout_period_us, uint8_t vcsel_period_pclks);
maru536 2:8d119e9b8f5a 171
maru536 2:8d119e9b8f5a 172 // mbed members
maru536 2:8d119e9b8f5a 173 I2C* i2c;
maru536 2:8d119e9b8f5a 174 Timer* timer;
maru536 2:8d119e9b8f5a 175 };
maru536 2:8d119e9b8f5a 176
maru536 2:8d119e9b8f5a 177 #endif