Expansion SW library to control high power stepper motor(s) using IHM03A1 expansion board(s) with Powerstep01 driver.
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: IHM03A1_ExampleFor1Motor HelloWorld_IHM03A1 IHM03A1_ExampleFor3Motors KYPHOS_Stepper_Motor_Control
Fork of X_NUCLEO_IHM03A1 by
Motor Control Library
Library to handle the X-NUCLEO-IHM03A1 Motor Control Expansion Board based on the Powerstep01 component.
It features the:
- read and write of Powerstep01 registers
- Nucleo and expansion board configuration (GPIOs, PWMs, IRQs, etc.)
- Powerstep01 application commands handling
- FLAG and BUSY interrupt handling (alarm reporting)
- Daisy chain handling
The API allows to easily:
- perform various positioning, moves and stops
- get/set or monitor the motor positions
- set home position and mark another position
- get/set minimum and maximum speed
- get current speed
- get/set acceleration and deceleration
- get/set the step mode (up to 1/128)
- get/set the control method
- get/set parameters for voltage mode driving
- get/set parameters for current mode driving
- get/set parameters for gate driving
- configure various protections such as overcurrent detection
- enable/disable alarms
- handle step-clock
- get system status
Daisy-Chain Configuration
The IHM03A1 board can be stacked up to three times so that the Powerstep01 components will be connected in daisy-chain configuration. For this purpose, some resistors must be correctly connected on the boards as depicted here below:
Platform compatibility
Compatible platforms have been tested with the default configuration provided by the HelloWorld_IHM03A1 example.
Components/powerstep01/PowerStep01_config.h@4:f48e8d87553e, 2017-03-24 (annotated)
- Committer:
- davide.aliprandi@st.com
- Date:
- Fri Mar 24 10:58:48 2017 +0100
- Revision:
- 4:f48e8d87553e
Aligning to ARM mbed coding style.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
davide.aliprandi@st.com | 4:f48e8d87553e | 1 | /** |
davide.aliprandi@st.com | 4:f48e8d87553e | 2 | ****************************************************************************** |
davide.aliprandi@st.com | 4:f48e8d87553e | 3 | * @file PowerStep01_config.h |
davide.aliprandi@st.com | 4:f48e8d87553e | 4 | * @author IPC Rennes |
davide.aliprandi@st.com | 4:f48e8d87553e | 5 | * @version V1.2.0 |
davide.aliprandi@st.com | 4:f48e8d87553e | 6 | * @date March 18th, 2016 |
davide.aliprandi@st.com | 4:f48e8d87553e | 7 | * @brief Predefines values for the Powerstep01 registers |
davide.aliprandi@st.com | 4:f48e8d87553e | 8 | * and for the devices parameters |
davide.aliprandi@st.com | 4:f48e8d87553e | 9 | * @note (C) COPYRIGHT 2016 STMicroelectronics |
davide.aliprandi@st.com | 4:f48e8d87553e | 10 | ****************************************************************************** |
davide.aliprandi@st.com | 4:f48e8d87553e | 11 | * @attention |
davide.aliprandi@st.com | 4:f48e8d87553e | 12 | * |
davide.aliprandi@st.com | 4:f48e8d87553e | 13 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
davide.aliprandi@st.com | 4:f48e8d87553e | 14 | * |
davide.aliprandi@st.com | 4:f48e8d87553e | 15 | * Redistribution and use in source and binary forms, with or without modification, |
davide.aliprandi@st.com | 4:f48e8d87553e | 16 | * are permitted provided that the following conditions are met: |
davide.aliprandi@st.com | 4:f48e8d87553e | 17 | * 1. Redistributions of source code must retain the above copyright notice, |
davide.aliprandi@st.com | 4:f48e8d87553e | 18 | * this list of conditions and the following disclaimer. |
davide.aliprandi@st.com | 4:f48e8d87553e | 19 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
davide.aliprandi@st.com | 4:f48e8d87553e | 20 | * this list of conditions and the following disclaimer in the documentation |
davide.aliprandi@st.com | 4:f48e8d87553e | 21 | * and/or other materials provided with the distribution. |
davide.aliprandi@st.com | 4:f48e8d87553e | 22 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
davide.aliprandi@st.com | 4:f48e8d87553e | 23 | * may be used to endorse or promote products derived from this software |
davide.aliprandi@st.com | 4:f48e8d87553e | 24 | * without specific prior written permission. |
davide.aliprandi@st.com | 4:f48e8d87553e | 25 | * |
davide.aliprandi@st.com | 4:f48e8d87553e | 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
davide.aliprandi@st.com | 4:f48e8d87553e | 27 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
davide.aliprandi@st.com | 4:f48e8d87553e | 28 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
davide.aliprandi@st.com | 4:f48e8d87553e | 29 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
davide.aliprandi@st.com | 4:f48e8d87553e | 30 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
davide.aliprandi@st.com | 4:f48e8d87553e | 31 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
davide.aliprandi@st.com | 4:f48e8d87553e | 32 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
davide.aliprandi@st.com | 4:f48e8d87553e | 33 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
davide.aliprandi@st.com | 4:f48e8d87553e | 34 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
davide.aliprandi@st.com | 4:f48e8d87553e | 35 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
davide.aliprandi@st.com | 4:f48e8d87553e | 36 | * |
davide.aliprandi@st.com | 4:f48e8d87553e | 37 | ****************************************************************************** |
davide.aliprandi@st.com | 4:f48e8d87553e | 38 | */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 39 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 40 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 41 | /* Define to prevent recursive inclusion -------------------------------------*/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 42 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 43 | #ifndef __POWERSTEP01_CONFIG_H |
davide.aliprandi@st.com | 4:f48e8d87553e | 44 | #define __POWERSTEP01_CONFIG_H |
davide.aliprandi@st.com | 4:f48e8d87553e | 45 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 46 | #ifdef __cplusplus |
davide.aliprandi@st.com | 4:f48e8d87553e | 47 | extern "C" { |
davide.aliprandi@st.com | 4:f48e8d87553e | 48 | #endif |
davide.aliprandi@st.com | 4:f48e8d87553e | 49 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 50 | /* Definitions ---------------------------------------------------------------*/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 51 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 52 | /** @addtogroup PowerStep01 |
davide.aliprandi@st.com | 4:f48e8d87553e | 53 | * @{ |
davide.aliprandi@st.com | 4:f48e8d87553e | 54 | */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 55 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 56 | /** @addtogroup Powerstep01_Exported_Defines |
davide.aliprandi@st.com | 4:f48e8d87553e | 57 | * @{ |
davide.aliprandi@st.com | 4:f48e8d87553e | 58 | */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 59 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 60 | /** @defgroup Predefined_Powerstep01_Registers_Values Predefined Powerstep01 Registers Values |
davide.aliprandi@st.com | 4:f48e8d87553e | 61 | * @{ |
davide.aliprandi@st.com | 4:f48e8d87553e | 62 | */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 63 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 64 | /// The maximum number of devices in the daisy chain |
davide.aliprandi@st.com | 4:f48e8d87553e | 65 | #define MAX_NUMBER_OF_DEVICES (3) |
davide.aliprandi@st.com | 4:f48e8d87553e | 66 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 67 | /****************************************************************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 68 | /* Device 0 */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 69 | /****************************************************************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 70 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 71 | /**************************** Speed Profile *********************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 72 | /// Register : ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 73 | /// Acceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
davide.aliprandi@st.com | 4:f48e8d87553e | 74 | #define POWERSTEP01_CONF_PARAM_ACC_DEVICE_0 (582) |
davide.aliprandi@st.com | 4:f48e8d87553e | 75 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 76 | /// Register : DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 77 | /// Deceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
davide.aliprandi@st.com | 4:f48e8d87553e | 78 | #define POWERSTEP01_CONF_PARAM_DEC_DEVICE_0 (582) |
davide.aliprandi@st.com | 4:f48e8d87553e | 79 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 80 | ///Register : MAX_SPEED |
davide.aliprandi@st.com | 4:f48e8d87553e | 81 | /// Maximum speed in step/s, range 15.25 to 15610 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 82 | #define POWERSTEP01_CONF_PARAM_MAX_SPEED_DEVICE_0 (488) |
davide.aliprandi@st.com | 4:f48e8d87553e | 83 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 84 | /// Register : MIN_SPEED |
davide.aliprandi@st.com | 4:f48e8d87553e | 85 | /// Minimum speed in step/s, range 0 to 976.3 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 86 | #define POWERSTEP01_CONF_PARAM_MIN_SPEED_DEVICE_0 (0) |
davide.aliprandi@st.com | 4:f48e8d87553e | 87 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 88 | /// Register : FS_SPD |
davide.aliprandi@st.com | 4:f48e8d87553e | 89 | /// Full step speed in step/s, range 7.63 to 15625 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 90 | #define POWERSTEP01_CONF_PARAM_FS_SPD_DEVICE_0 (244.16) |
davide.aliprandi@st.com | 4:f48e8d87553e | 91 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 92 | /// Register : FS_SPD - field : BOOST_MODE |
davide.aliprandi@st.com | 4:f48e8d87553e | 93 | /// Boost of the amplitude square wave, enum powerstep01_BoostMode_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 94 | #define POWERSTEP01_CONF_PARAM_BOOST_MODE_DEVICE_0 (POWERSTEP01_BOOST_MODE_OFF) |
davide.aliprandi@st.com | 4:f48e8d87553e | 95 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 96 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 97 | /************************ Voltage mode parameters **************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 98 | /// Register : KVAL_ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 99 | /// Acceleration duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 100 | #define POWERSTEP01_CONF_PARAM_KVAL_ACC_DEVICE_0 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 101 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 102 | /// Register : KVAL_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 103 | /// Deceleration duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 104 | #define POWERSTEP01_CONF_PARAM_KVAL_DEC_DEVICE_0 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 105 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 106 | /// Register : KVAL_RUN |
davide.aliprandi@st.com | 4:f48e8d87553e | 107 | /// run duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 108 | #define POWERSTEP01_CONF_PARAM_KVAL_RUN_DEVICE_0 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 109 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 110 | /// Register : KVAL_HOLD |
davide.aliprandi@st.com | 4:f48e8d87553e | 111 | /// Hold duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 112 | #define POWERSTEP01_CONF_PARAM_KVAL_HOLD_DEVICE_0 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 113 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 114 | /// Register : CONFIG - field : EN_VSCOMP |
davide.aliprandi@st.com | 4:f48e8d87553e | 115 | /// Motor Supply Voltage Compensation enabling , enum powerstep01_ConfigEnVscomp_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 116 | #define POWERSTEP01_CONF_PARAM_VS_COMP_DEVICE_0 (POWERSTEP01_CONFIG_VS_COMP_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 117 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 118 | /// Register : MIN_SPEED - field : LSPD_OPT |
davide.aliprandi@st.com | 4:f48e8d87553e | 119 | /// Low speed optimization bit, enum powerstep01_LspdOpt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 120 | #define POWERSTEP01_CONF_PARAM_LSPD_BIT_DEVICE_0 (POWERSTEP01_LSPD_OPT_OFF) |
davide.aliprandi@st.com | 4:f48e8d87553e | 121 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 122 | /// Register : K_THERM |
davide.aliprandi@st.com | 4:f48e8d87553e | 123 | /// Thermal compensation param, range 1 to 1.46875 |
davide.aliprandi@st.com | 4:f48e8d87553e | 124 | #define POWERSTEP01_CONF_PARAM_K_THERM_DEVICE_0 (1) |
davide.aliprandi@st.com | 4:f48e8d87553e | 125 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 126 | /// Register : INT_SPEED |
davide.aliprandi@st.com | 4:f48e8d87553e | 127 | /// Intersect speed settings for BEMF compensation in steps/s, range 0 to 3906 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 128 | #define POWERSTEP01_CONF_PARAM_INT_SPD_DEVICE_0 (61.512) |
davide.aliprandi@st.com | 4:f48e8d87553e | 129 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 130 | /// Register : ST_SLP |
davide.aliprandi@st.com | 4:f48e8d87553e | 131 | /// BEMF start slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
davide.aliprandi@st.com | 4:f48e8d87553e | 132 | #define POWERSTEP01_CONF_PARAM_ST_SLP_DEVICE_0 (0.03815) |
davide.aliprandi@st.com | 4:f48e8d87553e | 133 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 134 | /// Register : FN_SLP_ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 135 | /// BEMF final acc slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
davide.aliprandi@st.com | 4:f48e8d87553e | 136 | #define POWERSTEP01_CONF_PARAM_FN_SLP_ACC_DEVICE_0 (0.06256) |
davide.aliprandi@st.com | 4:f48e8d87553e | 137 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 138 | /// Register : FN_SLP_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 139 | /// BEMF final dec slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
davide.aliprandi@st.com | 4:f48e8d87553e | 140 | #define POWERSTEP01_CONF_PARAM_FN_SLP_DEC_DEVICE_0 (0.06256) |
davide.aliprandi@st.com | 4:f48e8d87553e | 141 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 142 | /// Register : CONFIG - field : F_PWM_INT |
davide.aliprandi@st.com | 4:f48e8d87553e | 143 | /// PWM Frequency Integer division, enum powerstep01_ConfigFPwmInt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 144 | #define POWERSTEP01_CONF_PARAM_PWM_DIV_DEVICE_0 (POWERSTEP01_CONFIG_PWM_DIV_2) |
davide.aliprandi@st.com | 4:f48e8d87553e | 145 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 146 | /// Register : CONFIG - field : F_PWM_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 147 | /// PWM Frequency Integer Multiplier, enum powerstep01_ConfigFPwmDec_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 148 | #define POWERSTEP01_CONF_PARAM_PWM_MUL_DEVICE_0 (POWERSTEP01_CONFIG_PWM_MUL_1) |
davide.aliprandi@st.com | 4:f48e8d87553e | 149 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 150 | /******************** Advance current control parameters *********************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 151 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 152 | /// Register : TVAL_ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 153 | /// Acceleration torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 154 | #define POWERSTEP01_CONF_PARAM_TVAL_ACC_DEVICE_0 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 155 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 156 | /// Register : TVAL_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 157 | /// Deceleration torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 158 | #define POWERSTEP01_CONF_PARAM_TVAL_DEC_DEVICE_0 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 159 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 160 | /// Register : TVAL_RUN |
davide.aliprandi@st.com | 4:f48e8d87553e | 161 | /// Running torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 162 | #define POWERSTEP01_CONF_PARAM_TVAL_RUN_DEVICE_0 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 163 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 164 | /// Register : TVAL_HOLD |
davide.aliprandi@st.com | 4:f48e8d87553e | 165 | /// Holding torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 166 | #define POWERSTEP01_CONF_PARAM_TVAL_HOLD_DEVICE_0 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 167 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 168 | /// Register : CONFIG - field : EN_TQREG |
davide.aliprandi@st.com | 4:f48e8d87553e | 169 | /// External torque regulation enabling , enum powerstep01_ConfigEnTqReg_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 170 | #define POWERSTEP01_CONF_PARAM_TQ_REG_DEVICE_0 (POWERSTEP01_CONFIG_TQ_REG_TVAL_USED) |
davide.aliprandi@st.com | 4:f48e8d87553e | 171 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 172 | /// Register : CONFIG - field : PRED_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 173 | /// Predictive current enabling , enum powerstep01_ConfigPredEn_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 174 | #define POWERSTEP01_CONF_PARAM_PRED_DEVICE_0 (POWERSTEP01_CONFIG_PRED_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 175 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 176 | /// Register : TON_MIN |
davide.aliprandi@st.com | 4:f48e8d87553e | 177 | /// Minimum on-time in us, range 0.5us to 64us |
davide.aliprandi@st.com | 4:f48e8d87553e | 178 | #define POWERSTEP01_CONF_PARAM_TON_MIN_DEVICE_0 (3.0) |
davide.aliprandi@st.com | 4:f48e8d87553e | 179 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 180 | /// Register : TOFF_MIN |
davide.aliprandi@st.com | 4:f48e8d87553e | 181 | /// Minimum off-time in us, range 0.5us to 64us |
davide.aliprandi@st.com | 4:f48e8d87553e | 182 | #define POWERSTEP01_CONF_PARAM_TOFF_MIN_DEVICE_0 (21.0) |
davide.aliprandi@st.com | 4:f48e8d87553e | 183 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 184 | /// Register : T_FAST - field: TOFF_FAST |
davide.aliprandi@st.com | 4:f48e8d87553e | 185 | /// Maximum fast decay time , enum powerstep01_ToffFast_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 186 | #define POWERSTEP01_CONF_PARAM_TOFF_FAST_DEVICE_0 (POWERSTEP01_TOFF_FAST_8us) |
davide.aliprandi@st.com | 4:f48e8d87553e | 187 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 188 | /// Register : T_FAST - field: FAST_STEP |
davide.aliprandi@st.com | 4:f48e8d87553e | 189 | /// Maximum fall step time , enum powerstep01_FastStep_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 190 | #define POWERSTEP01_CONF_PARAM_FAST_STEP_DEVICE_0 (POWERSTEP01_FAST_STEP_12us) |
davide.aliprandi@st.com | 4:f48e8d87553e | 191 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 192 | /// Register : CONFIG - field : TSW |
davide.aliprandi@st.com | 4:f48e8d87553e | 193 | /// Switching period, enum powerstep01_ConfigTsw_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 194 | #define POWERSTEP01_CONF_PARAM_TSW_DEVICE_0 (POWERSTEP01_CONFIG_TSW_048us) |
davide.aliprandi@st.com | 4:f48e8d87553e | 195 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 196 | /****************************** Gate Driving **********************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 197 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 198 | /// Register : GATECFG1 - field : IGATE |
davide.aliprandi@st.com | 4:f48e8d87553e | 199 | /// Gate sink/source current via enum powerstep01_Igate_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 200 | #define POWERSTEP01_CONF_PARAM_IGATE_DEVICE_0 (POWERSTEP01_IGATE_64mA) |
davide.aliprandi@st.com | 4:f48e8d87553e | 201 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 202 | /// Register : CONFIG - field : VCCVAL |
davide.aliprandi@st.com | 4:f48e8d87553e | 203 | /// VCC Val, enum powerstep01_ConfigVccVal_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 204 | #define POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_0 (POWERSTEP01_CONFIG_VCCVAL_15V) |
davide.aliprandi@st.com | 4:f48e8d87553e | 205 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 206 | /// Register : CONFIG - field : UVLOVAL |
davide.aliprandi@st.com | 4:f48e8d87553e | 207 | /// UVLO Threshold via powerstep01_ConfigUvLoVal_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 208 | #define POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_0 (POWERSTEP01_CONFIG_UVLOVAL_LOW) |
davide.aliprandi@st.com | 4:f48e8d87553e | 209 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 210 | /// Register : GATECFG1 - field : TBOOST |
davide.aliprandi@st.com | 4:f48e8d87553e | 211 | /// Duration of the overboost phase during gate turn-off via enum powerstep01_Tboost_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 212 | #define POWERSTEP01_CONF_PARAM_TBOOST_DEVICE_0 (POWERSTEP01_TBOOST_0ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 213 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 214 | /// Register : GATECFG1 - field : TCC |
davide.aliprandi@st.com | 4:f48e8d87553e | 215 | /// Controlled current time via enum powerstep01_Tcc_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 216 | #define POWERSTEP01_CONF_PARAM_TCC_DEVICE_0 (POWERSTEP01_TCC_500ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 217 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 218 | /// Duration of the blanking time via enum powerstep01_TBlank_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 219 | #define POWERSTEP01_CONF_PARAM_TBLANK_DEVICE_0 (POWERSTEP01_TBLANK_375ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 220 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 221 | /// Register : GATECFG2 - field : TDT |
davide.aliprandi@st.com | 4:f48e8d87553e | 222 | /// Duration of the dead time via enum powerstep01_Tdt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 223 | #define POWERSTEP01_CONF_PARAM_TDT_DEVICE_0 (POWERSTEP01_TDT_125ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 224 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 225 | /******************************* Others *************************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 226 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 227 | /// Register : OCD_TH |
davide.aliprandi@st.com | 4:f48e8d87553e | 228 | /// Overcurrent threshold settings via enum powerstep01_OcdTh_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 229 | #define POWERSTEP01_CONF_PARAM_OCD_TH_DEVICE_0 (POWERSTEP01_OCD_TH_281_25mV) |
davide.aliprandi@st.com | 4:f48e8d87553e | 230 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 231 | /// Register : CONFIG - field : OC_SD |
davide.aliprandi@st.com | 4:f48e8d87553e | 232 | /// Over current shutwdown enabling, enum powerstep01_ConfigOcSd_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 233 | #define POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_0 (POWERSTEP01_CONFIG_OC_SD_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 234 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 235 | /// Register : STALL_TH |
davide.aliprandi@st.com | 4:f48e8d87553e | 236 | /// Stall threshold settings in mV, range 31.25mV to 1000mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 237 | #define POWERSTEP01_CONF_PARAM_STALL_TH_DEVICE_0 (531.25) |
davide.aliprandi@st.com | 4:f48e8d87553e | 238 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 239 | /// Register : ALARM_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 240 | /// Alarm settings via bitmap enum powerstep01_AlarmEn_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 241 | #define POWERSTEP01_CONF_PARAM_ALARM_EN_DEVICE_0 (POWERSTEP01_ALARM_EN_OVERCURRENT | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 242 | POWERSTEP01_ALARM_EN_THERMAL_SHUTDOWN | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 243 | POWERSTEP01_ALARM_EN_THERMAL_WARNING | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 244 | POWERSTEP01_ALARM_EN_UVLO | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 245 | POWERSTEP01_ALARM_EN_STALL_DETECTION | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 246 | POWERSTEP01_ALARM_EN_SW_TURN_ON | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 247 | POWERSTEP01_ALARM_EN_WRONG_NPERF_CMD) |
davide.aliprandi@st.com | 4:f48e8d87553e | 248 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 249 | /// Register : CONFIG - field : SW_MODE |
davide.aliprandi@st.com | 4:f48e8d87553e | 250 | /// External switch hard stop interrupt mode, enum powerstep01_ConfigSwMode_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 251 | #define POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_0 (POWERSTEP01_CONFIG_SW_HARD_STOP) |
davide.aliprandi@st.com | 4:f48e8d87553e | 252 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 253 | /// Register : STEP_MODE - field : STEP_MODE |
davide.aliprandi@st.com | 4:f48e8d87553e | 254 | /// Step mode settings via enum motorStepMode_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 255 | #define POWERSTEP01_CONF_PARAM_STEP_MODE_DEVICE_0 (STEP_MODE_1_16) |
davide.aliprandi@st.com | 4:f48e8d87553e | 256 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 257 | /// Register : STEP_MODE - field : CM_VM |
davide.aliprandi@st.com | 4:f48e8d87553e | 258 | /// Current mode or Voltage mode via enum powerstep01_CmVm_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 259 | #define POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_0 (POWERSTEP01_CM_VM_CURRENT) |
davide.aliprandi@st.com | 4:f48e8d87553e | 260 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 261 | /// Register : STEP_MODE - Field : SYNC_MODE and SYNC_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 262 | /// Synch. Mode settings via enum powerstep01_SyncSel_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 263 | #define POWERSTEP01_CONF_PARAM_SYNC_MODE_DEVICE_0 (POWERSTEP01_SYNC_SEL_DISABLED) |
davide.aliprandi@st.com | 4:f48e8d87553e | 264 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 265 | /// Register : CONFIG - field : OSC_CLK_SEL |
davide.aliprandi@st.com | 4:f48e8d87553e | 266 | /// Clock setting , enum powerstep01_ConfigOscMgmt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 267 | #define POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_0 (POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_2MHZ) |
davide.aliprandi@st.com | 4:f48e8d87553e | 268 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 269 | /// Register : GATECFG1 - field : WD_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 270 | /// External clock watchdog, enum powerstep01_WdEn_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 271 | #define POWERSTEP01_CONF_PARAM_WD_EN_DEVICE_0 (POWERSTEP01_WD_EN_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 272 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 273 | /****************************************************************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 274 | /* Device 1 */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 275 | /****************************************************************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 276 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 277 | /**************************** Speed Profile *********************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 278 | /// Register : ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 279 | /// Acceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
davide.aliprandi@st.com | 4:f48e8d87553e | 280 | #define POWERSTEP01_CONF_PARAM_ACC_DEVICE_1 (2008.16) |
davide.aliprandi@st.com | 4:f48e8d87553e | 281 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 282 | /// Register : DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 283 | /// Deceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
davide.aliprandi@st.com | 4:f48e8d87553e | 284 | #define POWERSTEP01_CONF_PARAM_DEC_DEVICE_1 (2008.16) |
davide.aliprandi@st.com | 4:f48e8d87553e | 285 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 286 | ///Register : MAX_SPEED |
davide.aliprandi@st.com | 4:f48e8d87553e | 287 | /// Maximum speed in step/s, range 15.25 to 15610 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 288 | #define POWERSTEP01_CONF_PARAM_MAX_SPEED_DEVICE_1 (991.82) |
davide.aliprandi@st.com | 4:f48e8d87553e | 289 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 290 | /// Register : MIN_SPEED |
davide.aliprandi@st.com | 4:f48e8d87553e | 291 | /// Minimum speed in step/s, range 0 to 976.3 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 292 | #define POWERSTEP01_CONF_PARAM_MIN_SPEED_DEVICE_1 (0) |
davide.aliprandi@st.com | 4:f48e8d87553e | 293 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 294 | /// Register : FS_SPD |
davide.aliprandi@st.com | 4:f48e8d87553e | 295 | /// Full step speed in step/s, range 7.63 to 15625 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 296 | #define POWERSTEP01_CONF_PARAM_FS_SPD_DEVICE_1 (595.09) |
davide.aliprandi@st.com | 4:f48e8d87553e | 297 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 298 | /// Register : FS_SPD - field : BOOST_MODE |
davide.aliprandi@st.com | 4:f48e8d87553e | 299 | /// Boost of the amplitude square wave, enum powerstep01_BoostMode_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 300 | #define POWERSTEP01_CONF_PARAM_BOOST_MODE_DEVICE_1 (POWERSTEP01_BOOST_MODE_OFF) |
davide.aliprandi@st.com | 4:f48e8d87553e | 301 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 302 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 303 | /************************ Voltage mode parameters **************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 304 | /// Register : KVAL_ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 305 | /// Acceleration duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 306 | #define POWERSTEP01_CONF_PARAM_KVAL_ACC_DEVICE_1 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 307 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 308 | /// Register : KVAL_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 309 | /// Deceleration duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 310 | #define POWERSTEP01_CONF_PARAM_KVAL_DEC_DEVICE_1 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 311 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 312 | /// Register : KVAL_RUN |
davide.aliprandi@st.com | 4:f48e8d87553e | 313 | /// run duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 314 | #define POWERSTEP01_CONF_PARAM_KVAL_RUN_DEVICE_1 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 315 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 316 | /// Register : KVAL_HOLD |
davide.aliprandi@st.com | 4:f48e8d87553e | 317 | /// Hold duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 318 | #define POWERSTEP01_CONF_PARAM_KVAL_HOLD_DEVICE_1 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 319 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 320 | /// Register : CONFIG - field : EN_VSCOMP |
davide.aliprandi@st.com | 4:f48e8d87553e | 321 | /// Motor Supply Voltage Compensation enabling , enum powerstep01_ConfigEnVscomp_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 322 | #define POWERSTEP01_CONF_PARAM_VS_COMP_DEVICE_1 (POWERSTEP01_CONFIG_VS_COMP_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 323 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 324 | /// Register : MIN_SPEED - field : LSPD_OPT |
davide.aliprandi@st.com | 4:f48e8d87553e | 325 | /// Low speed optimization bit, enum powerstep01_LspdOpt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 326 | #define POWERSTEP01_CONF_PARAM_LSPD_BIT_DEVICE_1 (POWERSTEP01_LSPD_OPT_OFF) |
davide.aliprandi@st.com | 4:f48e8d87553e | 327 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 328 | /// Register : K_THERM |
davide.aliprandi@st.com | 4:f48e8d87553e | 329 | /// Thermal compensation param, range 1 to 1.46875 |
davide.aliprandi@st.com | 4:f48e8d87553e | 330 | #define POWERSTEP01_CONF_PARAM_K_THERM_DEVICE_1 (1) |
davide.aliprandi@st.com | 4:f48e8d87553e | 331 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 332 | /// Register : INT_SPEED |
davide.aliprandi@st.com | 4:f48e8d87553e | 333 | /// Intersect speed settings for BEMF compensation in steps/s, range 0 to 3906 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 334 | #define POWERSTEP01_CONF_PARAM_INT_SPD_DEVICE_1 (61.512) |
davide.aliprandi@st.com | 4:f48e8d87553e | 335 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 336 | /// Register : ST_SLP |
davide.aliprandi@st.com | 4:f48e8d87553e | 337 | /// BEMF start slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
davide.aliprandi@st.com | 4:f48e8d87553e | 338 | #define POWERSTEP01_CONF_PARAM_ST_SLP_DEVICE_1 (0.03815) |
davide.aliprandi@st.com | 4:f48e8d87553e | 339 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 340 | /// Register : FN_SLP_ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 341 | /// BEMF final acc slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
davide.aliprandi@st.com | 4:f48e8d87553e | 342 | #define POWERSTEP01_CONF_PARAM_FN_SLP_ACC_DEVICE_1 (0.06256) |
davide.aliprandi@st.com | 4:f48e8d87553e | 343 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 344 | /// Register : FN_SLP_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 345 | /// BEMF final dec slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
davide.aliprandi@st.com | 4:f48e8d87553e | 346 | #define POWERSTEP01_CONF_PARAM_FN_SLP_DEC_DEVICE_1 (0.06256) |
davide.aliprandi@st.com | 4:f48e8d87553e | 347 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 348 | /// Register : CONFIG - field : F_PWM_INT |
davide.aliprandi@st.com | 4:f48e8d87553e | 349 | /// PWM Frequency Integer division, enum powerstep01_ConfigFPwmInt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 350 | #define POWERSTEP01_CONF_PARAM_PWM_DIV_DEVICE_1 (POWERSTEP01_CONFIG_PWM_DIV_2) |
davide.aliprandi@st.com | 4:f48e8d87553e | 351 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 352 | /// Register : CONFIG - field : F_PWM_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 353 | /// PWM Frequency Integer Multiplier, enum powerstep01_ConfigFPwmDec_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 354 | #define POWERSTEP01_CONF_PARAM_PWM_MUL_DEVICE_1 (POWERSTEP01_CONFIG_PWM_MUL_1) |
davide.aliprandi@st.com | 4:f48e8d87553e | 355 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 356 | /******************** Advance current control parameters *********************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 357 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 358 | /// Register : TVAL_ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 359 | /// Acceleration torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 360 | #define POWERSTEP01_CONF_PARAM_TVAL_ACC_DEVICE_1 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 361 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 362 | /// Register : TVAL_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 363 | /// Deceleration torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 364 | #define POWERSTEP01_CONF_PARAM_TVAL_DEC_DEVICE_1 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 365 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 366 | /// Register : TVAL_RUN |
davide.aliprandi@st.com | 4:f48e8d87553e | 367 | /// Running torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 368 | #define POWERSTEP01_CONF_PARAM_TVAL_RUN_DEVICE_1 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 369 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 370 | /// Register : TVAL_HOLD |
davide.aliprandi@st.com | 4:f48e8d87553e | 371 | /// Holding torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 372 | #define POWERSTEP01_CONF_PARAM_TVAL_HOLD_DEVICE_1 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 373 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 374 | /// Register : CONFIG - field : EN_TQREG |
davide.aliprandi@st.com | 4:f48e8d87553e | 375 | /// External torque regulation enabling , enum powerstep01_ConfigEnTqReg_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 376 | #define POWERSTEP01_CONF_PARAM_TQ_REG_DEVICE_1 (POWERSTEP01_CONFIG_TQ_REG_TVAL_USED) |
davide.aliprandi@st.com | 4:f48e8d87553e | 377 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 378 | /// Register : CONFIG - field : PRED_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 379 | /// Predictive current enabling , enum powerstep01_ConfigPredEn_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 380 | #define POWERSTEP01_CONF_PARAM_PRED_DEVICE_1 (POWERSTEP01_CONFIG_PRED_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 381 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 382 | /// Register : TON_MIN |
davide.aliprandi@st.com | 4:f48e8d87553e | 383 | /// Minimum on-time in us, range 0.5us to 64us |
davide.aliprandi@st.com | 4:f48e8d87553e | 384 | #define POWERSTEP01_CONF_PARAM_TON_MIN_DEVICE_1 (3.0) |
davide.aliprandi@st.com | 4:f48e8d87553e | 385 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 386 | /// Register : TOFF_MIN |
davide.aliprandi@st.com | 4:f48e8d87553e | 387 | /// Minimum off-time in us, range 0.5us to 64us |
davide.aliprandi@st.com | 4:f48e8d87553e | 388 | #define POWERSTEP01_CONF_PARAM_TOFF_MIN_DEVICE_1 (21.0) |
davide.aliprandi@st.com | 4:f48e8d87553e | 389 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 390 | /// Register : T_FAST - field: TOFF_FAST |
davide.aliprandi@st.com | 4:f48e8d87553e | 391 | /// Maximum fast decay time , enum powerstep01_ToffFast_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 392 | #define POWERSTEP01_CONF_PARAM_TOFF_FAST_DEVICE_1 (POWERSTEP01_TOFF_FAST_8us) |
davide.aliprandi@st.com | 4:f48e8d87553e | 393 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 394 | /// Register : T_FAST - field: FAST_STEP |
davide.aliprandi@st.com | 4:f48e8d87553e | 395 | /// Maximum fall step time , enum powerstep01_FastStep_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 396 | #define POWERSTEP01_CONF_PARAM_FAST_STEP_DEVICE_1 (POWERSTEP01_FAST_STEP_12us) |
davide.aliprandi@st.com | 4:f48e8d87553e | 397 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 398 | /// Register : CONFIG - field : TSW |
davide.aliprandi@st.com | 4:f48e8d87553e | 399 | /// Switching period, enum powerstep01_ConfigTsw_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 400 | #define POWERSTEP01_CONF_PARAM_TSW_DEVICE_1 (POWERSTEP01_CONFIG_TSW_048us) |
davide.aliprandi@st.com | 4:f48e8d87553e | 401 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 402 | /****************************** Gate Driving **********************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 403 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 404 | /// Register : GATECFG1 - field : IGATE |
davide.aliprandi@st.com | 4:f48e8d87553e | 405 | /// Gate sink/source current via enum powerstep01_Igate_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 406 | #define POWERSTEP01_CONF_PARAM_IGATE_DEVICE_1 (POWERSTEP01_IGATE_64mA) |
davide.aliprandi@st.com | 4:f48e8d87553e | 407 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 408 | /// Register : CONFIG - field : VCCVAL |
davide.aliprandi@st.com | 4:f48e8d87553e | 409 | /// VCC Val, enum powerstep01_ConfigVccVal_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 410 | #define POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_1 (POWERSTEP01_CONFIG_VCCVAL_15V) |
davide.aliprandi@st.com | 4:f48e8d87553e | 411 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 412 | /// Register : CONFIG - field : UVLOVAL |
davide.aliprandi@st.com | 4:f48e8d87553e | 413 | /// UVLO Threshold via powerstep01_ConfigUvLoVal_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 414 | #define POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_1 (POWERSTEP01_CONFIG_UVLOVAL_LOW) |
davide.aliprandi@st.com | 4:f48e8d87553e | 415 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 416 | /// Register : GATECFG1 - field : TBOOST |
davide.aliprandi@st.com | 4:f48e8d87553e | 417 | /// Duration of the overboost phase during gate turn-off via enum powerstep01_Tboost_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 418 | #define POWERSTEP01_CONF_PARAM_TBOOST_DEVICE_1 (POWERSTEP01_TBOOST_0ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 419 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 420 | /// Register : GATECFG1 - field : TCC |
davide.aliprandi@st.com | 4:f48e8d87553e | 421 | /// Controlled current time via enum powerstep01_Tcc_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 422 | #define POWERSTEP01_CONF_PARAM_TCC_DEVICE_1 (POWERSTEP01_TCC_500ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 423 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 424 | /// Duration of the blanking time via enum powerstep01_TBlank_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 425 | #define POWERSTEP01_CONF_PARAM_TBLANK_DEVICE_1 (POWERSTEP01_TBLANK_375ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 426 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 427 | /// Register : GATECFG2 - field : TDT |
davide.aliprandi@st.com | 4:f48e8d87553e | 428 | /// Duration of the dead time via enum powerstep01_Tdt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 429 | #define POWERSTEP01_CONF_PARAM_TDT_DEVICE_1 (POWERSTEP01_TDT_125ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 430 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 431 | /******************************* Others *************************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 432 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 433 | /// Register : OCD_TH |
davide.aliprandi@st.com | 4:f48e8d87553e | 434 | /// Overcurrent threshold settings via enum powerstep01_OcdTh_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 435 | #define POWERSTEP01_CONF_PARAM_OCD_TH_DEVICE_1 (POWERSTEP01_OCD_TH_281_25mV) |
davide.aliprandi@st.com | 4:f48e8d87553e | 436 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 437 | /// Register : CONFIG - field : OC_SD |
davide.aliprandi@st.com | 4:f48e8d87553e | 438 | /// Over current shutwdown enabling, enum powerstep01_ConfigOcSd_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 439 | #define POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_1 (POWERSTEP01_CONFIG_OC_SD_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 440 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 441 | /// Register : STALL_TH |
davide.aliprandi@st.com | 4:f48e8d87553e | 442 | /// Stall threshold settings in mV, range 31.25mV to 1000mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 443 | #define POWERSTEP01_CONF_PARAM_STALL_TH_DEVICE_1 (531.25) |
davide.aliprandi@st.com | 4:f48e8d87553e | 444 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 445 | /// Register : ALARM_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 446 | /// Alarm settings via bitmap enum powerstep01_AlarmEn_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 447 | #define POWERSTEP01_CONF_PARAM_ALARM_EN_DEVICE_1 (POWERSTEP01_ALARM_EN_OVERCURRENT | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 448 | POWERSTEP01_ALARM_EN_THERMAL_SHUTDOWN | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 449 | POWERSTEP01_ALARM_EN_THERMAL_WARNING | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 450 | POWERSTEP01_ALARM_EN_UVLO | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 451 | POWERSTEP01_ALARM_EN_STALL_DETECTION | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 452 | POWERSTEP01_ALARM_EN_SW_TURN_ON | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 453 | POWERSTEP01_ALARM_EN_WRONG_NPERF_CMD) |
davide.aliprandi@st.com | 4:f48e8d87553e | 454 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 455 | /// Register : CONFIG - field : SW_MODE |
davide.aliprandi@st.com | 4:f48e8d87553e | 456 | /// External switch hard stop interrupt mode, enum powerstep01_ConfigSwMode_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 457 | #define POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_1 (POWERSTEP01_CONFIG_SW_HARD_STOP) |
davide.aliprandi@st.com | 4:f48e8d87553e | 458 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 459 | /// Register : STEP_MODE - field : STEP_MODE |
davide.aliprandi@st.com | 4:f48e8d87553e | 460 | /// Step mode settings via enum powerstep01_StepSel_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 461 | #define POWERSTEP01_CONF_PARAM_STEP_MODE_DEVICE_1 (STEP_MODE_1_16) |
davide.aliprandi@st.com | 4:f48e8d87553e | 462 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 463 | /// Register : STEP_MODE - field : CM_VM |
davide.aliprandi@st.com | 4:f48e8d87553e | 464 | /// Current mode or Voltage mode via enum powerstep01_CmVm_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 465 | #define POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_1 (POWERSTEP01_CM_VM_CURRENT) |
davide.aliprandi@st.com | 4:f48e8d87553e | 466 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 467 | /// Register : STEP_MODE - Field : SYNC_MODE and SYNC_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 468 | /// Synch. Mode settings via enum powerstep01_SyncSel_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 469 | #define POWERSTEP01_CONF_PARAM_SYNC_MODE_DEVICE_1 (POWERSTEP01_SYNC_SEL_DISABLED) |
davide.aliprandi@st.com | 4:f48e8d87553e | 470 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 471 | /// Register : CONFIG - field : OSC_CLK_SEL |
davide.aliprandi@st.com | 4:f48e8d87553e | 472 | /// Clock setting , enum powerstep01_ConfigOscMgmt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 473 | #define POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_1 (POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_2MHZ) |
davide.aliprandi@st.com | 4:f48e8d87553e | 474 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 475 | /// Register : GATECFG1 - field : WD_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 476 | /// External clock watchdog, enum powerstep01_WdEn_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 477 | #define POWERSTEP01_CONF_PARAM_WD_EN_DEVICE_1 (POWERSTEP01_WD_EN_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 478 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 479 | /****************************************************************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 480 | /* Device 2 */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 481 | /****************************************************************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 482 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 483 | /**************************** Speed Profile *********************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 484 | /// Register : ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 485 | /// Acceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
davide.aliprandi@st.com | 4:f48e8d87553e | 486 | #define POWERSTEP01_CONF_PARAM_ACC_DEVICE_2 (2008.16) |
davide.aliprandi@st.com | 4:f48e8d87553e | 487 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 488 | /// Register : DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 489 | /// Deceleration rate in step/s2, range 14.55 to 59590 steps/s^2 |
davide.aliprandi@st.com | 4:f48e8d87553e | 490 | #define POWERSTEP01_CONF_PARAM_DEC_DEVICE_2 (2008.16) |
davide.aliprandi@st.com | 4:f48e8d87553e | 491 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 492 | ///Register : MAX_SPEED |
davide.aliprandi@st.com | 4:f48e8d87553e | 493 | /// Maximum speed in step/s, range 15.25 to 15610 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 494 | #define POWERSTEP01_CONF_PARAM_MAX_SPEED_DEVICE_2 (991.82) |
davide.aliprandi@st.com | 4:f48e8d87553e | 495 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 496 | /// Register : MIN_SPEED |
davide.aliprandi@st.com | 4:f48e8d87553e | 497 | /// Minimum speed in step/s, range 0 to 976.3 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 498 | #define POWERSTEP01_CONF_PARAM_MIN_SPEED_DEVICE_2 (0) |
davide.aliprandi@st.com | 4:f48e8d87553e | 499 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 500 | /// Register : FS_SPD |
davide.aliprandi@st.com | 4:f48e8d87553e | 501 | /// Full step speed in step/s, range 7.63 to 15625 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 502 | #define POWERSTEP01_CONF_PARAM_FS_SPD_DEVICE_2 (595.09) |
davide.aliprandi@st.com | 4:f48e8d87553e | 503 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 504 | /// Register : FS_SPD - field : BOOST_MODE |
davide.aliprandi@st.com | 4:f48e8d87553e | 505 | /// Boost of the amplitude square wave, enum powerstep01_BoostMode_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 506 | #define POWERSTEP01_CONF_PARAM_BOOST_MODE_DEVICE_2 (POWERSTEP01_BOOST_MODE_OFF) |
davide.aliprandi@st.com | 4:f48e8d87553e | 507 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 508 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 509 | /************************ Voltage mode parameters **************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 510 | /// Register : KVAL_ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 511 | /// Acceleration duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 512 | #define POWERSTEP01_CONF_PARAM_KVAL_ACC_DEVICE_2 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 513 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 514 | /// Register : KVAL_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 515 | /// Deceleration duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 516 | #define POWERSTEP01_CONF_PARAM_KVAL_DEC_DEVICE_2 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 517 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 518 | /// Register : KVAL_RUN |
davide.aliprandi@st.com | 4:f48e8d87553e | 519 | /// run duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 520 | #define POWERSTEP01_CONF_PARAM_KVAL_RUN_DEVICE_2 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 521 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 522 | /// Register : KVAL_HOLD |
davide.aliprandi@st.com | 4:f48e8d87553e | 523 | /// Hold duty cycle (torque) in %, range 0 to 99.6% |
davide.aliprandi@st.com | 4:f48e8d87553e | 524 | #define POWERSTEP01_CONF_PARAM_KVAL_HOLD_DEVICE_2 (16.02) |
davide.aliprandi@st.com | 4:f48e8d87553e | 525 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 526 | /// Register : CONFIG - field : EN_VSCOMP |
davide.aliprandi@st.com | 4:f48e8d87553e | 527 | /// Motor Supply Voltage Compensation enabling , enum powerstep01_ConfigEnVscomp_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 528 | #define POWERSTEP01_CONF_PARAM_VS_COMP_DEVICE_2 (POWERSTEP01_CONFIG_VS_COMP_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 529 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 530 | /// Register : MIN_SPEED - field : LSPD_OPT |
davide.aliprandi@st.com | 4:f48e8d87553e | 531 | /// Low speed optimization bit, enum powerstep01_LspdOpt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 532 | #define POWERSTEP01_CONF_PARAM_LSPD_BIT_DEVICE_2 (POWERSTEP01_LSPD_OPT_OFF) |
davide.aliprandi@st.com | 4:f48e8d87553e | 533 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 534 | /// Register : K_THERM |
davide.aliprandi@st.com | 4:f48e8d87553e | 535 | /// Thermal compensation param, range 1 to 1.46875 |
davide.aliprandi@st.com | 4:f48e8d87553e | 536 | #define POWERSTEP01_CONF_PARAM_K_THERM_DEVICE_2 (1) |
davide.aliprandi@st.com | 4:f48e8d87553e | 537 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 538 | /// Register : INT_SPEED |
davide.aliprandi@st.com | 4:f48e8d87553e | 539 | /// Intersect speed settings for BEMF compensation in steps/s, range 0 to 3906 steps/s |
davide.aliprandi@st.com | 4:f48e8d87553e | 540 | #define POWERSTEP01_CONF_PARAM_INT_SPD_DEVICE_2 (61.512) |
davide.aliprandi@st.com | 4:f48e8d87553e | 541 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 542 | /// Register : ST_SLP |
davide.aliprandi@st.com | 4:f48e8d87553e | 543 | /// BEMF start slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
davide.aliprandi@st.com | 4:f48e8d87553e | 544 | #define POWERSTEP01_CONF_PARAM_ST_SLP_DEVICE_2 (0.03815) |
davide.aliprandi@st.com | 4:f48e8d87553e | 545 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 546 | /// Register : FN_SLP_ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 547 | /// BEMF final acc slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
davide.aliprandi@st.com | 4:f48e8d87553e | 548 | #define POWERSTEP01_CONF_PARAM_FN_SLP_ACC_DEVICE_2 (0.06256) |
davide.aliprandi@st.com | 4:f48e8d87553e | 549 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 550 | /// Register : FN_SLP_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 551 | /// BEMF final dec slope settings for BEMF compensation in % step/s, range 0 to 0.4% s/step |
davide.aliprandi@st.com | 4:f48e8d87553e | 552 | #define POWERSTEP01_CONF_PARAM_FN_SLP_DEC_DEVICE_2 (0.06256) |
davide.aliprandi@st.com | 4:f48e8d87553e | 553 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 554 | /// Register : CONFIG - field : F_PWM_INT |
davide.aliprandi@st.com | 4:f48e8d87553e | 555 | /// PWM Frequency Integer division, enum powerstep01_ConfigFPwmInt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 556 | #define POWERSTEP01_CONF_PARAM_PWM_DIV_DEVICE_2 (POWERSTEP01_CONFIG_PWM_DIV_2) |
davide.aliprandi@st.com | 4:f48e8d87553e | 557 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 558 | /// Register : CONFIG - field : F_PWM_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 559 | /// PWM Frequency Integer Multiplier, enum powerstep01_ConfigFPwmDec_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 560 | #define POWERSTEP01_CONF_PARAM_PWM_MUL_DEVICE_2 (POWERSTEP01_CONFIG_PWM_MUL_1) |
davide.aliprandi@st.com | 4:f48e8d87553e | 561 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 562 | /******************** Advance current control parameters *********************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 563 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 564 | /// Register : TVAL_ACC |
davide.aliprandi@st.com | 4:f48e8d87553e | 565 | /// Acceleration torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 566 | #define POWERSTEP01_CONF_PARAM_TVAL_ACC_DEVICE_2 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 567 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 568 | /// Register : TVAL_DEC |
davide.aliprandi@st.com | 4:f48e8d87553e | 569 | /// Deceleration torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 570 | #define POWERSTEP01_CONF_PARAM_TVAL_DEC_DEVICE_2 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 571 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 572 | /// Register : TVAL_RUN |
davide.aliprandi@st.com | 4:f48e8d87553e | 573 | /// Running torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 574 | #define POWERSTEP01_CONF_PARAM_TVAL_RUN_DEVICE_2 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 575 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 576 | /// Register : TVAL_HOLD |
davide.aliprandi@st.com | 4:f48e8d87553e | 577 | /// Holding torque in mV, range from 7.8mV to 1000 mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 578 | #define POWERSTEP01_CONF_PARAM_TVAL_HOLD_DEVICE_2 (328.12) |
davide.aliprandi@st.com | 4:f48e8d87553e | 579 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 580 | /// Register : CONFIG - field : EN_TQREG |
davide.aliprandi@st.com | 4:f48e8d87553e | 581 | /// External torque regulation enabling , enum powerstep01_ConfigEnTqReg_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 582 | #define POWERSTEP01_CONF_PARAM_TQ_REG_DEVICE_2 (POWERSTEP01_CONFIG_TQ_REG_TVAL_USED) |
davide.aliprandi@st.com | 4:f48e8d87553e | 583 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 584 | /// Register : CONFIG - field : PRED_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 585 | /// Predictive current enabling , enum powerstep01_ConfigPredEn_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 586 | #define POWERSTEP01_CONF_PARAM_PRED_DEVICE_2 (POWERSTEP01_CONFIG_PRED_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 587 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 588 | /// Register : TON_MIN |
davide.aliprandi@st.com | 4:f48e8d87553e | 589 | /// Minimum on-time in us, range 0.5us to 64us |
davide.aliprandi@st.com | 4:f48e8d87553e | 590 | #define POWERSTEP01_CONF_PARAM_TON_MIN_DEVICE_2 (3.0) |
davide.aliprandi@st.com | 4:f48e8d87553e | 591 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 592 | /// Register : TOFF_MIN |
davide.aliprandi@st.com | 4:f48e8d87553e | 593 | /// Minimum off-time in us, range 0.5us to 64us |
davide.aliprandi@st.com | 4:f48e8d87553e | 594 | #define POWERSTEP01_CONF_PARAM_TOFF_MIN_DEVICE_2 (21.0) |
davide.aliprandi@st.com | 4:f48e8d87553e | 595 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 596 | /// Register : T_FAST - field: TOFF_FAST |
davide.aliprandi@st.com | 4:f48e8d87553e | 597 | /// Maximum fast decay time , enum powerstep01_ToffFast_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 598 | #define POWERSTEP01_CONF_PARAM_TOFF_FAST_DEVICE_2 (POWERSTEP01_TOFF_FAST_8us) |
davide.aliprandi@st.com | 4:f48e8d87553e | 599 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 600 | /// Register : T_FAST - field: FAST_STEP |
davide.aliprandi@st.com | 4:f48e8d87553e | 601 | /// Maximum fall step time , enum powerstep01_FastStep_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 602 | #define POWERSTEP01_CONF_PARAM_FAST_STEP_DEVICE_2 (POWERSTEP01_FAST_STEP_12us) |
davide.aliprandi@st.com | 4:f48e8d87553e | 603 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 604 | /// Register : CONFIG - field : TSW |
davide.aliprandi@st.com | 4:f48e8d87553e | 605 | /// Switching period, enum powerstep01_ConfigTsw_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 606 | #define POWERSTEP01_CONF_PARAM_TSW_DEVICE_2 (POWERSTEP01_CONFIG_TSW_048us) |
davide.aliprandi@st.com | 4:f48e8d87553e | 607 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 608 | /****************************** Gate Driving **********************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 609 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 610 | /// Register : GATECFG1 - field : IGATE |
davide.aliprandi@st.com | 4:f48e8d87553e | 611 | /// Gate sink/source current via enum powerstep01_Igate_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 612 | #define POWERSTEP01_CONF_PARAM_IGATE_DEVICE_2 (POWERSTEP01_IGATE_64mA) |
davide.aliprandi@st.com | 4:f48e8d87553e | 613 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 614 | /// Register : CONFIG - field : VCCVAL |
davide.aliprandi@st.com | 4:f48e8d87553e | 615 | /// VCC Val, enum powerstep01_ConfigVccVal_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 616 | #define POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_2 (POWERSTEP01_CONFIG_VCCVAL_15V) |
davide.aliprandi@st.com | 4:f48e8d87553e | 617 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 618 | /// Register : CONFIG - field : UVLOVAL |
davide.aliprandi@st.com | 4:f48e8d87553e | 619 | /// UVLO Threshold via powerstep01_ConfigUvLoVal_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 620 | #define POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_2 (POWERSTEP01_CONFIG_UVLOVAL_LOW) |
davide.aliprandi@st.com | 4:f48e8d87553e | 621 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 622 | /// Register : GATECFG1 - field : TBOOST |
davide.aliprandi@st.com | 4:f48e8d87553e | 623 | /// Duration of the overboost phase during gate turn-off via enum powerstep01_Tboost_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 624 | #define POWERSTEP01_CONF_PARAM_TBOOST_DEVICE_2 (POWERSTEP01_TBOOST_0ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 625 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 626 | /// Register : GATECFG1 - field : TCC |
davide.aliprandi@st.com | 4:f48e8d87553e | 627 | /// Controlled current time via enum powerstep01_Tcc_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 628 | #define POWERSTEP01_CONF_PARAM_TCC_DEVICE_2 (POWERSTEP01_TCC_500ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 629 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 630 | /// Duration of the blanking time via enum powerstep01_TBlank_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 631 | #define POWERSTEP01_CONF_PARAM_TBLANK_DEVICE_2 (POWERSTEP01_TBLANK_375ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 632 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 633 | /// Register : GATECFG2 - field : TDT |
davide.aliprandi@st.com | 4:f48e8d87553e | 634 | /// Duration of the dead time via enum powerstep01_Tdt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 635 | #define POWERSTEP01_CONF_PARAM_TDT_DEVICE_2 (POWERSTEP01_TDT_125ns) |
davide.aliprandi@st.com | 4:f48e8d87553e | 636 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 637 | /******************************* Others *************************************/ |
davide.aliprandi@st.com | 4:f48e8d87553e | 638 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 639 | /// Register : OCD_TH |
davide.aliprandi@st.com | 4:f48e8d87553e | 640 | /// Overcurrent threshold settings via enum powerstep01_OcdTh_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 641 | #define POWERSTEP01_CONF_PARAM_OCD_TH_DEVICE_2 (POWERSTEP01_OCD_TH_281_25mV) |
davide.aliprandi@st.com | 4:f48e8d87553e | 642 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 643 | /// Register : CONFIG - field : OC_SD |
davide.aliprandi@st.com | 4:f48e8d87553e | 644 | /// Over current shutwdown enabling, enum powerstep01_ConfigOcSd_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 645 | #define POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_2 (POWERSTEP01_CONFIG_OC_SD_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 646 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 647 | /// Register : STALL_TH |
davide.aliprandi@st.com | 4:f48e8d87553e | 648 | /// Stall threshold settings in mV, range 31.25mV to 1000mV |
davide.aliprandi@st.com | 4:f48e8d87553e | 649 | #define POWERSTEP01_CONF_PARAM_STALL_TH_DEVICE_2 (531.25) |
davide.aliprandi@st.com | 4:f48e8d87553e | 650 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 651 | /// Register : ALARM_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 652 | /// Alarm settings via bitmap enum powerstep01_AlarmEn_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 653 | #define POWERSTEP01_CONF_PARAM_ALARM_EN_DEVICE_2 (POWERSTEP01_ALARM_EN_OVERCURRENT | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 654 | POWERSTEP01_ALARM_EN_THERMAL_SHUTDOWN | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 655 | POWERSTEP01_ALARM_EN_THERMAL_WARNING | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 656 | POWERSTEP01_ALARM_EN_UVLO | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 657 | POWERSTEP01_ALARM_EN_STALL_DETECTION | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 658 | POWERSTEP01_ALARM_EN_SW_TURN_ON | \ |
davide.aliprandi@st.com | 4:f48e8d87553e | 659 | POWERSTEP01_ALARM_EN_WRONG_NPERF_CMD) |
davide.aliprandi@st.com | 4:f48e8d87553e | 660 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 661 | /// Register : CONFIG - field : SW_MODE |
davide.aliprandi@st.com | 4:f48e8d87553e | 662 | /// External switch hard stop interrupt mode, enum powerstep01_ConfigSwMode_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 663 | #define POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_2 (POWERSTEP01_CONFIG_SW_HARD_STOP) |
davide.aliprandi@st.com | 4:f48e8d87553e | 664 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 665 | /// Register : STEP_MODE - field : STEP_MODE |
davide.aliprandi@st.com | 4:f48e8d87553e | 666 | /// Step mode settings via enum powerstep01_StepSel_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 667 | #define POWERSTEP01_CONF_PARAM_STEP_MODE_DEVICE_2 (STEP_MODE_1_16) |
davide.aliprandi@st.com | 4:f48e8d87553e | 668 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 669 | /// Register : STEP_MODE - field : CM_VM |
davide.aliprandi@st.com | 4:f48e8d87553e | 670 | /// Current mode or Voltage mode via enum powerstep01_CmVm_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 671 | #define POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_2 (POWERSTEP01_CM_VM_CURRENT) |
davide.aliprandi@st.com | 4:f48e8d87553e | 672 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 673 | /// Register : STEP_MODE - Field : SYNC_MODE and SYNC_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 674 | /// Synch. Mode settings via enum powerstep01_SyncSel_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 675 | #define POWERSTEP01_CONF_PARAM_SYNC_MODE_DEVICE_2 (POWERSTEP01_SYNC_SEL_DISABLED) |
davide.aliprandi@st.com | 4:f48e8d87553e | 676 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 677 | /// Register : CONFIG - field : OSC_CLK_SEL |
davide.aliprandi@st.com | 4:f48e8d87553e | 678 | /// Clock setting , enum powerstep01_ConfigOscMgmt_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 679 | #define POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_2 (POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_2MHZ) |
davide.aliprandi@st.com | 4:f48e8d87553e | 680 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 681 | /// Register : GATECFG1 - field : WD_EN |
davide.aliprandi@st.com | 4:f48e8d87553e | 682 | /// External clock watchdog, enum powerstep01_WdEn_t |
davide.aliprandi@st.com | 4:f48e8d87553e | 683 | #define POWERSTEP01_CONF_PARAM_WD_EN_DEVICE_2 (POWERSTEP01_WD_EN_DISABLE) |
davide.aliprandi@st.com | 4:f48e8d87553e | 684 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 685 | /** |
davide.aliprandi@st.com | 4:f48e8d87553e | 686 | * @} |
davide.aliprandi@st.com | 4:f48e8d87553e | 687 | */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 688 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 689 | /** |
davide.aliprandi@st.com | 4:f48e8d87553e | 690 | * @} |
davide.aliprandi@st.com | 4:f48e8d87553e | 691 | */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 692 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 693 | /** |
davide.aliprandi@st.com | 4:f48e8d87553e | 694 | * @} |
davide.aliprandi@st.com | 4:f48e8d87553e | 695 | */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 696 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 697 | #ifdef __cplusplus |
davide.aliprandi@st.com | 4:f48e8d87553e | 698 | } |
davide.aliprandi@st.com | 4:f48e8d87553e | 699 | #endif |
davide.aliprandi@st.com | 4:f48e8d87553e | 700 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 701 | #endif /* __POWERSTEP01_CONFIG_H */ |
davide.aliprandi@st.com | 4:f48e8d87553e | 702 | |
davide.aliprandi@st.com | 4:f48e8d87553e | 703 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |