Expansion SW library to control high power stepper motor(s) using IHM03A1 expansion board(s) with Powerstep01 driver.

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

Dependents:   IHM03A1_ExampleFor1Motor HelloWorld_IHM03A1 IHM03A1_ExampleFor3Motors KYPHOS_Stepper_Motor_Control

Fork of X_NUCLEO_IHM03A1 by ST Expansion SW Team

Motor Control Library

Library to handle the X-NUCLEO-IHM03A1 Motor Control Expansion Board based on the Powerstep01 component.

It features the:

  • read and write of Powerstep01 registers
  • Nucleo and expansion board configuration (GPIOs, PWMs, IRQs, etc.)
  • Powerstep01 application commands handling
  • FLAG and BUSY interrupt handling (alarm reporting)
  • Daisy chain handling

The API allows to easily:

  • perform various positioning, moves and stops
  • get/set or monitor the motor positions
  • set home position and mark another position
  • get/set minimum and maximum speed
  • get current speed
  • get/set acceleration and deceleration
  • get/set the step mode (up to 1/128)
  • get/set the control method
  • get/set parameters for voltage mode driving
  • get/set parameters for current mode driving
  • get/set parameters for gate driving
  • configure various protections such as overcurrent detection
  • enable/disable alarms
  • handle step-clock
  • get system status

Daisy-Chain Configuration

The IHM03A1 board can be stacked up to three times so that the Powerstep01 components will be connected in daisy-chain configuration. For this purpose, some resistors must be correctly connected on the boards as depicted here below:

/media/uploads/nucleosam/driving1steppermotor.png /media/uploads/nucleosam/driving2steppermotors.png /media/uploads/nucleosam/driving3steppermotors.png

Platform compatibility

Compatible platforms have been tested with the default configuration provided by the HelloWorld_IHM03A1 example.

Committer:
Davidroid
Date:
Fri Mar 24 10:24:39 2017 +0000
Revision:
5:e7dca8c6ae9f
Parent:
Components/powerstep01/PowerStep01_def.h@4:f48e8d87553e
Typo fixed.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
davide.aliprandi@st.com 4:f48e8d87553e 1 /**
davide.aliprandi@st.com 4:f48e8d87553e 2 ******************************************************************************
davide.aliprandi@st.com 4:f48e8d87553e 3 * @file PowerStep01.h
davide.aliprandi@st.com 4:f48e8d87553e 4 * @author IPC Rennes
davide.aliprandi@st.com 4:f48e8d87553e 5 * @version V1.2.0
davide.aliprandi@st.com 4:f48e8d87553e 6 * @date January 25th, 2016
davide.aliprandi@st.com 4:f48e8d87553e 7 * @brief Header for Powerstep01 motor driver (Microstepping controller with power MOSFETs)
davide.aliprandi@st.com 4:f48e8d87553e 8 * @note (C) COPYRIGHT 2016 STMicroelectronics
davide.aliprandi@st.com 4:f48e8d87553e 9 ******************************************************************************
davide.aliprandi@st.com 4:f48e8d87553e 10 * @attention
davide.aliprandi@st.com 4:f48e8d87553e 11 *
davide.aliprandi@st.com 4:f48e8d87553e 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
davide.aliprandi@st.com 4:f48e8d87553e 13 *
davide.aliprandi@st.com 4:f48e8d87553e 14 * Redistribution and use in source and binary forms, with or without modification,
davide.aliprandi@st.com 4:f48e8d87553e 15 * are permitted provided that the following conditions are met:
davide.aliprandi@st.com 4:f48e8d87553e 16 * 1. Redistributions of source code must retain the above copyright notice,
davide.aliprandi@st.com 4:f48e8d87553e 17 * this list of conditions and the following disclaimer.
davide.aliprandi@st.com 4:f48e8d87553e 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
davide.aliprandi@st.com 4:f48e8d87553e 19 * this list of conditions and the following disclaimer in the documentation
davide.aliprandi@st.com 4:f48e8d87553e 20 * and/or other materials provided with the distribution.
davide.aliprandi@st.com 4:f48e8d87553e 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
davide.aliprandi@st.com 4:f48e8d87553e 22 * may be used to endorse or promote products derived from this software
davide.aliprandi@st.com 4:f48e8d87553e 23 * without specific prior written permission.
davide.aliprandi@st.com 4:f48e8d87553e 24 *
davide.aliprandi@st.com 4:f48e8d87553e 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
davide.aliprandi@st.com 4:f48e8d87553e 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
davide.aliprandi@st.com 4:f48e8d87553e 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
davide.aliprandi@st.com 4:f48e8d87553e 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
davide.aliprandi@st.com 4:f48e8d87553e 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
davide.aliprandi@st.com 4:f48e8d87553e 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
davide.aliprandi@st.com 4:f48e8d87553e 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
davide.aliprandi@st.com 4:f48e8d87553e 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
davide.aliprandi@st.com 4:f48e8d87553e 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
davide.aliprandi@st.com 4:f48e8d87553e 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
davide.aliprandi@st.com 4:f48e8d87553e 35 *
davide.aliprandi@st.com 4:f48e8d87553e 36 ******************************************************************************
davide.aliprandi@st.com 4:f48e8d87553e 37 */
davide.aliprandi@st.com 4:f48e8d87553e 38
davide.aliprandi@st.com 4:f48e8d87553e 39 /* Define to prevent recursive inclusion -------------------------------------*/
davide.aliprandi@st.com 4:f48e8d87553e 40 #ifndef _POWERSTEP01_H_INCLUDED
davide.aliprandi@st.com 4:f48e8d87553e 41 #define _POWERSTEP01_H_INCLUDED
davide.aliprandi@st.com 4:f48e8d87553e 42
davide.aliprandi@st.com 4:f48e8d87553e 43 #ifdef __cplusplus
davide.aliprandi@st.com 4:f48e8d87553e 44 extern "C" {
davide.aliprandi@st.com 4:f48e8d87553e 45 #endif
davide.aliprandi@st.com 4:f48e8d87553e 46
davide.aliprandi@st.com 4:f48e8d87553e 47 /* Includes ------------------------------------------------------------------*/
davide.aliprandi@st.com 4:f48e8d87553e 48 #include "PowerStep01_config.h"
davide.aliprandi@st.com 4:f48e8d87553e 49 #include "stdint.h"
davide.aliprandi@st.com 4:f48e8d87553e 50 #include "motor_def.h"
davide.aliprandi@st.com 4:f48e8d87553e 51
davide.aliprandi@st.com 4:f48e8d87553e 52 /* Definitions ---------------------------------------------------------------*/
davide.aliprandi@st.com 4:f48e8d87553e 53
davide.aliprandi@st.com 4:f48e8d87553e 54 /** @addtogroup Components
davide.aliprandi@st.com 4:f48e8d87553e 55 * @{
davide.aliprandi@st.com 4:f48e8d87553e 56 */
davide.aliprandi@st.com 4:f48e8d87553e 57
davide.aliprandi@st.com 4:f48e8d87553e 58 /** @defgroup PowerStep01 PowerStep01
davide.aliprandi@st.com 4:f48e8d87553e 59 * @{
davide.aliprandi@st.com 4:f48e8d87553e 60 */
davide.aliprandi@st.com 4:f48e8d87553e 61
davide.aliprandi@st.com 4:f48e8d87553e 62 /** @defgroup Powerstep01_Exported_Defines Powerstep01_Exported_Defines
davide.aliprandi@st.com 4:f48e8d87553e 63 * @{
davide.aliprandi@st.com 4:f48e8d87553e 64 */
davide.aliprandi@st.com 4:f48e8d87553e 65 /// Current FW major version
davide.aliprandi@st.com 4:f48e8d87553e 66 #define POWERSTEP01_FW_MAJOR_VERSION (uint8_t)(1)
davide.aliprandi@st.com 4:f48e8d87553e 67 /// Current FW minor version
davide.aliprandi@st.com 4:f48e8d87553e 68 #define POWERSTEP01_FW_MINOR_VERSION (uint8_t)(2)
davide.aliprandi@st.com 4:f48e8d87553e 69 /// Current FW patch version
davide.aliprandi@st.com 4:f48e8d87553e 70 #define POWERSTEP01_FW_PATCH_VERSION (uint8_t)(0)
davide.aliprandi@st.com 4:f48e8d87553e 71 /// Current FW version
davide.aliprandi@st.com 4:f48e8d87553e 72 #define POWERSTEP01_FW_VERSION (uint32_t)((POWERSTEP01_FW_MAJOR_VERSION<<16)|\
davide.aliprandi@st.com 4:f48e8d87553e 73 (POWERSTEP01_FW_MINOR_VERSION<<8)|\
davide.aliprandi@st.com 4:f48e8d87553e 74 (POWERSTEP01_FW_PATCH_VERSION))
davide.aliprandi@st.com 4:f48e8d87553e 75
davide.aliprandi@st.com 4:f48e8d87553e 76 /// Powerstep01 max number of bytes of command & arguments to set a parameter
davide.aliprandi@st.com 4:f48e8d87553e 77 #define POWERSTEP01_CMD_ARG_MAX_NB_BYTES (4)
davide.aliprandi@st.com 4:f48e8d87553e 78
davide.aliprandi@st.com 4:f48e8d87553e 79 /// Powerstep01 command + argument bytes number for NOP command
davide.aliprandi@st.com 4:f48e8d87553e 80 #define POWERSTEP01_CMD_ARG_NB_BYTES_NOP (1)
davide.aliprandi@st.com 4:f48e8d87553e 81 /// Powerstep01 command + argument bytes number for RUN command
davide.aliprandi@st.com 4:f48e8d87553e 82 #define POWERSTEP01_CMD_ARG_NB_BYTES_RUN (4)
davide.aliprandi@st.com 4:f48e8d87553e 83 /// Powerstep01 command + argument bytes number for STEP_CLOCK command
davide.aliprandi@st.com 4:f48e8d87553e 84 #define POWERSTEP01_CMD_ARG_NB_BYTES_STEP_CLOCK (1)
davide.aliprandi@st.com 4:f48e8d87553e 85 /// Powerstep01 command + argument bytes number for MOVE command
davide.aliprandi@st.com 4:f48e8d87553e 86 #define POWERSTEP01_CMD_ARG_NB_BYTES_MOVE (4)
davide.aliprandi@st.com 4:f48e8d87553e 87 /// Powerstep01 command + argument bytes number for GO_TO command
davide.aliprandi@st.com 4:f48e8d87553e 88 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_TO (4)
davide.aliprandi@st.com 4:f48e8d87553e 89 /// Powerstep01 command + argument bytes number for GO_TO_DIR command
davide.aliprandi@st.com 4:f48e8d87553e 90 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_TO_DIR (4)
davide.aliprandi@st.com 4:f48e8d87553e 91 /// Powerstep01 command + argument bytes number for GO_UNTIL command
davide.aliprandi@st.com 4:f48e8d87553e 92 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_UNTIL (4)
davide.aliprandi@st.com 4:f48e8d87553e 93 /// Powerstep01 command + argument bytes number for RELEASE_SW command
davide.aliprandi@st.com 4:f48e8d87553e 94 #define POWERSTEP01_CMD_ARG_NB_BYTES_RELEASE_SW (1)
davide.aliprandi@st.com 4:f48e8d87553e 95 /// Powerstep01 command + argument bytes number for GO_HOME command
davide.aliprandi@st.com 4:f48e8d87553e 96 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_HOME (1)
davide.aliprandi@st.com 4:f48e8d87553e 97 /// Powerstep01 command + argument bytes number for GO_MARK command
davide.aliprandi@st.com 4:f48e8d87553e 98 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_MARK (1)
davide.aliprandi@st.com 4:f48e8d87553e 99 /// Powerstep01 command + argument bytes number for RESET_POS command
davide.aliprandi@st.com 4:f48e8d87553e 100 #define POWERSTEP01_CMD_ARG_NB_BYTES_RESET_POS (1)
davide.aliprandi@st.com 4:f48e8d87553e 101 /// Powerstep01 command + argument bytes number for RESET_DEVICE command
davide.aliprandi@st.com 4:f48e8d87553e 102 #define POWERSTEP01_CMD_ARG_NB_BYTES_RESET_DEVICE (1)
davide.aliprandi@st.com 4:f48e8d87553e 103 /// Powerstep01 command + argument bytes number for NOP command
davide.aliprandi@st.com 4:f48e8d87553e 104 #define POWERSTEP01_CMD_ARG_NB_BYTES_SOFT_STOP (1)
davide.aliprandi@st.com 4:f48e8d87553e 105 /// Powerstep01 command + argument bytes number for HARD_STOP command
davide.aliprandi@st.com 4:f48e8d87553e 106 #define POWERSTEP01_CMD_ARG_NB_BYTES_HARD_STOP (1)
davide.aliprandi@st.com 4:f48e8d87553e 107 /// Powerstep01 command + argument bytes number for SOFT_HIZ command
davide.aliprandi@st.com 4:f48e8d87553e 108 #define POWERSTEP01_CMD_ARG_NB_BYTES_SOFT_HIZ (1)
davide.aliprandi@st.com 4:f48e8d87553e 109 /// Powerstep01 command + argument bytes number for ARD_HIZ command
davide.aliprandi@st.com 4:f48e8d87553e 110 #define POWERSTEP01_CMD_ARG_NB_BYTES_HARD_HIZ (1)
davide.aliprandi@st.com 4:f48e8d87553e 111 /// Powerstep01 command + argument bytes number for GET_STATUS command
davide.aliprandi@st.com 4:f48e8d87553e 112 #define POWERSTEP01_CMD_ARG_NB_BYTES_GET_STATUS (1)
davide.aliprandi@st.com 4:f48e8d87553e 113
davide.aliprandi@st.com 4:f48e8d87553e 114 /// Powerstep01 response bytes number
davide.aliprandi@st.com 4:f48e8d87553e 115 #define POWERSTEP01_RSP_NB_BYTES_GET_STATUS (2)
davide.aliprandi@st.com 4:f48e8d87553e 116
davide.aliprandi@st.com 4:f48e8d87553e 117 /// Daisy chain command mask
davide.aliprandi@st.com 4:f48e8d87553e 118 #define DAISY_CHAIN_COMMAND_MASK (0xFA)
davide.aliprandi@st.com 4:f48e8d87553e 119
davide.aliprandi@st.com 4:f48e8d87553e 120 /// powerSTEP01 max absolute position
davide.aliprandi@st.com 4:f48e8d87553e 121 #define POWERSTEP01_MAX_POSITION (int32_t)(0x001FFFFF)
davide.aliprandi@st.com 4:f48e8d87553e 122
davide.aliprandi@st.com 4:f48e8d87553e 123 /// powerSTEP01 min absolute position
davide.aliprandi@st.com 4:f48e8d87553e 124 #define POWERSTEP01_MIN_POSITION (int32_t)(0xFFE00000)
davide.aliprandi@st.com 4:f48e8d87553e 125
davide.aliprandi@st.com 4:f48e8d87553e 126 /// powerSTEP01 error base number
davide.aliprandi@st.com 4:f48e8d87553e 127 #define POWERSTEP01_ERROR_BASE (0xB000)
davide.aliprandi@st.com 4:f48e8d87553e 128
davide.aliprandi@st.com 4:f48e8d87553e 129 /// powerSTEP01 acceleration and deceleration max value
davide.aliprandi@st.com 4:f48e8d87553e 130 #define POWERSTEP01_ACC_DEC_MAX_VALUE (float)(59590)
davide.aliprandi@st.com 4:f48e8d87553e 131 /// powerSTEP01 max speed max value
davide.aliprandi@st.com 4:f48e8d87553e 132 #define POWERSTEP01_MAX_SPEED_MAX_VALUE (float)(15610)
davide.aliprandi@st.com 4:f48e8d87553e 133 /// powerSTEP01 min speed max value
davide.aliprandi@st.com 4:f48e8d87553e 134 #define POWERSTEP01_MIN_SPEED_MAX_VALUE (float)(976.3)
davide.aliprandi@st.com 4:f48e8d87553e 135 /// powerSTEP01 full step speed max value
davide.aliprandi@st.com 4:f48e8d87553e 136 #define POWERSTEP01_FS_SPD_MAX_VALUE (float)(15625)
davide.aliprandi@st.com 4:f48e8d87553e 137 /// powerSTEP01 intersect speed max value
davide.aliprandi@st.com 4:f48e8d87553e 138 #define POWERSTEP01_INT_SPD_MAX_VALUE (float)(976.5)
davide.aliprandi@st.com 4:f48e8d87553e 139 /// powerSTEP01 thermal compensation max value
davide.aliprandi@st.com 4:f48e8d87553e 140 #define POWERSTEP01_K_THERM_MAX_VALUE (float)(1.46875)
davide.aliprandi@st.com 4:f48e8d87553e 141 /// powerSTEP01 thermal compensation min value
davide.aliprandi@st.com 4:f48e8d87553e 142 #define POWERSTEP01_K_THERM_MIN_VALUE (float)(1)
davide.aliprandi@st.com 4:f48e8d87553e 143 /// powerSTEP01 thermal compensation max value
davide.aliprandi@st.com 4:f48e8d87553e 144 #define POWERSTEP01_STALL_OCD_TH_MAX_VALUE (float)(1000)
davide.aliprandi@st.com 4:f48e8d87553e 145 /// powerSTEP01 thermal compensation max value
davide.aliprandi@st.com 4:f48e8d87553e 146 #define POWERSTEP01_K_THERM_MAX_VALUE (float)(1.46875)
davide.aliprandi@st.com 4:f48e8d87553e 147 /// powerSTEP01 voltage amplitude regulation max value
davide.aliprandi@st.com 4:f48e8d87553e 148 #define POWERSTEP01_KVAL_MAX_VALUE (float)(255/256)
davide.aliprandi@st.com 4:f48e8d87553e 149 /// powerSTEP01 BEMF compensation curve slope max value
davide.aliprandi@st.com 4:f48e8d87553e 150 #define POWERSTEP01_SLP_MAX_VALUE (float)(0.4)
davide.aliprandi@st.com 4:f48e8d87553e 151 /// powerSTEP01 torque regulation DAC reference voltage max value
davide.aliprandi@st.com 4:f48e8d87553e 152 #define POWERSTEP01_TVAL_MAX_VALUE (float)(1000)
davide.aliprandi@st.com 4:f48e8d87553e 153 /// powerSTEP01 minimum off and on time max value
davide.aliprandi@st.com 4:f48e8d87553e 154 #define POWERSTEP01_TOFF_TON_MIN_MAX_VALUE (float)(64)
davide.aliprandi@st.com 4:f48e8d87553e 155
davide.aliprandi@st.com 4:f48e8d87553e 156 ///Shift of the low speed optimization bit in MIN_SPEED register
davide.aliprandi@st.com 4:f48e8d87553e 157 #define POWERSTEP01_LSPD_OPT_SHIFT (12)
davide.aliprandi@st.com 4:f48e8d87553e 158 ///Shift of the boost mode bit in FS_SPD register
davide.aliprandi@st.com 4:f48e8d87553e 159 #define POWERSTEP01_BOOST_MODE_SHIFT (10)
davide.aliprandi@st.com 4:f48e8d87553e 160 ///Maximum fast decay time (TOFF_FAST) unit
davide.aliprandi@st.com 4:f48e8d87553e 161 #define POWERSTEP01_TOFF_FAST_UNIT_US (2)
davide.aliprandi@st.com 4:f48e8d87553e 162 ///Shift of the maximum fast decay time (TOFF_FAST) in T_FAST register
davide.aliprandi@st.com 4:f48e8d87553e 163 #define POWERSTEP01_TOFF_FAST_SHIFT (4)
davide.aliprandi@st.com 4:f48e8d87553e 164 ///Maximum fall step time (FAST_STEP) unit
davide.aliprandi@st.com 4:f48e8d87553e 165 #define POWERSTEP01_FAST_STEP_UNIT_US (2)
davide.aliprandi@st.com 4:f48e8d87553e 166 ///Shift of the maximum fall step time (FAST_STEP) in T_FAST register
davide.aliprandi@st.com 4:f48e8d87553e 167 #define POWERSTEP01_FAST_STEP_SHIFT (0)
davide.aliprandi@st.com 4:f48e8d87553e 168 ///Duration unit of constant current phase during gate turn-on and turn-off (TCC)
davide.aliprandi@st.com 4:f48e8d87553e 169 #define POWERSTEP01_TCC_UNIT_NS (125)
davide.aliprandi@st.com 4:f48e8d87553e 170 ///Shift of TCC field in GATECFG1 register
davide.aliprandi@st.com 4:f48e8d87553e 171 #define POWERSTEP01_TCC_SHIFT (0)
davide.aliprandi@st.com 4:f48e8d87553e 172 ///Shift of IGATE field in GATECFG1 register
davide.aliprandi@st.com 4:f48e8d87553e 173 #define POWERSTEP01_IGATE_SHIFT (5)
davide.aliprandi@st.com 4:f48e8d87553e 174 ///Shift of TBOOST field in GATECFG1 register
davide.aliprandi@st.com 4:f48e8d87553e 175 #define POWERSTEP01_TBOOST_SHIFT (8)
davide.aliprandi@st.com 4:f48e8d87553e 176 ///Duration unit of the blanking of the current sensing comparators (TBLANK)
davide.aliprandi@st.com 4:f48e8d87553e 177 #define POWERSTEP01_TBLANK_UNIT_NS (125)
davide.aliprandi@st.com 4:f48e8d87553e 178 ///Shift of TBLANK field in GATECFG2 register
davide.aliprandi@st.com 4:f48e8d87553e 179 #define POWERSTEP01_TBLANK_SHIFT (5)
davide.aliprandi@st.com 4:f48e8d87553e 180 ///Deadtime duration unit between gate turn-off and opposite gate turn-on (TDT)
davide.aliprandi@st.com 4:f48e8d87553e 181 #define POWERSTEP01_TDT_UNIT_NS (125)
davide.aliprandi@st.com 4:f48e8d87553e 182 ///Shift of TDT field in GATECFG2 register
davide.aliprandi@st.com 4:f48e8d87553e 183 #define POWERSTEP01_TDT_SHIFT (0)
davide.aliprandi@st.com 4:f48e8d87553e 184 ///Shift of F_PWM_INT field in CONFIG register for voltage mode
davide.aliprandi@st.com 4:f48e8d87553e 185 #define POWERSTEP01_CONFIG_PWM_DIV_SHIFT (13)
davide.aliprandi@st.com 4:f48e8d87553e 186 ///Shift of F_PWM_DEC field in CONFIG register for voltage mode
davide.aliprandi@st.com 4:f48e8d87553e 187 #define POWERSTEP01_CONFIG_PWM_MUL_SHIFT (10)
davide.aliprandi@st.com 4:f48e8d87553e 188 ///Target switching period (TSW) unit
davide.aliprandi@st.com 4:f48e8d87553e 189 #define POWERSTEP01_CONFIG_TSW_UNIT_US (4)
davide.aliprandi@st.com 4:f48e8d87553e 190 ///Shift of TSW field in CONFIG register for current mode
davide.aliprandi@st.com 4:f48e8d87553e 191 #define POWERSTEP01_CONFIG_TSW_SHIFT (10)
davide.aliprandi@st.com 4:f48e8d87553e 192 ///Shift of MOT_STATUS field in STATUS register
davide.aliprandi@st.com 4:f48e8d87553e 193 #define POWERSTEP01_STATUS_MOT_STATUS_SHIFT (5)
davide.aliprandi@st.com 4:f48e8d87553e 194 /**
davide.aliprandi@st.com 4:f48e8d87553e 195 * @}
davide.aliprandi@st.com 4:f48e8d87553e 196 */
davide.aliprandi@st.com 4:f48e8d87553e 197
davide.aliprandi@st.com 4:f48e8d87553e 198 /* Types ---------------------------------------------------------------------*/
davide.aliprandi@st.com 4:f48e8d87553e 199
davide.aliprandi@st.com 4:f48e8d87553e 200 /** @defgroup Powerstep01_Exported_Types Powerstep01 Exported Types
davide.aliprandi@st.com 4:f48e8d87553e 201 * @{
davide.aliprandi@st.com 4:f48e8d87553e 202 */
davide.aliprandi@st.com 4:f48e8d87553e 203 /// masks for ABS_POS register of PowerStep01
davide.aliprandi@st.com 4:f48e8d87553e 204 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 205 POWERSTEP01_ABS_POS_VALUE_MASK = ((uint32_t)0x003FFFFF),
davide.aliprandi@st.com 4:f48e8d87553e 206 POWERSTEP01_ABS_POS_SIGN_BIT_MASK = ((uint32_t)0x00200000)
davide.aliprandi@st.com 4:f48e8d87553e 207 } powerstep01_AbsPosMasks_t;
davide.aliprandi@st.com 4:f48e8d87553e 208
davide.aliprandi@st.com 4:f48e8d87553e 209 /// masks for EL_POS register of PowerStep01
davide.aliprandi@st.com 4:f48e8d87553e 210 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 211 POWERSTEP01_ELPOS_STEP_MASK = ((uint16_t)0x180),
davide.aliprandi@st.com 4:f48e8d87553e 212 POWERSTEP01_ELPOS_MICROSTEP_MASK = ((uint16_t)0x07F)
davide.aliprandi@st.com 4:f48e8d87553e 213 } powerstep01_ElPosMasks_t;
davide.aliprandi@st.com 4:f48e8d87553e 214
davide.aliprandi@st.com 4:f48e8d87553e 215 /// masks for MIN_SPEED register of PowerStep01
davide.aliprandi@st.com 4:f48e8d87553e 216 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 217 POWERSTEP01_LSPD_OPT = ((uint16_t)((0x1)<<POWERSTEP01_LSPD_OPT_SHIFT)),
davide.aliprandi@st.com 4:f48e8d87553e 218 POWERSTEP01_MIN_SPEED_MASK = ((uint16_t)0x0FFF)
davide.aliprandi@st.com 4:f48e8d87553e 219 } powerstep01_MinSpeedMasks_t;
davide.aliprandi@st.com 4:f48e8d87553e 220
davide.aliprandi@st.com 4:f48e8d87553e 221 /// Low speed optimization (MIN_SPEED register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 222 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 223 POWERSTEP01_LSPD_OPT_OFF = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 224 POWERSTEP01_LSPD_OPT_ON = ((uint16_t)POWERSTEP01_LSPD_OPT)
davide.aliprandi@st.com 4:f48e8d87553e 225 } powerstep01_LspdOpt_t;
davide.aliprandi@st.com 4:f48e8d87553e 226
davide.aliprandi@st.com 4:f48e8d87553e 227 /// masks for FS_SPD register of PowerStep01
davide.aliprandi@st.com 4:f48e8d87553e 228 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 229 POWERSTEP01_BOOST_MODE = ((uint16_t)((0x1)<<POWERSTEP01_BOOST_MODE_SHIFT)),
davide.aliprandi@st.com 4:f48e8d87553e 230 POWERSTEP01_FS_SPD_MASK = ((uint16_t)0x03FF)
davide.aliprandi@st.com 4:f48e8d87553e 231 } powerstep01_FsSpdMasks_t;
davide.aliprandi@st.com 4:f48e8d87553e 232
davide.aliprandi@st.com 4:f48e8d87553e 233 /// Full step boost (FS_SPD register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 234 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 235 POWERSTEP01_BOOST_MODE_OFF = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 236 POWERSTEP01_BOOST_MODE_ON = ((uint16_t)POWERSTEP01_BOOST_MODE)
davide.aliprandi@st.com 4:f48e8d87553e 237 } powerstep01_BoostMode_t;
davide.aliprandi@st.com 4:f48e8d87553e 238
davide.aliprandi@st.com 4:f48e8d87553e 239 /// masks for T_FAST register of PowerStep01
davide.aliprandi@st.com 4:f48e8d87553e 240 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 241 POWERSTEP01_FAST_STEP_MASK = ((uint16_t) ((0xF)<<POWERSTEP01_FAST_STEP_SHIFT)),
davide.aliprandi@st.com 4:f48e8d87553e 242 POWERSTEP01_TOFF_FAST_MASK = ((uint16_t) ((0xF)<<POWERSTEP01_TOFF_FAST_SHIFT))
davide.aliprandi@st.com 4:f48e8d87553e 243 } powerstep01_TFastMasks_t;
davide.aliprandi@st.com 4:f48e8d87553e 244
davide.aliprandi@st.com 4:f48e8d87553e 245 /// Maximum fall step times (T_FAST register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 246 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 247 POWERSTEP01_FAST_STEP_2us = (((uint8_t)0x00)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 248 POWERSTEP01_FAST_STEP_4us = (((uint8_t)0x01)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 249 POWERSTEP01_FAST_STEP_6us = (((uint8_t)0x02)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 250 POWERSTEP01_FAST_STEP_8us = (((uint8_t)0x03)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 251 POWERSTEP01_FAST_STEP_10us = (((uint8_t)0x04)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 252 POWERSTEP01_FAST_STEP_12us = (((uint8_t)0x05)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 253 POWERSTEP01_FAST_STEP_14us = (((uint8_t)0x06)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 254 POWERSTEP01_FAST_STEP_16us = (((uint8_t)0x07)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 255 POWERSTEP01_FAST_STEP_18us = (((uint8_t)0x08)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 256 POWERSTEP01_FAST_STEP_20us = (((uint8_t)0x09)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 257 POWERSTEP01_FAST_STEP_22us = (((uint8_t)0x0A)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 258 POWERSTEP01_FAST_STEP_24s = (((uint8_t)0x0B)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 259 POWERSTEP01_FAST_STEP_26us = (((uint8_t)0x0C)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 260 POWERSTEP01_FAST_STEP_28us = (((uint8_t)0x0D)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 261 POWERSTEP01_FAST_STEP_30us = (((uint8_t)0x0E)<<POWERSTEP01_FAST_STEP_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 262 POWERSTEP01_FAST_STEP_32us = (((uint8_t)0x0F)<<POWERSTEP01_FAST_STEP_SHIFT)
davide.aliprandi@st.com 4:f48e8d87553e 263 } powerstep01_FastStep_t;
davide.aliprandi@st.com 4:f48e8d87553e 264
davide.aliprandi@st.com 4:f48e8d87553e 265 /// Maximum fast decay times (T_FAST register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 266 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 267 POWERSTEP01_TOFF_FAST_2us = (((uint8_t)0x00)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 268 POWERSTEP01_TOFF_FAST_4us = (((uint8_t)0x01)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 269 POWERSTEP01_TOFF_FAST_6us = (((uint8_t)0x02)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 270 POWERSTEP01_TOFF_FAST_8us = (((uint8_t)0x03)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 271 POWERSTEP01_TOFF_FAST_10us = (((uint8_t)0x04)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 272 POWERSTEP01_TOFF_FAST_12us = (((uint8_t)0x05)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 273 POWERSTEP01_TOFF_FAST_14us = (((uint8_t)0x06)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 274 POWERSTEP01_TOFF_FAST_16us = (((uint8_t)0x07)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 275 POWERSTEP01_TOFF_FAST_18us = (((uint8_t)0x08)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 276 POWERSTEP01_TOFF_FAST_20us = (((uint8_t)0x09)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 277 POWERSTEP01_TOFF_FAST_22us = (((uint8_t)0x0A)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 278 POWERSTEP01_TOFF_FAST_24us = (((uint8_t)0x0B)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 279 POWERSTEP01_TOFF_FAST_26us = (((uint8_t)0x0C)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 280 POWERSTEP01_TOFF_FAST_28us = (((uint8_t)0x0D)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 281 POWERSTEP01_TOFF_FAST_30us = (((uint8_t)0x0E)<<POWERSTEP01_TOFF_FAST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 282 POWERSTEP01_TOFF_FAST_32us = (((uint8_t)0x0F)<<POWERSTEP01_TOFF_FAST_SHIFT)
davide.aliprandi@st.com 4:f48e8d87553e 283 } powerstep01_ToffFast_t;
davide.aliprandi@st.com 4:f48e8d87553e 284
davide.aliprandi@st.com 4:f48e8d87553e 285 /// Overcurrent threshold options (OCD register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 286 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 287 POWERSTEP01_OCD_TH_31_25mV = ((uint8_t)0x00),
davide.aliprandi@st.com 4:f48e8d87553e 288 POWERSTEP01_OCD_TH_62_5mV = ((uint8_t)0x01),
davide.aliprandi@st.com 4:f48e8d87553e 289 POWERSTEP01_OCD_TH_93_75mV = ((uint8_t)0x02),
davide.aliprandi@st.com 4:f48e8d87553e 290 POWERSTEP01_OCD_TH_125mV = ((uint8_t)0x03),
davide.aliprandi@st.com 4:f48e8d87553e 291 POWERSTEP01_OCD_TH_156_25mV = ((uint8_t)0x04),
davide.aliprandi@st.com 4:f48e8d87553e 292 POWERSTEP01_OCD_TH_187_50mV = ((uint8_t)0x05),
davide.aliprandi@st.com 4:f48e8d87553e 293 POWERSTEP01_OCD_TH_218_75mV = ((uint8_t)0x06),
davide.aliprandi@st.com 4:f48e8d87553e 294 POWERSTEP01_OCD_TH_250mV = ((uint8_t)0x07),
davide.aliprandi@st.com 4:f48e8d87553e 295 POWERSTEP01_OCD_TH_281_25mV = ((uint8_t)0x08),
davide.aliprandi@st.com 4:f48e8d87553e 296 POWERSTEP01_OCD_TH_312_5mV = ((uint8_t)0x09),
davide.aliprandi@st.com 4:f48e8d87553e 297 POWERSTEP01_OCD_TH_343_75mV = ((uint8_t)0x0A),
davide.aliprandi@st.com 4:f48e8d87553e 298 POWERSTEP01_OCD_TH_375mV = ((uint8_t)0x0B),
davide.aliprandi@st.com 4:f48e8d87553e 299 POWERSTEP01_OCD_TH_406_25mV = ((uint8_t)0x0C),
davide.aliprandi@st.com 4:f48e8d87553e 300 POWERSTEP01_OCD_TH_437_5mV = ((uint8_t)0x0D),
davide.aliprandi@st.com 4:f48e8d87553e 301 POWERSTEP01_OCD_TH_468_75mV = ((uint8_t)0x0E),
davide.aliprandi@st.com 4:f48e8d87553e 302 POWERSTEP01_OCD_TH_500mV = ((uint8_t)0x0F),
davide.aliprandi@st.com 4:f48e8d87553e 303 POWERSTEP01_OCD_TH_531_25mV = ((uint8_t)0x10),
davide.aliprandi@st.com 4:f48e8d87553e 304 POWERSTEP01_OCD_TH_562_5mV = ((uint8_t)0x11),
davide.aliprandi@st.com 4:f48e8d87553e 305 POWERSTEP01_OCD_TH_593_75mV = ((uint8_t)0x12),
davide.aliprandi@st.com 4:f48e8d87553e 306 POWERSTEP01_OCD_TH_625mV = ((uint8_t)0x13),
davide.aliprandi@st.com 4:f48e8d87553e 307 POWERSTEP01_OCD_TH_656_25mV = ((uint8_t)0x14),
davide.aliprandi@st.com 4:f48e8d87553e 308 POWERSTEP01_OCD_TH_687_5mV = ((uint8_t)0x15),
davide.aliprandi@st.com 4:f48e8d87553e 309 POWERSTEP01_OCD_TH_718_75mV = ((uint8_t)0x16),
davide.aliprandi@st.com 4:f48e8d87553e 310 POWERSTEP01_OCD_TH_750mV = ((uint8_t)0x17),
davide.aliprandi@st.com 4:f48e8d87553e 311 POWERSTEP01_OCD_TH_781_25mV = ((uint8_t)0x18),
davide.aliprandi@st.com 4:f48e8d87553e 312 POWERSTEP01_OCD_TH_812_5mV = ((uint8_t)0x19),
davide.aliprandi@st.com 4:f48e8d87553e 313 POWERSTEP01_OCD_TH_843_75mV = ((uint8_t)0x1A),
davide.aliprandi@st.com 4:f48e8d87553e 314 POWERSTEP01_OCD_TH_875mV = ((uint8_t)0x1B),
davide.aliprandi@st.com 4:f48e8d87553e 315 POWERSTEP01_OCD_TH_906_25mV = ((uint8_t)0x1C),
davide.aliprandi@st.com 4:f48e8d87553e 316 POWERSTEP01_OCD_TH_937_75mV = ((uint8_t)0x1D),
davide.aliprandi@st.com 4:f48e8d87553e 317 POWERSTEP01_OCD_TH_968_75mV = ((uint8_t)0x1E),
davide.aliprandi@st.com 4:f48e8d87553e 318 POWERSTEP01_OCD_TH_1V = ((uint8_t)0x1F)
davide.aliprandi@st.com 4:f48e8d87553e 319 } powerstep01_OcdTh_t;
davide.aliprandi@st.com 4:f48e8d87553e 320
davide.aliprandi@st.com 4:f48e8d87553e 321 /// masks for STEP_MODE register of PowerStep01
davide.aliprandi@st.com 4:f48e8d87553e 322 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 323 POWERSTEP01_STEP_MODE_STEP_SEL = ((uint8_t)0x07),
davide.aliprandi@st.com 4:f48e8d87553e 324 POWERSTEP01_STEP_MODE_CM_VM = ((uint8_t)0x08),
davide.aliprandi@st.com 4:f48e8d87553e 325 POWERSTEP01_STEP_MODE_SYNC_SEL = ((uint8_t)0x70),
davide.aliprandi@st.com 4:f48e8d87553e 326 POWERSTEP01_STEP_MODE_SYNC_EN = ((uint8_t)0x80)
davide.aliprandi@st.com 4:f48e8d87553e 327 } powerstep01_StepModeMasks_t;
davide.aliprandi@st.com 4:f48e8d87553e 328
davide.aliprandi@st.com 4:f48e8d87553e 329 /// Voltage or Current mode selection (CM_VM field of STEP_MODE register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 330 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 331 POWERSTEP01_CM_VM_VOLTAGE = ((uint8_t)0x00),
davide.aliprandi@st.com 4:f48e8d87553e 332 POWERSTEP01_CM_VM_CURRENT = ((uint8_t)0x08)
davide.aliprandi@st.com 4:f48e8d87553e 333 } powerstep01_CmVm_t;
davide.aliprandi@st.com 4:f48e8d87553e 334
davide.aliprandi@st.com 4:f48e8d87553e 335 /// Stepping options (field STEP_SEL of STEP_MODE register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 336 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 337 POWERSTEP01_STEP_SEL_1 = ((uint8_t)0x00),
davide.aliprandi@st.com 4:f48e8d87553e 338 POWERSTEP01_STEP_SEL_1_2 = ((uint8_t)0x01),
davide.aliprandi@st.com 4:f48e8d87553e 339 POWERSTEP01_STEP_SEL_1_4 = ((uint8_t)0x02),
davide.aliprandi@st.com 4:f48e8d87553e 340 POWERSTEP01_STEP_SEL_1_8 = ((uint8_t)0x03),
davide.aliprandi@st.com 4:f48e8d87553e 341 POWERSTEP01_STEP_SEL_1_16 = ((uint8_t)0x04),
davide.aliprandi@st.com 4:f48e8d87553e 342 POWERSTEP01_STEP_SEL_1_32 = ((uint8_t)0x05),
davide.aliprandi@st.com 4:f48e8d87553e 343 POWERSTEP01_STEP_SEL_1_64 = ((uint8_t)0x06),
davide.aliprandi@st.com 4:f48e8d87553e 344 POWERSTEP01_STEP_SEL_1_128 = ((uint8_t)0x07)
davide.aliprandi@st.com 4:f48e8d87553e 345 } powerstep01_StepSel_t;
davide.aliprandi@st.com 4:f48e8d87553e 346
davide.aliprandi@st.com 4:f48e8d87553e 347 /// Powerstep01 Sync Output frequency enabling bitw
davide.aliprandi@st.com 4:f48e8d87553e 348 #define POWERSTEP01_SYNC_EN ((0x1) << 7)
davide.aliprandi@st.com 4:f48e8d87553e 349
davide.aliprandi@st.com 4:f48e8d87553e 350 /// SYNC_SEL options (STEP_MODE register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 351 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 352 POWERSTEP01_SYNC_SEL_DISABLED = ((uint8_t)0x00),
davide.aliprandi@st.com 4:f48e8d87553e 353 POWERSTEP01_SYNC_SEL_1_2 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x00)),
davide.aliprandi@st.com 4:f48e8d87553e 354 POWERSTEP01_SYNC_SEL_1 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x10)),
davide.aliprandi@st.com 4:f48e8d87553e 355 POWERSTEP01_SYNC_SEL_2 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x20)),
davide.aliprandi@st.com 4:f48e8d87553e 356 POWERSTEP01_SYNC_SEL_4 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x30)),
davide.aliprandi@st.com 4:f48e8d87553e 357 POWERSTEP01_SYNC_SEL_8 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x40)),
davide.aliprandi@st.com 4:f48e8d87553e 358 POWERSTEP01_SYNC_SEL_16 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x50)),
davide.aliprandi@st.com 4:f48e8d87553e 359 POWERSTEP01_SYNC_SEL_32 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x60)),
davide.aliprandi@st.com 4:f48e8d87553e 360 POWERSTEP01_SYNC_SEL_64 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x70))
davide.aliprandi@st.com 4:f48e8d87553e 361 } powerstep01_SyncSel_t;
davide.aliprandi@st.com 4:f48e8d87553e 362
davide.aliprandi@st.com 4:f48e8d87553e 363 /// Alarms conditions (ALARM_EN register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 364 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 365 POWERSTEP01_ALARM_EN_OVERCURRENT = ((uint8_t)0x01),
davide.aliprandi@st.com 4:f48e8d87553e 366 POWERSTEP01_ALARM_EN_THERMAL_SHUTDOWN = ((uint8_t)0x02),
davide.aliprandi@st.com 4:f48e8d87553e 367 POWERSTEP01_ALARM_EN_THERMAL_WARNING = ((uint8_t)0x04),
davide.aliprandi@st.com 4:f48e8d87553e 368 POWERSTEP01_ALARM_EN_UVLO = ((uint8_t)0x08),
davide.aliprandi@st.com 4:f48e8d87553e 369 POWERSTEP01_ALARM_EN_ADC_UVLO = ((uint8_t)0x10),
davide.aliprandi@st.com 4:f48e8d87553e 370 POWERSTEP01_ALARM_EN_STALL_DETECTION = ((uint8_t)0x20),
davide.aliprandi@st.com 4:f48e8d87553e 371 POWERSTEP01_ALARM_EN_SW_TURN_ON = ((uint8_t)0x40),
davide.aliprandi@st.com 4:f48e8d87553e 372 POWERSTEP01_ALARM_EN_WRONG_NPERF_CMD = ((uint8_t)0x80)
davide.aliprandi@st.com 4:f48e8d87553e 373 } powerstep01_AlarmEn_t;
davide.aliprandi@st.com 4:f48e8d87553e 374
davide.aliprandi@st.com 4:f48e8d87553e 375
davide.aliprandi@st.com 4:f48e8d87553e 376 /// masks for GATECFG1 register of PowerStep01
davide.aliprandi@st.com 4:f48e8d87553e 377 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 378 POWERSTEP01_GATECFG1_TCC_MASK = ((uint16_t)0x001F),
davide.aliprandi@st.com 4:f48e8d87553e 379 POWERSTEP01_GATECFG1_IGATE_MASK = ((uint16_t)0x00E0),
davide.aliprandi@st.com 4:f48e8d87553e 380 POWERSTEP01_GATECFG1_TBOOST_MASK = ((uint16_t)0x0700),
davide.aliprandi@st.com 4:f48e8d87553e 381 POWERSTEP01_GATECFG1_WD_EN = ((uint16_t)0x0800)
davide.aliprandi@st.com 4:f48e8d87553e 382 } powerstep01_GateCfg1Masks_t;
davide.aliprandi@st.com 4:f48e8d87553e 383
davide.aliprandi@st.com 4:f48e8d87553e 384 /// Control current Time (field TCC of GATECFG1 register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 385 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 386 POWERSTEP01_TCC_125ns = (((uint8_t)0x00)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 387 POWERSTEP01_TCC_250ns = (((uint8_t)0x01)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 388 POWERSTEP01_TCC_375ns = (((uint8_t)0x02)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 389 POWERSTEP01_TCC_500ns = (((uint8_t)0x03)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 390 POWERSTEP01_TCC_625ns = (((uint8_t)0x04)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 391 POWERSTEP01_TCC_750ns = (((uint8_t)0x05)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 392 POWERSTEP01_TCC_875ns = (((uint8_t)0x06)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 393 POWERSTEP01_TCC_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 394 POWERSTEP01_TCC_1125ns = (((uint8_t)0x08)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 395 POWERSTEP01_TCC_1250ns = (((uint8_t)0x09)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 396 POWERSTEP01_TCC_1375ns = (((uint8_t)0x0A)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 397 POWERSTEP01_TCC_1500ns = (((uint8_t)0x0B)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 398 POWERSTEP01_TCC_1625ns = (((uint8_t)0x0C)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 399 POWERSTEP01_TCC_1750ns = (((uint8_t)0x0D)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 400 POWERSTEP01_TCC_1875ns = (((uint8_t)0x0E)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 401 POWERSTEP01_TCC_2000ns = (((uint8_t)0x0F)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 402 POWERSTEP01_TCC_2125ns = (((uint8_t)0x10)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 403 POWERSTEP01_TCC_2250ns = (((uint8_t)0x11)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 404 POWERSTEP01_TCC_2375ns = (((uint8_t)0x12)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 405 POWERSTEP01_TCC_2500ns = (((uint8_t)0x13)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 406 POWERSTEP01_TCC_2625ns = (((uint8_t)0x14)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 407 POWERSTEP01_TCC_2750ns = (((uint8_t)0x15)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 408 POWERSTEP01_TCC_2875ns = (((uint8_t)0x16)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 409 POWERSTEP01_TCC_3000ns = (((uint8_t)0x17)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 410 POWERSTEP01_TCC_3125ns = (((uint8_t)0x18)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 411 POWERSTEP01_TCC_3250ns = (((uint8_t)0x19)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 412 POWERSTEP01_TCC_3375ns = (((uint8_t)0x1A)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 413 POWERSTEP01_TCC_3500ns = (((uint8_t)0x1B)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 414 POWERSTEP01_TCC_3625ns = (((uint8_t)0x1C)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 415 POWERSTEP01_TCC_3750ns = (((uint8_t)0x1D)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 416 POWERSTEP01_TCC_3750ns_bis = (((uint8_t)0x1E)<<POWERSTEP01_TCC_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 417 POWERSTEP01_TCC_3750ns_ter = (((uint8_t)0x1F)<<POWERSTEP01_TCC_SHIFT)
davide.aliprandi@st.com 4:f48e8d87553e 418 } powerstep01_Tcc_t;
davide.aliprandi@st.com 4:f48e8d87553e 419
davide.aliprandi@st.com 4:f48e8d87553e 420 /// Igate options (GATECFG1 register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 421 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 422 POWERSTEP01_IGATE_4mA = (((uint8_t)0x00)<<POWERSTEP01_IGATE_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 423 POWERSTEP01_IGATE_4mA_Bis = (((uint8_t)0x01)<<POWERSTEP01_IGATE_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 424 POWERSTEP01_IGATE_8mA = (((uint8_t)0x02)<<POWERSTEP01_IGATE_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 425 POWERSTEP01_IGATE_16mA = (((uint8_t)0x03)<<POWERSTEP01_IGATE_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 426 POWERSTEP01_IGATE_24mA = (((uint8_t)0x04)<<POWERSTEP01_IGATE_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 427 POWERSTEP01_IGATE_32mA = (((uint8_t)0x05)<<POWERSTEP01_IGATE_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 428 POWERSTEP01_IGATE_64mA = (((uint8_t)0x06)<<POWERSTEP01_IGATE_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 429 POWERSTEP01_IGATE_96mA = (((uint8_t)0x07)<<POWERSTEP01_IGATE_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 430 } powerstep01_Igate_t;
davide.aliprandi@st.com 4:f48e8d87553e 431
davide.aliprandi@st.com 4:f48e8d87553e 432 /// Turn off boost time (TBOOST field of GATECFG1 register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 433 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 434 POWERSTEP01_TBOOST_0ns = (((uint8_t)0x00)<<POWERSTEP01_TBOOST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 435 POWERSTEP01_TBOOST_62_5__83_3__125ns = (((uint8_t)0x01)<<POWERSTEP01_TBOOST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 436 POWERSTEP01_TBOOST_125ns = (((uint8_t)0x02)<<POWERSTEP01_TBOOST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 437 POWERSTEP01_TBOOST_250ns = (((uint8_t)0x03)<<POWERSTEP01_TBOOST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 438 POWERSTEP01_TBOOST_375ns = (((uint8_t)0x04)<<POWERSTEP01_TBOOST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 439 POWERSTEP01_TBOOST_500ns = (((uint8_t)0x05)<<POWERSTEP01_TBOOST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 440 POWERSTEP01_TBOOST_750ns = (((uint8_t)0x06)<<POWERSTEP01_TBOOST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 441 POWERSTEP01_TBOOST_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TBOOST_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 442 } powerstep01_Tboost_t;
davide.aliprandi@st.com 4:f48e8d87553e 443
davide.aliprandi@st.com 4:f48e8d87553e 444 /// External clock watchdog (WD_EN field of GATECFG1 register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 445 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 446 POWERSTEP01_WD_EN_DISABLE = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 447 POWERSTEP01_WD_EN_ENABLE = ((uint16_t) ((0x1) << 11))
davide.aliprandi@st.com 4:f48e8d87553e 448 } powerstep01_WdEn_t;
davide.aliprandi@st.com 4:f48e8d87553e 449
davide.aliprandi@st.com 4:f48e8d87553e 450
davide.aliprandi@st.com 4:f48e8d87553e 451 /// masks for GATECFG2 register of PowerStep01
davide.aliprandi@st.com 4:f48e8d87553e 452 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 453 POWERSTEP01_GATECFG2_TDT = ((uint8_t)0x1F),
davide.aliprandi@st.com 4:f48e8d87553e 454 POWERSTEP01_GATECFG2_TBLANK = ((uint8_t)0xE0)
davide.aliprandi@st.com 4:f48e8d87553e 455 } powerstep01_GateCfg2Masks_t;
davide.aliprandi@st.com 4:f48e8d87553e 456
davide.aliprandi@st.com 4:f48e8d87553e 457 /// Blanking time (TBLANK field of GATECFG2 register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 458 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 459 POWERSTEP01_TBLANK_125ns = (((uint8_t)0x00)<<POWERSTEP01_TBLANK_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 460 POWERSTEP01_TBLANK_250ns = (((uint8_t)0x01)<<POWERSTEP01_TBLANK_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 461 POWERSTEP01_TBLANK_375ns = (((uint8_t)0x02)<<POWERSTEP01_TBLANK_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 462 POWERSTEP01_TBLANK_500ns = (((uint8_t)0x03)<<POWERSTEP01_TBLANK_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 463 POWERSTEP01_TBLANK_625ns = (((uint8_t)0x04)<<POWERSTEP01_TBLANK_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 464 POWERSTEP01_TBLANK_750ns = (((uint8_t)0x05)<<POWERSTEP01_TBLANK_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 465 POWERSTEP01_TBLANK_875ns = (((uint8_t)0x06)<<POWERSTEP01_TBLANK_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 466 POWERSTEP01_TBLANK_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TBLANK_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 467 } powerstep01_TBlank_t;
davide.aliprandi@st.com 4:f48e8d87553e 468
davide.aliprandi@st.com 4:f48e8d87553e 469 /// Dead time (TDT field of GATECFG2 register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 470 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 471 POWERSTEP01_TDT_125ns = (((uint8_t)0x00)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 472 POWERSTEP01_TDT_250ns = (((uint8_t)0x01)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 473 POWERSTEP01_TDT_375ns = (((uint8_t)0x02)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 474 POWERSTEP01_TDT_500ns = (((uint8_t)0x03)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 475 POWERSTEP01_TDT_625ns = (((uint8_t)0x04)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 476 POWERSTEP01_TDT_750ns = (((uint8_t)0x05)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 477 POWERSTEP01_TDT_875ns = (((uint8_t)0x06)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 478 POWERSTEP01_TDT_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 479 POWERSTEP01_TDT_1125ns = (((uint8_t)0x08)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 480 POWERSTEP01_TDT_1250ns = (((uint8_t)0x09)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 481 POWERSTEP01_TDT_1375ns = (((uint8_t)0x0A)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 482 POWERSTEP01_TDT_1500ns = (((uint8_t)0x0B)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 483 POWERSTEP01_TDT_1625ns = (((uint8_t)0x0C)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 484 POWERSTEP01_TDT_1750ns = (((uint8_t)0x0D)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 485 POWERSTEP01_TDT_1875ns = (((uint8_t)0x0E)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 486 POWERSTEP01_TDT_2000ns = (((uint8_t)0x0F)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 487 POWERSTEP01_TDT_2125ns = (((uint8_t)0x10)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 488 POWERSTEP01_TDT_2250ns = (((uint8_t)0x11)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 489 POWERSTEP01_TDT_2375ns = (((uint8_t)0x12)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 490 POWERSTEP01_TDT_2500ns = (((uint8_t)0x13)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 491 POWERSTEP01_TDT_2625ns = (((uint8_t)0x14)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 492 POWERSTEP01_TDT_2750ns = (((uint8_t)0x15)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 493 POWERSTEP01_TDT_2875ns = (((uint8_t)0x16)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 494 POWERSTEP01_TDT_3000ns = (((uint8_t)0x17)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 495 POWERSTEP01_TDT_3125ns = (((uint8_t)0x18)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 496 POWERSTEP01_TDT_3250ns = (((uint8_t)0x19)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 497 POWERSTEP01_TDT_3375ns = (((uint8_t)0x1A)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 498 POWERSTEP01_TDT_3500ns = (((uint8_t)0x1B)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 499 POWERSTEP01_TDT_3625ns = (((uint8_t)0x1C)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 500 POWERSTEP01_TDT_3750ns = (((uint8_t)0x1D)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 501 POWERSTEP01_TDT_3875ns = (((uint8_t)0x1E)<<POWERSTEP01_TDT_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 502 POWERSTEP01_TDT_4000ns = (((uint8_t)0x1F)<<POWERSTEP01_TDT_SHIFT)
davide.aliprandi@st.com 4:f48e8d87553e 503 } powerstep01_Tdt_t;
davide.aliprandi@st.com 4:f48e8d87553e 504
davide.aliprandi@st.com 4:f48e8d87553e 505 /// Masks for CONFIG register of Powerstep01
davide.aliprandi@st.com 4:f48e8d87553e 506 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 507 POWERSTEP01_CONFIG_OSC_SEL = ((uint16_t)0x0007),
davide.aliprandi@st.com 4:f48e8d87553e 508 POWERSTEP01_CONFIG_EXT_CLK = ((uint16_t)0x0008),
davide.aliprandi@st.com 4:f48e8d87553e 509 POWERSTEP01_CONFIG_SW_MODE = ((uint16_t)0x0010),
davide.aliprandi@st.com 4:f48e8d87553e 510 POWERSTEP01_CONFIG_OC_SD = ((uint16_t)0x0080),
davide.aliprandi@st.com 4:f48e8d87553e 511 POWERSTEP01_CONFIG_UVLOVAL = ((uint16_t)0x0100),
davide.aliprandi@st.com 4:f48e8d87553e 512 POWERSTEP01_CONFIG_VCCVAL = ((uint16_t)0x0200),
davide.aliprandi@st.com 4:f48e8d87553e 513 // Masks specific for voltage mode
davide.aliprandi@st.com 4:f48e8d87553e 514 POWERSTEP01_CONFIG_EN_VSCOMP = ((uint16_t)0x0020),
davide.aliprandi@st.com 4:f48e8d87553e 515 POWERSTEP01_CONFIG_F_PWM_DEC = ((uint16_t)0x1C00),
davide.aliprandi@st.com 4:f48e8d87553e 516 POWERSTEP01_CONFIG_F_PWM_INT = ((uint16_t)0xE000),
davide.aliprandi@st.com 4:f48e8d87553e 517 // Masks specific for current mode
davide.aliprandi@st.com 4:f48e8d87553e 518 POWERSTEP01_CONFIG_TSW = ((uint16_t)0x7C00),
davide.aliprandi@st.com 4:f48e8d87553e 519 POWERSTEP01_CONFIG_PRED_EN = ((uint16_t)0x8000)
davide.aliprandi@st.com 4:f48e8d87553e 520 } powerstep01_ConfigMasks_t;
davide.aliprandi@st.com 4:f48e8d87553e 521
davide.aliprandi@st.com 4:f48e8d87553e 522 /// Masks for CONFIG register of Powerstep01 (specific for current mode)
davide.aliprandi@st.com 4:f48e8d87553e 523 #define POWERSTEP01_CONFIG_EN_TQREG (POWERSTEP01_CONFIG_EN_VSCOMP)
davide.aliprandi@st.com 4:f48e8d87553e 524
davide.aliprandi@st.com 4:f48e8d87553e 525 /// Oscillator management (EXT_CLK and OSC_SEL fields of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 526 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 527 POWERSTEP01_CONFIG_INT_16MHZ = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 528 POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_2MHZ = ((uint16_t)0x0008),
davide.aliprandi@st.com 4:f48e8d87553e 529 POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_4MHZ = ((uint16_t)0x0009),
davide.aliprandi@st.com 4:f48e8d87553e 530 POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_8MHZ = ((uint16_t)0x000A),
davide.aliprandi@st.com 4:f48e8d87553e 531 POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_16MHZ = ((uint16_t)0x000B),
davide.aliprandi@st.com 4:f48e8d87553e 532 POWERSTEP01_CONFIG_EXT_8MHZ_XTAL_DRIVE = ((uint16_t)0x0004),
davide.aliprandi@st.com 4:f48e8d87553e 533 POWERSTEP01_CONFIG_EXT_16MHZ_XTAL_DRIVE = ((uint16_t)0x0005),
davide.aliprandi@st.com 4:f48e8d87553e 534 POWERSTEP01_CONFIG_EXT_24MHZ_XTAL_DRIVE = ((uint16_t)0x0006),
davide.aliprandi@st.com 4:f48e8d87553e 535 POWERSTEP01_CONFIG_EXT_32MHZ_XTAL_DRIVE = ((uint16_t)0x0007),
davide.aliprandi@st.com 4:f48e8d87553e 536 POWERSTEP01_CONFIG_EXT_8MHZ_OSCOUT_INVERT = ((uint16_t)0x000C),
davide.aliprandi@st.com 4:f48e8d87553e 537 POWERSTEP01_CONFIG_EXT_16MHZ_OSCOUT_INVERT = ((uint16_t)0x000D),
davide.aliprandi@st.com 4:f48e8d87553e 538 POWERSTEP01_CONFIG_EXT_24MHZ_OSCOUT_INVERT = ((uint16_t)0x000E),
davide.aliprandi@st.com 4:f48e8d87553e 539 POWERSTEP01_CONFIG_EXT_32MHZ_OSCOUT_INVERT = ((uint16_t)0x000F)
davide.aliprandi@st.com 4:f48e8d87553e 540 } powerstep01_ConfigOscMgmt_t;
davide.aliprandi@st.com 4:f48e8d87553e 541
davide.aliprandi@st.com 4:f48e8d87553e 542 /// Oscillator management (EXT_CLK and OSC_SEL fields of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 543 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 544 POWERSTEP01_CONFIG_SW_HARD_STOP = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 545 POWERSTEP01_CONFIG_SW_USER = ((uint16_t)0x0010)
davide.aliprandi@st.com 4:f48e8d87553e 546 } powerstep01_ConfigSwMode_t;
davide.aliprandi@st.com 4:f48e8d87553e 547
davide.aliprandi@st.com 4:f48e8d87553e 548 /// Voltage supply compensation enabling for voltage mode (EN_VSCOMP field of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 549 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 550 POWERSTEP01_CONFIG_VS_COMP_DISABLE = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 551 POWERSTEP01_CONFIG_VS_COMP_ENABLE = ((uint16_t)0x0020)
davide.aliprandi@st.com 4:f48e8d87553e 552 } powerstep01_ConfigEnVscomp_t;
davide.aliprandi@st.com 4:f48e8d87553e 553
davide.aliprandi@st.com 4:f48e8d87553e 554 /// External torque regulation enabling (EN_TQREG field of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 555 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 556 POWERSTEP01_CONFIG_TQ_REG_TVAL_USED = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 557 POWERSTEP01_CONFIG_TQ_REG_ADC_OUT = ((uint16_t)0x0020)
davide.aliprandi@st.com 4:f48e8d87553e 558 } powerstep01_ConfigEnTqReg_t;
davide.aliprandi@st.com 4:f48e8d87553e 559
davide.aliprandi@st.com 4:f48e8d87553e 560 /// Overcurrent shutdown (OC_SD field of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 561 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 562 POWERSTEP01_CONFIG_OC_SD_DISABLE = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 563 POWERSTEP01_CONFIG_OC_SD_ENABLE = ((uint16_t)0x0080)
davide.aliprandi@st.com 4:f48e8d87553e 564 } powerstep01_ConfigOcSd_t;
davide.aliprandi@st.com 4:f48e8d87553e 565
davide.aliprandi@st.com 4:f48e8d87553e 566 /// UVLO thresholds (UVLOVAL field of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 567 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 568 POWERSTEP01_CONFIG_UVLOVAL_LOW = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 569 POWERSTEP01_CONFIG_UVLOVAL_HIGH = ((uint16_t)0x0100),
davide.aliprandi@st.com 4:f48e8d87553e 570 } powerstep01_ConfigUvLoVal_t;
davide.aliprandi@st.com 4:f48e8d87553e 571
davide.aliprandi@st.com 4:f48e8d87553e 572 /// Vcc voltage (VCCVAL field of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 573 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 574 POWERSTEP01_CONFIG_VCCVAL_7_5V = ((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 575 POWERSTEP01_CONFIG_VCCVAL_15V = ((uint16_t)0x0200)
davide.aliprandi@st.com 4:f48e8d87553e 576 } powerstep01_ConfigVccVal_t;
davide.aliprandi@st.com 4:f48e8d87553e 577
davide.aliprandi@st.com 4:f48e8d87553e 578 /// PWM frequency division factor (F_PWM_INT field of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 579 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 580 POWERSTEP01_CONFIG_PWM_DIV_1 = (((uint16_t)0x00)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 581 POWERSTEP01_CONFIG_PWM_DIV_2 = (((uint16_t)0x01)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 582 POWERSTEP01_CONFIG_PWM_DIV_3 = (((uint16_t)0x02)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 583 POWERSTEP01_CONFIG_PWM_DIV_4 = (((uint16_t)0x03)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 584 POWERSTEP01_CONFIG_PWM_DIV_5 = (((uint16_t)0x04)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 585 POWERSTEP01_CONFIG_PWM_DIV_6 = (((uint16_t)0x05)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 586 POWERSTEP01_CONFIG_PWM_DIV_7 = (((uint16_t)0x06)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT)
davide.aliprandi@st.com 4:f48e8d87553e 587 } powerstep01_ConfigFPwmInt_t;
davide.aliprandi@st.com 4:f48e8d87553e 588
davide.aliprandi@st.com 4:f48e8d87553e 589 /// PWM frequency multiplication factor (F_PWM_DEC field of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 590 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 591 POWERSTEP01_CONFIG_PWM_MUL_0_625 = (((uint16_t)0x00)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 592 POWERSTEP01_CONFIG_PWM_MUL_0_75 = (((uint16_t)0x01)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 593 POWERSTEP01_CONFIG_PWM_MUL_0_875 = (((uint16_t)0x02)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 594 POWERSTEP01_CONFIG_PWM_MUL_1 = (((uint16_t)0x03)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 595 POWERSTEP01_CONFIG_PWM_MUL_1_25 = (((uint16_t)0x04)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 596 POWERSTEP01_CONFIG_PWM_MUL_1_5 = (((uint16_t)0x05)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 597 POWERSTEP01_CONFIG_PWM_MUL_1_75 = (((uint16_t)0x06)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 598 POWERSTEP01_CONFIG_PWM_MUL_2 = (((uint16_t)0x07)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT)
davide.aliprandi@st.com 4:f48e8d87553e 599 } powerstep01_ConfigFPwmDec_t;
davide.aliprandi@st.com 4:f48e8d87553e 600
davide.aliprandi@st.com 4:f48e8d87553e 601 /// Switching period (TSW field of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 602 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 603 POWERSTEP01_CONFIG_TSW_004us =(((uint16_t)0x01)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 604 POWERSTEP01_CONFIG_TSW_008us =(((uint16_t)0x02)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 605 POWERSTEP01_CONFIG_TSW_012us =(((uint16_t)0x03)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 606 POWERSTEP01_CONFIG_TSW_016us =(((uint16_t)0x04)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 607 POWERSTEP01_CONFIG_TSW_020us =(((uint16_t)0x05)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 608 POWERSTEP01_CONFIG_TSW_024us =(((uint16_t)0x06)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 609 POWERSTEP01_CONFIG_TSW_028us =(((uint16_t)0x07)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 610 POWERSTEP01_CONFIG_TSW_032us =(((uint16_t)0x08)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 611 POWERSTEP01_CONFIG_TSW_036us =(((uint16_t)0x09)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 612 POWERSTEP01_CONFIG_TSW_040us =(((uint16_t)0x0A)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 613 POWERSTEP01_CONFIG_TSW_044us =(((uint16_t)0x0B)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 614 POWERSTEP01_CONFIG_TSW_048us =(((uint16_t)0x0C)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 615 POWERSTEP01_CONFIG_TSW_052us =(((uint16_t)0x0D)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 616 POWERSTEP01_CONFIG_TSW_056us =(((uint16_t)0x0E)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 617 POWERSTEP01_CONFIG_TSW_060us =(((uint16_t)0x0F)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 618 POWERSTEP01_CONFIG_TSW_064us =(((uint16_t)0x10)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 619 POWERSTEP01_CONFIG_TSW_068us =(((uint16_t)0x11)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 620 POWERSTEP01_CONFIG_TSW_072us =(((uint16_t)0x12)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 621 POWERSTEP01_CONFIG_TSW_076us =(((uint16_t)0x13)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 622 POWERSTEP01_CONFIG_TSW_080us =(((uint16_t)0x14)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 623 POWERSTEP01_CONFIG_TSW_084us =(((uint16_t)0x15)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 624 POWERSTEP01_CONFIG_TSW_088us =(((uint16_t)0x16)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 625 POWERSTEP01_CONFIG_TSW_092us =(((uint16_t)0x17)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 626 POWERSTEP01_CONFIG_TSW_096us =(((uint16_t)0x18)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 627 POWERSTEP01_CONFIG_TSW_100us =(((uint16_t)0x19)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 628 POWERSTEP01_CONFIG_TSW_104us =(((uint16_t)0x1A)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 629 POWERSTEP01_CONFIG_TSW_108us =(((uint16_t)0x1B)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 630 POWERSTEP01_CONFIG_TSW_112us =(((uint16_t)0x1C)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 631 POWERSTEP01_CONFIG_TSW_116us =(((uint16_t)0x1D)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 632 POWERSTEP01_CONFIG_TSW_120us =(((uint16_t)0x1E)<<POWERSTEP01_CONFIG_TSW_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 633 POWERSTEP01_CONFIG_TSW_124us =(((uint16_t)0x1F)<<POWERSTEP01_CONFIG_TSW_SHIFT)
davide.aliprandi@st.com 4:f48e8d87553e 634 } powerstep01_ConfigTsw_t;
davide.aliprandi@st.com 4:f48e8d87553e 635
davide.aliprandi@st.com 4:f48e8d87553e 636 /// Voltage supply compensation enabling for current mode(EN_PRED field of CONFIG register of Powerstep01)
davide.aliprandi@st.com 4:f48e8d87553e 637 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 638 POWERSTEP01_CONFIG_PRED_DISABLE =((uint16_t)0x0000),
davide.aliprandi@st.com 4:f48e8d87553e 639 POWERSTEP01_CONFIG_PRED_ENABLE =((uint16_t)0x8000)
davide.aliprandi@st.com 4:f48e8d87553e 640 } powerstep01_ConfigPredEn_t;
davide.aliprandi@st.com 4:f48e8d87553e 641
davide.aliprandi@st.com 4:f48e8d87553e 642 /// Bit mask for STATUS Register of PowerStep01²
davide.aliprandi@st.com 4:f48e8d87553e 643 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 644 POWERSTEP01_STATUS_HIZ = (((uint16_t)0x0001)),
davide.aliprandi@st.com 4:f48e8d87553e 645 POWERSTEP01_STATUS_BUSY = (((uint16_t)0x0002)),
davide.aliprandi@st.com 4:f48e8d87553e 646 POWERSTEP01_STATUS_SW_F = (((uint16_t)0x0004)),
davide.aliprandi@st.com 4:f48e8d87553e 647 POWERSTEP01_STATUS_SW_EVN = (((uint16_t)0x0008)),
davide.aliprandi@st.com 4:f48e8d87553e 648 POWERSTEP01_STATUS_DIR = (((uint16_t)0x0010)),
davide.aliprandi@st.com 4:f48e8d87553e 649 POWERSTEP01_STATUS_MOT_STATUS = (((uint16_t)0x0060)),
davide.aliprandi@st.com 4:f48e8d87553e 650 POWERSTEP01_STATUS_CMD_ERROR = (((uint16_t)0x0080)),
davide.aliprandi@st.com 4:f48e8d87553e 651 POWERSTEP01_STATUS_STCK_MOD = (((uint16_t)0x0100)),
davide.aliprandi@st.com 4:f48e8d87553e 652 POWERSTEP01_STATUS_UVLO = (((uint16_t)0x0200)),
davide.aliprandi@st.com 4:f48e8d87553e 653 POWERSTEP01_STATUS_UVLO_ADC = (((uint16_t)0x0400)),
davide.aliprandi@st.com 4:f48e8d87553e 654 POWERSTEP01_STATUS_TH_STATUS = (((uint16_t)0x1800)),
davide.aliprandi@st.com 4:f48e8d87553e 655 POWERSTEP01_STATUS_OCD = (((uint16_t)0x2000)),
davide.aliprandi@st.com 4:f48e8d87553e 656 POWERSTEP01_STATUS_STALL_A = (((uint16_t)0x4000)),
davide.aliprandi@st.com 4:f48e8d87553e 657 POWERSTEP01_STATUS_STALL_B = (((uint16_t)0x8000))
davide.aliprandi@st.com 4:f48e8d87553e 658 } powerstep01_StatusMasks_t;
davide.aliprandi@st.com 4:f48e8d87553e 659
davide.aliprandi@st.com 4:f48e8d87553e 660 /// Motor state (MOT_STATUS filed of STATUS register of PowerStep01)
davide.aliprandi@st.com 4:f48e8d87553e 661 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 662 POWERSTEP01_STATUS_MOT_STATUS_STOPPED = (((uint16_t)0x0000)<<POWERSTEP01_STATUS_MOT_STATUS_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 663 POWERSTEP01_STATUS_MOT_STATUS_ACCELERATION = (((uint16_t)0x0001)<<POWERSTEP01_STATUS_MOT_STATUS_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 664 POWERSTEP01_STATUS_MOT_STATUS_DECELERATION = (((uint16_t)0x0002)<<POWERSTEP01_STATUS_MOT_STATUS_SHIFT),
davide.aliprandi@st.com 4:f48e8d87553e 665 POWERSTEP01_STATUS_MOT_STATUS_CONST_SPD = (((uint16_t)0x0003)<<POWERSTEP01_STATUS_MOT_STATUS_SHIFT)
davide.aliprandi@st.com 4:f48e8d87553e 666 } powerstep01_Status_t;
davide.aliprandi@st.com 4:f48e8d87553e 667
davide.aliprandi@st.com 4:f48e8d87553e 668 /// Powerstep01 internal register addresses
davide.aliprandi@st.com 4:f48e8d87553e 669 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 670 POWERSTEP01_ABS_POS = ((uint8_t)0x01),
davide.aliprandi@st.com 4:f48e8d87553e 671 POWERSTEP01_EL_POS = ((uint8_t)0x02),
davide.aliprandi@st.com 4:f48e8d87553e 672 POWERSTEP01_MARK = ((uint8_t)0x03),
davide.aliprandi@st.com 4:f48e8d87553e 673 POWERSTEP01_SPEED = ((uint8_t)0x04),
davide.aliprandi@st.com 4:f48e8d87553e 674 POWERSTEP01_ACC = ((uint8_t)0x05),
davide.aliprandi@st.com 4:f48e8d87553e 675 POWERSTEP01_DEC = ((uint8_t)0x06),
davide.aliprandi@st.com 4:f48e8d87553e 676 POWERSTEP01_MAX_SPEED = ((uint8_t)0x07),
davide.aliprandi@st.com 4:f48e8d87553e 677 POWERSTEP01_MIN_SPEED = ((uint8_t)0x08),
davide.aliprandi@st.com 4:f48e8d87553e 678 POWERSTEP01_FS_SPD = ((uint8_t)0x15),
davide.aliprandi@st.com 4:f48e8d87553e 679 POWERSTEP01_KVAL_HOLD = ((uint8_t)0x09),
davide.aliprandi@st.com 4:f48e8d87553e 680 POWERSTEP01_KVAL_RUN = ((uint8_t)0x0A),
davide.aliprandi@st.com 4:f48e8d87553e 681 POWERSTEP01_KVAL_ACC = ((uint8_t)0x0B),
davide.aliprandi@st.com 4:f48e8d87553e 682 POWERSTEP01_KVAL_DEC = ((uint8_t)0x0C),
davide.aliprandi@st.com 4:f48e8d87553e 683 POWERSTEP01_INT_SPD = ((uint8_t)0x0D),
davide.aliprandi@st.com 4:f48e8d87553e 684 POWERSTEP01_ST_SLP = ((uint8_t)0x0E),
davide.aliprandi@st.com 4:f48e8d87553e 685 POWERSTEP01_FN_SLP_ACC = ((uint8_t)0x0F),
davide.aliprandi@st.com 4:f48e8d87553e 686 POWERSTEP01_FN_SLP_DEC = ((uint8_t)0x10),
davide.aliprandi@st.com 4:f48e8d87553e 687 POWERSTEP01_K_THERM = ((uint8_t)0x11),
davide.aliprandi@st.com 4:f48e8d87553e 688 POWERSTEP01_ADC_OUT = ((uint8_t)0x12),
davide.aliprandi@st.com 4:f48e8d87553e 689 POWERSTEP01_OCD_TH = ((uint8_t)0x13),
davide.aliprandi@st.com 4:f48e8d87553e 690 POWERSTEP01_STALL_TH = ((uint8_t)0x14),
davide.aliprandi@st.com 4:f48e8d87553e 691 POWERSTEP01_STEP_MODE = ((uint8_t)0x16),
davide.aliprandi@st.com 4:f48e8d87553e 692 POWERSTEP01_ALARM_EN = ((uint8_t)0x17),
davide.aliprandi@st.com 4:f48e8d87553e 693 POWERSTEP01_GATECFG1 = ((uint8_t)0x18),
davide.aliprandi@st.com 4:f48e8d87553e 694 POWERSTEP01_GATECFG2 = ((uint8_t)0x19),
davide.aliprandi@st.com 4:f48e8d87553e 695 POWERSTEP01_CONFIG = ((uint8_t)0x1A),
davide.aliprandi@st.com 4:f48e8d87553e 696 POWERSTEP01_STATUS = ((uint8_t)0x1B)
davide.aliprandi@st.com 4:f48e8d87553e 697 } powerstep01_Registers_t;
davide.aliprandi@st.com 4:f48e8d87553e 698
davide.aliprandi@st.com 4:f48e8d87553e 699 /// Powerstep01 address of register TVAL_HOLD (Current mode only)
davide.aliprandi@st.com 4:f48e8d87553e 700 #define POWERSTEP01_TVAL_HOLD (POWERSTEP01_KVAL_HOLD )
davide.aliprandi@st.com 4:f48e8d87553e 701 /// Powerstep01 address of register TVAL_RUN (Current mode only)
davide.aliprandi@st.com 4:f48e8d87553e 702 #define POWERSTEP01_TVAL_RUN (POWERSTEP01_KVAL_RUN)
davide.aliprandi@st.com 4:f48e8d87553e 703 /// Powerstep01 address of register TVAL_HOLD (Current mode only)
davide.aliprandi@st.com 4:f48e8d87553e 704 #define POWERSTEP01_TVAL_ACC (POWERSTEP01_KVAL_ACC)
davide.aliprandi@st.com 4:f48e8d87553e 705 /// Powerstep01 address of register TVAL_DEC (Current mode only)
davide.aliprandi@st.com 4:f48e8d87553e 706 #define POWERSTEP01_TVAL_DEC (POWERSTEP01_KVAL_DEC)
davide.aliprandi@st.com 4:f48e8d87553e 707 /// Powerstep01 address of register T_FAST (Current mode only)
davide.aliprandi@st.com 4:f48e8d87553e 708 #define POWERSTEP01_T_FAST (POWERSTEP01_ST_SLP)
davide.aliprandi@st.com 4:f48e8d87553e 709 /// Powerstep01 address of register TON_MIN (Current mode only)
davide.aliprandi@st.com 4:f48e8d87553e 710 #define POWERSTEP01_TON_MIN (POWERSTEP01_FN_SLP_ACC)
davide.aliprandi@st.com 4:f48e8d87553e 711 /// Powerstep01 address of register TOFF_MIN (Current mode only)
davide.aliprandi@st.com 4:f48e8d87553e 712 #define POWERSTEP01_TOFF_MIN (POWERSTEP01_FN_SLP_DEC)
davide.aliprandi@st.com 4:f48e8d87553e 713
davide.aliprandi@st.com 4:f48e8d87553e 714 /// Powerstep01 application commands
davide.aliprandi@st.com 4:f48e8d87553e 715 typedef enum {
davide.aliprandi@st.com 4:f48e8d87553e 716 POWERSTEP01_NOP = ((uint8_t)0x00),
davide.aliprandi@st.com 4:f48e8d87553e 717 POWERSTEP01_SET_PARAM = ((uint8_t)0x00),
davide.aliprandi@st.com 4:f48e8d87553e 718 POWERSTEP01_GET_PARAM = ((uint8_t)0x20),
davide.aliprandi@st.com 4:f48e8d87553e 719 POWERSTEP01_RUN = ((uint8_t)0x50),
davide.aliprandi@st.com 4:f48e8d87553e 720 POWERSTEP01_STEP_CLOCK = ((uint8_t)0x58),
davide.aliprandi@st.com 4:f48e8d87553e 721 POWERSTEP01_MOVE = ((uint8_t)0x40),
davide.aliprandi@st.com 4:f48e8d87553e 722 POWERSTEP01_GO_TO = ((uint8_t)0x60),
davide.aliprandi@st.com 4:f48e8d87553e 723 POWERSTEP01_GO_TO_DIR = ((uint8_t)0x68),
davide.aliprandi@st.com 4:f48e8d87553e 724 POWERSTEP01_GO_UNTIL = ((uint8_t)0x82),
davide.aliprandi@st.com 4:f48e8d87553e 725 POWERSTEP01_GO_UNTIL_ACT_CPY = ((uint8_t)0x8A),
davide.aliprandi@st.com 4:f48e8d87553e 726 POWERSTEP01_RELEASE_SW = ((uint8_t)0x92),
davide.aliprandi@st.com 4:f48e8d87553e 727 POWERSTEP01_GO_HOME = ((uint8_t)0x70),
davide.aliprandi@st.com 4:f48e8d87553e 728 POWERSTEP01_GO_MARK = ((uint8_t)0x78),
davide.aliprandi@st.com 4:f48e8d87553e 729 POWERSTEP01_RESET_POS = ((uint8_t)0xD8),
davide.aliprandi@st.com 4:f48e8d87553e 730 POWERSTEP01_RESET_DEVICE = ((uint8_t)0xC0),
davide.aliprandi@st.com 4:f48e8d87553e 731 POWERSTEP01_SOFT_STOP = ((uint8_t)0xB0),
davide.aliprandi@st.com 4:f48e8d87553e 732 POWERSTEP01_HARD_STOP = ((uint8_t)0xB8),
davide.aliprandi@st.com 4:f48e8d87553e 733 POWERSTEP01_SOFT_HIZ = ((uint8_t)0xA0),
davide.aliprandi@st.com 4:f48e8d87553e 734 POWERSTEP01_HARD_HIZ = ((uint8_t)0xA8),
davide.aliprandi@st.com 4:f48e8d87553e 735 POWERSTEP01_GET_STATUS = ((uint8_t)0xD0),
davide.aliprandi@st.com 4:f48e8d87553e 736 POWERSTEP01_RESERVED_CMD1 = ((uint8_t)0xEB),
davide.aliprandi@st.com 4:f48e8d87553e 737 POWERSTEP01_RESERVED_CMD2 = ((uint8_t)0xF8)
davide.aliprandi@st.com 4:f48e8d87553e 738 } powerstep01_Commands_t;
davide.aliprandi@st.com 4:f48e8d87553e 739
davide.aliprandi@st.com 4:f48e8d87553e 740 /** @defgroup Motor_Driver_Initialization_Structure Motor Driver Initialization Structure
davide.aliprandi@st.com 4:f48e8d87553e 741 * @{
davide.aliprandi@st.com 4:f48e8d87553e 742 */
davide.aliprandi@st.com 4:f48e8d87553e 743 /* ACTION --------------------------------------------------------------------*
davide.aliprandi@st.com 4:f48e8d87553e 744 * Declare here the component's initialization structure, if any, one *
davide.aliprandi@st.com 4:f48e8d87553e 745 * variable per line without initialization. *
davide.aliprandi@st.com 4:f48e8d87553e 746 * *
davide.aliprandi@st.com 4:f48e8d87553e 747 * Example: *
davide.aliprandi@st.com 4:f48e8d87553e 748 * typedef struct *
davide.aliprandi@st.com 4:f48e8d87553e 749 * { *
davide.aliprandi@st.com 4:f48e8d87553e 750 * int frequency; *
davide.aliprandi@st.com 4:f48e8d87553e 751 * int update_mode; *
davide.aliprandi@st.com 4:f48e8d87553e 752 * } COMPONENT_init_t; *
davide.aliprandi@st.com 4:f48e8d87553e 753 *----------------------------------------------------------------------------*/
davide.aliprandi@st.com 4:f48e8d87553e 754 ///Initialization parameters structure common to current and voltage modes
davide.aliprandi@st.com 4:f48e8d87553e 755 typedef struct
davide.aliprandi@st.com 4:f48e8d87553e 756 {
davide.aliprandi@st.com 4:f48e8d87553e 757 ///Current or voltage mode selection
davide.aliprandi@st.com 4:f48e8d87553e 758 powerstep01_CmVm_t cmVmSelection;
davide.aliprandi@st.com 4:f48e8d87553e 759 ///Acceleration
davide.aliprandi@st.com 4:f48e8d87553e 760 float acceleration;
davide.aliprandi@st.com 4:f48e8d87553e 761 ///Deceleration
davide.aliprandi@st.com 4:f48e8d87553e 762 float deceleration;
davide.aliprandi@st.com 4:f48e8d87553e 763 ///Maximum speed
davide.aliprandi@st.com 4:f48e8d87553e 764 float maxSpeed;
davide.aliprandi@st.com 4:f48e8d87553e 765 ///Minimum speed
davide.aliprandi@st.com 4:f48e8d87553e 766 float minSpeed;
davide.aliprandi@st.com 4:f48e8d87553e 767 ///Low speed optimization bit
davide.aliprandi@st.com 4:f48e8d87553e 768 powerstep01_LspdOpt_t lowSpeedOptimization;
davide.aliprandi@st.com 4:f48e8d87553e 769 ///Full step speed
davide.aliprandi@st.com 4:f48e8d87553e 770 float fullStepSpeed;
davide.aliprandi@st.com 4:f48e8d87553e 771 ///Boost mode bit
davide.aliprandi@st.com 4:f48e8d87553e 772 powerstep01_BoostMode_t boostMode;
davide.aliprandi@st.com 4:f48e8d87553e 773 ///Over current detection threshold
davide.aliprandi@st.com 4:f48e8d87553e 774 float ocdThreshold;
davide.aliprandi@st.com 4:f48e8d87553e 775 ///Step mode
davide.aliprandi@st.com 4:f48e8d87553e 776 motorStepMode_t stepMode;
davide.aliprandi@st.com 4:f48e8d87553e 777 ///Sync clock selection
davide.aliprandi@st.com 4:f48e8d87553e 778 powerstep01_SyncSel_t syncClockSelection;
davide.aliprandi@st.com 4:f48e8d87553e 779 ///Alarm selection
davide.aliprandi@st.com 4:f48e8d87553e 780 uint8_t alarmsSelection;
davide.aliprandi@st.com 4:f48e8d87553e 781 ///Sink or source current used by gate driving circuitry
davide.aliprandi@st.com 4:f48e8d87553e 782 powerstep01_Igate_t iGate;
davide.aliprandi@st.com 4:f48e8d87553e 783 ///Duration of the overboost phase during gate turn-off
davide.aliprandi@st.com 4:f48e8d87553e 784 powerstep01_Tboost_t tBoost;
davide.aliprandi@st.com 4:f48e8d87553e 785 ///Duration of constant current phase during gate turn-on and turn-off
davide.aliprandi@st.com 4:f48e8d87553e 786 powerstep01_Tcc_t tcc;
davide.aliprandi@st.com 4:f48e8d87553e 787 ///Clock source monitoring enable bit
davide.aliprandi@st.com 4:f48e8d87553e 788 powerstep01_WdEn_t wdEn;
davide.aliprandi@st.com 4:f48e8d87553e 789 ///Duration of the blanking of the current sensing comparators
davide.aliprandi@st.com 4:f48e8d87553e 790 powerstep01_TBlank_t tBlank;
davide.aliprandi@st.com 4:f48e8d87553e 791 ///Deadtime duration between gate turn-off and opposite gate turn-on
davide.aliprandi@st.com 4:f48e8d87553e 792 powerstep01_Tdt_t tdt;
davide.aliprandi@st.com 4:f48e8d87553e 793 } commonParameters_t;
davide.aliprandi@st.com 4:f48e8d87553e 794
davide.aliprandi@st.com 4:f48e8d87553e 795 ///Initialization parameters structure for voltage mode
davide.aliprandi@st.com 4:f48e8d87553e 796 typedef struct
davide.aliprandi@st.com 4:f48e8d87553e 797 {
davide.aliprandi@st.com 4:f48e8d87553e 798 ///Parameters common to current and voltage modes
davide.aliprandi@st.com 4:f48e8d87553e 799 commonParameters_t cp;
davide.aliprandi@st.com 4:f48e8d87553e 800 ///Voltage amplitude regulation when the motor is stopped
davide.aliprandi@st.com 4:f48e8d87553e 801 float kvalHold;
davide.aliprandi@st.com 4:f48e8d87553e 802 ///Voltage amplitude regulation when the motor is running at constant speed
davide.aliprandi@st.com 4:f48e8d87553e 803 float kvalRun;
davide.aliprandi@st.com 4:f48e8d87553e 804 ///Voltage amplitude regulation during motor acceleration
davide.aliprandi@st.com 4:f48e8d87553e 805 float kvalAcc;
davide.aliprandi@st.com 4:f48e8d87553e 806 ///Voltage amplitude regulation during motor deceleration
davide.aliprandi@st.com 4:f48e8d87553e 807 float kvalDec;
davide.aliprandi@st.com 4:f48e8d87553e 808 ///Speed value at which the BEMF compensation curve changes slope
davide.aliprandi@st.com 4:f48e8d87553e 809 float intersectSpeed;
davide.aliprandi@st.com 4:f48e8d87553e 810 ///BEMF compensation curve slope when speed is lower than intersect speed
davide.aliprandi@st.com 4:f48e8d87553e 811 float startSlope;
davide.aliprandi@st.com 4:f48e8d87553e 812 ///BEMF compensation curve slope when speed is greater than intersect speed during acceleration
davide.aliprandi@st.com 4:f48e8d87553e 813 float accelerationFinalSlope;
davide.aliprandi@st.com 4:f48e8d87553e 814 ///BEMF compensation curve slope when speed is greater than intersect speed during deceleration
davide.aliprandi@st.com 4:f48e8d87553e 815 float decelerationFinalSlope;
davide.aliprandi@st.com 4:f48e8d87553e 816 ///Winding resistance thermal drift compensation coefficient
davide.aliprandi@st.com 4:f48e8d87553e 817 float thermalCompensationFactor;
davide.aliprandi@st.com 4:f48e8d87553e 818 ///Stall detection threshold
davide.aliprandi@st.com 4:f48e8d87553e 819 float stallThreshold;
davide.aliprandi@st.com 4:f48e8d87553e 820 ///System clock source management
davide.aliprandi@st.com 4:f48e8d87553e 821 powerstep01_ConfigOscMgmt_t oscClkSel;
davide.aliprandi@st.com 4:f48e8d87553e 822 ///External switch to act as hard_stop interrupt or not
davide.aliprandi@st.com 4:f48e8d87553e 823 powerstep01_ConfigSwMode_t swMode;
davide.aliprandi@st.com 4:f48e8d87553e 824 ///Motor supply voltage compensation enable bit
davide.aliprandi@st.com 4:f48e8d87553e 825 powerstep01_ConfigEnVscomp_t enVsComp;
davide.aliprandi@st.com 4:f48e8d87553e 826 ///Overcurrent event causes or not the bridges to turn-off
davide.aliprandi@st.com 4:f48e8d87553e 827 powerstep01_ConfigOcSd_t ocSd;
davide.aliprandi@st.com 4:f48e8d87553e 828 ///UVLO protection thresholds
davide.aliprandi@st.com 4:f48e8d87553e 829 powerstep01_ConfigUvLoVal_t uvloVal;
davide.aliprandi@st.com 4:f48e8d87553e 830 ///Internal VCC regulator output voltage
davide.aliprandi@st.com 4:f48e8d87553e 831 powerstep01_ConfigVccVal_t vccVal;
davide.aliprandi@st.com 4:f48e8d87553e 832 ///Integer division factor of PWM frequency generation
davide.aliprandi@st.com 4:f48e8d87553e 833 powerstep01_ConfigFPwmInt_t fPwmInt;
davide.aliprandi@st.com 4:f48e8d87553e 834 ///Multiplication factor of PWM frequency generation
davide.aliprandi@st.com 4:f48e8d87553e 835 powerstep01_ConfigFPwmDec_t fPwmDec;
davide.aliprandi@st.com 4:f48e8d87553e 836 } powerstep01_VoltageMode_init_t;
davide.aliprandi@st.com 4:f48e8d87553e 837
davide.aliprandi@st.com 4:f48e8d87553e 838 ///Initialization parameters structure for current mode
davide.aliprandi@st.com 4:f48e8d87553e 839 typedef struct
davide.aliprandi@st.com 4:f48e8d87553e 840 {
davide.aliprandi@st.com 4:f48e8d87553e 841 ///Parameters common to current and voltage modes
davide.aliprandi@st.com 4:f48e8d87553e 842 commonParameters_t cp;
davide.aliprandi@st.com 4:f48e8d87553e 843 ///Torque regulation DAC reference voltage when motor is stopped
davide.aliprandi@st.com 4:f48e8d87553e 844 float tvalHold;
davide.aliprandi@st.com 4:f48e8d87553e 845 ///Torque regulation DAC reference voltage when motor is runnig at constant speed
davide.aliprandi@st.com 4:f48e8d87553e 846 float tvalRun;
davide.aliprandi@st.com 4:f48e8d87553e 847 ///Torque regulation DAC reference voltage during motor acceleration
davide.aliprandi@st.com 4:f48e8d87553e 848 float tvalAcc;
davide.aliprandi@st.com 4:f48e8d87553e 849 ///Torque regulation DAC reference voltage during motor deceleration
davide.aliprandi@st.com 4:f48e8d87553e 850 float tvalDec;
davide.aliprandi@st.com 4:f48e8d87553e 851 ///Maximum fast decay time
davide.aliprandi@st.com 4:f48e8d87553e 852 powerstep01_ToffFast_t toffFast;
davide.aliprandi@st.com 4:f48e8d87553e 853 ///Maximum fall step time
davide.aliprandi@st.com 4:f48e8d87553e 854 powerstep01_FastStep_t fastStep;
davide.aliprandi@st.com 4:f48e8d87553e 855 ///Minimum on-time
davide.aliprandi@st.com 4:f48e8d87553e 856 float tonMin;
davide.aliprandi@st.com 4:f48e8d87553e 857 ///Minimum off-time
davide.aliprandi@st.com 4:f48e8d87553e 858 float toffMin;
davide.aliprandi@st.com 4:f48e8d87553e 859 ///System clock source management
davide.aliprandi@st.com 4:f48e8d87553e 860 powerstep01_ConfigOscMgmt_t oscClkSel;
davide.aliprandi@st.com 4:f48e8d87553e 861 ///External switch to act as hard_stop interrupt or not
davide.aliprandi@st.com 4:f48e8d87553e 862 powerstep01_ConfigSwMode_t swMode;
davide.aliprandi@st.com 4:f48e8d87553e 863 ///Peak current is adjusted through the ADCIN input or not
davide.aliprandi@st.com 4:f48e8d87553e 864 powerstep01_ConfigEnTqReg_t tqReg;
davide.aliprandi@st.com 4:f48e8d87553e 865 ///Motor supply voltage compensation enable bit
davide.aliprandi@st.com 4:f48e8d87553e 866 powerstep01_ConfigEnVscomp_t enVsComp;
davide.aliprandi@st.com 4:f48e8d87553e 867 ///Overcurrent event causes or not the bridges to turn-off
davide.aliprandi@st.com 4:f48e8d87553e 868 powerstep01_ConfigOcSd_t ocSd;
davide.aliprandi@st.com 4:f48e8d87553e 869 ///UVLO protection thresholds
davide.aliprandi@st.com 4:f48e8d87553e 870 powerstep01_ConfigUvLoVal_t uvloVal;
davide.aliprandi@st.com 4:f48e8d87553e 871 ///Internal VCC regulator output voltage
davide.aliprandi@st.com 4:f48e8d87553e 872 powerstep01_ConfigVccVal_t vccVal;
davide.aliprandi@st.com 4:f48e8d87553e 873 ///target switching period
davide.aliprandi@st.com 4:f48e8d87553e 874 powerstep01_ConfigTsw_t tsw;
davide.aliprandi@st.com 4:f48e8d87553e 875 ///predictive current control method enable bit
davide.aliprandi@st.com 4:f48e8d87553e 876 powerstep01_ConfigPredEn_t predEn;
davide.aliprandi@st.com 4:f48e8d87553e 877
davide.aliprandi@st.com 4:f48e8d87553e 878 } powerstep01_CurrentMode_init_t;
davide.aliprandi@st.com 4:f48e8d87553e 879
davide.aliprandi@st.com 4:f48e8d87553e 880 ///Union of current and volatge modes initialization parameters structures
davide.aliprandi@st.com 4:f48e8d87553e 881 typedef union powerstep01_init_u powerstep01_init_u_t;
davide.aliprandi@st.com 4:f48e8d87553e 882 union powerstep01_init_u
davide.aliprandi@st.com 4:f48e8d87553e 883 {
davide.aliprandi@st.com 4:f48e8d87553e 884 ///Initialization parameters structure for current mode
davide.aliprandi@st.com 4:f48e8d87553e 885 powerstep01_CurrentMode_init_t cm;
davide.aliprandi@st.com 4:f48e8d87553e 886 ///Initialization parameters structure for voltage mode
davide.aliprandi@st.com 4:f48e8d87553e 887 powerstep01_VoltageMode_init_t vm;
davide.aliprandi@st.com 4:f48e8d87553e 888 };
davide.aliprandi@st.com 4:f48e8d87553e 889 /**
davide.aliprandi@st.com 4:f48e8d87553e 890 * @}
davide.aliprandi@st.com 4:f48e8d87553e 891 */
davide.aliprandi@st.com 4:f48e8d87553e 892
davide.aliprandi@st.com 4:f48e8d87553e 893 /**
davide.aliprandi@st.com 4:f48e8d87553e 894 * @brief Powerstep01 driver data structure definition.
davide.aliprandi@st.com 4:f48e8d87553e 895 */
davide.aliprandi@st.com 4:f48e8d87553e 896 /* ACTION --------------------------------------------------------------------*
davide.aliprandi@st.com 4:f48e8d87553e 897 * Declare here the structure of component's data, if any, one variable per *
davide.aliprandi@st.com 4:f48e8d87553e 898 * line without initialization. *
davide.aliprandi@st.com 4:f48e8d87553e 899 * *
davide.aliprandi@st.com 4:f48e8d87553e 900 * Example: *
davide.aliprandi@st.com 4:f48e8d87553e 901 * typedef struct *
davide.aliprandi@st.com 4:f48e8d87553e 902 * { *
davide.aliprandi@st.com 4:f48e8d87553e 903 * int T0_out; *
davide.aliprandi@st.com 4:f48e8d87553e 904 * int T1_out; *
davide.aliprandi@st.com 4:f48e8d87553e 905 * float T0_degC; *
davide.aliprandi@st.com 4:f48e8d87553e 906 * float T1_degC; *
davide.aliprandi@st.com 4:f48e8d87553e 907 * } COMPONENT_Data_t; *
davide.aliprandi@st.com 4:f48e8d87553e 908 *----------------------------------------------------------------------------*/
davide.aliprandi@st.com 4:f48e8d87553e 909
davide.aliprandi@st.com 4:f48e8d87553e 910 /**
davide.aliprandi@st.com 4:f48e8d87553e 911 * @}
davide.aliprandi@st.com 4:f48e8d87553e 912 */
davide.aliprandi@st.com 4:f48e8d87553e 913
davide.aliprandi@st.com 4:f48e8d87553e 914 /* Functions -----------------------------------------------------------------*/
davide.aliprandi@st.com 4:f48e8d87553e 915
davide.aliprandi@st.com 4:f48e8d87553e 916 /** @defgroup Powerstep01_Board_Linked_Functions Powerstep01 Board Linked Functions
davide.aliprandi@st.com 4:f48e8d87553e 917 * @{
davide.aliprandi@st.com 4:f48e8d87553e 918 */
davide.aliprandi@st.com 4:f48e8d87553e 919
davide.aliprandi@st.com 4:f48e8d87553e 920 /* ACTION --------------------------------------------------------------------*
davide.aliprandi@st.com 4:f48e8d87553e 921 * Declare here extern platform-dependent APIs you might need (e.g.: I/O and *
davide.aliprandi@st.com 4:f48e8d87553e 922 * interrupt related functions), and implement them in a glue-logic file on *
davide.aliprandi@st.com 4:f48e8d87553e 923 * the target environment, for example within the "x_nucleo_board.c" file. *
davide.aliprandi@st.com 4:f48e8d87553e 924 * E.g.: *
davide.aliprandi@st.com 4:f48e8d87553e 925 * extern status_t COMPONENT_IO_Init (void *handle); *
davide.aliprandi@st.com 4:f48e8d87553e 926 * extern status_t COMPONENT_IO_Read (handle, buf, regadd, bytes); *
davide.aliprandi@st.com 4:f48e8d87553e 927 * extern status_t COMPONENT_IO_Write(handle, buf, regadd, bytes); *
davide.aliprandi@st.com 4:f48e8d87553e 928 * extern void COMPONENT_IO_ITConfig(void); *
davide.aliprandi@st.com 4:f48e8d87553e 929 *----------------------------------------------------------------------------*/
davide.aliprandi@st.com 4:f48e8d87553e 930 ///Delay of the requested number of milliseconds
davide.aliprandi@st.com 4:f48e8d87553e 931 extern void Powerstep01_Board_Delay(void *handle, uint32_t delay);
davide.aliprandi@st.com 4:f48e8d87553e 932 ///Enable Irq
davide.aliprandi@st.com 4:f48e8d87553e 933 extern void Powerstep01_Board_EnableIrq(void *handle);
davide.aliprandi@st.com 4:f48e8d87553e 934 ///Disable Irq
davide.aliprandi@st.com 4:f48e8d87553e 935 extern void Powerstep01_Board_DisableIrq(void *handle);
davide.aliprandi@st.com 4:f48e8d87553e 936 ///init the timer for the step clock
davide.aliprandi@st.com 4:f48e8d87553e 937 extern void Powerstep01_Board_StepClockInit(void *handle);
davide.aliprandi@st.com 4:f48e8d87553e 938 ///Set the Powerstep01 reset pin (high logic level)
davide.aliprandi@st.com 4:f48e8d87553e 939 extern void Powerstep01_Board_ReleaseReset(void *handle);
davide.aliprandi@st.com 4:f48e8d87553e 940 ///Reset the Powerstep01 reset pin (low logic level)
davide.aliprandi@st.com 4:f48e8d87553e 941 extern void Powerstep01_Board_Reset(void *handle);
davide.aliprandi@st.com 4:f48e8d87553e 942 ///Write bytes to the Powerstep01s via SPI
davide.aliprandi@st.com 4:f48e8d87553e 943 extern uint8_t Powerstep01_Board_SpiWriteBytes(void *handle, uint8_t *pByteToTransmit, uint8_t *pReceivedByte);
davide.aliprandi@st.com 4:f48e8d87553e 944
davide.aliprandi@st.com 4:f48e8d87553e 945
davide.aliprandi@st.com 4:f48e8d87553e 946 /**
davide.aliprandi@st.com 4:f48e8d87553e 947 * @}
davide.aliprandi@st.com 4:f48e8d87553e 948 */
davide.aliprandi@st.com 4:f48e8d87553e 949
davide.aliprandi@st.com 4:f48e8d87553e 950 /**
davide.aliprandi@st.com 4:f48e8d87553e 951 * @}
davide.aliprandi@st.com 4:f48e8d87553e 952 */
davide.aliprandi@st.com 4:f48e8d87553e 953
davide.aliprandi@st.com 4:f48e8d87553e 954 /**
davide.aliprandi@st.com 4:f48e8d87553e 955 * @}
davide.aliprandi@st.com 4:f48e8d87553e 956 */
davide.aliprandi@st.com 4:f48e8d87553e 957
davide.aliprandi@st.com 4:f48e8d87553e 958 #ifdef __cplusplus
davide.aliprandi@st.com 4:f48e8d87553e 959 }
davide.aliprandi@st.com 4:f48e8d87553e 960 #endif
davide.aliprandi@st.com 4:f48e8d87553e 961
davide.aliprandi@st.com 4:f48e8d87553e 962 #endif /* #ifndef _POWERSTEP01_H_INCLUDED */
davide.aliprandi@st.com 4:f48e8d87553e 963
davide.aliprandi@st.com 4:f48e8d87553e 964 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/