ST
Expansion SW library to control high power stepper motor(s) using IHM03A1 expansion board(s) with Powerstep01 driver.
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: IHM03A1_ExampleFor1Motor HelloWorld_IHM03A1 IHM03A1_ExampleFor3Motors KYPHOS_Stepper_Motor_Control
Fork of
X_NUCLEO_IHM03A1
by 
ST Expansion SW Team
Motor Control Library
Library to handle the X-NUCLEO-IHM03A1 Motor Control Expansion Board based on the Powerstep01 component.
It features the:
- read and write of Powerstep01 registers
- Nucleo and expansion board configuration (GPIOs, PWMs, IRQs, etc.)
- Powerstep01 application commands handling
- FLAG and BUSY interrupt handling (alarm reporting)
- Daisy chain handling
The API allows to easily:
- perform various positioning, moves and stops
- get/set or monitor the motor positions
- set home position and mark another position
- get/set minimum and maximum speed
- get current speed
- get/set acceleration and deceleration
- get/set the step mode (up to 1/128)
- get/set the control method
- get/set parameters for voltage mode driving
- get/set parameters for current mode driving
- get/set parameters for gate driving
- configure various protections such as overcurrent detection
- enable/disable alarms
- handle step-clock
- get system status
Daisy-Chain Configuration
The IHM03A1 board can be stacked up to three times so that the Powerstep01 components will be connected in daisy-chain configuration. For this purpose, some resistors must be correctly connected on the boards as depicted here below:
Platform compatibility
Compatible platforms have been tested with the default configuration provided by the HelloWorld_IHM03A1 example.
Components/PowerStep01/PowerStep01.cpp@5:e7dca8c6ae9f, 2017-03-24 (annotated)
- Committer:
- Davidroid
- Date:
- Fri Mar 24 10:24:39 2017 +0000
- Revision:
- 5:e7dca8c6ae9f
- Parent:
- Components/powerstep01/PowerStep01.cpp@4:f48e8d87553e
- Child:
- 7:9d772e2a9dbe
Typo fixed.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| davide.aliprandi@st.com | 4:f48e8d87553e | 1 | /** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 2 | ****************************************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 3 | * @file PowerStep01.cpp |
| davide.aliprandi@st.com | 4:f48e8d87553e | 4 | * @author IPC Rennes |
| davide.aliprandi@st.com | 4:f48e8d87553e | 5 | * @version V1.0.0 |
| davide.aliprandi@st.com | 4:f48e8d87553e | 6 | * @date March 18th, 2016 |
| davide.aliprandi@st.com | 4:f48e8d87553e | 7 | * @brief Powerstep01 motor driver (Microstepping controller with power MOSFETs) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 8 | * @note (C) COPYRIGHT 2016 STMicroelectronics |
| davide.aliprandi@st.com | 4:f48e8d87553e | 9 | ****************************************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 10 | * @attention |
| davide.aliprandi@st.com | 4:f48e8d87553e | 11 | * |
| davide.aliprandi@st.com | 4:f48e8d87553e | 12 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| davide.aliprandi@st.com | 4:f48e8d87553e | 13 | * |
| davide.aliprandi@st.com | 4:f48e8d87553e | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 15 | * are permitted provided that the following conditions are met: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 17 | * this list of conditions and the following disclaimer. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 19 | * this list of conditions and the following disclaimer in the documentation |
| davide.aliprandi@st.com | 4:f48e8d87553e | 20 | * and/or other materials provided with the distribution. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| davide.aliprandi@st.com | 4:f48e8d87553e | 22 | * may be used to endorse or promote products derived from this software |
| davide.aliprandi@st.com | 4:f48e8d87553e | 23 | * without specific prior written permission. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 24 | * |
| davide.aliprandi@st.com | 4:f48e8d87553e | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| davide.aliprandi@st.com | 4:f48e8d87553e | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| davide.aliprandi@st.com | 4:f48e8d87553e | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| davide.aliprandi@st.com | 4:f48e8d87553e | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| davide.aliprandi@st.com | 4:f48e8d87553e | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| davide.aliprandi@st.com | 4:f48e8d87553e | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| davide.aliprandi@st.com | 4:f48e8d87553e | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| davide.aliprandi@st.com | 4:f48e8d87553e | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| davide.aliprandi@st.com | 4:f48e8d87553e | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 35 | * |
| davide.aliprandi@st.com | 4:f48e8d87553e | 36 | ****************************************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 37 | */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 38 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 39 | /* Includes ------------------------------------------------------------------*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 40 | #include "PowerStep01.h" |
| davide.aliprandi@st.com | 4:f48e8d87553e | 41 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 42 | /* Definitions ---------------------------------------------------------------*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 43 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 44 | /* Error of bad SPI transaction. */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 45 | #define POWERSTEP01_ERROR_1 (POWERSTEP01_ERROR_BASE|0x0001) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 46 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 47 | /* Variables ----------------------------------------------------------------*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 48 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 49 | /* Number of devices. */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 50 | uint8_t PowerStep01::numberOfDevices = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 51 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 52 | /* ISR flags used to restart an interrupted SPI transfer when an error is reported. */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 53 | bool PowerStep01::spiPreemptionByIsr = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 54 | bool PowerStep01::isrFlag = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 55 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 56 | /* SPI Transmission for Daisy-Chain Configuration. */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 57 | uint8_t PowerStep01::spiTxBursts[POWERSTEP01_CMD_ARG_MAX_NB_BYTES][MAX_NUMBER_OF_DEVICES]; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 58 | uint8_t PowerStep01::spiRxBursts[POWERSTEP01_CMD_ARG_MAX_NB_BYTES][MAX_NUMBER_OF_DEVICES]; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 59 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 60 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 61 | /* Methods -------------------------------------------------------------------*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 62 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 63 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 64 | * @brief Starts the Powerstep01 library |
| davide.aliprandi@st.com | 4:f48e8d87553e | 65 | * @param[in] pInit pointer to the initialization data |
| davide.aliprandi@st.com | 4:f48e8d87553e | 66 | * @retval COMPONENT_OK in case of success. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 67 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 68 | status_t PowerStep01::Powerstep01_Init(void* pInit) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 69 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 70 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 71 | /* configure the step clock */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 72 | Powerstep01_Board_StepClockInit(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 73 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 74 | /* Standby-reset deactivation */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 75 | Powerstep01_Board_ReleaseReset(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 76 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 77 | /* Let a delay after reset */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 78 | Powerstep01_Board_Delay(1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 79 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 80 | if (pInit == 0) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 81 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 82 | // Set all registers to their predefined values |
| davide.aliprandi@st.com | 4:f48e8d87553e | 83 | // from powerstep01_target_config.h |
| davide.aliprandi@st.com | 4:f48e8d87553e | 84 | Powerstep01_SetRegisterToPredefinedValues(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 85 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 86 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 87 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 88 | Powerstep01_SetDeviceParamsToGivenValues((powerstep01_init_u_t*) pInit); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 89 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 90 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 91 | // Put the Powerstep01 in HiZ state |
| davide.aliprandi@st.com | 4:f48e8d87553e | 92 | Powerstep01_CmdHardHiZ(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 93 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 94 | Powerstep01_FetchAndClearAllStatus(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 95 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 96 | return COMPONENT_OK; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 97 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 98 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 99 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 100 | * @brief Read id |
| davide.aliprandi@st.com | 4:f48e8d87553e | 101 | * @param[in] id pointer to the identifier to be read. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 102 | * @retval COMPONENT_OK in case of success. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 103 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 104 | status_t PowerStep01::Powerstep01_ReadID(uint8_t *id) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 105 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 106 | *id = deviceInstance; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 107 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 108 | return COMPONENT_OK; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 109 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 110 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 111 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 112 | * @brief Attaches a user callback to the error Handler. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 113 | * The call back will be then called each time the library |
| davide.aliprandi@st.com | 4:f48e8d87553e | 114 | * detects an error |
| davide.aliprandi@st.com | 4:f48e8d87553e | 115 | * @param[in] callback Name of the callback to attach |
| davide.aliprandi@st.com | 4:f48e8d87553e | 116 | * to the error Hanlder |
| davide.aliprandi@st.com | 4:f48e8d87553e | 117 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 118 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 119 | void PowerStep01::Powerstep01_AttachErrorHandler(void (*callback)(uint16_t error)) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 120 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 121 | errorHandlerCallback = (void (*)(uint16_t error)) callback; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 122 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 123 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 124 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 125 | * @brief Issues the get_status command to the Powerstep01 device |
| davide.aliprandi@st.com | 4:f48e8d87553e | 126 | * @retval Status Register value |
| davide.aliprandi@st.com | 4:f48e8d87553e | 127 | * @note Once the get_status command is performed, the flags of the |
| davide.aliprandi@st.com | 4:f48e8d87553e | 128 | * status register are reset. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 129 | * This is not the case when the status register is read with the |
| davide.aliprandi@st.com | 4:f48e8d87553e | 130 | * GetParam command (via the functions Powerstep01_ReadStatusRegister |
| davide.aliprandi@st.com | 4:f48e8d87553e | 131 | * or Powerstep01_CmdGetParam). |
| davide.aliprandi@st.com | 4:f48e8d87553e | 132 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 133 | uint16_t PowerStep01::Powerstep01_CmdGetStatus(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 134 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 135 | uint16_t status = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 136 | uint32_t loop; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 137 | uint8_t spiIndex = numberOfDevices - deviceInstance - 1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 138 | bool itDisable = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 139 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 140 | do |
| davide.aliprandi@st.com | 4:f48e8d87553e | 141 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 142 | spiPreemptionByIsr = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 143 | if (itDisable) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 144 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 145 | /* re-enable Powerstep01_Board_EnableIrq if disable in previous iteration */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 146 | Powerstep01_Board_EnableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 147 | itDisable = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 148 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 149 | for (loop = 0; loop < numberOfDevices; loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 150 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 151 | spiTxBursts[0][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 152 | spiTxBursts[1][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 153 | spiTxBursts[2][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 154 | spiTxBursts[3][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 155 | spiRxBursts[0][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 156 | spiRxBursts[1][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 157 | spiRxBursts[2][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 158 | spiRxBursts[3][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 159 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 160 | spiTxBursts[0][spiIndex] = POWERSTEP01_GET_STATUS; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 161 | /* Disable interruption before checking */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 162 | /* pre-emption by ISR and SPI transfers*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 163 | Powerstep01_Board_DisableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 164 | itDisable = TRUE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 165 | } while (spiPreemptionByIsr); // check pre-emption by ISR |
| davide.aliprandi@st.com | 4:f48e8d87553e | 166 | for (loop = 0; loop < POWERSTEP01_CMD_ARG_NB_BYTES_GET_STATUS + POWERSTEP01_RSP_NB_BYTES_GET_STATUS; loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 167 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 168 | Powerstep01_WriteBytes(&spiTxBursts[loop][0], &spiRxBursts[loop][0]); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 169 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 170 | status = (spiRxBursts[1][spiIndex] << 8) | (spiRxBursts[2][spiIndex]); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 171 | /* re-enable Powerstep01_Board_EnableIrq after SPI transfers*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 172 | Powerstep01_Board_EnableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 173 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 174 | return (status); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 175 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 176 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 177 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 178 | * @brief Requests the motor to move to the home position (ABS_POSITION = 0) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 179 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 180 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 181 | void PowerStep01::Powerstep01_CmdGoHome(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 182 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 183 | Powerstep01_SendCommand(POWERSTEP01_GO_HOME, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 184 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 185 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 186 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 187 | * @brief Requests the motor to move to the mark position |
| davide.aliprandi@st.com | 4:f48e8d87553e | 188 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 189 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 190 | void PowerStep01::Powerstep01_CmdGoMark(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 191 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 192 | Powerstep01_SendCommand(POWERSTEP01_GO_MARK, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 193 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 194 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 195 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 196 | * @brief Requests the motor to move to the specified position |
| davide.aliprandi@st.com | 4:f48e8d87553e | 197 | * @param[in] targetPosition absolute position in steps |
| davide.aliprandi@st.com | 4:f48e8d87553e | 198 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 199 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 200 | void PowerStep01::Powerstep01_CmdGoTo(int32_t targetPosition) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 201 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 202 | Powerstep01_SendCommand(POWERSTEP01_GO_TO, targetPosition); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 203 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 204 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 205 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 206 | * @brief Issues PowerStep01 Go To Dir command |
| davide.aliprandi@st.com | 4:f48e8d87553e | 207 | * @param[in] direction movement direction |
| davide.aliprandi@st.com | 4:f48e8d87553e | 208 | * @param[in] abs_pos absolute position where requested to move |
| davide.aliprandi@st.com | 4:f48e8d87553e | 209 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 210 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 211 | void PowerStep01::Powerstep01_CmdGoToDir(motorDir_t direction, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 212 | int32_t abs_pos) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 213 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 214 | Powerstep01_SendCommand((uint8_t)POWERSTEP01_GO_TO_DIR| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 215 | (uint8_t)direction, abs_pos); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 216 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 217 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 218 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 219 | * @brief Issues PowerStep01 Go Until command |
| davide.aliprandi@st.com | 4:f48e8d87553e | 220 | * @param[in] action ACTION_RESET or ACTION_COPY |
| davide.aliprandi@st.com | 4:f48e8d87553e | 221 | * @param[in] direction movement direction |
| davide.aliprandi@st.com | 4:f48e8d87553e | 222 | * @param[in] speed in steps/tick |
| davide.aliprandi@st.com | 4:f48e8d87553e | 223 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 224 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 225 | void PowerStep01::Powerstep01_CmdGoUntil(motorAction_t action, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 226 | motorDir_t direction, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 227 | uint32_t speed) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 228 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 229 | Powerstep01_SendCommand( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 230 | (uint8_t)POWERSTEP01_GO_UNTIL|(uint8_t)action|(uint8_t)direction, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 231 | speed); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 232 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 233 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 234 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 235 | * @brief Immediatly stops the motor and disable the power bridge |
| davide.aliprandi@st.com | 4:f48e8d87553e | 236 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 237 | * @note The hard_hiz command immediately disables the power bridges |
| davide.aliprandi@st.com | 4:f48e8d87553e | 238 | * (high impedance state) and raises the HiZ flag. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 239 | * When the motor is stopped, a hard_hiz command forces the bridges |
| davide.aliprandi@st.com | 4:f48e8d87553e | 240 | * to enter high impedance state. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 241 | * This command can be given anytime and is immediately executed. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 242 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 243 | void PowerStep01::Powerstep01_CmdHardHiZ(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 244 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 245 | Powerstep01_SendCommand(POWERSTEP01_HARD_HIZ, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 246 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 247 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 248 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 249 | * @brief Immediatly stops the motor and disable the power bridge |
| davide.aliprandi@st.com | 4:f48e8d87553e | 250 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 251 | * @note The hard_stop command causes an immediate motor stop with |
| davide.aliprandi@st.com | 4:f48e8d87553e | 252 | * infinite deceleration. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 253 | * When the motor is in high impedance state, a hard_stop command |
| davide.aliprandi@st.com | 4:f48e8d87553e | 254 | * forces the bridges to exit high impedance state; no motion is performed. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 255 | * This command can be given anytime and is immediately executed. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 256 | * This command keeps the BUSY flag low until the motor is stopped. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 257 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 258 | void PowerStep01::Powerstep01_CmdHardStop(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 259 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 260 | Powerstep01_SendCommand(POWERSTEP01_HARD_STOP, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 261 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 262 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 263 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 264 | * @brief Moves the motor of the specified number of steps |
| davide.aliprandi@st.com | 4:f48e8d87553e | 265 | * @param[in] direction FORWARD or BACKWARD |
| davide.aliprandi@st.com | 4:f48e8d87553e | 266 | * @param[in] stepCount Number of steps to perform |
| davide.aliprandi@st.com | 4:f48e8d87553e | 267 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 268 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 269 | void PowerStep01::Powerstep01_CmdMove(motorDir_t direction, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 270 | uint32_t stepCount) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 271 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 272 | Powerstep01_SendCommand((uint8_t)POWERSTEP01_MOVE|(uint8_t)direction, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 273 | stepCount); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 274 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 275 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 276 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 277 | * @brief Issues the Nop command to the Powerstep01 device |
| davide.aliprandi@st.com | 4:f48e8d87553e | 278 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 279 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 280 | void PowerStep01::Powerstep01_CmdNop(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 281 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 282 | Powerstep01_SendCommand(POWERSTEP01_NOP, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 283 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 284 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 285 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 286 | * @brief Issues PowerStep01 Release SW command |
| davide.aliprandi@st.com | 4:f48e8d87553e | 287 | * @param[in] action type of action to undertake when the SW |
| davide.aliprandi@st.com | 4:f48e8d87553e | 288 | * input is forced high |
| davide.aliprandi@st.com | 4:f48e8d87553e | 289 | * @param[in] direction movement direction |
| davide.aliprandi@st.com | 4:f48e8d87553e | 290 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 291 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 292 | void PowerStep01::Powerstep01_CmdReleaseSw(motorAction_t action, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 293 | motorDir_t direction) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 294 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 295 | Powerstep01_SendCommand((uint8_t)POWERSTEP01_RELEASE_SW| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 296 | (uint8_t)action| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 297 | (uint8_t)direction, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 298 | 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 299 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 300 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 301 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 302 | * @brief Issues PowerStep01 Reset Device command |
| davide.aliprandi@st.com | 4:f48e8d87553e | 303 | * @param[in] deviceId (from 0 to MAX_NUMBER_OF_DEVICES-1 ) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 304 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 305 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 306 | void PowerStep01::Powerstep01_CmdResetDevice(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 307 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 308 | Powerstep01_SendCommand(POWERSTEP01_RESET_DEVICE, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 309 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 310 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 311 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 312 | * @brief Issues PowerStep01 Reset Pos command |
| davide.aliprandi@st.com | 4:f48e8d87553e | 313 | * @param[in] deviceId (from 0 to MAX_NUMBER_OF_DEVICES-1 ) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 314 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 315 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 316 | void PowerStep01::Powerstep01_CmdResetPos(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 317 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 318 | Powerstep01_SendCommand(POWERSTEP01_RESET_POS, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 319 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 320 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 321 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 322 | * @brief Runs the motor. It will accelerate from the min |
| davide.aliprandi@st.com | 4:f48e8d87553e | 323 | * speed up to the max speed by using the device acceleration. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 324 | * @param[in] direction FORWARD or BACKWARD |
| davide.aliprandi@st.com | 4:f48e8d87553e | 325 | * @param[in] speed in steps/s |
| davide.aliprandi@st.com | 4:f48e8d87553e | 326 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 327 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 328 | void PowerStep01::Powerstep01_CmdRun(motorDir_t direction, uint32_t speed) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 329 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 330 | Powerstep01_SendCommand((uint8_t)POWERSTEP01_RUN|(uint8_t)direction, speed); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 331 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 332 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 333 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 334 | * @brief Stops the motor by using the device deceleration |
| davide.aliprandi@st.com | 4:f48e8d87553e | 335 | * and disables the power bridges |
| davide.aliprandi@st.com | 4:f48e8d87553e | 336 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 337 | * @note The soft_hiz command disables the power bridges |
| davide.aliprandi@st.com | 4:f48e8d87553e | 338 | * (high impedance state) after a deceleration to zero. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 339 | * The deceleration value used is the one stored in the DEC register. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 340 | * When bridges are disabled, the HiZ flag is raised. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 341 | * When the motor is stopped, a soft_hiz command forces the bridges |
| davide.aliprandi@st.com | 4:f48e8d87553e | 342 | * to enter high impedance state. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 343 | * This command can be given anytime and is immediately executed. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 344 | * This command keeps the BUSY flag low until the motor is stopped. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 345 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 346 | void PowerStep01::Powerstep01_CmdSoftHiZ(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 347 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 348 | Powerstep01_SendCommand(POWERSTEP01_SOFT_HIZ, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 349 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 350 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 351 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 352 | * @brief Stops the motor by using the device deceleration |
| davide.aliprandi@st.com | 4:f48e8d87553e | 353 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 354 | * @note The soft_stop command causes an immediate deceleration |
| davide.aliprandi@st.com | 4:f48e8d87553e | 355 | * to zero speed and a consequent motor stop. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 356 | * The deceleration value used is the one stored in the DEC register. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 357 | * When the motor is in high impedance state, a soft_stop |
| davide.aliprandi@st.com | 4:f48e8d87553e | 358 | * command forces the bridges to exit from high impedance state. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 359 | * No motion is performed. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 360 | * This command can be given anytime and is immediately executed. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 361 | * This command keeps the BUSY flag low until the motor is stopped. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 362 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 363 | void PowerStep01::Powerstep01_CmdSoftStop(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 364 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 365 | Powerstep01_SendCommand(POWERSTEP01_SOFT_STOP, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 366 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 367 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 368 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 369 | * @brief Issues PowerStep01 Step Clock command |
| davide.aliprandi@st.com | 4:f48e8d87553e | 370 | * @param[in] direction Movement direction (FORWARD, BACKWARD) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 371 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 372 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 373 | void PowerStep01::Powerstep01_CmdStepClock(motorDir_t direction) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 374 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 375 | Powerstep01_SendCommand((uint8_t)POWERSTEP01_STEP_CLOCK|(uint8_t)direction, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 376 | 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 377 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 378 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 379 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 380 | * @brief Error handler which calls the user callback (if defined) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 381 | * @param[in] error Number of the error |
| davide.aliprandi@st.com | 4:f48e8d87553e | 382 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 383 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 384 | void PowerStep01::Powerstep01_ErrorHandler(uint16_t error) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 385 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 386 | if (errorHandlerCallback != 0) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 387 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 388 | (void) errorHandlerCallback(error); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 389 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 390 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 391 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 392 | /* Aborting the program. */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 393 | exit(EXIT_FAILURE); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 394 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 395 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 396 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 397 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 398 | * @brief Fetch and clear status flags of all devices |
| davide.aliprandi@st.com | 4:f48e8d87553e | 399 | * by issuing a GET_STATUS command simultaneously |
| davide.aliprandi@st.com | 4:f48e8d87553e | 400 | * to all devices. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 401 | * Then, the fetched status of each device can be retrieved |
| davide.aliprandi@st.com | 4:f48e8d87553e | 402 | * by using the Powerstep01_GetFetchedStatus function |
| davide.aliprandi@st.com | 4:f48e8d87553e | 403 | * provided there is no other calls to functions which |
| davide.aliprandi@st.com | 4:f48e8d87553e | 404 | * use the SPI in between. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 405 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 406 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 407 | void PowerStep01::Powerstep01_FetchAndClearAllStatus(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 408 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 409 | uint8_t loop; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 410 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 411 | for (loop = 0; loop < numberOfDevices; loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 412 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 413 | spiTxBursts[0][loop] = POWERSTEP01_GET_STATUS; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 414 | spiTxBursts[1][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 415 | spiTxBursts[2][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 416 | spiTxBursts[3][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 417 | spiRxBursts[0][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 418 | spiRxBursts[1][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 419 | spiRxBursts[2][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 420 | spiRxBursts[3][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 421 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 422 | for (loop = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 423 | loop < POWERSTEP01_CMD_ARG_NB_BYTES_GET_STATUS + |
| davide.aliprandi@st.com | 4:f48e8d87553e | 424 | POWERSTEP01_RSP_NB_BYTES_GET_STATUS; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 425 | loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 426 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 427 | Powerstep01_WriteBytes(&spiTxBursts[loop][0], &spiRxBursts[loop][0]); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 428 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 429 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 430 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 431 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 432 | * @brief Get the value of the STATUS register which was |
| davide.aliprandi@st.com | 4:f48e8d87553e | 433 | * fetched by using Powerstep01_FetchAndClearAllStatus. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 434 | * The fetched values are available as long as there |
| davide.aliprandi@st.com | 4:f48e8d87553e | 435 | * no other calls to functions which use the SPI. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 436 | * @retval Last fetched value of the STATUS register |
| davide.aliprandi@st.com | 4:f48e8d87553e | 437 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 438 | uint16_t PowerStep01::Powerstep01_GetFetchedStatus(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 439 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 440 | uint16_t status = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 441 | if (numberOfDevices > deviceInstance) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 442 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 443 | uint8_t spiIndex = numberOfDevices - deviceInstance - 1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 444 | status = (spiRxBursts[1][spiIndex] << 8) | (spiRxBursts[2][spiIndex]); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 445 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 446 | return (status); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 447 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 448 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 449 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 450 | * @brief Returns the FW version of the library |
| davide.aliprandi@st.com | 4:f48e8d87553e | 451 | * @retval POWERSTEP01_FW_VERSION |
| davide.aliprandi@st.com | 4:f48e8d87553e | 452 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 453 | uint32_t PowerStep01::Powerstep01_GetFwVersion(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 454 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 455 | return (POWERSTEP01_FW_VERSION); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 456 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 457 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 458 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 459 | * @brief Returns the mark position device |
| davide.aliprandi@st.com | 4:f48e8d87553e | 460 | * @retval Mark register value converted in a 32b signed integer |
| davide.aliprandi@st.com | 4:f48e8d87553e | 461 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 462 | int32_t PowerStep01::Powerstep01_GetMark(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 463 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 464 | return Powerstep01_ConvertPosition(Powerstep01_CmdGetParam(POWERSTEP01_MARK)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 465 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 466 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 467 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 468 | * @brief Returns the ABS_POSITION device |
| davide.aliprandi@st.com | 4:f48e8d87553e | 469 | * @retval ABS_POSITION register value converted in a 32b signed integer |
| davide.aliprandi@st.com | 4:f48e8d87553e | 470 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 471 | int32_t PowerStep01::Powerstep01_GetPosition(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 472 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 473 | return Powerstep01_ConvertPosition( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 474 | Powerstep01_CmdGetParam(POWERSTEP01_ABS_POS)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 475 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 476 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 477 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 478 | * @brief Checks if the device is busy |
| davide.aliprandi@st.com | 4:f48e8d87553e | 479 | * by reading the Busy flag bit of its status Register |
| davide.aliprandi@st.com | 4:f48e8d87553e | 480 | * This operation clears the status register |
| davide.aliprandi@st.com | 4:f48e8d87553e | 481 | * @retval true if device is busy, false zero |
| davide.aliprandi@st.com | 4:f48e8d87553e | 482 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 483 | bool PowerStep01::Powerstep01_IsDeviceBusy(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 484 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 485 | if(!(Powerstep01_CmdGetStatus() & POWERSTEP01_STATUS_BUSY)) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 486 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 487 | return TRUE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 488 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 489 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 490 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 491 | return FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 492 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 493 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 494 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 495 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 496 | * @brief Reads the Status Register value |
| davide.aliprandi@st.com | 4:f48e8d87553e | 497 | * @retval Status register value |
| davide.aliprandi@st.com | 4:f48e8d87553e | 498 | * @note The status register flags are not cleared |
| davide.aliprandi@st.com | 4:f48e8d87553e | 499 | * at the difference with Powerstep01_CmdGetStatus() |
| davide.aliprandi@st.com | 4:f48e8d87553e | 500 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 501 | uint16_t PowerStep01::Powerstep01_ReadStatusRegister(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 502 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 503 | return (Powerstep01_CmdGetParam(POWERSTEP01_STATUS)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 504 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 505 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 506 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 507 | * @brief Set the stepping mode |
| davide.aliprandi@st.com | 4:f48e8d87553e | 508 | * @param[in] stepMode from full step to 1/128 microstep |
| davide.aliprandi@st.com | 4:f48e8d87553e | 509 | * as specified in enum motorStepMode_t |
| davide.aliprandi@st.com | 4:f48e8d87553e | 510 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 511 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 512 | bool PowerStep01::Powerstep01_SelectStepMode(motorStepMode_t stepMode) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 513 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 514 | uint8_t stepModeRegister; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 515 | powerstep01_StepSel_t powerstep01StepMode; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 516 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 517 | switch (stepMode) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 518 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 519 | case STEP_MODE_FULL: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 520 | powerstep01StepMode = POWERSTEP01_STEP_SEL_1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 521 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 522 | case STEP_MODE_HALF: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 523 | powerstep01StepMode = POWERSTEP01_STEP_SEL_1_2; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 524 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 525 | case STEP_MODE_1_4: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 526 | powerstep01StepMode = POWERSTEP01_STEP_SEL_1_4; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 527 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 528 | case STEP_MODE_1_8: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 529 | powerstep01StepMode = POWERSTEP01_STEP_SEL_1_8; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 530 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 531 | case STEP_MODE_1_16: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 532 | powerstep01StepMode = POWERSTEP01_STEP_SEL_1_16; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 533 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 534 | case STEP_MODE_1_32: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 535 | powerstep01StepMode = POWERSTEP01_STEP_SEL_1_32; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 536 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 537 | case STEP_MODE_1_64: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 538 | powerstep01StepMode = POWERSTEP01_STEP_SEL_1_64; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 539 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 540 | case STEP_MODE_1_128: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 541 | powerstep01StepMode = POWERSTEP01_STEP_SEL_1_128; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 542 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 543 | default: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 544 | return false; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 545 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 546 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 547 | /* Set the powerstep01 in HiZ state */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 548 | Powerstep01_CmdHardHiZ(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 549 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 550 | /* Read Step mode register and clear STEP_SEL field */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 551 | stepModeRegister = (uint8_t)(0xF8 & Powerstep01_CmdGetParam(POWERSTEP01_STEP_MODE)) ; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 552 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 553 | /* Apply new step mode */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 554 | Powerstep01_CmdSetParam(POWERSTEP01_STEP_MODE, stepModeRegister | (uint8_t)powerstep01StepMode); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 555 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 556 | /* Reset abs pos register */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 557 | Powerstep01_CmdResetPos(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 558 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 559 | return true; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 560 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 561 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 562 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 563 | * @brief Set current position to be the Home position (ABS pos set to 0) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 564 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 565 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 566 | void PowerStep01::Powerstep01_SetHome(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 567 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 568 | Powerstep01_CmdSetParam(POWERSTEP01_ABS_POS, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 569 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 570 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 571 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 572 | * @brief Sets current position to be the Mark position |
| davide.aliprandi@st.com | 4:f48e8d87553e | 573 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 574 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 575 | void PowerStep01::Powerstep01_SetMark(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 576 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 577 | Powerstep01_CmdSetParam(POWERSTEP01_MARK, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 578 | Powerstep01_CmdGetParam(POWERSTEP01_ABS_POS)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 579 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 580 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 581 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 582 | * @brief Locks until the device state becomes Inactive |
| davide.aliprandi@st.com | 4:f48e8d87553e | 583 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 584 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 585 | void PowerStep01::Powerstep01_WaitWhileActive(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 586 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 587 | /* Wait while motor is running */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 588 | while (Powerstep01_IsDeviceBusy() != 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 589 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 590 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 591 | /** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 592 | * @brief To and from register parameter conversion functions |
| davide.aliprandi@st.com | 4:f48e8d87553e | 593 | */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 594 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 595 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 596 | * @brief Converts the ABS_POSITION register value to a 32b signed integer |
| davide.aliprandi@st.com | 4:f48e8d87553e | 597 | * @param[in] abs_position_reg value of the ABS_POSITION register |
| davide.aliprandi@st.com | 4:f48e8d87553e | 598 | * @retval operation_result 32b signed integer corresponding to the absolute position |
| davide.aliprandi@st.com | 4:f48e8d87553e | 599 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 600 | int32_t PowerStep01::Powerstep01_ConvertPosition(uint32_t abs_position_reg) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 601 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 602 | int32_t operation_result; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 603 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 604 | if (abs_position_reg & POWERSTEP01_ABS_POS_SIGN_BIT_MASK) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 605 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 606 | /* Negative register value */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 607 | abs_position_reg = ~abs_position_reg; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 608 | abs_position_reg += 1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 609 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 610 | operation_result = (int32_t) (abs_position_reg & POWERSTEP01_ABS_POS_VALUE_MASK); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 611 | operation_result = -operation_result; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 612 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 613 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 614 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 615 | operation_result = (int32_t) abs_position_reg; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 616 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 617 | return operation_result; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 618 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 619 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 620 | /** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 621 | * @brief Functions to initialize the registers |
| davide.aliprandi@st.com | 4:f48e8d87553e | 622 | */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 623 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 624 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 625 | * @brief Set the parameters of the device to values of initPrm structure |
| davide.aliprandi@st.com | 4:f48e8d87553e | 626 | * @param[in] initPrm structure containing values to initialize the device |
| davide.aliprandi@st.com | 4:f48e8d87553e | 627 | * parameters |
| davide.aliprandi@st.com | 4:f48e8d87553e | 628 | * @retval None. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 629 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 630 | void PowerStep01::Powerstep01_SetDeviceParamsToGivenValues( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 631 | powerstep01_init_u_t *initPrm) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 632 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 633 | Powerstep01_CmdSetParam(POWERSTEP01_ABS_POS, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 634 | Powerstep01_CmdSetParam(POWERSTEP01_EL_POS, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 635 | Powerstep01_CmdSetParam(POWERSTEP01_MARK, 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 636 | Powerstep01_CmdSetParam(POWERSTEP01_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 637 | acc_dec_steps_s2_to_reg_val(initPrm->cm.cp.acceleration)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 638 | Powerstep01_CmdSetParam(POWERSTEP01_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 639 | acc_dec_steps_s2_to_reg_val(initPrm->cm.cp.deceleration)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 640 | Powerstep01_CmdSetParam(POWERSTEP01_MAX_SPEED, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 641 | max_spd_steps_s_to_reg_val(initPrm->cm.cp.maxSpeed)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 642 | Powerstep01_CmdSetParam(POWERSTEP01_MIN_SPEED, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 643 | initPrm->cm.cp.lowSpeedOptimization| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 644 | max_spd_steps_s_to_reg_val(initPrm->cm.cp.minSpeed)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 645 | Powerstep01_CmdSetParam(POWERSTEP01_FS_SPD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 646 | initPrm->cm.cp.boostMode| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 647 | fs_spd_steps_s_to_reg_val(initPrm->cm.cp.fullStepSpeed)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 648 | Powerstep01_CmdSetParam(POWERSTEP01_OCD_TH, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 649 | stall_ocd_th_to_reg_val(initPrm->cm.cp.ocdThreshold)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 650 | Powerstep01_CmdSetParam(POWERSTEP01_STEP_MODE, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 651 | (uint8_t)initPrm->cm.cp.syncClockSelection| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 652 | (uint8_t)initPrm->cm.cp.cmVmSelection| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 653 | (uint8_t)(uint8_t)initPrm->cm.cp.stepMode); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 654 | Powerstep01_CmdSetParam(POWERSTEP01_ALARM_EN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 655 | initPrm->cm.cp.alarmsSelection); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 656 | Powerstep01_CmdSetParam(POWERSTEP01_GATECFG1, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 657 | (uint16_t)initPrm->cm.cp.iGate| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 658 | (uint16_t)initPrm->cm.cp.tcc| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 659 | (uint16_t)initPrm->cm.cp.tBoost| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 660 | (uint16_t)initPrm->cm.cp.wdEn); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 661 | Powerstep01_CmdSetParam(POWERSTEP01_GATECFG2, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 662 | (uint16_t)initPrm->cm.cp.tBlank| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 663 | (uint16_t)initPrm->cm.cp.tdt); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 664 | if (initPrm->cm.cp.cmVmSelection == POWERSTEP01_CM_VM_VOLTAGE) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 665 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 666 | //Voltage mode |
| davide.aliprandi@st.com | 4:f48e8d87553e | 667 | Powerstep01_CmdSetParam(POWERSTEP01_INT_SPD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 668 | int_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 669 | initPrm->vm.intersectSpeed)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 670 | Powerstep01_CmdSetParam(POWERSTEP01_K_THERM, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 671 | k_therm_comp_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 672 | initPrm->vm.thermalCompensationFactor)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 673 | Powerstep01_CmdSetParam(POWERSTEP01_STALL_TH, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 674 | stall_ocd_th_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 675 | initPrm->vm.stallThreshold)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 676 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_HOLD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 677 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 678 | initPrm->vm.kvalHold)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 679 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_RUN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 680 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 681 | initPrm->vm.kvalRun)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 682 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 683 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 684 | initPrm->vm.kvalAcc)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 685 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 686 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 687 | initPrm->vm.kvalDec)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 688 | Powerstep01_CmdSetParam(POWERSTEP01_ST_SLP, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 689 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 690 | initPrm->vm.startSlope)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 691 | Powerstep01_CmdSetParam(POWERSTEP01_FN_SLP_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 692 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 693 | initPrm->vm.accelerationFinalSlope)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 694 | Powerstep01_CmdSetParam(POWERSTEP01_FN_SLP_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 695 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 696 | initPrm->vm.decelerationFinalSlope)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 697 | Powerstep01_CmdSetParam(POWERSTEP01_CONFIG, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 698 | (uint16_t)initPrm->vm.oscClkSel| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 699 | (uint16_t)initPrm->vm.swMode | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 700 | (uint16_t)initPrm->vm.enVsComp| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 701 | (uint16_t)initPrm->vm.ocSd| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 702 | (uint16_t)initPrm->vm.uvloVal| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 703 | (uint16_t)initPrm->vm.vccVal| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 704 | (uint16_t)initPrm->vm.fPwmInt| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 705 | (uint16_t)initPrm->vm.fPwmDec); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 706 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 707 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 708 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 709 | // Current mode |
| davide.aliprandi@st.com | 4:f48e8d87553e | 710 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_HOLD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 711 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 712 | initPrm->cm.tvalHold)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 713 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_RUN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 714 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 715 | initPrm->cm.tvalRun)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 716 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 717 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 718 | initPrm->cm.tvalAcc)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 719 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 720 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 721 | initPrm->cm.tvalDec)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 722 | Powerstep01_CmdSetParam(POWERSTEP01_T_FAST, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 723 | (uint8_t)initPrm->cm.toffFast| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 724 | (uint8_t)initPrm->cm.fastStep); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 725 | Powerstep01_CmdSetParam(POWERSTEP01_TON_MIN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 726 | t_min_time_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 727 | initPrm->cm.tonMin)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 728 | Powerstep01_CmdSetParam(POWERSTEP01_TOFF_MIN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 729 | t_min_time_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 730 | initPrm->cm.toffMin)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 731 | Powerstep01_CmdSetParam(POWERSTEP01_CONFIG, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 732 | (uint16_t)initPrm->cm.oscClkSel| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 733 | (uint16_t)initPrm->cm.swMode| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 734 | (uint16_t)initPrm->cm.tqReg| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 735 | (uint16_t)initPrm->cm.ocSd| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 736 | (uint16_t)initPrm->cm.uvloVal| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 737 | (uint16_t)initPrm->cm.vccVal| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 738 | (uint16_t)initPrm->cm.tsw| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 739 | (uint16_t)initPrm->cm.predEn); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 740 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 741 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 742 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 743 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 744 | * @brief Sets the registers of the Powerstep01 to their predefined values |
| davide.aliprandi@st.com | 4:f48e8d87553e | 745 | * from powerstep01_target_config.h |
| davide.aliprandi@st.com | 4:f48e8d87553e | 746 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 747 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 748 | void PowerStep01::Powerstep01_SetRegisterToPredefinedValues(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 749 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 750 | powerstep01_CmVm_t cmVm; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 751 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 752 | Powerstep01_CmdSetParam( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 753 | POWERSTEP01_ABS_POS, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 754 | 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 755 | Powerstep01_CmdSetParam( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 756 | POWERSTEP01_EL_POS, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 757 | 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 758 | Powerstep01_CmdSetParam( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 759 | POWERSTEP01_MARK, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 760 | 0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 761 | switch (deviceInstance) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 762 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 763 | case 0: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 764 | cmVm = POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 765 | Powerstep01_CmdSetParam(POWERSTEP01_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 766 | acc_dec_steps_s2_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 767 | POWERSTEP01_CONF_PARAM_ACC_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 768 | Powerstep01_CmdSetParam(POWERSTEP01_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 769 | acc_dec_steps_s2_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 770 | POWERSTEP01_CONF_PARAM_DEC_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 771 | Powerstep01_CmdSetParam(POWERSTEP01_MAX_SPEED, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 772 | max_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 773 | POWERSTEP01_CONF_PARAM_MAX_SPEED_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 774 | Powerstep01_CmdSetParam(POWERSTEP01_MIN_SPEED, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 775 | POWERSTEP01_CONF_PARAM_LSPD_BIT_DEVICE_0| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 776 | min_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 777 | POWERSTEP01_CONF_PARAM_MIN_SPEED_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 778 | Powerstep01_CmdSetParam(POWERSTEP01_FS_SPD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 779 | POWERSTEP01_CONF_PARAM_BOOST_MODE_DEVICE_0| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 780 | fs_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 781 | POWERSTEP01_CONF_PARAM_FS_SPD_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 782 | Powerstep01_CmdSetParam(POWERSTEP01_OCD_TH, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 783 | (uint8_t)POWERSTEP01_CONF_PARAM_OCD_TH_DEVICE_0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 784 | Powerstep01_CmdSetParam(POWERSTEP01_STEP_MODE, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 785 | (uint8_t)POWERSTEP01_CONF_PARAM_SYNC_MODE_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 786 | (uint8_t)POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_0| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 787 | (uint8_t)POWERSTEP01_CONF_PARAM_STEP_MODE_DEVICE_0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 788 | Powerstep01_CmdSetParam(POWERSTEP01_ALARM_EN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 789 | POWERSTEP01_CONF_PARAM_ALARM_EN_DEVICE_0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 790 | Powerstep01_CmdSetParam(POWERSTEP01_GATECFG1, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 791 | (uint16_t)POWERSTEP01_CONF_PARAM_IGATE_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 792 | (uint16_t)POWERSTEP01_CONF_PARAM_TCC_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 793 | (uint16_t)POWERSTEP01_CONF_PARAM_TBOOST_DEVICE_0| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 794 | (uint16_t)POWERSTEP01_CONF_PARAM_WD_EN_DEVICE_0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 795 | Powerstep01_CmdSetParam(POWERSTEP01_GATECFG2, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 796 | (uint16_t)POWERSTEP01_CONF_PARAM_TBLANK_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 797 | (uint16_t)POWERSTEP01_CONF_PARAM_TDT_DEVICE_0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 798 | // Voltage mode |
| davide.aliprandi@st.com | 4:f48e8d87553e | 799 | if (cmVm == POWERSTEP01_CM_VM_VOLTAGE) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 800 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 801 | Powerstep01_CmdSetParam(POWERSTEP01_INT_SPD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 802 | int_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 803 | POWERSTEP01_CONF_PARAM_INT_SPD_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 804 | Powerstep01_CmdSetParam(POWERSTEP01_K_THERM, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 805 | k_therm_comp_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 806 | POWERSTEP01_CONF_PARAM_K_THERM_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 807 | Powerstep01_CmdSetParam(POWERSTEP01_STALL_TH, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 808 | stall_ocd_th_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 809 | POWERSTEP01_CONF_PARAM_STALL_TH_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 810 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_HOLD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 811 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 812 | POWERSTEP01_CONF_PARAM_KVAL_HOLD_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 813 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_RUN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 814 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 815 | POWERSTEP01_CONF_PARAM_KVAL_RUN_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 816 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 817 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 818 | POWERSTEP01_CONF_PARAM_KVAL_ACC_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 819 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 820 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 821 | POWERSTEP01_CONF_PARAM_KVAL_DEC_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 822 | Powerstep01_CmdSetParam(POWERSTEP01_ST_SLP, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 823 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 824 | POWERSTEP01_CONF_PARAM_ST_SLP_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 825 | Powerstep01_CmdSetParam(POWERSTEP01_FN_SLP_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 826 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 827 | POWERSTEP01_CONF_PARAM_FN_SLP_ACC_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 828 | Powerstep01_CmdSetParam(POWERSTEP01_FN_SLP_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 829 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 830 | POWERSTEP01_CONF_PARAM_FN_SLP_DEC_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 831 | Powerstep01_CmdSetParam(POWERSTEP01_CONFIG, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 832 | (uint16_t)POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 833 | (uint16_t)POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 834 | (uint16_t)POWERSTEP01_CONF_PARAM_VS_COMP_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 835 | (uint16_t)POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 836 | (uint16_t)POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 837 | (uint16_t)POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 838 | (uint16_t)POWERSTEP01_CONF_PARAM_PWM_DIV_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 839 | (uint16_t)POWERSTEP01_CONF_PARAM_PWM_MUL_DEVICE_0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 840 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 841 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 842 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 843 | // Current mode |
| davide.aliprandi@st.com | 4:f48e8d87553e | 844 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_HOLD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 845 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 846 | POWERSTEP01_CONF_PARAM_TVAL_HOLD_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 847 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_RUN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 848 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 849 | POWERSTEP01_CONF_PARAM_TVAL_RUN_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 850 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 851 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 852 | POWERSTEP01_CONF_PARAM_TVAL_ACC_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 853 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 854 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 855 | POWERSTEP01_CONF_PARAM_TVAL_DEC_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 856 | Powerstep01_CmdSetParam(POWERSTEP01_T_FAST, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 857 | (uint8_t)POWERSTEP01_CONF_PARAM_TOFF_FAST_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 858 | (uint8_t)POWERSTEP01_CONF_PARAM_FAST_STEP_DEVICE_0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 859 | Powerstep01_CmdSetParam(POWERSTEP01_TON_MIN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 860 | t_min_time_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 861 | POWERSTEP01_CONF_PARAM_TON_MIN_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 862 | Powerstep01_CmdSetParam(POWERSTEP01_TOFF_MIN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 863 | t_min_time_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 864 | POWERSTEP01_CONF_PARAM_TOFF_MIN_DEVICE_0)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 865 | Powerstep01_CmdSetParam(POWERSTEP01_CONFIG, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 866 | (uint16_t)POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 867 | (uint16_t)POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 868 | (uint16_t)POWERSTEP01_CONF_PARAM_TQ_REG_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 869 | (uint16_t)POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 870 | (uint16_t)POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 871 | (uint16_t)POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 872 | (uint16_t)POWERSTEP01_CONF_PARAM_TSW_DEVICE_0 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 873 | (uint16_t)POWERSTEP01_CONF_PARAM_PRED_DEVICE_0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 874 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 875 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 876 | #if (MAX_NUMBER_OF_DEVICES > 1) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 877 | case 1: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 878 | cmVm = POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 879 | Powerstep01_CmdSetParam(POWERSTEP01_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 880 | acc_dec_steps_s2_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 881 | POWERSTEP01_CONF_PARAM_ACC_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 882 | Powerstep01_CmdSetParam(POWERSTEP01_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 883 | acc_dec_steps_s2_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 884 | POWERSTEP01_CONF_PARAM_DEC_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 885 | Powerstep01_CmdSetParam(POWERSTEP01_MAX_SPEED, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 886 | max_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 887 | POWERSTEP01_CONF_PARAM_MAX_SPEED_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 888 | Powerstep01_CmdSetParam(POWERSTEP01_MIN_SPEED, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 889 | POWERSTEP01_CONF_PARAM_LSPD_BIT_DEVICE_1| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 890 | min_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 891 | POWERSTEP01_CONF_PARAM_MIN_SPEED_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 892 | Powerstep01_CmdSetParam(POWERSTEP01_FS_SPD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 893 | POWERSTEP01_CONF_PARAM_BOOST_MODE_DEVICE_1| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 894 | fs_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 895 | POWERSTEP01_CONF_PARAM_FS_SPD_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 896 | Powerstep01_CmdSetParam(POWERSTEP01_OCD_TH, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 897 | (uint8_t)POWERSTEP01_CONF_PARAM_OCD_TH_DEVICE_1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 898 | Powerstep01_CmdSetParam(POWERSTEP01_STEP_MODE, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 899 | (uint8_t)POWERSTEP01_CONF_PARAM_SYNC_MODE_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 900 | (uint8_t)POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_1| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 901 | (uint8_t)POWERSTEP01_CONF_PARAM_STEP_MODE_DEVICE_1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 902 | Powerstep01_CmdSetParam(POWERSTEP01_ALARM_EN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 903 | POWERSTEP01_CONF_PARAM_ALARM_EN_DEVICE_1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 904 | Powerstep01_CmdSetParam(POWERSTEP01_GATECFG1, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 905 | (uint16_t)POWERSTEP01_CONF_PARAM_IGATE_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 906 | (uint16_t)POWERSTEP01_CONF_PARAM_TCC_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 907 | (uint16_t)POWERSTEP01_CONF_PARAM_TBOOST_DEVICE_1| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 908 | (uint16_t)POWERSTEP01_CONF_PARAM_WD_EN_DEVICE_1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 909 | Powerstep01_CmdSetParam(POWERSTEP01_GATECFG2, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 910 | (uint16_t)POWERSTEP01_CONF_PARAM_TBLANK_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 911 | (uint16_t)POWERSTEP01_CONF_PARAM_TDT_DEVICE_1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 912 | // Voltage mode |
| davide.aliprandi@st.com | 4:f48e8d87553e | 913 | if (cmVm == POWERSTEP01_CM_VM_VOLTAGE) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 914 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 915 | Powerstep01_CmdSetParam(POWERSTEP01_INT_SPD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 916 | int_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 917 | POWERSTEP01_CONF_PARAM_INT_SPD_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 918 | Powerstep01_CmdSetParam(POWERSTEP01_K_THERM, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 919 | k_therm_comp_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 920 | POWERSTEP01_CONF_PARAM_K_THERM_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 921 | Powerstep01_CmdSetParam(POWERSTEP01_STALL_TH, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 922 | stall_ocd_th_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 923 | POWERSTEP01_CONF_PARAM_STALL_TH_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 924 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_HOLD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 925 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 926 | POWERSTEP01_CONF_PARAM_KVAL_HOLD_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 927 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_RUN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 928 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 929 | POWERSTEP01_CONF_PARAM_KVAL_RUN_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 930 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 931 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 932 | POWERSTEP01_CONF_PARAM_KVAL_ACC_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 933 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 934 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 935 | POWERSTEP01_CONF_PARAM_KVAL_DEC_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 936 | Powerstep01_CmdSetParam(POWERSTEP01_ST_SLP, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 937 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 938 | POWERSTEP01_CONF_PARAM_ST_SLP_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 939 | Powerstep01_CmdSetParam(POWERSTEP01_FN_SLP_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 940 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 941 | POWERSTEP01_CONF_PARAM_FN_SLP_ACC_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 942 | Powerstep01_CmdSetParam(POWERSTEP01_FN_SLP_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 943 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 944 | POWERSTEP01_CONF_PARAM_FN_SLP_DEC_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 945 | Powerstep01_CmdSetParam(POWERSTEP01_CONFIG, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 946 | (uint16_t)POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 947 | (uint16_t)POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 948 | (uint16_t)POWERSTEP01_CONF_PARAM_VS_COMP_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 949 | (uint16_t)POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 950 | (uint16_t)POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 951 | (uint16_t)POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 952 | (uint16_t)POWERSTEP01_CONF_PARAM_PWM_DIV_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 953 | (uint16_t)POWERSTEP01_CONF_PARAM_PWM_MUL_DEVICE_1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 954 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 955 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 956 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 957 | // Current mode |
| davide.aliprandi@st.com | 4:f48e8d87553e | 958 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_HOLD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 959 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 960 | POWERSTEP01_CONF_PARAM_TVAL_HOLD_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 961 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_RUN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 962 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 963 | POWERSTEP01_CONF_PARAM_TVAL_RUN_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 964 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 965 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 966 | POWERSTEP01_CONF_PARAM_TVAL_ACC_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 967 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 968 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 969 | POWERSTEP01_CONF_PARAM_TVAL_DEC_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 970 | Powerstep01_CmdSetParam(POWERSTEP01_T_FAST, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 971 | (uint8_t)POWERSTEP01_CONF_PARAM_TOFF_FAST_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 972 | (uint8_t)POWERSTEP01_CONF_PARAM_FAST_STEP_DEVICE_1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 973 | Powerstep01_CmdSetParam(POWERSTEP01_TON_MIN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 974 | t_min_time_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 975 | POWERSTEP01_CONF_PARAM_TON_MIN_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 976 | Powerstep01_CmdSetParam(POWERSTEP01_TOFF_MIN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 977 | t_min_time_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 978 | POWERSTEP01_CONF_PARAM_TOFF_MIN_DEVICE_1)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 979 | Powerstep01_CmdSetParam(POWERSTEP01_CONFIG, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 980 | (uint16_t)POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 981 | (uint16_t)POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 982 | (uint16_t)POWERSTEP01_CONF_PARAM_TQ_REG_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 983 | (uint16_t)POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 984 | (uint16_t)POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 985 | (uint16_t)POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 986 | (uint16_t)POWERSTEP01_CONF_PARAM_TSW_DEVICE_1 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 987 | (uint16_t)POWERSTEP01_CONF_PARAM_PRED_DEVICE_1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 988 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 989 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 990 | #endif |
| davide.aliprandi@st.com | 4:f48e8d87553e | 991 | #if (MAX_NUMBER_OF_DEVICES > 2) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 992 | case 2: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 993 | cmVm = POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_2; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 994 | Powerstep01_CmdSetParam(POWERSTEP01_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 995 | acc_dec_steps_s2_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 996 | POWERSTEP01_CONF_PARAM_ACC_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 997 | Powerstep01_CmdSetParam(POWERSTEP01_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 998 | acc_dec_steps_s2_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 999 | POWERSTEP01_CONF_PARAM_DEC_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1000 | Powerstep01_CmdSetParam(POWERSTEP01_MAX_SPEED, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1001 | max_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1002 | POWERSTEP01_CONF_PARAM_MAX_SPEED_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1003 | Powerstep01_CmdSetParam(POWERSTEP01_MIN_SPEED, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1004 | POWERSTEP01_CONF_PARAM_LSPD_BIT_DEVICE_2| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1005 | min_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1006 | POWERSTEP01_CONF_PARAM_MIN_SPEED_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1007 | Powerstep01_CmdSetParam(POWERSTEP01_FS_SPD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1008 | POWERSTEP01_CONF_PARAM_BOOST_MODE_DEVICE_2| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1009 | fs_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1010 | POWERSTEP01_CONF_PARAM_FS_SPD_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1011 | Powerstep01_CmdSetParam(POWERSTEP01_OCD_TH, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1012 | (uint8_t)POWERSTEP01_CONF_PARAM_OCD_TH_DEVICE_2); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1013 | Powerstep01_CmdSetParam(POWERSTEP01_STEP_MODE, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1014 | (uint8_t)POWERSTEP01_CONF_PARAM_SYNC_MODE_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1015 | (uint8_t)POWERSTEP01_CONF_PARAM_CM_VM_DEVICE_2| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1016 | (uint8_t)POWERSTEP01_CONF_PARAM_STEP_MODE_DEVICE_2); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1017 | Powerstep01_CmdSetParam(POWERSTEP01_ALARM_EN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1018 | POWERSTEP01_CONF_PARAM_ALARM_EN_DEVICE_2); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1019 | Powerstep01_CmdSetParam(POWERSTEP01_GATECFG1, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1020 | (uint16_t)POWERSTEP01_CONF_PARAM_IGATE_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1021 | (uint16_t)POWERSTEP01_CONF_PARAM_TCC_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1022 | (uint16_t)POWERSTEP01_CONF_PARAM_TBOOST_DEVICE_2| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1023 | (uint16_t)POWERSTEP01_CONF_PARAM_WD_EN_DEVICE_2); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1024 | Powerstep01_CmdSetParam(POWERSTEP01_GATECFG2, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1025 | (uint16_t)POWERSTEP01_CONF_PARAM_TBLANK_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1026 | (uint16_t)POWERSTEP01_CONF_PARAM_TDT_DEVICE_2); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1027 | // Voltage mode |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1028 | if (cmVm == POWERSTEP01_CM_VM_VOLTAGE) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1029 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1030 | Powerstep01_CmdSetParam(POWERSTEP01_INT_SPD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1031 | int_spd_steps_s_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1032 | POWERSTEP01_CONF_PARAM_INT_SPD_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1033 | Powerstep01_CmdSetParam(POWERSTEP01_K_THERM, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1034 | k_therm_comp_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1035 | POWERSTEP01_CONF_PARAM_K_THERM_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1036 | Powerstep01_CmdSetParam(POWERSTEP01_STALL_TH, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1037 | stall_ocd_th_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1038 | POWERSTEP01_CONF_PARAM_STALL_TH_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1039 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_HOLD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1040 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1041 | POWERSTEP01_CONF_PARAM_KVAL_HOLD_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1042 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_RUN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1043 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1044 | POWERSTEP01_CONF_PARAM_KVAL_RUN_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1045 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1046 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1047 | POWERSTEP01_CONF_PARAM_KVAL_ACC_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1048 | Powerstep01_CmdSetParam(POWERSTEP01_KVAL_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1049 | k_val_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1050 | POWERSTEP01_CONF_PARAM_KVAL_DEC_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1051 | Powerstep01_CmdSetParam(POWERSTEP01_ST_SLP, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1052 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1053 | POWERSTEP01_CONF_PARAM_ST_SLP_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1054 | Powerstep01_CmdSetParam(POWERSTEP01_FN_SLP_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1055 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1056 | POWERSTEP01_CONF_PARAM_FN_SLP_ACC_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1057 | Powerstep01_CmdSetParam(POWERSTEP01_FN_SLP_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1058 | bemf_slope_perc_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1059 | POWERSTEP01_CONF_PARAM_FN_SLP_DEC_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1060 | Powerstep01_CmdSetParam(POWERSTEP01_CONFIG, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1061 | (uint16_t)POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1062 | (uint16_t)POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1063 | (uint16_t)POWERSTEP01_CONF_PARAM_VS_COMP_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1064 | (uint16_t)POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1065 | (uint16_t)POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1066 | (uint16_t)POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1067 | (uint16_t)POWERSTEP01_CONF_PARAM_PWM_DIV_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1068 | (uint16_t)POWERSTEP01_CONF_PARAM_PWM_MUL_DEVICE_2); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1069 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1070 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1071 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1072 | // Current mode |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1073 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_HOLD, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1074 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1075 | POWERSTEP01_CONF_PARAM_TVAL_HOLD_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1076 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_RUN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1077 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1078 | POWERSTEP01_CONF_PARAM_TVAL_RUN_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1079 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_ACC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1080 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1081 | POWERSTEP01_CONF_PARAM_TVAL_ACC_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1082 | Powerstep01_CmdSetParam(POWERSTEP01_TVAL_DEC, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1083 | t_val_ref_voltage_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1084 | POWERSTEP01_CONF_PARAM_TVAL_DEC_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1085 | Powerstep01_CmdSetParam(POWERSTEP01_T_FAST, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1086 | (uint8_t)POWERSTEP01_CONF_PARAM_TOFF_FAST_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1087 | (uint8_t)POWERSTEP01_CONF_PARAM_FAST_STEP_DEVICE_2); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1088 | Powerstep01_CmdSetParam(POWERSTEP01_TON_MIN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1089 | t_min_time_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1090 | POWERSTEP01_CONF_PARAM_TON_MIN_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1091 | Powerstep01_CmdSetParam(POWERSTEP01_TOFF_MIN, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1092 | t_min_time_to_reg_val( |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1093 | POWERSTEP01_CONF_PARAM_TOFF_MIN_DEVICE_2)); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1094 | Powerstep01_CmdSetParam(POWERSTEP01_CONFIG, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1095 | (uint16_t)POWERSTEP01_CONF_PARAM_CLOCK_SETTING_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1096 | (uint16_t)POWERSTEP01_CONF_PARAM_SW_MODE_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1097 | (uint16_t)POWERSTEP01_CONF_PARAM_TQ_REG_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1098 | (uint16_t)POWERSTEP01_CONF_PARAM_OC_SD_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1099 | (uint16_t)POWERSTEP01_CONF_PARAM_UVLOVAL_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1100 | (uint16_t)POWERSTEP01_CONF_PARAM_VCCVAL_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1101 | (uint16_t)POWERSTEP01_CONF_PARAM_TSW_DEVICE_2 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1102 | (uint16_t)POWERSTEP01_CONF_PARAM_PRED_DEVICE_2); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1103 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1104 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1105 | #endif |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1106 | default: ; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1107 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1108 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1109 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1110 | /** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1111 | * @brief Functions to get and set parameters using digital or analog values |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1112 | */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1113 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1114 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1115 | * @brief Issues the GetParam command to the Powerstep01 device |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1116 | * @param[in] parameter Register adress (POWERSTEP01_ABS_POS, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1117 | * POWERSTEP01_MARK,...) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1118 | * @retval Register value |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1119 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1120 | uint32_t PowerStep01::Powerstep01_CmdGetParam(powerstep01_Registers_t param) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1121 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1122 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1123 | uint32_t spiRxData; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1124 | uint32_t loop; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1125 | uint8_t maxArgumentNbBytes = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1126 | uint8_t spiIndex = numberOfDevices - deviceInstance - 1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1127 | bool itDisable = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1128 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1129 | do |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1130 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1131 | spiPreemptionByIsr = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1132 | if (itDisable) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1133 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1134 | /* re-enable Powerstep01_Board_EnableIrq if disable in previous iteration */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1135 | Powerstep01_Board_EnableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1136 | itDisable = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1137 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1138 | for (loop = 0; loop < numberOfDevices; loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1139 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1140 | spiTxBursts[0][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1141 | spiTxBursts[1][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1142 | spiTxBursts[2][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1143 | spiTxBursts[3][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1144 | spiRxBursts[0][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1145 | spiRxBursts[1][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1146 | spiRxBursts[2][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1147 | spiRxBursts[3][loop] = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1148 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1149 | switch (param) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1150 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1151 | case POWERSTEP01_ABS_POS: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1152 | case POWERSTEP01_MARK: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1153 | case POWERSTEP01_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1154 | spiTxBursts[0][spiIndex] = ((uint8_t)POWERSTEP01_GET_PARAM )| (param); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1155 | maxArgumentNbBytes = 3; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1156 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1157 | case POWERSTEP01_EL_POS: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1158 | case POWERSTEP01_ACC: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1159 | case POWERSTEP01_DEC: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1160 | case POWERSTEP01_MAX_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1161 | case POWERSTEP01_MIN_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1162 | case POWERSTEP01_FS_SPD: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1163 | case POWERSTEP01_INT_SPD: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1164 | case POWERSTEP01_CONFIG: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1165 | case POWERSTEP01_GATECFG1: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1166 | case POWERSTEP01_STATUS: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1167 | spiTxBursts[1][spiIndex] = ((uint8_t)POWERSTEP01_GET_PARAM )| (param); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1168 | maxArgumentNbBytes = 2; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1169 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1170 | default: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1171 | spiTxBursts[2][spiIndex] = ((uint8_t)POWERSTEP01_GET_PARAM )| (param); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1172 | maxArgumentNbBytes = 1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1173 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1174 | /* Disable interruption before checking */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1175 | /* pre-emption by ISR and SPI transfers*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1176 | Powerstep01_Board_DisableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1177 | itDisable = TRUE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1178 | } while (spiPreemptionByIsr); // check pre-emption by ISR |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1179 | for (loop = POWERSTEP01_CMD_ARG_MAX_NB_BYTES-1-maxArgumentNbBytes; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1180 | loop < POWERSTEP01_CMD_ARG_MAX_NB_BYTES; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1181 | loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1182 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1183 | Powerstep01_WriteBytes(&spiTxBursts[loop][0], |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1184 | &spiRxBursts[loop][0]); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1185 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1186 | spiRxData = ((uint32_t)spiRxBursts[1][spiIndex] << 16)| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1187 | (spiRxBursts[2][spiIndex] << 8) | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1188 | (spiRxBursts[3][spiIndex]); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1189 | /* re-enable Powerstep01_Board_EnableIrq after SPI transfers*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1190 | Powerstep01_Board_EnableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1191 | return (spiRxData); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1192 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1193 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1194 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1195 | * @brief Issues the SetParam command to the PowerStep01 device |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1196 | * @param[in] parameter Register adress (POWERSTEP01_ABS_POS, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1197 | * POWERSTEP01_MARK,...) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1198 | * @param[in] value Value to set in the register |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1199 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1200 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1201 | void PowerStep01::Powerstep01_CmdSetParam(powerstep01_Registers_t param, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1202 | uint32_t value) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1203 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1204 | uint32_t loop; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1205 | uint8_t maxArgumentNbBytes = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1206 | uint8_t spiIndex = numberOfDevices - deviceInstance - 1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1207 | bool itDisable = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1208 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1209 | do |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1210 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1211 | spiPreemptionByIsr = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1212 | if (itDisable) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1213 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1214 | /* re-enable Powerstep01_Board_EnableIrq if disable in previous iteration */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1215 | Powerstep01_Board_EnableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1216 | itDisable = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1217 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1218 | for (loop = 0;loop < numberOfDevices; loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1219 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1220 | spiTxBursts[0][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1221 | spiTxBursts[1][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1222 | spiTxBursts[2][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1223 | spiTxBursts[3][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1224 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1225 | switch (param) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1226 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1227 | case POWERSTEP01_ABS_POS: ; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1228 | case POWERSTEP01_MARK: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1229 | spiTxBursts[0][spiIndex] = ((uint8_t)POWERSTEP01_SET_PARAM )| (param); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1230 | spiTxBursts[1][spiIndex] = (uint8_t)(value >> 16); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1231 | spiTxBursts[2][spiIndex] = (uint8_t)(value >> 8); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1232 | maxArgumentNbBytes = 3; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1233 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1234 | case POWERSTEP01_EL_POS: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1235 | case POWERSTEP01_ACC: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1236 | case POWERSTEP01_DEC: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1237 | case POWERSTEP01_MAX_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1238 | case POWERSTEP01_MIN_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1239 | case POWERSTEP01_FS_SPD: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1240 | case POWERSTEP01_INT_SPD: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1241 | case POWERSTEP01_CONFIG: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1242 | case POWERSTEP01_GATECFG1: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1243 | spiTxBursts[1][spiIndex] = ((uint8_t)POWERSTEP01_SET_PARAM )| (param); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1244 | spiTxBursts[2][spiIndex] = (uint8_t)(value >> 8); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1245 | maxArgumentNbBytes = 2; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1246 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1247 | default: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1248 | spiTxBursts[2][spiIndex] = ((uint8_t)POWERSTEP01_SET_PARAM )| (param); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1249 | maxArgumentNbBytes = 1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1250 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1251 | spiTxBursts[3][spiIndex] = (uint8_t)(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1252 | /* Disable interruption before checking */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1253 | /* pre-emption by ISR and SPI transfers*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1254 | Powerstep01_Board_DisableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1255 | itDisable = TRUE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1256 | } while (spiPreemptionByIsr); // check pre-emption by ISR |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1257 | /* SPI transfer */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1258 | for (loop = POWERSTEP01_CMD_ARG_MAX_NB_BYTES - 1 - maxArgumentNbBytes; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1259 | loop < POWERSTEP01_CMD_ARG_MAX_NB_BYTES; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1260 | loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1261 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1262 | Powerstep01_WriteBytes(&spiTxBursts[loop][0],&spiRxBursts[loop][0]); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1263 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1264 | /* re-enable Powerstep01_Board_EnableIrq after SPI transfers*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1265 | Powerstep01_Board_EnableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1266 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1267 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1268 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1269 | * @brief Issues PowerStep01 Get Parameter command and convert the result to |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1270 | * float value |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1271 | * @param[in] param PowerStep01 register address |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1272 | * @retval The parameter's float value. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1273 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1274 | float PowerStep01::Powerstep01_GetAnalogValue(powerstep01_Registers_t param) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1275 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1276 | bool voltageMode = ((POWERSTEP01_CM_VM_CURRENT&Powerstep01_CmdGetParam(POWERSTEP01_STEP_MODE))==0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1277 | uint32_t registerValue = Powerstep01_CmdGetParam((powerstep01_Registers_t) param); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1278 | float value; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1279 | switch (param) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1280 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1281 | case POWERSTEP01_ABS_POS: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1282 | case POWERSTEP01_MARK: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1283 | value = (float) Powerstep01_ConvertPosition(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1284 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1285 | case POWERSTEP01_ACC: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1286 | case POWERSTEP01_DEC: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1287 | value = acc_dec_reg_val_to_steps_s2(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1288 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1289 | case POWERSTEP01_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1290 | value = speed_reg_val_to_steps_s(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1291 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1292 | case POWERSTEP01_MAX_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1293 | value = max_spd_reg_val_to_steps_s(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1294 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1295 | case POWERSTEP01_MIN_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1296 | registerValue &= POWERSTEP01_MIN_SPEED_MASK; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1297 | value = min_spd_reg_val_to_steps_s(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1298 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1299 | case POWERSTEP01_FS_SPD: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1300 | registerValue &= POWERSTEP01_FS_SPD_MASK; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1301 | value = fs_spd_reg_val_to_steps_s(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1302 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1303 | case POWERSTEP01_INT_SPD: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1304 | value = int_spd_reg_val_to_steps_s(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1305 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1306 | case POWERSTEP01_K_THERM: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1307 | value = k_therm_reg_val_to_comp(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1308 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1309 | case POWERSTEP01_OCD_TH: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1310 | case POWERSTEP01_STALL_TH: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1311 | value = stall_ocd_reg_val_to_th(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1312 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1313 | case POWERSTEP01_KVAL_HOLD: //POWERSTEP01_TVAL_HOLD |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1314 | case POWERSTEP01_KVAL_RUN: //POWERSTEP01_TVAL_RUN |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1315 | case POWERSTEP01_KVAL_ACC: //POWERSTEP01_TVAL_ACC |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1316 | case POWERSTEP01_KVAL_DEC: //POWERSTEP01_TVAL_DEC |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1317 | if (voltageMode!=FALSE) value = k_val_reg_val_to_perc(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1318 | else value = k_val_reg_val_to_perc(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1319 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1320 | case POWERSTEP01_ST_SLP: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1321 | if (voltageMode==FALSE) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1322 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1323 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1324 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1325 | case POWERSTEP01_FN_SLP_ACC: //POWERSTEP01_TON_MIN |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1326 | case POWERSTEP01_FN_SLP_DEC: //POWERSTEP01_TOFF_MIN |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1327 | if (voltageMode!=FALSE) value = bemf_slope_reg_val_to_perc(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1328 | else value = t_min_reg_val_to_time(registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1329 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1330 | default: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1331 | value = (float) registerValue; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1332 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1333 | return value; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1334 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1335 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1336 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1337 | * @brief Put commands in queue before synchronous sending |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1338 | * done by calling Powerstep01_SendQueuedCommands. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1339 | * Any call to functions that use the SPI between the calls of |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1340 | * Powerstep01_QueueCommands and Powerstep01_SendQueuedCommands |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1341 | * will corrupt the queue. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1342 | * A command for each device of the daisy chain must be |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1343 | * specified before calling Powerstep01_SendQueuedCommands. |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1344 | * @param[in] command Command to queue (all Powerstep01 commmands |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1345 | * except POWERSTEP01_SET_PARAM, POWERSTEP01_GET_PARAM, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1346 | * POWERSTEP01_GET_STATUS) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1347 | * @param[in] value argument of the command to queue |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1348 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1349 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1350 | void PowerStep01::Powerstep01_QueueCommands(uint8_t command, int32_t value) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1351 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1352 | if (numberOfDevices > deviceInstance) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1353 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1354 | uint8_t spiIndex = numberOfDevices - deviceInstance - 1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1355 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1356 | switch (command & DAISY_CHAIN_COMMAND_MASK) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1357 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1358 | case POWERSTEP01_RUN: ; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1359 | case POWERSTEP01_MOVE: ; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1360 | case POWERSTEP01_GO_TO: ; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1361 | case POWERSTEP01_GO_TO_DIR: ; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1362 | case POWERSTEP01_GO_UNTIL: ; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1363 | case POWERSTEP01_GO_UNTIL_ACT_CPY: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1364 | spiTxBursts[0][spiIndex] = command; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1365 | spiTxBursts[1][spiIndex] = (uint8_t)(value >> 16); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1366 | spiTxBursts[2][spiIndex] = (uint8_t)(value >> 8); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1367 | spiTxBursts[3][spiIndex] = (uint8_t)(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1368 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1369 | default: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1370 | spiTxBursts[0][spiIndex] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1371 | spiTxBursts[1][spiIndex] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1372 | spiTxBursts[2][spiIndex] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1373 | spiTxBursts[3][spiIndex] = command; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1374 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1375 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1376 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1377 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1378 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1379 | * @brief Sends a command to the device via the SPI |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1380 | * @param[in] command Command to send (all Powerstep01 commmands |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1381 | * except POWERSTEP01_SET_PARAM, POWERSTEP01_GET_PARAM, |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1382 | * POWERSTEP01_GET_STATUS) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1383 | * @param[in] value arguments to send on 32 bits |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1384 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1385 | **********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1386 | void PowerStep01::Powerstep01_SendCommand(uint8_t command, uint32_t value) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1387 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1388 | uint32_t loop; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1389 | uint8_t maxArgumentNbBytes = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1390 | bool itDisable = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1391 | uint8_t spiIndex = numberOfDevices - deviceInstance - 1; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1392 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1393 | do |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1394 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1395 | spiPreemptionByIsr = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1396 | if (itDisable) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1397 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1398 | /* re-enable Powerstep01_Board_EnableIrq if disable in previous iteration */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1399 | Powerstep01_Board_EnableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1400 | itDisable = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1401 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1402 | for (loop = 0; loop < numberOfDevices; loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1403 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1404 | spiTxBursts[0][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1405 | spiTxBursts[1][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1406 | spiTxBursts[2][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1407 | spiTxBursts[3][loop] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1408 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1409 | switch (command & DAISY_CHAIN_COMMAND_MASK) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1410 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1411 | case POWERSTEP01_GO_TO: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1412 | case POWERSTEP01_GO_TO_DIR: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1413 | value = value & POWERSTEP01_ABS_POS_VALUE_MASK; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1414 | case POWERSTEP01_RUN: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1415 | case POWERSTEP01_MOVE: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1416 | case POWERSTEP01_GO_UNTIL: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1417 | case POWERSTEP01_GO_UNTIL_ACT_CPY: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1418 | spiTxBursts[0][spiIndex] = command; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1419 | spiTxBursts[1][spiIndex] = (uint8_t)(value >> 16); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1420 | spiTxBursts[2][spiIndex] = (uint8_t)(value >> 8); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1421 | spiTxBursts[3][spiIndex] = (uint8_t)(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1422 | maxArgumentNbBytes = 3; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1423 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1424 | default: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1425 | spiTxBursts[0][spiIndex] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1426 | spiTxBursts[1][spiIndex] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1427 | spiTxBursts[2][spiIndex] = POWERSTEP01_NOP; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1428 | spiTxBursts[3][spiIndex] = command; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1429 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1430 | /* Disable interruption before checking */ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1431 | /* pre-emption by ISR and SPI transfers*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1432 | Powerstep01_Board_DisableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1433 | itDisable = TRUE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1434 | } while (spiPreemptionByIsr); // check pre-emption by ISR |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1435 | for (loop = POWERSTEP01_CMD_ARG_MAX_NB_BYTES - 1 - maxArgumentNbBytes; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1436 | loop < POWERSTEP01_CMD_ARG_MAX_NB_BYTES; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1437 | loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1438 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1439 | Powerstep01_WriteBytes(&spiTxBursts[loop][0], &spiRxBursts[loop][0]); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1440 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1441 | /* re-enable Powerstep01_Board_EnableIrq after SPI transfers*/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1442 | Powerstep01_Board_EnableIrq(); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1443 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1444 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1445 | /******************************************************//** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1446 | * @brief Sends commands stored previously in the queue by |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1447 | * Powerstep01_QueueCommands |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1448 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1449 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1450 | void PowerStep01::Powerstep01_SendQueuedCommands(void) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1451 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1452 | uint8_t loop; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1453 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1454 | for (loop = 0; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1455 | loop < POWERSTEP01_CMD_ARG_MAX_NB_BYTES; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1456 | loop++) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1457 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1458 | Powerstep01_WriteBytes(&spiTxBursts[loop][0], &spiRxBursts[loop][0]); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1459 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1460 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1461 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1462 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1463 | * @brief Issues the SetParam command to the PowerStep01 |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1464 | * @param[in] param PowerStep01 Register address |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1465 | * @param[in] value Float value to convert and set into the register |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1466 | * @retval TRUE if param is valid, FALSE otherwise |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1467 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1468 | bool PowerStep01::Powerstep01_SetAnalogValue(powerstep01_Registers_t param, float value) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1469 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1470 | uint32_t registerValue; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1471 | bool result = TRUE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1472 | bool voltageMode = ((POWERSTEP01_CM_VM_CURRENT&Powerstep01_CmdGetParam(POWERSTEP01_STEP_MODE))==0); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1473 | if ((value < 0)&&((param != POWERSTEP01_ABS_POS)&&(param != POWERSTEP01_MARK))) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1474 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1475 | result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1476 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1477 | switch (param) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1478 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1479 | case POWERSTEP01_EL_POS: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1480 | if ((value > (POWERSTEP01_ELPOS_STEP_MASK|POWERSTEP01_ELPOS_MICROSTEP_MASK))|| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1481 | ((value!=0)&&(value < (1<<(7-(POWERSTEP01_STEP_MODE_STEP_SEL&Powerstep01_CmdGetParam(POWERSTEP01_STEP_MODE))))))) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1482 | else registerValue = ((uint32_t) value)&(POWERSTEP01_ELPOS_STEP_MASK|POWERSTEP01_ELPOS_MICROSTEP_MASK); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1483 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1484 | case POWERSTEP01_ABS_POS: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1485 | case POWERSTEP01_MARK: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1486 | if (value < 0) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1487 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1488 | value=-value; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1489 | if (((uint32_t)value)<=(POWERSTEP01_MAX_POSITION+1)) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1490 | registerValue = (POWERSTEP01_ABS_POS_VALUE_MASK+1-(uint32_t)value)&POWERSTEP01_ABS_POS_VALUE_MASK; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1491 | else result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1492 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1493 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1494 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1495 | if (((uint32_t)value)<=POWERSTEP01_MAX_POSITION) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1496 | registerValue = ((uint32_t) value)&POWERSTEP01_ABS_POS_VALUE_MASK; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1497 | else result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1498 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1499 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1500 | case POWERSTEP01_ACC: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1501 | case POWERSTEP01_DEC: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1502 | if (value > POWERSTEP01_ACC_DEC_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1503 | else registerValue = acc_dec_steps_s2_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1504 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1505 | case POWERSTEP01_MAX_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1506 | if (value > POWERSTEP01_MAX_SPEED_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1507 | else registerValue = max_spd_steps_s_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1508 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1509 | case POWERSTEP01_MIN_SPEED: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1510 | if (value > POWERSTEP01_MIN_SPEED_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1511 | else registerValue = (POWERSTEP01_LSPD_OPT&Powerstep01_CmdGetParam(param))|min_spd_steps_s_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1512 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1513 | case POWERSTEP01_FS_SPD: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1514 | if (value > POWERSTEP01_FS_SPD_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1515 | else registerValue = (POWERSTEP01_BOOST_MODE&Powerstep01_CmdGetParam(param))|fs_spd_steps_s_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1516 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1517 | case POWERSTEP01_INT_SPD: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1518 | if (value > POWERSTEP01_INT_SPD_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1519 | else registerValue = int_spd_steps_s_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1520 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1521 | case POWERSTEP01_K_THERM: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1522 | if ((value < POWERSTEP01_K_THERM_MIN_VALUE)|| |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1523 | (value > POWERSTEP01_K_THERM_MAX_VALUE)) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1524 | else registerValue = k_therm_comp_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1525 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1526 | case POWERSTEP01_OCD_TH: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1527 | case POWERSTEP01_STALL_TH: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1528 | if (value > POWERSTEP01_STALL_OCD_TH_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1529 | else registerValue = stall_ocd_th_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1530 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1531 | case POWERSTEP01_KVAL_HOLD: //POWERSTEP01_TVAL_HOLD |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1532 | case POWERSTEP01_KVAL_RUN: //POWERSTEP01_TVAL_RUN |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1533 | case POWERSTEP01_KVAL_ACC: //POWERSTEP01_TVAL_ACC |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1534 | case POWERSTEP01_KVAL_DEC: //POWERSTEP01_TVAL_DEC |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1535 | if (voltageMode==FALSE) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1536 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1537 | if (value > POWERSTEP01_TVAL_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1538 | else registerValue = t_val_ref_voltage_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1539 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1540 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1541 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1542 | if (value > POWERSTEP01_KVAL_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1543 | else registerValue = k_val_perc_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1544 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1545 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1546 | case POWERSTEP01_ST_SLP: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1547 | if (voltageMode==FALSE) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1548 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1549 | result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1550 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1551 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1552 | case POWERSTEP01_FN_SLP_ACC: //POWERSTEP01_TON_MIN |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1553 | case POWERSTEP01_FN_SLP_DEC: //POWERSTEP01_TOFF_MIN |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1554 | if (voltageMode==FALSE) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1555 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1556 | if (value>POWERSTEP01_TOFF_TON_MIN_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1557 | else registerValue = t_min_time_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1558 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1559 | else |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1560 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1561 | if (value > POWERSTEP01_SLP_MAX_VALUE) result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1562 | else registerValue = bemf_slope_perc_to_reg_val(value); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1563 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1564 | break; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1565 | default: |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1566 | result = FALSE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1567 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1568 | if (result!=FALSE) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1569 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1570 | Powerstep01_CmdSetParam(param, registerValue); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1571 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1572 | return result; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1573 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1574 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1575 | /********************************************************** |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1576 | * @brief Write and receive a byte via SPI |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1577 | * @param[in] pByteToTransmit pointer to the byte to transmit |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1578 | * @param[in] pReceivedByte pointer to the received byte |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1579 | * @retval None |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1580 | *********************************************************/ |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1581 | void PowerStep01::Powerstep01_WriteBytes(uint8_t *pByteToTransmit, uint8_t *pReceivedByte) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1582 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1583 | if (Powerstep01_Board_SpiWriteBytes(pByteToTransmit, pReceivedByte) != 0) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1584 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1585 | Powerstep01_ErrorHandler(POWERSTEP01_ERROR_1); |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1586 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1587 | if (isrFlag) |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1588 | { |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1589 | spiPreemptionByIsr = TRUE; |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1590 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1591 | } |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1592 | |
| davide.aliprandi@st.com | 4:f48e8d87553e | 1593 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
X-NUCLEO-IHM03A1 High Power Stepper Motor Driver