LSM6DSOX - iNEMO inertial module: 3D accelerometer and 3D gy…

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iNEMO inertial module: 3D accelerometer and 3D gyroscope.

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

lsm6dsox_reg.c@1:fe40aec6e97a, 2020-10-29 (annotated)

Committer:: cparata
Date:: Thu Oct 29 12:45:14 2020 +0000
Revision:: 1:fe40aec6e97a
Parent:: 0:f27ce43dee4f
Child:: 5:97fea56292cd

Update PID and add low power modes

Who changed what in which revision?

User	Revision	Line number	New contents of line
cparata	0:f27ce43dee4f	1	/*
cparata	0:f27ce43dee4f	2	******************************************************************************
cparata	0:f27ce43dee4f	3	* @file lsm6dsox_reg.c
cparata	1:fe40aec6e97a	4	* @author Sensors Software Solution Team
cparata	0:f27ce43dee4f	5	* @brief LSM6DSOX driver file
cparata	0:f27ce43dee4f	6	******************************************************************************
cparata	0:f27ce43dee4f	7	* @attention
cparata	0:f27ce43dee4f	8	*
cparata	0:f27ce43dee4f	9	* <h2><center>© Copyright (c) 2019 STMicroelectronics.
cparata	0:f27ce43dee4f	10	* All rights reserved.</center></h2>
cparata	0:f27ce43dee4f	11	*
cparata	0:f27ce43dee4f	12	* This software component is licensed by ST under BSD 3-Clause license,
cparata	0:f27ce43dee4f	13	* the "License"; You may not use this file except in compliance with the
cparata	0:f27ce43dee4f	14	* License. You may obtain a copy of the License at:
cparata	0:f27ce43dee4f	15	* opensource.org/licenses/BSD-3-Clause
cparata	0:f27ce43dee4f	16	*
cparata	0:f27ce43dee4f	17	******************************************************************************
cparata	0:f27ce43dee4f	18	*/
cparata	0:f27ce43dee4f	19
cparata	0:f27ce43dee4f	20	#include "lsm6dsox_reg.h"
cparata	0:f27ce43dee4f	21
cparata	0:f27ce43dee4f	22	/**
cparata	0:f27ce43dee4f	23	* @defgroup LSM6DSOX
cparata	0:f27ce43dee4f	24	* @brief This file provides a set of functions needed to drive the
cparata	0:f27ce43dee4f	25	* lsm6dsox enhanced inertial module.
cparata	0:f27ce43dee4f	26	* @{
cparata	0:f27ce43dee4f	27	*
cparata	1:fe40aec6e97a	28	*/
cparata	0:f27ce43dee4f	29
cparata	0:f27ce43dee4f	30	/**
cparata	0:f27ce43dee4f	31	* @defgroup LSM6DSOX_Interfaces_Functions
cparata	0:f27ce43dee4f	32	* @brief This section provide a set of functions used to read and
cparata	0:f27ce43dee4f	33	* write a generic register of the device.
cparata	0:f27ce43dee4f	34	* MANDATORY: return 0 -> no Error.
cparata	0:f27ce43dee4f	35	* @{
cparata	0:f27ce43dee4f	36	*
cparata	0:f27ce43dee4f	37	*/
cparata	0:f27ce43dee4f	38
cparata	0:f27ce43dee4f	39	/**
cparata	0:f27ce43dee4f	40	* @brief Read generic device register
cparata	0:f27ce43dee4f	41	*
cparata	1:fe40aec6e97a	42	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	43	* @param reg first register address to read.
cparata	1:fe40aec6e97a	44	* @param data buffer for data read.(ptr)
cparata	1:fe40aec6e97a	45	* @param len number of consecutive register to read.
cparata	1:fe40aec6e97a	46	* @retval interface status (MANDATORY: return 0 -> no Error).
cparata	0:f27ce43dee4f	47	*
cparata	0:f27ce43dee4f	48	*/
cparata	0:f27ce43dee4f	49	int32_t lsm6dsox_read_reg(lsm6dsox_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	1:fe40aec6e97a	50	uint16_t len)
cparata	0:f27ce43dee4f	51	{
cparata	0:f27ce43dee4f	52	int32_t ret;
cparata	0:f27ce43dee4f	53	ret = ctx->read_reg(ctx->handle, reg, data, len);
cparata	0:f27ce43dee4f	54	return ret;
cparata	0:f27ce43dee4f	55	}
cparata	0:f27ce43dee4f	56
cparata	0:f27ce43dee4f	57	/**
cparata	0:f27ce43dee4f	58	* @brief Write generic device register
cparata	0:f27ce43dee4f	59	*
cparata	1:fe40aec6e97a	60	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	61	* @param reg first register address to write.
cparata	1:fe40aec6e97a	62	* @param data the buffer contains data to be written.(ptr)
cparata	1:fe40aec6e97a	63	* @param len number of consecutive register to write.
cparata	1:fe40aec6e97a	64	* @retval interface status (MANDATORY: return 0 -> no Error).
cparata	0:f27ce43dee4f	65	*
cparata	0:f27ce43dee4f	66	*/
cparata	0:f27ce43dee4f	67	int32_t lsm6dsox_write_reg(lsm6dsox_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	1:fe40aec6e97a	68	uint16_t len)
cparata	0:f27ce43dee4f	69	{
cparata	0:f27ce43dee4f	70	int32_t ret;
cparata	0:f27ce43dee4f	71	ret = ctx->write_reg(ctx->handle, reg, data, len);
cparata	0:f27ce43dee4f	72	return ret;
cparata	0:f27ce43dee4f	73	}
cparata	0:f27ce43dee4f	74
cparata	0:f27ce43dee4f	75	/**
cparata	0:f27ce43dee4f	76	* @}
cparata	0:f27ce43dee4f	77	*
cparata	0:f27ce43dee4f	78	*/
cparata	0:f27ce43dee4f	79
cparata	0:f27ce43dee4f	80	/**
cparata	1:fe40aec6e97a	81	* @defgroup LSM6DSOX_Private_functions
cparata	1:fe40aec6e97a	82	* @brief Section collect all the utility functions needed by APIs.
cparata	1:fe40aec6e97a	83	* @{
cparata	1:fe40aec6e97a	84	*
cparata	1:fe40aec6e97a	85	*/
cparata	1:fe40aec6e97a	86
cparata	1:fe40aec6e97a	87	static void bytecpy(uint8_t target, uint8_t source)
cparata	1:fe40aec6e97a	88	{
cparata	1:fe40aec6e97a	89	if ( (target != NULL) && (source != NULL) ) {
cparata	1:fe40aec6e97a	90	target = source;
cparata	1:fe40aec6e97a	91	}
cparata	1:fe40aec6e97a	92	}
cparata	1:fe40aec6e97a	93
cparata	1:fe40aec6e97a	94	/**
cparata	1:fe40aec6e97a	95	* @}
cparata	1:fe40aec6e97a	96	*
cparata	1:fe40aec6e97a	97	*/
cparata	1:fe40aec6e97a	98
cparata	1:fe40aec6e97a	99	/**
cparata	0:f27ce43dee4f	100	* @defgroup LSM6DSOX_Sensitivity
cparata	0:f27ce43dee4f	101	* @brief These functions convert raw-data into engineering units.
cparata	0:f27ce43dee4f	102	* @{
cparata	0:f27ce43dee4f	103	*
cparata	0:f27ce43dee4f	104	*/
cparata	0:f27ce43dee4f	105	float_t lsm6dsox_from_fs2_to_mg(int16_t lsb)
cparata	0:f27ce43dee4f	106	{
cparata	0:f27ce43dee4f	107	return ((float_t)lsb) * 0.061f;
cparata	0:f27ce43dee4f	108	}
cparata	0:f27ce43dee4f	109
cparata	0:f27ce43dee4f	110	float_t lsm6dsox_from_fs4_to_mg(int16_t lsb)
cparata	0:f27ce43dee4f	111	{
cparata	0:f27ce43dee4f	112	return ((float_t)lsb) * 0.122f;
cparata	0:f27ce43dee4f	113	}
cparata	0:f27ce43dee4f	114
cparata	0:f27ce43dee4f	115	float_t lsm6dsox_from_fs8_to_mg(int16_t lsb)
cparata	0:f27ce43dee4f	116	{
cparata	0:f27ce43dee4f	117	return ((float_t)lsb) * 0.244f;
cparata	0:f27ce43dee4f	118	}
cparata	0:f27ce43dee4f	119
cparata	0:f27ce43dee4f	120	float_t lsm6dsox_from_fs16_to_mg(int16_t lsb)
cparata	0:f27ce43dee4f	121	{
cparata	0:f27ce43dee4f	122	return ((float_t)lsb) *0.488f;
cparata	0:f27ce43dee4f	123	}
cparata	0:f27ce43dee4f	124
cparata	0:f27ce43dee4f	125	float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb)
cparata	0:f27ce43dee4f	126	{
cparata	0:f27ce43dee4f	127	return ((float_t)lsb) *4.375f;
cparata	0:f27ce43dee4f	128	}
cparata	0:f27ce43dee4f	129
cparata	0:f27ce43dee4f	130	float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb)
cparata	0:f27ce43dee4f	131	{
cparata	0:f27ce43dee4f	132	return ((float_t)lsb) *17.50f;
cparata	0:f27ce43dee4f	133	}
cparata	0:f27ce43dee4f	134
cparata	0:f27ce43dee4f	135	float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb)
cparata	0:f27ce43dee4f	136	{
cparata	0:f27ce43dee4f	137	return ((float_t)lsb) *8.750f;
cparata	0:f27ce43dee4f	138	}
cparata	0:f27ce43dee4f	139
cparata	0:f27ce43dee4f	140	float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb)
cparata	0:f27ce43dee4f	141	{
cparata	0:f27ce43dee4f	142	return ((float_t)lsb) *35.0f;
cparata	0:f27ce43dee4f	143	}
cparata	0:f27ce43dee4f	144
cparata	0:f27ce43dee4f	145	float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb)
cparata	0:f27ce43dee4f	146	{
cparata	0:f27ce43dee4f	147	return ((float_t)lsb) *70.0f;
cparata	0:f27ce43dee4f	148	}
cparata	0:f27ce43dee4f	149
cparata	0:f27ce43dee4f	150	float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb)
cparata	0:f27ce43dee4f	151	{
cparata	0:f27ce43dee4f	152	return (((float_t)lsb / 256.0f) + 25.0f);
cparata	0:f27ce43dee4f	153	}
cparata	0:f27ce43dee4f	154
cparata	0:f27ce43dee4f	155	float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb)
cparata	0:f27ce43dee4f	156	{
cparata	0:f27ce43dee4f	157	return ((float_t)lsb * 25000.0f);
cparata	0:f27ce43dee4f	158	}
cparata	0:f27ce43dee4f	159
cparata	0:f27ce43dee4f	160	/**
cparata	0:f27ce43dee4f	161	* @}
cparata	0:f27ce43dee4f	162	*
cparata	0:f27ce43dee4f	163	*/
cparata	0:f27ce43dee4f	164
cparata	0:f27ce43dee4f	165	/**
cparata	0:f27ce43dee4f	166	* @defgroup LSM6DSOX_Data_Generation
cparata	0:f27ce43dee4f	167	* @brief This section groups all the functions concerning
cparata	0:f27ce43dee4f	168	* data generation.
cparata	0:f27ce43dee4f	169	*
cparata	0:f27ce43dee4f	170	*/
cparata	0:f27ce43dee4f	171
cparata	0:f27ce43dee4f	172	/**
cparata	0:f27ce43dee4f	173	* @brief Accelerometer full-scale selection.[set]
cparata	0:f27ce43dee4f	174	*
cparata	0:f27ce43dee4f	175	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	176	* @param val change the values of fs_xl in reg CTRL1_XL
cparata	0:f27ce43dee4f	177	*
cparata	0:f27ce43dee4f	178	*/
cparata	0:f27ce43dee4f	179	int32_t lsm6dsox_xl_full_scale_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	180	lsm6dsox_fs_xl_t val)
cparata	0:f27ce43dee4f	181	{
cparata	0:f27ce43dee4f	182	lsm6dsox_ctrl1_xl_t reg;
cparata	0:f27ce43dee4f	183	int32_t ret;
cparata	0:f27ce43dee4f	184
cparata	0:f27ce43dee4f	185	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	186	if (ret == 0) {
cparata	0:f27ce43dee4f	187	reg.fs_xl = (uint8_t) val;
cparata	0:f27ce43dee4f	188	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	189	}
cparata	0:f27ce43dee4f	190	return ret;
cparata	0:f27ce43dee4f	191	}
cparata	0:f27ce43dee4f	192
cparata	0:f27ce43dee4f	193	/**
cparata	0:f27ce43dee4f	194	* @brief Accelerometer full-scale selection.[get]
cparata	0:f27ce43dee4f	195	*
cparata	0:f27ce43dee4f	196	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	197	* @param val Get the values of fs_xl in reg CTRL1_XL
cparata	0:f27ce43dee4f	198	*
cparata	0:f27ce43dee4f	199	*/
cparata	0:f27ce43dee4f	200	int32_t lsm6dsox_xl_full_scale_get(lsm6dsox_ctx_t ctx, lsm6dsox_fs_xl_t val)
cparata	0:f27ce43dee4f	201	{
cparata	0:f27ce43dee4f	202	lsm6dsox_ctrl1_xl_t reg;
cparata	0:f27ce43dee4f	203	int32_t ret;
cparata	0:f27ce43dee4f	204
cparata	0:f27ce43dee4f	205	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	206	switch (reg.fs_xl) {
cparata	0:f27ce43dee4f	207	case LSM6DSOX_2g:
cparata	0:f27ce43dee4f	208	*val = LSM6DSOX_2g;
cparata	0:f27ce43dee4f	209	break;
cparata	0:f27ce43dee4f	210	case LSM6DSOX_16g:
cparata	0:f27ce43dee4f	211	*val = LSM6DSOX_16g;
cparata	0:f27ce43dee4f	212	break;
cparata	0:f27ce43dee4f	213	case LSM6DSOX_4g:
cparata	0:f27ce43dee4f	214	*val = LSM6DSOX_4g;
cparata	0:f27ce43dee4f	215	break;
cparata	0:f27ce43dee4f	216	case LSM6DSOX_8g:
cparata	0:f27ce43dee4f	217	*val = LSM6DSOX_8g;
cparata	0:f27ce43dee4f	218	break;
cparata	0:f27ce43dee4f	219	default:
cparata	0:f27ce43dee4f	220	*val = LSM6DSOX_2g;
cparata	0:f27ce43dee4f	221	break;
cparata	0:f27ce43dee4f	222	}
cparata	0:f27ce43dee4f	223
cparata	0:f27ce43dee4f	224	return ret;
cparata	0:f27ce43dee4f	225	}
cparata	0:f27ce43dee4f	226
cparata	0:f27ce43dee4f	227	/**
cparata	0:f27ce43dee4f	228	* @brief Accelerometer UI data rate selection.[set]
cparata	0:f27ce43dee4f	229	*
cparata	0:f27ce43dee4f	230	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	231	* @param val change the values of odr_xl in reg CTRL1_XL
cparata	0:f27ce43dee4f	232	*
cparata	0:f27ce43dee4f	233	*/
cparata	0:f27ce43dee4f	234	int32_t lsm6dsox_xl_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t val)
cparata	0:f27ce43dee4f	235	{
cparata	1:fe40aec6e97a	236	lsm6dsox_odr_xl_t odr_xl = val;
cparata	1:fe40aec6e97a	237	lsm6dsox_emb_fsm_enable_t fsm_enable;
cparata	1:fe40aec6e97a	238	lsm6dsox_fsm_odr_t fsm_odr;
cparata	1:fe40aec6e97a	239	lsm6dsox_emb_sens_t emb_sens;
cparata	1:fe40aec6e97a	240	lsm6dsox_mlc_odr_t mlc_odr;
cparata	0:f27ce43dee4f	241	lsm6dsox_ctrl1_xl_t reg;
cparata	0:f27ce43dee4f	242	int32_t ret;
cparata	0:f27ce43dee4f	243
cparata	1:fe40aec6e97a	244	/* Check the Finite State Machine data rate constraints */
cparata	1:fe40aec6e97a	245	ret = lsm6dsox_fsm_enable_get(ctx, &fsm_enable);
cparata	1:fe40aec6e97a	246	if (ret == 0) {
cparata	1:fe40aec6e97a	247	if ( (fsm_enable.fsm_enable_a.fsm1_en \|
cparata	1:fe40aec6e97a	248	fsm_enable.fsm_enable_a.fsm2_en \|
cparata	1:fe40aec6e97a	249	fsm_enable.fsm_enable_a.fsm3_en \|
cparata	1:fe40aec6e97a	250	fsm_enable.fsm_enable_a.fsm4_en \|
cparata	1:fe40aec6e97a	251	fsm_enable.fsm_enable_a.fsm5_en \|
cparata	1:fe40aec6e97a	252	fsm_enable.fsm_enable_a.fsm6_en \|
cparata	1:fe40aec6e97a	253	fsm_enable.fsm_enable_a.fsm7_en \|
cparata	1:fe40aec6e97a	254	fsm_enable.fsm_enable_a.fsm8_en \|
cparata	1:fe40aec6e97a	255	fsm_enable.fsm_enable_b.fsm9_en \|
cparata	1:fe40aec6e97a	256	fsm_enable.fsm_enable_b.fsm10_en \|
cparata	1:fe40aec6e97a	257	fsm_enable.fsm_enable_b.fsm11_en \|
cparata	1:fe40aec6e97a	258	fsm_enable.fsm_enable_b.fsm12_en \|
cparata	1:fe40aec6e97a	259	fsm_enable.fsm_enable_b.fsm13_en \|
cparata	1:fe40aec6e97a	260	fsm_enable.fsm_enable_b.fsm14_en \|
cparata	1:fe40aec6e97a	261	fsm_enable.fsm_enable_b.fsm15_en \|
cparata	1:fe40aec6e97a	262	fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
cparata	1:fe40aec6e97a	263
cparata	1:fe40aec6e97a	264	ret = lsm6dsox_fsm_data_rate_get(ctx, &fsm_odr);
cparata	1:fe40aec6e97a	265	if (ret == 0) {
cparata	1:fe40aec6e97a	266	switch (fsm_odr) {
cparata	1:fe40aec6e97a	267	case LSM6DSOX_ODR_FSM_12Hz5:
cparata	1:fe40aec6e97a	268
cparata	1:fe40aec6e97a	269	if (val == LSM6DSOX_XL_ODR_OFF){
cparata	1:fe40aec6e97a	270	odr_xl = LSM6DSOX_XL_ODR_12Hz5;
cparata	1:fe40aec6e97a	271
cparata	1:fe40aec6e97a	272	} else {
cparata	1:fe40aec6e97a	273	odr_xl = val;
cparata	1:fe40aec6e97a	274	}
cparata	1:fe40aec6e97a	275	break;
cparata	1:fe40aec6e97a	276	case LSM6DSOX_ODR_FSM_26Hz:
cparata	1:fe40aec6e97a	277
cparata	1:fe40aec6e97a	278	if (val == LSM6DSOX_XL_ODR_OFF){
cparata	1:fe40aec6e97a	279	odr_xl = LSM6DSOX_XL_ODR_26Hz;
cparata	1:fe40aec6e97a	280
cparata	1:fe40aec6e97a	281	} else if (val == LSM6DSOX_XL_ODR_12Hz5){
cparata	1:fe40aec6e97a	282	odr_xl = LSM6DSOX_XL_ODR_26Hz;
cparata	1:fe40aec6e97a	283
cparata	1:fe40aec6e97a	284	} else {
cparata	1:fe40aec6e97a	285	odr_xl = val;
cparata	1:fe40aec6e97a	286	}
cparata	1:fe40aec6e97a	287	break;
cparata	1:fe40aec6e97a	288	case LSM6DSOX_ODR_FSM_52Hz:
cparata	1:fe40aec6e97a	289
cparata	1:fe40aec6e97a	290	if (val == LSM6DSOX_XL_ODR_OFF){
cparata	1:fe40aec6e97a	291	odr_xl = LSM6DSOX_XL_ODR_52Hz;
cparata	1:fe40aec6e97a	292
cparata	1:fe40aec6e97a	293	} else if (val == LSM6DSOX_XL_ODR_12Hz5){
cparata	1:fe40aec6e97a	294	odr_xl = LSM6DSOX_XL_ODR_52Hz;
cparata	1:fe40aec6e97a	295
cparata	1:fe40aec6e97a	296	} else if (val == LSM6DSOX_XL_ODR_26Hz){
cparata	1:fe40aec6e97a	297	odr_xl = LSM6DSOX_XL_ODR_52Hz;
cparata	1:fe40aec6e97a	298
cparata	1:fe40aec6e97a	299	} else {
cparata	1:fe40aec6e97a	300	odr_xl = val;
cparata	1:fe40aec6e97a	301	}
cparata	1:fe40aec6e97a	302	break;
cparata	1:fe40aec6e97a	303	case LSM6DSOX_ODR_FSM_104Hz:
cparata	1:fe40aec6e97a	304
cparata	1:fe40aec6e97a	305	if (val == LSM6DSOX_XL_ODR_OFF){
cparata	1:fe40aec6e97a	306	odr_xl = LSM6DSOX_XL_ODR_104Hz;
cparata	1:fe40aec6e97a	307
cparata	1:fe40aec6e97a	308	} else if (val == LSM6DSOX_XL_ODR_12Hz5){
cparata	1:fe40aec6e97a	309	odr_xl = LSM6DSOX_XL_ODR_104Hz;
cparata	1:fe40aec6e97a	310
cparata	1:fe40aec6e97a	311	} else if (val == LSM6DSOX_XL_ODR_26Hz){
cparata	1:fe40aec6e97a	312	odr_xl = LSM6DSOX_XL_ODR_104Hz;
cparata	1:fe40aec6e97a	313
cparata	1:fe40aec6e97a	314	} else if (val == LSM6DSOX_XL_ODR_52Hz){
cparata	1:fe40aec6e97a	315	odr_xl = LSM6DSOX_XL_ODR_104Hz;
cparata	1:fe40aec6e97a	316
cparata	1:fe40aec6e97a	317	} else {
cparata	1:fe40aec6e97a	318	odr_xl = val;
cparata	1:fe40aec6e97a	319	}
cparata	1:fe40aec6e97a	320	break;
cparata	1:fe40aec6e97a	321	default:
cparata	1:fe40aec6e97a	322	odr_xl = val;
cparata	1:fe40aec6e97a	323	break;
cparata	1:fe40aec6e97a	324	}
cparata	1:fe40aec6e97a	325	}
cparata	1:fe40aec6e97a	326	}
cparata	1:fe40aec6e97a	327	}
cparata	1:fe40aec6e97a	328
cparata	1:fe40aec6e97a	329	/* Check the Machine Learning Core data rate constraints */
cparata	1:fe40aec6e97a	330	emb_sens.mlc = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	331	if (ret == 0) {
cparata	1:fe40aec6e97a	332	lsm6dsox_embedded_sens_get(ctx, &emb_sens);
cparata	1:fe40aec6e97a	333	if ( emb_sens.mlc == PROPERTY_ENABLE ){
cparata	1:fe40aec6e97a	334
cparata	1:fe40aec6e97a	335	ret = lsm6dsox_mlc_data_rate_get(ctx, &mlc_odr);
cparata	1:fe40aec6e97a	336	if (ret == 0) {
cparata	1:fe40aec6e97a	337	switch (mlc_odr) {
cparata	1:fe40aec6e97a	338	case LSM6DSOX_ODR_PRGS_12Hz5:
cparata	1:fe40aec6e97a	339
cparata	1:fe40aec6e97a	340	if (val == LSM6DSOX_XL_ODR_OFF){
cparata	1:fe40aec6e97a	341	odr_xl = LSM6DSOX_XL_ODR_12Hz5;
cparata	1:fe40aec6e97a	342
cparata	1:fe40aec6e97a	343	} else {
cparata	1:fe40aec6e97a	344	odr_xl = val;
cparata	1:fe40aec6e97a	345	}
cparata	1:fe40aec6e97a	346	break;
cparata	1:fe40aec6e97a	347	case LSM6DSOX_ODR_PRGS_26Hz:
cparata	1:fe40aec6e97a	348	if (val == LSM6DSOX_XL_ODR_OFF){
cparata	1:fe40aec6e97a	349	odr_xl = LSM6DSOX_XL_ODR_26Hz;
cparata	1:fe40aec6e97a	350
cparata	1:fe40aec6e97a	351	} else if (val == LSM6DSOX_XL_ODR_12Hz5){
cparata	1:fe40aec6e97a	352	odr_xl = LSM6DSOX_XL_ODR_26Hz;
cparata	1:fe40aec6e97a	353
cparata	1:fe40aec6e97a	354	} else {
cparata	1:fe40aec6e97a	355	odr_xl = val;
cparata	1:fe40aec6e97a	356	}
cparata	1:fe40aec6e97a	357	break;
cparata	1:fe40aec6e97a	358	case LSM6DSOX_ODR_PRGS_52Hz:
cparata	1:fe40aec6e97a	359
cparata	1:fe40aec6e97a	360	if (val == LSM6DSOX_XL_ODR_OFF){
cparata	1:fe40aec6e97a	361	odr_xl = LSM6DSOX_XL_ODR_52Hz;
cparata	1:fe40aec6e97a	362
cparata	1:fe40aec6e97a	363	} else if (val == LSM6DSOX_XL_ODR_12Hz5){
cparata	1:fe40aec6e97a	364	odr_xl = LSM6DSOX_XL_ODR_52Hz;
cparata	1:fe40aec6e97a	365
cparata	1:fe40aec6e97a	366	} else if (val == LSM6DSOX_XL_ODR_26Hz){
cparata	1:fe40aec6e97a	367	odr_xl = LSM6DSOX_XL_ODR_52Hz;
cparata	1:fe40aec6e97a	368
cparata	1:fe40aec6e97a	369	} else {
cparata	1:fe40aec6e97a	370	odr_xl = val;
cparata	1:fe40aec6e97a	371	}
cparata	1:fe40aec6e97a	372	break;
cparata	1:fe40aec6e97a	373	case LSM6DSOX_ODR_PRGS_104Hz:
cparata	1:fe40aec6e97a	374	if (val == LSM6DSOX_XL_ODR_OFF){
cparata	1:fe40aec6e97a	375	odr_xl = LSM6DSOX_XL_ODR_104Hz;
cparata	1:fe40aec6e97a	376
cparata	1:fe40aec6e97a	377	} else if (val == LSM6DSOX_XL_ODR_12Hz5){
cparata	1:fe40aec6e97a	378	odr_xl = LSM6DSOX_XL_ODR_104Hz;
cparata	1:fe40aec6e97a	379
cparata	1:fe40aec6e97a	380	} else if (val == LSM6DSOX_XL_ODR_26Hz){
cparata	1:fe40aec6e97a	381	odr_xl = LSM6DSOX_XL_ODR_104Hz;
cparata	1:fe40aec6e97a	382
cparata	1:fe40aec6e97a	383	} else if (val == LSM6DSOX_XL_ODR_52Hz){
cparata	1:fe40aec6e97a	384	odr_xl = LSM6DSOX_XL_ODR_104Hz;
cparata	1:fe40aec6e97a	385
cparata	1:fe40aec6e97a	386	} else {
cparata	1:fe40aec6e97a	387	odr_xl = val;
cparata	1:fe40aec6e97a	388	}
cparata	1:fe40aec6e97a	389	break;
cparata	1:fe40aec6e97a	390	default:
cparata	1:fe40aec6e97a	391	odr_xl = val;
cparata	1:fe40aec6e97a	392	break;
cparata	1:fe40aec6e97a	393	}
cparata	1:fe40aec6e97a	394	}
cparata	1:fe40aec6e97a	395	}
cparata	1:fe40aec6e97a	396	}
cparata	1:fe40aec6e97a	397	if (ret == 0) {
cparata	1:fe40aec6e97a	398	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	1:fe40aec6e97a	399	}
cparata	1:fe40aec6e97a	400	if (ret == 0) {
cparata	1:fe40aec6e97a	401	reg.odr_xl = (uint8_t) odr_xl;
cparata	0:f27ce43dee4f	402	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	403	}
cparata	0:f27ce43dee4f	404	return ret;
cparata	0:f27ce43dee4f	405	}
cparata	0:f27ce43dee4f	406
cparata	0:f27ce43dee4f	407	/**
cparata	0:f27ce43dee4f	408	* @brief Accelerometer UI data rate selection.[get]
cparata	0:f27ce43dee4f	409	*
cparata	0:f27ce43dee4f	410	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	411	* @param val Get the values of odr_xl in reg CTRL1_XL
cparata	0:f27ce43dee4f	412	*
cparata	0:f27ce43dee4f	413	*/
cparata	0:f27ce43dee4f	414	int32_t lsm6dsox_xl_data_rate_get(lsm6dsox_ctx_t ctx, lsm6dsox_odr_xl_t val)
cparata	0:f27ce43dee4f	415	{
cparata	0:f27ce43dee4f	416	lsm6dsox_ctrl1_xl_t reg;
cparata	0:f27ce43dee4f	417	int32_t ret;
cparata	0:f27ce43dee4f	418
cparata	0:f27ce43dee4f	419	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	420
cparata	0:f27ce43dee4f	421	switch (reg.odr_xl) {
cparata	0:f27ce43dee4f	422	case LSM6DSOX_XL_ODR_OFF:
cparata	0:f27ce43dee4f	423	*val = LSM6DSOX_XL_ODR_OFF;
cparata	0:f27ce43dee4f	424	break;
cparata	0:f27ce43dee4f	425	case LSM6DSOX_XL_ODR_12Hz5:
cparata	0:f27ce43dee4f	426	*val = LSM6DSOX_XL_ODR_12Hz5;
cparata	0:f27ce43dee4f	427	break;
cparata	0:f27ce43dee4f	428	case LSM6DSOX_XL_ODR_26Hz:
cparata	0:f27ce43dee4f	429	*val = LSM6DSOX_XL_ODR_26Hz;
cparata	0:f27ce43dee4f	430	break;
cparata	0:f27ce43dee4f	431	case LSM6DSOX_XL_ODR_52Hz:
cparata	0:f27ce43dee4f	432	*val = LSM6DSOX_XL_ODR_52Hz;
cparata	0:f27ce43dee4f	433	break;
cparata	0:f27ce43dee4f	434	case LSM6DSOX_XL_ODR_104Hz:
cparata	0:f27ce43dee4f	435	*val = LSM6DSOX_XL_ODR_104Hz;
cparata	0:f27ce43dee4f	436	break;
cparata	0:f27ce43dee4f	437	case LSM6DSOX_XL_ODR_208Hz:
cparata	0:f27ce43dee4f	438	*val = LSM6DSOX_XL_ODR_208Hz;
cparata	0:f27ce43dee4f	439	break;
cparata	0:f27ce43dee4f	440	case LSM6DSOX_XL_ODR_417Hz:
cparata	0:f27ce43dee4f	441	*val = LSM6DSOX_XL_ODR_417Hz;
cparata	0:f27ce43dee4f	442	break;
cparata	0:f27ce43dee4f	443	case LSM6DSOX_XL_ODR_833Hz:
cparata	0:f27ce43dee4f	444	*val = LSM6DSOX_XL_ODR_833Hz;
cparata	0:f27ce43dee4f	445	break;
cparata	0:f27ce43dee4f	446	case LSM6DSOX_XL_ODR_1667Hz:
cparata	0:f27ce43dee4f	447	*val = LSM6DSOX_XL_ODR_1667Hz;
cparata	0:f27ce43dee4f	448	break;
cparata	0:f27ce43dee4f	449	case LSM6DSOX_XL_ODR_3333Hz:
cparata	0:f27ce43dee4f	450	*val = LSM6DSOX_XL_ODR_3333Hz;
cparata	0:f27ce43dee4f	451	break;
cparata	0:f27ce43dee4f	452	case LSM6DSOX_XL_ODR_6667Hz:
cparata	0:f27ce43dee4f	453	*val = LSM6DSOX_XL_ODR_6667Hz;
cparata	0:f27ce43dee4f	454	break;
cparata	1:fe40aec6e97a	455	case LSM6DSOX_XL_ODR_1Hz6:
cparata	1:fe40aec6e97a	456	*val = LSM6DSOX_XL_ODR_1Hz6;
cparata	0:f27ce43dee4f	457	break;
cparata	0:f27ce43dee4f	458	default:
cparata	0:f27ce43dee4f	459	*val = LSM6DSOX_XL_ODR_OFF;
cparata	0:f27ce43dee4f	460	break;
cparata	0:f27ce43dee4f	461	}
cparata	0:f27ce43dee4f	462	return ret;
cparata	0:f27ce43dee4f	463	}
cparata	0:f27ce43dee4f	464
cparata	0:f27ce43dee4f	465	/**
cparata	0:f27ce43dee4f	466	* @brief Gyroscope UI chain full-scale selection.[set]
cparata	0:f27ce43dee4f	467	*
cparata	0:f27ce43dee4f	468	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	469	* @param val change the values of fs_g in reg CTRL2_G
cparata	0:f27ce43dee4f	470	*
cparata	0:f27ce43dee4f	471	*/
cparata	0:f27ce43dee4f	472	int32_t lsm6dsox_gy_full_scale_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t val)
cparata	0:f27ce43dee4f	473	{
cparata	0:f27ce43dee4f	474	lsm6dsox_ctrl2_g_t reg;
cparata	0:f27ce43dee4f	475	int32_t ret;
cparata	0:f27ce43dee4f	476
cparata	0:f27ce43dee4f	477	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	478	if (ret == 0) {
cparata	0:f27ce43dee4f	479	reg.fs_g = (uint8_t) val;
cparata	0:f27ce43dee4f	480	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	481	}
cparata	0:f27ce43dee4f	482
cparata	0:f27ce43dee4f	483	return ret;
cparata	0:f27ce43dee4f	484	}
cparata	0:f27ce43dee4f	485
cparata	0:f27ce43dee4f	486	/**
cparata	0:f27ce43dee4f	487	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:f27ce43dee4f	488	*
cparata	0:f27ce43dee4f	489	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	490	* @param val Get the values of fs_g in reg CTRL2_G
cparata	0:f27ce43dee4f	491	*
cparata	0:f27ce43dee4f	492	*/
cparata	0:f27ce43dee4f	493	int32_t lsm6dsox_gy_full_scale_get(lsm6dsox_ctx_t ctx, lsm6dsox_fs_g_t val)
cparata	0:f27ce43dee4f	494	{
cparata	0:f27ce43dee4f	495	lsm6dsox_ctrl2_g_t reg;
cparata	0:f27ce43dee4f	496	int32_t ret;
cparata	0:f27ce43dee4f	497
cparata	0:f27ce43dee4f	498	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	499	switch (reg.fs_g) {
cparata	0:f27ce43dee4f	500	case LSM6DSOX_250dps:
cparata	0:f27ce43dee4f	501	*val = LSM6DSOX_250dps;
cparata	0:f27ce43dee4f	502	break;
cparata	0:f27ce43dee4f	503	case LSM6DSOX_125dps:
cparata	0:f27ce43dee4f	504	*val = LSM6DSOX_125dps;
cparata	0:f27ce43dee4f	505	break;
cparata	0:f27ce43dee4f	506	case LSM6DSOX_500dps:
cparata	0:f27ce43dee4f	507	*val = LSM6DSOX_500dps;
cparata	0:f27ce43dee4f	508	break;
cparata	0:f27ce43dee4f	509	case LSM6DSOX_1000dps:
cparata	0:f27ce43dee4f	510	*val = LSM6DSOX_1000dps;
cparata	0:f27ce43dee4f	511	break;
cparata	0:f27ce43dee4f	512	case LSM6DSOX_2000dps:
cparata	0:f27ce43dee4f	513	*val = LSM6DSOX_2000dps;
cparata	0:f27ce43dee4f	514	break;
cparata	0:f27ce43dee4f	515	default:
cparata	0:f27ce43dee4f	516	*val = LSM6DSOX_250dps;
cparata	0:f27ce43dee4f	517	break;
cparata	0:f27ce43dee4f	518	}
cparata	0:f27ce43dee4f	519
cparata	0:f27ce43dee4f	520	return ret;
cparata	0:f27ce43dee4f	521	}
cparata	0:f27ce43dee4f	522
cparata	0:f27ce43dee4f	523	/**
cparata	0:f27ce43dee4f	524	* @brief Gyroscope UI data rate selection.[set]
cparata	0:f27ce43dee4f	525	*
cparata	0:f27ce43dee4f	526	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	527	* @param val change the values of odr_g in reg CTRL2_G
cparata	0:f27ce43dee4f	528	*
cparata	0:f27ce43dee4f	529	*/
cparata	0:f27ce43dee4f	530	int32_t lsm6dsox_gy_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t val)
cparata	0:f27ce43dee4f	531	{
cparata	1:fe40aec6e97a	532	lsm6dsox_odr_g_t odr_gy = val;
cparata	1:fe40aec6e97a	533	lsm6dsox_emb_fsm_enable_t fsm_enable;
cparata	1:fe40aec6e97a	534	lsm6dsox_fsm_odr_t fsm_odr;
cparata	1:fe40aec6e97a	535	lsm6dsox_emb_sens_t emb_sens;
cparata	1:fe40aec6e97a	536	lsm6dsox_mlc_odr_t mlc_odr;
cparata	0:f27ce43dee4f	537	lsm6dsox_ctrl2_g_t reg;
cparata	0:f27ce43dee4f	538	int32_t ret;
cparata	0:f27ce43dee4f	539
cparata	1:fe40aec6e97a	540	/* Check the Finite State Machine data rate constraints */
cparata	1:fe40aec6e97a	541	ret = lsm6dsox_fsm_enable_get(ctx, &fsm_enable);
cparata	1:fe40aec6e97a	542	if (ret == 0) {
cparata	1:fe40aec6e97a	543	if ( (fsm_enable.fsm_enable_a.fsm1_en \|
cparata	1:fe40aec6e97a	544	fsm_enable.fsm_enable_a.fsm2_en \|
cparata	1:fe40aec6e97a	545	fsm_enable.fsm_enable_a.fsm3_en \|
cparata	1:fe40aec6e97a	546	fsm_enable.fsm_enable_a.fsm4_en \|
cparata	1:fe40aec6e97a	547	fsm_enable.fsm_enable_a.fsm5_en \|
cparata	1:fe40aec6e97a	548	fsm_enable.fsm_enable_a.fsm6_en \|
cparata	1:fe40aec6e97a	549	fsm_enable.fsm_enable_a.fsm7_en \|
cparata	1:fe40aec6e97a	550	fsm_enable.fsm_enable_a.fsm8_en \|
cparata	1:fe40aec6e97a	551	fsm_enable.fsm_enable_b.fsm9_en \|
cparata	1:fe40aec6e97a	552	fsm_enable.fsm_enable_b.fsm10_en \|
cparata	1:fe40aec6e97a	553	fsm_enable.fsm_enable_b.fsm11_en \|
cparata	1:fe40aec6e97a	554	fsm_enable.fsm_enable_b.fsm12_en \|
cparata	1:fe40aec6e97a	555	fsm_enable.fsm_enable_b.fsm13_en \|
cparata	1:fe40aec6e97a	556	fsm_enable.fsm_enable_b.fsm14_en \|
cparata	1:fe40aec6e97a	557	fsm_enable.fsm_enable_b.fsm15_en \|
cparata	1:fe40aec6e97a	558	fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
cparata	1:fe40aec6e97a	559
cparata	1:fe40aec6e97a	560	ret = lsm6dsox_fsm_data_rate_get(ctx, &fsm_odr);
cparata	1:fe40aec6e97a	561	if (ret == 0) {
cparata	1:fe40aec6e97a	562	switch (fsm_odr) {
cparata	1:fe40aec6e97a	563	case LSM6DSOX_ODR_FSM_12Hz5:
cparata	1:fe40aec6e97a	564
cparata	1:fe40aec6e97a	565	if (val == LSM6DSOX_GY_ODR_OFF){
cparata	1:fe40aec6e97a	566	odr_gy = LSM6DSOX_GY_ODR_12Hz5;
cparata	1:fe40aec6e97a	567
cparata	1:fe40aec6e97a	568	} else {
cparata	1:fe40aec6e97a	569	odr_gy = val;
cparata	1:fe40aec6e97a	570	}
cparata	1:fe40aec6e97a	571	break;
cparata	1:fe40aec6e97a	572	case LSM6DSOX_ODR_FSM_26Hz:
cparata	1:fe40aec6e97a	573
cparata	1:fe40aec6e97a	574	if (val == LSM6DSOX_GY_ODR_OFF){
cparata	1:fe40aec6e97a	575	odr_gy = LSM6DSOX_GY_ODR_26Hz;
cparata	1:fe40aec6e97a	576
cparata	1:fe40aec6e97a	577	} else if (val == LSM6DSOX_GY_ODR_12Hz5){
cparata	1:fe40aec6e97a	578	odr_gy = LSM6DSOX_GY_ODR_26Hz;
cparata	1:fe40aec6e97a	579
cparata	1:fe40aec6e97a	580	} else {
cparata	1:fe40aec6e97a	581	odr_gy = val;
cparata	1:fe40aec6e97a	582	}
cparata	1:fe40aec6e97a	583	break;
cparata	1:fe40aec6e97a	584	case LSM6DSOX_ODR_FSM_52Hz:
cparata	1:fe40aec6e97a	585
cparata	1:fe40aec6e97a	586	if (val == LSM6DSOX_GY_ODR_OFF){
cparata	1:fe40aec6e97a	587	odr_gy = LSM6DSOX_GY_ODR_52Hz;
cparata	1:fe40aec6e97a	588
cparata	1:fe40aec6e97a	589	} else if (val == LSM6DSOX_GY_ODR_12Hz5){
cparata	1:fe40aec6e97a	590	odr_gy = LSM6DSOX_GY_ODR_52Hz;
cparata	1:fe40aec6e97a	591
cparata	1:fe40aec6e97a	592	} else if (val == LSM6DSOX_GY_ODR_26Hz){
cparata	1:fe40aec6e97a	593	odr_gy = LSM6DSOX_GY_ODR_52Hz;
cparata	1:fe40aec6e97a	594
cparata	1:fe40aec6e97a	595	} else {
cparata	1:fe40aec6e97a	596	odr_gy = val;
cparata	1:fe40aec6e97a	597	}
cparata	1:fe40aec6e97a	598	break;
cparata	1:fe40aec6e97a	599	case LSM6DSOX_ODR_FSM_104Hz:
cparata	1:fe40aec6e97a	600
cparata	1:fe40aec6e97a	601	if (val == LSM6DSOX_GY_ODR_OFF){
cparata	1:fe40aec6e97a	602	odr_gy = LSM6DSOX_GY_ODR_104Hz;
cparata	1:fe40aec6e97a	603
cparata	1:fe40aec6e97a	604	} else if (val == LSM6DSOX_GY_ODR_12Hz5){
cparata	1:fe40aec6e97a	605	odr_gy = LSM6DSOX_GY_ODR_104Hz;
cparata	1:fe40aec6e97a	606
cparata	1:fe40aec6e97a	607	} else if (val == LSM6DSOX_GY_ODR_26Hz){
cparata	1:fe40aec6e97a	608	odr_gy = LSM6DSOX_GY_ODR_104Hz;
cparata	1:fe40aec6e97a	609
cparata	1:fe40aec6e97a	610	} else if (val == LSM6DSOX_GY_ODR_52Hz){
cparata	1:fe40aec6e97a	611	odr_gy = LSM6DSOX_GY_ODR_104Hz;
cparata	1:fe40aec6e97a	612
cparata	1:fe40aec6e97a	613	} else {
cparata	1:fe40aec6e97a	614	odr_gy = val;
cparata	1:fe40aec6e97a	615	}
cparata	1:fe40aec6e97a	616	break;
cparata	1:fe40aec6e97a	617	default:
cparata	1:fe40aec6e97a	618	odr_gy = val;
cparata	1:fe40aec6e97a	619	break;
cparata	1:fe40aec6e97a	620	}
cparata	1:fe40aec6e97a	621	}
cparata	1:fe40aec6e97a	622	}
cparata	1:fe40aec6e97a	623	}
cparata	1:fe40aec6e97a	624
cparata	1:fe40aec6e97a	625	/* Check the Machine Learning Core data rate constraints */
cparata	1:fe40aec6e97a	626	emb_sens.mlc = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	627	if (ret == 0) {
cparata	1:fe40aec6e97a	628	ret = lsm6dsox_embedded_sens_get(ctx, &emb_sens);
cparata	1:fe40aec6e97a	629	if ( emb_sens.mlc == PROPERTY_ENABLE ){
cparata	1:fe40aec6e97a	630
cparata	1:fe40aec6e97a	631	ret = lsm6dsox_mlc_data_rate_get(ctx, &mlc_odr);
cparata	1:fe40aec6e97a	632	if (ret == 0) {
cparata	1:fe40aec6e97a	633	switch (mlc_odr) {
cparata	1:fe40aec6e97a	634	case LSM6DSOX_ODR_PRGS_12Hz5:
cparata	1:fe40aec6e97a	635
cparata	1:fe40aec6e97a	636	if (val == LSM6DSOX_GY_ODR_OFF){
cparata	1:fe40aec6e97a	637	odr_gy = LSM6DSOX_GY_ODR_12Hz5;
cparata	1:fe40aec6e97a	638
cparata	1:fe40aec6e97a	639	} else {
cparata	1:fe40aec6e97a	640	odr_gy = val;
cparata	1:fe40aec6e97a	641	}
cparata	1:fe40aec6e97a	642	break;
cparata	1:fe40aec6e97a	643	case LSM6DSOX_ODR_PRGS_26Hz:
cparata	1:fe40aec6e97a	644
cparata	1:fe40aec6e97a	645	if (val == LSM6DSOX_GY_ODR_OFF){
cparata	1:fe40aec6e97a	646	odr_gy = LSM6DSOX_GY_ODR_26Hz;
cparata	1:fe40aec6e97a	647
cparata	1:fe40aec6e97a	648	} else if (val == LSM6DSOX_GY_ODR_12Hz5){
cparata	1:fe40aec6e97a	649	odr_gy = LSM6DSOX_GY_ODR_26Hz;
cparata	1:fe40aec6e97a	650
cparata	1:fe40aec6e97a	651	} else {
cparata	1:fe40aec6e97a	652	odr_gy = val;
cparata	1:fe40aec6e97a	653	}
cparata	1:fe40aec6e97a	654	break;
cparata	1:fe40aec6e97a	655	case LSM6DSOX_ODR_PRGS_52Hz:
cparata	1:fe40aec6e97a	656
cparata	1:fe40aec6e97a	657	if (val == LSM6DSOX_GY_ODR_OFF){
cparata	1:fe40aec6e97a	658	odr_gy = LSM6DSOX_GY_ODR_52Hz;
cparata	1:fe40aec6e97a	659
cparata	1:fe40aec6e97a	660	} else if (val == LSM6DSOX_GY_ODR_12Hz5){
cparata	1:fe40aec6e97a	661	odr_gy = LSM6DSOX_GY_ODR_52Hz;
cparata	1:fe40aec6e97a	662
cparata	1:fe40aec6e97a	663	} else if (val == LSM6DSOX_GY_ODR_26Hz){
cparata	1:fe40aec6e97a	664	odr_gy = LSM6DSOX_GY_ODR_52Hz;
cparata	1:fe40aec6e97a	665
cparata	1:fe40aec6e97a	666	} else {
cparata	1:fe40aec6e97a	667	odr_gy = val;
cparata	1:fe40aec6e97a	668	}
cparata	1:fe40aec6e97a	669	break;
cparata	1:fe40aec6e97a	670	case LSM6DSOX_ODR_PRGS_104Hz:
cparata	1:fe40aec6e97a	671
cparata	1:fe40aec6e97a	672	if (val == LSM6DSOX_GY_ODR_OFF){
cparata	1:fe40aec6e97a	673	odr_gy = LSM6DSOX_GY_ODR_104Hz;
cparata	1:fe40aec6e97a	674
cparata	1:fe40aec6e97a	675	} else if (val == LSM6DSOX_GY_ODR_12Hz5){
cparata	1:fe40aec6e97a	676	odr_gy = LSM6DSOX_GY_ODR_104Hz;
cparata	1:fe40aec6e97a	677
cparata	1:fe40aec6e97a	678	} else if (val == LSM6DSOX_GY_ODR_26Hz){
cparata	1:fe40aec6e97a	679	odr_gy = LSM6DSOX_GY_ODR_104Hz;
cparata	1:fe40aec6e97a	680
cparata	1:fe40aec6e97a	681	} else if (val == LSM6DSOX_GY_ODR_52Hz){
cparata	1:fe40aec6e97a	682	odr_gy = LSM6DSOX_GY_ODR_104Hz;
cparata	1:fe40aec6e97a	683
cparata	1:fe40aec6e97a	684	} else {
cparata	1:fe40aec6e97a	685	odr_gy = val;
cparata	1:fe40aec6e97a	686	}
cparata	1:fe40aec6e97a	687	break;
cparata	1:fe40aec6e97a	688	default:
cparata	1:fe40aec6e97a	689	odr_gy = val;
cparata	1:fe40aec6e97a	690	break;
cparata	1:fe40aec6e97a	691	}
cparata	1:fe40aec6e97a	692	}
cparata	1:fe40aec6e97a	693	}
cparata	1:fe40aec6e97a	694	}
cparata	1:fe40aec6e97a	695	if (ret == 0) {
cparata	1:fe40aec6e97a	696	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata	1:fe40aec6e97a	697	}
cparata	1:fe40aec6e97a	698	if (ret == 0) {
cparata	1:fe40aec6e97a	699	reg.odr_g = (uint8_t) odr_gy;
cparata	0:f27ce43dee4f	700	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	701	}
cparata	0:f27ce43dee4f	702
cparata	0:f27ce43dee4f	703	return ret;
cparata	0:f27ce43dee4f	704	}
cparata	0:f27ce43dee4f	705
cparata	0:f27ce43dee4f	706	/**
cparata	0:f27ce43dee4f	707	* @brief Gyroscope UI data rate selection.[get]
cparata	0:f27ce43dee4f	708	*
cparata	0:f27ce43dee4f	709	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	710	* @param val Get the values of odr_g in reg CTRL2_G
cparata	0:f27ce43dee4f	711	*
cparata	0:f27ce43dee4f	712	*/
cparata	0:f27ce43dee4f	713	int32_t lsm6dsox_gy_data_rate_get(lsm6dsox_ctx_t ctx, lsm6dsox_odr_g_t val)
cparata	0:f27ce43dee4f	714	{
cparata	0:f27ce43dee4f	715	lsm6dsox_ctrl2_g_t reg;
cparata	0:f27ce43dee4f	716	int32_t ret;
cparata	0:f27ce43dee4f	717
cparata	0:f27ce43dee4f	718	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	719	switch (reg.odr_g) {
cparata	0:f27ce43dee4f	720	case LSM6DSOX_GY_ODR_OFF:
cparata	0:f27ce43dee4f	721	*val = LSM6DSOX_GY_ODR_OFF;
cparata	0:f27ce43dee4f	722	break;
cparata	0:f27ce43dee4f	723	case LSM6DSOX_GY_ODR_12Hz5:
cparata	0:f27ce43dee4f	724	*val = LSM6DSOX_GY_ODR_12Hz5;
cparata	0:f27ce43dee4f	725	break;
cparata	0:f27ce43dee4f	726	case LSM6DSOX_GY_ODR_26Hz:
cparata	0:f27ce43dee4f	727	*val = LSM6DSOX_GY_ODR_26Hz;
cparata	0:f27ce43dee4f	728	break;
cparata	0:f27ce43dee4f	729	case LSM6DSOX_GY_ODR_52Hz:
cparata	0:f27ce43dee4f	730	*val = LSM6DSOX_GY_ODR_52Hz;
cparata	0:f27ce43dee4f	731	break;
cparata	0:f27ce43dee4f	732	case LSM6DSOX_GY_ODR_104Hz:
cparata	0:f27ce43dee4f	733	*val = LSM6DSOX_GY_ODR_104Hz;
cparata	0:f27ce43dee4f	734	break;
cparata	0:f27ce43dee4f	735	case LSM6DSOX_GY_ODR_208Hz:
cparata	0:f27ce43dee4f	736	*val = LSM6DSOX_GY_ODR_208Hz;
cparata	0:f27ce43dee4f	737	break;
cparata	0:f27ce43dee4f	738	case LSM6DSOX_GY_ODR_417Hz:
cparata	0:f27ce43dee4f	739	*val = LSM6DSOX_GY_ODR_417Hz;
cparata	0:f27ce43dee4f	740	break;
cparata	0:f27ce43dee4f	741	case LSM6DSOX_GY_ODR_833Hz:
cparata	0:f27ce43dee4f	742	*val = LSM6DSOX_GY_ODR_833Hz;
cparata	0:f27ce43dee4f	743	break;
cparata	0:f27ce43dee4f	744	case LSM6DSOX_GY_ODR_1667Hz:
cparata	0:f27ce43dee4f	745	*val = LSM6DSOX_GY_ODR_1667Hz;
cparata	0:f27ce43dee4f	746	break;
cparata	0:f27ce43dee4f	747	case LSM6DSOX_GY_ODR_3333Hz:
cparata	0:f27ce43dee4f	748	*val = LSM6DSOX_GY_ODR_3333Hz;
cparata	0:f27ce43dee4f	749	break;
cparata	0:f27ce43dee4f	750	case LSM6DSOX_GY_ODR_6667Hz:
cparata	0:f27ce43dee4f	751	*val = LSM6DSOX_GY_ODR_6667Hz;
cparata	0:f27ce43dee4f	752	break;
cparata	0:f27ce43dee4f	753	default:
cparata	0:f27ce43dee4f	754	*val = LSM6DSOX_GY_ODR_OFF;
cparata	0:f27ce43dee4f	755	break;
cparata	0:f27ce43dee4f	756	}
cparata	0:f27ce43dee4f	757	return ret;
cparata	0:f27ce43dee4f	758	}
cparata	0:f27ce43dee4f	759
cparata	0:f27ce43dee4f	760	/**
cparata	0:f27ce43dee4f	761	* @brief Block data update.[set]
cparata	0:f27ce43dee4f	762	*
cparata	0:f27ce43dee4f	763	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	764	* @param val change the values of bdu in reg CTRL3_C
cparata	0:f27ce43dee4f	765	*
cparata	0:f27ce43dee4f	766	*/
cparata	0:f27ce43dee4f	767	int32_t lsm6dsox_block_data_update_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	768	{
cparata	0:f27ce43dee4f	769	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	770	int32_t ret;
cparata	0:f27ce43dee4f	771
cparata	0:f27ce43dee4f	772	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	773	if (ret == 0) {
cparata	0:f27ce43dee4f	774	reg.bdu = val;
cparata	0:f27ce43dee4f	775	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	776	}
cparata	0:f27ce43dee4f	777	return ret;
cparata	0:f27ce43dee4f	778	}
cparata	0:f27ce43dee4f	779
cparata	0:f27ce43dee4f	780	/**
cparata	0:f27ce43dee4f	781	* @brief Block data update.[get]
cparata	0:f27ce43dee4f	782	*
cparata	0:f27ce43dee4f	783	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	784	* @param val change the values of bdu in reg CTRL3_C
cparata	0:f27ce43dee4f	785	*
cparata	0:f27ce43dee4f	786	*/
cparata	0:f27ce43dee4f	787	int32_t lsm6dsox_block_data_update_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	788	{
cparata	0:f27ce43dee4f	789	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	790	int32_t ret;
cparata	0:f27ce43dee4f	791
cparata	0:f27ce43dee4f	792	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	793	*val = reg.bdu;
cparata	0:f27ce43dee4f	794
cparata	0:f27ce43dee4f	795	return ret;
cparata	0:f27ce43dee4f	796	}
cparata	0:f27ce43dee4f	797
cparata	0:f27ce43dee4f	798	/**
cparata	0:f27ce43dee4f	799	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:f27ce43dee4f	800	* Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
cparata	0:f27ce43dee4f	801	*
cparata	0:f27ce43dee4f	802	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	803	* @param val change the values of usr_off_w in reg CTRL6_C
cparata	0:f27ce43dee4f	804	*
cparata	0:f27ce43dee4f	805	*/
cparata	0:f27ce43dee4f	806	int32_t lsm6dsox_xl_offset_weight_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	807	lsm6dsox_usr_off_w_t val)
cparata	0:f27ce43dee4f	808	{
cparata	0:f27ce43dee4f	809	lsm6dsox_ctrl6_c_t reg;
cparata	0:f27ce43dee4f	810	int32_t ret;
cparata	0:f27ce43dee4f	811
cparata	0:f27ce43dee4f	812	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	813	if (ret == 0) {
cparata	0:f27ce43dee4f	814	reg.usr_off_w = (uint8_t)val;
cparata	0:f27ce43dee4f	815	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	816	}
cparata	0:f27ce43dee4f	817	return ret;
cparata	0:f27ce43dee4f	818	}
cparata	0:f27ce43dee4f	819
cparata	0:f27ce43dee4f	820	/**
cparata	0:f27ce43dee4f	821	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:f27ce43dee4f	822	* Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
cparata	0:f27ce43dee4f	823	*
cparata	0:f27ce43dee4f	824	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	825	* @param val Get the values of usr_off_w in reg CTRL6_C
cparata	0:f27ce43dee4f	826	*
cparata	0:f27ce43dee4f	827	*/
cparata	0:f27ce43dee4f	828	int32_t lsm6dsox_xl_offset_weight_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	829	lsm6dsox_usr_off_w_t *val)
cparata	0:f27ce43dee4f	830	{
cparata	0:f27ce43dee4f	831	lsm6dsox_ctrl6_c_t reg;
cparata	0:f27ce43dee4f	832	int32_t ret;
cparata	0:f27ce43dee4f	833
cparata	0:f27ce43dee4f	834	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	835
cparata	0:f27ce43dee4f	836	switch (reg.usr_off_w) {
cparata	0:f27ce43dee4f	837	case LSM6DSOX_LSb_1mg:
cparata	0:f27ce43dee4f	838	*val = LSM6DSOX_LSb_1mg;
cparata	0:f27ce43dee4f	839	break;
cparata	0:f27ce43dee4f	840	case LSM6DSOX_LSb_16mg:
cparata	0:f27ce43dee4f	841	*val = LSM6DSOX_LSb_16mg;
cparata	0:f27ce43dee4f	842	break;
cparata	0:f27ce43dee4f	843	default:
cparata	0:f27ce43dee4f	844	*val = LSM6DSOX_LSb_1mg;
cparata	0:f27ce43dee4f	845	break;
cparata	0:f27ce43dee4f	846	}
cparata	0:f27ce43dee4f	847	return ret;
cparata	0:f27ce43dee4f	848	}
cparata	0:f27ce43dee4f	849
cparata	0:f27ce43dee4f	850	/**
cparata	0:f27ce43dee4f	851	* @brief Accelerometer power mode.[set]
cparata	0:f27ce43dee4f	852	*
cparata	0:f27ce43dee4f	853	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	854	* @param val change the values of xl_hm_mode in
cparata	0:f27ce43dee4f	855	* reg CTRL6_C
cparata	0:f27ce43dee4f	856	*
cparata	0:f27ce43dee4f	857	*/
cparata	0:f27ce43dee4f	858	int32_t lsm6dsox_xl_power_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	859	lsm6dsox_xl_hm_mode_t val)
cparata	0:f27ce43dee4f	860	{
cparata	0:f27ce43dee4f	861	lsm6dsox_ctrl5_c_t ctrl5_c;
cparata	0:f27ce43dee4f	862	lsm6dsox_ctrl6_c_t ctrl6_c;
cparata	0:f27ce43dee4f	863	int32_t ret;
cparata	0:f27ce43dee4f	864
cparata	0:f27ce43dee4f	865	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	0:f27ce43dee4f	866	if (ret == 0) {
cparata	0:f27ce43dee4f	867	ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
cparata	0:f27ce43dee4f	868	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	0:f27ce43dee4f	869	}
cparata	0:f27ce43dee4f	870	if (ret == 0) {
cparata	0:f27ce43dee4f	871	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	0:f27ce43dee4f	872	}
cparata	0:f27ce43dee4f	873	if (ret == 0) {
cparata	0:f27ce43dee4f	874	ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
cparata	0:f27ce43dee4f	875	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	0:f27ce43dee4f	876	}
cparata	0:f27ce43dee4f	877	return ret;
cparata	0:f27ce43dee4f	878	}
cparata	0:f27ce43dee4f	879
cparata	0:f27ce43dee4f	880	/**
cparata	0:f27ce43dee4f	881	* @brief Accelerometer power mode.[get]
cparata	0:f27ce43dee4f	882	*
cparata	0:f27ce43dee4f	883	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	884	* @param val Get the values of xl_hm_mode in reg CTRL6_C
cparata	0:f27ce43dee4f	885	*
cparata	0:f27ce43dee4f	886	*/
cparata	0:f27ce43dee4f	887	int32_t lsm6dsox_xl_power_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	888	lsm6dsox_xl_hm_mode_t *val)
cparata	0:f27ce43dee4f	889	{
cparata	0:f27ce43dee4f	890	lsm6dsox_ctrl5_c_t ctrl5_c;
cparata	0:f27ce43dee4f	891	lsm6dsox_ctrl6_c_t ctrl6_c;
cparata	0:f27ce43dee4f	892	int32_t ret;
cparata	0:f27ce43dee4f	893
cparata	0:f27ce43dee4f	894	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	0:f27ce43dee4f	895	if (ret == 0) {
cparata	0:f27ce43dee4f	896	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	0:f27ce43dee4f	897	switch ( (ctrl5_c.xl_ulp_en << 1) \| ctrl6_c.xl_hm_mode) {
cparata	0:f27ce43dee4f	898	case LSM6DSOX_HIGH_PERFORMANCE_MD:
cparata	0:f27ce43dee4f	899	*val = LSM6DSOX_HIGH_PERFORMANCE_MD;
cparata	0:f27ce43dee4f	900	break;
cparata	0:f27ce43dee4f	901	case LSM6DSOX_LOW_NORMAL_POWER_MD:
cparata	0:f27ce43dee4f	902	*val = LSM6DSOX_LOW_NORMAL_POWER_MD;
cparata	0:f27ce43dee4f	903	break;
cparata	0:f27ce43dee4f	904	case LSM6DSOX_ULTRA_LOW_POWER_MD:
cparata	0:f27ce43dee4f	905	*val = LSM6DSOX_ULTRA_LOW_POWER_MD;
cparata	0:f27ce43dee4f	906	break;
cparata	0:f27ce43dee4f	907	default:
cparata	0:f27ce43dee4f	908	*val = LSM6DSOX_HIGH_PERFORMANCE_MD;
cparata	0:f27ce43dee4f	909	break;
cparata	0:f27ce43dee4f	910	}
cparata	0:f27ce43dee4f	911	}
cparata	0:f27ce43dee4f	912	return ret;
cparata	0:f27ce43dee4f	913	}
cparata	0:f27ce43dee4f	914
cparata	0:f27ce43dee4f	915	/**
cparata	0:f27ce43dee4f	916	* @brief Operating mode for gyroscope.[set]
cparata	0:f27ce43dee4f	917	*
cparata	0:f27ce43dee4f	918	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	919	* @param val change the values of g_hm_mode in reg CTRL7_G
cparata	0:f27ce43dee4f	920	*
cparata	0:f27ce43dee4f	921	*/
cparata	0:f27ce43dee4f	922	int32_t lsm6dsox_gy_power_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	923	lsm6dsox_g_hm_mode_t val)
cparata	0:f27ce43dee4f	924	{
cparata	0:f27ce43dee4f	925	lsm6dsox_ctrl7_g_t reg;
cparata	0:f27ce43dee4f	926	int32_t ret;
cparata	0:f27ce43dee4f	927
cparata	0:f27ce43dee4f	928	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	929	if (ret == 0) {
cparata	0:f27ce43dee4f	930	reg.g_hm_mode = (uint8_t)val;
cparata	0:f27ce43dee4f	931	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	932	}
cparata	0:f27ce43dee4f	933	return ret;
cparata	0:f27ce43dee4f	934	}
cparata	0:f27ce43dee4f	935
cparata	0:f27ce43dee4f	936	/**
cparata	0:f27ce43dee4f	937	* @brief Operating mode for gyroscope.[get]
cparata	0:f27ce43dee4f	938	*
cparata	0:f27ce43dee4f	939	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	940	* @param val Get the values of g_hm_mode in reg CTRL7_G
cparata	0:f27ce43dee4f	941	*
cparata	0:f27ce43dee4f	942	*/
cparata	0:f27ce43dee4f	943	int32_t lsm6dsox_gy_power_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	944	lsm6dsox_g_hm_mode_t *val)
cparata	0:f27ce43dee4f	945	{
cparata	0:f27ce43dee4f	946	lsm6dsox_ctrl7_g_t reg;
cparata	0:f27ce43dee4f	947	int32_t ret;
cparata	0:f27ce43dee4f	948
cparata	0:f27ce43dee4f	949	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	950	switch (reg.g_hm_mode) {
cparata	0:f27ce43dee4f	951	case LSM6DSOX_GY_HIGH_PERFORMANCE:
cparata	0:f27ce43dee4f	952	*val = LSM6DSOX_GY_HIGH_PERFORMANCE;
cparata	0:f27ce43dee4f	953	break;
cparata	0:f27ce43dee4f	954	case LSM6DSOX_GY_NORMAL:
cparata	0:f27ce43dee4f	955	*val = LSM6DSOX_GY_NORMAL;
cparata	0:f27ce43dee4f	956	break;
cparata	0:f27ce43dee4f	957	default:
cparata	0:f27ce43dee4f	958	*val = LSM6DSOX_GY_HIGH_PERFORMANCE;
cparata	0:f27ce43dee4f	959	break;
cparata	0:f27ce43dee4f	960	}
cparata	0:f27ce43dee4f	961	return ret;
cparata	0:f27ce43dee4f	962	}
cparata	0:f27ce43dee4f	963
cparata	0:f27ce43dee4f	964	/**
cparata	0:f27ce43dee4f	965	* @brief The STATUS_REG register is read by the primary interface.[get]
cparata	0:f27ce43dee4f	966	*
cparata	0:f27ce43dee4f	967	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	968	* @param val register STATUS_REG
cparata	0:f27ce43dee4f	969	*
cparata	0:f27ce43dee4f	970	*/
cparata	0:f27ce43dee4f	971	int32_t lsm6dsox_status_reg_get(lsm6dsox_ctx_t ctx, lsm6dsox_status_reg_t val)
cparata	0:f27ce43dee4f	972	{
cparata	0:f27ce43dee4f	973	int32_t ret;
cparata	0:f27ce43dee4f	974	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*) val, 1);
cparata	0:f27ce43dee4f	975	return ret;
cparata	0:f27ce43dee4f	976	}
cparata	0:f27ce43dee4f	977
cparata	0:f27ce43dee4f	978	/**
cparata	0:f27ce43dee4f	979	* @brief Accelerometer new data available.[get]
cparata	0:f27ce43dee4f	980	*
cparata	0:f27ce43dee4f	981	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	982	* @param val change the values of xlda in reg STATUS_REG
cparata	0:f27ce43dee4f	983	*
cparata	0:f27ce43dee4f	984	*/
cparata	0:f27ce43dee4f	985	int32_t lsm6dsox_xl_flag_data_ready_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	986	{
cparata	0:f27ce43dee4f	987	lsm6dsox_status_reg_t reg;
cparata	0:f27ce43dee4f	988	int32_t ret;
cparata	0:f27ce43dee4f	989
cparata	0:f27ce43dee4f	990	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	991	*val = reg.xlda;
cparata	0:f27ce43dee4f	992
cparata	0:f27ce43dee4f	993	return ret;
cparata	0:f27ce43dee4f	994	}
cparata	0:f27ce43dee4f	995
cparata	0:f27ce43dee4f	996	/**
cparata	0:f27ce43dee4f	997	* @brief Gyroscope new data available.[get]
cparata	0:f27ce43dee4f	998	*
cparata	0:f27ce43dee4f	999	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1000	* @param val change the values of gda in reg STATUS_REG
cparata	0:f27ce43dee4f	1001	*
cparata	0:f27ce43dee4f	1002	*/
cparata	0:f27ce43dee4f	1003	int32_t lsm6dsox_gy_flag_data_ready_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	1004	{
cparata	0:f27ce43dee4f	1005	lsm6dsox_status_reg_t reg;
cparata	0:f27ce43dee4f	1006	int32_t ret;
cparata	0:f27ce43dee4f	1007
cparata	0:f27ce43dee4f	1008	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1009	*val = reg.gda;
cparata	0:f27ce43dee4f	1010
cparata	0:f27ce43dee4f	1011	return ret;
cparata	0:f27ce43dee4f	1012	}
cparata	0:f27ce43dee4f	1013
cparata	0:f27ce43dee4f	1014	/**
cparata	0:f27ce43dee4f	1015	* @brief Temperature new data available.[get]
cparata	0:f27ce43dee4f	1016	*
cparata	0:f27ce43dee4f	1017	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1018	* @param val change the values of tda in reg STATUS_REG
cparata	0:f27ce43dee4f	1019	*
cparata	0:f27ce43dee4f	1020	*/
cparata	0:f27ce43dee4f	1021	int32_t lsm6dsox_temp_flag_data_ready_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	1022	{
cparata	0:f27ce43dee4f	1023	lsm6dsox_status_reg_t reg;
cparata	0:f27ce43dee4f	1024	int32_t ret;
cparata	0:f27ce43dee4f	1025
cparata	0:f27ce43dee4f	1026	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1027	*val = reg.tda;
cparata	0:f27ce43dee4f	1028
cparata	0:f27ce43dee4f	1029	return ret;
cparata	0:f27ce43dee4f	1030	}
cparata	0:f27ce43dee4f	1031
cparata	0:f27ce43dee4f	1032	/**
cparata	0:f27ce43dee4f	1033	* @brief Accelerometer X-axis user offset correction expressed in
cparata	0:f27ce43dee4f	1034	* two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:f27ce43dee4f	1035	* The value must be in the range [-127 127].[set]
cparata	0:f27ce43dee4f	1036	*
cparata	0:f27ce43dee4f	1037	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1038	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	1039	*
cparata	0:f27ce43dee4f	1040	*/
cparata	0:f27ce43dee4f	1041	int32_t lsm6dsox_xl_usr_offset_x_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1042	{
cparata	0:f27ce43dee4f	1043	int32_t ret;
cparata	0:f27ce43dee4f	1044	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1);
cparata	0:f27ce43dee4f	1045	return ret;
cparata	0:f27ce43dee4f	1046	}
cparata	0:f27ce43dee4f	1047
cparata	0:f27ce43dee4f	1048	/**
cparata	0:f27ce43dee4f	1049	* @brief Accelerometer X-axis user offset correction expressed in two’s
cparata	0:f27ce43dee4f	1050	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:f27ce43dee4f	1051	* The value must be in the range [-127 127].[get]
cparata	0:f27ce43dee4f	1052	*
cparata	0:f27ce43dee4f	1053	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1054	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1055	*
cparata	0:f27ce43dee4f	1056	*/
cparata	0:f27ce43dee4f	1057	int32_t lsm6dsox_xl_usr_offset_x_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1058	{
cparata	0:f27ce43dee4f	1059	int32_t ret;
cparata	0:f27ce43dee4f	1060	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1);
cparata	0:f27ce43dee4f	1061	return ret;
cparata	0:f27ce43dee4f	1062	}
cparata	0:f27ce43dee4f	1063
cparata	0:f27ce43dee4f	1064	/**
cparata	0:f27ce43dee4f	1065	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:f27ce43dee4f	1066	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:f27ce43dee4f	1067	* The value must be in the range [-127 127].[set]
cparata	0:f27ce43dee4f	1068	*
cparata	0:f27ce43dee4f	1069	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1070	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	1071	*
cparata	0:f27ce43dee4f	1072	*/
cparata	0:f27ce43dee4f	1073	int32_t lsm6dsox_xl_usr_offset_y_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1074	{
cparata	0:f27ce43dee4f	1075	int32_t ret;
cparata	0:f27ce43dee4f	1076	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1);
cparata	0:f27ce43dee4f	1077	return ret;
cparata	0:f27ce43dee4f	1078	}
cparata	0:f27ce43dee4f	1079
cparata	0:f27ce43dee4f	1080	/**
cparata	0:f27ce43dee4f	1081	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:f27ce43dee4f	1082	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:f27ce43dee4f	1083	* The value must be in the range [-127 127].[get]
cparata	0:f27ce43dee4f	1084	*
cparata	0:f27ce43dee4f	1085	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1086	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1087	*
cparata	0:f27ce43dee4f	1088	*/
cparata	0:f27ce43dee4f	1089	int32_t lsm6dsox_xl_usr_offset_y_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1090	{
cparata	0:f27ce43dee4f	1091	int32_t ret;
cparata	0:f27ce43dee4f	1092	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1);
cparata	0:f27ce43dee4f	1093	return ret;
cparata	0:f27ce43dee4f	1094	}
cparata	0:f27ce43dee4f	1095
cparata	0:f27ce43dee4f	1096	/**
cparata	0:f27ce43dee4f	1097	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:f27ce43dee4f	1098	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:f27ce43dee4f	1099	* The value must be in the range [-127 127].[set]
cparata	0:f27ce43dee4f	1100	*
cparata	0:f27ce43dee4f	1101	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1102	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	1103	*
cparata	0:f27ce43dee4f	1104	*/
cparata	0:f27ce43dee4f	1105	int32_t lsm6dsox_xl_usr_offset_z_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1106	{
cparata	0:f27ce43dee4f	1107	int32_t ret;
cparata	0:f27ce43dee4f	1108	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1);
cparata	0:f27ce43dee4f	1109	return ret;
cparata	0:f27ce43dee4f	1110	}
cparata	0:f27ce43dee4f	1111
cparata	0:f27ce43dee4f	1112	/**
cparata	0:f27ce43dee4f	1113	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:f27ce43dee4f	1114	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:f27ce43dee4f	1115	* The value must be in the range [-127 127].[get]
cparata	0:f27ce43dee4f	1116	*
cparata	0:f27ce43dee4f	1117	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1118	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1119	*
cparata	0:f27ce43dee4f	1120	*/
cparata	0:f27ce43dee4f	1121	int32_t lsm6dsox_xl_usr_offset_z_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1122	{
cparata	0:f27ce43dee4f	1123	int32_t ret;
cparata	0:f27ce43dee4f	1124	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1);
cparata	0:f27ce43dee4f	1125	return ret;
cparata	0:f27ce43dee4f	1126	}
cparata	0:f27ce43dee4f	1127
cparata	0:f27ce43dee4f	1128	/**
cparata	0:f27ce43dee4f	1129	* @brief Enables user offset on out.[set]
cparata	0:f27ce43dee4f	1130	*
cparata	0:f27ce43dee4f	1131	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1132	* @param val change the values of usr_off_on_out in reg CTRL7_G
cparata	0:f27ce43dee4f	1133	*
cparata	0:f27ce43dee4f	1134	*/
cparata	0:f27ce43dee4f	1135	int32_t lsm6dsox_xl_usr_offset_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	1136	{
cparata	0:f27ce43dee4f	1137	lsm6dsox_ctrl7_g_t reg;
cparata	0:f27ce43dee4f	1138	int32_t ret;
cparata	0:f27ce43dee4f	1139
cparata	0:f27ce43dee4f	1140	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1141	if (ret == 0) {
cparata	0:f27ce43dee4f	1142	reg.usr_off_on_out = val;
cparata	0:f27ce43dee4f	1143	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1144	}
cparata	0:f27ce43dee4f	1145	return ret;
cparata	0:f27ce43dee4f	1146	}
cparata	0:f27ce43dee4f	1147
cparata	0:f27ce43dee4f	1148	/**
cparata	0:f27ce43dee4f	1149	* @brief User offset on out flag.[get]
cparata	0:f27ce43dee4f	1150	*
cparata	0:f27ce43dee4f	1151	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1152	* @param val values of usr_off_on_out in reg CTRL7_G
cparata	0:f27ce43dee4f	1153	*
cparata	0:f27ce43dee4f	1154	*/
cparata	0:f27ce43dee4f	1155	int32_t lsm6dsox_xl_usr_offset_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	1156	{
cparata	0:f27ce43dee4f	1157	lsm6dsox_ctrl7_g_t reg;
cparata	0:f27ce43dee4f	1158	int32_t ret;
cparata	0:f27ce43dee4f	1159
cparata	0:f27ce43dee4f	1160	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1161	*val = reg.usr_off_on_out;
cparata	0:f27ce43dee4f	1162
cparata	0:f27ce43dee4f	1163	return ret;
cparata	0:f27ce43dee4f	1164	}
cparata	0:f27ce43dee4f	1165
cparata	0:f27ce43dee4f	1166	/**
cparata	0:f27ce43dee4f	1167	* @}
cparata	0:f27ce43dee4f	1168	*
cparata	0:f27ce43dee4f	1169	*/
cparata	0:f27ce43dee4f	1170
cparata	0:f27ce43dee4f	1171	/**
cparata	0:f27ce43dee4f	1172	* @defgroup LSM6DSOX_Timestamp
cparata	0:f27ce43dee4f	1173	* @brief This section groups all the functions that manage the
cparata	0:f27ce43dee4f	1174	* timestamp generation.
cparata	0:f27ce43dee4f	1175	* @{
cparata	0:f27ce43dee4f	1176	*
cparata	0:f27ce43dee4f	1177	*/
cparata	0:f27ce43dee4f	1178
cparata	0:f27ce43dee4f	1179	/**
cparata	1:fe40aec6e97a	1180	* @brief Reset timestamp counter.[set]
cparata	1:fe40aec6e97a	1181	*
cparata	1:fe40aec6e97a	1182	* @param ctx Read / write interface definitions.(ptr)
cparata	1:fe40aec6e97a	1183	* @retval Interface status (MANDATORY: return 0 -> no Error).
cparata	1:fe40aec6e97a	1184	*
cparata	1:fe40aec6e97a	1185	*/
cparata	1:fe40aec6e97a	1186	int32_t lsm6dsox_timestamp_rst(lsm6dsox_ctx_t *ctx)
cparata	1:fe40aec6e97a	1187	{
cparata	1:fe40aec6e97a	1188	uint8_t rst_val = 0xAA;
cparata	1:fe40aec6e97a	1189
cparata	1:fe40aec6e97a	1190	return lsm6dsox_write_reg(ctx, LSM6DSOX_TIMESTAMP2, &rst_val, 1);
cparata	1:fe40aec6e97a	1191	}
cparata	1:fe40aec6e97a	1192
cparata	1:fe40aec6e97a	1193	/**
cparata	0:f27ce43dee4f	1194	* @brief Enables timestamp counter.[set]
cparata	0:f27ce43dee4f	1195	*
cparata	0:f27ce43dee4f	1196	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1197	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:f27ce43dee4f	1198	*
cparata	0:f27ce43dee4f	1199	*/
cparata	0:f27ce43dee4f	1200	int32_t lsm6dsox_timestamp_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	1201	{
cparata	0:f27ce43dee4f	1202	lsm6dsox_ctrl10_c_t reg;
cparata	0:f27ce43dee4f	1203	int32_t ret;
cparata	0:f27ce43dee4f	1204
cparata	0:f27ce43dee4f	1205	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1206	if (ret == 0) {
cparata	0:f27ce43dee4f	1207	reg.timestamp_en = val;
cparata	0:f27ce43dee4f	1208	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1209	}
cparata	0:f27ce43dee4f	1210	return ret;
cparata	0:f27ce43dee4f	1211	}
cparata	0:f27ce43dee4f	1212
cparata	0:f27ce43dee4f	1213	/**
cparata	0:f27ce43dee4f	1214	* @brief Enables timestamp counter.[get]
cparata	0:f27ce43dee4f	1215	*
cparata	0:f27ce43dee4f	1216	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1217	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:f27ce43dee4f	1218	*
cparata	0:f27ce43dee4f	1219	*/
cparata	0:f27ce43dee4f	1220	int32_t lsm6dsox_timestamp_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	1221	{
cparata	0:f27ce43dee4f	1222	lsm6dsox_ctrl10_c_t reg;
cparata	0:f27ce43dee4f	1223	int32_t ret;
cparata	0:f27ce43dee4f	1224
cparata	0:f27ce43dee4f	1225	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1226	*val = reg.timestamp_en;
cparata	0:f27ce43dee4f	1227
cparata	0:f27ce43dee4f	1228	return ret;
cparata	0:f27ce43dee4f	1229	}
cparata	0:f27ce43dee4f	1230
cparata	0:f27ce43dee4f	1231	/**
cparata	0:f27ce43dee4f	1232	* @brief Timestamp first data output register (r).
cparata	0:f27ce43dee4f	1233	* The value is expressed as a 32-bit word and the bit
cparata	0:f27ce43dee4f	1234	* resolution is 25 μs.[get]
cparata	0:f27ce43dee4f	1235	*
cparata	0:f27ce43dee4f	1236	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1237	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1238	*
cparata	0:f27ce43dee4f	1239	*/
cparata	0:f27ce43dee4f	1240	int32_t lsm6dsox_timestamp_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1241	{
cparata	0:f27ce43dee4f	1242	int32_t ret;
cparata	0:f27ce43dee4f	1243	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TIMESTAMP0, buff, 4);
cparata	0:f27ce43dee4f	1244	return ret;
cparata	0:f27ce43dee4f	1245	}
cparata	0:f27ce43dee4f	1246
cparata	0:f27ce43dee4f	1247	/**
cparata	0:f27ce43dee4f	1248	* @}
cparata	0:f27ce43dee4f	1249	*
cparata	0:f27ce43dee4f	1250	*/
cparata	0:f27ce43dee4f	1251
cparata	0:f27ce43dee4f	1252	/**
cparata	0:f27ce43dee4f	1253	* @defgroup LSM6DSOX_Data output
cparata	0:f27ce43dee4f	1254	* @brief This section groups all the data output functions.
cparata	0:f27ce43dee4f	1255	* @{
cparata	0:f27ce43dee4f	1256	*
cparata	0:f27ce43dee4f	1257	*/
cparata	0:f27ce43dee4f	1258
cparata	0:f27ce43dee4f	1259	/**
cparata	0:f27ce43dee4f	1260	* @brief Circular burst-mode (rounding) read of the output
cparata	0:f27ce43dee4f	1261	* registers.[set]
cparata	0:f27ce43dee4f	1262	*
cparata	0:f27ce43dee4f	1263	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1264	* @param val change the values of rounding in reg CTRL5_C
cparata	0:f27ce43dee4f	1265	*
cparata	0:f27ce43dee4f	1266	*/
cparata	0:f27ce43dee4f	1267	int32_t lsm6dsox_rounding_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	1268	lsm6dsox_rounding_t val)
cparata	0:f27ce43dee4f	1269	{
cparata	0:f27ce43dee4f	1270	lsm6dsox_ctrl5_c_t reg;
cparata	0:f27ce43dee4f	1271	int32_t ret;
cparata	0:f27ce43dee4f	1272
cparata	0:f27ce43dee4f	1273	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1274	if (ret == 0) {
cparata	0:f27ce43dee4f	1275	reg.rounding = (uint8_t)val;
cparata	0:f27ce43dee4f	1276	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1277	}
cparata	0:f27ce43dee4f	1278	return ret;
cparata	0:f27ce43dee4f	1279	}
cparata	0:f27ce43dee4f	1280
cparata	0:f27ce43dee4f	1281	/**
cparata	0:f27ce43dee4f	1282	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:f27ce43dee4f	1283	*
cparata	0:f27ce43dee4f	1284	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1285	* @param val Get the values of rounding in reg CTRL5_C
cparata	0:f27ce43dee4f	1286	*
cparata	0:f27ce43dee4f	1287	*/
cparata	0:f27ce43dee4f	1288	int32_t lsm6dsox_rounding_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	1289	lsm6dsox_rounding_t *val)
cparata	0:f27ce43dee4f	1290	{
cparata	0:f27ce43dee4f	1291	lsm6dsox_ctrl5_c_t reg;
cparata	0:f27ce43dee4f	1292	int32_t ret;
cparata	0:f27ce43dee4f	1293
cparata	0:f27ce43dee4f	1294	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1295	switch (reg.rounding) {
cparata	0:f27ce43dee4f	1296	case LSM6DSOX_NO_ROUND:
cparata	0:f27ce43dee4f	1297	*val = LSM6DSOX_NO_ROUND;
cparata	0:f27ce43dee4f	1298	break;
cparata	0:f27ce43dee4f	1299	case LSM6DSOX_ROUND_XL:
cparata	0:f27ce43dee4f	1300	*val = LSM6DSOX_ROUND_XL;
cparata	0:f27ce43dee4f	1301	break;
cparata	0:f27ce43dee4f	1302	case LSM6DSOX_ROUND_GY:
cparata	0:f27ce43dee4f	1303	*val = LSM6DSOX_ROUND_GY;
cparata	0:f27ce43dee4f	1304	break;
cparata	0:f27ce43dee4f	1305	case LSM6DSOX_ROUND_GY_XL:
cparata	0:f27ce43dee4f	1306	*val = LSM6DSOX_ROUND_GY_XL;
cparata	0:f27ce43dee4f	1307	break;
cparata	0:f27ce43dee4f	1308	default:
cparata	0:f27ce43dee4f	1309	*val = LSM6DSOX_NO_ROUND;
cparata	0:f27ce43dee4f	1310	break;
cparata	0:f27ce43dee4f	1311	}
cparata	0:f27ce43dee4f	1312	return ret;
cparata	0:f27ce43dee4f	1313	}
cparata	0:f27ce43dee4f	1314
cparata	0:f27ce43dee4f	1315	/**
cparata	0:f27ce43dee4f	1316	* @brief rounding_on_status: [set] Source register rounding function in
cparata	0:f27ce43dee4f	1317	* ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh),
cparata	0:f27ce43dee4f	1318	* TAP_SRC (1Ch), D6D_SRC (1Dh),
cparata	0:f27ce43dee4f	1319	* STATUS_REG (1Eh) and
cparata	0:f27ce43dee4f	1320	* EMB_FUNC_STATUS_MAINPAGE(35h),
cparata	0:f27ce43dee4f	1321	* FSM_STATUS_A_MAINPAGE (36h),
cparata	0:f27ce43dee4f	1322	* FSM_STATUS_B_MAINPAGE (37h),
cparata	0:f27ce43dee4f	1323	* MLC_STATUS_MAINPAGE (38h),
cparata	0:f27ce43dee4f	1324	* STATUS_MASTER_MAINPAGE (39h),
cparata	0:f27ce43dee4f	1325	* FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh).
cparata	0:f27ce43dee4f	1326	*
cparata	0:f27ce43dee4f	1327	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1328	* @param lsm6dsox_rounding_status_t: change the values of rounding_status
cparata	0:f27ce43dee4f	1329	* in reg CTRL7_G
cparata	0:f27ce43dee4f	1330	*
cparata	0:f27ce43dee4f	1331	*/
cparata	0:f27ce43dee4f	1332	int32_t lsm6dsox_rounding_on_status_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	1333	lsm6dsox_rounding_status_t val)
cparata	0:f27ce43dee4f	1334	{
cparata	0:f27ce43dee4f	1335	lsm6dsox_ctrl5_c_t reg;
cparata	0:f27ce43dee4f	1336	int32_t ret;
cparata	0:f27ce43dee4f	1337
cparata	0:f27ce43dee4f	1338	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1339	if (ret == 0) {
cparata	0:f27ce43dee4f	1340	reg.rounding_status = (uint8_t)val;
cparata	0:f27ce43dee4f	1341	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1342	}
cparata	0:f27ce43dee4f	1343
cparata	0:f27ce43dee4f	1344	return ret;
cparata	0:f27ce43dee4f	1345	}
cparata	0:f27ce43dee4f	1346
cparata	0:f27ce43dee4f	1347	/**
cparata	0:f27ce43dee4f	1348	* @brief rounding_on_status: [get] Source register rounding function in
cparata	0:f27ce43dee4f	1349	* ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh),
cparata	0:f27ce43dee4f	1350	* TAP_SRC (1Ch), D6D_SRC (1Dh),
cparata	0:f27ce43dee4f	1351	* STATUS_REG (1Eh) and
cparata	0:f27ce43dee4f	1352	* EMB_FUNC_STATUS_MAINPAGE(35h),
cparata	0:f27ce43dee4f	1353	* FSM_STATUS_A_MAINPAGE (36h),
cparata	0:f27ce43dee4f	1354	* FSM_STATUS_B_MAINPAGE (37h),
cparata	0:f27ce43dee4f	1355	* MLC_STATUS_MAINPAGE (38h),
cparata	0:f27ce43dee4f	1356	* STATUS_MASTER_MAINPAGE (39h),
cparata	0:f27ce43dee4f	1357	* FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh).
cparata	0:f27ce43dee4f	1358	*
cparata	0:f27ce43dee4f	1359	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1360	* @param lsm6dsox_rounding_status_t: Get the values of rounding_status
cparata	0:f27ce43dee4f	1361	* in reg CTRL7_G
cparata	0:f27ce43dee4f	1362	*
cparata	0:f27ce43dee4f	1363	*/
cparata	0:f27ce43dee4f	1364	int32_t lsm6dsox_rounding_on_status_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	1365	lsm6dsox_rounding_status_t *val)
cparata	0:f27ce43dee4f	1366	{
cparata	0:f27ce43dee4f	1367	lsm6dsox_ctrl5_c_t reg;
cparata	0:f27ce43dee4f	1368	int32_t ret;
cparata	0:f27ce43dee4f	1369
cparata	0:f27ce43dee4f	1370	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1371	switch (reg.rounding_status) {
cparata	0:f27ce43dee4f	1372	case LSM6DSOX_STAT_RND_DISABLE:
cparata	0:f27ce43dee4f	1373	*val = LSM6DSOX_STAT_RND_DISABLE;
cparata	0:f27ce43dee4f	1374	break;
cparata	0:f27ce43dee4f	1375	case LSM6DSOX_STAT_RND_ENABLE:
cparata	0:f27ce43dee4f	1376	*val = LSM6DSOX_STAT_RND_ENABLE;
cparata	0:f27ce43dee4f	1377	break;
cparata	0:f27ce43dee4f	1378	default:
cparata	0:f27ce43dee4f	1379	*val = LSM6DSOX_STAT_RND_DISABLE;
cparata	0:f27ce43dee4f	1380	break;
cparata	0:f27ce43dee4f	1381	}
cparata	0:f27ce43dee4f	1382	return ret;
cparata	0:f27ce43dee4f	1383	}
cparata	0:f27ce43dee4f	1384
cparata	0:f27ce43dee4f	1385	/**
cparata	0:f27ce43dee4f	1386	* @brief Temperature data output register (r).
cparata	0:f27ce43dee4f	1387	* L and H registers together express a 16-bit word in two’s
cparata	0:f27ce43dee4f	1388	* complement.[get]
cparata	0:f27ce43dee4f	1389	*
cparata	0:f27ce43dee4f	1390	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1391	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1392	*
cparata	0:f27ce43dee4f	1393	*/
cparata	0:f27ce43dee4f	1394	int32_t lsm6dsox_temperature_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1395	{
cparata	0:f27ce43dee4f	1396	int32_t ret;
cparata	0:f27ce43dee4f	1397	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 2);
cparata	0:f27ce43dee4f	1398	return ret;
cparata	0:f27ce43dee4f	1399	}
cparata	0:f27ce43dee4f	1400
cparata	0:f27ce43dee4f	1401	/**
cparata	0:f27ce43dee4f	1402	* @brief Angular rate sensor. The value is expressed as a 16-bit
cparata	0:f27ce43dee4f	1403	* word in two’s complement.[get]
cparata	0:f27ce43dee4f	1404	*
cparata	0:f27ce43dee4f	1405	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1406	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1407	*
cparata	0:f27ce43dee4f	1408	*/
cparata	0:f27ce43dee4f	1409	int32_t lsm6dsox_angular_rate_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1410	{
cparata	0:f27ce43dee4f	1411	int32_t ret;
cparata	0:f27ce43dee4f	1412	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_G, buff, 6);
cparata	0:f27ce43dee4f	1413	return ret;
cparata	0:f27ce43dee4f	1414	}
cparata	0:f27ce43dee4f	1415
cparata	0:f27ce43dee4f	1416	/**
cparata	0:f27ce43dee4f	1417	* @brief Linear acceleration output register.
cparata	0:f27ce43dee4f	1418	* The value is expressed as a 16-bit word in two’s complement.[get]
cparata	0:f27ce43dee4f	1419	*
cparata	0:f27ce43dee4f	1420	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1421	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1422	*
cparata	0:f27ce43dee4f	1423	*/
cparata	0:f27ce43dee4f	1424	int32_t lsm6dsox_acceleration_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1425	{
cparata	0:f27ce43dee4f	1426	int32_t ret;
cparata	0:f27ce43dee4f	1427	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_A, buff, 6);
cparata	0:f27ce43dee4f	1428	return ret;
cparata	0:f27ce43dee4f	1429	}
cparata	0:f27ce43dee4f	1430
cparata	0:f27ce43dee4f	1431	/**
cparata	0:f27ce43dee4f	1432	* @brief FIFO data output [get]
cparata	0:f27ce43dee4f	1433	*
cparata	0:f27ce43dee4f	1434	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1435	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1436	*
cparata	0:f27ce43dee4f	1437	*/
cparata	0:f27ce43dee4f	1438	int32_t lsm6dsox_fifo_out_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1439	{
cparata	0:f27ce43dee4f	1440	int32_t ret;
cparata	0:f27ce43dee4f	1441	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_X_L, buff, 6);
cparata	0:f27ce43dee4f	1442	return ret;
cparata	0:f27ce43dee4f	1443	}
cparata	0:f27ce43dee4f	1444
cparata	0:f27ce43dee4f	1445	/**
cparata	0:f27ce43dee4f	1446	* @brief ois_angular_rate_raw: [get] OIS angular rate sensor.
cparata	0:f27ce43dee4f	1447	* The value is expressed as a
cparata	0:f27ce43dee4f	1448	* 16-bit word in two’s complement.
cparata	0:f27ce43dee4f	1449	*
cparata	0:f27ce43dee4f	1450	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1451	* @param uint8_t * : buffer that stores data read
cparata	0:f27ce43dee4f	1452	*
cparata	0:f27ce43dee4f	1453	*/
cparata	0:f27ce43dee4f	1454	int32_t lsm6dsox_ois_angular_rate_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1455	{
cparata	0:f27ce43dee4f	1456	return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 6);
cparata	0:f27ce43dee4f	1457	}
cparata	0:f27ce43dee4f	1458
cparata	0:f27ce43dee4f	1459	/**
cparata	0:f27ce43dee4f	1460	* @brief ois_acceleration_raw: [get] OIS Linear acceleration output register.
cparata	0:f27ce43dee4f	1461	* The value is expressed as a
cparata	0:f27ce43dee4f	1462	* 16-bit word in two’s complement.
cparata	0:f27ce43dee4f	1463	*
cparata	0:f27ce43dee4f	1464	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1465	* @param uint8_t * : buffer that stores data read
cparata	0:f27ce43dee4f	1466	*
cparata	0:f27ce43dee4f	1467	*/
cparata	0:f27ce43dee4f	1468	int32_t lsm6dsox_ois_acceleration_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1469	{
cparata	0:f27ce43dee4f	1470	return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_A_OIS, buff, 6);
cparata	0:f27ce43dee4f	1471	}
cparata	0:f27ce43dee4f	1472
cparata	0:f27ce43dee4f	1473	/**
cparata	0:f27ce43dee4f	1474	* @brief aux_temperature_raw: [get] Temperature from auxiliary
cparata	0:f27ce43dee4f	1475	* interface.
cparata	0:f27ce43dee4f	1476	* The value is expressed as a
cparata	0:f27ce43dee4f	1477	* 16-bit word in two’s complement.
cparata	0:f27ce43dee4f	1478	*
cparata	0:f27ce43dee4f	1479	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1480	* @param uint8_t * : buffer that stores data read
cparata	0:f27ce43dee4f	1481	*
cparata	0:f27ce43dee4f	1482	*/
cparata	0:f27ce43dee4f	1483	int32_t lsm6dsox_aux_temperature_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1484	{
cparata	0:f27ce43dee4f	1485	return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUT_TEMP_L, buff, 2);
cparata	0:f27ce43dee4f	1486	}
cparata	0:f27ce43dee4f	1487
cparata	0:f27ce43dee4f	1488	/**
cparata	0:f27ce43dee4f	1489	* @brief aux_ois_angular_rate_raw: [get] OIS angular rate sensor from
cparata	0:f27ce43dee4f	1490	* auxiliary interface.
cparata	0:f27ce43dee4f	1491	* The value is expressed as a
cparata	0:f27ce43dee4f	1492	* 16-bit word in two’s complement.
cparata	0:f27ce43dee4f	1493	*
cparata	0:f27ce43dee4f	1494	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1495	* @param uint8_t * : buffer that stores data read
cparata	0:f27ce43dee4f	1496	*
cparata	0:f27ce43dee4f	1497	*/
cparata	0:f27ce43dee4f	1498	int32_t lsm6dsox_aux_ois_angular_rate_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1499	{
cparata	0:f27ce43dee4f	1500	return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 6);
cparata	0:f27ce43dee4f	1501	}
cparata	0:f27ce43dee4f	1502
cparata	0:f27ce43dee4f	1503	/**
cparata	0:f27ce43dee4f	1504	* @brief aux_ois_acceleration_raw: [get] OIS linear acceleration output
cparata	0:f27ce43dee4f	1505	* register from auxiliary interface.
cparata	0:f27ce43dee4f	1506	* The value is expressed as a
cparata	0:f27ce43dee4f	1507	* 16-bit word in two’s complement.
cparata	0:f27ce43dee4f	1508	*
cparata	0:f27ce43dee4f	1509	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1510	* @param uint8_t * : buffer that stores data read
cparata	0:f27ce43dee4f	1511	*
cparata	0:f27ce43dee4f	1512	*/
cparata	0:f27ce43dee4f	1513	int32_t lsm6dsox_aux_ois_acceleration_raw_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1514	{
cparata	0:f27ce43dee4f	1515	return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_A_OIS, buff, 6);
cparata	0:f27ce43dee4f	1516	}
cparata	0:f27ce43dee4f	1517
cparata	0:f27ce43dee4f	1518	/**
cparata	0:f27ce43dee4f	1519	* @brief Step counter output register.[get]
cparata	0:f27ce43dee4f	1520	*
cparata	0:f27ce43dee4f	1521	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1522	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1523	*
cparata	0:f27ce43dee4f	1524	*/
cparata	0:f27ce43dee4f	1525	int32_t lsm6dsox_number_of_steps_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1526	{
cparata	0:f27ce43dee4f	1527	int32_t ret;
cparata	0:f27ce43dee4f	1528
cparata	0:f27ce43dee4f	1529	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	1530	if (ret == 0) {
cparata	0:f27ce43dee4f	1531	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STEP_COUNTER_L, buff, 2);
cparata	0:f27ce43dee4f	1532	}
cparata	0:f27ce43dee4f	1533	if (ret == 0) {
cparata	0:f27ce43dee4f	1534	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	1535	}
cparata	0:f27ce43dee4f	1536	return ret;
cparata	0:f27ce43dee4f	1537	}
cparata	0:f27ce43dee4f	1538
cparata	0:f27ce43dee4f	1539	/**
cparata	0:f27ce43dee4f	1540	* @brief Reset step counter register.[get]
cparata	0:f27ce43dee4f	1541	*
cparata	0:f27ce43dee4f	1542	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1543	*
cparata	0:f27ce43dee4f	1544	*/
cparata	0:f27ce43dee4f	1545	int32_t lsm6dsox_steps_reset(lsm6dsox_ctx_t *ctx)
cparata	0:f27ce43dee4f	1546	{
cparata	0:f27ce43dee4f	1547	lsm6dsox_emb_func_src_t reg;
cparata	0:f27ce43dee4f	1548	int32_t ret;
cparata	0:f27ce43dee4f	1549
cparata	0:f27ce43dee4f	1550	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	1551	if (ret == 0) {
cparata	0:f27ce43dee4f	1552	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1553	}
cparata	0:f27ce43dee4f	1554	if (ret == 0) {
cparata	0:f27ce43dee4f	1555	reg.pedo_rst_step = PROPERTY_ENABLE;
cparata	0:f27ce43dee4f	1556	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1557	}
cparata	0:f27ce43dee4f	1558	if (ret == 0) {
cparata	0:f27ce43dee4f	1559	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	1560	}
cparata	0:f27ce43dee4f	1561	return ret;
cparata	0:f27ce43dee4f	1562	}
cparata	0:f27ce43dee4f	1563
cparata	0:f27ce43dee4f	1564	/**
cparata	0:f27ce43dee4f	1565	* @brief prgsens_out: [get] Output value of all MLCx decision trees.
cparata	0:f27ce43dee4f	1566	*
cparata	0:f27ce43dee4f	1567	* @param ctx_t *ctx: read / write interface definitions
cparata	0:f27ce43dee4f	1568	* @param uint8_t * : buffer that stores data read
cparata	0:f27ce43dee4f	1569	*
cparata	0:f27ce43dee4f	1570	*/
cparata	0:f27ce43dee4f	1571	int32_t lsm6dsox_mlc_out_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1572	{
cparata	0:f27ce43dee4f	1573	int32_t ret;
cparata	0:f27ce43dee4f	1574	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	1575	if (ret == 0) {
cparata	0:f27ce43dee4f	1576	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC0_SRC, buff, 8);
cparata	0:f27ce43dee4f	1577	}
cparata	0:f27ce43dee4f	1578	if (ret == 0) {
cparata	0:f27ce43dee4f	1579	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	1580	}
cparata	0:f27ce43dee4f	1581	return ret;
cparata	0:f27ce43dee4f	1582	}
cparata	0:f27ce43dee4f	1583
cparata	0:f27ce43dee4f	1584	/**
cparata	0:f27ce43dee4f	1585	* @}
cparata	0:f27ce43dee4f	1586	*
cparata	0:f27ce43dee4f	1587	*/
cparata	0:f27ce43dee4f	1588
cparata	0:f27ce43dee4f	1589	/**
cparata	0:f27ce43dee4f	1590	* @defgroup LSM6DSOX_common
cparata	0:f27ce43dee4f	1591	* @brief This section groups common usefull functions.
cparata	0:f27ce43dee4f	1592	* @{
cparata	0:f27ce43dee4f	1593	*
cparata	0:f27ce43dee4f	1594	*/
cparata	0:f27ce43dee4f	1595
cparata	0:f27ce43dee4f	1596	/**
cparata	0:f27ce43dee4f	1597	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:f27ce43dee4f	1598	* with respect to the typical.
cparata	0:f27ce43dee4f	1599	* Step: 0.15%. 8-bit format, 2's complement.[set]
cparata	0:f27ce43dee4f	1600	*
cparata	0:f27ce43dee4f	1601	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1602	* @param val change the values of freq_fine in reg
cparata	0:f27ce43dee4f	1603	* INTERNAL_FREQ_FINE
cparata	0:f27ce43dee4f	1604	*
cparata	0:f27ce43dee4f	1605	*/
cparata	0:f27ce43dee4f	1606	int32_t lsm6dsox_odr_cal_reg_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	1607	{
cparata	0:f27ce43dee4f	1608	lsm6dsox_internal_freq_fine_t reg;
cparata	0:f27ce43dee4f	1609	int32_t ret;
cparata	0:f27ce43dee4f	1610
cparata	0:f27ce43dee4f	1611	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1612	if (ret == 0) {
cparata	0:f27ce43dee4f	1613	reg.freq_fine = val;
cparata	0:f27ce43dee4f	1614	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE,
cparata	0:f27ce43dee4f	1615	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1616	}
cparata	0:f27ce43dee4f	1617	return ret;
cparata	0:f27ce43dee4f	1618	}
cparata	0:f27ce43dee4f	1619
cparata	0:f27ce43dee4f	1620	/**
cparata	0:f27ce43dee4f	1621	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:f27ce43dee4f	1622	* with respect to the typical.
cparata	0:f27ce43dee4f	1623	* Step: 0.15%. 8-bit format, 2's complement.[get]
cparata	0:f27ce43dee4f	1624	*
cparata	0:f27ce43dee4f	1625	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1626	* @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
cparata	0:f27ce43dee4f	1627	*
cparata	0:f27ce43dee4f	1628	*/
cparata	0:f27ce43dee4f	1629	int32_t lsm6dsox_odr_cal_reg_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	1630	{
cparata	0:f27ce43dee4f	1631	lsm6dsox_internal_freq_fine_t reg;
cparata	0:f27ce43dee4f	1632	int32_t ret;
cparata	0:f27ce43dee4f	1633
cparata	0:f27ce43dee4f	1634	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1635	*val = reg.freq_fine;
cparata	0:f27ce43dee4f	1636
cparata	0:f27ce43dee4f	1637	return ret;
cparata	0:f27ce43dee4f	1638	}
cparata	0:f27ce43dee4f	1639
cparata	0:f27ce43dee4f	1640
cparata	0:f27ce43dee4f	1641	/**
cparata	0:f27ce43dee4f	1642	* @brief Enable access to the embedded functions/sensor
cparata	0:f27ce43dee4f	1643	* hub configuration registers.[set]
cparata	0:f27ce43dee4f	1644	*
cparata	0:f27ce43dee4f	1645	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1646	* @param val change the values of reg_access in
cparata	0:f27ce43dee4f	1647	* reg FUNC_CFG_ACCESS
cparata	0:f27ce43dee4f	1648	*
cparata	0:f27ce43dee4f	1649	*/
cparata	0:f27ce43dee4f	1650	int32_t lsm6dsox_mem_bank_set(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t val)
cparata	0:f27ce43dee4f	1651	{
cparata	0:f27ce43dee4f	1652	lsm6dsox_func_cfg_access_t reg;
cparata	0:f27ce43dee4f	1653	int32_t ret;
cparata	0:f27ce43dee4f	1654
cparata	0:f27ce43dee4f	1655	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1656	if (ret == 0) {
cparata	0:f27ce43dee4f	1657	reg.reg_access = (uint8_t)val;
cparata	0:f27ce43dee4f	1658	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1659	}
cparata	0:f27ce43dee4f	1660	return ret;
cparata	0:f27ce43dee4f	1661	}
cparata	0:f27ce43dee4f	1662
cparata	0:f27ce43dee4f	1663	/**
cparata	0:f27ce43dee4f	1664	* @brief Enable access to the embedded functions/sensor
cparata	0:f27ce43dee4f	1665	* hub configuration registers.[get]
cparata	0:f27ce43dee4f	1666	*
cparata	0:f27ce43dee4f	1667	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1668	* @param val Get the values of reg_access in
cparata	0:f27ce43dee4f	1669	* reg FUNC_CFG_ACCESS
cparata	0:f27ce43dee4f	1670	*
cparata	0:f27ce43dee4f	1671	*/
cparata	0:f27ce43dee4f	1672	int32_t lsm6dsox_mem_bank_get(lsm6dsox_ctx_t ctx, lsm6dsox_reg_access_t val)
cparata	0:f27ce43dee4f	1673	{
cparata	0:f27ce43dee4f	1674	lsm6dsox_func_cfg_access_t reg;
cparata	0:f27ce43dee4f	1675	int32_t ret;
cparata	0:f27ce43dee4f	1676
cparata	0:f27ce43dee4f	1677	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1678	switch (reg.reg_access) {
cparata	0:f27ce43dee4f	1679	case LSM6DSOX_USER_BANK:
cparata	0:f27ce43dee4f	1680	*val = LSM6DSOX_USER_BANK;
cparata	0:f27ce43dee4f	1681	break;
cparata	0:f27ce43dee4f	1682	case LSM6DSOX_SENSOR_HUB_BANK:
cparata	0:f27ce43dee4f	1683	*val = LSM6DSOX_SENSOR_HUB_BANK;
cparata	0:f27ce43dee4f	1684	break;
cparata	0:f27ce43dee4f	1685	case LSM6DSOX_EMBEDDED_FUNC_BANK:
cparata	0:f27ce43dee4f	1686	*val = LSM6DSOX_EMBEDDED_FUNC_BANK;
cparata	0:f27ce43dee4f	1687	break;
cparata	0:f27ce43dee4f	1688	default:
cparata	0:f27ce43dee4f	1689	*val = LSM6DSOX_USER_BANK;
cparata	0:f27ce43dee4f	1690	break;
cparata	0:f27ce43dee4f	1691	}
cparata	0:f27ce43dee4f	1692	return ret;
cparata	0:f27ce43dee4f	1693	}
cparata	0:f27ce43dee4f	1694
cparata	0:f27ce43dee4f	1695	/**
cparata	0:f27ce43dee4f	1696	* @brief Write a line(byte) in a page.[set]
cparata	0:f27ce43dee4f	1697	*
cparata	0:f27ce43dee4f	1698	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1699	* @param uint8_t address: page line address
cparata	0:f27ce43dee4f	1700	* @param val value to write
cparata	0:f27ce43dee4f	1701	*
cparata	0:f27ce43dee4f	1702	*/
cparata	0:f27ce43dee4f	1703	int32_t lsm6dsox_ln_pg_write_byte(lsm6dsox_ctx_t *ctx, uint16_t address,
cparata	0:f27ce43dee4f	1704	uint8_t *val)
cparata	0:f27ce43dee4f	1705	{
cparata	0:f27ce43dee4f	1706	lsm6dsox_page_rw_t page_rw;
cparata	0:f27ce43dee4f	1707	lsm6dsox_page_sel_t page_sel;
cparata	0:f27ce43dee4f	1708	lsm6dsox_page_address_t page_address;
cparata	0:f27ce43dee4f	1709	int32_t ret;
cparata	0:f27ce43dee4f	1710
cparata	0:f27ce43dee4f	1711	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	1712
cparata	0:f27ce43dee4f	1713	if (ret == 0) {
cparata	0:f27ce43dee4f	1714	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1715	}
cparata	0:f27ce43dee4f	1716	if (ret == 0) {
cparata	0:f27ce43dee4f	1717	page_rw.page_rw = 0x02; /* page_write enable */
cparata	0:f27ce43dee4f	1718	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1719	}
cparata	0:f27ce43dee4f	1720	if (ret == 0) {
cparata	0:f27ce43dee4f	1721	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:f27ce43dee4f	1722	}
cparata	0:f27ce43dee4f	1723
cparata	0:f27ce43dee4f	1724	if (ret == 0) {
cparata	0:f27ce43dee4f	1725	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	0:f27ce43dee4f	1726	page_sel.not_used_01 = 1;
cparata	0:f27ce43dee4f	1727	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:f27ce43dee4f	1728	}
cparata	0:f27ce43dee4f	1729	if (ret == 0) {
cparata	0:f27ce43dee4f	1730	page_address.page_addr = (uint8_t)address & 0xFFU;
cparata	0:f27ce43dee4f	1731	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
cparata	0:f27ce43dee4f	1732	(uint8_t*)&page_address, 1);
cparata	0:f27ce43dee4f	1733	}
cparata	0:f27ce43dee4f	1734	if (ret == 0) {
cparata	0:f27ce43dee4f	1735	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1);
cparata	0:f27ce43dee4f	1736	}
cparata	0:f27ce43dee4f	1737	if (ret == 0) {
cparata	0:f27ce43dee4f	1738	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1739	}
cparata	0:f27ce43dee4f	1740	if (ret == 0) {
cparata	0:f27ce43dee4f	1741	page_rw.page_rw = 0x00; /* page_write disable */
cparata	0:f27ce43dee4f	1742	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1743	}
cparata	0:f27ce43dee4f	1744	if (ret == 0) {
cparata	0:f27ce43dee4f	1745
cparata	0:f27ce43dee4f	1746	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	1747	}
cparata	0:f27ce43dee4f	1748	return ret;
cparata	0:f27ce43dee4f	1749	}
cparata	0:f27ce43dee4f	1750
cparata	0:f27ce43dee4f	1751	/**
cparata	0:f27ce43dee4f	1752	* @brief Write buffer in a page.[set]
cparata	0:f27ce43dee4f	1753	*
cparata	0:f27ce43dee4f	1754	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1755	* @param uint8_t address: page line address
cparata	0:f27ce43dee4f	1756	* @param uint8_t *buf: buffer to write
cparata	0:f27ce43dee4f	1757	* @param uint8_t len: buffer len
cparata	0:f27ce43dee4f	1758	*
cparata	0:f27ce43dee4f	1759	*/
cparata	0:f27ce43dee4f	1760	int32_t lsm6dsox_ln_pg_write(lsm6dsox_ctx_t *ctx, uint16_t address,
cparata	0:f27ce43dee4f	1761	uint8_t *buf, uint8_t len)
cparata	0:f27ce43dee4f	1762	{
cparata	0:f27ce43dee4f	1763	lsm6dsox_page_rw_t page_rw;
cparata	0:f27ce43dee4f	1764	lsm6dsox_page_sel_t page_sel;
cparata	0:f27ce43dee4f	1765	lsm6dsox_page_address_t page_address;
cparata	0:f27ce43dee4f	1766	int32_t ret;
cparata	0:f27ce43dee4f	1767	uint8_t msb, lsb;
cparata	0:f27ce43dee4f	1768	uint8_t i ;
cparata	0:f27ce43dee4f	1769
cparata	0:f27ce43dee4f	1770	msb = ((uint8_t)(address >> 8) & 0x0FU);
cparata	0:f27ce43dee4f	1771	lsb = (uint8_t)address & 0xFFU;
cparata	0:f27ce43dee4f	1772
cparata	0:f27ce43dee4f	1773	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	1774	if (ret == 0) {
cparata	0:f27ce43dee4f	1775
cparata	0:f27ce43dee4f	1776	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1777	}
cparata	0:f27ce43dee4f	1778	if (ret == 0) {
cparata	0:f27ce43dee4f	1779	page_rw.page_rw = 0x02; /* page_write enable*/
cparata	0:f27ce43dee4f	1780	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1781	}
cparata	0:f27ce43dee4f	1782	if (ret == 0) {
cparata	0:f27ce43dee4f	1783	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:f27ce43dee4f	1784	}
cparata	0:f27ce43dee4f	1785	if (ret == 0) {
cparata	0:f27ce43dee4f	1786	page_sel.page_sel = msb;
cparata	0:f27ce43dee4f	1787	page_sel.not_used_01 = 1;
cparata	0:f27ce43dee4f	1788	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:f27ce43dee4f	1789	}
cparata	0:f27ce43dee4f	1790	if (ret == 0) {
cparata	0:f27ce43dee4f	1791	page_address.page_addr = lsb;
cparata	0:f27ce43dee4f	1792	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
cparata	0:f27ce43dee4f	1793	(uint8_t*)&page_address, 1);
cparata	0:f27ce43dee4f	1794	}
cparata	0:f27ce43dee4f	1795
cparata	0:f27ce43dee4f	1796	if (ret == 0) {
cparata	0:f27ce43dee4f	1797	for (i = 0; ( (i < len) && (ret == 0) ); i++)
cparata	0:f27ce43dee4f	1798	{
cparata	0:f27ce43dee4f	1799	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, &buf[i], 1);
cparata	1:fe40aec6e97a	1800	lsb++;
cparata	0:f27ce43dee4f	1801	/* Check if page wrap */
cparata	0:f27ce43dee4f	1802	if ( (lsb == 0x00U) && (ret == 0) ) {
cparata	0:f27ce43dee4f	1803	msb++;
cparata	0:f27ce43dee4f	1804	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*)&page_sel, 1);
cparata	0:f27ce43dee4f	1805	if (ret == 0) {
cparata	0:f27ce43dee4f	1806	page_sel.page_sel = msb;
cparata	0:f27ce43dee4f	1807	page_sel.not_used_01 = 1;
cparata	0:f27ce43dee4f	1808	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
cparata	0:f27ce43dee4f	1809	(uint8_t*)&page_sel, 1);
cparata	0:f27ce43dee4f	1810	}
cparata	0:f27ce43dee4f	1811	}
cparata	0:f27ce43dee4f	1812	}
cparata	1:fe40aec6e97a	1813	}
cparata	1:fe40aec6e97a	1814	page_sel.page_sel = 0;
cparata	1:fe40aec6e97a	1815	page_sel.not_used_01 = 1;
cparata	1:fe40aec6e97a	1816	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	1:fe40aec6e97a	1817
cparata	0:f27ce43dee4f	1818	if (ret == 0) {
cparata	0:f27ce43dee4f	1819
cparata	0:f27ce43dee4f	1820	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1821	}
cparata	0:f27ce43dee4f	1822	if (ret == 0) {
cparata	0:f27ce43dee4f	1823	page_rw.page_rw = 0x00; /* page_write disable */
cparata	0:f27ce43dee4f	1824	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1825	}
cparata	0:f27ce43dee4f	1826
cparata	0:f27ce43dee4f	1827	if (ret == 0) {
cparata	0:f27ce43dee4f	1828
cparata	0:f27ce43dee4f	1829	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	1830	}
cparata	0:f27ce43dee4f	1831	return ret;
cparata	0:f27ce43dee4f	1832	}
cparata	0:f27ce43dee4f	1833
cparata	0:f27ce43dee4f	1834	/**
cparata	0:f27ce43dee4f	1835	* @brief Read a line(byte) in a page.[get]
cparata	0:f27ce43dee4f	1836	*
cparata	0:f27ce43dee4f	1837	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1838	* @param uint8_t address: page line address
cparata	0:f27ce43dee4f	1839	* @param val read value
cparata	0:f27ce43dee4f	1840	*
cparata	0:f27ce43dee4f	1841	*/
cparata	0:f27ce43dee4f	1842	int32_t lsm6dsox_ln_pg_read_byte(lsm6dsox_ctx_t *ctx, uint16_t address,
cparata	0:f27ce43dee4f	1843	uint8_t *val)
cparata	0:f27ce43dee4f	1844	{
cparata	0:f27ce43dee4f	1845	lsm6dsox_page_rw_t page_rw;
cparata	0:f27ce43dee4f	1846	lsm6dsox_page_sel_t page_sel;
cparata	0:f27ce43dee4f	1847	lsm6dsox_page_address_t page_address;
cparata	0:f27ce43dee4f	1848	int32_t ret;
cparata	0:f27ce43dee4f	1849
cparata	0:f27ce43dee4f	1850	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	1851	if (ret == 0) {
cparata	0:f27ce43dee4f	1852
cparata	0:f27ce43dee4f	1853	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1854	}
cparata	0:f27ce43dee4f	1855	if (ret == 0) {
cparata	0:f27ce43dee4f	1856	page_rw.page_rw = 0x01; /* page_read enable*/
cparata	0:f27ce43dee4f	1857	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1858	}
cparata	0:f27ce43dee4f	1859	if (ret == 0) {
cparata	0:f27ce43dee4f	1860
cparata	0:f27ce43dee4f	1861	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:f27ce43dee4f	1862	}
cparata	0:f27ce43dee4f	1863	if (ret == 0) {
cparata	0:f27ce43dee4f	1864	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	0:f27ce43dee4f	1865	page_sel.not_used_01 = 1;
cparata	0:f27ce43dee4f	1866	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:f27ce43dee4f	1867	}
cparata	0:f27ce43dee4f	1868	if (ret == 0) {
cparata	0:f27ce43dee4f	1869	page_address.page_addr = (uint8_t)address & 0x00FFU;
cparata	0:f27ce43dee4f	1870	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
cparata	0:f27ce43dee4f	1871	(uint8_t*)&page_address, 1);
cparata	0:f27ce43dee4f	1872	}
cparata	0:f27ce43dee4f	1873	if (ret == 0) {
cparata	0:f27ce43dee4f	1874
cparata	1:fe40aec6e97a	1875	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1);
cparata	0:f27ce43dee4f	1876	}
cparata	0:f27ce43dee4f	1877	if (ret == 0) {
cparata	0:f27ce43dee4f	1878	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1879	}
cparata	0:f27ce43dee4f	1880	if (ret == 0) {
cparata	0:f27ce43dee4f	1881	page_rw.page_rw = 0x00; /* page_read disable */
cparata	0:f27ce43dee4f	1882	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	1883	}
cparata	0:f27ce43dee4f	1884	if (ret == 0) {
cparata	0:f27ce43dee4f	1885	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	1886	}
cparata	0:f27ce43dee4f	1887
cparata	0:f27ce43dee4f	1888	return ret;
cparata	0:f27ce43dee4f	1889	}
cparata	0:f27ce43dee4f	1890
cparata	0:f27ce43dee4f	1891	/**
cparata	0:f27ce43dee4f	1892	* @brief Data-ready pulsed / letched mode.[set]
cparata	0:f27ce43dee4f	1893	*
cparata	0:f27ce43dee4f	1894	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1895	* @param val change the values of
cparata	0:f27ce43dee4f	1896	* dataready_pulsed in
cparata	0:f27ce43dee4f	1897	* reg COUNTER_BDR_REG1
cparata	0:f27ce43dee4f	1898	*
cparata	0:f27ce43dee4f	1899	*/
cparata	0:f27ce43dee4f	1900	int32_t lsm6dsox_data_ready_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	1901	lsm6dsox_dataready_pulsed_t val)
cparata	0:f27ce43dee4f	1902	{
cparata	0:f27ce43dee4f	1903	lsm6dsox_counter_bdr_reg1_t reg;
cparata	0:f27ce43dee4f	1904	int32_t ret;
cparata	0:f27ce43dee4f	1905
cparata	0:f27ce43dee4f	1906	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1907	if (ret == 0) {
cparata	0:f27ce43dee4f	1908	reg.dataready_pulsed = (uint8_t)val;
cparata	0:f27ce43dee4f	1909	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1910	}
cparata	0:f27ce43dee4f	1911	return ret;
cparata	0:f27ce43dee4f	1912	}
cparata	0:f27ce43dee4f	1913
cparata	0:f27ce43dee4f	1914	/**
cparata	0:f27ce43dee4f	1915	* @brief Data-ready pulsed / letched mode.[get]
cparata	0:f27ce43dee4f	1916	*
cparata	0:f27ce43dee4f	1917	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1918	* @param val Get the values of
cparata	0:f27ce43dee4f	1919	* dataready_pulsed in
cparata	0:f27ce43dee4f	1920	* reg COUNTER_BDR_REG1
cparata	0:f27ce43dee4f	1921	*
cparata	0:f27ce43dee4f	1922	*/
cparata	0:f27ce43dee4f	1923	int32_t lsm6dsox_data_ready_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	1924	lsm6dsox_dataready_pulsed_t *val)
cparata	0:f27ce43dee4f	1925	{
cparata	0:f27ce43dee4f	1926	lsm6dsox_counter_bdr_reg1_t reg;
cparata	0:f27ce43dee4f	1927	int32_t ret;
cparata	0:f27ce43dee4f	1928
cparata	0:f27ce43dee4f	1929	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1930	switch (reg.dataready_pulsed) {
cparata	0:f27ce43dee4f	1931	case LSM6DSOX_DRDY_LATCHED:
cparata	0:f27ce43dee4f	1932	*val = LSM6DSOX_DRDY_LATCHED;
cparata	0:f27ce43dee4f	1933	break;
cparata	0:f27ce43dee4f	1934	case LSM6DSOX_DRDY_PULSED:
cparata	0:f27ce43dee4f	1935	*val = LSM6DSOX_DRDY_PULSED;
cparata	0:f27ce43dee4f	1936	break;
cparata	0:f27ce43dee4f	1937	default:
cparata	0:f27ce43dee4f	1938	*val = LSM6DSOX_DRDY_LATCHED;
cparata	0:f27ce43dee4f	1939	break;
cparata	0:f27ce43dee4f	1940	}
cparata	0:f27ce43dee4f	1941	return ret;
cparata	0:f27ce43dee4f	1942	}
cparata	0:f27ce43dee4f	1943
cparata	0:f27ce43dee4f	1944	/**
cparata	0:f27ce43dee4f	1945	* @brief Device "Who am I".[get]
cparata	0:f27ce43dee4f	1946	*
cparata	0:f27ce43dee4f	1947	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1948	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	1949	*
cparata	0:f27ce43dee4f	1950	*/
cparata	0:f27ce43dee4f	1951	int32_t lsm6dsox_device_id_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	1952	{
cparata	0:f27ce43dee4f	1953	int32_t ret;
cparata	0:f27ce43dee4f	1954	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I, buff, 1);
cparata	0:f27ce43dee4f	1955	return ret;
cparata	0:f27ce43dee4f	1956	}
cparata	0:f27ce43dee4f	1957
cparata	0:f27ce43dee4f	1958	/**
cparata	0:f27ce43dee4f	1959	* @brief Software reset. Restore the default values
cparata	0:f27ce43dee4f	1960	* in user registers[set]
cparata	0:f27ce43dee4f	1961	*
cparata	0:f27ce43dee4f	1962	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1963	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:f27ce43dee4f	1964	*
cparata	0:f27ce43dee4f	1965	*/
cparata	0:f27ce43dee4f	1966	int32_t lsm6dsox_reset_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	1967	{
cparata	0:f27ce43dee4f	1968	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	1969	int32_t ret;
cparata	0:f27ce43dee4f	1970
cparata	0:f27ce43dee4f	1971	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1972	if (ret == 0) {
cparata	0:f27ce43dee4f	1973	reg.sw_reset = val;
cparata	0:f27ce43dee4f	1974	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1975	}
cparata	0:f27ce43dee4f	1976
cparata	0:f27ce43dee4f	1977	return ret;
cparata	0:f27ce43dee4f	1978	}
cparata	0:f27ce43dee4f	1979
cparata	0:f27ce43dee4f	1980	/**
cparata	0:f27ce43dee4f	1981	* @brief Software reset. Restore the default values in user registers.[get]
cparata	0:f27ce43dee4f	1982	*
cparata	0:f27ce43dee4f	1983	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	1984	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:f27ce43dee4f	1985	*
cparata	0:f27ce43dee4f	1986	*/
cparata	0:f27ce43dee4f	1987	int32_t lsm6dsox_reset_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	1988	{
cparata	0:f27ce43dee4f	1989	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	1990	int32_t ret;
cparata	0:f27ce43dee4f	1991
cparata	0:f27ce43dee4f	1992	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	1993	*val = reg.sw_reset;
cparata	0:f27ce43dee4f	1994
cparata	0:f27ce43dee4f	1995	return ret;
cparata	0:f27ce43dee4f	1996	}
cparata	0:f27ce43dee4f	1997
cparata	0:f27ce43dee4f	1998	/**
cparata	0:f27ce43dee4f	1999	* @brief Register address automatically incremented during a multiple byte
cparata	0:f27ce43dee4f	2000	* access with a serial interface.[set]
cparata	0:f27ce43dee4f	2001	*
cparata	0:f27ce43dee4f	2002	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2003	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:f27ce43dee4f	2004	*
cparata	0:f27ce43dee4f	2005	*/
cparata	0:f27ce43dee4f	2006	int32_t lsm6dsox_auto_increment_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	2007	{
cparata	0:f27ce43dee4f	2008	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	2009	int32_t ret;
cparata	0:f27ce43dee4f	2010
cparata	0:f27ce43dee4f	2011	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2012	if (ret == 0) {
cparata	0:f27ce43dee4f	2013	reg.if_inc = val;
cparata	0:f27ce43dee4f	2014	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2015	}
cparata	0:f27ce43dee4f	2016	return ret;
cparata	0:f27ce43dee4f	2017	}
cparata	0:f27ce43dee4f	2018
cparata	0:f27ce43dee4f	2019	/**
cparata	0:f27ce43dee4f	2020	* @brief Register address automatically incremented during a multiple byte
cparata	0:f27ce43dee4f	2021	* access with a serial interface.[get]
cparata	0:f27ce43dee4f	2022	*
cparata	0:f27ce43dee4f	2023	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2024	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:f27ce43dee4f	2025	*
cparata	0:f27ce43dee4f	2026	*/
cparata	0:f27ce43dee4f	2027	int32_t lsm6dsox_auto_increment_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2028	{
cparata	0:f27ce43dee4f	2029	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	2030	int32_t ret;
cparata	0:f27ce43dee4f	2031
cparata	0:f27ce43dee4f	2032	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2033	*val = reg.if_inc;
cparata	0:f27ce43dee4f	2034
cparata	0:f27ce43dee4f	2035	return ret;
cparata	0:f27ce43dee4f	2036	}
cparata	0:f27ce43dee4f	2037
cparata	0:f27ce43dee4f	2038	/**
cparata	0:f27ce43dee4f	2039	* @brief Reboot memory content. Reload the calibration parameters.[set]
cparata	0:f27ce43dee4f	2040	*
cparata	0:f27ce43dee4f	2041	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2042	* @param val change the values of boot in reg CTRL3_C
cparata	0:f27ce43dee4f	2043	*
cparata	0:f27ce43dee4f	2044	*/
cparata	0:f27ce43dee4f	2045	int32_t lsm6dsox_boot_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	2046	{
cparata	0:f27ce43dee4f	2047	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	2048	int32_t ret;
cparata	0:f27ce43dee4f	2049
cparata	0:f27ce43dee4f	2050	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2051	if (ret == 0) {
cparata	0:f27ce43dee4f	2052	reg.boot = val;
cparata	0:f27ce43dee4f	2053	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2054	}
cparata	0:f27ce43dee4f	2055	return ret;
cparata	0:f27ce43dee4f	2056	}
cparata	0:f27ce43dee4f	2057
cparata	0:f27ce43dee4f	2058	/**
cparata	0:f27ce43dee4f	2059	* @brief Reboot memory content. Reload the calibration parameters.[get]
cparata	0:f27ce43dee4f	2060	*
cparata	0:f27ce43dee4f	2061	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2062	* @param val change the values of boot in reg CTRL3_C
cparata	0:f27ce43dee4f	2063	*
cparata	0:f27ce43dee4f	2064	*/
cparata	0:f27ce43dee4f	2065	int32_t lsm6dsox_boot_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2066	{
cparata	0:f27ce43dee4f	2067	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	2068	int32_t ret;
cparata	0:f27ce43dee4f	2069
cparata	0:f27ce43dee4f	2070	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2071	*val = reg.boot;
cparata	0:f27ce43dee4f	2072
cparata	0:f27ce43dee4f	2073	return ret;
cparata	0:f27ce43dee4f	2074	}
cparata	0:f27ce43dee4f	2075
cparata	0:f27ce43dee4f	2076	/**
cparata	0:f27ce43dee4f	2077	* @brief Linear acceleration sensor self-test enable.[set]
cparata	0:f27ce43dee4f	2078	*
cparata	0:f27ce43dee4f	2079	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2080	* @param val change the values of st_xl in reg CTRL5_C
cparata	0:f27ce43dee4f	2081	*
cparata	0:f27ce43dee4f	2082	*/
cparata	0:f27ce43dee4f	2083	int32_t lsm6dsox_xl_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t val)
cparata	0:f27ce43dee4f	2084	{
cparata	0:f27ce43dee4f	2085	lsm6dsox_ctrl5_c_t reg;
cparata	0:f27ce43dee4f	2086	int32_t ret;
cparata	0:f27ce43dee4f	2087
cparata	0:f27ce43dee4f	2088	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2089	if (ret == 0) {
cparata	0:f27ce43dee4f	2090	reg.st_xl = (uint8_t)val;
cparata	0:f27ce43dee4f	2091	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2092	}
cparata	0:f27ce43dee4f	2093	return ret;
cparata	0:f27ce43dee4f	2094	}
cparata	0:f27ce43dee4f	2095
cparata	0:f27ce43dee4f	2096	/**
cparata	0:f27ce43dee4f	2097	* @brief Linear acceleration sensor self-test enable.[get]
cparata	0:f27ce43dee4f	2098	*
cparata	0:f27ce43dee4f	2099	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2100	* @param val Get the values of st_xl in reg CTRL5_C
cparata	0:f27ce43dee4f	2101	*
cparata	0:f27ce43dee4f	2102	*/
cparata	0:f27ce43dee4f	2103	int32_t lsm6dsox_xl_self_test_get(lsm6dsox_ctx_t ctx, lsm6dsox_st_xl_t val)
cparata	0:f27ce43dee4f	2104	{
cparata	0:f27ce43dee4f	2105	lsm6dsox_ctrl5_c_t reg;
cparata	0:f27ce43dee4f	2106	int32_t ret;
cparata	0:f27ce43dee4f	2107
cparata	0:f27ce43dee4f	2108	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2109	switch (reg.st_xl) {
cparata	0:f27ce43dee4f	2110	case LSM6DSOX_XL_ST_DISABLE:
cparata	0:f27ce43dee4f	2111	*val = LSM6DSOX_XL_ST_DISABLE;
cparata	0:f27ce43dee4f	2112	break;
cparata	0:f27ce43dee4f	2113	case LSM6DSOX_XL_ST_POSITIVE:
cparata	0:f27ce43dee4f	2114	*val = LSM6DSOX_XL_ST_POSITIVE;
cparata	0:f27ce43dee4f	2115	break;
cparata	0:f27ce43dee4f	2116	case LSM6DSOX_XL_ST_NEGATIVE:
cparata	0:f27ce43dee4f	2117	*val = LSM6DSOX_XL_ST_NEGATIVE;
cparata	0:f27ce43dee4f	2118	break;
cparata	0:f27ce43dee4f	2119	default:
cparata	0:f27ce43dee4f	2120	*val = LSM6DSOX_XL_ST_DISABLE;
cparata	0:f27ce43dee4f	2121	break;
cparata	0:f27ce43dee4f	2122	}
cparata	0:f27ce43dee4f	2123	return ret;
cparata	0:f27ce43dee4f	2124	}
cparata	0:f27ce43dee4f	2125
cparata	0:f27ce43dee4f	2126	/**
cparata	0:f27ce43dee4f	2127	* @brief Angular rate sensor self-test enable.[set]
cparata	0:f27ce43dee4f	2128	*
cparata	0:f27ce43dee4f	2129	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2130	* @param val change the values of st_g in reg CTRL5_C
cparata	0:f27ce43dee4f	2131	*
cparata	0:f27ce43dee4f	2132	*/
cparata	0:f27ce43dee4f	2133	int32_t lsm6dsox_gy_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t val)
cparata	0:f27ce43dee4f	2134	{
cparata	0:f27ce43dee4f	2135	lsm6dsox_ctrl5_c_t reg;
cparata	0:f27ce43dee4f	2136	int32_t ret;
cparata	0:f27ce43dee4f	2137
cparata	0:f27ce43dee4f	2138	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2139	if (ret == 0) {
cparata	0:f27ce43dee4f	2140	reg.st_g = (uint8_t)val;
cparata	0:f27ce43dee4f	2141	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2142	}
cparata	0:f27ce43dee4f	2143	return ret;
cparata	0:f27ce43dee4f	2144	}
cparata	0:f27ce43dee4f	2145
cparata	0:f27ce43dee4f	2146	/**
cparata	0:f27ce43dee4f	2147	* @brief Angular rate sensor self-test enable.[get]
cparata	0:f27ce43dee4f	2148	*
cparata	0:f27ce43dee4f	2149	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2150	* @param val Get the values of st_g in reg CTRL5_C
cparata	0:f27ce43dee4f	2151	*
cparata	0:f27ce43dee4f	2152	*/
cparata	0:f27ce43dee4f	2153	int32_t lsm6dsox_gy_self_test_get(lsm6dsox_ctx_t ctx, lsm6dsox_st_g_t val)
cparata	0:f27ce43dee4f	2154	{
cparata	0:f27ce43dee4f	2155	lsm6dsox_ctrl5_c_t reg;
cparata	0:f27ce43dee4f	2156	int32_t ret;
cparata	0:f27ce43dee4f	2157
cparata	0:f27ce43dee4f	2158	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2159	switch (reg.st_g) {
cparata	0:f27ce43dee4f	2160	case LSM6DSOX_GY_ST_DISABLE:
cparata	0:f27ce43dee4f	2161	*val = LSM6DSOX_GY_ST_DISABLE;
cparata	0:f27ce43dee4f	2162	break;
cparata	0:f27ce43dee4f	2163	case LSM6DSOX_GY_ST_POSITIVE:
cparata	0:f27ce43dee4f	2164	*val = LSM6DSOX_GY_ST_POSITIVE;
cparata	0:f27ce43dee4f	2165	break;
cparata	0:f27ce43dee4f	2166	case LSM6DSOX_GY_ST_NEGATIVE:
cparata	0:f27ce43dee4f	2167	*val = LSM6DSOX_GY_ST_NEGATIVE;
cparata	0:f27ce43dee4f	2168	break;
cparata	0:f27ce43dee4f	2169	default:
cparata	0:f27ce43dee4f	2170	*val = LSM6DSOX_GY_ST_DISABLE;
cparata	0:f27ce43dee4f	2171	break;
cparata	0:f27ce43dee4f	2172	}
cparata	0:f27ce43dee4f	2173	return ret;
cparata	0:f27ce43dee4f	2174	}
cparata	0:f27ce43dee4f	2175
cparata	0:f27ce43dee4f	2176	/**
cparata	0:f27ce43dee4f	2177	* @}
cparata	0:f27ce43dee4f	2178	*
cparata	0:f27ce43dee4f	2179	*/
cparata	0:f27ce43dee4f	2180
cparata	0:f27ce43dee4f	2181	/**
cparata	0:f27ce43dee4f	2182	* @defgroup LSM6DSOX_filters
cparata	0:f27ce43dee4f	2183	* @brief This section group all the functions concerning the
cparata	0:f27ce43dee4f	2184	* filters configuration
cparata	0:f27ce43dee4f	2185	* @{
cparata	0:f27ce43dee4f	2186	*
cparata	0:f27ce43dee4f	2187	*/
cparata	0:f27ce43dee4f	2188
cparata	0:f27ce43dee4f	2189	/**
cparata	0:f27ce43dee4f	2190	* @brief Accelerometer output from LPF2 filtering stage selection.[set]
cparata	0:f27ce43dee4f	2191	*
cparata	0:f27ce43dee4f	2192	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2193	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:f27ce43dee4f	2194	*
cparata	0:f27ce43dee4f	2195	*/
cparata	0:f27ce43dee4f	2196	int32_t lsm6dsox_xl_filter_lp2_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	2197	{
cparata	0:f27ce43dee4f	2198	lsm6dsox_ctrl1_xl_t reg;
cparata	0:f27ce43dee4f	2199	int32_t ret;
cparata	0:f27ce43dee4f	2200
cparata	0:f27ce43dee4f	2201	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2202	if (ret == 0) {
cparata	0:f27ce43dee4f	2203	reg.lpf2_xl_en = val;
cparata	0:f27ce43dee4f	2204	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2205	}
cparata	0:f27ce43dee4f	2206	return ret;
cparata	0:f27ce43dee4f	2207	}
cparata	0:f27ce43dee4f	2208
cparata	0:f27ce43dee4f	2209	/**
cparata	0:f27ce43dee4f	2210	* @brief Accelerometer output from LPF2 filtering stage selection.[get]
cparata	0:f27ce43dee4f	2211	*
cparata	0:f27ce43dee4f	2212	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2213	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:f27ce43dee4f	2214	*
cparata	0:f27ce43dee4f	2215	*/
cparata	0:f27ce43dee4f	2216	int32_t lsm6dsox_xl_filter_lp2_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2217	{
cparata	0:f27ce43dee4f	2218	lsm6dsox_ctrl1_xl_t reg;
cparata	0:f27ce43dee4f	2219	int32_t ret;
cparata	0:f27ce43dee4f	2220
cparata	0:f27ce43dee4f	2221	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2222	*val = reg.lpf2_xl_en;
cparata	0:f27ce43dee4f	2223
cparata	0:f27ce43dee4f	2224	return ret;
cparata	0:f27ce43dee4f	2225	}
cparata	0:f27ce43dee4f	2226
cparata	0:f27ce43dee4f	2227	/**
cparata	0:f27ce43dee4f	2228	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:f27ce43dee4f	2229	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:f27ce43dee4f	2230	* in CTRL6_C (15h).[set]
cparata	0:f27ce43dee4f	2231	*
cparata	0:f27ce43dee4f	2232	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2233	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:f27ce43dee4f	2234	*
cparata	0:f27ce43dee4f	2235	*/
cparata	0:f27ce43dee4f	2236	int32_t lsm6dsox_gy_filter_lp1_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	2237	{
cparata	0:f27ce43dee4f	2238	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	2239	int32_t ret;
cparata	0:f27ce43dee4f	2240
cparata	0:f27ce43dee4f	2241	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2242	if (ret == 0) {
cparata	0:f27ce43dee4f	2243	reg.lpf1_sel_g = val;
cparata	0:f27ce43dee4f	2244	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2245	}
cparata	0:f27ce43dee4f	2246	return ret;
cparata	0:f27ce43dee4f	2247	}
cparata	0:f27ce43dee4f	2248
cparata	0:f27ce43dee4f	2249	/**
cparata	0:f27ce43dee4f	2250	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:f27ce43dee4f	2251	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:f27ce43dee4f	2252	* in CTRL6_C (15h).[get]
cparata	0:f27ce43dee4f	2253	*
cparata	0:f27ce43dee4f	2254	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2255	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:f27ce43dee4f	2256	*
cparata	0:f27ce43dee4f	2257	*/
cparata	0:f27ce43dee4f	2258	int32_t lsm6dsox_gy_filter_lp1_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2259	{
cparata	0:f27ce43dee4f	2260	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	2261	int32_t ret;
cparata	0:f27ce43dee4f	2262
cparata	0:f27ce43dee4f	2263	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2264	*val = reg.lpf1_sel_g;
cparata	0:f27ce43dee4f	2265
cparata	0:f27ce43dee4f	2266	return ret;
cparata	0:f27ce43dee4f	2267	}
cparata	0:f27ce43dee4f	2268
cparata	0:f27ce43dee4f	2269	/**
cparata	0:f27ce43dee4f	2270	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:f27ce43dee4f	2271	* (XL and Gyro independently masked).[set]
cparata	0:f27ce43dee4f	2272	*
cparata	0:f27ce43dee4f	2273	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2274	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:f27ce43dee4f	2275	*
cparata	0:f27ce43dee4f	2276	*/
cparata	0:f27ce43dee4f	2277	int32_t lsm6dsox_filter_settling_mask_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	2278	{
cparata	0:f27ce43dee4f	2279	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	2280	int32_t ret;
cparata	0:f27ce43dee4f	2281
cparata	0:f27ce43dee4f	2282	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2283	if (ret == 0) {
cparata	0:f27ce43dee4f	2284	reg.drdy_mask = val;
cparata	0:f27ce43dee4f	2285	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2286	}
cparata	0:f27ce43dee4f	2287	return ret;
cparata	0:f27ce43dee4f	2288	}
cparata	0:f27ce43dee4f	2289
cparata	0:f27ce43dee4f	2290	/**
cparata	0:f27ce43dee4f	2291	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:f27ce43dee4f	2292	* (XL and Gyro independently masked).[get]
cparata	0:f27ce43dee4f	2293	*
cparata	0:f27ce43dee4f	2294	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2295	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:f27ce43dee4f	2296	*
cparata	0:f27ce43dee4f	2297	*/
cparata	0:f27ce43dee4f	2298	int32_t lsm6dsox_filter_settling_mask_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2299	{
cparata	0:f27ce43dee4f	2300	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	2301	int32_t ret;
cparata	0:f27ce43dee4f	2302
cparata	0:f27ce43dee4f	2303	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2304	*val = reg.drdy_mask;
cparata	0:f27ce43dee4f	2305
cparata	0:f27ce43dee4f	2306	return ret;
cparata	0:f27ce43dee4f	2307	}
cparata	0:f27ce43dee4f	2308
cparata	0:f27ce43dee4f	2309	/**
cparata	0:f27ce43dee4f	2310	* @brief Gyroscope lp1 bandwidth.[set]
cparata	0:f27ce43dee4f	2311	*
cparata	0:f27ce43dee4f	2312	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2313	* @param val change the values of ftype in reg CTRL6_C
cparata	0:f27ce43dee4f	2314	*
cparata	0:f27ce43dee4f	2315	*/
cparata	0:f27ce43dee4f	2316	int32_t lsm6dsox_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ftype_t val)
cparata	0:f27ce43dee4f	2317	{
cparata	0:f27ce43dee4f	2318	lsm6dsox_ctrl6_c_t reg;
cparata	0:f27ce43dee4f	2319	int32_t ret;
cparata	0:f27ce43dee4f	2320
cparata	0:f27ce43dee4f	2321	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2322	if (ret == 0) {
cparata	0:f27ce43dee4f	2323	reg.ftype = (uint8_t)val;
cparata	0:f27ce43dee4f	2324	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2325	}
cparata	0:f27ce43dee4f	2326	return ret;
cparata	0:f27ce43dee4f	2327	}
cparata	0:f27ce43dee4f	2328
cparata	0:f27ce43dee4f	2329	/**
cparata	0:f27ce43dee4f	2330	* @brief Gyroscope lp1 bandwidth.[get]
cparata	0:f27ce43dee4f	2331	*
cparata	0:f27ce43dee4f	2332	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2333	* @param val Get the values of ftype in reg CTRL6_C
cparata	0:f27ce43dee4f	2334	*
cparata	0:f27ce43dee4f	2335	*/
cparata	0:f27ce43dee4f	2336	int32_t lsm6dsox_gy_lp1_bandwidth_get(lsm6dsox_ctx_t ctx, lsm6dsox_ftype_t val)
cparata	0:f27ce43dee4f	2337	{
cparata	0:f27ce43dee4f	2338	lsm6dsox_ctrl6_c_t reg;
cparata	0:f27ce43dee4f	2339	int32_t ret;
cparata	0:f27ce43dee4f	2340
cparata	0:f27ce43dee4f	2341	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2342	switch (reg.ftype) {
cparata	0:f27ce43dee4f	2343	case LSM6DSOX_ULTRA_LIGHT:
cparata	0:f27ce43dee4f	2344	*val = LSM6DSOX_ULTRA_LIGHT;
cparata	0:f27ce43dee4f	2345	break;
cparata	0:f27ce43dee4f	2346	case LSM6DSOX_VERY_LIGHT:
cparata	0:f27ce43dee4f	2347	*val = LSM6DSOX_VERY_LIGHT;
cparata	0:f27ce43dee4f	2348	break;
cparata	0:f27ce43dee4f	2349	case LSM6DSOX_LIGHT:
cparata	0:f27ce43dee4f	2350	*val = LSM6DSOX_LIGHT;
cparata	0:f27ce43dee4f	2351	break;
cparata	0:f27ce43dee4f	2352	case LSM6DSOX_MEDIUM:
cparata	0:f27ce43dee4f	2353	*val = LSM6DSOX_MEDIUM;
cparata	0:f27ce43dee4f	2354	break;
cparata	0:f27ce43dee4f	2355	case LSM6DSOX_STRONG:
cparata	0:f27ce43dee4f	2356	*val = LSM6DSOX_STRONG;
cparata	0:f27ce43dee4f	2357	break;
cparata	0:f27ce43dee4f	2358	case LSM6DSOX_VERY_STRONG:
cparata	0:f27ce43dee4f	2359	*val = LSM6DSOX_VERY_STRONG;
cparata	0:f27ce43dee4f	2360	break;
cparata	0:f27ce43dee4f	2361	case LSM6DSOX_AGGRESSIVE:
cparata	0:f27ce43dee4f	2362	*val = LSM6DSOX_AGGRESSIVE;
cparata	0:f27ce43dee4f	2363	break;
cparata	0:f27ce43dee4f	2364	case LSM6DSOX_XTREME:
cparata	0:f27ce43dee4f	2365	*val = LSM6DSOX_XTREME;
cparata	0:f27ce43dee4f	2366	break;
cparata	0:f27ce43dee4f	2367	default:
cparata	0:f27ce43dee4f	2368	*val = LSM6DSOX_ULTRA_LIGHT;
cparata	0:f27ce43dee4f	2369	break;
cparata	0:f27ce43dee4f	2370	}
cparata	0:f27ce43dee4f	2371	return ret;
cparata	0:f27ce43dee4f	2372	}
cparata	0:f27ce43dee4f	2373
cparata	0:f27ce43dee4f	2374	/**
cparata	0:f27ce43dee4f	2375	* @brief Low pass filter 2 on 6D function selection.[set]
cparata	0:f27ce43dee4f	2376	*
cparata	0:f27ce43dee4f	2377	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2378	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:f27ce43dee4f	2379	*
cparata	0:f27ce43dee4f	2380	*/
cparata	0:f27ce43dee4f	2381	int32_t lsm6dsox_xl_lp2_on_6d_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	2382	{
cparata	0:f27ce43dee4f	2383	lsm6dsox_ctrl8_xl_t reg;
cparata	0:f27ce43dee4f	2384	int32_t ret;
cparata	0:f27ce43dee4f	2385
cparata	0:f27ce43dee4f	2386	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2387	if (ret == 0) {
cparata	0:f27ce43dee4f	2388	reg.low_pass_on_6d = val;
cparata	0:f27ce43dee4f	2389	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2390	}
cparata	0:f27ce43dee4f	2391	return ret;
cparata	0:f27ce43dee4f	2392	}
cparata	0:f27ce43dee4f	2393
cparata	0:f27ce43dee4f	2394	/**
cparata	0:f27ce43dee4f	2395	* @brief Low pass filter 2 on 6D function selection.[get]
cparata	0:f27ce43dee4f	2396	*
cparata	0:f27ce43dee4f	2397	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2398	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:f27ce43dee4f	2399	*
cparata	0:f27ce43dee4f	2400	*/
cparata	0:f27ce43dee4f	2401	int32_t lsm6dsox_xl_lp2_on_6d_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2402	{
cparata	0:f27ce43dee4f	2403	lsm6dsox_ctrl8_xl_t reg;
cparata	0:f27ce43dee4f	2404	int32_t ret;
cparata	0:f27ce43dee4f	2405
cparata	0:f27ce43dee4f	2406	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2407	*val = reg.low_pass_on_6d;
cparata	0:f27ce43dee4f	2408
cparata	0:f27ce43dee4f	2409	return ret;
cparata	0:f27ce43dee4f	2410	}
cparata	0:f27ce43dee4f	2411
cparata	0:f27ce43dee4f	2412	/**
cparata	0:f27ce43dee4f	2413	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:f27ce43dee4f	2414	* on output.[set]
cparata	0:f27ce43dee4f	2415	*
cparata	0:f27ce43dee4f	2416	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2417	* @param val change the values of hp_slope_xl_en
cparata	0:f27ce43dee4f	2418	* in reg CTRL8_XL
cparata	0:f27ce43dee4f	2419	*
cparata	0:f27ce43dee4f	2420	*/
cparata	0:f27ce43dee4f	2421	int32_t lsm6dsox_xl_hp_path_on_out_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2422	lsm6dsox_hp_slope_xl_en_t val)
cparata	0:f27ce43dee4f	2423	{
cparata	0:f27ce43dee4f	2424	lsm6dsox_ctrl8_xl_t reg;
cparata	0:f27ce43dee4f	2425	int32_t ret;
cparata	0:f27ce43dee4f	2426
cparata	0:f27ce43dee4f	2427	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2428	if (ret == 0) {
cparata	0:f27ce43dee4f	2429	reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
cparata	0:f27ce43dee4f	2430	reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
cparata	0:f27ce43dee4f	2431	reg.hpcf_xl = (uint8_t)val & 0x07U;
cparata	0:f27ce43dee4f	2432	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2433	}
cparata	0:f27ce43dee4f	2434	return ret;
cparata	0:f27ce43dee4f	2435	}
cparata	0:f27ce43dee4f	2436
cparata	0:f27ce43dee4f	2437	/**
cparata	0:f27ce43dee4f	2438	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:f27ce43dee4f	2439	* on output.[get]
cparata	0:f27ce43dee4f	2440	*
cparata	0:f27ce43dee4f	2441	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2442	* @param val Get the values of hp_slope_xl_en
cparata	0:f27ce43dee4f	2443	* in reg CTRL8_XL
cparata	0:f27ce43dee4f	2444	*
cparata	0:f27ce43dee4f	2445	*/
cparata	0:f27ce43dee4f	2446	int32_t lsm6dsox_xl_hp_path_on_out_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2447	lsm6dsox_hp_slope_xl_en_t *val)
cparata	0:f27ce43dee4f	2448	{
cparata	0:f27ce43dee4f	2449	lsm6dsox_ctrl8_xl_t reg;
cparata	0:f27ce43dee4f	2450	int32_t ret;
cparata	0:f27ce43dee4f	2451
cparata	0:f27ce43dee4f	2452	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2453	switch ((reg.hp_ref_mode_xl << 5) \| (reg.hp_slope_xl_en << 4) \|
cparata	0:f27ce43dee4f	2454	reg.hpcf_xl) {
cparata	0:f27ce43dee4f	2455	case LSM6DSOX_HP_PATH_DISABLE_ON_OUT:
cparata	0:f27ce43dee4f	2456	*val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT;
cparata	0:f27ce43dee4f	2457	break;
cparata	0:f27ce43dee4f	2458	case LSM6DSOX_SLOPE_ODR_DIV_4:
cparata	0:f27ce43dee4f	2459	*val = LSM6DSOX_SLOPE_ODR_DIV_4;
cparata	0:f27ce43dee4f	2460	break;
cparata	0:f27ce43dee4f	2461	case LSM6DSOX_HP_ODR_DIV_10:
cparata	0:f27ce43dee4f	2462	*val = LSM6DSOX_HP_ODR_DIV_10;
cparata	0:f27ce43dee4f	2463	break;
cparata	0:f27ce43dee4f	2464	case LSM6DSOX_HP_ODR_DIV_20:
cparata	0:f27ce43dee4f	2465	*val = LSM6DSOX_HP_ODR_DIV_20;
cparata	0:f27ce43dee4f	2466	break;
cparata	0:f27ce43dee4f	2467	case LSM6DSOX_HP_ODR_DIV_45:
cparata	0:f27ce43dee4f	2468	*val = LSM6DSOX_HP_ODR_DIV_45;
cparata	0:f27ce43dee4f	2469	break;
cparata	0:f27ce43dee4f	2470	case LSM6DSOX_HP_ODR_DIV_100:
cparata	0:f27ce43dee4f	2471	*val = LSM6DSOX_HP_ODR_DIV_100;
cparata	0:f27ce43dee4f	2472	break;
cparata	0:f27ce43dee4f	2473	case LSM6DSOX_HP_ODR_DIV_200:
cparata	0:f27ce43dee4f	2474	*val = LSM6DSOX_HP_ODR_DIV_200;
cparata	0:f27ce43dee4f	2475	break;
cparata	0:f27ce43dee4f	2476	case LSM6DSOX_HP_ODR_DIV_400:
cparata	0:f27ce43dee4f	2477	*val = LSM6DSOX_HP_ODR_DIV_400;
cparata	0:f27ce43dee4f	2478	break;
cparata	0:f27ce43dee4f	2479	case LSM6DSOX_HP_ODR_DIV_800:
cparata	0:f27ce43dee4f	2480	*val = LSM6DSOX_HP_ODR_DIV_800;
cparata	0:f27ce43dee4f	2481	break;
cparata	0:f27ce43dee4f	2482	case LSM6DSOX_HP_REF_MD_ODR_DIV_10:
cparata	0:f27ce43dee4f	2483	*val = LSM6DSOX_HP_REF_MD_ODR_DIV_10;
cparata	0:f27ce43dee4f	2484	break;
cparata	0:f27ce43dee4f	2485	case LSM6DSOX_HP_REF_MD_ODR_DIV_20:
cparata	0:f27ce43dee4f	2486	*val = LSM6DSOX_HP_REF_MD_ODR_DIV_20;
cparata	0:f27ce43dee4f	2487	break;
cparata	0:f27ce43dee4f	2488	case LSM6DSOX_HP_REF_MD_ODR_DIV_45:
cparata	0:f27ce43dee4f	2489	*val = LSM6DSOX_HP_REF_MD_ODR_DIV_45;
cparata	0:f27ce43dee4f	2490	break;
cparata	0:f27ce43dee4f	2491	case LSM6DSOX_HP_REF_MD_ODR_DIV_100:
cparata	0:f27ce43dee4f	2492	*val = LSM6DSOX_HP_REF_MD_ODR_DIV_100;
cparata	0:f27ce43dee4f	2493	break;
cparata	0:f27ce43dee4f	2494	case LSM6DSOX_HP_REF_MD_ODR_DIV_200:
cparata	0:f27ce43dee4f	2495	*val = LSM6DSOX_HP_REF_MD_ODR_DIV_200;
cparata	0:f27ce43dee4f	2496	break;
cparata	0:f27ce43dee4f	2497	case LSM6DSOX_HP_REF_MD_ODR_DIV_400:
cparata	0:f27ce43dee4f	2498	*val = LSM6DSOX_HP_REF_MD_ODR_DIV_400;
cparata	0:f27ce43dee4f	2499	break;
cparata	0:f27ce43dee4f	2500	case LSM6DSOX_HP_REF_MD_ODR_DIV_800:
cparata	0:f27ce43dee4f	2501	*val = LSM6DSOX_HP_REF_MD_ODR_DIV_800;
cparata	0:f27ce43dee4f	2502	break;
cparata	0:f27ce43dee4f	2503	case LSM6DSOX_LP_ODR_DIV_10:
cparata	0:f27ce43dee4f	2504	*val = LSM6DSOX_LP_ODR_DIV_10;
cparata	0:f27ce43dee4f	2505	break;
cparata	0:f27ce43dee4f	2506	case LSM6DSOX_LP_ODR_DIV_20:
cparata	0:f27ce43dee4f	2507	*val = LSM6DSOX_LP_ODR_DIV_20;
cparata	0:f27ce43dee4f	2508	break;
cparata	0:f27ce43dee4f	2509	case LSM6DSOX_LP_ODR_DIV_45:
cparata	0:f27ce43dee4f	2510	*val = LSM6DSOX_LP_ODR_DIV_45;
cparata	0:f27ce43dee4f	2511	break;
cparata	0:f27ce43dee4f	2512	case LSM6DSOX_LP_ODR_DIV_100:
cparata	0:f27ce43dee4f	2513	*val = LSM6DSOX_LP_ODR_DIV_100;
cparata	0:f27ce43dee4f	2514	break;
cparata	0:f27ce43dee4f	2515	case LSM6DSOX_LP_ODR_DIV_200:
cparata	0:f27ce43dee4f	2516	*val = LSM6DSOX_LP_ODR_DIV_200;
cparata	0:f27ce43dee4f	2517	break;
cparata	0:f27ce43dee4f	2518	case LSM6DSOX_LP_ODR_DIV_400:
cparata	0:f27ce43dee4f	2519	*val = LSM6DSOX_LP_ODR_DIV_400;
cparata	0:f27ce43dee4f	2520	break;
cparata	0:f27ce43dee4f	2521	case LSM6DSOX_LP_ODR_DIV_800:
cparata	0:f27ce43dee4f	2522	*val = LSM6DSOX_LP_ODR_DIV_800;
cparata	0:f27ce43dee4f	2523	break;
cparata	0:f27ce43dee4f	2524	default:
cparata	0:f27ce43dee4f	2525	*val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT;
cparata	0:f27ce43dee4f	2526	break;
cparata	0:f27ce43dee4f	2527	}
cparata	0:f27ce43dee4f	2528
cparata	0:f27ce43dee4f	2529	return ret;
cparata	0:f27ce43dee4f	2530	}
cparata	0:f27ce43dee4f	2531
cparata	0:f27ce43dee4f	2532	/**
cparata	0:f27ce43dee4f	2533	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:f27ce43dee4f	2534	* The filter sets the second samples after writing this bit.
cparata	0:f27ce43dee4f	2535	* Active only during device exit from power-down mode.[set]
cparata	0:f27ce43dee4f	2536	*
cparata	0:f27ce43dee4f	2537	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2538	* @param val change the values of fastsettl_mode_xl in
cparata	0:f27ce43dee4f	2539	* reg CTRL8_XL
cparata	0:f27ce43dee4f	2540	*
cparata	0:f27ce43dee4f	2541	*/
cparata	0:f27ce43dee4f	2542	int32_t lsm6dsox_xl_fast_settling_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	2543	{
cparata	0:f27ce43dee4f	2544	lsm6dsox_ctrl8_xl_t reg;
cparata	0:f27ce43dee4f	2545	int32_t ret;
cparata	0:f27ce43dee4f	2546
cparata	0:f27ce43dee4f	2547	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2548	if (ret == 0) {
cparata	0:f27ce43dee4f	2549	reg.fastsettl_mode_xl = val;
cparata	0:f27ce43dee4f	2550	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2551	}
cparata	0:f27ce43dee4f	2552	return ret;
cparata	0:f27ce43dee4f	2553	}
cparata	0:f27ce43dee4f	2554
cparata	0:f27ce43dee4f	2555	/**
cparata	0:f27ce43dee4f	2556	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:f27ce43dee4f	2557	* The filter sets the second samples after writing this bit.
cparata	0:f27ce43dee4f	2558	* Active only during device exit from power-down mode.[get]
cparata	0:f27ce43dee4f	2559	*
cparata	0:f27ce43dee4f	2560	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2561	* @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
cparata	0:f27ce43dee4f	2562	*
cparata	0:f27ce43dee4f	2563	*/
cparata	0:f27ce43dee4f	2564	int32_t lsm6dsox_xl_fast_settling_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2565	{
cparata	0:f27ce43dee4f	2566	lsm6dsox_ctrl8_xl_t reg;
cparata	0:f27ce43dee4f	2567	int32_t ret;
cparata	0:f27ce43dee4f	2568
cparata	0:f27ce43dee4f	2569	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2570	*val = reg.fastsettl_mode_xl;
cparata	0:f27ce43dee4f	2571
cparata	0:f27ce43dee4f	2572	return ret;
cparata	0:f27ce43dee4f	2573	}
cparata	0:f27ce43dee4f	2574
cparata	0:f27ce43dee4f	2575	/**
cparata	0:f27ce43dee4f	2576	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:f27ce43dee4f	2577	* functions.[set]
cparata	0:f27ce43dee4f	2578	*
cparata	0:f27ce43dee4f	2579	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2580	* @param val change the values of slope_fds in reg TAP_CFG0
cparata	0:f27ce43dee4f	2581	*
cparata	0:f27ce43dee4f	2582	*/
cparata	0:f27ce43dee4f	2583	int32_t lsm6dsox_xl_hp_path_internal_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2584	lsm6dsox_slope_fds_t val)
cparata	0:f27ce43dee4f	2585	{
cparata	0:f27ce43dee4f	2586	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	2587	int32_t ret;
cparata	0:f27ce43dee4f	2588
cparata	0:f27ce43dee4f	2589	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2590	if (ret == 0) {
cparata	0:f27ce43dee4f	2591	reg.slope_fds = (uint8_t)val;
cparata	0:f27ce43dee4f	2592	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2593	}
cparata	0:f27ce43dee4f	2594	return ret;
cparata	0:f27ce43dee4f	2595	}
cparata	0:f27ce43dee4f	2596
cparata	0:f27ce43dee4f	2597	/**
cparata	0:f27ce43dee4f	2598	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:f27ce43dee4f	2599	* functions.[get]
cparata	0:f27ce43dee4f	2600	*
cparata	0:f27ce43dee4f	2601	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2602	* @param val Change the values of slope_fds in reg TAP_CFG0
cparata	0:f27ce43dee4f	2603	*
cparata	0:f27ce43dee4f	2604	*/
cparata	0:f27ce43dee4f	2605	int32_t lsm6dsox_xl_hp_path_internal_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2606	lsm6dsox_slope_fds_t *val)
cparata	0:f27ce43dee4f	2607	{
cparata	0:f27ce43dee4f	2608	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	2609	int32_t ret;
cparata	0:f27ce43dee4f	2610
cparata	0:f27ce43dee4f	2611	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2612	switch (reg.slope_fds) {
cparata	0:f27ce43dee4f	2613	case LSM6DSOX_USE_SLOPE:
cparata	0:f27ce43dee4f	2614	*val = LSM6DSOX_USE_SLOPE;
cparata	0:f27ce43dee4f	2615	break;
cparata	0:f27ce43dee4f	2616	case LSM6DSOX_USE_HPF:
cparata	0:f27ce43dee4f	2617	*val = LSM6DSOX_USE_HPF;
cparata	0:f27ce43dee4f	2618	break;
cparata	0:f27ce43dee4f	2619	default:
cparata	0:f27ce43dee4f	2620	*val = LSM6DSOX_USE_SLOPE;
cparata	0:f27ce43dee4f	2621	break;
cparata	0:f27ce43dee4f	2622	}
cparata	0:f27ce43dee4f	2623	return ret;
cparata	0:f27ce43dee4f	2624	}
cparata	0:f27ce43dee4f	2625
cparata	0:f27ce43dee4f	2626	/**
cparata	0:f27ce43dee4f	2627	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:f27ce43dee4f	2628	* enabled only if the gyro is in HP mode.[set]
cparata	0:f27ce43dee4f	2629	*
cparata	0:f27ce43dee4f	2630	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2631	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:f27ce43dee4f	2632	* in reg CTRL7_G
cparata	0:f27ce43dee4f	2633	*
cparata	0:f27ce43dee4f	2634	*/
cparata	0:f27ce43dee4f	2635	int32_t lsm6dsox_gy_hp_path_internal_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2636	lsm6dsox_hpm_g_t val)
cparata	0:f27ce43dee4f	2637	{
cparata	0:f27ce43dee4f	2638	lsm6dsox_ctrl7_g_t reg;
cparata	0:f27ce43dee4f	2639	int32_t ret;
cparata	0:f27ce43dee4f	2640
cparata	0:f27ce43dee4f	2641	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2642	if (ret == 0) {
cparata	0:f27ce43dee4f	2643	reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
cparata	0:f27ce43dee4f	2644	reg.hpm_g = (uint8_t)val & 0x03U;
cparata	0:f27ce43dee4f	2645	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2646	}
cparata	0:f27ce43dee4f	2647	return ret;
cparata	0:f27ce43dee4f	2648	}
cparata	0:f27ce43dee4f	2649
cparata	0:f27ce43dee4f	2650	/**
cparata	0:f27ce43dee4f	2651	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:f27ce43dee4f	2652	* enabled only if the gyro is in HP mode.[get]
cparata	0:f27ce43dee4f	2653	*
cparata	0:f27ce43dee4f	2654	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2655	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:f27ce43dee4f	2656	* in reg CTRL7_G
cparata	0:f27ce43dee4f	2657	*
cparata	0:f27ce43dee4f	2658	*/
cparata	0:f27ce43dee4f	2659	int32_t lsm6dsox_gy_hp_path_internal_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2660	lsm6dsox_hpm_g_t *val)
cparata	0:f27ce43dee4f	2661	{
cparata	0:f27ce43dee4f	2662	lsm6dsox_ctrl7_g_t reg;
cparata	0:f27ce43dee4f	2663	int32_t ret;
cparata	0:f27ce43dee4f	2664
cparata	0:f27ce43dee4f	2665	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2666	switch ((reg.hp_en_g << 7) + reg.hpm_g) {
cparata	0:f27ce43dee4f	2667	case LSM6DSOX_HP_FILTER_NONE:
cparata	0:f27ce43dee4f	2668	*val = LSM6DSOX_HP_FILTER_NONE;
cparata	0:f27ce43dee4f	2669	break;
cparata	0:f27ce43dee4f	2670	case LSM6DSOX_HP_FILTER_16mHz:
cparata	0:f27ce43dee4f	2671	*val = LSM6DSOX_HP_FILTER_16mHz;
cparata	0:f27ce43dee4f	2672	break;
cparata	0:f27ce43dee4f	2673	case LSM6DSOX_HP_FILTER_65mHz:
cparata	0:f27ce43dee4f	2674	*val = LSM6DSOX_HP_FILTER_65mHz;
cparata	0:f27ce43dee4f	2675	break;
cparata	0:f27ce43dee4f	2676	case LSM6DSOX_HP_FILTER_260mHz:
cparata	0:f27ce43dee4f	2677	*val = LSM6DSOX_HP_FILTER_260mHz;
cparata	0:f27ce43dee4f	2678	break;
cparata	0:f27ce43dee4f	2679	case LSM6DSOX_HP_FILTER_1Hz04:
cparata	0:f27ce43dee4f	2680	*val = LSM6DSOX_HP_FILTER_1Hz04;
cparata	0:f27ce43dee4f	2681	break;
cparata	0:f27ce43dee4f	2682	default:
cparata	0:f27ce43dee4f	2683	*val = LSM6DSOX_HP_FILTER_NONE;
cparata	0:f27ce43dee4f	2684	break;
cparata	0:f27ce43dee4f	2685	}
cparata	0:f27ce43dee4f	2686	return ret;
cparata	0:f27ce43dee4f	2687	}
cparata	0:f27ce43dee4f	2688
cparata	0:f27ce43dee4f	2689	/**
cparata	0:f27ce43dee4f	2690	* @}
cparata	0:f27ce43dee4f	2691	*
cparata	0:f27ce43dee4f	2692	*/
cparata	0:f27ce43dee4f	2693
cparata	0:f27ce43dee4f	2694	/**
cparata	0:f27ce43dee4f	2695	* @defgroup LSM6DSOX_ Auxiliary_interface
cparata	0:f27ce43dee4f	2696	* @brief This section groups all the functions concerning
cparata	0:f27ce43dee4f	2697	* auxiliary interface.
cparata	0:f27ce43dee4f	2698	* @{
cparata	0:f27ce43dee4f	2699	*
cparata	0:f27ce43dee4f	2700	*/
cparata	0:f27ce43dee4f	2701
cparata	0:f27ce43dee4f	2702	/**
cparata	0:f27ce43dee4f	2703	* @brief OIS data reading from Auxiliary / Main SPI.[set]
cparata	0:f27ce43dee4f	2704	*
cparata	0:f27ce43dee4f	2705	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2706	* @param val change the values of spi2_read_en in reg UI_INT_OIS
cparata	0:f27ce43dee4f	2707	*
cparata	0:f27ce43dee4f	2708	*/
cparata	0:f27ce43dee4f	2709	int32_t lsm6dsox_ois_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_spi2_read_en_t val)
cparata	0:f27ce43dee4f	2710	{
cparata	0:f27ce43dee4f	2711	lsm6dsox_func_cfg_access_t func_cfg_access;
cparata	0:f27ce43dee4f	2712	lsm6dsox_ui_int_ois_t ui_int_ois;
cparata	0:f27ce43dee4f	2713	int32_t ret;
cparata	0:f27ce43dee4f	2714
cparata	0:f27ce43dee4f	2715	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1);
cparata	0:f27ce43dee4f	2716	if (ret == 0) {
cparata	0:f27ce43dee4f	2717	ui_int_ois.spi2_read_en = ((uint8_t)val & 0x01U);
cparata	0:f27ce43dee4f	2718	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS,
cparata	0:f27ce43dee4f	2719	(uint8_t*)&ui_int_ois, 1);
cparata	0:f27ce43dee4f	2720	}
cparata	0:f27ce43dee4f	2721	if (ret == 0) {
cparata	0:f27ce43dee4f	2722	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
cparata	0:f27ce43dee4f	2723	(uint8_t*)&func_cfg_access, 1);
cparata	0:f27ce43dee4f	2724	}
cparata	0:f27ce43dee4f	2725	if (ret == 0) {
cparata	0:f27ce43dee4f	2726	func_cfg_access.ois_ctrl_from_ui = ( ((uint8_t)val & 0x02U) >> 1 );
cparata	0:f27ce43dee4f	2727	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
cparata	0:f27ce43dee4f	2728	(uint8_t*)&func_cfg_access, 1);
cparata	0:f27ce43dee4f	2729	}
cparata	0:f27ce43dee4f	2730	return ret;
cparata	0:f27ce43dee4f	2731	}
cparata	0:f27ce43dee4f	2732
cparata	0:f27ce43dee4f	2733	/**
cparata	0:f27ce43dee4f	2734	* @brief aux_ois_data: [get] OIS data reading from Auxiliary / Main SPI
cparata	0:f27ce43dee4f	2735	*
cparata	0:f27ce43dee4f	2736	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2737	* @param val Get the values of spi2_read_en
cparata	0:f27ce43dee4f	2738	* in reg UI_INT_OIS
cparata	0:f27ce43dee4f	2739	*
cparata	0:f27ce43dee4f	2740	*/
cparata	0:f27ce43dee4f	2741	int32_t lsm6dsox_ois_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2742	lsm6dsox_spi2_read_en_t *val)
cparata	0:f27ce43dee4f	2743	{
cparata	0:f27ce43dee4f	2744	lsm6dsox_func_cfg_access_t func_cfg_access;
cparata	0:f27ce43dee4f	2745	lsm6dsox_ui_int_ois_t ui_int_ois;
cparata	0:f27ce43dee4f	2746	int32_t ret;
cparata	0:f27ce43dee4f	2747
cparata	0:f27ce43dee4f	2748	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1);
cparata	0:f27ce43dee4f	2749	if (ret == 0) {
cparata	0:f27ce43dee4f	2750	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
cparata	0:f27ce43dee4f	2751	(uint8_t*)&func_cfg_access, 1);
cparata	0:f27ce43dee4f	2752	}
cparata	0:f27ce43dee4f	2753	switch ((func_cfg_access.ois_ctrl_from_ui << 1) + ui_int_ois.spi2_read_en) {
cparata	0:f27ce43dee4f	2754	case LSM6DSOX_OIS_CTRL_AUX_DATA_UI:
cparata	0:f27ce43dee4f	2755	*val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI;
cparata	0:f27ce43dee4f	2756	break;
cparata	0:f27ce43dee4f	2757	case LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX:
cparata	0:f27ce43dee4f	2758	*val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX;
cparata	0:f27ce43dee4f	2759	break;
cparata	0:f27ce43dee4f	2760	case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI:
cparata	0:f27ce43dee4f	2761	*val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI;
cparata	0:f27ce43dee4f	2762	break;
cparata	0:f27ce43dee4f	2763	case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX:
cparata	0:f27ce43dee4f	2764	*val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX;
cparata	0:f27ce43dee4f	2765	break;
cparata	0:f27ce43dee4f	2766	default:
cparata	0:f27ce43dee4f	2767	*val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI;
cparata	0:f27ce43dee4f	2768	break;
cparata	0:f27ce43dee4f	2769	}
cparata	0:f27ce43dee4f	2770	return ret;
cparata	0:f27ce43dee4f	2771	}
cparata	0:f27ce43dee4f	2772
cparata	0:f27ce43dee4f	2773	/**
cparata	0:f27ce43dee4f	2774	* @brief aOn auxiliary interface connect/disconnect SDO and OCS
cparata	0:f27ce43dee4f	2775	* internal pull-up.[set]
cparata	0:f27ce43dee4f	2776	*
cparata	0:f27ce43dee4f	2777	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2778	* @param val change the values of ois_pu_dis in
cparata	0:f27ce43dee4f	2779	* reg PIN_CTRL
cparata	0:f27ce43dee4f	2780	*
cparata	0:f27ce43dee4f	2781	*/
cparata	0:f27ce43dee4f	2782	int32_t lsm6dsox_aux_sdo_ocs_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2783	lsm6dsox_ois_pu_dis_t val)
cparata	0:f27ce43dee4f	2784	{
cparata	0:f27ce43dee4f	2785	lsm6dsox_pin_ctrl_t reg;
cparata	0:f27ce43dee4f	2786	int32_t ret;
cparata	0:f27ce43dee4f	2787
cparata	0:f27ce43dee4f	2788	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2789	if (ret == 0) {
cparata	0:f27ce43dee4f	2790	reg.ois_pu_dis = (uint8_t)val;
cparata	0:f27ce43dee4f	2791	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2792	}
cparata	0:f27ce43dee4f	2793	return ret;
cparata	0:f27ce43dee4f	2794	}
cparata	0:f27ce43dee4f	2795
cparata	0:f27ce43dee4f	2796	/**
cparata	0:f27ce43dee4f	2797	* @brief On auxiliary interface connect/disconnect SDO and OCS
cparata	0:f27ce43dee4f	2798	* internal pull-up.[get]
cparata	0:f27ce43dee4f	2799	*
cparata	0:f27ce43dee4f	2800	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2801	* @param val Get the values of ois_pu_dis in reg PIN_CTRL
cparata	0:f27ce43dee4f	2802	*
cparata	0:f27ce43dee4f	2803	*/
cparata	0:f27ce43dee4f	2804	int32_t lsm6dsox_aux_sdo_ocs_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2805	lsm6dsox_ois_pu_dis_t *val)
cparata	0:f27ce43dee4f	2806	{
cparata	0:f27ce43dee4f	2807	lsm6dsox_pin_ctrl_t reg;
cparata	0:f27ce43dee4f	2808	int32_t ret;
cparata	0:f27ce43dee4f	2809
cparata	0:f27ce43dee4f	2810	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2811	switch (reg.ois_pu_dis) {
cparata	0:f27ce43dee4f	2812	case LSM6DSOX_AUX_PULL_UP_DISC:
cparata	0:f27ce43dee4f	2813	*val = LSM6DSOX_AUX_PULL_UP_DISC;
cparata	0:f27ce43dee4f	2814	break;
cparata	0:f27ce43dee4f	2815	case LSM6DSOX_AUX_PULL_UP_CONNECT:
cparata	0:f27ce43dee4f	2816	*val = LSM6DSOX_AUX_PULL_UP_CONNECT;
cparata	0:f27ce43dee4f	2817	break;
cparata	0:f27ce43dee4f	2818	default:
cparata	0:f27ce43dee4f	2819	*val = LSM6DSOX_AUX_PULL_UP_DISC;
cparata	0:f27ce43dee4f	2820	break;
cparata	0:f27ce43dee4f	2821	}
cparata	0:f27ce43dee4f	2822	return ret;
cparata	0:f27ce43dee4f	2823	}
cparata	0:f27ce43dee4f	2824
cparata	0:f27ce43dee4f	2825	/**
cparata	0:f27ce43dee4f	2826	* @brief OIS chain on aux interface power on mode.[set]
cparata	0:f27ce43dee4f	2827	*
cparata	0:f27ce43dee4f	2828	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2829	* @param val change the values of ois_on in reg CTRL7_G
cparata	0:f27ce43dee4f	2830	*
cparata	0:f27ce43dee4f	2831	*/
cparata	0:f27ce43dee4f	2832	int32_t lsm6dsox_aux_pw_on_ctrl_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t val)
cparata	0:f27ce43dee4f	2833	{
cparata	0:f27ce43dee4f	2834	lsm6dsox_ctrl7_g_t reg;
cparata	0:f27ce43dee4f	2835	int32_t ret;
cparata	0:f27ce43dee4f	2836
cparata	0:f27ce43dee4f	2837	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2838	if (ret == 0) {
cparata	0:f27ce43dee4f	2839	reg.ois_on_en = (uint8_t)val & 0x01U;
cparata	0:f27ce43dee4f	2840	reg.ois_on = (uint8_t)val & 0x01U;
cparata	0:f27ce43dee4f	2841	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2842	}
cparata	0:f27ce43dee4f	2843	return ret;
cparata	0:f27ce43dee4f	2844	}
cparata	0:f27ce43dee4f	2845
cparata	0:f27ce43dee4f	2846	/**
cparata	0:f27ce43dee4f	2847	* @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode
cparata	0:f27ce43dee4f	2848	*
cparata	0:f27ce43dee4f	2849	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2850	* @param val Get the values of ois_on in reg CTRL7_G
cparata	0:f27ce43dee4f	2851	*
cparata	0:f27ce43dee4f	2852	*/
cparata	0:f27ce43dee4f	2853	int32_t lsm6dsox_aux_pw_on_ctrl_get(lsm6dsox_ctx_t ctx, lsm6dsox_ois_on_t val)
cparata	0:f27ce43dee4f	2854	{
cparata	0:f27ce43dee4f	2855	lsm6dsox_ctrl7_g_t reg;
cparata	0:f27ce43dee4f	2856	int32_t ret;
cparata	0:f27ce43dee4f	2857
cparata	0:f27ce43dee4f	2858	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2859	switch (reg.ois_on) {
cparata	0:f27ce43dee4f	2860	case LSM6DSOX_AUX_ON:
cparata	0:f27ce43dee4f	2861	*val = LSM6DSOX_AUX_ON;
cparata	0:f27ce43dee4f	2862	break;
cparata	0:f27ce43dee4f	2863	case LSM6DSOX_AUX_ON_BY_AUX_INTERFACE:
cparata	0:f27ce43dee4f	2864	*val = LSM6DSOX_AUX_ON_BY_AUX_INTERFACE;
cparata	0:f27ce43dee4f	2865	break;
cparata	0:f27ce43dee4f	2866	default:
cparata	0:f27ce43dee4f	2867	*val = LSM6DSOX_AUX_ON;
cparata	0:f27ce43dee4f	2868	break;
cparata	0:f27ce43dee4f	2869	}
cparata	0:f27ce43dee4f	2870
cparata	0:f27ce43dee4f	2871	return ret;
cparata	0:f27ce43dee4f	2872	}
cparata	0:f27ce43dee4f	2873
cparata	0:f27ce43dee4f	2874	/**
cparata	0:f27ce43dee4f	2875	* @brief Accelerometer full-scale management between UI chain and
cparata	0:f27ce43dee4f	2876	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:f27ce43dee4f	2877	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:f27ce43dee4f	2878	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:f27ce43dee4f	2879	* Full scales are independent between the UI/OIS chain
cparata	0:f27ce43dee4f	2880	* but both bound to 8 g.[set]
cparata	0:f27ce43dee4f	2881	*
cparata	0:f27ce43dee4f	2882	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2883	* @param val change the values of xl_fs_mode in
cparata	0:f27ce43dee4f	2884	* reg CTRL8_XL
cparata	0:f27ce43dee4f	2885	*
cparata	0:f27ce43dee4f	2886	*/
cparata	0:f27ce43dee4f	2887	int32_t lsm6dsox_aux_xl_fs_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2888	lsm6dsox_xl_fs_mode_t val)
cparata	0:f27ce43dee4f	2889	{
cparata	0:f27ce43dee4f	2890	lsm6dsox_ctrl8_xl_t reg;
cparata	0:f27ce43dee4f	2891	int32_t ret;
cparata	0:f27ce43dee4f	2892
cparata	0:f27ce43dee4f	2893	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2894	if (ret == 0) {
cparata	0:f27ce43dee4f	2895	reg.xl_fs_mode = (uint8_t)val;
cparata	0:f27ce43dee4f	2896	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2897	}
cparata	0:f27ce43dee4f	2898	return ret;
cparata	0:f27ce43dee4f	2899	}
cparata	0:f27ce43dee4f	2900
cparata	0:f27ce43dee4f	2901	/**
cparata	0:f27ce43dee4f	2902	* @brief Accelerometer full-scale management between UI chain and
cparata	0:f27ce43dee4f	2903	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:f27ce43dee4f	2904	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:f27ce43dee4f	2905	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:f27ce43dee4f	2906	* Full scales are independent between the UI/OIS chain
cparata	0:f27ce43dee4f	2907	* but both bound to 8 g.[get]
cparata	0:f27ce43dee4f	2908	*
cparata	0:f27ce43dee4f	2909	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2910	* @param val Get the values of xl_fs_mode in reg CTRL8_XL
cparata	0:f27ce43dee4f	2911	*
cparata	0:f27ce43dee4f	2912	*/
cparata	0:f27ce43dee4f	2913	int32_t lsm6dsox_aux_xl_fs_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2914	lsm6dsox_xl_fs_mode_t *val)
cparata	0:f27ce43dee4f	2915	{
cparata	0:f27ce43dee4f	2916	lsm6dsox_ctrl8_xl_t reg;
cparata	0:f27ce43dee4f	2917	int32_t ret;
cparata	0:f27ce43dee4f	2918
cparata	0:f27ce43dee4f	2919	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2920	switch (reg.xl_fs_mode) {
cparata	0:f27ce43dee4f	2921	case LSM6DSOX_USE_SAME_XL_FS:
cparata	0:f27ce43dee4f	2922	*val = LSM6DSOX_USE_SAME_XL_FS;
cparata	0:f27ce43dee4f	2923	break;
cparata	0:f27ce43dee4f	2924	case LSM6DSOX_USE_DIFFERENT_XL_FS:
cparata	0:f27ce43dee4f	2925	*val = LSM6DSOX_USE_DIFFERENT_XL_FS;
cparata	0:f27ce43dee4f	2926	break;
cparata	0:f27ce43dee4f	2927	default:
cparata	0:f27ce43dee4f	2928	*val = LSM6DSOX_USE_SAME_XL_FS;
cparata	0:f27ce43dee4f	2929	break;
cparata	0:f27ce43dee4f	2930	}
cparata	0:f27ce43dee4f	2931
cparata	0:f27ce43dee4f	2932	return ret;
cparata	0:f27ce43dee4f	2933	}
cparata	0:f27ce43dee4f	2934
cparata	0:f27ce43dee4f	2935	/**
cparata	0:f27ce43dee4f	2936	* @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
cparata	0:f27ce43dee4f	2937	*
cparata	0:f27ce43dee4f	2938	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2939	* @param val Get registers STATUS_SPIAUX
cparata	0:f27ce43dee4f	2940	*
cparata	0:f27ce43dee4f	2941	*/
cparata	0:f27ce43dee4f	2942	int32_t lsm6dsox_aux_status_reg_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	2943	lsm6dsox_spi2_status_reg_ois_t *val)
cparata	0:f27ce43dee4f	2944	{
cparata	0:f27ce43dee4f	2945	int32_t ret;
cparata	0:f27ce43dee4f	2946	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*) val, 1);
cparata	0:f27ce43dee4f	2947	return ret;
cparata	0:f27ce43dee4f	2948	}
cparata	0:f27ce43dee4f	2949
cparata	0:f27ce43dee4f	2950	/**
cparata	0:f27ce43dee4f	2951	* @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available
cparata	0:f27ce43dee4f	2952	*
cparata	0:f27ce43dee4f	2953	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2954	* @param val change the values of xlda in reg STATUS_SPIAUX
cparata	0:f27ce43dee4f	2955	*
cparata	0:f27ce43dee4f	2956	*/
cparata	0:f27ce43dee4f	2957	int32_t lsm6dsox_aux_xl_flag_data_ready_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2958	{
cparata	0:f27ce43dee4f	2959	lsm6dsox_spi2_status_reg_ois_t reg;
cparata	0:f27ce43dee4f	2960	int32_t ret;
cparata	0:f27ce43dee4f	2961
cparata	0:f27ce43dee4f	2962	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2963	*val = reg.xlda;
cparata	0:f27ce43dee4f	2964
cparata	0:f27ce43dee4f	2965	return ret;
cparata	0:f27ce43dee4f	2966	}
cparata	0:f27ce43dee4f	2967
cparata	0:f27ce43dee4f	2968	/**
cparata	0:f27ce43dee4f	2969	* @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available.
cparata	0:f27ce43dee4f	2970	*
cparata	0:f27ce43dee4f	2971	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2972	* @param val change the values of gda in reg STATUS_SPIAUX
cparata	0:f27ce43dee4f	2973	*
cparata	0:f27ce43dee4f	2974	*/
cparata	0:f27ce43dee4f	2975	int32_t lsm6dsox_aux_gy_flag_data_ready_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2976	{
cparata	0:f27ce43dee4f	2977	lsm6dsox_spi2_status_reg_ois_t reg;
cparata	0:f27ce43dee4f	2978	int32_t ret;
cparata	0:f27ce43dee4f	2979
cparata	0:f27ce43dee4f	2980	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2981	*val = reg.gda;
cparata	0:f27ce43dee4f	2982
cparata	0:f27ce43dee4f	2983	return ret;
cparata	0:f27ce43dee4f	2984	}
cparata	0:f27ce43dee4f	2985
cparata	0:f27ce43dee4f	2986	/**
cparata	0:f27ce43dee4f	2987	* @brief High when the gyroscope output is in the settling phase.[get]
cparata	0:f27ce43dee4f	2988	*
cparata	0:f27ce43dee4f	2989	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	2990	* @param val change the values of gyro_settling in reg STATUS_SPIAUX
cparata	0:f27ce43dee4f	2991	*
cparata	0:f27ce43dee4f	2992	*/
cparata	0:f27ce43dee4f	2993	int32_t lsm6dsox_aux_gy_flag_settling_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	2994	{
cparata	0:f27ce43dee4f	2995	lsm6dsox_spi2_status_reg_ois_t reg;
cparata	0:f27ce43dee4f	2996	int32_t ret;
cparata	0:f27ce43dee4f	2997
cparata	0:f27ce43dee4f	2998	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	2999	*val = reg.gyro_settling;
cparata	0:f27ce43dee4f	3000
cparata	0:f27ce43dee4f	3001	return ret;
cparata	0:f27ce43dee4f	3002	}
cparata	0:f27ce43dee4f	3003
cparata	0:f27ce43dee4f	3004	/**
cparata	0:f27ce43dee4f	3005	* @brief Indicates polarity of DEN signal on OIS chain.[set]
cparata	0:f27ce43dee4f	3006	*
cparata	0:f27ce43dee4f	3007	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3008	* @param val change the values of den_lh_ois in
cparata	0:f27ce43dee4f	3009	* reg INT_OIS
cparata	0:f27ce43dee4f	3010	*
cparata	0:f27ce43dee4f	3011	*/
cparata	0:f27ce43dee4f	3012	int32_t lsm6dsox_aux_den_polarity_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3013	lsm6dsox_den_lh_ois_t val)
cparata	0:f27ce43dee4f	3014	{
cparata	0:f27ce43dee4f	3015	lsm6dsox_ui_int_ois_t reg;
cparata	0:f27ce43dee4f	3016	int32_t ret;
cparata	0:f27ce43dee4f	3017
cparata	0:f27ce43dee4f	3018	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3019	if (ret == 0) {
cparata	0:f27ce43dee4f	3020	reg.den_lh_ois = (uint8_t)val;
cparata	0:f27ce43dee4f	3021	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3022	}
cparata	0:f27ce43dee4f	3023	return ret;
cparata	0:f27ce43dee4f	3024	}
cparata	0:f27ce43dee4f	3025
cparata	0:f27ce43dee4f	3026	/**
cparata	0:f27ce43dee4f	3027	* @brief Indicates polarity of DEN signal on OIS chain.[get]
cparata	0:f27ce43dee4f	3028	*
cparata	0:f27ce43dee4f	3029	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3030	* @param val Get the values of den_lh_ois in reg INT_OIS
cparata	0:f27ce43dee4f	3031	*
cparata	0:f27ce43dee4f	3032	*/
cparata	0:f27ce43dee4f	3033	int32_t lsm6dsox_aux_den_polarity_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3034	lsm6dsox_den_lh_ois_t *val)
cparata	0:f27ce43dee4f	3035	{
cparata	0:f27ce43dee4f	3036	lsm6dsox_ui_int_ois_t reg;
cparata	0:f27ce43dee4f	3037	int32_t ret;
cparata	0:f27ce43dee4f	3038
cparata	0:f27ce43dee4f	3039	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3040	switch (reg.den_lh_ois) {
cparata	0:f27ce43dee4f	3041	case LSM6DSOX_AUX_DEN_ACTIVE_LOW:
cparata	0:f27ce43dee4f	3042	*val = LSM6DSOX_AUX_DEN_ACTIVE_LOW;
cparata	0:f27ce43dee4f	3043	break;
cparata	0:f27ce43dee4f	3044	case LSM6DSOX_AUX_DEN_ACTIVE_HIGH:
cparata	0:f27ce43dee4f	3045	*val = LSM6DSOX_AUX_DEN_ACTIVE_HIGH;
cparata	0:f27ce43dee4f	3046	break;
cparata	0:f27ce43dee4f	3047	default:
cparata	0:f27ce43dee4f	3048	*val = LSM6DSOX_AUX_DEN_ACTIVE_LOW;
cparata	0:f27ce43dee4f	3049	break;
cparata	0:f27ce43dee4f	3050	}
cparata	0:f27ce43dee4f	3051	return ret;
cparata	0:f27ce43dee4f	3052	}
cparata	0:f27ce43dee4f	3053
cparata	0:f27ce43dee4f	3054	/**
cparata	0:f27ce43dee4f	3055	* @brief Configure DEN mode on the OIS chain.[set]
cparata	0:f27ce43dee4f	3056	*
cparata	0:f27ce43dee4f	3057	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3058	* @param val change the values of lvl2_ois in reg INT_OIS
cparata	0:f27ce43dee4f	3059	*
cparata	0:f27ce43dee4f	3060	*/
cparata	0:f27ce43dee4f	3061	int32_t lsm6dsox_aux_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lvl2_ois_t val)
cparata	0:f27ce43dee4f	3062	{
cparata	0:f27ce43dee4f	3063	lsm6dsox_ui_ctrl1_ois_t ctrl1_ois;
cparata	0:f27ce43dee4f	3064	lsm6dsox_ui_int_ois_t int_ois;
cparata	0:f27ce43dee4f	3065	int32_t ret;
cparata	0:f27ce43dee4f	3066
cparata	0:f27ce43dee4f	3067	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	0:f27ce43dee4f	3068	if (ret == 0) {
cparata	0:f27ce43dee4f	3069	int_ois.lvl2_ois = (uint8_t)val & 0x01U;
cparata	0:f27ce43dee4f	3070	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	0:f27ce43dee4f	3071	}
cparata	0:f27ce43dee4f	3072	if (ret == 0) {
cparata	0:f27ce43dee4f	3073	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	0:f27ce43dee4f	3074	}
cparata	0:f27ce43dee4f	3075	if (ret == 0) {
cparata	0:f27ce43dee4f	3076	ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
cparata	0:f27ce43dee4f	3077	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	0:f27ce43dee4f	3078	}
cparata	0:f27ce43dee4f	3079	return ret;
cparata	0:f27ce43dee4f	3080	}
cparata	0:f27ce43dee4f	3081
cparata	0:f27ce43dee4f	3082	/**
cparata	0:f27ce43dee4f	3083	* @brief Configure DEN mode on the OIS chain.[get]
cparata	0:f27ce43dee4f	3084	*
cparata	0:f27ce43dee4f	3085	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3086	* @param val Get the values of lvl2_ois in reg INT_OIS
cparata	0:f27ce43dee4f	3087	*
cparata	0:f27ce43dee4f	3088	*/
cparata	0:f27ce43dee4f	3089	int32_t lsm6dsox_aux_den_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_lvl2_ois_t val)
cparata	0:f27ce43dee4f	3090	{
cparata	0:f27ce43dee4f	3091	lsm6dsox_ui_ctrl1_ois_t ctrl1_ois;
cparata	0:f27ce43dee4f	3092	lsm6dsox_ui_int_ois_t int_ois;
cparata	0:f27ce43dee4f	3093	int32_t ret;
cparata	0:f27ce43dee4f	3094
cparata	0:f27ce43dee4f	3095	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	0:f27ce43dee4f	3096	if (ret == 0) {
cparata	0:f27ce43dee4f	3097	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	0:f27ce43dee4f	3098	switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) {
cparata	0:f27ce43dee4f	3099	case LSM6DSOX_AUX_DEN_DISABLE:
cparata	0:f27ce43dee4f	3100	*val = LSM6DSOX_AUX_DEN_DISABLE;
cparata	0:f27ce43dee4f	3101	break;
cparata	0:f27ce43dee4f	3102	case LSM6DSOX_AUX_DEN_LEVEL_LATCH:
cparata	0:f27ce43dee4f	3103	*val = LSM6DSOX_AUX_DEN_LEVEL_LATCH;
cparata	0:f27ce43dee4f	3104	break;
cparata	0:f27ce43dee4f	3105	case LSM6DSOX_AUX_DEN_LEVEL_TRIG:
cparata	0:f27ce43dee4f	3106	*val = LSM6DSOX_AUX_DEN_LEVEL_TRIG;
cparata	0:f27ce43dee4f	3107	break;
cparata	0:f27ce43dee4f	3108	default:
cparata	0:f27ce43dee4f	3109	*val = LSM6DSOX_AUX_DEN_DISABLE;
cparata	0:f27ce43dee4f	3110	break;
cparata	0:f27ce43dee4f	3111	}
cparata	0:f27ce43dee4f	3112	}
cparata	0:f27ce43dee4f	3113	return ret;
cparata	0:f27ce43dee4f	3114	}
cparata	0:f27ce43dee4f	3115
cparata	0:f27ce43dee4f	3116	/**
cparata	0:f27ce43dee4f	3117	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:f27ce43dee4f	3118	* This setting has priority over all other INT2 settings.[set]
cparata	0:f27ce43dee4f	3119	*
cparata	0:f27ce43dee4f	3120	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3121	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:f27ce43dee4f	3122	*
cparata	0:f27ce43dee4f	3123	*/
cparata	0:f27ce43dee4f	3124	int32_t lsm6dsox_aux_drdy_on_int2_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	3125	{
cparata	0:f27ce43dee4f	3126	lsm6dsox_ui_int_ois_t reg;
cparata	0:f27ce43dee4f	3127	int32_t ret;
cparata	0:f27ce43dee4f	3128
cparata	0:f27ce43dee4f	3129	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3130	if (ret == 0) {
cparata	0:f27ce43dee4f	3131	reg.int2_drdy_ois = val;
cparata	0:f27ce43dee4f	3132	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3133	}
cparata	0:f27ce43dee4f	3134	return ret;
cparata	0:f27ce43dee4f	3135	}
cparata	0:f27ce43dee4f	3136
cparata	0:f27ce43dee4f	3137	/**
cparata	0:f27ce43dee4f	3138	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:f27ce43dee4f	3139	* This setting has priority over all other INT2 settings.[get]
cparata	0:f27ce43dee4f	3140	*
cparata	0:f27ce43dee4f	3141	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3142	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:f27ce43dee4f	3143	*
cparata	0:f27ce43dee4f	3144	*/
cparata	0:f27ce43dee4f	3145	int32_t lsm6dsox_aux_drdy_on_int2_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	3146	{
cparata	0:f27ce43dee4f	3147	lsm6dsox_ui_int_ois_t reg;
cparata	0:f27ce43dee4f	3148	int32_t ret;
cparata	0:f27ce43dee4f	3149
cparata	0:f27ce43dee4f	3150	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3151	*val = reg.int2_drdy_ois;
cparata	0:f27ce43dee4f	3152
cparata	0:f27ce43dee4f	3153	return ret;
cparata	0:f27ce43dee4f	3154	}
cparata	0:f27ce43dee4f	3155
cparata	0:f27ce43dee4f	3156	/**
cparata	0:f27ce43dee4f	3157	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:f27ce43dee4f	3158	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:f27ce43dee4f	3159	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:f27ce43dee4f	3160	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:f27ce43dee4f	3161	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:f27ce43dee4f	3162	* LPF1 is dedicated to this chain.[set]
cparata	0:f27ce43dee4f	3163	*
cparata	0:f27ce43dee4f	3164	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3165	* @param val change the values of ois_en_spi2 in
cparata	0:f27ce43dee4f	3166	* reg CTRL1_OIS
cparata	0:f27ce43dee4f	3167	*
cparata	0:f27ce43dee4f	3168	*/
cparata	0:f27ce43dee4f	3169	int32_t lsm6dsox_aux_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_en_spi2_t val)
cparata	0:f27ce43dee4f	3170	{
cparata	0:f27ce43dee4f	3171	lsm6dsox_ui_ctrl1_ois_t reg;
cparata	0:f27ce43dee4f	3172	int32_t ret;
cparata	0:f27ce43dee4f	3173
cparata	0:f27ce43dee4f	3174	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3175	if (ret == 0) {
cparata	0:f27ce43dee4f	3176	reg.ois_en_spi2 = (uint8_t)val & 0x01U;
cparata	0:f27ce43dee4f	3177	reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
cparata	0:f27ce43dee4f	3178	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3179	}
cparata	0:f27ce43dee4f	3180	return ret;
cparata	0:f27ce43dee4f	3181	}
cparata	0:f27ce43dee4f	3182
cparata	0:f27ce43dee4f	3183	/**
cparata	0:f27ce43dee4f	3184	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:f27ce43dee4f	3185	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:f27ce43dee4f	3186	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:f27ce43dee4f	3187	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:f27ce43dee4f	3188	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:f27ce43dee4f	3189	* LPF1 is dedicated to this chain.[get]
cparata	0:f27ce43dee4f	3190	*
cparata	0:f27ce43dee4f	3191	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3192	* @param val Get the values of ois_en_spi2 in
cparata	0:f27ce43dee4f	3193	* reg CTRL1_OIS
cparata	0:f27ce43dee4f	3194	*
cparata	0:f27ce43dee4f	3195	*/
cparata	0:f27ce43dee4f	3196	int32_t lsm6dsox_aux_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_ois_en_spi2_t val)
cparata	0:f27ce43dee4f	3197	{
cparata	0:f27ce43dee4f	3198	lsm6dsox_ui_ctrl1_ois_t reg;
cparata	0:f27ce43dee4f	3199	int32_t ret;
cparata	0:f27ce43dee4f	3200
cparata	0:f27ce43dee4f	3201	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3202	switch ((reg.mode4_en << 1) \| reg.ois_en_spi2) {
cparata	0:f27ce43dee4f	3203	case LSM6DSOX_AUX_DISABLE:
cparata	0:f27ce43dee4f	3204	*val = LSM6DSOX_AUX_DISABLE;
cparata	0:f27ce43dee4f	3205	break;
cparata	0:f27ce43dee4f	3206	case LSM6DSOX_MODE_3_GY:
cparata	0:f27ce43dee4f	3207	*val = LSM6DSOX_MODE_3_GY;
cparata	0:f27ce43dee4f	3208	break;
cparata	0:f27ce43dee4f	3209	case LSM6DSOX_MODE_4_GY_XL:
cparata	0:f27ce43dee4f	3210	*val = LSM6DSOX_MODE_4_GY_XL;
cparata	0:f27ce43dee4f	3211	break;
cparata	0:f27ce43dee4f	3212	default:
cparata	0:f27ce43dee4f	3213	*val = LSM6DSOX_AUX_DISABLE;
cparata	0:f27ce43dee4f	3214	break;
cparata	0:f27ce43dee4f	3215	}
cparata	0:f27ce43dee4f	3216	return ret;
cparata	0:f27ce43dee4f	3217	}
cparata	0:f27ce43dee4f	3218
cparata	0:f27ce43dee4f	3219	/**
cparata	0:f27ce43dee4f	3220	* @brief Selects gyroscope OIS chain full-scale.[set]
cparata	0:f27ce43dee4f	3221	*
cparata	0:f27ce43dee4f	3222	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3223	* @param val change the values of fs_g_ois in reg CTRL1_OIS
cparata	0:f27ce43dee4f	3224	*
cparata	0:f27ce43dee4f	3225	*/
cparata	0:f27ce43dee4f	3226	int32_t lsm6dsox_aux_gy_full_scale_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3227	lsm6dsox_fs_g_ois_t val)
cparata	0:f27ce43dee4f	3228	{
cparata	0:f27ce43dee4f	3229	lsm6dsox_ui_ctrl1_ois_t reg;
cparata	0:f27ce43dee4f	3230	int32_t ret;
cparata	0:f27ce43dee4f	3231
cparata	0:f27ce43dee4f	3232	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3233	if (ret == 0) {
cparata	0:f27ce43dee4f	3234	reg.fs_g_ois = (uint8_t)val;
cparata	0:f27ce43dee4f	3235	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3236	}
cparata	0:f27ce43dee4f	3237	return ret;
cparata	0:f27ce43dee4f	3238	}
cparata	0:f27ce43dee4f	3239
cparata	0:f27ce43dee4f	3240	/**
cparata	0:f27ce43dee4f	3241	* @brief Selects gyroscope OIS chain full-scale.[get]
cparata	0:f27ce43dee4f	3242	*
cparata	0:f27ce43dee4f	3243	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3244	* @param val Get the values of fs_g_ois in reg CTRL1_OIS
cparata	0:f27ce43dee4f	3245	*
cparata	0:f27ce43dee4f	3246	*/
cparata	0:f27ce43dee4f	3247	int32_t lsm6dsox_aux_gy_full_scale_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3248	lsm6dsox_fs_g_ois_t *val)
cparata	0:f27ce43dee4f	3249	{
cparata	0:f27ce43dee4f	3250	lsm6dsox_ui_ctrl1_ois_t reg;
cparata	0:f27ce43dee4f	3251	int32_t ret;
cparata	0:f27ce43dee4f	3252
cparata	0:f27ce43dee4f	3253	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3254	switch (reg.fs_g_ois) {
cparata	0:f27ce43dee4f	3255	case LSM6DSOX_250dps_AUX:
cparata	0:f27ce43dee4f	3256	*val = LSM6DSOX_250dps_AUX;
cparata	0:f27ce43dee4f	3257	break;
cparata	0:f27ce43dee4f	3258	case LSM6DSOX_125dps_AUX:
cparata	0:f27ce43dee4f	3259	*val = LSM6DSOX_125dps_AUX;
cparata	0:f27ce43dee4f	3260	break;
cparata	0:f27ce43dee4f	3261	case LSM6DSOX_500dps_AUX:
cparata	0:f27ce43dee4f	3262	*val = LSM6DSOX_500dps_AUX;
cparata	0:f27ce43dee4f	3263	break;
cparata	0:f27ce43dee4f	3264	case LSM6DSOX_1000dps_AUX:
cparata	0:f27ce43dee4f	3265	*val = LSM6DSOX_1000dps_AUX;
cparata	0:f27ce43dee4f	3266	break;
cparata	0:f27ce43dee4f	3267	case LSM6DSOX_2000dps_AUX:
cparata	0:f27ce43dee4f	3268	*val = LSM6DSOX_2000dps_AUX;
cparata	0:f27ce43dee4f	3269	break;
cparata	0:f27ce43dee4f	3270	default:
cparata	0:f27ce43dee4f	3271	*val = LSM6DSOX_250dps_AUX;
cparata	0:f27ce43dee4f	3272	break;
cparata	0:f27ce43dee4f	3273	}
cparata	0:f27ce43dee4f	3274	return ret;
cparata	0:f27ce43dee4f	3275	}
cparata	0:f27ce43dee4f	3276
cparata	0:f27ce43dee4f	3277	/**
cparata	0:f27ce43dee4f	3278	* @brief SPI2 3- or 4-wire interface.[set]
cparata	0:f27ce43dee4f	3279	*
cparata	0:f27ce43dee4f	3280	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3281	* @param val change the values of sim_ois in reg CTRL1_OIS
cparata	0:f27ce43dee4f	3282	*
cparata	0:f27ce43dee4f	3283	*/
cparata	0:f27ce43dee4f	3284	int32_t lsm6dsox_aux_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_ois_t val)
cparata	0:f27ce43dee4f	3285	{
cparata	0:f27ce43dee4f	3286	lsm6dsox_ui_ctrl1_ois_t reg;
cparata	0:f27ce43dee4f	3287	int32_t ret;
cparata	0:f27ce43dee4f	3288
cparata	0:f27ce43dee4f	3289	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3290	if (ret == 0) {
cparata	0:f27ce43dee4f	3291	reg.sim_ois = (uint8_t)val;
cparata	0:f27ce43dee4f	3292	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3293	}
cparata	0:f27ce43dee4f	3294	return ret;
cparata	0:f27ce43dee4f	3295	}
cparata	0:f27ce43dee4f	3296
cparata	0:f27ce43dee4f	3297	/**
cparata	0:f27ce43dee4f	3298	* @brief SPI2 3- or 4-wire interface.[get]
cparata	0:f27ce43dee4f	3299	*
cparata	0:f27ce43dee4f	3300	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3301	* @param val Get the values of sim_ois in reg CTRL1_OIS
cparata	0:f27ce43dee4f	3302	*
cparata	0:f27ce43dee4f	3303	*/
cparata	0:f27ce43dee4f	3304	int32_t lsm6dsox_aux_spi_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_sim_ois_t val)
cparata	0:f27ce43dee4f	3305	{
cparata	0:f27ce43dee4f	3306	lsm6dsox_ui_ctrl1_ois_t reg;
cparata	0:f27ce43dee4f	3307	int32_t ret;
cparata	0:f27ce43dee4f	3308
cparata	0:f27ce43dee4f	3309	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3310	switch (reg.sim_ois) {
cparata	0:f27ce43dee4f	3311	case LSM6DSOX_AUX_SPI_4_WIRE:
cparata	0:f27ce43dee4f	3312	*val = LSM6DSOX_AUX_SPI_4_WIRE;
cparata	0:f27ce43dee4f	3313	break;
cparata	0:f27ce43dee4f	3314	case LSM6DSOX_AUX_SPI_3_WIRE:
cparata	0:f27ce43dee4f	3315	*val = LSM6DSOX_AUX_SPI_3_WIRE;
cparata	0:f27ce43dee4f	3316	break;
cparata	0:f27ce43dee4f	3317	default:
cparata	0:f27ce43dee4f	3318	*val = LSM6DSOX_AUX_SPI_4_WIRE;
cparata	0:f27ce43dee4f	3319	break;
cparata	0:f27ce43dee4f	3320	}
cparata	0:f27ce43dee4f	3321	return ret;
cparata	0:f27ce43dee4f	3322	}
cparata	0:f27ce43dee4f	3323
cparata	0:f27ce43dee4f	3324	/**
cparata	0:f27ce43dee4f	3325	* @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
cparata	0:f27ce43dee4f	3326	*
cparata	0:f27ce43dee4f	3327	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3328	* @param val change the values of ftype_ois in
cparata	0:f27ce43dee4f	3329	* reg CTRL2_OIS
cparata	0:f27ce43dee4f	3330	*
cparata	0:f27ce43dee4f	3331	*/
cparata	0:f27ce43dee4f	3332	int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3333	lsm6dsox_ftype_ois_t val)
cparata	0:f27ce43dee4f	3334	{
cparata	0:f27ce43dee4f	3335	lsm6dsox_ui_ctrl2_ois_t reg;
cparata	0:f27ce43dee4f	3336	int32_t ret;
cparata	0:f27ce43dee4f	3337
cparata	0:f27ce43dee4f	3338	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3339	if (ret == 0) {
cparata	0:f27ce43dee4f	3340	reg.ftype_ois = (uint8_t)val;
cparata	0:f27ce43dee4f	3341	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3342	}
cparata	0:f27ce43dee4f	3343	return ret;
cparata	0:f27ce43dee4f	3344	}
cparata	0:f27ce43dee4f	3345
cparata	0:f27ce43dee4f	3346	/**
cparata	0:f27ce43dee4f	3347	* @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
cparata	0:f27ce43dee4f	3348	*
cparata	0:f27ce43dee4f	3349	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3350	* @param val Get the values of ftype_ois in reg CTRL2_OIS
cparata	0:f27ce43dee4f	3351	*
cparata	0:f27ce43dee4f	3352	*/
cparata	0:f27ce43dee4f	3353	int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3354	lsm6dsox_ftype_ois_t *val)
cparata	0:f27ce43dee4f	3355	{
cparata	0:f27ce43dee4f	3356	lsm6dsox_ui_ctrl2_ois_t reg;
cparata	0:f27ce43dee4f	3357	int32_t ret;
cparata	0:f27ce43dee4f	3358
cparata	0:f27ce43dee4f	3359	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3360	switch (reg.ftype_ois) {
cparata	0:f27ce43dee4f	3361	case LSM6DSOX_351Hz39:
cparata	0:f27ce43dee4f	3362	*val = LSM6DSOX_351Hz39;
cparata	0:f27ce43dee4f	3363	break;
cparata	0:f27ce43dee4f	3364	case LSM6DSOX_236Hz63:
cparata	0:f27ce43dee4f	3365	*val = LSM6DSOX_236Hz63;
cparata	0:f27ce43dee4f	3366	break;
cparata	0:f27ce43dee4f	3367	case LSM6DSOX_172Hz70:
cparata	0:f27ce43dee4f	3368	*val = LSM6DSOX_172Hz70;
cparata	0:f27ce43dee4f	3369	break;
cparata	0:f27ce43dee4f	3370	case LSM6DSOX_937Hz91:
cparata	0:f27ce43dee4f	3371	*val = LSM6DSOX_937Hz91;
cparata	0:f27ce43dee4f	3372	break;
cparata	0:f27ce43dee4f	3373	default:
cparata	0:f27ce43dee4f	3374	*val = LSM6DSOX_351Hz39;
cparata	0:f27ce43dee4f	3375	break;
cparata	0:f27ce43dee4f	3376	}
cparata	0:f27ce43dee4f	3377	return ret;
cparata	0:f27ce43dee4f	3378	}
cparata	0:f27ce43dee4f	3379
cparata	0:f27ce43dee4f	3380	/**
cparata	0:f27ce43dee4f	3381	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
cparata	0:f27ce43dee4f	3382	*
cparata	0:f27ce43dee4f	3383	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3384	* @param val change the values of hpm_ois in reg CTRL2_OIS
cparata	0:f27ce43dee4f	3385	*
cparata	0:f27ce43dee4f	3386	*/
cparata	0:f27ce43dee4f	3387	int32_t lsm6dsox_aux_gy_hp_bandwidth_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3388	lsm6dsox_hpm_ois_t val)
cparata	0:f27ce43dee4f	3389	{
cparata	0:f27ce43dee4f	3390	lsm6dsox_ui_ctrl2_ois_t reg;
cparata	0:f27ce43dee4f	3391	int32_t ret;
cparata	0:f27ce43dee4f	3392
cparata	0:f27ce43dee4f	3393	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3394	if (ret == 0) {
cparata	0:f27ce43dee4f	3395	reg.hpm_ois = (uint8_t)val & 0x03U;
cparata	0:f27ce43dee4f	3396	reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
cparata	0:f27ce43dee4f	3397	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3398	}
cparata	0:f27ce43dee4f	3399	return ret;
cparata	0:f27ce43dee4f	3400	}
cparata	0:f27ce43dee4f	3401
cparata	0:f27ce43dee4f	3402	/**
cparata	0:f27ce43dee4f	3403	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
cparata	0:f27ce43dee4f	3404	*
cparata	0:f27ce43dee4f	3405	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3406	* @param val Get the values of hpm_ois in reg CTRL2_OIS
cparata	0:f27ce43dee4f	3407	*
cparata	0:f27ce43dee4f	3408	*/
cparata	0:f27ce43dee4f	3409	int32_t lsm6dsox_aux_gy_hp_bandwidth_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3410	lsm6dsox_hpm_ois_t *val)
cparata	0:f27ce43dee4f	3411	{
cparata	0:f27ce43dee4f	3412	lsm6dsox_ui_ctrl2_ois_t reg;
cparata	0:f27ce43dee4f	3413	int32_t ret;
cparata	0:f27ce43dee4f	3414
cparata	0:f27ce43dee4f	3415	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3416	switch ((reg.hp_en_ois << 4) \| reg.hpm_ois) {
cparata	0:f27ce43dee4f	3417	case LSM6DSOX_AUX_HP_DISABLE:
cparata	0:f27ce43dee4f	3418	*val = LSM6DSOX_AUX_HP_DISABLE;
cparata	0:f27ce43dee4f	3419	break;
cparata	0:f27ce43dee4f	3420	case LSM6DSOX_AUX_HP_Hz016:
cparata	0:f27ce43dee4f	3421	*val = LSM6DSOX_AUX_HP_Hz016;
cparata	0:f27ce43dee4f	3422	break;
cparata	0:f27ce43dee4f	3423	case LSM6DSOX_AUX_HP_Hz065:
cparata	0:f27ce43dee4f	3424	*val = LSM6DSOX_AUX_HP_Hz065;
cparata	0:f27ce43dee4f	3425	break;
cparata	0:f27ce43dee4f	3426	case LSM6DSOX_AUX_HP_Hz260:
cparata	0:f27ce43dee4f	3427	*val = LSM6DSOX_AUX_HP_Hz260;
cparata	0:f27ce43dee4f	3428	break;
cparata	0:f27ce43dee4f	3429	case LSM6DSOX_AUX_HP_1Hz040:
cparata	0:f27ce43dee4f	3430	*val = LSM6DSOX_AUX_HP_1Hz040;
cparata	0:f27ce43dee4f	3431	break;
cparata	0:f27ce43dee4f	3432	default:
cparata	0:f27ce43dee4f	3433	*val = LSM6DSOX_AUX_HP_DISABLE;
cparata	0:f27ce43dee4f	3434	break;
cparata	0:f27ce43dee4f	3435	}
cparata	0:f27ce43dee4f	3436	return ret;
cparata	0:f27ce43dee4f	3437	}
cparata	0:f27ce43dee4f	3438
cparata	0:f27ce43dee4f	3439	/**
cparata	0:f27ce43dee4f	3440	* @brief Enable / Disables OIS chain clamp.
cparata	0:f27ce43dee4f	3441	* Enable: All OIS chain outputs = 8000h
cparata	0:f27ce43dee4f	3442	* during self-test; Disable: OIS chain self-test
cparata	0:f27ce43dee4f	3443	* outputs dependent from the aux gyro full
cparata	0:f27ce43dee4f	3444	* scale selected.[set]
cparata	0:f27ce43dee4f	3445	*
cparata	0:f27ce43dee4f	3446	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3447	* @param val change the values of st_ois_clampdis in
cparata	0:f27ce43dee4f	3448	* reg CTRL3_OIS
cparata	0:f27ce43dee4f	3449	*
cparata	0:f27ce43dee4f	3450	*/
cparata	0:f27ce43dee4f	3451	int32_t lsm6dsox_aux_gy_clamp_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3452	lsm6dsox_st_ois_clampdis_t val)
cparata	0:f27ce43dee4f	3453	{
cparata	0:f27ce43dee4f	3454	lsm6dsox_ui_ctrl3_ois_t reg;
cparata	0:f27ce43dee4f	3455	int32_t ret;
cparata	0:f27ce43dee4f	3456
cparata	0:f27ce43dee4f	3457	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3458	if (ret == 0) {
cparata	0:f27ce43dee4f	3459	reg.st_ois_clampdis = (uint8_t)val;
cparata	0:f27ce43dee4f	3460	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3461	}
cparata	0:f27ce43dee4f	3462	return ret;
cparata	0:f27ce43dee4f	3463	}
cparata	0:f27ce43dee4f	3464
cparata	0:f27ce43dee4f	3465	/**
cparata	0:f27ce43dee4f	3466	* @brief Enable / Disables OIS chain clamp.
cparata	0:f27ce43dee4f	3467	* Enable: All OIS chain outputs = 8000h
cparata	0:f27ce43dee4f	3468	* during self-test; Disable: OIS chain self-test
cparata	0:f27ce43dee4f	3469	* outputs dependent from the aux gyro full
cparata	0:f27ce43dee4f	3470	* scale selected.[set]
cparata	0:f27ce43dee4f	3471	*
cparata	0:f27ce43dee4f	3472	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3473	* @param val Get the values of st_ois_clampdis in
cparata	0:f27ce43dee4f	3474	* reg CTRL3_OIS
cparata	0:f27ce43dee4f	3475	*
cparata	0:f27ce43dee4f	3476	*/
cparata	0:f27ce43dee4f	3477	int32_t lsm6dsox_aux_gy_clamp_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3478	lsm6dsox_st_ois_clampdis_t *val)
cparata	0:f27ce43dee4f	3479	{
cparata	0:f27ce43dee4f	3480	lsm6dsox_ui_ctrl3_ois_t reg;
cparata	0:f27ce43dee4f	3481	int32_t ret;
cparata	0:f27ce43dee4f	3482
cparata	0:f27ce43dee4f	3483	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3484	switch (reg.st_ois_clampdis) {
cparata	0:f27ce43dee4f	3485	case LSM6DSOX_ENABLE_CLAMP:
cparata	0:f27ce43dee4f	3486	*val = LSM6DSOX_ENABLE_CLAMP;
cparata	0:f27ce43dee4f	3487	break;
cparata	0:f27ce43dee4f	3488	case LSM6DSOX_DISABLE_CLAMP:
cparata	0:f27ce43dee4f	3489	*val = LSM6DSOX_DISABLE_CLAMP;
cparata	0:f27ce43dee4f	3490	break;
cparata	0:f27ce43dee4f	3491	default:
cparata	0:f27ce43dee4f	3492	*val = LSM6DSOX_ENABLE_CLAMP;
cparata	0:f27ce43dee4f	3493	break;
cparata	0:f27ce43dee4f	3494	}
cparata	0:f27ce43dee4f	3495	return ret;
cparata	0:f27ce43dee4f	3496	}
cparata	0:f27ce43dee4f	3497
cparata	0:f27ce43dee4f	3498	/**
cparata	0:f27ce43dee4f	3499	* @brief Selects accelerometer OIS channel bandwidth.[set]
cparata	0:f27ce43dee4f	3500	*
cparata	0:f27ce43dee4f	3501	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3502	* @param val change the values of
cparata	0:f27ce43dee4f	3503	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:f27ce43dee4f	3504	*
cparata	0:f27ce43dee4f	3505	*/
cparata	0:f27ce43dee4f	3506	int32_t lsm6dsox_aux_xl_bandwidth_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3507	lsm6dsox_filter_xl_conf_ois_t val)
cparata	0:f27ce43dee4f	3508	{
cparata	0:f27ce43dee4f	3509	lsm6dsox_ui_ctrl3_ois_t reg;
cparata	0:f27ce43dee4f	3510	int32_t ret;
cparata	0:f27ce43dee4f	3511
cparata	0:f27ce43dee4f	3512	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3513	if (ret == 0) {
cparata	0:f27ce43dee4f	3514	reg.filter_xl_conf_ois = (uint8_t)val;
cparata	0:f27ce43dee4f	3515	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3516	}
cparata	0:f27ce43dee4f	3517	return ret;
cparata	0:f27ce43dee4f	3518	}
cparata	0:f27ce43dee4f	3519
cparata	0:f27ce43dee4f	3520	/**
cparata	0:f27ce43dee4f	3521	* @brief Selects accelerometer OIS channel bandwidth.[get]
cparata	0:f27ce43dee4f	3522	*
cparata	0:f27ce43dee4f	3523	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3524	* @param val Get the values of
cparata	0:f27ce43dee4f	3525	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:f27ce43dee4f	3526	*
cparata	0:f27ce43dee4f	3527	*/
cparata	0:f27ce43dee4f	3528	int32_t lsm6dsox_aux_xl_bandwidth_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3529	lsm6dsox_filter_xl_conf_ois_t *val)
cparata	0:f27ce43dee4f	3530	{
cparata	0:f27ce43dee4f	3531	lsm6dsox_ui_ctrl3_ois_t reg;
cparata	0:f27ce43dee4f	3532	int32_t ret;
cparata	0:f27ce43dee4f	3533
cparata	0:f27ce43dee4f	3534	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3535
cparata	0:f27ce43dee4f	3536	switch (reg.filter_xl_conf_ois) {
cparata	0:f27ce43dee4f	3537	case LSM6DSOX_289Hz:
cparata	0:f27ce43dee4f	3538	*val = LSM6DSOX_289Hz;
cparata	0:f27ce43dee4f	3539	break;
cparata	0:f27ce43dee4f	3540	case LSM6DSOX_258Hz:
cparata	0:f27ce43dee4f	3541	*val = LSM6DSOX_258Hz;
cparata	0:f27ce43dee4f	3542	break;
cparata	0:f27ce43dee4f	3543	case LSM6DSOX_120Hz:
cparata	0:f27ce43dee4f	3544	*val = LSM6DSOX_120Hz;
cparata	0:f27ce43dee4f	3545	break;
cparata	0:f27ce43dee4f	3546	case LSM6DSOX_65Hz2:
cparata	0:f27ce43dee4f	3547	*val = LSM6DSOX_65Hz2;
cparata	0:f27ce43dee4f	3548	break;
cparata	0:f27ce43dee4f	3549	case LSM6DSOX_33Hz2:
cparata	0:f27ce43dee4f	3550	*val = LSM6DSOX_33Hz2;
cparata	0:f27ce43dee4f	3551	break;
cparata	0:f27ce43dee4f	3552	case LSM6DSOX_16Hz6:
cparata	0:f27ce43dee4f	3553	*val = LSM6DSOX_16Hz6;
cparata	0:f27ce43dee4f	3554	break;
cparata	0:f27ce43dee4f	3555	case LSM6DSOX_8Hz30:
cparata	0:f27ce43dee4f	3556	*val = LSM6DSOX_8Hz30;
cparata	0:f27ce43dee4f	3557	break;
cparata	0:f27ce43dee4f	3558	case LSM6DSOX_4Hz15:
cparata	0:f27ce43dee4f	3559	*val = LSM6DSOX_4Hz15;
cparata	0:f27ce43dee4f	3560	break;
cparata	0:f27ce43dee4f	3561	default:
cparata	0:f27ce43dee4f	3562	*val = LSM6DSOX_289Hz;
cparata	0:f27ce43dee4f	3563	break;
cparata	0:f27ce43dee4f	3564	}
cparata	0:f27ce43dee4f	3565	return ret;
cparata	0:f27ce43dee4f	3566	}
cparata	0:f27ce43dee4f	3567
cparata	0:f27ce43dee4f	3568	/**
cparata	0:f27ce43dee4f	3569	* @brief Selects accelerometer OIS channel full-scale.[set]
cparata	0:f27ce43dee4f	3570	*
cparata	0:f27ce43dee4f	3571	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3572	* @param val change the values of fs_xl_ois in
cparata	0:f27ce43dee4f	3573	* reg CTRL3_OIS
cparata	0:f27ce43dee4f	3574	*
cparata	0:f27ce43dee4f	3575	*/
cparata	0:f27ce43dee4f	3576	int32_t lsm6dsox_aux_xl_full_scale_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3577	lsm6dsox_fs_xl_ois_t val)
cparata	0:f27ce43dee4f	3578	{
cparata	0:f27ce43dee4f	3579	lsm6dsox_ui_ctrl3_ois_t reg;
cparata	0:f27ce43dee4f	3580	int32_t ret;
cparata	0:f27ce43dee4f	3581
cparata	0:f27ce43dee4f	3582	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3583	if (ret == 0) {
cparata	0:f27ce43dee4f	3584	reg.fs_xl_ois = (uint8_t)val;
cparata	0:f27ce43dee4f	3585	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3586	}
cparata	0:f27ce43dee4f	3587	return ret;
cparata	0:f27ce43dee4f	3588	}
cparata	0:f27ce43dee4f	3589
cparata	0:f27ce43dee4f	3590	/**
cparata	0:f27ce43dee4f	3591	* @brief Selects accelerometer OIS channel full-scale.[get]
cparata	0:f27ce43dee4f	3592	*
cparata	0:f27ce43dee4f	3593	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3594	* @param val Get the values of fs_xl_ois in reg CTRL3_OIS
cparata	0:f27ce43dee4f	3595	*
cparata	0:f27ce43dee4f	3596	*/
cparata	0:f27ce43dee4f	3597	int32_t lsm6dsox_aux_xl_full_scale_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3598	lsm6dsox_fs_xl_ois_t *val)
cparata	0:f27ce43dee4f	3599	{
cparata	0:f27ce43dee4f	3600	lsm6dsox_ui_ctrl3_ois_t reg;
cparata	0:f27ce43dee4f	3601	int32_t ret;
cparata	0:f27ce43dee4f	3602
cparata	0:f27ce43dee4f	3603	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3604	switch (reg.fs_xl_ois) {
cparata	0:f27ce43dee4f	3605	case LSM6DSOX_AUX_2g:
cparata	0:f27ce43dee4f	3606	*val = LSM6DSOX_AUX_2g;
cparata	0:f27ce43dee4f	3607	break;
cparata	0:f27ce43dee4f	3608	case LSM6DSOX_AUX_16g:
cparata	0:f27ce43dee4f	3609	*val = LSM6DSOX_AUX_16g;
cparata	0:f27ce43dee4f	3610	break;
cparata	0:f27ce43dee4f	3611	case LSM6DSOX_AUX_4g:
cparata	0:f27ce43dee4f	3612	*val = LSM6DSOX_AUX_4g;
cparata	0:f27ce43dee4f	3613	break;
cparata	0:f27ce43dee4f	3614	case LSM6DSOX_AUX_8g:
cparata	0:f27ce43dee4f	3615	*val = LSM6DSOX_AUX_8g;
cparata	0:f27ce43dee4f	3616	break;
cparata	0:f27ce43dee4f	3617	default:
cparata	0:f27ce43dee4f	3618	*val = LSM6DSOX_AUX_2g;
cparata	0:f27ce43dee4f	3619	break;
cparata	0:f27ce43dee4f	3620	}
cparata	0:f27ce43dee4f	3621	return ret;
cparata	0:f27ce43dee4f	3622	}
cparata	0:f27ce43dee4f	3623
cparata	0:f27ce43dee4f	3624	/**
cparata	0:f27ce43dee4f	3625	* @}
cparata	0:f27ce43dee4f	3626	*
cparata	0:f27ce43dee4f	3627	*/
cparata	0:f27ce43dee4f	3628
cparata	0:f27ce43dee4f	3629	/**
cparata	0:f27ce43dee4f	3630	* @defgroup LSM6DSOX_ main_serial_interface
cparata	0:f27ce43dee4f	3631	* @brief This section groups all the functions concerning main
cparata	0:f27ce43dee4f	3632	* serial interface management (not auxiliary)
cparata	0:f27ce43dee4f	3633	* @{
cparata	0:f27ce43dee4f	3634	*
cparata	0:f27ce43dee4f	3635	*/
cparata	0:f27ce43dee4f	3636
cparata	0:f27ce43dee4f	3637	/**
cparata	0:f27ce43dee4f	3638	* @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
cparata	0:f27ce43dee4f	3639	*
cparata	0:f27ce43dee4f	3640	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3641	* @param val change the values of sdo_pu_en in
cparata	0:f27ce43dee4f	3642	* reg PIN_CTRL
cparata	0:f27ce43dee4f	3643	*
cparata	0:f27ce43dee4f	3644	*/
cparata	0:f27ce43dee4f	3645	int32_t lsm6dsox_sdo_sa0_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sdo_pu_en_t val)
cparata	0:f27ce43dee4f	3646	{
cparata	0:f27ce43dee4f	3647	lsm6dsox_pin_ctrl_t reg;
cparata	0:f27ce43dee4f	3648	int32_t ret;
cparata	0:f27ce43dee4f	3649
cparata	0:f27ce43dee4f	3650	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3651	if (ret == 0) {
cparata	0:f27ce43dee4f	3652	reg.sdo_pu_en = (uint8_t)val;
cparata	0:f27ce43dee4f	3653	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3654	}
cparata	0:f27ce43dee4f	3655	return ret;
cparata	0:f27ce43dee4f	3656	}
cparata	0:f27ce43dee4f	3657
cparata	0:f27ce43dee4f	3658	/**
cparata	0:f27ce43dee4f	3659	* @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
cparata	0:f27ce43dee4f	3660	*
cparata	0:f27ce43dee4f	3661	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3662	* @param val Get the values of sdo_pu_en in reg PIN_CTRL
cparata	0:f27ce43dee4f	3663	*
cparata	0:f27ce43dee4f	3664	*/
cparata	0:f27ce43dee4f	3665	int32_t lsm6dsox_sdo_sa0_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_sdo_pu_en_t val)
cparata	0:f27ce43dee4f	3666	{
cparata	0:f27ce43dee4f	3667	lsm6dsox_pin_ctrl_t reg;
cparata	0:f27ce43dee4f	3668	int32_t ret;
cparata	0:f27ce43dee4f	3669
cparata	0:f27ce43dee4f	3670	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3671	switch (reg.sdo_pu_en) {
cparata	0:f27ce43dee4f	3672	case LSM6DSOX_PULL_UP_DISC:
cparata	0:f27ce43dee4f	3673	*val = LSM6DSOX_PULL_UP_DISC;
cparata	0:f27ce43dee4f	3674	break;
cparata	0:f27ce43dee4f	3675	case LSM6DSOX_PULL_UP_CONNECT:
cparata	0:f27ce43dee4f	3676	*val = LSM6DSOX_PULL_UP_CONNECT;
cparata	0:f27ce43dee4f	3677	break;
cparata	0:f27ce43dee4f	3678	default:
cparata	0:f27ce43dee4f	3679	*val = LSM6DSOX_PULL_UP_DISC;
cparata	0:f27ce43dee4f	3680	break;
cparata	0:f27ce43dee4f	3681	}
cparata	0:f27ce43dee4f	3682	return ret;
cparata	0:f27ce43dee4f	3683	}
cparata	0:f27ce43dee4f	3684
cparata	0:f27ce43dee4f	3685	/**
cparata	0:f27ce43dee4f	3686	* @brief SPI Serial Interface Mode selection.[set]
cparata	0:f27ce43dee4f	3687	*
cparata	0:f27ce43dee4f	3688	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3689	* @param val change the values of sim in reg CTRL3_C
cparata	0:f27ce43dee4f	3690	*
cparata	0:f27ce43dee4f	3691	*/
cparata	0:f27ce43dee4f	3692	int32_t lsm6dsox_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t val)
cparata	0:f27ce43dee4f	3693	{
cparata	0:f27ce43dee4f	3694	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	3695	int32_t ret;
cparata	0:f27ce43dee4f	3696
cparata	0:f27ce43dee4f	3697	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3698	if (ret == 0) {
cparata	0:f27ce43dee4f	3699	reg.sim = (uint8_t)val;
cparata	0:f27ce43dee4f	3700	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3701	}
cparata	0:f27ce43dee4f	3702	return ret;
cparata	0:f27ce43dee4f	3703	}
cparata	0:f27ce43dee4f	3704
cparata	0:f27ce43dee4f	3705	/**
cparata	0:f27ce43dee4f	3706	* @brief SPI Serial Interface Mode selection.[get]
cparata	0:f27ce43dee4f	3707	*
cparata	0:f27ce43dee4f	3708	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3709	* @param val Get the values of sim in reg CTRL3_C
cparata	0:f27ce43dee4f	3710	*
cparata	0:f27ce43dee4f	3711	*/
cparata	0:f27ce43dee4f	3712	int32_t lsm6dsox_spi_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_sim_t val)
cparata	0:f27ce43dee4f	3713	{
cparata	0:f27ce43dee4f	3714	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	3715	int32_t ret;
cparata	0:f27ce43dee4f	3716
cparata	0:f27ce43dee4f	3717	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3718	switch (reg.sim) {
cparata	0:f27ce43dee4f	3719	case LSM6DSOX_SPI_4_WIRE:
cparata	0:f27ce43dee4f	3720	*val = LSM6DSOX_SPI_4_WIRE;
cparata	0:f27ce43dee4f	3721	break;
cparata	0:f27ce43dee4f	3722	case LSM6DSOX_SPI_3_WIRE:
cparata	0:f27ce43dee4f	3723	*val = LSM6DSOX_SPI_3_WIRE;
cparata	0:f27ce43dee4f	3724	break;
cparata	0:f27ce43dee4f	3725	default:
cparata	0:f27ce43dee4f	3726	*val = LSM6DSOX_SPI_4_WIRE;
cparata	0:f27ce43dee4f	3727	break;
cparata	0:f27ce43dee4f	3728	}
cparata	0:f27ce43dee4f	3729	return ret;
cparata	0:f27ce43dee4f	3730	}
cparata	0:f27ce43dee4f	3731
cparata	0:f27ce43dee4f	3732	/**
cparata	0:f27ce43dee4f	3733	* @brief Disable / Enable I2C interface.[set]
cparata	0:f27ce43dee4f	3734	*
cparata	0:f27ce43dee4f	3735	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3736	* @param val change the values of i2c_disable in
cparata	0:f27ce43dee4f	3737	* reg CTRL4_C
cparata	0:f27ce43dee4f	3738	*
cparata	0:f27ce43dee4f	3739	*/
cparata	0:f27ce43dee4f	3740	int32_t lsm6dsox_i2c_interface_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3741	lsm6dsox_i2c_disable_t val)
cparata	0:f27ce43dee4f	3742	{
cparata	0:f27ce43dee4f	3743	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	3744	int32_t ret;
cparata	0:f27ce43dee4f	3745
cparata	0:f27ce43dee4f	3746	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3747	if (ret == 0) {
cparata	0:f27ce43dee4f	3748	reg.i2c_disable = (uint8_t)val;
cparata	0:f27ce43dee4f	3749	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3750	}
cparata	0:f27ce43dee4f	3751	return ret;
cparata	0:f27ce43dee4f	3752	}
cparata	0:f27ce43dee4f	3753
cparata	0:f27ce43dee4f	3754	/**
cparata	0:f27ce43dee4f	3755	* @brief Disable / Enable I2C interface.[get]
cparata	0:f27ce43dee4f	3756	*
cparata	0:f27ce43dee4f	3757	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3758	* @param val Get the values of i2c_disable in
cparata	0:f27ce43dee4f	3759	* reg CTRL4_C
cparata	0:f27ce43dee4f	3760	*
cparata	0:f27ce43dee4f	3761	*/
cparata	0:f27ce43dee4f	3762	int32_t lsm6dsox_i2c_interface_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	3763	lsm6dsox_i2c_disable_t *val)
cparata	0:f27ce43dee4f	3764	{
cparata	0:f27ce43dee4f	3765	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	3766	int32_t ret;
cparata	0:f27ce43dee4f	3767
cparata	0:f27ce43dee4f	3768	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3769	switch (reg.i2c_disable) {
cparata	0:f27ce43dee4f	3770	case LSM6DSOX_I2C_ENABLE:
cparata	0:f27ce43dee4f	3771	*val = LSM6DSOX_I2C_ENABLE;
cparata	0:f27ce43dee4f	3772	break;
cparata	0:f27ce43dee4f	3773	case LSM6DSOX_I2C_DISABLE:
cparata	0:f27ce43dee4f	3774	*val = LSM6DSOX_I2C_DISABLE;
cparata	0:f27ce43dee4f	3775	break;
cparata	0:f27ce43dee4f	3776	default:
cparata	0:f27ce43dee4f	3777	*val = LSM6DSOX_I2C_ENABLE;
cparata	0:f27ce43dee4f	3778	break;
cparata	0:f27ce43dee4f	3779	}
cparata	0:f27ce43dee4f	3780	return ret;
cparata	0:f27ce43dee4f	3781	}
cparata	0:f27ce43dee4f	3782
cparata	0:f27ce43dee4f	3783	/**
cparata	0:f27ce43dee4f	3784	* @brief I3C Enable/Disable communication protocol[.set]
cparata	0:f27ce43dee4f	3785	*
cparata	0:f27ce43dee4f	3786	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3787	* @param val change the values of i3c_disable
cparata	0:f27ce43dee4f	3788	* in reg CTRL9_XL
cparata	0:f27ce43dee4f	3789	*
cparata	0:f27ce43dee4f	3790	*/
cparata	0:f27ce43dee4f	3791	int32_t lsm6dsox_i3c_disable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_i3c_disable_t val)
cparata	0:f27ce43dee4f	3792	{
cparata	0:f27ce43dee4f	3793	lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata	0:f27ce43dee4f	3794	lsm6dsox_ctrl9_xl_t ctrl9_xl;
cparata	0:f27ce43dee4f	3795	int32_t ret;
cparata	0:f27ce43dee4f	3796
cparata	0:f27ce43dee4f	3797	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata	0:f27ce43dee4f	3798	if (ret == 0) {
cparata	0:f27ce43dee4f	3799	ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
cparata	0:f27ce43dee4f	3800	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata	0:f27ce43dee4f	3801	}
cparata	0:f27ce43dee4f	3802	if (ret == 0) {
cparata	0:f27ce43dee4f	3803
cparata	0:f27ce43dee4f	3804	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	0:f27ce43dee4f	3805	(uint8_t*)&i3c_bus_avb, 1);
cparata	0:f27ce43dee4f	3806	}
cparata	0:f27ce43dee4f	3807	if (ret == 0) {
cparata	0:f27ce43dee4f	3808	i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
cparata	0:f27ce43dee4f	3809	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	0:f27ce43dee4f	3810	(uint8_t*)&i3c_bus_avb, 1);
cparata	0:f27ce43dee4f	3811	}
cparata	0:f27ce43dee4f	3812
cparata	0:f27ce43dee4f	3813	return ret;
cparata	0:f27ce43dee4f	3814	}
cparata	0:f27ce43dee4f	3815
cparata	0:f27ce43dee4f	3816	/**
cparata	0:f27ce43dee4f	3817	* @brief I3C Enable/Disable communication protocol.[get]
cparata	0:f27ce43dee4f	3818	*
cparata	0:f27ce43dee4f	3819	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3820	* @param val change the values of i3c_disable in
cparata	0:f27ce43dee4f	3821	* reg CTRL9_XL
cparata	0:f27ce43dee4f	3822	*
cparata	0:f27ce43dee4f	3823	*/
cparata	0:f27ce43dee4f	3824	int32_t lsm6dsox_i3c_disable_get(lsm6dsox_ctx_t ctx, lsm6dsox_i3c_disable_t val)
cparata	0:f27ce43dee4f	3825	{
cparata	0:f27ce43dee4f	3826	lsm6dsox_ctrl9_xl_t ctrl9_xl;
cparata	0:f27ce43dee4f	3827	lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata	0:f27ce43dee4f	3828	int32_t ret;
cparata	0:f27ce43dee4f	3829
cparata	0:f27ce43dee4f	3830	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata	0:f27ce43dee4f	3831	if (ret == 0) {
cparata	0:f27ce43dee4f	3832	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	0:f27ce43dee4f	3833	(uint8_t*)&i3c_bus_avb, 1);
cparata	0:f27ce43dee4f	3834
cparata	0:f27ce43dee4f	3835	switch ((ctrl9_xl.i3c_disable << 7) \| i3c_bus_avb.i3c_bus_avb_sel) {
cparata	0:f27ce43dee4f	3836	case LSM6DSOX_I3C_DISABLE:
cparata	0:f27ce43dee4f	3837	*val = LSM6DSOX_I3C_DISABLE;
cparata	0:f27ce43dee4f	3838	break;
cparata	0:f27ce43dee4f	3839	case LSM6DSOX_I3C_ENABLE_T_50us:
cparata	0:f27ce43dee4f	3840	*val = LSM6DSOX_I3C_ENABLE_T_50us;
cparata	0:f27ce43dee4f	3841	break;
cparata	0:f27ce43dee4f	3842	case LSM6DSOX_I3C_ENABLE_T_2us:
cparata	0:f27ce43dee4f	3843	*val = LSM6DSOX_I3C_ENABLE_T_2us;
cparata	0:f27ce43dee4f	3844	break;
cparata	0:f27ce43dee4f	3845	case LSM6DSOX_I3C_ENABLE_T_1ms:
cparata	0:f27ce43dee4f	3846	*val = LSM6DSOX_I3C_ENABLE_T_1ms;
cparata	0:f27ce43dee4f	3847	break;
cparata	0:f27ce43dee4f	3848	case LSM6DSOX_I3C_ENABLE_T_25ms:
cparata	0:f27ce43dee4f	3849	*val = LSM6DSOX_I3C_ENABLE_T_25ms;
cparata	0:f27ce43dee4f	3850	break;
cparata	0:f27ce43dee4f	3851	default:
cparata	0:f27ce43dee4f	3852	*val = LSM6DSOX_I3C_DISABLE;
cparata	0:f27ce43dee4f	3853	break;
cparata	0:f27ce43dee4f	3854	}
cparata	0:f27ce43dee4f	3855	}
cparata	0:f27ce43dee4f	3856	return ret;
cparata	0:f27ce43dee4f	3857	}
cparata	0:f27ce43dee4f	3858
cparata	0:f27ce43dee4f	3859	/**
cparata	0:f27ce43dee4f	3860	* @}
cparata	0:f27ce43dee4f	3861	*
cparata	0:f27ce43dee4f	3862	*/
cparata	0:f27ce43dee4f	3863
cparata	0:f27ce43dee4f	3864	/**
cparata	0:f27ce43dee4f	3865	* @defgroup LSM6DSOX_interrupt_pins
cparata	0:f27ce43dee4f	3866	* @brief This section groups all the functions that manage interrup pins
cparata	0:f27ce43dee4f	3867	* @{
cparata	0:f27ce43dee4f	3868	*
cparata	0:f27ce43dee4f	3869	*/
cparata	0:f27ce43dee4f	3870
cparata	0:f27ce43dee4f	3871	/**
cparata	0:f27ce43dee4f	3872	* @brief Push-pull/open drain selection on interrupt pads.[set]
cparata	0:f27ce43dee4f	3873	*
cparata	0:f27ce43dee4f	3874	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3875	* @param val change the values of pp_od in reg CTRL3_C
cparata	0:f27ce43dee4f	3876	*
cparata	0:f27ce43dee4f	3877	*/
cparata	0:f27ce43dee4f	3878	int32_t lsm6dsox_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t val)
cparata	0:f27ce43dee4f	3879	{
cparata	0:f27ce43dee4f	3880	lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata	0:f27ce43dee4f	3881	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	0:f27ce43dee4f	3882	int32_t ret;
cparata	0:f27ce43dee4f	3883
cparata	0:f27ce43dee4f	3884	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	0:f27ce43dee4f	3885	if (ret == 0) {
cparata	0:f27ce43dee4f	3886	ctrl3_c.pp_od = (uint8_t)val;
cparata	0:f27ce43dee4f	3887	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	0:f27ce43dee4f	3888	}
cparata	0:f27ce43dee4f	3889	if (ret == 0) {
cparata	0:f27ce43dee4f	3890	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	0:f27ce43dee4f	3891	(uint8_t*)&i3c_bus_avb, 1);
cparata	0:f27ce43dee4f	3892	}
cparata	0:f27ce43dee4f	3893	if (ret == 0) {
cparata	0:f27ce43dee4f	3894	i3c_bus_avb.pd_dis_int1 = ( (uint8_t) val & 0x02U ) >> 1;
cparata	0:f27ce43dee4f	3895	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	0:f27ce43dee4f	3896	(uint8_t*)&i3c_bus_avb, 1);
cparata	0:f27ce43dee4f	3897	}
cparata	0:f27ce43dee4f	3898	return ret;
cparata	0:f27ce43dee4f	3899	}
cparata	0:f27ce43dee4f	3900
cparata	0:f27ce43dee4f	3901	/**
cparata	0:f27ce43dee4f	3902	* @brief Push-pull/open drain selection on interrupt pads.[get]
cparata	0:f27ce43dee4f	3903	*
cparata	0:f27ce43dee4f	3904	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3905	* @param val Get the values of pp_od in reg CTRL3_C
cparata	0:f27ce43dee4f	3906	*
cparata	0:f27ce43dee4f	3907	*/
cparata	0:f27ce43dee4f	3908	int32_t lsm6dsox_pin_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_pp_od_t val)
cparata	0:f27ce43dee4f	3909	{
cparata	0:f27ce43dee4f	3910	lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata	0:f27ce43dee4f	3911	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	0:f27ce43dee4f	3912	int32_t ret;
cparata	0:f27ce43dee4f	3913
cparata	0:f27ce43dee4f	3914	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	0:f27ce43dee4f	3915	if (ret == 0) {
cparata	0:f27ce43dee4f	3916	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	0:f27ce43dee4f	3917	(uint8_t*)&i3c_bus_avb, 1);
cparata	0:f27ce43dee4f	3918	}
cparata	1:fe40aec6e97a	3919
cparata	0:f27ce43dee4f	3920	switch ( (i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od) {
cparata	0:f27ce43dee4f	3921	case LSM6DSOX_PUSH_PULL:
cparata	0:f27ce43dee4f	3922	*val = LSM6DSOX_PUSH_PULL;
cparata	0:f27ce43dee4f	3923	break;
cparata	0:f27ce43dee4f	3924	case LSM6DSOX_OPEN_DRAIN:
cparata	0:f27ce43dee4f	3925	*val = LSM6DSOX_OPEN_DRAIN;
cparata	0:f27ce43dee4f	3926	break;
cparata	0:f27ce43dee4f	3927	case LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL:
cparata	0:f27ce43dee4f	3928	*val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL;
cparata	0:f27ce43dee4f	3929	break;
cparata	0:f27ce43dee4f	3930	case LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN:
cparata	0:f27ce43dee4f	3931	*val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN;
cparata	0:f27ce43dee4f	3932	break;
cparata	0:f27ce43dee4f	3933	default:
cparata	0:f27ce43dee4f	3934	*val = LSM6DSOX_PUSH_PULL;
cparata	0:f27ce43dee4f	3935	break;
cparata	0:f27ce43dee4f	3936	}
cparata	0:f27ce43dee4f	3937	return ret;
cparata	0:f27ce43dee4f	3938	}
cparata	0:f27ce43dee4f	3939
cparata	0:f27ce43dee4f	3940	/**
cparata	0:f27ce43dee4f	3941	* @brief Interrupt active-high/low.[set]
cparata	0:f27ce43dee4f	3942	*
cparata	0:f27ce43dee4f	3943	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3944	* @param val change the values of h_lactive in reg CTRL3_C
cparata	0:f27ce43dee4f	3945	*
cparata	0:f27ce43dee4f	3946	*/
cparata	0:f27ce43dee4f	3947	int32_t lsm6dsox_pin_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_h_lactive_t val)
cparata	0:f27ce43dee4f	3948	{
cparata	0:f27ce43dee4f	3949	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	3950	int32_t ret;
cparata	0:f27ce43dee4f	3951
cparata	0:f27ce43dee4f	3952	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3953	if (ret == 0) {
cparata	0:f27ce43dee4f	3954	reg.h_lactive = (uint8_t)val;
cparata	0:f27ce43dee4f	3955	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3956	}
cparata	0:f27ce43dee4f	3957
cparata	0:f27ce43dee4f	3958	return ret;
cparata	0:f27ce43dee4f	3959	}
cparata	0:f27ce43dee4f	3960
cparata	0:f27ce43dee4f	3961	/**
cparata	0:f27ce43dee4f	3962	* @brief Interrupt active-high/low.[get]
cparata	0:f27ce43dee4f	3963	*
cparata	0:f27ce43dee4f	3964	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3965	* @param val Get the values of h_lactive in reg CTRL3_C
cparata	0:f27ce43dee4f	3966	*
cparata	0:f27ce43dee4f	3967	*/
cparata	0:f27ce43dee4f	3968	int32_t lsm6dsox_pin_polarity_get(lsm6dsox_ctx_t ctx, lsm6dsox_h_lactive_t val)
cparata	0:f27ce43dee4f	3969	{
cparata	0:f27ce43dee4f	3970	lsm6dsox_ctrl3_c_t reg;
cparata	0:f27ce43dee4f	3971	int32_t ret;
cparata	0:f27ce43dee4f	3972
cparata	0:f27ce43dee4f	3973	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	3974
cparata	0:f27ce43dee4f	3975	switch (reg.h_lactive) {
cparata	0:f27ce43dee4f	3976	case LSM6DSOX_ACTIVE_HIGH:
cparata	0:f27ce43dee4f	3977	*val = LSM6DSOX_ACTIVE_HIGH;
cparata	0:f27ce43dee4f	3978	break;
cparata	0:f27ce43dee4f	3979	case LSM6DSOX_ACTIVE_LOW:
cparata	0:f27ce43dee4f	3980	*val = LSM6DSOX_ACTIVE_LOW;
cparata	0:f27ce43dee4f	3981	break;
cparata	0:f27ce43dee4f	3982	default:
cparata	0:f27ce43dee4f	3983	*val = LSM6DSOX_ACTIVE_HIGH;
cparata	0:f27ce43dee4f	3984	break;
cparata	0:f27ce43dee4f	3985	}
cparata	0:f27ce43dee4f	3986	return ret;
cparata	0:f27ce43dee4f	3987	}
cparata	0:f27ce43dee4f	3988
cparata	0:f27ce43dee4f	3989	/**
cparata	0:f27ce43dee4f	3990	* @brief All interrupt signals become available on INT1 pin.[set]
cparata	0:f27ce43dee4f	3991	*
cparata	0:f27ce43dee4f	3992	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	3993	* @param val change the values of int2_on_int1 in reg CTRL4_C
cparata	0:f27ce43dee4f	3994	*
cparata	0:f27ce43dee4f	3995	*/
cparata	0:f27ce43dee4f	3996	int32_t lsm6dsox_all_on_int1_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	3997	{
cparata	0:f27ce43dee4f	3998	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	3999	int32_t ret;
cparata	0:f27ce43dee4f	4000
cparata	0:f27ce43dee4f	4001	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4002	if (ret == 0) {
cparata	0:f27ce43dee4f	4003	reg.int2_on_int1 = val;
cparata	0:f27ce43dee4f	4004	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4005	}
cparata	0:f27ce43dee4f	4006
cparata	0:f27ce43dee4f	4007	return ret;
cparata	0:f27ce43dee4f	4008	}
cparata	0:f27ce43dee4f	4009
cparata	0:f27ce43dee4f	4010	/**
cparata	0:f27ce43dee4f	4011	* @brief All interrupt signals become available on INT1 pin.[get]
cparata	0:f27ce43dee4f	4012	*
cparata	0:f27ce43dee4f	4013	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4014	* @param val change the values of int2_on_int1 in reg CTRL4_C
cparata	0:f27ce43dee4f	4015	*
cparata	0:f27ce43dee4f	4016	*/
cparata	0:f27ce43dee4f	4017	int32_t lsm6dsox_all_on_int1_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4018	{
cparata	0:f27ce43dee4f	4019	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	4020	int32_t ret;
cparata	0:f27ce43dee4f	4021
cparata	0:f27ce43dee4f	4022	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4023	*val = reg.int2_on_int1;
cparata	0:f27ce43dee4f	4024
cparata	0:f27ce43dee4f	4025	return ret;
cparata	0:f27ce43dee4f	4026	}
cparata	0:f27ce43dee4f	4027
cparata	0:f27ce43dee4f	4028	/**
cparata	0:f27ce43dee4f	4029	* @brief Interrupt notification mode.[set]
cparata	0:f27ce43dee4f	4030	*
cparata	0:f27ce43dee4f	4031	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4032	* @param val change the values of lir in reg TAP_CFG0
cparata	0:f27ce43dee4f	4033	*
cparata	0:f27ce43dee4f	4034	*/
cparata	0:f27ce43dee4f	4035	int32_t lsm6dsox_int_notification_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t val)
cparata	0:f27ce43dee4f	4036	{
cparata	0:f27ce43dee4f	4037	lsm6dsox_tap_cfg0_t tap_cfg0;
cparata	0:f27ce43dee4f	4038	lsm6dsox_page_rw_t page_rw;
cparata	0:f27ce43dee4f	4039	int32_t ret;
cparata	0:f27ce43dee4f	4040
cparata	0:f27ce43dee4f	4041	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	0:f27ce43dee4f	4042	if (ret == 0) {
cparata	0:f27ce43dee4f	4043	tap_cfg0.lir = (uint8_t)val & 0x01U;
cparata	0:f27ce43dee4f	4044	tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
cparata	0:f27ce43dee4f	4045	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	0:f27ce43dee4f	4046	}
cparata	0:f27ce43dee4f	4047	if (ret == 0) {
cparata	0:f27ce43dee4f	4048
cparata	0:f27ce43dee4f	4049	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	4050	}
cparata	0:f27ce43dee4f	4051	if (ret == 0) {
cparata	0:f27ce43dee4f	4052	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	4053	}
cparata	0:f27ce43dee4f	4054	if (ret == 0) {
cparata	0:f27ce43dee4f	4055	page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
cparata	0:f27ce43dee4f	4056	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	4057	}
cparata	0:f27ce43dee4f	4058	if (ret == 0) {
cparata	0:f27ce43dee4f	4059	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	4060	}
cparata	0:f27ce43dee4f	4061
cparata	0:f27ce43dee4f	4062	return ret;
cparata	0:f27ce43dee4f	4063	}
cparata	0:f27ce43dee4f	4064
cparata	0:f27ce43dee4f	4065	/**
cparata	0:f27ce43dee4f	4066	* @brief Interrupt notification mode.[get]
cparata	0:f27ce43dee4f	4067	*
cparata	0:f27ce43dee4f	4068	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4069	* @param val Get the values of lir in reg TAP_CFG0
cparata	0:f27ce43dee4f	4070	*
cparata	0:f27ce43dee4f	4071	*/
cparata	0:f27ce43dee4f	4072	int32_t lsm6dsox_int_notification_get(lsm6dsox_ctx_t ctx, lsm6dsox_lir_t val)
cparata	0:f27ce43dee4f	4073	{
cparata	0:f27ce43dee4f	4074	lsm6dsox_tap_cfg0_t tap_cfg0;
cparata	0:f27ce43dee4f	4075	lsm6dsox_page_rw_t page_rw;
cparata	0:f27ce43dee4f	4076	int32_t ret;
cparata	0:f27ce43dee4f	4077
cparata	0:f27ce43dee4f	4078
cparata	0:f27ce43dee4f	4079	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	0:f27ce43dee4f	4080	if (ret == 0) {
cparata	0:f27ce43dee4f	4081
cparata	0:f27ce43dee4f	4082	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	4083	}
cparata	0:f27ce43dee4f	4084	if (ret == 0) {
cparata	0:f27ce43dee4f	4085	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	4086	}
cparata	0:f27ce43dee4f	4087	if (ret == 0) {
cparata	0:f27ce43dee4f	4088	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	4089	}
cparata	0:f27ce43dee4f	4090	if (ret == 0) {
cparata	0:f27ce43dee4f	4091	switch ((page_rw.emb_func_lir << 1) \| tap_cfg0.lir) {
cparata	0:f27ce43dee4f	4092	case LSM6DSOX_ALL_INT_PULSED:
cparata	0:f27ce43dee4f	4093	*val = LSM6DSOX_ALL_INT_PULSED;
cparata	0:f27ce43dee4f	4094	break;
cparata	0:f27ce43dee4f	4095	case LSM6DSOX_BASE_LATCHED_EMB_PULSED:
cparata	0:f27ce43dee4f	4096	*val = LSM6DSOX_BASE_LATCHED_EMB_PULSED;
cparata	0:f27ce43dee4f	4097	break;
cparata	0:f27ce43dee4f	4098	case LSM6DSOX_BASE_PULSED_EMB_LATCHED:
cparata	0:f27ce43dee4f	4099	*val = LSM6DSOX_BASE_PULSED_EMB_LATCHED;
cparata	0:f27ce43dee4f	4100	break;
cparata	0:f27ce43dee4f	4101	case LSM6DSOX_ALL_INT_LATCHED:
cparata	0:f27ce43dee4f	4102	*val = LSM6DSOX_ALL_INT_LATCHED;
cparata	0:f27ce43dee4f	4103	break;
cparata	0:f27ce43dee4f	4104	default:
cparata	0:f27ce43dee4f	4105	*val = LSM6DSOX_ALL_INT_PULSED;
cparata	0:f27ce43dee4f	4106	break;
cparata	0:f27ce43dee4f	4107	}
cparata	0:f27ce43dee4f	4108	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	4109	}
cparata	0:f27ce43dee4f	4110	if (ret == 0) {
cparata	0:f27ce43dee4f	4111	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:f27ce43dee4f	4112	}
cparata	0:f27ce43dee4f	4113	if (ret == 0) {
cparata	0:f27ce43dee4f	4114	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	4115	}
cparata	0:f27ce43dee4f	4116
cparata	0:f27ce43dee4f	4117	return ret;
cparata	0:f27ce43dee4f	4118	}
cparata	0:f27ce43dee4f	4119
cparata	0:f27ce43dee4f	4120	/**
cparata	0:f27ce43dee4f	4121	* @}
cparata	0:f27ce43dee4f	4122	*
cparata	0:f27ce43dee4f	4123	*/
cparata	0:f27ce43dee4f	4124
cparata	0:f27ce43dee4f	4125	/**
cparata	0:f27ce43dee4f	4126	* @defgroup LSM6DSOX_Wake_Up_event
cparata	0:f27ce43dee4f	4127	* @brief This section groups all the functions that manage the Wake Up
cparata	0:f27ce43dee4f	4128	* event generation.
cparata	0:f27ce43dee4f	4129	* @{
cparata	0:f27ce43dee4f	4130	*
cparata	0:f27ce43dee4f	4131	*/
cparata	0:f27ce43dee4f	4132
cparata	0:f27ce43dee4f	4133	/**
cparata	0:f27ce43dee4f	4134	* @brief Weight of 1 LSB of wakeup threshold.[set]
cparata	0:f27ce43dee4f	4135	* 0: 1 LSB =FS_XL / 64
cparata	0:f27ce43dee4f	4136	* 1: 1 LSB = FS_XL / 256
cparata	0:f27ce43dee4f	4137	*
cparata	0:f27ce43dee4f	4138	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4139	* @param val change the values of wake_ths_w in
cparata	0:f27ce43dee4f	4140	* reg WAKE_UP_DUR
cparata	0:f27ce43dee4f	4141	*
cparata	0:f27ce43dee4f	4142	*/
cparata	0:f27ce43dee4f	4143	int32_t lsm6dsox_wkup_ths_weight_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	4144	lsm6dsox_wake_ths_w_t val)
cparata	0:f27ce43dee4f	4145	{
cparata	0:f27ce43dee4f	4146	lsm6dsox_wake_up_dur_t reg;
cparata	0:f27ce43dee4f	4147	int32_t ret;
cparata	0:f27ce43dee4f	4148
cparata	0:f27ce43dee4f	4149	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4150	if (ret == 0) {
cparata	0:f27ce43dee4f	4151	reg.wake_ths_w = (uint8_t)val;
cparata	0:f27ce43dee4f	4152	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4153	}
cparata	0:f27ce43dee4f	4154	return ret;
cparata	0:f27ce43dee4f	4155	}
cparata	0:f27ce43dee4f	4156
cparata	0:f27ce43dee4f	4157	/**
cparata	0:f27ce43dee4f	4158	* @brief Weight of 1 LSB of wakeup threshold.[get]
cparata	0:f27ce43dee4f	4159	* 0: 1 LSB =FS_XL / 64
cparata	0:f27ce43dee4f	4160	* 1: 1 LSB = FS_XL / 256
cparata	0:f27ce43dee4f	4161	*
cparata	0:f27ce43dee4f	4162	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4163	* @param val Get the values of wake_ths_w in
cparata	0:f27ce43dee4f	4164	* reg WAKE_UP_DUR
cparata	0:f27ce43dee4f	4165	*
cparata	0:f27ce43dee4f	4166	*/
cparata	0:f27ce43dee4f	4167	int32_t lsm6dsox_wkup_ths_weight_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	4168	lsm6dsox_wake_ths_w_t *val)
cparata	0:f27ce43dee4f	4169	{
cparata	0:f27ce43dee4f	4170	lsm6dsox_wake_up_dur_t reg;
cparata	0:f27ce43dee4f	4171	int32_t ret;
cparata	0:f27ce43dee4f	4172
cparata	0:f27ce43dee4f	4173	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4174
cparata	0:f27ce43dee4f	4175	switch (reg.wake_ths_w) {
cparata	0:f27ce43dee4f	4176	case LSM6DSOX_LSb_FS_DIV_64:
cparata	0:f27ce43dee4f	4177	*val = LSM6DSOX_LSb_FS_DIV_64;
cparata	0:f27ce43dee4f	4178	break;
cparata	0:f27ce43dee4f	4179	case LSM6DSOX_LSb_FS_DIV_256:
cparata	0:f27ce43dee4f	4180	*val = LSM6DSOX_LSb_FS_DIV_256;
cparata	0:f27ce43dee4f	4181	break;
cparata	0:f27ce43dee4f	4182	default:
cparata	0:f27ce43dee4f	4183	*val = LSM6DSOX_LSb_FS_DIV_64;
cparata	0:f27ce43dee4f	4184	break;
cparata	0:f27ce43dee4f	4185	}
cparata	0:f27ce43dee4f	4186	return ret;
cparata	0:f27ce43dee4f	4187	}
cparata	0:f27ce43dee4f	4188
cparata	0:f27ce43dee4f	4189	/**
cparata	0:f27ce43dee4f	4190	* @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata	0:f27ce43dee4f	4191	* WAKE_UP_DUR.[set]
cparata	0:f27ce43dee4f	4192	*
cparata	0:f27ce43dee4f	4193	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4194	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:f27ce43dee4f	4195	*
cparata	0:f27ce43dee4f	4196	*/
cparata	0:f27ce43dee4f	4197	int32_t lsm6dsox_wkup_threshold_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4198	{
cparata	0:f27ce43dee4f	4199	lsm6dsox_wake_up_ths_t reg;
cparata	0:f27ce43dee4f	4200	int32_t ret;
cparata	0:f27ce43dee4f	4201
cparata	0:f27ce43dee4f	4202	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4203	if (ret == 0) {
cparata	0:f27ce43dee4f	4204	reg.wk_ths = val;
cparata	0:f27ce43dee4f	4205	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4206	}
cparata	0:f27ce43dee4f	4207	return ret;
cparata	0:f27ce43dee4f	4208	}
cparata	0:f27ce43dee4f	4209
cparata	0:f27ce43dee4f	4210	/**
cparata	0:f27ce43dee4f	4211	* @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata	0:f27ce43dee4f	4212	* WAKE_UP_DUR.[get]
cparata	0:f27ce43dee4f	4213	*
cparata	0:f27ce43dee4f	4214	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4215	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:f27ce43dee4f	4216	*
cparata	0:f27ce43dee4f	4217	*/
cparata	0:f27ce43dee4f	4218	int32_t lsm6dsox_wkup_threshold_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4219	{
cparata	0:f27ce43dee4f	4220	lsm6dsox_wake_up_ths_t reg;
cparata	0:f27ce43dee4f	4221	int32_t ret;
cparata	0:f27ce43dee4f	4222
cparata	0:f27ce43dee4f	4223	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4224	*val = reg.wk_ths;
cparata	0:f27ce43dee4f	4225
cparata	0:f27ce43dee4f	4226	return ret;
cparata	0:f27ce43dee4f	4227	}
cparata	0:f27ce43dee4f	4228
cparata	0:f27ce43dee4f	4229	/**
cparata	0:f27ce43dee4f	4230	* @brief Wake up duration event.[set]
cparata	0:f27ce43dee4f	4231	* 1LSb = 1 / ODR
cparata	0:f27ce43dee4f	4232	*
cparata	0:f27ce43dee4f	4233	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4234	* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata	0:f27ce43dee4f	4235	*
cparata	0:f27ce43dee4f	4236	*/
cparata	0:f27ce43dee4f	4237	int32_t lsm6dsox_xl_usr_offset_on_wkup_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4238	{
cparata	0:f27ce43dee4f	4239	lsm6dsox_wake_up_ths_t reg;
cparata	0:f27ce43dee4f	4240	int32_t ret;
cparata	0:f27ce43dee4f	4241
cparata	0:f27ce43dee4f	4242	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4243	if (ret == 0) {
cparata	0:f27ce43dee4f	4244	reg.usr_off_on_wu = val;
cparata	0:f27ce43dee4f	4245	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4246	}
cparata	0:f27ce43dee4f	4247	return ret;
cparata	0:f27ce43dee4f	4248	}
cparata	0:f27ce43dee4f	4249
cparata	0:f27ce43dee4f	4250	/**
cparata	0:f27ce43dee4f	4251	* @brief Wake up duration event.[get]
cparata	0:f27ce43dee4f	4252	* 1LSb = 1 / ODR
cparata	0:f27ce43dee4f	4253	*
cparata	0:f27ce43dee4f	4254	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4255	* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata	0:f27ce43dee4f	4256	*
cparata	0:f27ce43dee4f	4257	*/
cparata	0:f27ce43dee4f	4258	int32_t lsm6dsox_xl_usr_offset_on_wkup_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4259	{
cparata	0:f27ce43dee4f	4260	lsm6dsox_wake_up_ths_t reg;
cparata	0:f27ce43dee4f	4261	int32_t ret;
cparata	0:f27ce43dee4f	4262
cparata	0:f27ce43dee4f	4263	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4264	*val = reg.usr_off_on_wu;
cparata	0:f27ce43dee4f	4265
cparata	0:f27ce43dee4f	4266	return ret;
cparata	0:f27ce43dee4f	4267	}
cparata	0:f27ce43dee4f	4268
cparata	0:f27ce43dee4f	4269	/**
cparata	0:f27ce43dee4f	4270	* @brief Wake up duration event.[set]
cparata	0:f27ce43dee4f	4271	* 1LSb = 1 / ODR
cparata	0:f27ce43dee4f	4272	*
cparata	0:f27ce43dee4f	4273	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4274	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:f27ce43dee4f	4275	*
cparata	0:f27ce43dee4f	4276	*/
cparata	0:f27ce43dee4f	4277	int32_t lsm6dsox_wkup_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4278	{
cparata	0:f27ce43dee4f	4279	lsm6dsox_wake_up_dur_t reg;
cparata	0:f27ce43dee4f	4280	int32_t ret;
cparata	0:f27ce43dee4f	4281
cparata	0:f27ce43dee4f	4282	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4283	if (ret == 0) {
cparata	0:f27ce43dee4f	4284	reg.wake_dur = val;
cparata	0:f27ce43dee4f	4285	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4286	}
cparata	0:f27ce43dee4f	4287	return ret;
cparata	0:f27ce43dee4f	4288	}
cparata	0:f27ce43dee4f	4289
cparata	0:f27ce43dee4f	4290	/**
cparata	0:f27ce43dee4f	4291	* @brief Wake up duration event.[get]
cparata	0:f27ce43dee4f	4292	* 1LSb = 1 / ODR
cparata	0:f27ce43dee4f	4293	*
cparata	0:f27ce43dee4f	4294	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4295	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:f27ce43dee4f	4296	*
cparata	0:f27ce43dee4f	4297	*/
cparata	0:f27ce43dee4f	4298	int32_t lsm6dsox_wkup_dur_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4299	{
cparata	0:f27ce43dee4f	4300	lsm6dsox_wake_up_dur_t reg;
cparata	0:f27ce43dee4f	4301	int32_t ret;
cparata	0:f27ce43dee4f	4302
cparata	0:f27ce43dee4f	4303	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4304	*val = reg.wake_dur;
cparata	0:f27ce43dee4f	4305
cparata	0:f27ce43dee4f	4306	return ret;
cparata	0:f27ce43dee4f	4307	}
cparata	0:f27ce43dee4f	4308
cparata	0:f27ce43dee4f	4309	/**
cparata	0:f27ce43dee4f	4310	* @}
cparata	0:f27ce43dee4f	4311	*
cparata	0:f27ce43dee4f	4312	*/
cparata	0:f27ce43dee4f	4313
cparata	0:f27ce43dee4f	4314	/**
cparata	0:f27ce43dee4f	4315	* @defgroup LSM6DSOX_ Activity/Inactivity_detection
cparata	0:f27ce43dee4f	4316	* @brief This section groups all the functions concerning
cparata	0:f27ce43dee4f	4317	* activity/inactivity detection.
cparata	0:f27ce43dee4f	4318	* @{
cparata	0:f27ce43dee4f	4319	*
cparata	0:f27ce43dee4f	4320	*/
cparata	0:f27ce43dee4f	4321
cparata	0:f27ce43dee4f	4322	/**
cparata	0:f27ce43dee4f	4323	* @brief Enables gyroscope Sleep mode.[set]
cparata	0:f27ce43dee4f	4324	*
cparata	0:f27ce43dee4f	4325	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4326	* @param val change the values of sleep_g in reg CTRL4_C
cparata	0:f27ce43dee4f	4327	*
cparata	0:f27ce43dee4f	4328	*/
cparata	0:f27ce43dee4f	4329	int32_t lsm6dsox_gy_sleep_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4330	{
cparata	0:f27ce43dee4f	4331	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	4332	int32_t ret;
cparata	0:f27ce43dee4f	4333
cparata	0:f27ce43dee4f	4334	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4335	if (ret == 0) {
cparata	0:f27ce43dee4f	4336	reg.sleep_g = val;
cparata	0:f27ce43dee4f	4337	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4338	}
cparata	0:f27ce43dee4f	4339	return ret;
cparata	0:f27ce43dee4f	4340	}
cparata	0:f27ce43dee4f	4341
cparata	0:f27ce43dee4f	4342	/**
cparata	0:f27ce43dee4f	4343	* @brief Enables gyroscope Sleep mode.[get]
cparata	0:f27ce43dee4f	4344	*
cparata	0:f27ce43dee4f	4345	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4346	* @param val change the values of sleep_g in reg CTRL4_C
cparata	0:f27ce43dee4f	4347	*
cparata	0:f27ce43dee4f	4348	*/
cparata	0:f27ce43dee4f	4349	int32_t lsm6dsox_gy_sleep_mode_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4350	{
cparata	0:f27ce43dee4f	4351	lsm6dsox_ctrl4_c_t reg;
cparata	0:f27ce43dee4f	4352	int32_t ret;
cparata	0:f27ce43dee4f	4353
cparata	0:f27ce43dee4f	4354	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4355	*val = reg.sleep_g;
cparata	0:f27ce43dee4f	4356
cparata	0:f27ce43dee4f	4357	return ret;
cparata	0:f27ce43dee4f	4358	}
cparata	0:f27ce43dee4f	4359
cparata	0:f27ce43dee4f	4360	/**
cparata	0:f27ce43dee4f	4361	* @brief Drives the sleep status instead of
cparata	0:f27ce43dee4f	4362	* sleep change on INT pins
cparata	0:f27ce43dee4f	4363	* (only if INT1_SLEEP_CHANGE or
cparata	0:f27ce43dee4f	4364	* INT2_SLEEP_CHANGE bits are enabled).[set]
cparata	0:f27ce43dee4f	4365	*
cparata	0:f27ce43dee4f	4366	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4367	* @param val change the values of sleep_status_on_int in reg TAP_CFG0
cparata	0:f27ce43dee4f	4368	*
cparata	0:f27ce43dee4f	4369	*/
cparata	0:f27ce43dee4f	4370	int32_t lsm6dsox_act_pin_notification_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	4371	lsm6dsox_sleep_status_on_int_t val)
cparata	0:f27ce43dee4f	4372	{
cparata	0:f27ce43dee4f	4373	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	4374	int32_t ret;
cparata	0:f27ce43dee4f	4375
cparata	0:f27ce43dee4f	4376	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4377	if (ret == 0) {
cparata	0:f27ce43dee4f	4378	reg.sleep_status_on_int = (uint8_t)val;
cparata	0:f27ce43dee4f	4379	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4380	}
cparata	0:f27ce43dee4f	4381	return ret;
cparata	0:f27ce43dee4f	4382	}
cparata	0:f27ce43dee4f	4383
cparata	0:f27ce43dee4f	4384	/**
cparata	0:f27ce43dee4f	4385	* @brief Drives the sleep status instead of
cparata	0:f27ce43dee4f	4386	* sleep change on INT pins (only if
cparata	0:f27ce43dee4f	4387	* INT1_SLEEP_CHANGE or
cparata	0:f27ce43dee4f	4388	* INT2_SLEEP_CHANGE bits are enabled).[get]
cparata	0:f27ce43dee4f	4389	*
cparata	0:f27ce43dee4f	4390	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4391	* @param val Get the values of sleep_status_on_int in reg TAP_CFG0
cparata	0:f27ce43dee4f	4392	*
cparata	0:f27ce43dee4f	4393	*/
cparata	0:f27ce43dee4f	4394	int32_t lsm6dsox_act_pin_notification_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	4395	lsm6dsox_sleep_status_on_int_t *val)
cparata	0:f27ce43dee4f	4396	{
cparata	0:f27ce43dee4f	4397	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	4398	int32_t ret;
cparata	0:f27ce43dee4f	4399
cparata	0:f27ce43dee4f	4400	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4401	switch (reg.sleep_status_on_int) {
cparata	0:f27ce43dee4f	4402	case LSM6DSOX_DRIVE_SLEEP_CHG_EVENT:
cparata	0:f27ce43dee4f	4403	*val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT;
cparata	0:f27ce43dee4f	4404	break;
cparata	0:f27ce43dee4f	4405	case LSM6DSOX_DRIVE_SLEEP_STATUS:
cparata	0:f27ce43dee4f	4406	*val = LSM6DSOX_DRIVE_SLEEP_STATUS;
cparata	0:f27ce43dee4f	4407	break;
cparata	0:f27ce43dee4f	4408	default:
cparata	0:f27ce43dee4f	4409	*val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT;
cparata	0:f27ce43dee4f	4410	break;
cparata	0:f27ce43dee4f	4411	}
cparata	0:f27ce43dee4f	4412	return ret;
cparata	0:f27ce43dee4f	4413	}
cparata	0:f27ce43dee4f	4414
cparata	0:f27ce43dee4f	4415	/**
cparata	0:f27ce43dee4f	4416	* @brief Enable inactivity function.[set]
cparata	0:f27ce43dee4f	4417	*
cparata	0:f27ce43dee4f	4418	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4419	* @param val change the values of inact_en in reg TAP_CFG2
cparata	0:f27ce43dee4f	4420	*
cparata	0:f27ce43dee4f	4421	*/
cparata	0:f27ce43dee4f	4422	int32_t lsm6dsox_act_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t val)
cparata	0:f27ce43dee4f	4423	{
cparata	0:f27ce43dee4f	4424	lsm6dsox_tap_cfg2_t reg;
cparata	0:f27ce43dee4f	4425	int32_t ret;
cparata	0:f27ce43dee4f	4426
cparata	0:f27ce43dee4f	4427	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4428	if (ret == 0) {
cparata	0:f27ce43dee4f	4429	reg.inact_en = (uint8_t)val;
cparata	0:f27ce43dee4f	4430	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4431	}
cparata	0:f27ce43dee4f	4432	return ret;
cparata	0:f27ce43dee4f	4433	}
cparata	0:f27ce43dee4f	4434
cparata	0:f27ce43dee4f	4435	/**
cparata	0:f27ce43dee4f	4436	* @brief Enable inactivity function.[get]
cparata	0:f27ce43dee4f	4437	*
cparata	0:f27ce43dee4f	4438	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4439	* @param val Get the values of inact_en in reg TAP_CFG2
cparata	0:f27ce43dee4f	4440	*
cparata	0:f27ce43dee4f	4441	*/
cparata	0:f27ce43dee4f	4442	int32_t lsm6dsox_act_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_inact_en_t val)
cparata	0:f27ce43dee4f	4443	{
cparata	0:f27ce43dee4f	4444	lsm6dsox_tap_cfg2_t reg;
cparata	0:f27ce43dee4f	4445	int32_t ret;
cparata	0:f27ce43dee4f	4446
cparata	0:f27ce43dee4f	4447	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4448	switch (reg.inact_en) {
cparata	0:f27ce43dee4f	4449	case LSM6DSOX_XL_AND_GY_NOT_AFFECTED:
cparata	0:f27ce43dee4f	4450	*val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED;
cparata	0:f27ce43dee4f	4451	break;
cparata	0:f27ce43dee4f	4452	case LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED:
cparata	0:f27ce43dee4f	4453	*val = LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED;
cparata	0:f27ce43dee4f	4454	break;
cparata	0:f27ce43dee4f	4455	case LSM6DSOX_XL_12Hz5_GY_SLEEP:
cparata	0:f27ce43dee4f	4456	*val = LSM6DSOX_XL_12Hz5_GY_SLEEP;
cparata	0:f27ce43dee4f	4457	break;
cparata	0:f27ce43dee4f	4458	case LSM6DSOX_XL_12Hz5_GY_PD:
cparata	0:f27ce43dee4f	4459	*val = LSM6DSOX_XL_12Hz5_GY_PD;
cparata	0:f27ce43dee4f	4460	break;
cparata	0:f27ce43dee4f	4461	default:
cparata	0:f27ce43dee4f	4462	*val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED;
cparata	0:f27ce43dee4f	4463	break;
cparata	0:f27ce43dee4f	4464	}
cparata	0:f27ce43dee4f	4465	return ret;
cparata	0:f27ce43dee4f	4466	}
cparata	0:f27ce43dee4f	4467
cparata	0:f27ce43dee4f	4468	/**
cparata	0:f27ce43dee4f	4469	* @brief Duration to go in sleep mode.[set]
cparata	0:f27ce43dee4f	4470	* 1 LSb = 512 / ODR
cparata	0:f27ce43dee4f	4471	*
cparata	0:f27ce43dee4f	4472	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4473	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:f27ce43dee4f	4474	*
cparata	0:f27ce43dee4f	4475	*/
cparata	0:f27ce43dee4f	4476	int32_t lsm6dsox_act_sleep_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4477	{
cparata	0:f27ce43dee4f	4478	lsm6dsox_wake_up_dur_t reg;
cparata	0:f27ce43dee4f	4479	int32_t ret;
cparata	0:f27ce43dee4f	4480
cparata	0:f27ce43dee4f	4481	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4482	if (ret == 0) {
cparata	0:f27ce43dee4f	4483	reg.sleep_dur = val;
cparata	0:f27ce43dee4f	4484	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4485	}
cparata	0:f27ce43dee4f	4486	return ret;
cparata	0:f27ce43dee4f	4487	}
cparata	0:f27ce43dee4f	4488
cparata	0:f27ce43dee4f	4489	/**
cparata	0:f27ce43dee4f	4490	* @brief Duration to go in sleep mode.[get]
cparata	0:f27ce43dee4f	4491	* 1 LSb = 512 / ODR
cparata	0:f27ce43dee4f	4492	*
cparata	0:f27ce43dee4f	4493	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4494	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:f27ce43dee4f	4495	*
cparata	0:f27ce43dee4f	4496	*/
cparata	0:f27ce43dee4f	4497	int32_t lsm6dsox_act_sleep_dur_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4498	{
cparata	0:f27ce43dee4f	4499	lsm6dsox_wake_up_dur_t reg;
cparata	0:f27ce43dee4f	4500	int32_t ret;
cparata	0:f27ce43dee4f	4501
cparata	0:f27ce43dee4f	4502	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4503	*val = reg.sleep_dur;
cparata	0:f27ce43dee4f	4504
cparata	0:f27ce43dee4f	4505	return ret;
cparata	0:f27ce43dee4f	4506	}
cparata	0:f27ce43dee4f	4507
cparata	0:f27ce43dee4f	4508	/**
cparata	0:f27ce43dee4f	4509	* @}
cparata	0:f27ce43dee4f	4510	*
cparata	0:f27ce43dee4f	4511	*/
cparata	0:f27ce43dee4f	4512
cparata	0:f27ce43dee4f	4513	/**
cparata	0:f27ce43dee4f	4514	* @defgroup LSM6DSOX_tap_generator
cparata	0:f27ce43dee4f	4515	* @brief This section groups all the functions that manage the
cparata	0:f27ce43dee4f	4516	* tap and double tap event generation.
cparata	0:f27ce43dee4f	4517	* @{
cparata	0:f27ce43dee4f	4518	*
cparata	0:f27ce43dee4f	4519	*/
cparata	0:f27ce43dee4f	4520
cparata	0:f27ce43dee4f	4521	/**
cparata	0:f27ce43dee4f	4522	* @brief Enable Z direction in tap recognition.[set]
cparata	0:f27ce43dee4f	4523	*
cparata	0:f27ce43dee4f	4524	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4525	* @param val change the values of tap_z_en in reg TAP_CFG0
cparata	0:f27ce43dee4f	4526	*
cparata	0:f27ce43dee4f	4527	*/
cparata	0:f27ce43dee4f	4528	int32_t lsm6dsox_tap_detection_on_z_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4529	{
cparata	0:f27ce43dee4f	4530	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	4531	int32_t ret;
cparata	0:f27ce43dee4f	4532
cparata	0:f27ce43dee4f	4533	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4534	if (ret == 0) {
cparata	0:f27ce43dee4f	4535	reg.tap_z_en = val;
cparata	0:f27ce43dee4f	4536	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4537	}
cparata	0:f27ce43dee4f	4538	return ret;
cparata	0:f27ce43dee4f	4539	}
cparata	0:f27ce43dee4f	4540
cparata	0:f27ce43dee4f	4541	/**
cparata	0:f27ce43dee4f	4542	* @brief Enable Z direction in tap recognition.[get]
cparata	0:f27ce43dee4f	4543	*
cparata	0:f27ce43dee4f	4544	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4545	* @param val change the values of tap_z_en in reg TAP_CFG0
cparata	0:f27ce43dee4f	4546	*
cparata	0:f27ce43dee4f	4547	*/
cparata	0:f27ce43dee4f	4548	int32_t lsm6dsox_tap_detection_on_z_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4549	{
cparata	0:f27ce43dee4f	4550	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	4551	int32_t ret;
cparata	0:f27ce43dee4f	4552
cparata	0:f27ce43dee4f	4553	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4554	*val = reg.tap_z_en;
cparata	0:f27ce43dee4f	4555
cparata	0:f27ce43dee4f	4556	return ret;
cparata	0:f27ce43dee4f	4557	}
cparata	0:f27ce43dee4f	4558
cparata	0:f27ce43dee4f	4559	/**
cparata	0:f27ce43dee4f	4560	* @brief Enable Y direction in tap recognition.[set]
cparata	0:f27ce43dee4f	4561	*
cparata	0:f27ce43dee4f	4562	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4563	* @param val change the values of tap_y_en in reg TAP_CFG0
cparata	0:f27ce43dee4f	4564	*
cparata	0:f27ce43dee4f	4565	*/
cparata	0:f27ce43dee4f	4566	int32_t lsm6dsox_tap_detection_on_y_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4567	{
cparata	0:f27ce43dee4f	4568	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	4569	int32_t ret;
cparata	0:f27ce43dee4f	4570
cparata	0:f27ce43dee4f	4571	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4572	if (ret == 0) {
cparata	0:f27ce43dee4f	4573	reg.tap_y_en = val;
cparata	0:f27ce43dee4f	4574	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4575	}
cparata	0:f27ce43dee4f	4576	return ret;
cparata	0:f27ce43dee4f	4577	}
cparata	0:f27ce43dee4f	4578
cparata	0:f27ce43dee4f	4579	/**
cparata	0:f27ce43dee4f	4580	* @brief Enable Y direction in tap recognition.[get]
cparata	0:f27ce43dee4f	4581	*
cparata	0:f27ce43dee4f	4582	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4583	* @param val change the values of tap_y_en in reg TAP_CFG0
cparata	0:f27ce43dee4f	4584	*
cparata	0:f27ce43dee4f	4585	*/
cparata	0:f27ce43dee4f	4586	int32_t lsm6dsox_tap_detection_on_y_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4587	{
cparata	0:f27ce43dee4f	4588	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	4589	int32_t ret;
cparata	0:f27ce43dee4f	4590
cparata	0:f27ce43dee4f	4591	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4592	*val = reg.tap_y_en;
cparata	0:f27ce43dee4f	4593
cparata	0:f27ce43dee4f	4594	return ret;
cparata	0:f27ce43dee4f	4595	}
cparata	0:f27ce43dee4f	4596
cparata	0:f27ce43dee4f	4597	/**
cparata	0:f27ce43dee4f	4598	* @brief Enable X direction in tap recognition.[set]
cparata	0:f27ce43dee4f	4599	*
cparata	0:f27ce43dee4f	4600	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4601	* @param val change the values of tap_x_en in reg TAP_CFG0
cparata	0:f27ce43dee4f	4602	*
cparata	0:f27ce43dee4f	4603	*/
cparata	0:f27ce43dee4f	4604	int32_t lsm6dsox_tap_detection_on_x_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4605	{
cparata	0:f27ce43dee4f	4606	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	4607	int32_t ret;
cparata	0:f27ce43dee4f	4608
cparata	0:f27ce43dee4f	4609	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4610	if (ret == 0) {
cparata	0:f27ce43dee4f	4611	reg.tap_x_en = val;
cparata	0:f27ce43dee4f	4612	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4613	}
cparata	0:f27ce43dee4f	4614	return ret;
cparata	0:f27ce43dee4f	4615	}
cparata	0:f27ce43dee4f	4616
cparata	0:f27ce43dee4f	4617	/**
cparata	0:f27ce43dee4f	4618	* @brief Enable X direction in tap recognition.[get]
cparata	0:f27ce43dee4f	4619	*
cparata	0:f27ce43dee4f	4620	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4621	* @param val change the values of tap_x_en in reg TAP_CFG0
cparata	0:f27ce43dee4f	4622	*
cparata	0:f27ce43dee4f	4623	*/
cparata	0:f27ce43dee4f	4624	int32_t lsm6dsox_tap_detection_on_x_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4625	{
cparata	0:f27ce43dee4f	4626	lsm6dsox_tap_cfg0_t reg;
cparata	0:f27ce43dee4f	4627	int32_t ret;
cparata	0:f27ce43dee4f	4628
cparata	0:f27ce43dee4f	4629	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4630	*val = reg.tap_x_en;
cparata	0:f27ce43dee4f	4631
cparata	0:f27ce43dee4f	4632	return ret;
cparata	0:f27ce43dee4f	4633	}
cparata	0:f27ce43dee4f	4634
cparata	0:f27ce43dee4f	4635	/**
cparata	0:f27ce43dee4f	4636	* @brief X-axis tap recognition threshold.[set]
cparata	0:f27ce43dee4f	4637	*
cparata	0:f27ce43dee4f	4638	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4639	* @param val change the values of tap_ths_x in reg TAP_CFG1
cparata	0:f27ce43dee4f	4640	*
cparata	0:f27ce43dee4f	4641	*/
cparata	0:f27ce43dee4f	4642	int32_t lsm6dsox_tap_threshold_x_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4643	{
cparata	0:f27ce43dee4f	4644	lsm6dsox_tap_cfg1_t reg;
cparata	0:f27ce43dee4f	4645	int32_t ret;
cparata	0:f27ce43dee4f	4646
cparata	0:f27ce43dee4f	4647	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4648	if (ret == 0) {
cparata	0:f27ce43dee4f	4649	reg.tap_ths_x = val;
cparata	0:f27ce43dee4f	4650	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4651	}
cparata	0:f27ce43dee4f	4652	return ret;
cparata	0:f27ce43dee4f	4653	}
cparata	0:f27ce43dee4f	4654
cparata	0:f27ce43dee4f	4655	/**
cparata	0:f27ce43dee4f	4656	* @brief X-axis tap recognition threshold.[get]
cparata	0:f27ce43dee4f	4657	*
cparata	0:f27ce43dee4f	4658	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4659	* @param val change the values of tap_ths_x in reg TAP_CFG1
cparata	0:f27ce43dee4f	4660	*
cparata	0:f27ce43dee4f	4661	*/
cparata	0:f27ce43dee4f	4662	int32_t lsm6dsox_tap_threshold_x_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4663	{
cparata	0:f27ce43dee4f	4664	lsm6dsox_tap_cfg1_t reg;
cparata	0:f27ce43dee4f	4665	int32_t ret;
cparata	0:f27ce43dee4f	4666
cparata	0:f27ce43dee4f	4667	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4668	*val = reg.tap_ths_x;
cparata	0:f27ce43dee4f	4669
cparata	0:f27ce43dee4f	4670	return ret;
cparata	0:f27ce43dee4f	4671	}
cparata	0:f27ce43dee4f	4672
cparata	0:f27ce43dee4f	4673	/**
cparata	0:f27ce43dee4f	4674	* @brief Selection of axis priority for TAP detection.[set]
cparata	0:f27ce43dee4f	4675	*
cparata	0:f27ce43dee4f	4676	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4677	* @param val change the values of tap_priority in
cparata	0:f27ce43dee4f	4678	* reg TAP_CFG1
cparata	0:f27ce43dee4f	4679	*
cparata	0:f27ce43dee4f	4680	*/
cparata	0:f27ce43dee4f	4681	int32_t lsm6dsox_tap_axis_priority_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	4682	lsm6dsox_tap_priority_t val)
cparata	0:f27ce43dee4f	4683	{
cparata	0:f27ce43dee4f	4684	lsm6dsox_tap_cfg1_t reg;
cparata	0:f27ce43dee4f	4685	int32_t ret;
cparata	0:f27ce43dee4f	4686
cparata	0:f27ce43dee4f	4687	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4688	if (ret == 0) {
cparata	0:f27ce43dee4f	4689	reg.tap_priority = (uint8_t)val;
cparata	0:f27ce43dee4f	4690	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4691	}
cparata	0:f27ce43dee4f	4692	return ret;
cparata	0:f27ce43dee4f	4693	}
cparata	0:f27ce43dee4f	4694
cparata	0:f27ce43dee4f	4695	/**
cparata	0:f27ce43dee4f	4696	* @brief Selection of axis priority for TAP detection.[get]
cparata	0:f27ce43dee4f	4697	*
cparata	0:f27ce43dee4f	4698	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4699	* @param val Get the values of tap_priority in
cparata	0:f27ce43dee4f	4700	* reg TAP_CFG1
cparata	0:f27ce43dee4f	4701	*
cparata	0:f27ce43dee4f	4702	*/
cparata	0:f27ce43dee4f	4703	int32_t lsm6dsox_tap_axis_priority_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	4704	lsm6dsox_tap_priority_t *val)
cparata	0:f27ce43dee4f	4705	{
cparata	0:f27ce43dee4f	4706	lsm6dsox_tap_cfg1_t reg;
cparata	0:f27ce43dee4f	4707	int32_t ret;
cparata	0:f27ce43dee4f	4708
cparata	0:f27ce43dee4f	4709	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4710	switch (reg.tap_priority) {
cparata	0:f27ce43dee4f	4711	case LSM6DSOX_XYZ:
cparata	0:f27ce43dee4f	4712	*val = LSM6DSOX_XYZ;
cparata	0:f27ce43dee4f	4713	break;
cparata	0:f27ce43dee4f	4714	case LSM6DSOX_YXZ:
cparata	0:f27ce43dee4f	4715	*val = LSM6DSOX_YXZ;
cparata	0:f27ce43dee4f	4716	break;
cparata	0:f27ce43dee4f	4717	case LSM6DSOX_XZY:
cparata	0:f27ce43dee4f	4718	*val = LSM6DSOX_XZY;
cparata	0:f27ce43dee4f	4719	break;
cparata	0:f27ce43dee4f	4720	case LSM6DSOX_ZYX:
cparata	0:f27ce43dee4f	4721	*val = LSM6DSOX_ZYX;
cparata	0:f27ce43dee4f	4722	break;
cparata	0:f27ce43dee4f	4723	case LSM6DSOX_YZX:
cparata	0:f27ce43dee4f	4724	*val = LSM6DSOX_YZX;
cparata	0:f27ce43dee4f	4725	break;
cparata	0:f27ce43dee4f	4726	case LSM6DSOX_ZXY:
cparata	0:f27ce43dee4f	4727	*val = LSM6DSOX_ZXY;
cparata	0:f27ce43dee4f	4728	break;
cparata	0:f27ce43dee4f	4729	default:
cparata	0:f27ce43dee4f	4730	*val = LSM6DSOX_XYZ;
cparata	0:f27ce43dee4f	4731	break;
cparata	0:f27ce43dee4f	4732	}
cparata	0:f27ce43dee4f	4733	return ret;
cparata	0:f27ce43dee4f	4734	}
cparata	0:f27ce43dee4f	4735
cparata	0:f27ce43dee4f	4736	/**
cparata	0:f27ce43dee4f	4737	* @brief Y-axis tap recognition threshold.[set]
cparata	0:f27ce43dee4f	4738	*
cparata	0:f27ce43dee4f	4739	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4740	* @param val change the values of tap_ths_y in reg TAP_CFG2
cparata	0:f27ce43dee4f	4741	*
cparata	0:f27ce43dee4f	4742	*/
cparata	0:f27ce43dee4f	4743	int32_t lsm6dsox_tap_threshold_y_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4744	{
cparata	0:f27ce43dee4f	4745	lsm6dsox_tap_cfg2_t reg;
cparata	0:f27ce43dee4f	4746	int32_t ret;
cparata	0:f27ce43dee4f	4747
cparata	0:f27ce43dee4f	4748	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4749	if (ret == 0) {
cparata	0:f27ce43dee4f	4750	reg.tap_ths_y = val;
cparata	0:f27ce43dee4f	4751	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4752	}
cparata	0:f27ce43dee4f	4753	return ret;
cparata	0:f27ce43dee4f	4754	}
cparata	0:f27ce43dee4f	4755
cparata	0:f27ce43dee4f	4756	/**
cparata	0:f27ce43dee4f	4757	* @brief Y-axis tap recognition threshold.[get]
cparata	0:f27ce43dee4f	4758	*
cparata	0:f27ce43dee4f	4759	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4760	* @param val change the values of tap_ths_y in reg TAP_CFG2
cparata	0:f27ce43dee4f	4761	*
cparata	0:f27ce43dee4f	4762	*/
cparata	0:f27ce43dee4f	4763	int32_t lsm6dsox_tap_threshold_y_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4764	{
cparata	0:f27ce43dee4f	4765	lsm6dsox_tap_cfg2_t reg;
cparata	0:f27ce43dee4f	4766	int32_t ret;
cparata	0:f27ce43dee4f	4767
cparata	0:f27ce43dee4f	4768	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4769	*val = reg.tap_ths_y;
cparata	0:f27ce43dee4f	4770
cparata	0:f27ce43dee4f	4771	return ret;
cparata	0:f27ce43dee4f	4772	}
cparata	0:f27ce43dee4f	4773
cparata	0:f27ce43dee4f	4774	/**
cparata	0:f27ce43dee4f	4775	* @brief Z-axis recognition threshold.[set]
cparata	0:f27ce43dee4f	4776	*
cparata	0:f27ce43dee4f	4777	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4778	* @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata	0:f27ce43dee4f	4779	*
cparata	0:f27ce43dee4f	4780	*/
cparata	0:f27ce43dee4f	4781	int32_t lsm6dsox_tap_threshold_z_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4782	{
cparata	0:f27ce43dee4f	4783	lsm6dsox_tap_ths_6d_t reg;
cparata	0:f27ce43dee4f	4784	int32_t ret;
cparata	0:f27ce43dee4f	4785
cparata	0:f27ce43dee4f	4786	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4787	if (ret == 0) {
cparata	0:f27ce43dee4f	4788	reg.tap_ths_z = val;
cparata	0:f27ce43dee4f	4789	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4790	}
cparata	0:f27ce43dee4f	4791	return ret;
cparata	0:f27ce43dee4f	4792	}
cparata	0:f27ce43dee4f	4793
cparata	0:f27ce43dee4f	4794	/**
cparata	0:f27ce43dee4f	4795	* @brief Z-axis recognition threshold.[get]
cparata	0:f27ce43dee4f	4796	*
cparata	0:f27ce43dee4f	4797	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4798	* @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata	0:f27ce43dee4f	4799	*
cparata	0:f27ce43dee4f	4800	*/
cparata	0:f27ce43dee4f	4801	int32_t lsm6dsox_tap_threshold_z_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4802	{
cparata	0:f27ce43dee4f	4803	lsm6dsox_tap_ths_6d_t reg;
cparata	0:f27ce43dee4f	4804	int32_t ret;
cparata	0:f27ce43dee4f	4805
cparata	0:f27ce43dee4f	4806	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4807	*val = reg.tap_ths_z;
cparata	0:f27ce43dee4f	4808
cparata	0:f27ce43dee4f	4809	return ret;
cparata	0:f27ce43dee4f	4810	}
cparata	0:f27ce43dee4f	4811
cparata	0:f27ce43dee4f	4812	/**
cparata	0:f27ce43dee4f	4813	* @brief Maximum duration is the maximum time of an
cparata	0:f27ce43dee4f	4814	* over threshold signal detection to be recognized
cparata	0:f27ce43dee4f	4815	* as a tap event. The default value of these bits
cparata	0:f27ce43dee4f	4816	* is 00b which corresponds to 4*ODR_XL time.
cparata	0:f27ce43dee4f	4817	* If the SHOCK[1:0] bits are set to a different
cparata	0:f27ce43dee4f	4818	* value, 1LSB corresponds to 8*ODR_XL time.[set]
cparata	0:f27ce43dee4f	4819	*
cparata	0:f27ce43dee4f	4820	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4821	* @param val change the values of shock in reg INT_DUR2
cparata	0:f27ce43dee4f	4822	*
cparata	0:f27ce43dee4f	4823	*/
cparata	0:f27ce43dee4f	4824	int32_t lsm6dsox_tap_shock_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4825	{
cparata	0:f27ce43dee4f	4826	lsm6dsox_int_dur2_t reg;
cparata	0:f27ce43dee4f	4827	int32_t ret;
cparata	0:f27ce43dee4f	4828
cparata	0:f27ce43dee4f	4829	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4830	if (ret == 0) {
cparata	0:f27ce43dee4f	4831	reg.shock = val;
cparata	0:f27ce43dee4f	4832	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4833	}
cparata	0:f27ce43dee4f	4834	return ret;
cparata	0:f27ce43dee4f	4835	}
cparata	0:f27ce43dee4f	4836
cparata	0:f27ce43dee4f	4837	/**
cparata	0:f27ce43dee4f	4838	* @brief Maximum duration is the maximum time of an
cparata	0:f27ce43dee4f	4839	* over threshold signal detection to be recognized
cparata	0:f27ce43dee4f	4840	* as a tap event. The default value of these bits
cparata	0:f27ce43dee4f	4841	* is 00b which corresponds to 4*ODR_XL time.
cparata	0:f27ce43dee4f	4842	* If the SHOCK[1:0] bits are set to a different
cparata	0:f27ce43dee4f	4843	* value, 1LSB corresponds to 8*ODR_XL time.[get]
cparata	0:f27ce43dee4f	4844	*
cparata	0:f27ce43dee4f	4845	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4846	* @param val change the values of shock in reg INT_DUR2
cparata	0:f27ce43dee4f	4847	*
cparata	0:f27ce43dee4f	4848	*/
cparata	0:f27ce43dee4f	4849	int32_t lsm6dsox_tap_shock_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4850	{
cparata	0:f27ce43dee4f	4851	lsm6dsox_int_dur2_t reg;
cparata	0:f27ce43dee4f	4852	int32_t ret;
cparata	0:f27ce43dee4f	4853
cparata	0:f27ce43dee4f	4854	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4855	*val = reg.shock;
cparata	0:f27ce43dee4f	4856
cparata	0:f27ce43dee4f	4857	return ret;
cparata	0:f27ce43dee4f	4858	}
cparata	0:f27ce43dee4f	4859
cparata	0:f27ce43dee4f	4860	/**
cparata	0:f27ce43dee4f	4861	* @brief Quiet time is the time after the first detected
cparata	0:f27ce43dee4f	4862	* tap in which there must not be any over threshold
cparata	0:f27ce43dee4f	4863	* event.
cparata	0:f27ce43dee4f	4864	* The default value of these bits is 00b which
cparata	0:f27ce43dee4f	4865	* corresponds to 2*ODR_XL time. If the QUIET[1:0]
cparata	0:f27ce43dee4f	4866	* bits are set to a different value,
cparata	0:f27ce43dee4f	4867	* 1LSB corresponds to 4*ODR_XL time.[set]
cparata	0:f27ce43dee4f	4868	*
cparata	0:f27ce43dee4f	4869	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4870	* @param val change the values of quiet in reg INT_DUR2
cparata	0:f27ce43dee4f	4871	*
cparata	0:f27ce43dee4f	4872	*/
cparata	0:f27ce43dee4f	4873	int32_t lsm6dsox_tap_quiet_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4874	{
cparata	0:f27ce43dee4f	4875	lsm6dsox_int_dur2_t reg;
cparata	0:f27ce43dee4f	4876	int32_t ret;
cparata	0:f27ce43dee4f	4877
cparata	0:f27ce43dee4f	4878	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4879	if (ret == 0) {
cparata	0:f27ce43dee4f	4880	reg.quiet = val;
cparata	0:f27ce43dee4f	4881	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4882	}
cparata	0:f27ce43dee4f	4883	return ret;
cparata	0:f27ce43dee4f	4884	}
cparata	0:f27ce43dee4f	4885
cparata	0:f27ce43dee4f	4886	/**
cparata	0:f27ce43dee4f	4887	* @brief Quiet time is the time after the first detected
cparata	0:f27ce43dee4f	4888	* tap in which there must not be any over threshold
cparata	0:f27ce43dee4f	4889	* event.
cparata	0:f27ce43dee4f	4890	* The default value of these bits is 00b which
cparata	0:f27ce43dee4f	4891	* corresponds to 2*ODR_XL time.
cparata	0:f27ce43dee4f	4892	* If the QUIET[1:0] bits are set to a different
cparata	0:f27ce43dee4f	4893	* value, 1LSB corresponds to 4*ODR_XL time.[get]
cparata	0:f27ce43dee4f	4894	*
cparata	0:f27ce43dee4f	4895	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4896	* @param val change the values of quiet in reg INT_DUR2
cparata	0:f27ce43dee4f	4897	*
cparata	0:f27ce43dee4f	4898	*/
cparata	0:f27ce43dee4f	4899	int32_t lsm6dsox_tap_quiet_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4900	{
cparata	0:f27ce43dee4f	4901	lsm6dsox_int_dur2_t reg;
cparata	0:f27ce43dee4f	4902	int32_t ret;
cparata	0:f27ce43dee4f	4903
cparata	0:f27ce43dee4f	4904	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4905	*val = reg.quiet;
cparata	0:f27ce43dee4f	4906
cparata	0:f27ce43dee4f	4907	return ret;
cparata	0:f27ce43dee4f	4908	}
cparata	0:f27ce43dee4f	4909
cparata	0:f27ce43dee4f	4910	/**
cparata	0:f27ce43dee4f	4911	* @brief When double tap recognition is enabled,
cparata	0:f27ce43dee4f	4912	* this register expresses the maximum time
cparata	0:f27ce43dee4f	4913	* between two consecutive detected taps to
cparata	0:f27ce43dee4f	4914	* determine a double tap event.
cparata	0:f27ce43dee4f	4915	* The default value of these bits is 0000b which
cparata	0:f27ce43dee4f	4916	* corresponds to 16*ODR_XL time.
cparata	0:f27ce43dee4f	4917	* If the DUR[3:0] bits are set to a different value,
cparata	0:f27ce43dee4f	4918	* 1LSB corresponds to 32*ODR_XL time.[set]
cparata	0:f27ce43dee4f	4919	*
cparata	0:f27ce43dee4f	4920	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4921	* @param val change the values of dur in reg INT_DUR2
cparata	0:f27ce43dee4f	4922	*
cparata	0:f27ce43dee4f	4923	*/
cparata	0:f27ce43dee4f	4924	int32_t lsm6dsox_tap_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	4925	{
cparata	0:f27ce43dee4f	4926	lsm6dsox_int_dur2_t reg;
cparata	0:f27ce43dee4f	4927	int32_t ret;
cparata	0:f27ce43dee4f	4928
cparata	0:f27ce43dee4f	4929	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4930	if (ret == 0) {
cparata	0:f27ce43dee4f	4931	reg.dur = val;
cparata	0:f27ce43dee4f	4932	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4933	}
cparata	0:f27ce43dee4f	4934	return ret;
cparata	0:f27ce43dee4f	4935	}
cparata	0:f27ce43dee4f	4936
cparata	0:f27ce43dee4f	4937	/**
cparata	0:f27ce43dee4f	4938	* @brief When double tap recognition is enabled,
cparata	0:f27ce43dee4f	4939	* this register expresses the maximum time
cparata	0:f27ce43dee4f	4940	* between two consecutive detected taps to
cparata	0:f27ce43dee4f	4941	* determine a double tap event.
cparata	0:f27ce43dee4f	4942	* The default value of these bits is 0000b which
cparata	0:f27ce43dee4f	4943	* corresponds to 16*ODR_XL time. If the DUR[3:0]
cparata	0:f27ce43dee4f	4944	* bits are set to a different value,
cparata	0:f27ce43dee4f	4945	* 1LSB corresponds to 32*ODR_XL time.[get]
cparata	0:f27ce43dee4f	4946	*
cparata	0:f27ce43dee4f	4947	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4948	* @param val change the values of dur in reg INT_DUR2
cparata	0:f27ce43dee4f	4949	*
cparata	0:f27ce43dee4f	4950	*/
cparata	0:f27ce43dee4f	4951	int32_t lsm6dsox_tap_dur_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	4952	{
cparata	0:f27ce43dee4f	4953	lsm6dsox_int_dur2_t reg;
cparata	0:f27ce43dee4f	4954	int32_t ret;
cparata	0:f27ce43dee4f	4955
cparata	0:f27ce43dee4f	4956	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4957	*val = reg.dur;
cparata	0:f27ce43dee4f	4958
cparata	0:f27ce43dee4f	4959	return ret;
cparata	0:f27ce43dee4f	4960	}
cparata	0:f27ce43dee4f	4961
cparata	0:f27ce43dee4f	4962	/**
cparata	0:f27ce43dee4f	4963	* @brief Single/double-tap event enable.[set]
cparata	0:f27ce43dee4f	4964	*
cparata	0:f27ce43dee4f	4965	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4966	* @param val change the values of single_double_tap in reg WAKE_UP_THS
cparata	0:f27ce43dee4f	4967	*
cparata	0:f27ce43dee4f	4968	*/
cparata	0:f27ce43dee4f	4969	int32_t lsm6dsox_tap_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	4970	lsm6dsox_single_double_tap_t val)
cparata	0:f27ce43dee4f	4971	{
cparata	0:f27ce43dee4f	4972	lsm6dsox_wake_up_ths_t reg;
cparata	0:f27ce43dee4f	4973	int32_t ret;
cparata	0:f27ce43dee4f	4974
cparata	0:f27ce43dee4f	4975	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4976	if (ret == 0) {
cparata	0:f27ce43dee4f	4977	reg.single_double_tap = (uint8_t)val;
cparata	0:f27ce43dee4f	4978	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4979	}
cparata	0:f27ce43dee4f	4980	return ret;
cparata	0:f27ce43dee4f	4981	}
cparata	0:f27ce43dee4f	4982
cparata	0:f27ce43dee4f	4983	/**
cparata	0:f27ce43dee4f	4984	* @brief Single/double-tap event enable.[get]
cparata	0:f27ce43dee4f	4985	*
cparata	0:f27ce43dee4f	4986	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	4987	* @param val Get the values of single_double_tap in reg WAKE_UP_THS
cparata	0:f27ce43dee4f	4988	*
cparata	0:f27ce43dee4f	4989	*/
cparata	0:f27ce43dee4f	4990	int32_t lsm6dsox_tap_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	4991	lsm6dsox_single_double_tap_t *val)
cparata	0:f27ce43dee4f	4992	{
cparata	0:f27ce43dee4f	4993	lsm6dsox_wake_up_ths_t reg;
cparata	0:f27ce43dee4f	4994	int32_t ret;
cparata	0:f27ce43dee4f	4995
cparata	0:f27ce43dee4f	4996	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	4997
cparata	0:f27ce43dee4f	4998	switch (reg.single_double_tap) {
cparata	0:f27ce43dee4f	4999	case LSM6DSOX_ONLY_SINGLE:
cparata	0:f27ce43dee4f	5000	*val = LSM6DSOX_ONLY_SINGLE;
cparata	0:f27ce43dee4f	5001	break;
cparata	0:f27ce43dee4f	5002	case LSM6DSOX_BOTH_SINGLE_DOUBLE:
cparata	0:f27ce43dee4f	5003	*val = LSM6DSOX_BOTH_SINGLE_DOUBLE;
cparata	0:f27ce43dee4f	5004	break;
cparata	0:f27ce43dee4f	5005	default:
cparata	0:f27ce43dee4f	5006	*val = LSM6DSOX_ONLY_SINGLE;
cparata	0:f27ce43dee4f	5007	break;
cparata	0:f27ce43dee4f	5008	}
cparata	0:f27ce43dee4f	5009
cparata	0:f27ce43dee4f	5010	return ret;
cparata	0:f27ce43dee4f	5011	}
cparata	0:f27ce43dee4f	5012
cparata	0:f27ce43dee4f	5013	/**
cparata	0:f27ce43dee4f	5014	* @}
cparata	0:f27ce43dee4f	5015	*
cparata	0:f27ce43dee4f	5016	*/
cparata	0:f27ce43dee4f	5017
cparata	0:f27ce43dee4f	5018	/**
cparata	0:f27ce43dee4f	5019	* @defgroup LSM6DSOX_ Six_position_detection(6D/4D)
cparata	0:f27ce43dee4f	5020	* @brief This section groups all the functions concerning six position
cparata	0:f27ce43dee4f	5021	* detection (6D).
cparata	0:f27ce43dee4f	5022	* @{
cparata	0:f27ce43dee4f	5023	*
cparata	0:f27ce43dee4f	5024	*/
cparata	0:f27ce43dee4f	5025
cparata	0:f27ce43dee4f	5026	/**
cparata	0:f27ce43dee4f	5027	* @brief Threshold for 4D/6D function.[set]
cparata	0:f27ce43dee4f	5028	*
cparata	0:f27ce43dee4f	5029	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5030	* @param val change the values of sixd_ths in reg TAP_THS_6D
cparata	0:f27ce43dee4f	5031	*
cparata	0:f27ce43dee4f	5032	*/
cparata	0:f27ce43dee4f	5033	int32_t lsm6dsox_6d_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sixd_ths_t val)
cparata	0:f27ce43dee4f	5034	{
cparata	0:f27ce43dee4f	5035	lsm6dsox_tap_ths_6d_t reg;
cparata	0:f27ce43dee4f	5036	int32_t ret;
cparata	0:f27ce43dee4f	5037
cparata	0:f27ce43dee4f	5038	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5039	if (ret == 0) {
cparata	0:f27ce43dee4f	5040	reg.sixd_ths = (uint8_t)val;
cparata	0:f27ce43dee4f	5041	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5042	}
cparata	0:f27ce43dee4f	5043	return ret;
cparata	0:f27ce43dee4f	5044	}
cparata	0:f27ce43dee4f	5045
cparata	0:f27ce43dee4f	5046	/**
cparata	0:f27ce43dee4f	5047	* @brief Threshold for 4D/6D function.[get]
cparata	0:f27ce43dee4f	5048	*
cparata	0:f27ce43dee4f	5049	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5050	* @param val Get the values of sixd_ths in reg TAP_THS_6D
cparata	0:f27ce43dee4f	5051	*
cparata	0:f27ce43dee4f	5052	*/
cparata	0:f27ce43dee4f	5053	int32_t lsm6dsox_6d_threshold_get(lsm6dsox_ctx_t ctx, lsm6dsox_sixd_ths_t val)
cparata	0:f27ce43dee4f	5054	{
cparata	0:f27ce43dee4f	5055	lsm6dsox_tap_ths_6d_t reg;
cparata	0:f27ce43dee4f	5056	int32_t ret;
cparata	0:f27ce43dee4f	5057
cparata	0:f27ce43dee4f	5058	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5059	switch (reg.sixd_ths) {
cparata	0:f27ce43dee4f	5060	case LSM6DSOX_DEG_80:
cparata	0:f27ce43dee4f	5061	*val = LSM6DSOX_DEG_80;
cparata	0:f27ce43dee4f	5062	break;
cparata	0:f27ce43dee4f	5063	case LSM6DSOX_DEG_70:
cparata	0:f27ce43dee4f	5064	*val = LSM6DSOX_DEG_70;
cparata	0:f27ce43dee4f	5065	break;
cparata	0:f27ce43dee4f	5066	case LSM6DSOX_DEG_60:
cparata	0:f27ce43dee4f	5067	*val = LSM6DSOX_DEG_60;
cparata	0:f27ce43dee4f	5068	break;
cparata	0:f27ce43dee4f	5069	case LSM6DSOX_DEG_50:
cparata	0:f27ce43dee4f	5070	*val = LSM6DSOX_DEG_50;
cparata	0:f27ce43dee4f	5071	break;
cparata	0:f27ce43dee4f	5072	default:
cparata	0:f27ce43dee4f	5073	*val = LSM6DSOX_DEG_80;
cparata	0:f27ce43dee4f	5074	break;
cparata	0:f27ce43dee4f	5075	}
cparata	0:f27ce43dee4f	5076	return ret;
cparata	0:f27ce43dee4f	5077	}
cparata	0:f27ce43dee4f	5078
cparata	0:f27ce43dee4f	5079	/**
cparata	0:f27ce43dee4f	5080	* @brief 4D orientation detection enable.[set]
cparata	0:f27ce43dee4f	5081	*
cparata	0:f27ce43dee4f	5082	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5083	* @param val change the values of d4d_en in reg TAP_THS_6D
cparata	0:f27ce43dee4f	5084	*
cparata	0:f27ce43dee4f	5085	*/
cparata	0:f27ce43dee4f	5086	int32_t lsm6dsox_4d_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	5087	{
cparata	0:f27ce43dee4f	5088	lsm6dsox_tap_ths_6d_t reg;
cparata	0:f27ce43dee4f	5089	int32_t ret;
cparata	0:f27ce43dee4f	5090
cparata	0:f27ce43dee4f	5091	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5092	if (ret == 0) {
cparata	0:f27ce43dee4f	5093	reg.d4d_en = val;
cparata	0:f27ce43dee4f	5094	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5095	}
cparata	0:f27ce43dee4f	5096	return ret;
cparata	0:f27ce43dee4f	5097	}
cparata	0:f27ce43dee4f	5098
cparata	0:f27ce43dee4f	5099	/**
cparata	0:f27ce43dee4f	5100	* @brief 4D orientation detection enable.[get]
cparata	0:f27ce43dee4f	5101	*
cparata	0:f27ce43dee4f	5102	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5103	* @param val change the values of d4d_en in reg TAP_THS_6D
cparata	0:f27ce43dee4f	5104	*
cparata	0:f27ce43dee4f	5105	*/
cparata	0:f27ce43dee4f	5106	int32_t lsm6dsox_4d_mode_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	5107	{
cparata	0:f27ce43dee4f	5108	lsm6dsox_tap_ths_6d_t reg;
cparata	0:f27ce43dee4f	5109	int32_t ret;
cparata	0:f27ce43dee4f	5110
cparata	0:f27ce43dee4f	5111	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5112	*val = reg.d4d_en;
cparata	0:f27ce43dee4f	5113
cparata	0:f27ce43dee4f	5114	return ret;
cparata	0:f27ce43dee4f	5115	}
cparata	0:f27ce43dee4f	5116
cparata	0:f27ce43dee4f	5117	/**
cparata	0:f27ce43dee4f	5118	* @}
cparata	0:f27ce43dee4f	5119	*
cparata	0:f27ce43dee4f	5120	*/
cparata	0:f27ce43dee4f	5121
cparata	0:f27ce43dee4f	5122	/**
cparata	0:f27ce43dee4f	5123	* @defgroup LSM6DSOX_free_fall
cparata	0:f27ce43dee4f	5124	* @brief This section group all the functions concerning the free
cparata	0:f27ce43dee4f	5125	* fall detection.
cparata	0:f27ce43dee4f	5126	* @{
cparata	0:f27ce43dee4f	5127	*
cparata	0:f27ce43dee4f	5128	*/
cparata	0:f27ce43dee4f	5129	/**
cparata	0:f27ce43dee4f	5130	* @brief Free fall threshold setting.[set]
cparata	0:f27ce43dee4f	5131	*
cparata	0:f27ce43dee4f	5132	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5133	* @param val change the values of ff_ths in reg FREE_FALL
cparata	0:f27ce43dee4f	5134	*
cparata	0:f27ce43dee4f	5135	*/
cparata	0:f27ce43dee4f	5136	int32_t lsm6dsox_ff_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t val)
cparata	0:f27ce43dee4f	5137	{
cparata	0:f27ce43dee4f	5138	lsm6dsox_free_fall_t reg;
cparata	0:f27ce43dee4f	5139	int32_t ret;
cparata	0:f27ce43dee4f	5140
cparata	0:f27ce43dee4f	5141	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5142	if (ret == 0) {
cparata	0:f27ce43dee4f	5143	reg.ff_ths = (uint8_t)val;
cparata	0:f27ce43dee4f	5144	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5145	}
cparata	0:f27ce43dee4f	5146	return ret;
cparata	0:f27ce43dee4f	5147	}
cparata	0:f27ce43dee4f	5148
cparata	0:f27ce43dee4f	5149	/**
cparata	0:f27ce43dee4f	5150	* @brief Free fall threshold setting.[get]
cparata	0:f27ce43dee4f	5151	*
cparata	0:f27ce43dee4f	5152	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5153	* @param val Get the values of ff_ths in reg FREE_FALL
cparata	0:f27ce43dee4f	5154	*
cparata	0:f27ce43dee4f	5155	*/
cparata	0:f27ce43dee4f	5156	int32_t lsm6dsox_ff_threshold_get(lsm6dsox_ctx_t ctx, lsm6dsox_ff_ths_t val)
cparata	0:f27ce43dee4f	5157	{
cparata	0:f27ce43dee4f	5158	lsm6dsox_free_fall_t reg;
cparata	0:f27ce43dee4f	5159	int32_t ret;
cparata	0:f27ce43dee4f	5160
cparata	0:f27ce43dee4f	5161	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5162	switch (reg.ff_ths) {
cparata	0:f27ce43dee4f	5163	case LSM6DSOX_FF_TSH_156mg:
cparata	0:f27ce43dee4f	5164	*val = LSM6DSOX_FF_TSH_156mg;
cparata	0:f27ce43dee4f	5165	break;
cparata	0:f27ce43dee4f	5166	case LSM6DSOX_FF_TSH_219mg:
cparata	0:f27ce43dee4f	5167	*val = LSM6DSOX_FF_TSH_219mg;
cparata	0:f27ce43dee4f	5168	break;
cparata	0:f27ce43dee4f	5169	case LSM6DSOX_FF_TSH_250mg:
cparata	0:f27ce43dee4f	5170	*val = LSM6DSOX_FF_TSH_250mg;
cparata	0:f27ce43dee4f	5171	break;
cparata	0:f27ce43dee4f	5172	case LSM6DSOX_FF_TSH_312mg:
cparata	0:f27ce43dee4f	5173	*val = LSM6DSOX_FF_TSH_312mg;
cparata	0:f27ce43dee4f	5174	break;
cparata	0:f27ce43dee4f	5175	case LSM6DSOX_FF_TSH_344mg:
cparata	0:f27ce43dee4f	5176	*val = LSM6DSOX_FF_TSH_344mg;
cparata	0:f27ce43dee4f	5177	break;
cparata	0:f27ce43dee4f	5178	case LSM6DSOX_FF_TSH_406mg:
cparata	0:f27ce43dee4f	5179	*val = LSM6DSOX_FF_TSH_406mg;
cparata	0:f27ce43dee4f	5180	break;
cparata	0:f27ce43dee4f	5181	case LSM6DSOX_FF_TSH_469mg:
cparata	0:f27ce43dee4f	5182	*val = LSM6DSOX_FF_TSH_469mg;
cparata	0:f27ce43dee4f	5183	break;
cparata	0:f27ce43dee4f	5184	case LSM6DSOX_FF_TSH_500mg:
cparata	0:f27ce43dee4f	5185	*val = LSM6DSOX_FF_TSH_500mg;
cparata	0:f27ce43dee4f	5186	break;
cparata	0:f27ce43dee4f	5187	default:
cparata	0:f27ce43dee4f	5188	*val = LSM6DSOX_FF_TSH_156mg;
cparata	0:f27ce43dee4f	5189	break;
cparata	0:f27ce43dee4f	5190	}
cparata	0:f27ce43dee4f	5191	return ret;
cparata	0:f27ce43dee4f	5192	}
cparata	0:f27ce43dee4f	5193
cparata	0:f27ce43dee4f	5194	/**
cparata	0:f27ce43dee4f	5195	* @brief Free-fall duration event.[set]
cparata	0:f27ce43dee4f	5196	* 1LSb = 1 / ODR
cparata	0:f27ce43dee4f	5197	*
cparata	0:f27ce43dee4f	5198	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5199	* @param val change the values of ff_dur in reg FREE_FALL
cparata	0:f27ce43dee4f	5200	*
cparata	0:f27ce43dee4f	5201	*/
cparata	0:f27ce43dee4f	5202	int32_t lsm6dsox_ff_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	5203	{
cparata	0:f27ce43dee4f	5204	lsm6dsox_wake_up_dur_t wake_up_dur;
cparata	0:f27ce43dee4f	5205	lsm6dsox_free_fall_t free_fall;
cparata	0:f27ce43dee4f	5206	int32_t ret;
cparata	0:f27ce43dee4f	5207
cparata	0:f27ce43dee4f	5208	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
cparata	0:f27ce43dee4f	5209	if (ret == 0) {
cparata	0:f27ce43dee4f	5210	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata	0:f27ce43dee4f	5211	}
cparata	0:f27ce43dee4f	5212	if (ret == 0) {
cparata	0:f27ce43dee4f	5213	wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
cparata	0:f27ce43dee4f	5214	free_fall.ff_dur = (uint8_t)val & 0x1FU;
cparata	0:f27ce43dee4f	5215	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR,
cparata	0:f27ce43dee4f	5216	(uint8_t*)&wake_up_dur, 1);
cparata	0:f27ce43dee4f	5217	}
cparata	0:f27ce43dee4f	5218	if (ret == 0) {
cparata	0:f27ce43dee4f	5219	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata	0:f27ce43dee4f	5220	}
cparata	0:f27ce43dee4f	5221	return ret;
cparata	0:f27ce43dee4f	5222	}
cparata	0:f27ce43dee4f	5223
cparata	0:f27ce43dee4f	5224	/**
cparata	0:f27ce43dee4f	5225	* @brief Free-fall duration event.[get]
cparata	0:f27ce43dee4f	5226	* 1LSb = 1 / ODR
cparata	0:f27ce43dee4f	5227	*
cparata	0:f27ce43dee4f	5228	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5229	* @param val change the values of ff_dur in reg FREE_FALL
cparata	0:f27ce43dee4f	5230	*
cparata	0:f27ce43dee4f	5231	*/
cparata	0:f27ce43dee4f	5232	int32_t lsm6dsox_ff_dur_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	5233	{
cparata	0:f27ce43dee4f	5234	lsm6dsox_wake_up_dur_t wake_up_dur;
cparata	0:f27ce43dee4f	5235	lsm6dsox_free_fall_t free_fall;
cparata	0:f27ce43dee4f	5236	int32_t ret;
cparata	0:f27ce43dee4f	5237
cparata	0:f27ce43dee4f	5238	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
cparata	0:f27ce43dee4f	5239	if (ret == 0) {
cparata	0:f27ce43dee4f	5240	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata	0:f27ce43dee4f	5241	*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
cparata	0:f27ce43dee4f	5242	}
cparata	0:f27ce43dee4f	5243	return ret;
cparata	0:f27ce43dee4f	5244	}
cparata	0:f27ce43dee4f	5245
cparata	0:f27ce43dee4f	5246	/**
cparata	0:f27ce43dee4f	5247	* @}
cparata	0:f27ce43dee4f	5248	*
cparata	0:f27ce43dee4f	5249	*/
cparata	0:f27ce43dee4f	5250
cparata	0:f27ce43dee4f	5251	/**
cparata	0:f27ce43dee4f	5252	* @defgroup LSM6DSOX_fifo
cparata	0:f27ce43dee4f	5253	* @brief This section group all the functions concerning the fifo usage
cparata	0:f27ce43dee4f	5254	* @{
cparata	0:f27ce43dee4f	5255	*
cparata	0:f27ce43dee4f	5256	*/
cparata	0:f27ce43dee4f	5257
cparata	0:f27ce43dee4f	5258	/**
cparata	0:f27ce43dee4f	5259	* @brief FIFO watermark level selection.[set]
cparata	0:f27ce43dee4f	5260	*
cparata	0:f27ce43dee4f	5261	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5262	* @param val change the values of wtm in reg FIFO_CTRL1
cparata	0:f27ce43dee4f	5263	*
cparata	0:f27ce43dee4f	5264	*/
cparata	0:f27ce43dee4f	5265	int32_t lsm6dsox_fifo_watermark_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata	0:f27ce43dee4f	5266	{
cparata	0:f27ce43dee4f	5267	lsm6dsox_fifo_ctrl1_t fifo_ctrl1;
cparata	0:f27ce43dee4f	5268	lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
cparata	0:f27ce43dee4f	5269	int32_t ret;
cparata	0:f27ce43dee4f	5270
cparata	0:f27ce43dee4f	5271	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata	0:f27ce43dee4f	5272	if (ret == 0) {
cparata	0:f27ce43dee4f	5273	fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
cparata	0:f27ce43dee4f	5274	fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
cparata	0:f27ce43dee4f	5275	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
cparata	0:f27ce43dee4f	5276	}
cparata	0:f27ce43dee4f	5277	if (ret == 0) {
cparata	0:f27ce43dee4f	5278	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata	0:f27ce43dee4f	5279	}
cparata	0:f27ce43dee4f	5280	return ret;
cparata	0:f27ce43dee4f	5281	}
cparata	0:f27ce43dee4f	5282
cparata	0:f27ce43dee4f	5283	/**
cparata	0:f27ce43dee4f	5284	* @brief FIFO watermark level selection.[get]
cparata	0:f27ce43dee4f	5285	*
cparata	0:f27ce43dee4f	5286	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5287	* @param val change the values of wtm in reg FIFO_CTRL1
cparata	0:f27ce43dee4f	5288	*
cparata	0:f27ce43dee4f	5289	*/
cparata	0:f27ce43dee4f	5290	int32_t lsm6dsox_fifo_watermark_get(lsm6dsox_ctx_t ctx, uint16_t val)
cparata	0:f27ce43dee4f	5291	{
cparata	0:f27ce43dee4f	5292	lsm6dsox_fifo_ctrl1_t fifo_ctrl1;
cparata	0:f27ce43dee4f	5293	lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
cparata	0:f27ce43dee4f	5294	int32_t ret;
cparata	0:f27ce43dee4f	5295
cparata	0:f27ce43dee4f	5296	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
cparata	0:f27ce43dee4f	5297	if (ret == 0) {
cparata	0:f27ce43dee4f	5298	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata	0:f27ce43dee4f	5299	*val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
cparata	0:f27ce43dee4f	5300	}
cparata	0:f27ce43dee4f	5301	return ret;
cparata	0:f27ce43dee4f	5302	}
cparata	0:f27ce43dee4f	5303
cparata	0:f27ce43dee4f	5304	/**
cparata	0:f27ce43dee4f	5305	* @brief FIFO compression feature initialization request [set].
cparata	0:f27ce43dee4f	5306	*
cparata	0:f27ce43dee4f	5307	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5308	* @param val change the values of FIFO_COMPR_INIT in
cparata	0:f27ce43dee4f	5309	* reg EMB_FUNC_INIT_B
cparata	0:f27ce43dee4f	5310	*
cparata	0:f27ce43dee4f	5311	*/
cparata	0:f27ce43dee4f	5312	int32_t lsm6dsox_compression_algo_init_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	5313	{
cparata	0:f27ce43dee4f	5314	lsm6dsox_emb_func_init_b_t reg;
cparata	0:f27ce43dee4f	5315	int32_t ret;
cparata	0:f27ce43dee4f	5316
cparata	0:f27ce43dee4f	5317	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	5318	if (ret == 0) {
cparata	0:f27ce43dee4f	5319	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5320	}
cparata	0:f27ce43dee4f	5321	if (ret == 0) {
cparata	0:f27ce43dee4f	5322	reg.fifo_compr_init = val;
cparata	0:f27ce43dee4f	5323	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5324	}
cparata	0:f27ce43dee4f	5325	if (ret == 0) {
cparata	0:f27ce43dee4f	5326	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	5327	}
cparata	0:f27ce43dee4f	5328
cparata	0:f27ce43dee4f	5329	return ret;
cparata	0:f27ce43dee4f	5330	}
cparata	0:f27ce43dee4f	5331
cparata	0:f27ce43dee4f	5332	/**
cparata	0:f27ce43dee4f	5333	* @brief FIFO compression feature initialization request [get].
cparata	0:f27ce43dee4f	5334	*
cparata	0:f27ce43dee4f	5335	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5336	* @param val change the values of FIFO_COMPR_INIT in
cparata	0:f27ce43dee4f	5337	* reg EMB_FUNC_INIT_B
cparata	0:f27ce43dee4f	5338	*
cparata	0:f27ce43dee4f	5339	*/
cparata	0:f27ce43dee4f	5340	int32_t lsm6dsox_compression_algo_init_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	5341	{
cparata	0:f27ce43dee4f	5342	lsm6dsox_emb_func_init_b_t reg;
cparata	0:f27ce43dee4f	5343	int32_t ret;
cparata	0:f27ce43dee4f	5344
cparata	0:f27ce43dee4f	5345	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	5346	if (ret == 0) {
cparata	0:f27ce43dee4f	5347	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5348	}
cparata	0:f27ce43dee4f	5349	if (ret == 0) {
cparata	0:f27ce43dee4f	5350	*val = reg.fifo_compr_init;
cparata	0:f27ce43dee4f	5351	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	5352	}
cparata	0:f27ce43dee4f	5353
cparata	0:f27ce43dee4f	5354	return ret;
cparata	0:f27ce43dee4f	5355	}
cparata	0:f27ce43dee4f	5356
cparata	0:f27ce43dee4f	5357	/**
cparata	0:f27ce43dee4f	5358	* @brief Enable and configure compression algo.[set]
cparata	0:f27ce43dee4f	5359	*
cparata	0:f27ce43dee4f	5360	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5361	* @param val change the values of uncoptr_rate in
cparata	0:f27ce43dee4f	5362	* reg FIFO_CTRL2
cparata	0:f27ce43dee4f	5363	*
cparata	0:f27ce43dee4f	5364	*/
cparata	0:f27ce43dee4f	5365	int32_t lsm6dsox_compression_algo_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5366	lsm6dsox_uncoptr_rate_t val)
cparata	0:f27ce43dee4f	5367	{
cparata	0:f27ce43dee4f	5368	lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
cparata	0:f27ce43dee4f	5369	int32_t ret;
cparata	0:f27ce43dee4f	5370
cparata	1:fe40aec6e97a	5371	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2,
cparata	1:fe40aec6e97a	5372	(uint8_t*)&fifo_ctrl2, 1);
cparata	0:f27ce43dee4f	5373	if (ret == 0) {
cparata	0:f27ce43dee4f	5374	fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
cparata	0:f27ce43dee4f	5375	fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
cparata	0:f27ce43dee4f	5376	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2,
cparata	0:f27ce43dee4f	5377	(uint8_t*)&fifo_ctrl2, 1);
cparata	0:f27ce43dee4f	5378	}
cparata	0:f27ce43dee4f	5379	return ret;
cparata	0:f27ce43dee4f	5380	}
cparata	0:f27ce43dee4f	5381
cparata	0:f27ce43dee4f	5382	/**
cparata	0:f27ce43dee4f	5383	* @brief Enable and configure compression algo.[get]
cparata	0:f27ce43dee4f	5384	*
cparata	0:f27ce43dee4f	5385	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5386	* @param val Get the values of uncoptr_rate in
cparata	0:f27ce43dee4f	5387	* reg FIFO_CTRL2
cparata	0:f27ce43dee4f	5388	*
cparata	0:f27ce43dee4f	5389	*/
cparata	0:f27ce43dee4f	5390	int32_t lsm6dsox_compression_algo_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5391	lsm6dsox_uncoptr_rate_t *val)
cparata	0:f27ce43dee4f	5392	{
cparata	0:f27ce43dee4f	5393	lsm6dsox_fifo_ctrl2_t reg;
cparata	0:f27ce43dee4f	5394	int32_t ret;
cparata	0:f27ce43dee4f	5395
cparata	0:f27ce43dee4f	5396	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5397
cparata	0:f27ce43dee4f	5398	switch ((reg.fifo_compr_rt_en<<2) \| reg.uncoptr_rate) {
cparata	0:f27ce43dee4f	5399	case LSM6DSOX_CMP_DISABLE:
cparata	0:f27ce43dee4f	5400	*val = LSM6DSOX_CMP_DISABLE;
cparata	0:f27ce43dee4f	5401	break;
cparata	0:f27ce43dee4f	5402	case LSM6DSOX_CMP_ALWAYS:
cparata	0:f27ce43dee4f	5403	*val = LSM6DSOX_CMP_ALWAYS;
cparata	0:f27ce43dee4f	5404	break;
cparata	0:f27ce43dee4f	5405	case LSM6DSOX_CMP_8_TO_1:
cparata	0:f27ce43dee4f	5406	*val = LSM6DSOX_CMP_8_TO_1;
cparata	0:f27ce43dee4f	5407	break;
cparata	0:f27ce43dee4f	5408	case LSM6DSOX_CMP_16_TO_1:
cparata	0:f27ce43dee4f	5409	*val = LSM6DSOX_CMP_16_TO_1;
cparata	0:f27ce43dee4f	5410	break;
cparata	0:f27ce43dee4f	5411	case LSM6DSOX_CMP_32_TO_1:
cparata	0:f27ce43dee4f	5412	*val = LSM6DSOX_CMP_32_TO_1;
cparata	0:f27ce43dee4f	5413	break;
cparata	0:f27ce43dee4f	5414	default:
cparata	0:f27ce43dee4f	5415	*val = LSM6DSOX_CMP_DISABLE;
cparata	0:f27ce43dee4f	5416	break;
cparata	0:f27ce43dee4f	5417	}
cparata	0:f27ce43dee4f	5418	return ret;
cparata	0:f27ce43dee4f	5419	}
cparata	0:f27ce43dee4f	5420
cparata	0:f27ce43dee4f	5421	/**
cparata	0:f27ce43dee4f	5422	* @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
cparata	0:f27ce43dee4f	5423	*
cparata	0:f27ce43dee4f	5424	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5425	* @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata	0:f27ce43dee4f	5426	*
cparata	0:f27ce43dee4f	5427	*/
cparata	0:f27ce43dee4f	5428	int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5429	uint8_t val)
cparata	0:f27ce43dee4f	5430	{
cparata	0:f27ce43dee4f	5431	lsm6dsox_fifo_ctrl2_t reg;
cparata	0:f27ce43dee4f	5432	int32_t ret;
cparata	0:f27ce43dee4f	5433
cparata	0:f27ce43dee4f	5434	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5435	if (ret == 0) {
cparata	0:f27ce43dee4f	5436	reg.odrchg_en = val;
cparata	0:f27ce43dee4f	5437	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5438	}
cparata	0:f27ce43dee4f	5439	return ret;
cparata	0:f27ce43dee4f	5440	}
cparata	0:f27ce43dee4f	5441
cparata	0:f27ce43dee4f	5442	/**
cparata	0:f27ce43dee4f	5443	* @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
cparata	0:f27ce43dee4f	5444	*
cparata	0:f27ce43dee4f	5445	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5446	* @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata	0:f27ce43dee4f	5447	*
cparata	0:f27ce43dee4f	5448	*/
cparata	0:f27ce43dee4f	5449	int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5450	uint8_t *val)
cparata	0:f27ce43dee4f	5451	{
cparata	0:f27ce43dee4f	5452	lsm6dsox_fifo_ctrl2_t reg;
cparata	0:f27ce43dee4f	5453	int32_t ret;
cparata	0:f27ce43dee4f	5454
cparata	0:f27ce43dee4f	5455	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5456	*val = reg.odrchg_en;
cparata	0:f27ce43dee4f	5457
cparata	0:f27ce43dee4f	5458	return ret;
cparata	0:f27ce43dee4f	5459	}
cparata	0:f27ce43dee4f	5460
cparata	0:f27ce43dee4f	5461	/**
cparata	0:f27ce43dee4f	5462	* @brief Enables/Disables compression algorithm runtime.[set]
cparata	0:f27ce43dee4f	5463	*
cparata	0:f27ce43dee4f	5464	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5465	* @param val change the values of fifo_compr_rt_en in
cparata	0:f27ce43dee4f	5466	* reg FIFO_CTRL2
cparata	0:f27ce43dee4f	5467	*
cparata	0:f27ce43dee4f	5468	*/
cparata	0:f27ce43dee4f	5469	int32_t lsm6dsox_compression_algo_real_time_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5470	uint8_t val)
cparata	0:f27ce43dee4f	5471	{
cparata	0:f27ce43dee4f	5472	lsm6dsox_fifo_ctrl2_t reg;
cparata	0:f27ce43dee4f	5473	int32_t ret;
cparata	0:f27ce43dee4f	5474
cparata	0:f27ce43dee4f	5475	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5476	if (ret == 0) {
cparata	0:f27ce43dee4f	5477	reg.fifo_compr_rt_en = val;
cparata	0:f27ce43dee4f	5478	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5479	}
cparata	0:f27ce43dee4f	5480	return ret;
cparata	0:f27ce43dee4f	5481	}
cparata	0:f27ce43dee4f	5482
cparata	0:f27ce43dee4f	5483	/**
cparata	0:f27ce43dee4f	5484	* @brief Enables/Disables compression algorithm runtime. [get]
cparata	0:f27ce43dee4f	5485	*
cparata	0:f27ce43dee4f	5486	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5487	* @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
cparata	0:f27ce43dee4f	5488	*
cparata	0:f27ce43dee4f	5489	*/
cparata	0:f27ce43dee4f	5490	int32_t lsm6dsox_compression_algo_real_time_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5491	uint8_t *val)
cparata	0:f27ce43dee4f	5492	{
cparata	0:f27ce43dee4f	5493	lsm6dsox_fifo_ctrl2_t reg;
cparata	0:f27ce43dee4f	5494	int32_t ret;
cparata	0:f27ce43dee4f	5495
cparata	0:f27ce43dee4f	5496	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5497	*val = reg.fifo_compr_rt_en;
cparata	0:f27ce43dee4f	5498
cparata	0:f27ce43dee4f	5499	return ret;
cparata	0:f27ce43dee4f	5500	}
cparata	0:f27ce43dee4f	5501
cparata	0:f27ce43dee4f	5502	/**
cparata	0:f27ce43dee4f	5503	* @brief Sensing chain FIFO stop values memorization at
cparata	0:f27ce43dee4f	5504	* threshold level.[set]
cparata	0:f27ce43dee4f	5505	*
cparata	0:f27ce43dee4f	5506	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5507	* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata	0:f27ce43dee4f	5508	*
cparata	0:f27ce43dee4f	5509	*/
cparata	0:f27ce43dee4f	5510	int32_t lsm6dsox_fifo_stop_on_wtm_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	5511	{
cparata	0:f27ce43dee4f	5512	lsm6dsox_fifo_ctrl2_t reg;
cparata	0:f27ce43dee4f	5513	int32_t ret;
cparata	0:f27ce43dee4f	5514
cparata	0:f27ce43dee4f	5515	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5516	if (ret == 0) {
cparata	0:f27ce43dee4f	5517	reg.stop_on_wtm = val;
cparata	0:f27ce43dee4f	5518	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5519	}
cparata	0:f27ce43dee4f	5520	return ret;
cparata	0:f27ce43dee4f	5521	}
cparata	0:f27ce43dee4f	5522
cparata	0:f27ce43dee4f	5523	/**
cparata	0:f27ce43dee4f	5524	* @brief Sensing chain FIFO stop values memorization at
cparata	0:f27ce43dee4f	5525	* threshold level.[get]
cparata	0:f27ce43dee4f	5526	*
cparata	0:f27ce43dee4f	5527	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5528	* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata	0:f27ce43dee4f	5529	*
cparata	0:f27ce43dee4f	5530	*/
cparata	0:f27ce43dee4f	5531	int32_t lsm6dsox_fifo_stop_on_wtm_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	5532	{
cparata	0:f27ce43dee4f	5533	lsm6dsox_fifo_ctrl2_t reg;
cparata	0:f27ce43dee4f	5534	int32_t ret;
cparata	0:f27ce43dee4f	5535
cparata	0:f27ce43dee4f	5536	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5537	*val = reg.stop_on_wtm;
cparata	0:f27ce43dee4f	5538
cparata	0:f27ce43dee4f	5539	return ret;
cparata	0:f27ce43dee4f	5540	}
cparata	0:f27ce43dee4f	5541
cparata	0:f27ce43dee4f	5542	/**
cparata	0:f27ce43dee4f	5543	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:f27ce43dee4f	5544	* for accelerometer data.[set]
cparata	0:f27ce43dee4f	5545	*
cparata	0:f27ce43dee4f	5546	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5547	* @param val change the values of bdr_xl in reg FIFO_CTRL3
cparata	0:f27ce43dee4f	5548	*
cparata	0:f27ce43dee4f	5549	*/
cparata	0:f27ce43dee4f	5550	int32_t lsm6dsox_fifo_xl_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t val)
cparata	0:f27ce43dee4f	5551	{
cparata	0:f27ce43dee4f	5552	lsm6dsox_fifo_ctrl3_t reg;
cparata	0:f27ce43dee4f	5553	int32_t ret;
cparata	0:f27ce43dee4f	5554
cparata	0:f27ce43dee4f	5555	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5556	if (ret == 0) {
cparata	0:f27ce43dee4f	5557	reg.bdr_xl = (uint8_t)val;
cparata	0:f27ce43dee4f	5558	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5559	}
cparata	0:f27ce43dee4f	5560	return ret;
cparata	0:f27ce43dee4f	5561	}
cparata	0:f27ce43dee4f	5562
cparata	0:f27ce43dee4f	5563	/**
cparata	0:f27ce43dee4f	5564	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:f27ce43dee4f	5565	* for accelerometer data.[get]
cparata	0:f27ce43dee4f	5566	*
cparata	0:f27ce43dee4f	5567	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5568	* @param val Get the values of bdr_xl in reg FIFO_CTRL3
cparata	0:f27ce43dee4f	5569	*
cparata	0:f27ce43dee4f	5570	*/
cparata	0:f27ce43dee4f	5571	int32_t lsm6dsox_fifo_xl_batch_get(lsm6dsox_ctx_t ctx, lsm6dsox_bdr_xl_t val)
cparata	0:f27ce43dee4f	5572	{
cparata	0:f27ce43dee4f	5573	lsm6dsox_fifo_ctrl3_t reg;
cparata	0:f27ce43dee4f	5574	int32_t ret;
cparata	0:f27ce43dee4f	5575
cparata	0:f27ce43dee4f	5576	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5577	switch (reg.bdr_xl) {
cparata	0:f27ce43dee4f	5578	case LSM6DSOX_XL_NOT_BATCHED:
cparata	0:f27ce43dee4f	5579	*val = LSM6DSOX_XL_NOT_BATCHED;
cparata	0:f27ce43dee4f	5580	break;
cparata	0:f27ce43dee4f	5581	case LSM6DSOX_XL_BATCHED_AT_12Hz5:
cparata	0:f27ce43dee4f	5582	*val = LSM6DSOX_XL_BATCHED_AT_12Hz5;
cparata	0:f27ce43dee4f	5583	break;
cparata	0:f27ce43dee4f	5584	case LSM6DSOX_XL_BATCHED_AT_26Hz:
cparata	0:f27ce43dee4f	5585	*val = LSM6DSOX_XL_BATCHED_AT_26Hz;
cparata	0:f27ce43dee4f	5586	break;
cparata	0:f27ce43dee4f	5587	case LSM6DSOX_XL_BATCHED_AT_52Hz:
cparata	0:f27ce43dee4f	5588	*val = LSM6DSOX_XL_BATCHED_AT_52Hz;
cparata	0:f27ce43dee4f	5589	break;
cparata	0:f27ce43dee4f	5590	case LSM6DSOX_XL_BATCHED_AT_104Hz:
cparata	0:f27ce43dee4f	5591	*val = LSM6DSOX_XL_BATCHED_AT_104Hz;
cparata	0:f27ce43dee4f	5592	break;
cparata	0:f27ce43dee4f	5593	case LSM6DSOX_XL_BATCHED_AT_208Hz:
cparata	0:f27ce43dee4f	5594	*val = LSM6DSOX_XL_BATCHED_AT_208Hz;
cparata	0:f27ce43dee4f	5595	break;
cparata	0:f27ce43dee4f	5596	case LSM6DSOX_XL_BATCHED_AT_417Hz:
cparata	0:f27ce43dee4f	5597	*val = LSM6DSOX_XL_BATCHED_AT_417Hz;
cparata	0:f27ce43dee4f	5598	break;
cparata	0:f27ce43dee4f	5599	case LSM6DSOX_XL_BATCHED_AT_833Hz:
cparata	0:f27ce43dee4f	5600	*val = LSM6DSOX_XL_BATCHED_AT_833Hz;
cparata	0:f27ce43dee4f	5601	break;
cparata	0:f27ce43dee4f	5602	case LSM6DSOX_XL_BATCHED_AT_1667Hz:
cparata	0:f27ce43dee4f	5603	*val = LSM6DSOX_XL_BATCHED_AT_1667Hz;
cparata	0:f27ce43dee4f	5604	break;
cparata	0:f27ce43dee4f	5605	case LSM6DSOX_XL_BATCHED_AT_3333Hz:
cparata	0:f27ce43dee4f	5606	*val = LSM6DSOX_XL_BATCHED_AT_3333Hz;
cparata	0:f27ce43dee4f	5607	break;
cparata	0:f27ce43dee4f	5608	case LSM6DSOX_XL_BATCHED_AT_6667Hz:
cparata	0:f27ce43dee4f	5609	*val = LSM6DSOX_XL_BATCHED_AT_6667Hz;
cparata	0:f27ce43dee4f	5610	break;
cparata	0:f27ce43dee4f	5611	case LSM6DSOX_XL_BATCHED_AT_6Hz5:
cparata	0:f27ce43dee4f	5612	*val = LSM6DSOX_XL_BATCHED_AT_6Hz5;
cparata	0:f27ce43dee4f	5613	break;
cparata	0:f27ce43dee4f	5614	default:
cparata	0:f27ce43dee4f	5615	*val = LSM6DSOX_XL_NOT_BATCHED;
cparata	0:f27ce43dee4f	5616	break;
cparata	0:f27ce43dee4f	5617	}
cparata	0:f27ce43dee4f	5618
cparata	0:f27ce43dee4f	5619	return ret;
cparata	0:f27ce43dee4f	5620	}
cparata	0:f27ce43dee4f	5621
cparata	0:f27ce43dee4f	5622	/**
cparata	0:f27ce43dee4f	5623	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:f27ce43dee4f	5624	* for gyroscope data.[set]
cparata	0:f27ce43dee4f	5625	*
cparata	0:f27ce43dee4f	5626	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5627	* @param val change the values of bdr_gy in reg FIFO_CTRL3
cparata	0:f27ce43dee4f	5628	*
cparata	0:f27ce43dee4f	5629	*/
cparata	0:f27ce43dee4f	5630	int32_t lsm6dsox_fifo_gy_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t val)
cparata	0:f27ce43dee4f	5631	{
cparata	0:f27ce43dee4f	5632	lsm6dsox_fifo_ctrl3_t reg;
cparata	0:f27ce43dee4f	5633	int32_t ret;
cparata	0:f27ce43dee4f	5634
cparata	0:f27ce43dee4f	5635	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5636	if (ret == 0) {
cparata	0:f27ce43dee4f	5637	reg.bdr_gy = (uint8_t)val;
cparata	0:f27ce43dee4f	5638	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5639	}
cparata	0:f27ce43dee4f	5640	return ret;
cparata	0:f27ce43dee4f	5641	}
cparata	0:f27ce43dee4f	5642
cparata	0:f27ce43dee4f	5643	/**
cparata	0:f27ce43dee4f	5644	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:f27ce43dee4f	5645	* for gyroscope data.[get]
cparata	0:f27ce43dee4f	5646	*
cparata	0:f27ce43dee4f	5647	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5648	* @param val Get the values of bdr_gy in reg FIFO_CTRL3
cparata	0:f27ce43dee4f	5649	*
cparata	0:f27ce43dee4f	5650	*/
cparata	0:f27ce43dee4f	5651	int32_t lsm6dsox_fifo_gy_batch_get(lsm6dsox_ctx_t ctx, lsm6dsox_bdr_gy_t val)
cparata	0:f27ce43dee4f	5652	{
cparata	0:f27ce43dee4f	5653	lsm6dsox_fifo_ctrl3_t reg;
cparata	0:f27ce43dee4f	5654	int32_t ret;
cparata	0:f27ce43dee4f	5655
cparata	0:f27ce43dee4f	5656	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5657	switch (reg.bdr_gy) {
cparata	0:f27ce43dee4f	5658	case LSM6DSOX_GY_NOT_BATCHED:
cparata	0:f27ce43dee4f	5659	*val = LSM6DSOX_GY_NOT_BATCHED;
cparata	0:f27ce43dee4f	5660	break;
cparata	0:f27ce43dee4f	5661	case LSM6DSOX_GY_BATCHED_AT_12Hz5:
cparata	0:f27ce43dee4f	5662	*val = LSM6DSOX_GY_BATCHED_AT_12Hz5;
cparata	0:f27ce43dee4f	5663	break;
cparata	0:f27ce43dee4f	5664	case LSM6DSOX_GY_BATCHED_AT_26Hz:
cparata	0:f27ce43dee4f	5665	*val = LSM6DSOX_GY_BATCHED_AT_26Hz;
cparata	0:f27ce43dee4f	5666	break;
cparata	0:f27ce43dee4f	5667	case LSM6DSOX_GY_BATCHED_AT_52Hz:
cparata	0:f27ce43dee4f	5668	*val = LSM6DSOX_GY_BATCHED_AT_52Hz;
cparata	0:f27ce43dee4f	5669	break;
cparata	0:f27ce43dee4f	5670	case LSM6DSOX_GY_BATCHED_AT_104Hz:
cparata	0:f27ce43dee4f	5671	*val = LSM6DSOX_GY_BATCHED_AT_104Hz;
cparata	0:f27ce43dee4f	5672	break;
cparata	0:f27ce43dee4f	5673	case LSM6DSOX_GY_BATCHED_AT_208Hz:
cparata	0:f27ce43dee4f	5674	*val = LSM6DSOX_GY_BATCHED_AT_208Hz;
cparata	0:f27ce43dee4f	5675	break;
cparata	0:f27ce43dee4f	5676	case LSM6DSOX_GY_BATCHED_AT_417Hz:
cparata	0:f27ce43dee4f	5677	*val = LSM6DSOX_GY_BATCHED_AT_417Hz;
cparata	0:f27ce43dee4f	5678	break;
cparata	0:f27ce43dee4f	5679	case LSM6DSOX_GY_BATCHED_AT_833Hz:
cparata	0:f27ce43dee4f	5680	*val = LSM6DSOX_GY_BATCHED_AT_833Hz;
cparata	0:f27ce43dee4f	5681	break;
cparata	0:f27ce43dee4f	5682	case LSM6DSOX_GY_BATCHED_AT_1667Hz:
cparata	0:f27ce43dee4f	5683	*val = LSM6DSOX_GY_BATCHED_AT_1667Hz;
cparata	0:f27ce43dee4f	5684	break;
cparata	0:f27ce43dee4f	5685	case LSM6DSOX_GY_BATCHED_AT_3333Hz:
cparata	0:f27ce43dee4f	5686	*val = LSM6DSOX_GY_BATCHED_AT_3333Hz;
cparata	0:f27ce43dee4f	5687	break;
cparata	0:f27ce43dee4f	5688	case LSM6DSOX_GY_BATCHED_AT_6667Hz:
cparata	0:f27ce43dee4f	5689	*val = LSM6DSOX_GY_BATCHED_AT_6667Hz;
cparata	0:f27ce43dee4f	5690	break;
cparata	0:f27ce43dee4f	5691	case LSM6DSOX_GY_BATCHED_AT_6Hz5:
cparata	0:f27ce43dee4f	5692	*val = LSM6DSOX_GY_BATCHED_AT_6Hz5;
cparata	0:f27ce43dee4f	5693	break;
cparata	0:f27ce43dee4f	5694	default:
cparata	0:f27ce43dee4f	5695	*val = LSM6DSOX_GY_NOT_BATCHED;
cparata	0:f27ce43dee4f	5696	break;
cparata	0:f27ce43dee4f	5697	}
cparata	0:f27ce43dee4f	5698	return ret;
cparata	0:f27ce43dee4f	5699	}
cparata	0:f27ce43dee4f	5700
cparata	0:f27ce43dee4f	5701	/**
cparata	0:f27ce43dee4f	5702	* @brief FIFO mode selection.[set]
cparata	0:f27ce43dee4f	5703	*
cparata	0:f27ce43dee4f	5704	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5705	* @param val change the values of fifo_mode in reg FIFO_CTRL4
cparata	0:f27ce43dee4f	5706	*
cparata	0:f27ce43dee4f	5707	*/
cparata	0:f27ce43dee4f	5708	int32_t lsm6dsox_fifo_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t val)
cparata	0:f27ce43dee4f	5709	{
cparata	0:f27ce43dee4f	5710	lsm6dsox_fifo_ctrl4_t reg;
cparata	0:f27ce43dee4f	5711	int32_t ret;
cparata	0:f27ce43dee4f	5712
cparata	0:f27ce43dee4f	5713	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5714	if (ret == 0) {
cparata	0:f27ce43dee4f	5715	reg.fifo_mode = (uint8_t)val;
cparata	0:f27ce43dee4f	5716	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5717	}
cparata	0:f27ce43dee4f	5718	return ret;
cparata	0:f27ce43dee4f	5719	}
cparata	0:f27ce43dee4f	5720
cparata	0:f27ce43dee4f	5721	/**
cparata	0:f27ce43dee4f	5722	* @brief FIFO mode selection.[get]
cparata	0:f27ce43dee4f	5723	*
cparata	0:f27ce43dee4f	5724	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5725	* @param val Get the values of fifo_mode in reg FIFO_CTRL4
cparata	0:f27ce43dee4f	5726	*
cparata	0:f27ce43dee4f	5727	*/
cparata	0:f27ce43dee4f	5728	int32_t lsm6dsox_fifo_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_fifo_mode_t val)
cparata	0:f27ce43dee4f	5729	{
cparata	0:f27ce43dee4f	5730	lsm6dsox_fifo_ctrl4_t reg;
cparata	0:f27ce43dee4f	5731	int32_t ret;
cparata	0:f27ce43dee4f	5732
cparata	0:f27ce43dee4f	5733	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5734
cparata	0:f27ce43dee4f	5735	switch (reg.fifo_mode) {
cparata	0:f27ce43dee4f	5736	case LSM6DSOX_BYPASS_MODE:
cparata	0:f27ce43dee4f	5737	*val = LSM6DSOX_BYPASS_MODE;
cparata	0:f27ce43dee4f	5738	break;
cparata	0:f27ce43dee4f	5739	case LSM6DSOX_FIFO_MODE:
cparata	0:f27ce43dee4f	5740	*val = LSM6DSOX_FIFO_MODE;
cparata	0:f27ce43dee4f	5741	break;
cparata	0:f27ce43dee4f	5742	case LSM6DSOX_STREAM_TO_FIFO_MODE:
cparata	0:f27ce43dee4f	5743	*val = LSM6DSOX_STREAM_TO_FIFO_MODE;
cparata	0:f27ce43dee4f	5744	break;
cparata	0:f27ce43dee4f	5745	case LSM6DSOX_BYPASS_TO_STREAM_MODE:
cparata	0:f27ce43dee4f	5746	*val = LSM6DSOX_BYPASS_TO_STREAM_MODE;
cparata	0:f27ce43dee4f	5747	break;
cparata	0:f27ce43dee4f	5748	case LSM6DSOX_STREAM_MODE:
cparata	0:f27ce43dee4f	5749	*val = LSM6DSOX_STREAM_MODE;
cparata	0:f27ce43dee4f	5750	break;
cparata	0:f27ce43dee4f	5751	case LSM6DSOX_BYPASS_TO_FIFO_MODE:
cparata	0:f27ce43dee4f	5752	*val = LSM6DSOX_BYPASS_TO_FIFO_MODE;
cparata	0:f27ce43dee4f	5753	break;
cparata	0:f27ce43dee4f	5754	default:
cparata	0:f27ce43dee4f	5755	*val = LSM6DSOX_BYPASS_MODE;
cparata	0:f27ce43dee4f	5756	break;
cparata	0:f27ce43dee4f	5757	}
cparata	0:f27ce43dee4f	5758	return ret;
cparata	0:f27ce43dee4f	5759	}
cparata	0:f27ce43dee4f	5760
cparata	0:f27ce43dee4f	5761	/**
cparata	0:f27ce43dee4f	5762	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:f27ce43dee4f	5763	* for temperature data.[set]
cparata	0:f27ce43dee4f	5764	*
cparata	0:f27ce43dee4f	5765	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5766	* @param val change the values of odr_t_batch in reg FIFO_CTRL4
cparata	0:f27ce43dee4f	5767	*
cparata	0:f27ce43dee4f	5768	*/
cparata	0:f27ce43dee4f	5769	int32_t lsm6dsox_fifo_temp_batch_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5770	lsm6dsox_odr_t_batch_t val)
cparata	0:f27ce43dee4f	5771	{
cparata	0:f27ce43dee4f	5772	lsm6dsox_fifo_ctrl4_t reg;
cparata	0:f27ce43dee4f	5773	int32_t ret;
cparata	0:f27ce43dee4f	5774
cparata	0:f27ce43dee4f	5775	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5776	if (ret == 0) {
cparata	0:f27ce43dee4f	5777	reg.odr_t_batch = (uint8_t)val;
cparata	0:f27ce43dee4f	5778	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5779	}
cparata	0:f27ce43dee4f	5780	return ret;
cparata	0:f27ce43dee4f	5781	}
cparata	0:f27ce43dee4f	5782
cparata	0:f27ce43dee4f	5783	/**
cparata	0:f27ce43dee4f	5784	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:f27ce43dee4f	5785	* for temperature data.[get]
cparata	0:f27ce43dee4f	5786	*
cparata	0:f27ce43dee4f	5787	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5788	* @param val Get the values of odr_t_batch in reg FIFO_CTRL4
cparata	0:f27ce43dee4f	5789	*
cparata	0:f27ce43dee4f	5790	*/
cparata	0:f27ce43dee4f	5791	int32_t lsm6dsox_fifo_temp_batch_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5792	lsm6dsox_odr_t_batch_t *val)
cparata	0:f27ce43dee4f	5793	{
cparata	0:f27ce43dee4f	5794	lsm6dsox_fifo_ctrl4_t reg;
cparata	0:f27ce43dee4f	5795	int32_t ret;
cparata	0:f27ce43dee4f	5796
cparata	0:f27ce43dee4f	5797	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5798
cparata	0:f27ce43dee4f	5799	switch (reg.odr_t_batch) {
cparata	0:f27ce43dee4f	5800	case LSM6DSOX_TEMP_NOT_BATCHED:
cparata	0:f27ce43dee4f	5801	*val = LSM6DSOX_TEMP_NOT_BATCHED;
cparata	0:f27ce43dee4f	5802	break;
cparata	0:f27ce43dee4f	5803	case LSM6DSOX_TEMP_BATCHED_AT_1Hz6:
cparata	0:f27ce43dee4f	5804	*val = LSM6DSOX_TEMP_BATCHED_AT_1Hz6;
cparata	0:f27ce43dee4f	5805	break;
cparata	0:f27ce43dee4f	5806	case LSM6DSOX_TEMP_BATCHED_AT_12Hz5:
cparata	0:f27ce43dee4f	5807	*val = LSM6DSOX_TEMP_BATCHED_AT_12Hz5;
cparata	0:f27ce43dee4f	5808	break;
cparata	0:f27ce43dee4f	5809	case LSM6DSOX_TEMP_BATCHED_AT_52Hz:
cparata	0:f27ce43dee4f	5810	*val = LSM6DSOX_TEMP_BATCHED_AT_52Hz;
cparata	0:f27ce43dee4f	5811	break;
cparata	0:f27ce43dee4f	5812	default:
cparata	0:f27ce43dee4f	5813	*val = LSM6DSOX_TEMP_NOT_BATCHED;
cparata	0:f27ce43dee4f	5814	break;
cparata	0:f27ce43dee4f	5815	}
cparata	0:f27ce43dee4f	5816	return ret;
cparata	0:f27ce43dee4f	5817	}
cparata	0:f27ce43dee4f	5818
cparata	0:f27ce43dee4f	5819	/**
cparata	0:f27ce43dee4f	5820	* @brief Selects decimation for timestamp batching in FIFO.
cparata	0:f27ce43dee4f	5821	* Writing rate will be the maximum rate between XL and
cparata	0:f27ce43dee4f	5822	* GYRO BDR divided by decimation decoder.[set]
cparata	0:f27ce43dee4f	5823	*
cparata	0:f27ce43dee4f	5824	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5825	* @param val change the values of odr_ts_batch in reg FIFO_CTRL4
cparata	0:f27ce43dee4f	5826	*
cparata	0:f27ce43dee4f	5827	*/
cparata	0:f27ce43dee4f	5828	int32_t lsm6dsox_fifo_timestamp_decimation_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5829	lsm6dsox_odr_ts_batch_t val)
cparata	0:f27ce43dee4f	5830	{
cparata	0:f27ce43dee4f	5831	lsm6dsox_fifo_ctrl4_t reg;
cparata	0:f27ce43dee4f	5832	int32_t ret;
cparata	0:f27ce43dee4f	5833
cparata	0:f27ce43dee4f	5834	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5835	if (ret == 0) {
cparata	0:f27ce43dee4f	5836	reg.odr_ts_batch = (uint8_t)val;
cparata	0:f27ce43dee4f	5837	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5838	}
cparata	0:f27ce43dee4f	5839	return ret;
cparata	0:f27ce43dee4f	5840	}
cparata	0:f27ce43dee4f	5841
cparata	0:f27ce43dee4f	5842	/**
cparata	0:f27ce43dee4f	5843	* @brief Selects decimation for timestamp batching in FIFO.
cparata	0:f27ce43dee4f	5844	* Writing rate will be the maximum rate between XL and
cparata	0:f27ce43dee4f	5845	* GYRO BDR divided by decimation decoder.[get]
cparata	0:f27ce43dee4f	5846	*
cparata	0:f27ce43dee4f	5847	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5848	* @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
cparata	0:f27ce43dee4f	5849	*
cparata	0:f27ce43dee4f	5850	*/
cparata	0:f27ce43dee4f	5851	int32_t lsm6dsox_fifo_timestamp_decimation_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5852	lsm6dsox_odr_ts_batch_t *val)
cparata	0:f27ce43dee4f	5853	{
cparata	0:f27ce43dee4f	5854	lsm6dsox_fifo_ctrl4_t reg;
cparata	0:f27ce43dee4f	5855	int32_t ret;
cparata	0:f27ce43dee4f	5856
cparata	0:f27ce43dee4f	5857	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5858	switch (reg.odr_ts_batch) {
cparata	0:f27ce43dee4f	5859	case LSM6DSOX_NO_DECIMATION:
cparata	0:f27ce43dee4f	5860	*val = LSM6DSOX_NO_DECIMATION;
cparata	0:f27ce43dee4f	5861	break;
cparata	0:f27ce43dee4f	5862	case LSM6DSOX_DEC_1:
cparata	0:f27ce43dee4f	5863	*val = LSM6DSOX_DEC_1;
cparata	0:f27ce43dee4f	5864	break;
cparata	0:f27ce43dee4f	5865	case LSM6DSOX_DEC_8:
cparata	0:f27ce43dee4f	5866	*val = LSM6DSOX_DEC_8;
cparata	0:f27ce43dee4f	5867	break;
cparata	0:f27ce43dee4f	5868	case LSM6DSOX_DEC_32:
cparata	0:f27ce43dee4f	5869	*val = LSM6DSOX_DEC_32;
cparata	0:f27ce43dee4f	5870	break;
cparata	0:f27ce43dee4f	5871	default:
cparata	0:f27ce43dee4f	5872	*val = LSM6DSOX_NO_DECIMATION;
cparata	0:f27ce43dee4f	5873	break;
cparata	0:f27ce43dee4f	5874	}
cparata	0:f27ce43dee4f	5875	return ret;
cparata	0:f27ce43dee4f	5876	}
cparata	0:f27ce43dee4f	5877
cparata	0:f27ce43dee4f	5878	/**
cparata	0:f27ce43dee4f	5879	* @brief Selects the trigger for the internal counter of batching events
cparata	0:f27ce43dee4f	5880	* between XL and gyro.[set]
cparata	0:f27ce43dee4f	5881	*
cparata	0:f27ce43dee4f	5882	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5883	* @param val change the values of trig_counter_bdr
cparata	0:f27ce43dee4f	5884	* in reg COUNTER_BDR_REG1
cparata	0:f27ce43dee4f	5885	*
cparata	0:f27ce43dee4f	5886	*/
cparata	0:f27ce43dee4f	5887	int32_t lsm6dsox_fifo_cnt_event_batch_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5888	lsm6dsox_trig_counter_bdr_t val)
cparata	0:f27ce43dee4f	5889	{
cparata	0:f27ce43dee4f	5890	lsm6dsox_counter_bdr_reg1_t reg;
cparata	0:f27ce43dee4f	5891	int32_t ret;
cparata	0:f27ce43dee4f	5892
cparata	0:f27ce43dee4f	5893	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5894	if (ret == 0) {
cparata	0:f27ce43dee4f	5895	reg.trig_counter_bdr = (uint8_t)val;
cparata	0:f27ce43dee4f	5896	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5897	}
cparata	0:f27ce43dee4f	5898	return ret;
cparata	0:f27ce43dee4f	5899	}
cparata	0:f27ce43dee4f	5900
cparata	0:f27ce43dee4f	5901	/**
cparata	0:f27ce43dee4f	5902	* @brief Selects the trigger for the internal counter of batching events
cparata	0:f27ce43dee4f	5903	* between XL and gyro.[get]
cparata	0:f27ce43dee4f	5904	*
cparata	0:f27ce43dee4f	5905	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5906	* @param val Get the values of trig_counter_bdr
cparata	0:f27ce43dee4f	5907	* in reg COUNTER_BDR_REG1
cparata	0:f27ce43dee4f	5908	*
cparata	0:f27ce43dee4f	5909	*/
cparata	0:f27ce43dee4f	5910	int32_t lsm6dsox_fifo_cnt_event_batch_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	5911	lsm6dsox_trig_counter_bdr_t *val)
cparata	0:f27ce43dee4f	5912	{
cparata	0:f27ce43dee4f	5913	lsm6dsox_counter_bdr_reg1_t reg;
cparata	0:f27ce43dee4f	5914	int32_t ret;
cparata	0:f27ce43dee4f	5915
cparata	0:f27ce43dee4f	5916	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5917	switch (reg.trig_counter_bdr) {
cparata	0:f27ce43dee4f	5918	case LSM6DSOX_XL_BATCH_EVENT:
cparata	0:f27ce43dee4f	5919	*val = LSM6DSOX_XL_BATCH_EVENT;
cparata	0:f27ce43dee4f	5920	break;
cparata	0:f27ce43dee4f	5921	case LSM6DSOX_GYRO_BATCH_EVENT:
cparata	0:f27ce43dee4f	5922	*val = LSM6DSOX_GYRO_BATCH_EVENT;
cparata	0:f27ce43dee4f	5923	break;
cparata	0:f27ce43dee4f	5924	default:
cparata	0:f27ce43dee4f	5925	*val = LSM6DSOX_XL_BATCH_EVENT;
cparata	0:f27ce43dee4f	5926	break;
cparata	0:f27ce43dee4f	5927	}
cparata	0:f27ce43dee4f	5928	return ret;
cparata	0:f27ce43dee4f	5929	}
cparata	0:f27ce43dee4f	5930
cparata	0:f27ce43dee4f	5931	/**
cparata	0:f27ce43dee4f	5932	* @brief Resets the internal counter of batching vents for a single sensor.
cparata	0:f27ce43dee4f	5933	* This bit is automatically reset to zero if it was set to ‘1’.[set]
cparata	0:f27ce43dee4f	5934	*
cparata	0:f27ce43dee4f	5935	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5936	* @param val change the values of rst_counter_bdr in
cparata	0:f27ce43dee4f	5937	* reg COUNTER_BDR_REG1
cparata	0:f27ce43dee4f	5938	*
cparata	0:f27ce43dee4f	5939	*/
cparata	0:f27ce43dee4f	5940	int32_t lsm6dsox_rst_batch_counter_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	5941	{
cparata	0:f27ce43dee4f	5942	lsm6dsox_counter_bdr_reg1_t reg;
cparata	0:f27ce43dee4f	5943	int32_t ret;
cparata	0:f27ce43dee4f	5944
cparata	0:f27ce43dee4f	5945	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5946	if (ret == 0) {
cparata	0:f27ce43dee4f	5947	reg.rst_counter_bdr = val;
cparata	0:f27ce43dee4f	5948	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5949	}
cparata	0:f27ce43dee4f	5950	return ret;
cparata	0:f27ce43dee4f	5951	}
cparata	0:f27ce43dee4f	5952
cparata	0:f27ce43dee4f	5953	/**
cparata	0:f27ce43dee4f	5954	* @brief Resets the internal counter of batching events for a single sensor.
cparata	0:f27ce43dee4f	5955	* This bit is automatically reset to zero if it was set to ‘1’.[get]
cparata	0:f27ce43dee4f	5956	*
cparata	0:f27ce43dee4f	5957	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5958	* @param val change the values of rst_counter_bdr in
cparata	0:f27ce43dee4f	5959	* reg COUNTER_BDR_REG1
cparata	0:f27ce43dee4f	5960	*
cparata	0:f27ce43dee4f	5961	*/
cparata	0:f27ce43dee4f	5962	int32_t lsm6dsox_rst_batch_counter_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	5963	{
cparata	0:f27ce43dee4f	5964	lsm6dsox_counter_bdr_reg1_t reg;
cparata	0:f27ce43dee4f	5965	int32_t ret;
cparata	0:f27ce43dee4f	5966
cparata	0:f27ce43dee4f	5967	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	5968	*val = reg.rst_counter_bdr;
cparata	0:f27ce43dee4f	5969
cparata	0:f27ce43dee4f	5970	return ret;
cparata	0:f27ce43dee4f	5971	}
cparata	0:f27ce43dee4f	5972
cparata	0:f27ce43dee4f	5973	/**
cparata	0:f27ce43dee4f	5974	* @brief Batch data rate counter.[set]
cparata	0:f27ce43dee4f	5975	*
cparata	0:f27ce43dee4f	5976	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	5977	* @param val change the values of cnt_bdr_th in
cparata	0:f27ce43dee4f	5978	* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata	0:f27ce43dee4f	5979	*
cparata	0:f27ce43dee4f	5980	*/
cparata	0:f27ce43dee4f	5981	int32_t lsm6dsox_batch_counter_threshold_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata	0:f27ce43dee4f	5982	{
cparata	0:f27ce43dee4f	5983	lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1;
cparata	0:f27ce43dee4f	5984	lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2;
cparata	0:f27ce43dee4f	5985	int32_t ret;
cparata	0:f27ce43dee4f	5986
cparata	0:f27ce43dee4f	5987	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
cparata	0:f27ce43dee4f	5988	(uint8_t*)&counter_bdr_reg1, 1);
cparata	0:f27ce43dee4f	5989	if (ret == 0) {
cparata	0:f27ce43dee4f	5990	counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
cparata	0:f27ce43dee4f	5991	counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
cparata	0:f27ce43dee4f	5992	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
cparata	0:f27ce43dee4f	5993	(uint8_t*)&counter_bdr_reg1, 1);
cparata	0:f27ce43dee4f	5994	}
cparata	0:f27ce43dee4f	5995	if (ret == 0) {
cparata	0:f27ce43dee4f	5996	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2,
cparata	0:f27ce43dee4f	5997	(uint8_t*)&counter_bdr_reg2, 1);
cparata	0:f27ce43dee4f	5998	}
cparata	0:f27ce43dee4f	5999	return ret;
cparata	0:f27ce43dee4f	6000	}
cparata	0:f27ce43dee4f	6001
cparata	0:f27ce43dee4f	6002	/**
cparata	0:f27ce43dee4f	6003	* @brief Batch data rate counter.[get]
cparata	0:f27ce43dee4f	6004	*
cparata	0:f27ce43dee4f	6005	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6006	* @param val change the values of cnt_bdr_th in
cparata	0:f27ce43dee4f	6007	* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata	0:f27ce43dee4f	6008	*
cparata	0:f27ce43dee4f	6009	*/
cparata	0:f27ce43dee4f	6010	int32_t lsm6dsox_batch_counter_threshold_get(lsm6dsox_ctx_t ctx, uint16_t val)
cparata	0:f27ce43dee4f	6011	{
cparata	0:f27ce43dee4f	6012	lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1;
cparata	0:f27ce43dee4f	6013	lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2;
cparata	0:f27ce43dee4f	6014	int32_t ret;
cparata	0:f27ce43dee4f	6015
cparata	0:f27ce43dee4f	6016	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
cparata	0:f27ce43dee4f	6017	(uint8_t*)&counter_bdr_reg1, 1);
cparata	0:f27ce43dee4f	6018	if (ret == 0) {
cparata	0:f27ce43dee4f	6019	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2,
cparata	0:f27ce43dee4f	6020	(uint8_t*)&counter_bdr_reg2, 1);
cparata	0:f27ce43dee4f	6021
cparata	0:f27ce43dee4f	6022	*val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
cparata	0:f27ce43dee4f	6023	+ (uint16_t)counter_bdr_reg2.cnt_bdr_th;
cparata	0:f27ce43dee4f	6024	}
cparata	0:f27ce43dee4f	6025
cparata	0:f27ce43dee4f	6026	return ret;
cparata	0:f27ce43dee4f	6027	}
cparata	0:f27ce43dee4f	6028
cparata	0:f27ce43dee4f	6029	/**
cparata	0:f27ce43dee4f	6030	* @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
cparata	0:f27ce43dee4f	6031	*
cparata	0:f27ce43dee4f	6032	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6033	* @param val change the values of diff_fifo in reg FIFO_STATUS1
cparata	0:f27ce43dee4f	6034	*
cparata	0:f27ce43dee4f	6035	*/
cparata	0:f27ce43dee4f	6036	int32_t lsm6dsox_fifo_data_level_get(lsm6dsox_ctx_t ctx, uint16_t val)
cparata	0:f27ce43dee4f	6037	{
cparata	0:f27ce43dee4f	6038	lsm6dsox_fifo_status1_t fifo_status1;
cparata	0:f27ce43dee4f	6039	lsm6dsox_fifo_status2_t fifo_status2;
cparata	0:f27ce43dee4f	6040	int32_t ret;
cparata	0:f27ce43dee4f	6041
cparata	0:f27ce43dee4f	6042	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1,
cparata	0:f27ce43dee4f	6043	(uint8_t*)&fifo_status1, 1);
cparata	0:f27ce43dee4f	6044	if (ret == 0) {
cparata	0:f27ce43dee4f	6045	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2,
cparata	0:f27ce43dee4f	6046	(uint8_t*)&fifo_status2, 1);
cparata	0:f27ce43dee4f	6047	*val = ((uint16_t)fifo_status2.diff_fifo << 8) +
cparata	0:f27ce43dee4f	6048	(uint16_t)fifo_status1.diff_fifo;
cparata	0:f27ce43dee4f	6049	}
cparata	0:f27ce43dee4f	6050	return ret;
cparata	0:f27ce43dee4f	6051	}
cparata	0:f27ce43dee4f	6052
cparata	0:f27ce43dee4f	6053	/**
cparata	0:f27ce43dee4f	6054	* @brief FIFO status.[get]
cparata	0:f27ce43dee4f	6055	*
cparata	0:f27ce43dee4f	6056	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6057	* @param val registers FIFO_STATUS2
cparata	0:f27ce43dee4f	6058	*
cparata	0:f27ce43dee4f	6059	*/
cparata	0:f27ce43dee4f	6060	int32_t lsm6dsox_fifo_status_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	6061	lsm6dsox_fifo_status2_t *val)
cparata	0:f27ce43dee4f	6062	{
cparata	0:f27ce43dee4f	6063	int32_t ret;
cparata	0:f27ce43dee4f	6064	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*) val, 1);
cparata	0:f27ce43dee4f	6065	return ret;
cparata	0:f27ce43dee4f	6066	}
cparata	0:f27ce43dee4f	6067
cparata	0:f27ce43dee4f	6068	/**
cparata	0:f27ce43dee4f	6069	* @brief Smart FIFO full status.[get]
cparata	0:f27ce43dee4f	6070	*
cparata	0:f27ce43dee4f	6071	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6072	* @param val change the values of fifo_full_ia in reg FIFO_STATUS2
cparata	0:f27ce43dee4f	6073	*
cparata	0:f27ce43dee4f	6074	*/
cparata	0:f27ce43dee4f	6075	int32_t lsm6dsox_fifo_full_flag_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6076	{
cparata	0:f27ce43dee4f	6077	lsm6dsox_fifo_status2_t reg;
cparata	0:f27ce43dee4f	6078	int32_t ret;
cparata	0:f27ce43dee4f	6079
cparata	0:f27ce43dee4f	6080	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6081	*val = reg.fifo_full_ia;
cparata	0:f27ce43dee4f	6082
cparata	0:f27ce43dee4f	6083	return ret;
cparata	0:f27ce43dee4f	6084	}
cparata	0:f27ce43dee4f	6085
cparata	0:f27ce43dee4f	6086	/**
cparata	0:f27ce43dee4f	6087	* @brief FIFO overrun status.[get]
cparata	0:f27ce43dee4f	6088	*
cparata	0:f27ce43dee4f	6089	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6090	* @param val change the values of fifo_over_run_latched in
cparata	0:f27ce43dee4f	6091	* reg FIFO_STATUS2
cparata	0:f27ce43dee4f	6092	*
cparata	0:f27ce43dee4f	6093	*/
cparata	0:f27ce43dee4f	6094	int32_t lsm6dsox_fifo_ovr_flag_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6095	{
cparata	0:f27ce43dee4f	6096	lsm6dsox_fifo_status2_t reg;
cparata	0:f27ce43dee4f	6097	int32_t ret;
cparata	0:f27ce43dee4f	6098
cparata	0:f27ce43dee4f	6099	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6100	*val = reg.fifo_ovr_ia;
cparata	0:f27ce43dee4f	6101
cparata	0:f27ce43dee4f	6102	return ret;
cparata	0:f27ce43dee4f	6103	}
cparata	0:f27ce43dee4f	6104
cparata	0:f27ce43dee4f	6105	/**
cparata	0:f27ce43dee4f	6106	* @brief FIFO watermark status.[get]
cparata	0:f27ce43dee4f	6107	*
cparata	0:f27ce43dee4f	6108	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6109	* @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
cparata	0:f27ce43dee4f	6110	*
cparata	0:f27ce43dee4f	6111	*/
cparata	0:f27ce43dee4f	6112	int32_t lsm6dsox_fifo_wtm_flag_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6113	{
cparata	0:f27ce43dee4f	6114	lsm6dsox_fifo_status2_t reg;
cparata	0:f27ce43dee4f	6115	int32_t ret;
cparata	0:f27ce43dee4f	6116
cparata	0:f27ce43dee4f	6117	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6118	*val = reg.fifo_wtm_ia;
cparata	0:f27ce43dee4f	6119
cparata	0:f27ce43dee4f	6120	return ret;
cparata	0:f27ce43dee4f	6121	}
cparata	0:f27ce43dee4f	6122
cparata	0:f27ce43dee4f	6123	/**
cparata	0:f27ce43dee4f	6124	* @brief Identifies the sensor in FIFO_DATA_OUT.[get]
cparata	0:f27ce43dee4f	6125	*
cparata	0:f27ce43dee4f	6126	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6127	* @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
cparata	0:f27ce43dee4f	6128	*
cparata	0:f27ce43dee4f	6129	*/
cparata	0:f27ce43dee4f	6130	int32_t lsm6dsox_fifo_sensor_tag_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	6131	lsm6dsox_fifo_tag_t *val)
cparata	0:f27ce43dee4f	6132	{
cparata	0:f27ce43dee4f	6133	lsm6dsox_fifo_data_out_tag_t reg;
cparata	0:f27ce43dee4f	6134	int32_t ret;
cparata	0:f27ce43dee4f	6135
cparata	0:f27ce43dee4f	6136	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_TAG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6137	switch (reg.tag_sensor) {
cparata	0:f27ce43dee4f	6138	case LSM6DSOX_GYRO_NC_TAG:
cparata	0:f27ce43dee4f	6139	*val = LSM6DSOX_GYRO_NC_TAG;
cparata	0:f27ce43dee4f	6140	break;
cparata	0:f27ce43dee4f	6141	case LSM6DSOX_XL_NC_TAG:
cparata	0:f27ce43dee4f	6142	*val = LSM6DSOX_XL_NC_TAG;
cparata	0:f27ce43dee4f	6143	break;
cparata	0:f27ce43dee4f	6144	case LSM6DSOX_TEMPERATURE_TAG:
cparata	0:f27ce43dee4f	6145	*val = LSM6DSOX_TEMPERATURE_TAG;
cparata	0:f27ce43dee4f	6146	break;
cparata	1:fe40aec6e97a	6147	case LSM6DSOX_TIMESTAMP_TAG:
cparata	1:fe40aec6e97a	6148	*val = LSM6DSOX_TIMESTAMP_TAG;
cparata	1:fe40aec6e97a	6149	break;
cparata	0:f27ce43dee4f	6150	case LSM6DSOX_CFG_CHANGE_TAG:
cparata	0:f27ce43dee4f	6151	*val = LSM6DSOX_CFG_CHANGE_TAG;
cparata	0:f27ce43dee4f	6152	break;
cparata	0:f27ce43dee4f	6153	case LSM6DSOX_XL_NC_T_2_TAG:
cparata	0:f27ce43dee4f	6154	*val = LSM6DSOX_XL_NC_T_2_TAG;
cparata	0:f27ce43dee4f	6155	break;
cparata	0:f27ce43dee4f	6156	case LSM6DSOX_XL_NC_T_1_TAG:
cparata	0:f27ce43dee4f	6157	*val = LSM6DSOX_XL_NC_T_1_TAG;
cparata	0:f27ce43dee4f	6158	break;
cparata	0:f27ce43dee4f	6159	case LSM6DSOX_XL_2XC_TAG:
cparata	0:f27ce43dee4f	6160	*val = LSM6DSOX_XL_2XC_TAG;
cparata	0:f27ce43dee4f	6161	break;
cparata	0:f27ce43dee4f	6162	case LSM6DSOX_XL_3XC_TAG:
cparata	0:f27ce43dee4f	6163	*val = LSM6DSOX_XL_3XC_TAG;
cparata	0:f27ce43dee4f	6164	break;
cparata	0:f27ce43dee4f	6165	case LSM6DSOX_GYRO_NC_T_2_TAG:
cparata	0:f27ce43dee4f	6166	*val = LSM6DSOX_GYRO_NC_T_2_TAG;
cparata	0:f27ce43dee4f	6167	break;
cparata	0:f27ce43dee4f	6168	case LSM6DSOX_GYRO_NC_T_1_TAG:
cparata	0:f27ce43dee4f	6169	*val = LSM6DSOX_GYRO_NC_T_1_TAG;
cparata	0:f27ce43dee4f	6170	break;
cparata	0:f27ce43dee4f	6171	case LSM6DSOX_GYRO_2XC_TAG:
cparata	0:f27ce43dee4f	6172	*val = LSM6DSOX_GYRO_2XC_TAG;
cparata	0:f27ce43dee4f	6173	break;
cparata	0:f27ce43dee4f	6174	case LSM6DSOX_GYRO_3XC_TAG:
cparata	0:f27ce43dee4f	6175	*val = LSM6DSOX_GYRO_3XC_TAG;
cparata	0:f27ce43dee4f	6176	break;
cparata	0:f27ce43dee4f	6177	case LSM6DSOX_SENSORHUB_SLAVE0_TAG:
cparata	0:f27ce43dee4f	6178	*val = LSM6DSOX_SENSORHUB_SLAVE0_TAG;
cparata	0:f27ce43dee4f	6179	break;
cparata	0:f27ce43dee4f	6180	case LSM6DSOX_SENSORHUB_SLAVE1_TAG:
cparata	0:f27ce43dee4f	6181	*val = LSM6DSOX_SENSORHUB_SLAVE1_TAG;
cparata	0:f27ce43dee4f	6182	break;
cparata	0:f27ce43dee4f	6183	case LSM6DSOX_SENSORHUB_SLAVE2_TAG:
cparata	0:f27ce43dee4f	6184	*val = LSM6DSOX_SENSORHUB_SLAVE2_TAG;
cparata	0:f27ce43dee4f	6185	break;
cparata	0:f27ce43dee4f	6186	case LSM6DSOX_SENSORHUB_SLAVE3_TAG:
cparata	0:f27ce43dee4f	6187	*val = LSM6DSOX_SENSORHUB_SLAVE3_TAG;
cparata	0:f27ce43dee4f	6188	break;
cparata	0:f27ce43dee4f	6189	case LSM6DSOX_STEP_CPUNTER_TAG:
cparata	0:f27ce43dee4f	6190	*val = LSM6DSOX_STEP_CPUNTER_TAG;
cparata	0:f27ce43dee4f	6191	break;
cparata	0:f27ce43dee4f	6192	case LSM6DSOX_GAME_ROTATION_TAG:
cparata	0:f27ce43dee4f	6193	*val = LSM6DSOX_GAME_ROTATION_TAG;
cparata	0:f27ce43dee4f	6194	break;
cparata	0:f27ce43dee4f	6195	case LSM6DSOX_GEOMAG_ROTATION_TAG:
cparata	0:f27ce43dee4f	6196	*val = LSM6DSOX_GEOMAG_ROTATION_TAG;
cparata	0:f27ce43dee4f	6197	break;
cparata	0:f27ce43dee4f	6198	case LSM6DSOX_ROTATION_TAG:
cparata	0:f27ce43dee4f	6199	*val = LSM6DSOX_ROTATION_TAG;
cparata	0:f27ce43dee4f	6200	break;
cparata	0:f27ce43dee4f	6201	case LSM6DSOX_SENSORHUB_NACK_TAG:
cparata	0:f27ce43dee4f	6202	*val = LSM6DSOX_SENSORHUB_NACK_TAG;
cparata	0:f27ce43dee4f	6203	break;
cparata	0:f27ce43dee4f	6204	default:
cparata	0:f27ce43dee4f	6205	*val = LSM6DSOX_GYRO_NC_TAG;
cparata	0:f27ce43dee4f	6206	break;
cparata	0:f27ce43dee4f	6207	}
cparata	0:f27ce43dee4f	6208	return ret;
cparata	0:f27ce43dee4f	6209	}
cparata	0:f27ce43dee4f	6210
cparata	0:f27ce43dee4f	6211	/**
cparata	0:f27ce43dee4f	6212	* @brief : Enable FIFO batching of pedometer embedded
cparata	0:f27ce43dee4f	6213	* function values.[set]
cparata	0:f27ce43dee4f	6214	*
cparata	0:f27ce43dee4f	6215	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6216	* @param val change the values of gbias_fifo_en in
cparata	0:f27ce43dee4f	6217	* reg LSM6DSOX_EMB_FUNC_FIFO_CFG
cparata	0:f27ce43dee4f	6218	*
cparata	0:f27ce43dee4f	6219	*/
cparata	0:f27ce43dee4f	6220	int32_t lsm6dsox_fifo_pedo_batch_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	6221	{
cparata	0:f27ce43dee4f	6222	lsm6dsox_emb_func_fifo_cfg_t reg;
cparata	0:f27ce43dee4f	6223	int32_t ret;
cparata	0:f27ce43dee4f	6224
cparata	0:f27ce43dee4f	6225	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	6226	if (ret == 0) {
cparata	0:f27ce43dee4f	6227	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6228	}
cparata	0:f27ce43dee4f	6229	if (ret == 0) {
cparata	0:f27ce43dee4f	6230	reg.pedo_fifo_en = val;
cparata	0:f27ce43dee4f	6231	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG,
cparata	0:f27ce43dee4f	6232	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6233	}
cparata	0:f27ce43dee4f	6234	if (ret == 0) {
cparata	0:f27ce43dee4f	6235	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6236	}
cparata	0:f27ce43dee4f	6237	return ret;
cparata	0:f27ce43dee4f	6238	}
cparata	0:f27ce43dee4f	6239
cparata	0:f27ce43dee4f	6240	/**
cparata	0:f27ce43dee4f	6241	* @brief Enable FIFO batching of pedometer embedded function values.[get]
cparata	0:f27ce43dee4f	6242	*
cparata	0:f27ce43dee4f	6243	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6244	* @param val change the values of pedo_fifo_en in
cparata	0:f27ce43dee4f	6245	* reg LSM6DSOX_EMB_FUNC_FIFO_CFG
cparata	0:f27ce43dee4f	6246	*
cparata	0:f27ce43dee4f	6247	*/
cparata	0:f27ce43dee4f	6248	int32_t lsm6dsox_fifo_pedo_batch_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6249	{
cparata	0:f27ce43dee4f	6250	lsm6dsox_emb_func_fifo_cfg_t reg;
cparata	0:f27ce43dee4f	6251	int32_t ret;
cparata	0:f27ce43dee4f	6252
cparata	0:f27ce43dee4f	6253	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	6254	if (ret == 0) {
cparata	0:f27ce43dee4f	6255	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6256	}
cparata	0:f27ce43dee4f	6257	if (ret == 0) {
cparata	0:f27ce43dee4f	6258	*val = reg.pedo_fifo_en;
cparata	0:f27ce43dee4f	6259	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6260	}
cparata	0:f27ce43dee4f	6261	return ret;
cparata	0:f27ce43dee4f	6262	}
cparata	0:f27ce43dee4f	6263
cparata	0:f27ce43dee4f	6264	/**
cparata	0:f27ce43dee4f	6265	* @brief Enable FIFO batching data of first slave.[set]
cparata	0:f27ce43dee4f	6266	*
cparata	0:f27ce43dee4f	6267	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6268	* @param val change the values of batch_ext_sens_0_en in
cparata	0:f27ce43dee4f	6269	* reg SLV0_CONFIG
cparata	0:f27ce43dee4f	6270	*
cparata	0:f27ce43dee4f	6271	*/
cparata	0:f27ce43dee4f	6272	int32_t lsm6dsox_sh_batch_slave_0_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	6273	{
cparata	0:f27ce43dee4f	6274	lsm6dsox_slv0_config_t reg;
cparata	0:f27ce43dee4f	6275	int32_t ret;
cparata	0:f27ce43dee4f	6276
cparata	0:f27ce43dee4f	6277	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	6278	if (ret == 0) {
cparata	0:f27ce43dee4f	6279	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6280	}
cparata	0:f27ce43dee4f	6281	if (ret == 0) {
cparata	0:f27ce43dee4f	6282	reg.batch_ext_sens_0_en = val;
cparata	0:f27ce43dee4f	6283	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6284	}
cparata	0:f27ce43dee4f	6285	if (ret == 0) {
cparata	0:f27ce43dee4f	6286	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6287	}
cparata	0:f27ce43dee4f	6288	return ret;
cparata	0:f27ce43dee4f	6289	}
cparata	0:f27ce43dee4f	6290
cparata	0:f27ce43dee4f	6291	/**
cparata	0:f27ce43dee4f	6292	* @brief Enable FIFO batching data of first slave.[get]
cparata	0:f27ce43dee4f	6293	*
cparata	0:f27ce43dee4f	6294	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6295	* @param val change the values of batch_ext_sens_0_en in
cparata	0:f27ce43dee4f	6296	* reg SLV0_CONFIG
cparata	0:f27ce43dee4f	6297	*
cparata	0:f27ce43dee4f	6298	*/
cparata	0:f27ce43dee4f	6299	int32_t lsm6dsox_sh_batch_slave_0_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6300	{
cparata	0:f27ce43dee4f	6301	lsm6dsox_slv0_config_t reg;
cparata	0:f27ce43dee4f	6302	int32_t ret;
cparata	0:f27ce43dee4f	6303
cparata	0:f27ce43dee4f	6304	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	6305	if (ret == 0) {
cparata	0:f27ce43dee4f	6306	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6307	}
cparata	0:f27ce43dee4f	6308	if (ret == 0) {
cparata	0:f27ce43dee4f	6309	*val = reg.batch_ext_sens_0_en;
cparata	0:f27ce43dee4f	6310	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6311	}
cparata	0:f27ce43dee4f	6312	return ret;
cparata	0:f27ce43dee4f	6313	}
cparata	0:f27ce43dee4f	6314
cparata	0:f27ce43dee4f	6315	/**
cparata	0:f27ce43dee4f	6316	* @brief Enable FIFO batching data of second slave.[set]
cparata	0:f27ce43dee4f	6317	*
cparata	0:f27ce43dee4f	6318	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6319	* @param val change the values of batch_ext_sens_1_en in
cparata	0:f27ce43dee4f	6320	* reg SLV1_CONFIG
cparata	0:f27ce43dee4f	6321	*
cparata	0:f27ce43dee4f	6322	*/
cparata	0:f27ce43dee4f	6323	int32_t lsm6dsox_sh_batch_slave_1_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	6324	{
cparata	0:f27ce43dee4f	6325	lsm6dsox_slv1_config_t reg;
cparata	0:f27ce43dee4f	6326	int32_t ret;
cparata	0:f27ce43dee4f	6327
cparata	0:f27ce43dee4f	6328	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	6329	if (ret == 0) {
cparata	0:f27ce43dee4f	6330	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6331	}
cparata	0:f27ce43dee4f	6332	if (ret == 0) {
cparata	0:f27ce43dee4f	6333	reg.batch_ext_sens_1_en = val;
cparata	0:f27ce43dee4f	6334	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6335	}
cparata	0:f27ce43dee4f	6336	if (ret == 0) {
cparata	0:f27ce43dee4f	6337	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6338	}
cparata	0:f27ce43dee4f	6339
cparata	0:f27ce43dee4f	6340	return ret;
cparata	0:f27ce43dee4f	6341	}
cparata	0:f27ce43dee4f	6342
cparata	0:f27ce43dee4f	6343	/**
cparata	0:f27ce43dee4f	6344	* @brief Enable FIFO batching data of second slave.[get]
cparata	0:f27ce43dee4f	6345	*
cparata	0:f27ce43dee4f	6346	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6347	* @param val change the values of batch_ext_sens_1_en in
cparata	0:f27ce43dee4f	6348	* reg SLV1_CONFIG
cparata	0:f27ce43dee4f	6349	*
cparata	0:f27ce43dee4f	6350	*/
cparata	0:f27ce43dee4f	6351	int32_t lsm6dsox_sh_batch_slave_1_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6352	{
cparata	0:f27ce43dee4f	6353	lsm6dsox_slv1_config_t reg;
cparata	0:f27ce43dee4f	6354	int32_t ret;
cparata	0:f27ce43dee4f	6355
cparata	0:f27ce43dee4f	6356	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	6357	if (ret == 0) {
cparata	0:f27ce43dee4f	6358	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6359	*val = reg.batch_ext_sens_1_en;
cparata	0:f27ce43dee4f	6360	}
cparata	0:f27ce43dee4f	6361	if (ret == 0) {
cparata	0:f27ce43dee4f	6362	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6363	}
cparata	0:f27ce43dee4f	6364	return ret;
cparata	0:f27ce43dee4f	6365	}
cparata	0:f27ce43dee4f	6366
cparata	0:f27ce43dee4f	6367	/**
cparata	0:f27ce43dee4f	6368	* @brief Enable FIFO batching data of third slave.[set]
cparata	0:f27ce43dee4f	6369	*
cparata	0:f27ce43dee4f	6370	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6371	* @param val change the values of batch_ext_sens_2_en in
cparata	0:f27ce43dee4f	6372	* reg SLV2_CONFIG
cparata	0:f27ce43dee4f	6373	*
cparata	0:f27ce43dee4f	6374	*/
cparata	0:f27ce43dee4f	6375	int32_t lsm6dsox_sh_batch_slave_2_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	6376	{
cparata	0:f27ce43dee4f	6377	lsm6dsox_slv2_config_t reg;
cparata	0:f27ce43dee4f	6378	int32_t ret;
cparata	0:f27ce43dee4f	6379
cparata	0:f27ce43dee4f	6380	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	6381
cparata	0:f27ce43dee4f	6382	if (ret == 0) {
cparata	0:f27ce43dee4f	6383	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6384	}
cparata	0:f27ce43dee4f	6385	if (ret == 0) {
cparata	0:f27ce43dee4f	6386	reg.batch_ext_sens_2_en = val;
cparata	0:f27ce43dee4f	6387	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6388	}
cparata	0:f27ce43dee4f	6389	if (ret == 0) {
cparata	0:f27ce43dee4f	6390	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6391	}
cparata	0:f27ce43dee4f	6392	return ret;
cparata	0:f27ce43dee4f	6393	}
cparata	0:f27ce43dee4f	6394
cparata	0:f27ce43dee4f	6395	/**
cparata	0:f27ce43dee4f	6396	* @brief Enable FIFO batching data of third slave.[get]
cparata	0:f27ce43dee4f	6397	*
cparata	0:f27ce43dee4f	6398	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6399	* @param val change the values of batch_ext_sens_2_en in
cparata	0:f27ce43dee4f	6400	* reg SLV2_CONFIG
cparata	0:f27ce43dee4f	6401	*
cparata	0:f27ce43dee4f	6402	*/
cparata	0:f27ce43dee4f	6403	int32_t lsm6dsox_sh_batch_slave_2_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6404	{
cparata	0:f27ce43dee4f	6405	lsm6dsox_slv2_config_t reg;
cparata	0:f27ce43dee4f	6406	int32_t ret;
cparata	0:f27ce43dee4f	6407
cparata	0:f27ce43dee4f	6408	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	6409	if (ret == 0) {
cparata	0:f27ce43dee4f	6410	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6411	}
cparata	0:f27ce43dee4f	6412	if (ret == 0) {
cparata	0:f27ce43dee4f	6413	*val = reg.batch_ext_sens_2_en;
cparata	0:f27ce43dee4f	6414	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6415	}
cparata	0:f27ce43dee4f	6416
cparata	0:f27ce43dee4f	6417	return ret;
cparata	0:f27ce43dee4f	6418	}
cparata	0:f27ce43dee4f	6419
cparata	0:f27ce43dee4f	6420	/**
cparata	0:f27ce43dee4f	6421	* @brief Enable FIFO batching data of fourth slave.[set]
cparata	0:f27ce43dee4f	6422	*
cparata	0:f27ce43dee4f	6423	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6424	* @param val change the values of batch_ext_sens_3_en
cparata	0:f27ce43dee4f	6425	* in reg SLV3_CONFIG
cparata	0:f27ce43dee4f	6426	*
cparata	0:f27ce43dee4f	6427	*/
cparata	0:f27ce43dee4f	6428	int32_t lsm6dsox_sh_batch_slave_3_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	6429	{
cparata	0:f27ce43dee4f	6430	lsm6dsox_slv3_config_t reg;
cparata	0:f27ce43dee4f	6431	int32_t ret;
cparata	0:f27ce43dee4f	6432
cparata	0:f27ce43dee4f	6433	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	6434	if (ret == 0) {
cparata	0:f27ce43dee4f	6435	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6436	}
cparata	0:f27ce43dee4f	6437	if (ret == 0) {
cparata	0:f27ce43dee4f	6438	reg.batch_ext_sens_3_en = val;
cparata	0:f27ce43dee4f	6439	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6440	}
cparata	0:f27ce43dee4f	6441	if (ret == 0) {
cparata	0:f27ce43dee4f	6442	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6443	}
cparata	0:f27ce43dee4f	6444
cparata	0:f27ce43dee4f	6445	return ret;
cparata	0:f27ce43dee4f	6446	}
cparata	0:f27ce43dee4f	6447
cparata	0:f27ce43dee4f	6448	/**
cparata	0:f27ce43dee4f	6449	* @brief Enable FIFO batching data of fourth slave.[get]
cparata	0:f27ce43dee4f	6450	*
cparata	0:f27ce43dee4f	6451	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6452	* @param val change the values of batch_ext_sens_3_en in
cparata	0:f27ce43dee4f	6453	* reg SLV3_CONFIG
cparata	0:f27ce43dee4f	6454	*
cparata	0:f27ce43dee4f	6455	*/
cparata	0:f27ce43dee4f	6456	int32_t lsm6dsox_sh_batch_slave_3_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6457	{
cparata	0:f27ce43dee4f	6458	lsm6dsox_slv3_config_t reg;
cparata	0:f27ce43dee4f	6459	int32_t ret;
cparata	0:f27ce43dee4f	6460
cparata	0:f27ce43dee4f	6461	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	6462	if (ret == 0) {
cparata	0:f27ce43dee4f	6463	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6464	}
cparata	0:f27ce43dee4f	6465	if (ret == 0) {
cparata	0:f27ce43dee4f	6466	*val = reg.batch_ext_sens_3_en;
cparata	0:f27ce43dee4f	6467	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6468	}
cparata	0:f27ce43dee4f	6469
cparata	0:f27ce43dee4f	6470	return ret;
cparata	0:f27ce43dee4f	6471	}
cparata	0:f27ce43dee4f	6472
cparata	0:f27ce43dee4f	6473	/**
cparata	0:f27ce43dee4f	6474	* @}
cparata	0:f27ce43dee4f	6475	*
cparata	0:f27ce43dee4f	6476	*/
cparata	0:f27ce43dee4f	6477
cparata	0:f27ce43dee4f	6478	/**
cparata	0:f27ce43dee4f	6479	* @defgroup LSM6DSOX_DEN_functionality
cparata	0:f27ce43dee4f	6480	* @brief This section groups all the functions concerning
cparata	0:f27ce43dee4f	6481	* DEN functionality.
cparata	0:f27ce43dee4f	6482	* @{
cparata	0:f27ce43dee4f	6483	*
cparata	0:f27ce43dee4f	6484	*/
cparata	0:f27ce43dee4f	6485
cparata	0:f27ce43dee4f	6486	/**
cparata	0:f27ce43dee4f	6487	* @brief DEN functionality marking mode.[set]
cparata	0:f27ce43dee4f	6488	*
cparata	0:f27ce43dee4f	6489	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6490	* @param val change the values of den_mode in reg CTRL6_C
cparata	0:f27ce43dee4f	6491	*
cparata	0:f27ce43dee4f	6492	*/
cparata	0:f27ce43dee4f	6493	int32_t lsm6dsox_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t val)
cparata	0:f27ce43dee4f	6494	{
cparata	0:f27ce43dee4f	6495	lsm6dsox_ctrl6_c_t reg;
cparata	0:f27ce43dee4f	6496	int32_t ret;
cparata	0:f27ce43dee4f	6497
cparata	0:f27ce43dee4f	6498	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6499	if (ret == 0) {
cparata	0:f27ce43dee4f	6500	reg.den_mode = (uint8_t)val;
cparata	0:f27ce43dee4f	6501	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6502	}
cparata	0:f27ce43dee4f	6503
cparata	0:f27ce43dee4f	6504	return ret;
cparata	0:f27ce43dee4f	6505	}
cparata	0:f27ce43dee4f	6506
cparata	0:f27ce43dee4f	6507	/**
cparata	0:f27ce43dee4f	6508	* @brief DEN functionality marking mode.[get]
cparata	0:f27ce43dee4f	6509	*
cparata	0:f27ce43dee4f	6510	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6511	* @param val Get the values of den_mode in reg CTRL6_C
cparata	0:f27ce43dee4f	6512	*
cparata	0:f27ce43dee4f	6513	*/
cparata	0:f27ce43dee4f	6514	int32_t lsm6dsox_den_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_den_mode_t val)
cparata	0:f27ce43dee4f	6515	{
cparata	0:f27ce43dee4f	6516	lsm6dsox_ctrl6_c_t reg;
cparata	0:f27ce43dee4f	6517	int32_t ret;
cparata	0:f27ce43dee4f	6518
cparata	0:f27ce43dee4f	6519	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6520
cparata	0:f27ce43dee4f	6521	switch (reg.den_mode) {
cparata	0:f27ce43dee4f	6522	case LSM6DSOX_DEN_DISABLE:
cparata	0:f27ce43dee4f	6523	*val = LSM6DSOX_DEN_DISABLE;
cparata	0:f27ce43dee4f	6524	break;
cparata	0:f27ce43dee4f	6525	case LSM6DSOX_LEVEL_FIFO:
cparata	0:f27ce43dee4f	6526	*val = LSM6DSOX_LEVEL_FIFO;
cparata	0:f27ce43dee4f	6527	break;
cparata	0:f27ce43dee4f	6528	case LSM6DSOX_LEVEL_LETCHED:
cparata	0:f27ce43dee4f	6529	*val = LSM6DSOX_LEVEL_LETCHED;
cparata	0:f27ce43dee4f	6530	break;
cparata	0:f27ce43dee4f	6531	case LSM6DSOX_LEVEL_TRIGGER:
cparata	0:f27ce43dee4f	6532	*val = LSM6DSOX_LEVEL_TRIGGER;
cparata	0:f27ce43dee4f	6533	break;
cparata	0:f27ce43dee4f	6534	case LSM6DSOX_EDGE_TRIGGER:
cparata	0:f27ce43dee4f	6535	*val = LSM6DSOX_EDGE_TRIGGER;
cparata	0:f27ce43dee4f	6536	break;
cparata	0:f27ce43dee4f	6537	default:
cparata	0:f27ce43dee4f	6538	*val = LSM6DSOX_DEN_DISABLE;
cparata	0:f27ce43dee4f	6539	break;
cparata	0:f27ce43dee4f	6540	}
cparata	0:f27ce43dee4f	6541	return ret;
cparata	0:f27ce43dee4f	6542	}
cparata	0:f27ce43dee4f	6543
cparata	0:f27ce43dee4f	6544	/**
cparata	0:f27ce43dee4f	6545	* @brief DEN active level configuration.[set]
cparata	0:f27ce43dee4f	6546	*
cparata	0:f27ce43dee4f	6547	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6548	* @param val change the values of den_lh in reg CTRL9_XL
cparata	0:f27ce43dee4f	6549	*
cparata	0:f27ce43dee4f	6550	*/
cparata	0:f27ce43dee4f	6551	int32_t lsm6dsox_den_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t val)
cparata	0:f27ce43dee4f	6552	{
cparata	0:f27ce43dee4f	6553	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6554	int32_t ret;
cparata	0:f27ce43dee4f	6555
cparata	0:f27ce43dee4f	6556	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6557	if (ret == 0) {
cparata	0:f27ce43dee4f	6558	reg.den_lh = (uint8_t)val;
cparata	0:f27ce43dee4f	6559	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6560	}
cparata	0:f27ce43dee4f	6561
cparata	0:f27ce43dee4f	6562	return ret;
cparata	0:f27ce43dee4f	6563	}
cparata	0:f27ce43dee4f	6564
cparata	0:f27ce43dee4f	6565	/**
cparata	0:f27ce43dee4f	6566	* @brief DEN active level configuration.[get]
cparata	0:f27ce43dee4f	6567	*
cparata	0:f27ce43dee4f	6568	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6569	* @param val Get the values of den_lh in reg CTRL9_XL
cparata	0:f27ce43dee4f	6570	*
cparata	0:f27ce43dee4f	6571	*/
cparata	0:f27ce43dee4f	6572	int32_t lsm6dsox_den_polarity_get(lsm6dsox_ctx_t ctx, lsm6dsox_den_lh_t val)
cparata	0:f27ce43dee4f	6573	{
cparata	0:f27ce43dee4f	6574	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6575	int32_t ret;
cparata	0:f27ce43dee4f	6576
cparata	0:f27ce43dee4f	6577	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6578
cparata	0:f27ce43dee4f	6579	switch (reg.den_lh) {
cparata	0:f27ce43dee4f	6580	case LSM6DSOX_DEN_ACT_LOW:
cparata	0:f27ce43dee4f	6581	*val = LSM6DSOX_DEN_ACT_LOW;
cparata	0:f27ce43dee4f	6582	break;
cparata	0:f27ce43dee4f	6583	case LSM6DSOX_DEN_ACT_HIGH:
cparata	0:f27ce43dee4f	6584	*val = LSM6DSOX_DEN_ACT_HIGH;
cparata	0:f27ce43dee4f	6585	break;
cparata	0:f27ce43dee4f	6586	default:
cparata	0:f27ce43dee4f	6587	*val = LSM6DSOX_DEN_ACT_LOW;
cparata	0:f27ce43dee4f	6588	break;
cparata	0:f27ce43dee4f	6589	}
cparata	0:f27ce43dee4f	6590	return ret;
cparata	0:f27ce43dee4f	6591	}
cparata	0:f27ce43dee4f	6592
cparata	0:f27ce43dee4f	6593	/**
cparata	0:f27ce43dee4f	6594	* @brief DEN enable.[set]
cparata	0:f27ce43dee4f	6595	*
cparata	0:f27ce43dee4f	6596	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6597	* @param val change the values of den_xl_g in reg CTRL9_XL
cparata	0:f27ce43dee4f	6598	*
cparata	0:f27ce43dee4f	6599	*/
cparata	0:f27ce43dee4f	6600	int32_t lsm6dsox_den_enable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t val)
cparata	0:f27ce43dee4f	6601	{
cparata	0:f27ce43dee4f	6602	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6603	int32_t ret;
cparata	0:f27ce43dee4f	6604
cparata	0:f27ce43dee4f	6605	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6606	if (ret == 0) {
cparata	0:f27ce43dee4f	6607	reg.den_xl_g = (uint8_t)val;
cparata	0:f27ce43dee4f	6608	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6609	}
cparata	0:f27ce43dee4f	6610
cparata	0:f27ce43dee4f	6611	return ret;
cparata	0:f27ce43dee4f	6612	}
cparata	0:f27ce43dee4f	6613
cparata	0:f27ce43dee4f	6614	/**
cparata	0:f27ce43dee4f	6615	* @brief DEN enable.[get]
cparata	0:f27ce43dee4f	6616	*
cparata	0:f27ce43dee4f	6617	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6618	* @param val Get the values of den_xl_g in reg CTRL9_XL
cparata	0:f27ce43dee4f	6619	*
cparata	0:f27ce43dee4f	6620	*/
cparata	0:f27ce43dee4f	6621	int32_t lsm6dsox_den_enable_get(lsm6dsox_ctx_t ctx, lsm6dsox_den_xl_g_t val)
cparata	0:f27ce43dee4f	6622	{
cparata	0:f27ce43dee4f	6623	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6624	int32_t ret;
cparata	0:f27ce43dee4f	6625
cparata	0:f27ce43dee4f	6626	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6627
cparata	0:f27ce43dee4f	6628	switch (reg.den_xl_g) {
cparata	0:f27ce43dee4f	6629	case LSM6DSOX_STAMP_IN_GY_DATA:
cparata	0:f27ce43dee4f	6630	*val = LSM6DSOX_STAMP_IN_GY_DATA;
cparata	0:f27ce43dee4f	6631	break;
cparata	0:f27ce43dee4f	6632	case LSM6DSOX_STAMP_IN_XL_DATA:
cparata	0:f27ce43dee4f	6633	*val = LSM6DSOX_STAMP_IN_XL_DATA;
cparata	0:f27ce43dee4f	6634	break;
cparata	0:f27ce43dee4f	6635	case LSM6DSOX_STAMP_IN_GY_XL_DATA:
cparata	0:f27ce43dee4f	6636	*val = LSM6DSOX_STAMP_IN_GY_XL_DATA;
cparata	0:f27ce43dee4f	6637	break;
cparata	0:f27ce43dee4f	6638	default:
cparata	0:f27ce43dee4f	6639	*val = LSM6DSOX_STAMP_IN_GY_DATA;
cparata	0:f27ce43dee4f	6640	break;
cparata	0:f27ce43dee4f	6641	}
cparata	0:f27ce43dee4f	6642	return ret;
cparata	0:f27ce43dee4f	6643	}
cparata	0:f27ce43dee4f	6644
cparata	0:f27ce43dee4f	6645	/**
cparata	0:f27ce43dee4f	6646	* @brief DEN value stored in LSB of X-axis.[set]
cparata	0:f27ce43dee4f	6647	*
cparata	0:f27ce43dee4f	6648	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6649	* @param val change the values of den_z in reg CTRL9_XL
cparata	0:f27ce43dee4f	6650	*
cparata	0:f27ce43dee4f	6651	*/
cparata	0:f27ce43dee4f	6652	int32_t lsm6dsox_den_mark_axis_x_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	6653	{
cparata	0:f27ce43dee4f	6654	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6655	int32_t ret;
cparata	0:f27ce43dee4f	6656
cparata	0:f27ce43dee4f	6657	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6658	if (ret == 0) {
cparata	0:f27ce43dee4f	6659	reg.den_z = val;
cparata	0:f27ce43dee4f	6660	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6661	}
cparata	0:f27ce43dee4f	6662
cparata	0:f27ce43dee4f	6663	return ret;
cparata	0:f27ce43dee4f	6664	}
cparata	0:f27ce43dee4f	6665
cparata	0:f27ce43dee4f	6666	/**
cparata	0:f27ce43dee4f	6667	* @brief DEN value stored in LSB of X-axis.[get]
cparata	0:f27ce43dee4f	6668	*
cparata	0:f27ce43dee4f	6669	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6670	* @param val change the values of den_z in reg CTRL9_XL
cparata	0:f27ce43dee4f	6671	*
cparata	0:f27ce43dee4f	6672	*/
cparata	0:f27ce43dee4f	6673	int32_t lsm6dsox_den_mark_axis_x_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6674	{
cparata	0:f27ce43dee4f	6675	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6676	int32_t ret;
cparata	0:f27ce43dee4f	6677
cparata	0:f27ce43dee4f	6678	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6679	*val = reg.den_z;
cparata	0:f27ce43dee4f	6680
cparata	0:f27ce43dee4f	6681	return ret;
cparata	0:f27ce43dee4f	6682	}
cparata	0:f27ce43dee4f	6683
cparata	0:f27ce43dee4f	6684	/**
cparata	0:f27ce43dee4f	6685	* @brief DEN value stored in LSB of Y-axis.[set]
cparata	0:f27ce43dee4f	6686	*
cparata	0:f27ce43dee4f	6687	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6688	* @param val change the values of den_y in reg CTRL9_XL
cparata	0:f27ce43dee4f	6689	*
cparata	0:f27ce43dee4f	6690	*/
cparata	0:f27ce43dee4f	6691	int32_t lsm6dsox_den_mark_axis_y_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	6692	{
cparata	0:f27ce43dee4f	6693	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6694	int32_t ret;
cparata	0:f27ce43dee4f	6695
cparata	0:f27ce43dee4f	6696	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6697	if (ret == 0) {
cparata	0:f27ce43dee4f	6698	reg.den_y = val;
cparata	0:f27ce43dee4f	6699	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6700	}
cparata	0:f27ce43dee4f	6701
cparata	0:f27ce43dee4f	6702	return ret;
cparata	0:f27ce43dee4f	6703	}
cparata	0:f27ce43dee4f	6704
cparata	0:f27ce43dee4f	6705	/**
cparata	0:f27ce43dee4f	6706	* @brief DEN value stored in LSB of Y-axis.[get]
cparata	0:f27ce43dee4f	6707	*
cparata	0:f27ce43dee4f	6708	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6709	* @param val change the values of den_y in reg CTRL9_XL
cparata	0:f27ce43dee4f	6710	*
cparata	0:f27ce43dee4f	6711	*/
cparata	0:f27ce43dee4f	6712	int32_t lsm6dsox_den_mark_axis_y_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6713	{
cparata	0:f27ce43dee4f	6714	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6715	int32_t ret;
cparata	0:f27ce43dee4f	6716
cparata	0:f27ce43dee4f	6717	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6718	*val = reg.den_y;
cparata	0:f27ce43dee4f	6719
cparata	0:f27ce43dee4f	6720	return ret;
cparata	0:f27ce43dee4f	6721	}
cparata	0:f27ce43dee4f	6722
cparata	0:f27ce43dee4f	6723	/**
cparata	0:f27ce43dee4f	6724	* @brief DEN value stored in LSB of Z-axis.[set]
cparata	0:f27ce43dee4f	6725	*
cparata	0:f27ce43dee4f	6726	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6727	* @param val change the values of den_x in reg CTRL9_XL
cparata	0:f27ce43dee4f	6728	*
cparata	0:f27ce43dee4f	6729	*/
cparata	0:f27ce43dee4f	6730	int32_t lsm6dsox_den_mark_axis_z_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	6731	{
cparata	0:f27ce43dee4f	6732	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6733	int32_t ret;
cparata	0:f27ce43dee4f	6734
cparata	0:f27ce43dee4f	6735	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6736	if (ret == 0) {
cparata	0:f27ce43dee4f	6737	reg.den_x = val;
cparata	0:f27ce43dee4f	6738	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6739	}
cparata	0:f27ce43dee4f	6740
cparata	0:f27ce43dee4f	6741	return ret;
cparata	0:f27ce43dee4f	6742	}
cparata	0:f27ce43dee4f	6743
cparata	0:f27ce43dee4f	6744	/**
cparata	0:f27ce43dee4f	6745	* @brief DEN value stored in LSB of Z-axis.[get]
cparata	0:f27ce43dee4f	6746	*
cparata	0:f27ce43dee4f	6747	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6748	* @param val change the values of den_x in reg CTRL9_XL
cparata	0:f27ce43dee4f	6749	*
cparata	0:f27ce43dee4f	6750	*/
cparata	0:f27ce43dee4f	6751	int32_t lsm6dsox_den_mark_axis_z_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6752	{
cparata	0:f27ce43dee4f	6753	lsm6dsox_ctrl9_xl_t reg;
cparata	0:f27ce43dee4f	6754	int32_t ret;
cparata	0:f27ce43dee4f	6755
cparata	0:f27ce43dee4f	6756	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6757	*val = reg.den_x;
cparata	0:f27ce43dee4f	6758
cparata	0:f27ce43dee4f	6759	return ret;
cparata	0:f27ce43dee4f	6760	}
cparata	0:f27ce43dee4f	6761
cparata	0:f27ce43dee4f	6762	/**
cparata	0:f27ce43dee4f	6763	* @}
cparata	0:f27ce43dee4f	6764	*
cparata	0:f27ce43dee4f	6765	*/
cparata	0:f27ce43dee4f	6766
cparata	0:f27ce43dee4f	6767	/**
cparata	0:f27ce43dee4f	6768	* @defgroup LSM6DSOX_Pedometer
cparata	0:f27ce43dee4f	6769	* @brief This section groups all the functions that manage pedometer.
cparata	0:f27ce43dee4f	6770	* @{
cparata	0:f27ce43dee4f	6771	*
cparata	0:f27ce43dee4f	6772	*/
cparata	0:f27ce43dee4f	6773
cparata	0:f27ce43dee4f	6774	/**
cparata	0:f27ce43dee4f	6775	* @brief Enable pedometer algorithm.[set]
cparata	0:f27ce43dee4f	6776	*
cparata	0:f27ce43dee4f	6777	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6778	* @param val turn on and configure pedometer
cparata	0:f27ce43dee4f	6779	*
cparata	0:f27ce43dee4f	6780	*/
cparata	0:f27ce43dee4f	6781	int32_t lsm6dsox_pedo_sens_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t val)
cparata	0:f27ce43dee4f	6782	{
cparata	0:f27ce43dee4f	6783	lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg;
cparata	0:f27ce43dee4f	6784	int32_t ret;
cparata	0:f27ce43dee4f	6785
cparata	0:f27ce43dee4f	6786	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
cparata	0:f27ce43dee4f	6787	(uint8_t*)&pedo_cmd_reg);
cparata	1:fe40aec6e97a	6788
cparata	1:fe40aec6e97a	6789	if (ret == 0) {
cparata	0:f27ce43dee4f	6790	pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4;
cparata	0:f27ce43dee4f	6791	pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5;
cparata	1:fe40aec6e97a	6792
cparata	0:f27ce43dee4f	6793	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
cparata	0:f27ce43dee4f	6794	(uint8_t*)&pedo_cmd_reg);
cparata	0:f27ce43dee4f	6795	}
cparata	0:f27ce43dee4f	6796	return ret;
cparata	0:f27ce43dee4f	6797	}
cparata	0:f27ce43dee4f	6798
cparata	0:f27ce43dee4f	6799	/**
cparata	0:f27ce43dee4f	6800	* @brief Enable pedometer algorithm.[get]
cparata	0:f27ce43dee4f	6801	*
cparata	0:f27ce43dee4f	6802	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6803	* @param val turn on and configure pedometer
cparata	0:f27ce43dee4f	6804	*
cparata	0:f27ce43dee4f	6805	*/
cparata	0:f27ce43dee4f	6806	int32_t lsm6dsox_pedo_sens_get(lsm6dsox_ctx_t ctx, lsm6dsox_pedo_md_t val)
cparata	0:f27ce43dee4f	6807	{
cparata	0:f27ce43dee4f	6808	lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg;
cparata	0:f27ce43dee4f	6809	int32_t ret;
cparata	0:f27ce43dee4f	6810
cparata	0:f27ce43dee4f	6811	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
cparata	1:fe40aec6e97a	6812	(uint8_t*)&pedo_cmd_reg);
cparata	1:fe40aec6e97a	6813	switch ( (pedo_cmd_reg.ad_det_en <<5) \| (pedo_cmd_reg.fp_rejection_en << 4) ){
cparata	0:f27ce43dee4f	6814	case LSM6DSOX_PEDO_BASE_MODE:
cparata	0:f27ce43dee4f	6815	*val = LSM6DSOX_PEDO_BASE_MODE;
cparata	0:f27ce43dee4f	6816	break;
cparata	0:f27ce43dee4f	6817	case LSM6DSOX_FALSE_STEP_REJ:
cparata	0:f27ce43dee4f	6818	*val = LSM6DSOX_FALSE_STEP_REJ;
cparata	0:f27ce43dee4f	6819	break;
cparata	0:f27ce43dee4f	6820	case LSM6DSOX_FALSE_STEP_REJ_ADV_MODE:
cparata	0:f27ce43dee4f	6821	*val = LSM6DSOX_FALSE_STEP_REJ_ADV_MODE;
cparata	0:f27ce43dee4f	6822	break;
cparata	0:f27ce43dee4f	6823	default:
cparata	1:fe40aec6e97a	6824	*val = LSM6DSOX_PEDO_BASE_MODE;
cparata	0:f27ce43dee4f	6825	break;
cparata	0:f27ce43dee4f	6826	}
cparata	0:f27ce43dee4f	6827	return ret;
cparata	0:f27ce43dee4f	6828	}
cparata	0:f27ce43dee4f	6829
cparata	0:f27ce43dee4f	6830	/**
cparata	0:f27ce43dee4f	6831	* @brief Interrupt status bit for step detection.[get]
cparata	0:f27ce43dee4f	6832	*
cparata	0:f27ce43dee4f	6833	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6834	* @param val change the values of is_step_det in reg EMB_FUNC_STATUS
cparata	0:f27ce43dee4f	6835	*
cparata	0:f27ce43dee4f	6836	*/
cparata	0:f27ce43dee4f	6837	int32_t lsm6dsox_pedo_step_detect_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6838	{
cparata	0:f27ce43dee4f	6839	lsm6dsox_emb_func_status_t reg;
cparata	0:f27ce43dee4f	6840	int32_t ret;
cparata	0:f27ce43dee4f	6841
cparata	0:f27ce43dee4f	6842	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	6843	if (ret == 0) {
cparata	0:f27ce43dee4f	6844	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	6845	}
cparata	0:f27ce43dee4f	6846	if (ret == 0) {
cparata	0:f27ce43dee4f	6847	*val = reg.is_step_det;
cparata	0:f27ce43dee4f	6848	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	6849	}
cparata	0:f27ce43dee4f	6850
cparata	0:f27ce43dee4f	6851	return ret;
cparata	0:f27ce43dee4f	6852	}
cparata	0:f27ce43dee4f	6853
cparata	0:f27ce43dee4f	6854	/**
cparata	0:f27ce43dee4f	6855	* @brief Pedometer debounce configuration register (r/w).[set]
cparata	0:f27ce43dee4f	6856	*
cparata	0:f27ce43dee4f	6857	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6858	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	6859	*
cparata	0:f27ce43dee4f	6860	*/
cparata	0:f27ce43dee4f	6861	int32_t lsm6dsox_pedo_debounce_steps_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	6862	{
cparata	0:f27ce43dee4f	6863	int32_t ret;
cparata	0:f27ce43dee4f	6864	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff);
cparata	0:f27ce43dee4f	6865	return ret;
cparata	0:f27ce43dee4f	6866	}
cparata	0:f27ce43dee4f	6867
cparata	0:f27ce43dee4f	6868	/**
cparata	0:f27ce43dee4f	6869	* @brief Pedometer debounce configuration register (r/w).[get]
cparata	0:f27ce43dee4f	6870	*
cparata	0:f27ce43dee4f	6871	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6872	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	6873	*
cparata	0:f27ce43dee4f	6874	*/
cparata	0:f27ce43dee4f	6875	int32_t lsm6dsox_pedo_debounce_steps_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	6876	{
cparata	0:f27ce43dee4f	6877	int32_t ret;
cparata	0:f27ce43dee4f	6878	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff);
cparata	0:f27ce43dee4f	6879	return ret;
cparata	0:f27ce43dee4f	6880	}
cparata	0:f27ce43dee4f	6881
cparata	0:f27ce43dee4f	6882	/**
cparata	0:f27ce43dee4f	6883	* @brief Time period register for step detection on delta time (r/w).[set]
cparata	0:f27ce43dee4f	6884	*
cparata	0:f27ce43dee4f	6885	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6886	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	6887	*
cparata	0:f27ce43dee4f	6888	*/
cparata	0:f27ce43dee4f	6889	int32_t lsm6dsox_pedo_steps_period_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	6890	{
cparata	0:f27ce43dee4f	6891	int32_t ret;
cparata	0:f27ce43dee4f	6892	uint8_t index;
cparata	0:f27ce43dee4f	6893
cparata	0:f27ce43dee4f	6894	index = 0x00U;
cparata	0:f27ce43dee4f	6895	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]);
cparata	0:f27ce43dee4f	6896	if (ret == 0) {
cparata	0:f27ce43dee4f	6897	index++;
cparata	0:f27ce43dee4f	6898	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H,
cparata	0:f27ce43dee4f	6899	&buff[index]);
cparata	0:f27ce43dee4f	6900	}
cparata	0:f27ce43dee4f	6901	return ret;
cparata	0:f27ce43dee4f	6902	}
cparata	0:f27ce43dee4f	6903
cparata	0:f27ce43dee4f	6904	/**
cparata	0:f27ce43dee4f	6905	* @brief Time period register for step detection on delta time (r/w).[get]
cparata	0:f27ce43dee4f	6906	*
cparata	0:f27ce43dee4f	6907	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6908	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	6909	*
cparata	0:f27ce43dee4f	6910	*/
cparata	0:f27ce43dee4f	6911	int32_t lsm6dsox_pedo_steps_period_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	6912	{
cparata	0:f27ce43dee4f	6913	int32_t ret;
cparata	0:f27ce43dee4f	6914	uint8_t index;
cparata	0:f27ce43dee4f	6915
cparata	0:f27ce43dee4f	6916	index = 0x00U;
cparata	0:f27ce43dee4f	6917	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]);
cparata	0:f27ce43dee4f	6918	if (ret == 0) {
cparata	0:f27ce43dee4f	6919	index++;
cparata	0:f27ce43dee4f	6920	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H,
cparata	0:f27ce43dee4f	6921	&buff[index]);
cparata	0:f27ce43dee4f	6922	}
cparata	0:f27ce43dee4f	6923	return ret;
cparata	0:f27ce43dee4f	6924	}
cparata	0:f27ce43dee4f	6925
cparata	0:f27ce43dee4f	6926	/**
cparata	0:f27ce43dee4f	6927	* @brief Set when user wants to generate interrupt on count overflow
cparata	0:f27ce43dee4f	6928	* event/every step.[set]
cparata	0:f27ce43dee4f	6929	*
cparata	0:f27ce43dee4f	6930	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6931	* @param val change the values of carry_count_en in reg PEDO_CMD_REG
cparata	0:f27ce43dee4f	6932	*
cparata	0:f27ce43dee4f	6933	*/
cparata	0:f27ce43dee4f	6934	int32_t lsm6dsox_pedo_int_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	6935	lsm6dsox_carry_count_en_t val)
cparata	0:f27ce43dee4f	6936	{
cparata	0:f27ce43dee4f	6937	lsm6dsox_pedo_cmd_reg_t reg;
cparata	0:f27ce43dee4f	6938	int32_t ret;
cparata	0:f27ce43dee4f	6939
cparata	0:f27ce43dee4f	6940	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	6941	if (ret == 0) {
cparata	0:f27ce43dee4f	6942	reg.carry_count_en = (uint8_t)val;
cparata	0:f27ce43dee4f	6943	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
cparata	0:f27ce43dee4f	6944	(uint8_t*)&reg);
cparata	0:f27ce43dee4f	6945	}
cparata	0:f27ce43dee4f	6946	return ret;
cparata	0:f27ce43dee4f	6947	}
cparata	0:f27ce43dee4f	6948
cparata	0:f27ce43dee4f	6949	/**
cparata	0:f27ce43dee4f	6950	* @brief Set when user wants to generate interrupt on count overflow
cparata	0:f27ce43dee4f	6951	* event/every step.[get]
cparata	0:f27ce43dee4f	6952	*
cparata	0:f27ce43dee4f	6953	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6954	* @param val Get the values of carry_count_en in reg PEDO_CMD_REG
cparata	0:f27ce43dee4f	6955	*
cparata	0:f27ce43dee4f	6956	*/
cparata	0:f27ce43dee4f	6957	int32_t lsm6dsox_pedo_int_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	6958	lsm6dsox_carry_count_en_t *val)
cparata	0:f27ce43dee4f	6959	{
cparata	0:f27ce43dee4f	6960	lsm6dsox_pedo_cmd_reg_t reg;
cparata	0:f27ce43dee4f	6961	int32_t ret;
cparata	0:f27ce43dee4f	6962
cparata	0:f27ce43dee4f	6963	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	6964	switch (reg.carry_count_en) {
cparata	0:f27ce43dee4f	6965	case LSM6DSOX_EVERY_STEP:
cparata	0:f27ce43dee4f	6966	*val = LSM6DSOX_EVERY_STEP;
cparata	0:f27ce43dee4f	6967	break;
cparata	0:f27ce43dee4f	6968	case LSM6DSOX_COUNT_OVERFLOW:
cparata	0:f27ce43dee4f	6969	*val = LSM6DSOX_COUNT_OVERFLOW;
cparata	0:f27ce43dee4f	6970	break;
cparata	0:f27ce43dee4f	6971	default:
cparata	0:f27ce43dee4f	6972	*val = LSM6DSOX_EVERY_STEP;
cparata	0:f27ce43dee4f	6973	break;
cparata	0:f27ce43dee4f	6974	}
cparata	0:f27ce43dee4f	6975	return ret;
cparata	0:f27ce43dee4f	6976	}
cparata	0:f27ce43dee4f	6977
cparata	0:f27ce43dee4f	6978	/**
cparata	0:f27ce43dee4f	6979	* @}
cparata	0:f27ce43dee4f	6980	*
cparata	0:f27ce43dee4f	6981	*/
cparata	0:f27ce43dee4f	6982
cparata	0:f27ce43dee4f	6983	/**
cparata	0:f27ce43dee4f	6984	* @defgroup LSM6DSOX_significant_motion
cparata	0:f27ce43dee4f	6985	* @brief This section groups all the functions that manage the
cparata	0:f27ce43dee4f	6986	* significant motion detection.
cparata	0:f27ce43dee4f	6987	* @{
cparata	0:f27ce43dee4f	6988	*
cparata	0:f27ce43dee4f	6989	*/
cparata	0:f27ce43dee4f	6990
cparata	0:f27ce43dee4f	6991	/**
cparata	0:f27ce43dee4f	6992	* @brief Interrupt status bit for significant motion detection.[get]
cparata	0:f27ce43dee4f	6993	*
cparata	0:f27ce43dee4f	6994	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	6995	* @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
cparata	0:f27ce43dee4f	6996	*
cparata	0:f27ce43dee4f	6997	*/
cparata	0:f27ce43dee4f	6998	int32_t lsm6dsox_motion_flag_data_ready_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	6999	{
cparata	0:f27ce43dee4f	7000	lsm6dsox_emb_func_status_t reg;
cparata	0:f27ce43dee4f	7001	int32_t ret;
cparata	0:f27ce43dee4f	7002
cparata	0:f27ce43dee4f	7003	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7004	if (ret == 0) {
cparata	0:f27ce43dee4f	7005	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7006	}
cparata	0:f27ce43dee4f	7007	if (ret == 0) {
cparata	0:f27ce43dee4f	7008	*val = reg.is_sigmot;
cparata	0:f27ce43dee4f	7009	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7010	}
cparata	0:f27ce43dee4f	7011
cparata	0:f27ce43dee4f	7012	return ret;
cparata	0:f27ce43dee4f	7013	}
cparata	0:f27ce43dee4f	7014
cparata	0:f27ce43dee4f	7015	/**
cparata	0:f27ce43dee4f	7016	* @}
cparata	0:f27ce43dee4f	7017	*
cparata	0:f27ce43dee4f	7018	*/
cparata	0:f27ce43dee4f	7019
cparata	0:f27ce43dee4f	7020	/**
cparata	0:f27ce43dee4f	7021	* @defgroup LSM6DSOX_tilt_detection
cparata	0:f27ce43dee4f	7022	* @brief This section groups all the functions that manage the tilt
cparata	0:f27ce43dee4f	7023	* event detection.
cparata	0:f27ce43dee4f	7024	* @{
cparata	0:f27ce43dee4f	7025	*
cparata	0:f27ce43dee4f	7026	*/
cparata	0:f27ce43dee4f	7027
cparata	0:f27ce43dee4f	7028	/**
cparata	0:f27ce43dee4f	7029	* @brief Interrupt status bit for tilt detection.[get]
cparata	0:f27ce43dee4f	7030	*
cparata	0:f27ce43dee4f	7031	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7032	* @param val change the values of is_tilt in reg EMB_FUNC_STATUS
cparata	0:f27ce43dee4f	7033	*
cparata	0:f27ce43dee4f	7034	*/
cparata	0:f27ce43dee4f	7035	int32_t lsm6dsox_tilt_flag_data_ready_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	7036	{
cparata	0:f27ce43dee4f	7037	lsm6dsox_emb_func_status_t reg;
cparata	0:f27ce43dee4f	7038	int32_t ret;
cparata	0:f27ce43dee4f	7039
cparata	0:f27ce43dee4f	7040	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7041	if (ret == 0) {
cparata	0:f27ce43dee4f	7042	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7043	}
cparata	0:f27ce43dee4f	7044	if (ret == 0) {
cparata	0:f27ce43dee4f	7045	*val = reg.is_tilt;
cparata	0:f27ce43dee4f	7046	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7047	}
cparata	0:f27ce43dee4f	7048
cparata	0:f27ce43dee4f	7049	return ret;
cparata	0:f27ce43dee4f	7050	}
cparata	0:f27ce43dee4f	7051
cparata	0:f27ce43dee4f	7052	/**
cparata	0:f27ce43dee4f	7053	* @}
cparata	0:f27ce43dee4f	7054	*
cparata	0:f27ce43dee4f	7055	*/
cparata	0:f27ce43dee4f	7056
cparata	0:f27ce43dee4f	7057	/**
cparata	0:f27ce43dee4f	7058	* @defgroup LSM6DSOX_ magnetometer_sensor
cparata	0:f27ce43dee4f	7059	* @brief This section groups all the functions that manage additional
cparata	0:f27ce43dee4f	7060	* magnetometer sensor.
cparata	0:f27ce43dee4f	7061	* @{
cparata	0:f27ce43dee4f	7062	*
cparata	0:f27ce43dee4f	7063	*/
cparata	0:f27ce43dee4f	7064
cparata	0:f27ce43dee4f	7065	/**
cparata	0:f27ce43dee4f	7066	* @brief External magnetometer sensitivity value register for
cparata	0:f27ce43dee4f	7067	* Sensor hub.[set]
cparata	0:f27ce43dee4f	7068	*
cparata	0:f27ce43dee4f	7069	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7070	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	7071	*
cparata	0:f27ce43dee4f	7072	*/
cparata	0:f27ce43dee4f	7073	int32_t lsm6dsox_sh_mag_sensitivity_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7074	{
cparata	0:f27ce43dee4f	7075	int32_t ret;
cparata	0:f27ce43dee4f	7076	uint8_t index;
cparata	0:f27ce43dee4f	7077
cparata	0:f27ce43dee4f	7078	index = 0x00U;
cparata	0:f27ce43dee4f	7079	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L,
cparata	0:f27ce43dee4f	7080	&buff[index]);
cparata	0:f27ce43dee4f	7081	if (ret == 0) {
cparata	0:f27ce43dee4f	7082	index++;
cparata	0:f27ce43dee4f	7083	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H,
cparata	0:f27ce43dee4f	7084	&buff[index]);
cparata	0:f27ce43dee4f	7085	}
cparata	0:f27ce43dee4f	7086
cparata	0:f27ce43dee4f	7087	return ret;
cparata	0:f27ce43dee4f	7088	}
cparata	0:f27ce43dee4f	7089
cparata	0:f27ce43dee4f	7090	/**
cparata	0:f27ce43dee4f	7091	* @brief External magnetometer sensitivity value register for
cparata	0:f27ce43dee4f	7092	* Sensor hub.[get]
cparata	0:f27ce43dee4f	7093	*
cparata	0:f27ce43dee4f	7094	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7095	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	7096	*
cparata	0:f27ce43dee4f	7097	*/
cparata	0:f27ce43dee4f	7098	int32_t lsm6dsox_sh_mag_sensitivity_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7099	{
cparata	0:f27ce43dee4f	7100	int32_t ret;
cparata	0:f27ce43dee4f	7101	uint8_t index;
cparata	0:f27ce43dee4f	7102
cparata	0:f27ce43dee4f	7103	index = 0x00U;
cparata	0:f27ce43dee4f	7104	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L,
cparata	0:f27ce43dee4f	7105	&buff[index]);
cparata	0:f27ce43dee4f	7106	if (ret == 0) {
cparata	0:f27ce43dee4f	7107	index++;
cparata	0:f27ce43dee4f	7108	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H,
cparata	0:f27ce43dee4f	7109	&buff[index]);
cparata	0:f27ce43dee4f	7110	}
cparata	0:f27ce43dee4f	7111
cparata	0:f27ce43dee4f	7112	return ret;
cparata	0:f27ce43dee4f	7113	}
cparata	0:f27ce43dee4f	7114
cparata	0:f27ce43dee4f	7115	/**
cparata	0:f27ce43dee4f	7116	* @brief External magnetometer sensitivity value register for
cparata	0:f27ce43dee4f	7117	* Machine Learning Core.[set]
cparata	0:f27ce43dee4f	7118	*
cparata	0:f27ce43dee4f	7119	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7120	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	7121	*
cparata	0:f27ce43dee4f	7122	*/
cparata	0:f27ce43dee4f	7123	int32_t lsm6dsox_mlc_mag_sensitivity_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7124	{
cparata	0:f27ce43dee4f	7125	int32_t ret;
cparata	0:f27ce43dee4f	7126	uint8_t index;
cparata	0:f27ce43dee4f	7127
cparata	0:f27ce43dee4f	7128	index = 0x00U;
cparata	0:f27ce43dee4f	7129	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L,
cparata	0:f27ce43dee4f	7130	&buff[index]);
cparata	0:f27ce43dee4f	7131	if (ret == 0) {
cparata	0:f27ce43dee4f	7132	index++;
cparata	0:f27ce43dee4f	7133	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H,
cparata	0:f27ce43dee4f	7134	&buff[index]);
cparata	0:f27ce43dee4f	7135	}
cparata	0:f27ce43dee4f	7136	return ret;
cparata	0:f27ce43dee4f	7137	}
cparata	0:f27ce43dee4f	7138
cparata	0:f27ce43dee4f	7139	/**
cparata	0:f27ce43dee4f	7140	* @brief External magnetometer sensitivity value register for
cparata	0:f27ce43dee4f	7141	* Machine Learning Core.[get]
cparata	0:f27ce43dee4f	7142	*
cparata	0:f27ce43dee4f	7143	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7144	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	7145	*
cparata	0:f27ce43dee4f	7146	*/
cparata	0:f27ce43dee4f	7147	int32_t lsm6dsox_mlc_mag_sensitivity_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7148	{
cparata	0:f27ce43dee4f	7149	int32_t ret;
cparata	0:f27ce43dee4f	7150	uint8_t index;
cparata	0:f27ce43dee4f	7151
cparata	0:f27ce43dee4f	7152	index = 0x00U;
cparata	0:f27ce43dee4f	7153	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L,
cparata	0:f27ce43dee4f	7154	&buff[index]);
cparata	0:f27ce43dee4f	7155	if (ret == 0) {
cparata	0:f27ce43dee4f	7156	index++;
cparata	0:f27ce43dee4f	7157	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H,
cparata	0:f27ce43dee4f	7158	&buff[index]);
cparata	0:f27ce43dee4f	7159	}
cparata	0:f27ce43dee4f	7160	return ret;
cparata	0:f27ce43dee4f	7161	}
cparata	0:f27ce43dee4f	7162
cparata	0:f27ce43dee4f	7163
cparata	0:f27ce43dee4f	7164	/**
cparata	0:f27ce43dee4f	7165	* @brief Offset for hard-iron compensation register (r/w).[set]
cparata	0:f27ce43dee4f	7166	*
cparata	0:f27ce43dee4f	7167	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7168	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	7169	*
cparata	0:f27ce43dee4f	7170	*/
cparata	0:f27ce43dee4f	7171	int32_t lsm6dsox_mag_offset_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7172	{
cparata	0:f27ce43dee4f	7173	int32_t ret;
cparata	0:f27ce43dee4f	7174	uint8_t index;
cparata	0:f27ce43dee4f	7175
cparata	0:f27ce43dee4f	7176	index = 0x00U;
cparata	0:f27ce43dee4f	7177	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]);
cparata	0:f27ce43dee4f	7178	if (ret == 0) {
cparata	0:f27ce43dee4f	7179	index++;
cparata	0:f27ce43dee4f	7180	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]);
cparata	0:f27ce43dee4f	7181	}
cparata	0:f27ce43dee4f	7182	if (ret == 0) {
cparata	0:f27ce43dee4f	7183	index++;
cparata	0:f27ce43dee4f	7184	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]);
cparata	0:f27ce43dee4f	7185	}
cparata	0:f27ce43dee4f	7186	if (ret == 0) {
cparata	0:f27ce43dee4f	7187	index++;
cparata	0:f27ce43dee4f	7188	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]);
cparata	0:f27ce43dee4f	7189	}
cparata	0:f27ce43dee4f	7190	if (ret == 0) {
cparata	0:f27ce43dee4f	7191	index++;
cparata	0:f27ce43dee4f	7192
cparata	0:f27ce43dee4f	7193	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]);
cparata	0:f27ce43dee4f	7194	}
cparata	0:f27ce43dee4f	7195	if (ret == 0) {
cparata	0:f27ce43dee4f	7196	index++;
cparata	0:f27ce43dee4f	7197	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]);
cparata	0:f27ce43dee4f	7198	}
cparata	0:f27ce43dee4f	7199
cparata	0:f27ce43dee4f	7200	return ret;
cparata	0:f27ce43dee4f	7201	}
cparata	0:f27ce43dee4f	7202
cparata	0:f27ce43dee4f	7203	/**
cparata	0:f27ce43dee4f	7204	* @brief Offset for hard-iron compensation register (r/w).[get]
cparata	0:f27ce43dee4f	7205	*
cparata	0:f27ce43dee4f	7206	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7207	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	7208	*
cparata	0:f27ce43dee4f	7209	*/
cparata	0:f27ce43dee4f	7210	int32_t lsm6dsox_mag_offset_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7211	{
cparata	0:f27ce43dee4f	7212	int32_t ret;
cparata	0:f27ce43dee4f	7213	uint8_t index;
cparata	0:f27ce43dee4f	7214
cparata	0:f27ce43dee4f	7215	index = 0x00U;
cparata	0:f27ce43dee4f	7216	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]);
cparata	0:f27ce43dee4f	7217	if (ret == 0) {
cparata	0:f27ce43dee4f	7218	index++;
cparata	0:f27ce43dee4f	7219	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]);
cparata	0:f27ce43dee4f	7220	}
cparata	0:f27ce43dee4f	7221	if (ret == 0) {
cparata	0:f27ce43dee4f	7222	index++;
cparata	0:f27ce43dee4f	7223
cparata	0:f27ce43dee4f	7224	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]);
cparata	0:f27ce43dee4f	7225	}
cparata	0:f27ce43dee4f	7226	if (ret == 0) {
cparata	0:f27ce43dee4f	7227	index++;
cparata	0:f27ce43dee4f	7228	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]);
cparata	0:f27ce43dee4f	7229	}
cparata	0:f27ce43dee4f	7230	if (ret == 0) {
cparata	0:f27ce43dee4f	7231	index++;
cparata	0:f27ce43dee4f	7232
cparata	0:f27ce43dee4f	7233	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]);
cparata	0:f27ce43dee4f	7234	}
cparata	0:f27ce43dee4f	7235	if (ret == 0) {
cparata	0:f27ce43dee4f	7236	index++;
cparata	0:f27ce43dee4f	7237	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]);
cparata	0:f27ce43dee4f	7238	}
cparata	0:f27ce43dee4f	7239	return ret;
cparata	0:f27ce43dee4f	7240	}
cparata	0:f27ce43dee4f	7241
cparata	0:f27ce43dee4f	7242	/**
cparata	0:f27ce43dee4f	7243	* @brief Soft-iron (3x3 symmetric) matrix correction
cparata	0:f27ce43dee4f	7244	* register (r/w). The value is expressed as
cparata	0:f27ce43dee4f	7245	* half-precision floating-point format:
cparata	0:f27ce43dee4f	7246	* SEEEEEFFFFFFFFFF
cparata	0:f27ce43dee4f	7247	* S: 1 sign bit;
cparata	0:f27ce43dee4f	7248	* E: 5 exponent bits;
cparata	0:f27ce43dee4f	7249	* F: 10 fraction bits).[set]
cparata	0:f27ce43dee4f	7250	*
cparata	0:f27ce43dee4f	7251	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7252	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	7253	*
cparata	0:f27ce43dee4f	7254	*/
cparata	0:f27ce43dee4f	7255	int32_t lsm6dsox_mag_soft_iron_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7256	{
cparata	0:f27ce43dee4f	7257	int32_t ret;
cparata	0:f27ce43dee4f	7258	uint8_t index;
cparata	0:f27ce43dee4f	7259
cparata	0:f27ce43dee4f	7260	index = 0x00U;
cparata	0:f27ce43dee4f	7261	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]);
cparata	0:f27ce43dee4f	7262	if (ret == 0) {
cparata	0:f27ce43dee4f	7263	index++;
cparata	0:f27ce43dee4f	7264	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]);
cparata	0:f27ce43dee4f	7265	}
cparata	0:f27ce43dee4f	7266	if (ret == 0) {
cparata	0:f27ce43dee4f	7267	index++;
cparata	0:f27ce43dee4f	7268
cparata	0:f27ce43dee4f	7269	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]);
cparata	0:f27ce43dee4f	7270	}
cparata	0:f27ce43dee4f	7271	if (ret == 0) {
cparata	0:f27ce43dee4f	7272	index++;
cparata	0:f27ce43dee4f	7273	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]);
cparata	0:f27ce43dee4f	7274	}
cparata	0:f27ce43dee4f	7275	if (ret == 0) {
cparata	0:f27ce43dee4f	7276	index++;
cparata	0:f27ce43dee4f	7277
cparata	0:f27ce43dee4f	7278	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]);
cparata	0:f27ce43dee4f	7279	}
cparata	0:f27ce43dee4f	7280	if (ret == 0) {
cparata	0:f27ce43dee4f	7281	index++;
cparata	0:f27ce43dee4f	7282	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]);
cparata	0:f27ce43dee4f	7283	}
cparata	0:f27ce43dee4f	7284	if (ret == 0) {
cparata	0:f27ce43dee4f	7285	index++;
cparata	0:f27ce43dee4f	7286
cparata	0:f27ce43dee4f	7287	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]);
cparata	0:f27ce43dee4f	7288	}
cparata	0:f27ce43dee4f	7289	if (ret == 0) {
cparata	0:f27ce43dee4f	7290	index++;
cparata	0:f27ce43dee4f	7291	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]);
cparata	0:f27ce43dee4f	7292	}
cparata	0:f27ce43dee4f	7293	if (ret == 0) {
cparata	0:f27ce43dee4f	7294	index++;
cparata	0:f27ce43dee4f	7295
cparata	0:f27ce43dee4f	7296	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]);
cparata	0:f27ce43dee4f	7297	}
cparata	0:f27ce43dee4f	7298	if (ret == 0) {
cparata	0:f27ce43dee4f	7299	index++;
cparata	0:f27ce43dee4f	7300	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]);
cparata	0:f27ce43dee4f	7301	}
cparata	0:f27ce43dee4f	7302	if (ret == 0) {
cparata	0:f27ce43dee4f	7303	index++;
cparata	0:f27ce43dee4f	7304
cparata	0:f27ce43dee4f	7305	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]);
cparata	0:f27ce43dee4f	7306	}
cparata	0:f27ce43dee4f	7307	if (ret == 0) {
cparata	0:f27ce43dee4f	7308	index++;
cparata	0:f27ce43dee4f	7309	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]);
cparata	0:f27ce43dee4f	7310	}
cparata	0:f27ce43dee4f	7311
cparata	0:f27ce43dee4f	7312	return ret;
cparata	0:f27ce43dee4f	7313	}
cparata	0:f27ce43dee4f	7314
cparata	0:f27ce43dee4f	7315	/**
cparata	0:f27ce43dee4f	7316	* @brief Soft-iron (3x3 symmetric) matrix
cparata	0:f27ce43dee4f	7317	* correction register (r/w).
cparata	0:f27ce43dee4f	7318	* The value is expressed as half-precision
cparata	0:f27ce43dee4f	7319	* floating-point format:
cparata	0:f27ce43dee4f	7320	* SEEEEEFFFFFFFFFF
cparata	0:f27ce43dee4f	7321	* S: 1 sign bit;
cparata	0:f27ce43dee4f	7322	* E: 5 exponent bits;
cparata	0:f27ce43dee4f	7323	* F: 10 fraction bits.[get]
cparata	0:f27ce43dee4f	7324	*
cparata	0:f27ce43dee4f	7325	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7326	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	7327	*
cparata	0:f27ce43dee4f	7328	*/
cparata	0:f27ce43dee4f	7329	int32_t lsm6dsox_mag_soft_iron_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7330	{
cparata	0:f27ce43dee4f	7331	int32_t ret;
cparata	0:f27ce43dee4f	7332	uint8_t index;
cparata	0:f27ce43dee4f	7333
cparata	0:f27ce43dee4f	7334	index = 0x00U;
cparata	0:f27ce43dee4f	7335	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]);
cparata	0:f27ce43dee4f	7336	if (ret == 0) {
cparata	0:f27ce43dee4f	7337	index++;
cparata	0:f27ce43dee4f	7338	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]);
cparata	0:f27ce43dee4f	7339	}
cparata	0:f27ce43dee4f	7340	if (ret == 0) {
cparata	0:f27ce43dee4f	7341	index++;
cparata	0:f27ce43dee4f	7342
cparata	0:f27ce43dee4f	7343	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]);
cparata	0:f27ce43dee4f	7344	}
cparata	0:f27ce43dee4f	7345	if (ret == 0) {
cparata	0:f27ce43dee4f	7346	index++;
cparata	0:f27ce43dee4f	7347	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]);
cparata	0:f27ce43dee4f	7348	}
cparata	0:f27ce43dee4f	7349	if (ret == 0) {
cparata	0:f27ce43dee4f	7350	index++;
cparata	0:f27ce43dee4f	7351
cparata	0:f27ce43dee4f	7352	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]);
cparata	0:f27ce43dee4f	7353	}
cparata	0:f27ce43dee4f	7354	if (ret == 0) {
cparata	0:f27ce43dee4f	7355	index++;
cparata	0:f27ce43dee4f	7356	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]);
cparata	0:f27ce43dee4f	7357	}
cparata	0:f27ce43dee4f	7358	if (ret == 0) {
cparata	0:f27ce43dee4f	7359	index++;
cparata	0:f27ce43dee4f	7360
cparata	0:f27ce43dee4f	7361	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]);
cparata	0:f27ce43dee4f	7362	}
cparata	0:f27ce43dee4f	7363	if (ret == 0) {
cparata	0:f27ce43dee4f	7364	index++;
cparata	0:f27ce43dee4f	7365	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]);
cparata	0:f27ce43dee4f	7366	}
cparata	0:f27ce43dee4f	7367	if (ret == 0) {
cparata	0:f27ce43dee4f	7368	index++;
cparata	0:f27ce43dee4f	7369
cparata	0:f27ce43dee4f	7370	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]);
cparata	0:f27ce43dee4f	7371	}
cparata	0:f27ce43dee4f	7372	if (ret == 0) {
cparata	0:f27ce43dee4f	7373	index++;
cparata	0:f27ce43dee4f	7374	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]);
cparata	0:f27ce43dee4f	7375	}
cparata	0:f27ce43dee4f	7376	if (ret == 0) {
cparata	0:f27ce43dee4f	7377	index++;
cparata	0:f27ce43dee4f	7378
cparata	0:f27ce43dee4f	7379	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]);
cparata	0:f27ce43dee4f	7380	}
cparata	0:f27ce43dee4f	7381	if (ret == 0) {
cparata	0:f27ce43dee4f	7382	index++;
cparata	0:f27ce43dee4f	7383	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]);
cparata	0:f27ce43dee4f	7384	}
cparata	0:f27ce43dee4f	7385
cparata	0:f27ce43dee4f	7386	return ret;
cparata	0:f27ce43dee4f	7387	}
cparata	0:f27ce43dee4f	7388
cparata	0:f27ce43dee4f	7389	/**
cparata	0:f27ce43dee4f	7390	* @brief Magnetometer Z-axis coordinates
cparata	0:f27ce43dee4f	7391	* rotation (to be aligned to
cparata	0:f27ce43dee4f	7392	* accelerometer/gyroscope axes
cparata	0:f27ce43dee4f	7393	* orientation).[set]
cparata	0:f27ce43dee4f	7394	*
cparata	0:f27ce43dee4f	7395	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7396	* @param val change the values of mag_z_axis in reg MAG_CFG_A
cparata	0:f27ce43dee4f	7397	*
cparata	0:f27ce43dee4f	7398	*/
cparata	0:f27ce43dee4f	7399	int32_t lsm6dsox_mag_z_orient_set(lsm6dsox_ctx_t *ctx, lsm6dsox_mag_z_axis_t val)
cparata	0:f27ce43dee4f	7400	{
cparata	0:f27ce43dee4f	7401	lsm6dsox_mag_cfg_a_t reg;
cparata	0:f27ce43dee4f	7402	int32_t ret;
cparata	0:f27ce43dee4f	7403
cparata	0:f27ce43dee4f	7404	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	7405	if (ret == 0) {
cparata	0:f27ce43dee4f	7406	reg.mag_z_axis = (uint8_t) val;
cparata	0:f27ce43dee4f	7407	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	7408	}
cparata	0:f27ce43dee4f	7409
cparata	0:f27ce43dee4f	7410	return ret;
cparata	0:f27ce43dee4f	7411	}
cparata	0:f27ce43dee4f	7412
cparata	0:f27ce43dee4f	7413	/**
cparata	0:f27ce43dee4f	7414	* @brief Magnetometer Z-axis coordinates
cparata	0:f27ce43dee4f	7415	* rotation (to be aligned to
cparata	0:f27ce43dee4f	7416	* accelerometer/gyroscope axes
cparata	0:f27ce43dee4f	7417	* orientation).[get]
cparata	0:f27ce43dee4f	7418	*
cparata	0:f27ce43dee4f	7419	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7420	* @param val Get the values of mag_z_axis in reg MAG_CFG_A
cparata	0:f27ce43dee4f	7421	*
cparata	0:f27ce43dee4f	7422	*/
cparata	0:f27ce43dee4f	7423	int32_t lsm6dsox_mag_z_orient_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	7424	lsm6dsox_mag_z_axis_t *val)
cparata	0:f27ce43dee4f	7425	{
cparata	0:f27ce43dee4f	7426	lsm6dsox_mag_cfg_a_t reg;
cparata	0:f27ce43dee4f	7427	int32_t ret;
cparata	0:f27ce43dee4f	7428	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	7429	switch (reg.mag_z_axis) {
cparata	0:f27ce43dee4f	7430	case LSM6DSOX_Z_EQ_Y:
cparata	0:f27ce43dee4f	7431	*val = LSM6DSOX_Z_EQ_Y;
cparata	0:f27ce43dee4f	7432	break;
cparata	0:f27ce43dee4f	7433	case LSM6DSOX_Z_EQ_MIN_Y:
cparata	0:f27ce43dee4f	7434	*val = LSM6DSOX_Z_EQ_MIN_Y;
cparata	0:f27ce43dee4f	7435	break;
cparata	0:f27ce43dee4f	7436	case LSM6DSOX_Z_EQ_X:
cparata	0:f27ce43dee4f	7437	*val = LSM6DSOX_Z_EQ_X;
cparata	0:f27ce43dee4f	7438	break;
cparata	0:f27ce43dee4f	7439	case LSM6DSOX_Z_EQ_MIN_X:
cparata	0:f27ce43dee4f	7440	*val = LSM6DSOX_Z_EQ_MIN_X;
cparata	0:f27ce43dee4f	7441	break;
cparata	0:f27ce43dee4f	7442	case LSM6DSOX_Z_EQ_MIN_Z:
cparata	0:f27ce43dee4f	7443	*val = LSM6DSOX_Z_EQ_MIN_Z;
cparata	0:f27ce43dee4f	7444	break;
cparata	0:f27ce43dee4f	7445	case LSM6DSOX_Z_EQ_Z:
cparata	0:f27ce43dee4f	7446	*val = LSM6DSOX_Z_EQ_Z;
cparata	0:f27ce43dee4f	7447	break;
cparata	0:f27ce43dee4f	7448	default:
cparata	0:f27ce43dee4f	7449	*val = LSM6DSOX_Z_EQ_Y;
cparata	0:f27ce43dee4f	7450	break;
cparata	0:f27ce43dee4f	7451	}
cparata	0:f27ce43dee4f	7452	return ret;
cparata	0:f27ce43dee4f	7453	}
cparata	0:f27ce43dee4f	7454
cparata	0:f27ce43dee4f	7455	/**
cparata	0:f27ce43dee4f	7456	* @brief Magnetometer Y-axis coordinates
cparata	0:f27ce43dee4f	7457	* rotation (to be aligned to
cparata	0:f27ce43dee4f	7458	* accelerometer/gyroscope axes
cparata	0:f27ce43dee4f	7459	* orientation).[set]
cparata	0:f27ce43dee4f	7460	*
cparata	0:f27ce43dee4f	7461	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7462	* @param val change the values of mag_y_axis in reg MAG_CFG_A
cparata	0:f27ce43dee4f	7463	*
cparata	0:f27ce43dee4f	7464	*/
cparata	0:f27ce43dee4f	7465	int32_t lsm6dsox_mag_y_orient_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	7466	lsm6dsox_mag_y_axis_t val)
cparata	0:f27ce43dee4f	7467	{
cparata	0:f27ce43dee4f	7468	lsm6dsox_mag_cfg_a_t reg;
cparata	0:f27ce43dee4f	7469	int32_t ret;
cparata	0:f27ce43dee4f	7470
cparata	0:f27ce43dee4f	7471	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	7472	if (ret == 0) {
cparata	0:f27ce43dee4f	7473	reg.mag_y_axis = (uint8_t)val;
cparata	0:f27ce43dee4f	7474	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A,(uint8_t*) &reg);
cparata	0:f27ce43dee4f	7475	}
cparata	0:f27ce43dee4f	7476	return ret;
cparata	0:f27ce43dee4f	7477	}
cparata	0:f27ce43dee4f	7478
cparata	0:f27ce43dee4f	7479	/**
cparata	0:f27ce43dee4f	7480	* @brief Magnetometer Y-axis coordinates
cparata	0:f27ce43dee4f	7481	* rotation (to be aligned to
cparata	0:f27ce43dee4f	7482	* accelerometer/gyroscope axes
cparata	0:f27ce43dee4f	7483	* orientation).[get]
cparata	0:f27ce43dee4f	7484	*
cparata	0:f27ce43dee4f	7485	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7486	* @param val Get the values of mag_y_axis in reg MAG_CFG_A
cparata	0:f27ce43dee4f	7487	*
cparata	0:f27ce43dee4f	7488	*/
cparata	0:f27ce43dee4f	7489	int32_t lsm6dsox_mag_y_orient_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	7490	lsm6dsox_mag_y_axis_t *val)
cparata	0:f27ce43dee4f	7491	{
cparata	0:f27ce43dee4f	7492	lsm6dsox_mag_cfg_a_t reg;
cparata	0:f27ce43dee4f	7493	int32_t ret;
cparata	0:f27ce43dee4f	7494
cparata	0:f27ce43dee4f	7495	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	7496	switch (reg.mag_y_axis) {
cparata	0:f27ce43dee4f	7497	case LSM6DSOX_Y_EQ_Y:
cparata	0:f27ce43dee4f	7498	*val = LSM6DSOX_Y_EQ_Y;
cparata	0:f27ce43dee4f	7499	break;
cparata	0:f27ce43dee4f	7500	case LSM6DSOX_Y_EQ_MIN_Y:
cparata	0:f27ce43dee4f	7501	*val = LSM6DSOX_Y_EQ_MIN_Y;
cparata	0:f27ce43dee4f	7502	break;
cparata	0:f27ce43dee4f	7503	case LSM6DSOX_Y_EQ_X:
cparata	0:f27ce43dee4f	7504	*val = LSM6DSOX_Y_EQ_X;
cparata	0:f27ce43dee4f	7505	break;
cparata	0:f27ce43dee4f	7506	case LSM6DSOX_Y_EQ_MIN_X:
cparata	0:f27ce43dee4f	7507	*val = LSM6DSOX_Y_EQ_MIN_X;
cparata	0:f27ce43dee4f	7508	break;
cparata	0:f27ce43dee4f	7509	case LSM6DSOX_Y_EQ_MIN_Z:
cparata	0:f27ce43dee4f	7510	*val = LSM6DSOX_Y_EQ_MIN_Z;
cparata	0:f27ce43dee4f	7511	break;
cparata	0:f27ce43dee4f	7512	case LSM6DSOX_Y_EQ_Z:
cparata	0:f27ce43dee4f	7513	*val = LSM6DSOX_Y_EQ_Z;
cparata	0:f27ce43dee4f	7514	break;
cparata	0:f27ce43dee4f	7515	default:
cparata	0:f27ce43dee4f	7516	*val = LSM6DSOX_Y_EQ_Y;
cparata	0:f27ce43dee4f	7517	break;
cparata	0:f27ce43dee4f	7518	}
cparata	0:f27ce43dee4f	7519	return ret;
cparata	0:f27ce43dee4f	7520	}
cparata	0:f27ce43dee4f	7521
cparata	0:f27ce43dee4f	7522	/**
cparata	0:f27ce43dee4f	7523	* @brief Magnetometer X-axis coordinates
cparata	0:f27ce43dee4f	7524	* rotation (to be aligned to
cparata	0:f27ce43dee4f	7525	* accelerometer/gyroscope axes
cparata	0:f27ce43dee4f	7526	* orientation).[set]
cparata	0:f27ce43dee4f	7527	*
cparata	0:f27ce43dee4f	7528	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7529	* @param val change the values of mag_x_axis in reg MAG_CFG_B
cparata	0:f27ce43dee4f	7530	*
cparata	0:f27ce43dee4f	7531	*/
cparata	0:f27ce43dee4f	7532	int32_t lsm6dsox_mag_x_orient_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	7533	lsm6dsox_mag_x_axis_t val)
cparata	0:f27ce43dee4f	7534	{
cparata	0:f27ce43dee4f	7535	lsm6dsox_mag_cfg_b_t reg;
cparata	0:f27ce43dee4f	7536	int32_t ret;
cparata	0:f27ce43dee4f	7537
cparata	0:f27ce43dee4f	7538	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	7539	if (ret == 0) {
cparata	0:f27ce43dee4f	7540	reg.mag_x_axis = (uint8_t)val;
cparata	0:f27ce43dee4f	7541	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	7542	}
cparata	0:f27ce43dee4f	7543	return ret;
cparata	0:f27ce43dee4f	7544	}
cparata	0:f27ce43dee4f	7545
cparata	0:f27ce43dee4f	7546	/**
cparata	0:f27ce43dee4f	7547	* @brief Magnetometer X-axis coordinates
cparata	0:f27ce43dee4f	7548	* rotation (to be aligned to
cparata	0:f27ce43dee4f	7549	* accelerometer/gyroscope axes
cparata	0:f27ce43dee4f	7550	* orientation).[get]
cparata	0:f27ce43dee4f	7551	*
cparata	0:f27ce43dee4f	7552	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7553	* @param val Get the values of mag_x_axis in reg MAG_CFG_B
cparata	0:f27ce43dee4f	7554	*
cparata	0:f27ce43dee4f	7555	*/
cparata	0:f27ce43dee4f	7556	int32_t lsm6dsox_mag_x_orient_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	7557	lsm6dsox_mag_x_axis_t *val)
cparata	0:f27ce43dee4f	7558	{
cparata	0:f27ce43dee4f	7559	lsm6dsox_mag_cfg_b_t reg;
cparata	0:f27ce43dee4f	7560	int32_t ret;
cparata	0:f27ce43dee4f	7561
cparata	0:f27ce43dee4f	7562	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)&reg);
cparata	0:f27ce43dee4f	7563	switch (reg.mag_x_axis) {
cparata	0:f27ce43dee4f	7564	case LSM6DSOX_X_EQ_Y:
cparata	0:f27ce43dee4f	7565	*val = LSM6DSOX_X_EQ_Y;
cparata	0:f27ce43dee4f	7566	break;
cparata	0:f27ce43dee4f	7567	case LSM6DSOX_X_EQ_MIN_Y:
cparata	0:f27ce43dee4f	7568	*val = LSM6DSOX_X_EQ_MIN_Y;
cparata	0:f27ce43dee4f	7569	break;
cparata	0:f27ce43dee4f	7570	case LSM6DSOX_X_EQ_X:
cparata	0:f27ce43dee4f	7571	*val = LSM6DSOX_X_EQ_X;
cparata	0:f27ce43dee4f	7572	break;
cparata	0:f27ce43dee4f	7573	case LSM6DSOX_X_EQ_MIN_X:
cparata	0:f27ce43dee4f	7574	*val = LSM6DSOX_X_EQ_MIN_X;
cparata	0:f27ce43dee4f	7575	break;
cparata	0:f27ce43dee4f	7576	case LSM6DSOX_X_EQ_MIN_Z:
cparata	0:f27ce43dee4f	7577	*val = LSM6DSOX_X_EQ_MIN_Z;
cparata	0:f27ce43dee4f	7578	break;
cparata	0:f27ce43dee4f	7579	case LSM6DSOX_X_EQ_Z:
cparata	0:f27ce43dee4f	7580	*val = LSM6DSOX_X_EQ_Z;
cparata	0:f27ce43dee4f	7581	break;
cparata	0:f27ce43dee4f	7582	default:
cparata	0:f27ce43dee4f	7583	*val = LSM6DSOX_X_EQ_Y;
cparata	0:f27ce43dee4f	7584	break;
cparata	0:f27ce43dee4f	7585	}
cparata	0:f27ce43dee4f	7586	return ret;
cparata	0:f27ce43dee4f	7587	}
cparata	0:f27ce43dee4f	7588
cparata	0:f27ce43dee4f	7589	/**
cparata	0:f27ce43dee4f	7590	* @}
cparata	0:f27ce43dee4f	7591	*
cparata	0:f27ce43dee4f	7592	*/
cparata	0:f27ce43dee4f	7593
cparata	0:f27ce43dee4f	7594	/**
cparata	1:fe40aec6e97a	7595	* @defgroup LSM6DSOX_finite_state_machine
cparata	0:f27ce43dee4f	7596	* @brief This section groups all the functions that manage the
cparata	0:f27ce43dee4f	7597	* state_machine.
cparata	0:f27ce43dee4f	7598	* @{
cparata	0:f27ce43dee4f	7599	*
cparata	0:f27ce43dee4f	7600	*/
cparata	0:f27ce43dee4f	7601
cparata	0:f27ce43dee4f	7602	/**
cparata	0:f27ce43dee4f	7603	* @brief Interrupt status bit for FSM long counter
cparata	0:f27ce43dee4f	7604	* timeout interrupt event.[get]
cparata	0:f27ce43dee4f	7605	*
cparata	0:f27ce43dee4f	7606	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7607	* @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
cparata	0:f27ce43dee4f	7608	*
cparata	0:f27ce43dee4f	7609	*/
cparata	0:f27ce43dee4f	7610	int32_t lsm6dsox_long_cnt_flag_data_ready_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	7611	{
cparata	0:f27ce43dee4f	7612	lsm6dsox_emb_func_status_t reg;
cparata	0:f27ce43dee4f	7613	int32_t ret;
cparata	0:f27ce43dee4f	7614
cparata	0:f27ce43dee4f	7615	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7616	if (ret == 0) {
cparata	0:f27ce43dee4f	7617	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7618	}
cparata	0:f27ce43dee4f	7619	if (ret == 0) {
cparata	0:f27ce43dee4f	7620	*val = reg.is_fsm_lc;
cparata	0:f27ce43dee4f	7621	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7622	}
cparata	0:f27ce43dee4f	7623	return ret;
cparata	0:f27ce43dee4f	7624	}
cparata	0:f27ce43dee4f	7625
cparata	0:f27ce43dee4f	7626	/**
cparata	0:f27ce43dee4f	7627	* @brief Finite State Machine enable.[set]
cparata	0:f27ce43dee4f	7628	*
cparata	0:f27ce43dee4f	7629	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7630	* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata	0:f27ce43dee4f	7631	*
cparata	0:f27ce43dee4f	7632	*/
cparata	0:f27ce43dee4f	7633	int32_t lsm6dsox_fsm_enable_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	7634	lsm6dsox_emb_fsm_enable_t *val)
cparata	0:f27ce43dee4f	7635	{
cparata	0:f27ce43dee4f	7636	int32_t ret;
cparata	0:f27ce43dee4f	7637
cparata	0:f27ce43dee4f	7638	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7639	if (ret == 0) {
cparata	0:f27ce43dee4f	7640	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_A,
cparata	0:f27ce43dee4f	7641	(uint8_t*)&val->fsm_enable_a, 1);
cparata	0:f27ce43dee4f	7642	}
cparata	0:f27ce43dee4f	7643	if (ret == 0) {
cparata	0:f27ce43dee4f	7644	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_B,
cparata	0:f27ce43dee4f	7645	(uint8_t*)&val->fsm_enable_b, 1);
cparata	0:f27ce43dee4f	7646	}
cparata	0:f27ce43dee4f	7647	if (ret == 0) {
cparata	0:f27ce43dee4f	7648	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7649	}
cparata	0:f27ce43dee4f	7650
cparata	0:f27ce43dee4f	7651	return ret;
cparata	0:f27ce43dee4f	7652	}
cparata	0:f27ce43dee4f	7653
cparata	0:f27ce43dee4f	7654	/**
cparata	0:f27ce43dee4f	7655	* @brief Finite State Machine enable.[get]
cparata	0:f27ce43dee4f	7656	*
cparata	0:f27ce43dee4f	7657	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7658	* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata	0:f27ce43dee4f	7659	*
cparata	0:f27ce43dee4f	7660	*/
cparata	0:f27ce43dee4f	7661	int32_t lsm6dsox_fsm_enable_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	7662	lsm6dsox_emb_fsm_enable_t *val)
cparata	0:f27ce43dee4f	7663	{
cparata	0:f27ce43dee4f	7664	int32_t ret;
cparata	0:f27ce43dee4f	7665
cparata	0:f27ce43dee4f	7666	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7667	if (ret == 0) {
cparata	0:f27ce43dee4f	7668	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, (uint8_t*) val, 2);
cparata	0:f27ce43dee4f	7669	}
cparata	0:f27ce43dee4f	7670	if (ret == 0) {
cparata	0:f27ce43dee4f	7671	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7672	}
cparata	0:f27ce43dee4f	7673	return ret;
cparata	0:f27ce43dee4f	7674	}
cparata	0:f27ce43dee4f	7675
cparata	0:f27ce43dee4f	7676	/**
cparata	0:f27ce43dee4f	7677	* @brief FSM long counter status register. Long counter value is an
cparata	0:f27ce43dee4f	7678	* unsigned integer value (16-bit format).[set]
cparata	0:f27ce43dee4f	7679	*
cparata	0:f27ce43dee4f	7680	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7681	* @param buff buffer that contains data to write
cparata	0:f27ce43dee4f	7682	*
cparata	0:f27ce43dee4f	7683	*/
cparata	0:f27ce43dee4f	7684	int32_t lsm6dsox_long_cnt_set(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7685	{
cparata	0:f27ce43dee4f	7686	int32_t ret;
cparata	0:f27ce43dee4f	7687
cparata	0:f27ce43dee4f	7688	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7689	if (ret == 0) {
cparata	0:f27ce43dee4f	7690	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2);
cparata	0:f27ce43dee4f	7691	}
cparata	0:f27ce43dee4f	7692	if (ret == 0) {
cparata	0:f27ce43dee4f	7693	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7694	}
cparata	0:f27ce43dee4f	7695
cparata	0:f27ce43dee4f	7696	return ret;
cparata	0:f27ce43dee4f	7697	}
cparata	0:f27ce43dee4f	7698
cparata	0:f27ce43dee4f	7699	/**
cparata	0:f27ce43dee4f	7700	* @brief FSM long counter status register. Long counter value is an
cparata	0:f27ce43dee4f	7701	* unsigned integer value (16-bit format).[get]
cparata	0:f27ce43dee4f	7702	*
cparata	0:f27ce43dee4f	7703	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7704	* @param buff buffer that stores data read
cparata	0:f27ce43dee4f	7705	*
cparata	0:f27ce43dee4f	7706	*/
cparata	0:f27ce43dee4f	7707	int32_t lsm6dsox_long_cnt_get(lsm6dsox_ctx_t ctx, uint8_t buff)
cparata	0:f27ce43dee4f	7708	{
cparata	0:f27ce43dee4f	7709	int32_t ret;
cparata	0:f27ce43dee4f	7710
cparata	0:f27ce43dee4f	7711	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7712	if (ret == 0) {
cparata	0:f27ce43dee4f	7713	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2);
cparata	0:f27ce43dee4f	7714	}
cparata	0:f27ce43dee4f	7715	if (ret == 0) {
cparata	0:f27ce43dee4f	7716	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7717	}
cparata	0:f27ce43dee4f	7718
cparata	0:f27ce43dee4f	7719	return ret;
cparata	0:f27ce43dee4f	7720	}
cparata	0:f27ce43dee4f	7721
cparata	0:f27ce43dee4f	7722	/**
cparata	0:f27ce43dee4f	7723	* @brief Clear FSM long counter value.[set]
cparata	0:f27ce43dee4f	7724	*
cparata	0:f27ce43dee4f	7725	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7726	* @param val change the values of fsm_lc_clr in
cparata	0:f27ce43dee4f	7727	* reg FSM_LONG_COUNTER_CLEAR
cparata	0:f27ce43dee4f	7728	*
cparata	0:f27ce43dee4f	7729	*/
cparata	0:f27ce43dee4f	7730	int32_t lsm6dsox_long_clr_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val)
cparata	0:f27ce43dee4f	7731	{
cparata	0:f27ce43dee4f	7732	lsm6dsox_fsm_long_counter_clear_t reg;
cparata	0:f27ce43dee4f	7733	int32_t ret;
cparata	0:f27ce43dee4f	7734
cparata	0:f27ce43dee4f	7735	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7736	if (ret == 0) {
cparata	0:f27ce43dee4f	7737	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
cparata	0:f27ce43dee4f	7738	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7739	}
cparata	0:f27ce43dee4f	7740	if (ret == 0) {
cparata	0:f27ce43dee4f	7741	reg. fsm_lc_clr = (uint8_t)val;
cparata	0:f27ce43dee4f	7742	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
cparata	0:f27ce43dee4f	7743	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7744	}
cparata	0:f27ce43dee4f	7745	if (ret == 0) {
cparata	0:f27ce43dee4f	7746	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7747	}
cparata	0:f27ce43dee4f	7748	return ret;
cparata	0:f27ce43dee4f	7749	}
cparata	0:f27ce43dee4f	7750
cparata	0:f27ce43dee4f	7751	/**
cparata	0:f27ce43dee4f	7752	* @brief Clear FSM long counter value.[get]
cparata	0:f27ce43dee4f	7753	*
cparata	0:f27ce43dee4f	7754	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7755	* @param val Get the values of fsm_lc_clr in
cparata	0:f27ce43dee4f	7756	* reg FSM_LONG_COUNTER_CLEAR
cparata	0:f27ce43dee4f	7757	*
cparata	0:f27ce43dee4f	7758	*/
cparata	0:f27ce43dee4f	7759	int32_t lsm6dsox_long_clr_get(lsm6dsox_ctx_t ctx, lsm6dsox_fsm_lc_clr_t val)
cparata	0:f27ce43dee4f	7760	{
cparata	0:f27ce43dee4f	7761	lsm6dsox_fsm_long_counter_clear_t reg;
cparata	0:f27ce43dee4f	7762	int32_t ret;
cparata	0:f27ce43dee4f	7763
cparata	0:f27ce43dee4f	7764	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7765	if (ret == 0) {
cparata	0:f27ce43dee4f	7766	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
cparata	0:f27ce43dee4f	7767	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7768	}
cparata	0:f27ce43dee4f	7769	if (ret == 0) {
cparata	0:f27ce43dee4f	7770	switch (reg.fsm_lc_clr) {
cparata	0:f27ce43dee4f	7771	case LSM6DSOX_LC_NORMAL:
cparata	0:f27ce43dee4f	7772	*val = LSM6DSOX_LC_NORMAL;
cparata	0:f27ce43dee4f	7773	break;
cparata	0:f27ce43dee4f	7774	case LSM6DSOX_LC_CLEAR:
cparata	0:f27ce43dee4f	7775	*val = LSM6DSOX_LC_CLEAR;
cparata	0:f27ce43dee4f	7776	break;
cparata	0:f27ce43dee4f	7777	case LSM6DSOX_LC_CLEAR_DONE:
cparata	0:f27ce43dee4f	7778	*val = LSM6DSOX_LC_CLEAR_DONE;
cparata	0:f27ce43dee4f	7779	break;
cparata	0:f27ce43dee4f	7780	default:
cparata	0:f27ce43dee4f	7781	*val = LSM6DSOX_LC_NORMAL;
cparata	0:f27ce43dee4f	7782	break;
cparata	0:f27ce43dee4f	7783	}
cparata	0:f27ce43dee4f	7784	}
cparata	0:f27ce43dee4f	7785
cparata	0:f27ce43dee4f	7786	if (ret == 0) {
cparata	0:f27ce43dee4f	7787	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7788	}
cparata	0:f27ce43dee4f	7789
cparata	0:f27ce43dee4f	7790	return ret;
cparata	0:f27ce43dee4f	7791	}
cparata	0:f27ce43dee4f	7792
cparata	0:f27ce43dee4f	7793	/**
cparata	0:f27ce43dee4f	7794	* @brief FSM output registers[get]
cparata	0:f27ce43dee4f	7795	*
cparata	0:f27ce43dee4f	7796	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7797	* @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
cparata	0:f27ce43dee4f	7798	*
cparata	0:f27ce43dee4f	7799	*/
cparata	0:f27ce43dee4f	7800	int32_t lsm6dsox_fsm_out_get(lsm6dsox_ctx_t ctx, lsm6dsox_fsm_out_t val)
cparata	0:f27ce43dee4f	7801	{
cparata	0:f27ce43dee4f	7802	int32_t ret;
cparata	0:f27ce43dee4f	7803
cparata	0:f27ce43dee4f	7804	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7805	if (ret == 0) {
cparata	0:f27ce43dee4f	7806	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_OUTS1, (uint8_t*)val, 16);
cparata	0:f27ce43dee4f	7807	}
cparata	0:f27ce43dee4f	7808	if (ret == 0) {
cparata	0:f27ce43dee4f	7809	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7810	}
cparata	0:f27ce43dee4f	7811
cparata	0:f27ce43dee4f	7812	return ret;
cparata	0:f27ce43dee4f	7813	}
cparata	0:f27ce43dee4f	7814
cparata	0:f27ce43dee4f	7815	/**
cparata	0:f27ce43dee4f	7816	* @brief Finite State Machine ODR configuration.[set]
cparata	0:f27ce43dee4f	7817	*
cparata	0:f27ce43dee4f	7818	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7819	* @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata	0:f27ce43dee4f	7820	*
cparata	0:f27ce43dee4f	7821	*/
cparata	0:f27ce43dee4f	7822	int32_t lsm6dsox_fsm_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t val)
cparata	0:f27ce43dee4f	7823	{
cparata	0:f27ce43dee4f	7824	lsm6dsox_emb_func_odr_cfg_b_t reg;
cparata	0:f27ce43dee4f	7825	int32_t ret;
cparata	0:f27ce43dee4f	7826
cparata	0:f27ce43dee4f	7827	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7828	if (ret == 0) {
cparata	0:f27ce43dee4f	7829	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
cparata	0:f27ce43dee4f	7830	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7831	}
cparata	0:f27ce43dee4f	7832	if (ret == 0) {
cparata	0:f27ce43dee4f	7833	reg.not_used_01 = 3; /* set default values */
cparata	0:f27ce43dee4f	7834	reg.not_used_02 = 2; /* set default values */
cparata	0:f27ce43dee4f	7835	reg.fsm_odr = (uint8_t)val;
cparata	0:f27ce43dee4f	7836	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
cparata	0:f27ce43dee4f	7837	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7838	}
cparata	0:f27ce43dee4f	7839	if (ret == 0) {
cparata	0:f27ce43dee4f	7840	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7841	}
cparata	0:f27ce43dee4f	7842	return ret;
cparata	0:f27ce43dee4f	7843	}
cparata	0:f27ce43dee4f	7844
cparata	0:f27ce43dee4f	7845	/**
cparata	0:f27ce43dee4f	7846	* @brief Finite State Machine ODR configuration.[get]
cparata	0:f27ce43dee4f	7847	*
cparata	0:f27ce43dee4f	7848	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7849	* @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata	0:f27ce43dee4f	7850	*
cparata	0:f27ce43dee4f	7851	*/
cparata	0:f27ce43dee4f	7852	int32_t lsm6dsox_fsm_data_rate_get(lsm6dsox_ctx_t ctx, lsm6dsox_fsm_odr_t val)
cparata	0:f27ce43dee4f	7853	{
cparata	0:f27ce43dee4f	7854	lsm6dsox_emb_func_odr_cfg_b_t reg;
cparata	0:f27ce43dee4f	7855	int32_t ret;
cparata	0:f27ce43dee4f	7856
cparata	0:f27ce43dee4f	7857	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7858	if (ret == 0) {
cparata	0:f27ce43dee4f	7859	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
cparata	0:f27ce43dee4f	7860	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7861	}
cparata	0:f27ce43dee4f	7862	if (ret == 0) {
cparata	0:f27ce43dee4f	7863	switch (reg.fsm_odr) {
cparata	0:f27ce43dee4f	7864	case LSM6DSOX_ODR_FSM_12Hz5:
cparata	0:f27ce43dee4f	7865	*val = LSM6DSOX_ODR_FSM_12Hz5;
cparata	0:f27ce43dee4f	7866	break;
cparata	0:f27ce43dee4f	7867	case LSM6DSOX_ODR_FSM_26Hz:
cparata	0:f27ce43dee4f	7868	*val = LSM6DSOX_ODR_FSM_26Hz;
cparata	0:f27ce43dee4f	7869	break;
cparata	0:f27ce43dee4f	7870	case LSM6DSOX_ODR_FSM_52Hz:
cparata	0:f27ce43dee4f	7871	*val = LSM6DSOX_ODR_FSM_52Hz;
cparata	0:f27ce43dee4f	7872	break;
cparata	0:f27ce43dee4f	7873	case LSM6DSOX_ODR_FSM_104Hz:
cparata	0:f27ce43dee4f	7874	*val = LSM6DSOX_ODR_FSM_104Hz;
cparata	0:f27ce43dee4f	7875	break;
cparata	0:f27ce43dee4f	7876	default:
cparata	0:f27ce43dee4f	7877	*val = LSM6DSOX_ODR_FSM_12Hz5;
cparata	0:f27ce43dee4f	7878	break;
cparata	0:f27ce43dee4f	7879	}
cparata	0:f27ce43dee4f	7880	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7881	}
cparata	0:f27ce43dee4f	7882
cparata	0:f27ce43dee4f	7883	return ret;
cparata	0:f27ce43dee4f	7884	}
cparata	0:f27ce43dee4f	7885
cparata	0:f27ce43dee4f	7886	/**
cparata	0:f27ce43dee4f	7887	* @brief FSM initialization request.[set]
cparata	0:f27ce43dee4f	7888	*
cparata	0:f27ce43dee4f	7889	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7890	* @param val change the values of fsm_init in reg FSM_INIT
cparata	0:f27ce43dee4f	7891	*
cparata	0:f27ce43dee4f	7892	*/
cparata	0:f27ce43dee4f	7893	int32_t lsm6dsox_fsm_init_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	7894	{
cparata	0:f27ce43dee4f	7895	lsm6dsox_emb_func_init_b_t reg;
cparata	0:f27ce43dee4f	7896	int32_t ret;
cparata	0:f27ce43dee4f	7897
cparata	0:f27ce43dee4f	7898	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7899	if (ret == 0) {
cparata	0:f27ce43dee4f	7900	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7901	}
cparata	0:f27ce43dee4f	7902	if (ret == 0) {
cparata	0:f27ce43dee4f	7903	reg.fsm_init = val;
cparata	0:f27ce43dee4f	7904	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7905	}
cparata	0:f27ce43dee4f	7906	if (ret == 0) {
cparata	0:f27ce43dee4f	7907	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7908	}
cparata	0:f27ce43dee4f	7909
cparata	0:f27ce43dee4f	7910	return ret;
cparata	0:f27ce43dee4f	7911	}
cparata	0:f27ce43dee4f	7912
cparata	0:f27ce43dee4f	7913	/**
cparata	0:f27ce43dee4f	7914	* @brief FSM initialization request.[get]
cparata	0:f27ce43dee4f	7915	*
cparata	0:f27ce43dee4f	7916	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7917	* @param val change the values of fsm_init in reg FSM_INIT
cparata	0:f27ce43dee4f	7918	*
cparata	0:f27ce43dee4f	7919	*/
cparata	0:f27ce43dee4f	7920	int32_t lsm6dsox_fsm_init_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	7921	{
cparata	0:f27ce43dee4f	7922	lsm6dsox_emb_func_init_b_t reg;
cparata	0:f27ce43dee4f	7923	int32_t ret;
cparata	0:f27ce43dee4f	7924
cparata	0:f27ce43dee4f	7925	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	7926	if (ret == 0) {
cparata	0:f27ce43dee4f	7927	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	7928	}
cparata	0:f27ce43dee4f	7929	if (ret == 0) {
cparata	0:f27ce43dee4f	7930	*val = reg.fsm_init;
cparata	0:f27ce43dee4f	7931	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	7932	}
cparata	0:f27ce43dee4f	7933	return ret;
cparata	0:f27ce43dee4f	7934	}
cparata	0:f27ce43dee4f	7935
cparata	0:f27ce43dee4f	7936	/**
cparata	0:f27ce43dee4f	7937	* @brief FSM long counter timeout register (r/w). The long counter
cparata	0:f27ce43dee4f	7938	* timeout value is an unsigned integer value (16-bit format).
cparata	0:f27ce43dee4f	7939	* When the long counter value reached this value,
cparata	0:f27ce43dee4f	7940	* the FSM generates an interrupt.[set]
cparata	0:f27ce43dee4f	7941	*
cparata	0:f27ce43dee4f	7942	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7943	* @param val the value of long counter
cparata	0:f27ce43dee4f	7944	*
cparata	0:f27ce43dee4f	7945	*/
cparata	0:f27ce43dee4f	7946	int32_t lsm6dsox_long_cnt_int_value_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata	0:f27ce43dee4f	7947	{
cparata	0:f27ce43dee4f	7948	int32_t ret;
cparata	0:f27ce43dee4f	7949	uint8_t add_l;
cparata	0:f27ce43dee4f	7950	uint8_t add_h;
cparata	0:f27ce43dee4f	7951
cparata	0:f27ce43dee4f	7952	add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
cparata	0:f27ce43dee4f	7953	add_l = (uint8_t)( val & 0x00FFU );
cparata	0:f27ce43dee4f	7954
cparata	0:f27ce43dee4f	7955	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l);
cparata	0:f27ce43dee4f	7956	if (ret == 0) {
cparata	0:f27ce43dee4f	7957	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h);
cparata	0:f27ce43dee4f	7958	}
cparata	0:f27ce43dee4f	7959
cparata	0:f27ce43dee4f	7960	return ret;
cparata	0:f27ce43dee4f	7961	}
cparata	0:f27ce43dee4f	7962
cparata	0:f27ce43dee4f	7963	/**
cparata	0:f27ce43dee4f	7964	* @brief FSM long counter timeout register (r/w). The long counter
cparata	0:f27ce43dee4f	7965	* timeout value is an unsigned integer value (16-bit format).
cparata	0:f27ce43dee4f	7966	* When the long counter value reached this value,
cparata	0:f27ce43dee4f	7967	* the FSM generates an interrupt.[get]
cparata	0:f27ce43dee4f	7968	*
cparata	0:f27ce43dee4f	7969	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7970	* @param val buffer that stores the value of long counter
cparata	0:f27ce43dee4f	7971	*
cparata	0:f27ce43dee4f	7972	*/
cparata	0:f27ce43dee4f	7973	int32_t lsm6dsox_long_cnt_int_value_get(lsm6dsox_ctx_t ctx, uint16_t val)
cparata	0:f27ce43dee4f	7974	{
cparata	0:f27ce43dee4f	7975	int32_t ret;
cparata	0:f27ce43dee4f	7976	uint8_t add_l;
cparata	0:f27ce43dee4f	7977	uint8_t add_h;
cparata	0:f27ce43dee4f	7978
cparata	0:f27ce43dee4f	7979	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l);
cparata	0:f27ce43dee4f	7980	if (ret == 0) {
cparata	0:f27ce43dee4f	7981	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h);
cparata	0:f27ce43dee4f	7982	*val = add_h;
cparata	0:f27ce43dee4f	7983	val = val << 8;
cparata	0:f27ce43dee4f	7984	*val += add_l;
cparata	0:f27ce43dee4f	7985	}
cparata	0:f27ce43dee4f	7986
cparata	0:f27ce43dee4f	7987	return ret;
cparata	0:f27ce43dee4f	7988	}
cparata	0:f27ce43dee4f	7989
cparata	0:f27ce43dee4f	7990	/**
cparata	0:f27ce43dee4f	7991	* @brief FSM number of programs register.[set]
cparata	0:f27ce43dee4f	7992	*
cparata	0:f27ce43dee4f	7993	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	7994	* @param val value to write
cparata	0:f27ce43dee4f	7995	*
cparata	0:f27ce43dee4f	7996	*/
cparata	0:f27ce43dee4f	7997	int32_t lsm6dsox_fsm_number_of_programs_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	7998	{
cparata	0:f27ce43dee4f	7999	int32_t ret;
cparata	0:f27ce43dee4f	8000
cparata	0:f27ce43dee4f	8001	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_PROGRAMS, &val);
cparata	0:f27ce43dee4f	8002
cparata	0:f27ce43dee4f	8003	return ret;
cparata	0:f27ce43dee4f	8004	}
cparata	0:f27ce43dee4f	8005
cparata	0:f27ce43dee4f	8006	/**
cparata	0:f27ce43dee4f	8007	* @brief FSM number of programs register.[get]
cparata	0:f27ce43dee4f	8008	*
cparata	0:f27ce43dee4f	8009	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8010	* @param val buffer that stores data read.
cparata	0:f27ce43dee4f	8011	*
cparata	0:f27ce43dee4f	8012	*/
cparata	0:f27ce43dee4f	8013	int32_t lsm6dsox_fsm_number_of_programs_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	8014	{
cparata	0:f27ce43dee4f	8015	int32_t ret;
cparata	0:f27ce43dee4f	8016
cparata	0:f27ce43dee4f	8017	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_PROGRAMS, val);
cparata	0:f27ce43dee4f	8018
cparata	0:f27ce43dee4f	8019	return ret;
cparata	0:f27ce43dee4f	8020	}
cparata	0:f27ce43dee4f	8021
cparata	0:f27ce43dee4f	8022	/**
cparata	0:f27ce43dee4f	8023	* @brief FSM start address register (r/w).
cparata	0:f27ce43dee4f	8024	* First available address is 0x033C.[set]
cparata	0:f27ce43dee4f	8025	*
cparata	0:f27ce43dee4f	8026	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8027	* @param val the value of start address
cparata	0:f27ce43dee4f	8028	*
cparata	0:f27ce43dee4f	8029	*/
cparata	0:f27ce43dee4f	8030	int32_t lsm6dsox_fsm_start_address_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata	0:f27ce43dee4f	8031	{
cparata	0:f27ce43dee4f	8032	int32_t ret;
cparata	0:f27ce43dee4f	8033	uint8_t add_l;
cparata	0:f27ce43dee4f	8034	uint8_t add_h;
cparata	0:f27ce43dee4f	8035
cparata	0:f27ce43dee4f	8036	add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
cparata	0:f27ce43dee4f	8037	add_l = (uint8_t)( val & 0x00FFU );
cparata	0:f27ce43dee4f	8038
cparata	0:f27ce43dee4f	8039	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l);
cparata	0:f27ce43dee4f	8040	if (ret == 0) {
cparata	0:f27ce43dee4f	8041	ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h);
cparata	0:f27ce43dee4f	8042	}
cparata	0:f27ce43dee4f	8043	return ret;
cparata	0:f27ce43dee4f	8044	}
cparata	0:f27ce43dee4f	8045
cparata	0:f27ce43dee4f	8046	/**
cparata	0:f27ce43dee4f	8047	* @brief FSM start address register (r/w).
cparata	0:f27ce43dee4f	8048	* First available address is 0x033C.[get]
cparata	0:f27ce43dee4f	8049	*
cparata	0:f27ce43dee4f	8050	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8051	* @param val buffer the value of start address.
cparata	0:f27ce43dee4f	8052	*
cparata	0:f27ce43dee4f	8053	*/
cparata	0:f27ce43dee4f	8054	int32_t lsm6dsox_fsm_start_address_get(lsm6dsox_ctx_t ctx, uint16_t val)
cparata	0:f27ce43dee4f	8055	{
cparata	0:f27ce43dee4f	8056	int32_t ret;
cparata	0:f27ce43dee4f	8057	uint8_t add_l;
cparata	0:f27ce43dee4f	8058	uint8_t add_h;
cparata	0:f27ce43dee4f	8059
cparata	0:f27ce43dee4f	8060	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l);
cparata	0:f27ce43dee4f	8061	if (ret == 0) {
cparata	0:f27ce43dee4f	8062	ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h);
cparata	0:f27ce43dee4f	8063	*val = add_h;
cparata	0:f27ce43dee4f	8064	val = val << 8;
cparata	0:f27ce43dee4f	8065	*val += add_l;
cparata	0:f27ce43dee4f	8066	}
cparata	0:f27ce43dee4f	8067	return ret;
cparata	0:f27ce43dee4f	8068	}
cparata	0:f27ce43dee4f	8069
cparata	0:f27ce43dee4f	8070	/**
cparata	0:f27ce43dee4f	8071	* @}
cparata	0:f27ce43dee4f	8072	*
cparata	0:f27ce43dee4f	8073	*/
cparata	0:f27ce43dee4f	8074
cparata	0:f27ce43dee4f	8075	/**
cparata	0:f27ce43dee4f	8076	* @addtogroup Machine Learning Core
cparata	0:f27ce43dee4f	8077	* @brief This section group all the functions concerning the
cparata	0:f27ce43dee4f	8078	* usage of Machine Learning Core
cparata	0:f27ce43dee4f	8079	* @{
cparata	0:f27ce43dee4f	8080	*
cparata	0:f27ce43dee4f	8081	*/
cparata	0:f27ce43dee4f	8082
cparata	0:f27ce43dee4f	8083	/**
cparata	0:f27ce43dee4f	8084	* @brief Machine Learning Core status register[get]
cparata	0:f27ce43dee4f	8085	*
cparata	0:f27ce43dee4f	8086	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8087	* @param val register MLC_STATUS_MAINPAGE
cparata	0:f27ce43dee4f	8088	*
cparata	0:f27ce43dee4f	8089	*/
cparata	0:f27ce43dee4f	8090	int32_t lsm6dsox_mlc_status_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8091	lsm6dsox_mlc_status_mainpage_t *val)
cparata	0:f27ce43dee4f	8092	{
cparata	0:f27ce43dee4f	8093	return lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_STATUS_MAINPAGE,
cparata	0:f27ce43dee4f	8094	(uint8_t*) val, 1);
cparata	0:f27ce43dee4f	8095	}
cparata	0:f27ce43dee4f	8096
cparata	0:f27ce43dee4f	8097	/**
cparata	0:f27ce43dee4f	8098	* @brief Machine Learning Core data rate selection.[set]
cparata	0:f27ce43dee4f	8099	*
cparata	0:f27ce43dee4f	8100	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8101	* @param val get the values of mlc_odr in
cparata	0:f27ce43dee4f	8102	* reg EMB_FUNC_ODR_CFG_C
cparata	0:f27ce43dee4f	8103	*
cparata	0:f27ce43dee4f	8104	*/
cparata	0:f27ce43dee4f	8105	int32_t lsm6dsox_mlc_data_rate_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8106	lsm6dsox_mlc_odr_t val)
cparata	0:f27ce43dee4f	8107	{
cparata	0:f27ce43dee4f	8108	lsm6dsox_emb_func_odr_cfg_c_t reg;
cparata	0:f27ce43dee4f	8109	int32_t ret;
cparata	0:f27ce43dee4f	8110
cparata	0:f27ce43dee4f	8111	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	0:f27ce43dee4f	8112	if (ret == 0) {
cparata	0:f27ce43dee4f	8113	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
cparata	0:f27ce43dee4f	8114	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8115	}
cparata	0:f27ce43dee4f	8116	if (ret == 0) {
cparata	0:f27ce43dee4f	8117	reg.mlc_odr = (uint8_t)val;
cparata	0:f27ce43dee4f	8118	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8119	}
cparata	0:f27ce43dee4f	8120	if (ret == 0) {
cparata	0:f27ce43dee4f	8121	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8122	}
cparata	0:f27ce43dee4f	8123
cparata	0:f27ce43dee4f	8124	return ret;
cparata	0:f27ce43dee4f	8125	}
cparata	0:f27ce43dee4f	8126
cparata	0:f27ce43dee4f	8127	/**
cparata	0:f27ce43dee4f	8128	* @brief Machine Learning Core data rate selection.[get]
cparata	0:f27ce43dee4f	8129	*
cparata	0:f27ce43dee4f	8130	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8131	* @param val change the values of mlc_odr in
cparata	0:f27ce43dee4f	8132	* reg EMB_FUNC_ODR_CFG_C
cparata	0:f27ce43dee4f	8133	*
cparata	0:f27ce43dee4f	8134	*/
cparata	0:f27ce43dee4f	8135	int32_t lsm6dsox_mlc_data_rate_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8136	lsm6dsox_mlc_odr_t *val)
cparata	0:f27ce43dee4f	8137	{
cparata	0:f27ce43dee4f	8138	lsm6dsox_emb_func_odr_cfg_c_t reg;
cparata	0:f27ce43dee4f	8139	int32_t ret;
cparata	0:f27ce43dee4f	8140
cparata	0:f27ce43dee4f	8141	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	8142	if (ret == 0) {
cparata	1:fe40aec6e97a	8143	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
cparata	0:f27ce43dee4f	8144	(uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8145	}
cparata	0:f27ce43dee4f	8146	if (ret == 0) {
cparata	0:f27ce43dee4f	8147	switch (reg.mlc_odr) {
cparata	0:f27ce43dee4f	8148	case LSM6DSOX_ODR_PRGS_12Hz5:
cparata	0:f27ce43dee4f	8149	*val = LSM6DSOX_ODR_PRGS_12Hz5;
cparata	0:f27ce43dee4f	8150	break;
cparata	0:f27ce43dee4f	8151	case LSM6DSOX_ODR_PRGS_26Hz:
cparata	0:f27ce43dee4f	8152	*val = LSM6DSOX_ODR_PRGS_26Hz;
cparata	0:f27ce43dee4f	8153	break;
cparata	0:f27ce43dee4f	8154	case LSM6DSOX_ODR_PRGS_52Hz:
cparata	0:f27ce43dee4f	8155	*val = LSM6DSOX_ODR_PRGS_52Hz;
cparata	0:f27ce43dee4f	8156	break;
cparata	0:f27ce43dee4f	8157	case LSM6DSOX_ODR_PRGS_104Hz:
cparata	0:f27ce43dee4f	8158	*val = LSM6DSOX_ODR_PRGS_104Hz;
cparata	0:f27ce43dee4f	8159	break;
cparata	0:f27ce43dee4f	8160	default:
cparata	0:f27ce43dee4f	8161	*val = LSM6DSOX_ODR_PRGS_12Hz5;
cparata	0:f27ce43dee4f	8162	break;
cparata	0:f27ce43dee4f	8163	}
cparata	0:f27ce43dee4f	8164	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8165	}
cparata	0:f27ce43dee4f	8166	return ret;
cparata	0:f27ce43dee4f	8167	}
cparata	0:f27ce43dee4f	8168
cparata	0:f27ce43dee4f	8169	/**
cparata	0:f27ce43dee4f	8170	* @}
cparata	0:f27ce43dee4f	8171	*
cparata	0:f27ce43dee4f	8172	*/
cparata	0:f27ce43dee4f	8173
cparata	0:f27ce43dee4f	8174	/**
cparata	0:f27ce43dee4f	8175	* @defgroup LSM6DSOX_Sensor_hub
cparata	0:f27ce43dee4f	8176	* @brief This section groups all the functions that manage the
cparata	0:f27ce43dee4f	8177	* sensor hub.
cparata	0:f27ce43dee4f	8178	* @{
cparata	0:f27ce43dee4f	8179	*
cparata	0:f27ce43dee4f	8180	*/
cparata	0:f27ce43dee4f	8181
cparata	0:f27ce43dee4f	8182	/**
cparata	0:f27ce43dee4f	8183	* @brief Sensor hub output registers.[get]
cparata	0:f27ce43dee4f	8184	*
cparata	0:f27ce43dee4f	8185	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8186	* @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
cparata	0:f27ce43dee4f	8187	*
cparata	0:f27ce43dee4f	8188	*/
cparata	0:f27ce43dee4f	8189	int32_t lsm6dsox_sh_read_data_raw_get(lsm6dsox_ctx_t *ctx,
cparata	1:fe40aec6e97a	8190	lsm6dsox_emb_sh_read_t *val,
cparata	1:fe40aec6e97a	8191	uint8_t len)
cparata	0:f27ce43dee4f	8192	{
cparata	0:f27ce43dee4f	8193	int32_t ret;
cparata	0:f27ce43dee4f	8194
cparata	0:f27ce43dee4f	8195	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8196	if (ret == 0) {
cparata	1:fe40aec6e97a	8197	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SENSOR_HUB_1, (uint8_t*) val, len);
cparata	0:f27ce43dee4f	8198	}
cparata	0:f27ce43dee4f	8199	if (ret == 0) {
cparata	0:f27ce43dee4f	8200	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8201	}
cparata	0:f27ce43dee4f	8202
cparata	0:f27ce43dee4f	8203	return ret;
cparata	0:f27ce43dee4f	8204	}
cparata	0:f27ce43dee4f	8205
cparata	0:f27ce43dee4f	8206	/**
cparata	0:f27ce43dee4f	8207	* @brief Number of external sensors to be read by the sensor hub.[set]
cparata	0:f27ce43dee4f	8208	*
cparata	0:f27ce43dee4f	8209	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8210	* @param val change the values of aux_sens_on in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8211	*
cparata	0:f27ce43dee4f	8212	*/
cparata	0:f27ce43dee4f	8213	int32_t lsm6dsox_sh_slave_connected_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8214	lsm6dsox_aux_sens_on_t val)
cparata	0:f27ce43dee4f	8215	{
cparata	0:f27ce43dee4f	8216	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8217	int32_t ret;
cparata	0:f27ce43dee4f	8218
cparata	0:f27ce43dee4f	8219	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8220	if (ret == 0) {
cparata	0:f27ce43dee4f	8221	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8222	}
cparata	0:f27ce43dee4f	8223	if (ret == 0) {
cparata	0:f27ce43dee4f	8224	reg.aux_sens_on = (uint8_t)val;
cparata	0:f27ce43dee4f	8225	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8226	}
cparata	0:f27ce43dee4f	8227	if (ret == 0) {
cparata	0:f27ce43dee4f	8228	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8229	}
cparata	0:f27ce43dee4f	8230	return ret;
cparata	0:f27ce43dee4f	8231	}
cparata	0:f27ce43dee4f	8232
cparata	0:f27ce43dee4f	8233	/**
cparata	0:f27ce43dee4f	8234	* @brief Number of external sensors to be read by the sensor hub.[get]
cparata	0:f27ce43dee4f	8235	*
cparata	0:f27ce43dee4f	8236	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8237	* @param val Get the values of aux_sens_on in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8238	*
cparata	0:f27ce43dee4f	8239	*/
cparata	0:f27ce43dee4f	8240	int32_t lsm6dsox_sh_slave_connected_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8241	lsm6dsox_aux_sens_on_t *val)
cparata	0:f27ce43dee4f	8242	{
cparata	0:f27ce43dee4f	8243	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8244	int32_t ret;
cparata	0:f27ce43dee4f	8245
cparata	0:f27ce43dee4f	8246	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8247	if (ret == 0) {
cparata	0:f27ce43dee4f	8248	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8249	}
cparata	0:f27ce43dee4f	8250	if (ret == 0) {
cparata	0:f27ce43dee4f	8251	switch (reg.aux_sens_on) {
cparata	0:f27ce43dee4f	8252	case LSM6DSOX_SLV_0:
cparata	0:f27ce43dee4f	8253	*val = LSM6DSOX_SLV_0;
cparata	0:f27ce43dee4f	8254	break;
cparata	0:f27ce43dee4f	8255	case LSM6DSOX_SLV_0_1:
cparata	0:f27ce43dee4f	8256	*val = LSM6DSOX_SLV_0_1;
cparata	0:f27ce43dee4f	8257	break;
cparata	0:f27ce43dee4f	8258	case LSM6DSOX_SLV_0_1_2:
cparata	0:f27ce43dee4f	8259	*val = LSM6DSOX_SLV_0_1_2;
cparata	0:f27ce43dee4f	8260	break;
cparata	0:f27ce43dee4f	8261	case LSM6DSOX_SLV_0_1_2_3:
cparata	0:f27ce43dee4f	8262	*val = LSM6DSOX_SLV_0_1_2_3;
cparata	0:f27ce43dee4f	8263	break;
cparata	0:f27ce43dee4f	8264	default:
cparata	0:f27ce43dee4f	8265	*val = LSM6DSOX_SLV_0;
cparata	0:f27ce43dee4f	8266	break;
cparata	0:f27ce43dee4f	8267	}
cparata	0:f27ce43dee4f	8268	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8269	}
cparata	0:f27ce43dee4f	8270
cparata	0:f27ce43dee4f	8271	return ret;
cparata	0:f27ce43dee4f	8272	}
cparata	0:f27ce43dee4f	8273
cparata	0:f27ce43dee4f	8274	/**
cparata	0:f27ce43dee4f	8275	* @brief Sensor hub I2C master enable.[set]
cparata	0:f27ce43dee4f	8276	*
cparata	0:f27ce43dee4f	8277	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8278	* @param val change the values of master_on in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8279	*
cparata	0:f27ce43dee4f	8280	*/
cparata	0:f27ce43dee4f	8281	int32_t lsm6dsox_sh_master_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	8282	{
cparata	0:f27ce43dee4f	8283	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8284	int32_t ret;
cparata	0:f27ce43dee4f	8285
cparata	0:f27ce43dee4f	8286	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8287	if (ret == 0) {
cparata	0:f27ce43dee4f	8288	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8289	}
cparata	0:f27ce43dee4f	8290	if (ret == 0) {
cparata	0:f27ce43dee4f	8291	reg.master_on = val;
cparata	0:f27ce43dee4f	8292	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8293	}
cparata	0:f27ce43dee4f	8294	if (ret == 0) {
cparata	0:f27ce43dee4f	8295	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8296	}
cparata	0:f27ce43dee4f	8297	return ret;
cparata	0:f27ce43dee4f	8298	}
cparata	0:f27ce43dee4f	8299
cparata	0:f27ce43dee4f	8300	/**
cparata	0:f27ce43dee4f	8301	* @brief Sensor hub I2C master enable.[get]
cparata	0:f27ce43dee4f	8302	*
cparata	0:f27ce43dee4f	8303	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8304	* @param val change the values of master_on in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8305	*
cparata	0:f27ce43dee4f	8306	*/
cparata	0:f27ce43dee4f	8307	int32_t lsm6dsox_sh_master_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	8308	{
cparata	0:f27ce43dee4f	8309	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8310	int32_t ret;
cparata	0:f27ce43dee4f	8311
cparata	0:f27ce43dee4f	8312	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8313	if (ret == 0) {
cparata	0:f27ce43dee4f	8314	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8315	}
cparata	0:f27ce43dee4f	8316	if (ret == 0) {
cparata	0:f27ce43dee4f	8317	*val = reg.master_on;
cparata	0:f27ce43dee4f	8318	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8319	}
cparata	0:f27ce43dee4f	8320
cparata	0:f27ce43dee4f	8321	return ret;
cparata	0:f27ce43dee4f	8322	}
cparata	0:f27ce43dee4f	8323
cparata	0:f27ce43dee4f	8324	/**
cparata	0:f27ce43dee4f	8325	* @brief Master I2C pull-up enable.[set]
cparata	0:f27ce43dee4f	8326	*
cparata	0:f27ce43dee4f	8327	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8328	* @param val change the values of shub_pu_en in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8329	*
cparata	0:f27ce43dee4f	8330	*/
cparata	0:f27ce43dee4f	8331	int32_t lsm6dsox_sh_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_pu_en_t val)
cparata	0:f27ce43dee4f	8332	{
cparata	0:f27ce43dee4f	8333	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8334	int32_t ret;
cparata	0:f27ce43dee4f	8335
cparata	0:f27ce43dee4f	8336	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8337	if (ret == 0) {
cparata	0:f27ce43dee4f	8338	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8339	}
cparata	0:f27ce43dee4f	8340	if (ret == 0) {
cparata	0:f27ce43dee4f	8341	reg.shub_pu_en = (uint8_t)val;
cparata	0:f27ce43dee4f	8342	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8343	}
cparata	0:f27ce43dee4f	8344	if (ret == 0) {
cparata	0:f27ce43dee4f	8345	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8346	}
cparata	0:f27ce43dee4f	8347
cparata	0:f27ce43dee4f	8348	return ret;
cparata	0:f27ce43dee4f	8349	}
cparata	0:f27ce43dee4f	8350
cparata	0:f27ce43dee4f	8351	/**
cparata	0:f27ce43dee4f	8352	* @brief Master I2C pull-up enable.[get]
cparata	0:f27ce43dee4f	8353	*
cparata	0:f27ce43dee4f	8354	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8355	* @param val Get the values of shub_pu_en in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8356	*
cparata	0:f27ce43dee4f	8357	*/
cparata	0:f27ce43dee4f	8358	int32_t lsm6dsox_sh_pin_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8359	lsm6dsox_shub_pu_en_t *val)
cparata	0:f27ce43dee4f	8360	{
cparata	0:f27ce43dee4f	8361	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8362	int32_t ret;
cparata	0:f27ce43dee4f	8363
cparata	0:f27ce43dee4f	8364	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8365	if (ret == 0) {
cparata	0:f27ce43dee4f	8366	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8367	}
cparata	0:f27ce43dee4f	8368	if (ret == 0) {
cparata	0:f27ce43dee4f	8369	switch (reg.shub_pu_en) {
cparata	0:f27ce43dee4f	8370	case LSM6DSOX_EXT_PULL_UP:
cparata	0:f27ce43dee4f	8371	*val = LSM6DSOX_EXT_PULL_UP;
cparata	0:f27ce43dee4f	8372	break;
cparata	0:f27ce43dee4f	8373	case LSM6DSOX_INTERNAL_PULL_UP:
cparata	0:f27ce43dee4f	8374	*val = LSM6DSOX_INTERNAL_PULL_UP;
cparata	0:f27ce43dee4f	8375	break;
cparata	0:f27ce43dee4f	8376	default:
cparata	0:f27ce43dee4f	8377	*val = LSM6DSOX_EXT_PULL_UP;
cparata	0:f27ce43dee4f	8378	break;
cparata	0:f27ce43dee4f	8379	}
cparata	0:f27ce43dee4f	8380	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8381	}
cparata	0:f27ce43dee4f	8382
cparata	0:f27ce43dee4f	8383	return ret;
cparata	0:f27ce43dee4f	8384	}
cparata	0:f27ce43dee4f	8385
cparata	0:f27ce43dee4f	8386	/**
cparata	0:f27ce43dee4f	8387	* @brief I2C interface pass-through.[set]
cparata	0:f27ce43dee4f	8388	*
cparata	0:f27ce43dee4f	8389	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8390	* @param val change the values of pass_through_mode in
cparata	0:f27ce43dee4f	8391	* reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8392	*
cparata	0:f27ce43dee4f	8393	*/
cparata	0:f27ce43dee4f	8394	int32_t lsm6dsox_sh_pass_through_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	8395	{
cparata	0:f27ce43dee4f	8396	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8397	int32_t ret;
cparata	0:f27ce43dee4f	8398
cparata	0:f27ce43dee4f	8399	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8400	if (ret == 0) {
cparata	0:f27ce43dee4f	8401	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8402	}
cparata	0:f27ce43dee4f	8403	if (ret == 0) {
cparata	0:f27ce43dee4f	8404	reg.pass_through_mode = val;
cparata	0:f27ce43dee4f	8405	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8406	}
cparata	0:f27ce43dee4f	8407	if (ret == 0) {
cparata	0:f27ce43dee4f	8408	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8409	}
cparata	0:f27ce43dee4f	8410
cparata	0:f27ce43dee4f	8411	return ret;
cparata	0:f27ce43dee4f	8412	}
cparata	0:f27ce43dee4f	8413
cparata	0:f27ce43dee4f	8414	/**
cparata	0:f27ce43dee4f	8415	* @brief I2C interface pass-through.[get]
cparata	0:f27ce43dee4f	8416	*
cparata	0:f27ce43dee4f	8417	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8418	* @param val change the values of pass_through_mode in
cparata	0:f27ce43dee4f	8419	* reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8420	*
cparata	0:f27ce43dee4f	8421	*/
cparata	0:f27ce43dee4f	8422	int32_t lsm6dsox_sh_pass_through_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	8423	{
cparata	0:f27ce43dee4f	8424	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8425	int32_t ret;
cparata	0:f27ce43dee4f	8426
cparata	0:f27ce43dee4f	8427	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8428	if (ret == 0) {
cparata	0:f27ce43dee4f	8429	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8430	}
cparata	0:f27ce43dee4f	8431	if (ret == 0) {
cparata	0:f27ce43dee4f	8432	*val = reg.pass_through_mode;
cparata	0:f27ce43dee4f	8433	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8434	}
cparata	0:f27ce43dee4f	8435
cparata	0:f27ce43dee4f	8436	return ret;
cparata	0:f27ce43dee4f	8437	}
cparata	0:f27ce43dee4f	8438
cparata	0:f27ce43dee4f	8439	/**
cparata	0:f27ce43dee4f	8440	* @brief Sensor hub trigger signal selection.[set]
cparata	0:f27ce43dee4f	8441	*
cparata	0:f27ce43dee4f	8442	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8443	* @param val change the values of start_config in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8444	*
cparata	0:f27ce43dee4f	8445	*/
cparata	0:f27ce43dee4f	8446	int32_t lsm6dsox_sh_syncro_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8447	lsm6dsox_start_config_t val)
cparata	0:f27ce43dee4f	8448	{
cparata	0:f27ce43dee4f	8449	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8450	int32_t ret;
cparata	0:f27ce43dee4f	8451
cparata	0:f27ce43dee4f	8452	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8453	if (ret == 0) {
cparata	0:f27ce43dee4f	8454	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8455	}
cparata	0:f27ce43dee4f	8456	if (ret == 0) {
cparata	0:f27ce43dee4f	8457	reg.start_config = (uint8_t)val;
cparata	0:f27ce43dee4f	8458	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8459	}
cparata	0:f27ce43dee4f	8460	if (ret == 0) {
cparata	0:f27ce43dee4f	8461	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8462	}
cparata	0:f27ce43dee4f	8463
cparata	0:f27ce43dee4f	8464	return ret;
cparata	0:f27ce43dee4f	8465	}
cparata	0:f27ce43dee4f	8466
cparata	0:f27ce43dee4f	8467	/**
cparata	0:f27ce43dee4f	8468	* @brief Sensor hub trigger signal selection.[get]
cparata	0:f27ce43dee4f	8469	*
cparata	0:f27ce43dee4f	8470	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8471	* @param val Get the values of start_config in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8472	*
cparata	0:f27ce43dee4f	8473	*/
cparata	0:f27ce43dee4f	8474	int32_t lsm6dsox_sh_syncro_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8475	lsm6dsox_start_config_t *val)
cparata	0:f27ce43dee4f	8476	{
cparata	0:f27ce43dee4f	8477	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8478	int32_t ret;
cparata	0:f27ce43dee4f	8479
cparata	0:f27ce43dee4f	8480	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8481	if (ret == 0) {
cparata	0:f27ce43dee4f	8482	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8483	}
cparata	0:f27ce43dee4f	8484	if (ret == 0) {
cparata	0:f27ce43dee4f	8485	switch (reg.start_config) {
cparata	0:f27ce43dee4f	8486	case LSM6DSOX_EXT_ON_INT2_PIN:
cparata	0:f27ce43dee4f	8487	*val = LSM6DSOX_EXT_ON_INT2_PIN;
cparata	0:f27ce43dee4f	8488	break;
cparata	0:f27ce43dee4f	8489	case LSM6DSOX_XL_GY_DRDY:
cparata	0:f27ce43dee4f	8490	*val = LSM6DSOX_XL_GY_DRDY;
cparata	0:f27ce43dee4f	8491	break;
cparata	0:f27ce43dee4f	8492	default:
cparata	0:f27ce43dee4f	8493	*val = LSM6DSOX_EXT_ON_INT2_PIN;
cparata	0:f27ce43dee4f	8494	break;
cparata	0:f27ce43dee4f	8495	}
cparata	0:f27ce43dee4f	8496	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8497	}
cparata	0:f27ce43dee4f	8498	return ret;
cparata	0:f27ce43dee4f	8499	}
cparata	0:f27ce43dee4f	8500
cparata	0:f27ce43dee4f	8501	/**
cparata	0:f27ce43dee4f	8502	* @brief Slave 0 write operation is performed only at the first
cparata	0:f27ce43dee4f	8503	* sensor hub cycle.[set]
cparata	0:f27ce43dee4f	8504	*
cparata	0:f27ce43dee4f	8505	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8506	* @param val change the values of write_once in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8507	*
cparata	0:f27ce43dee4f	8508	*/
cparata	0:f27ce43dee4f	8509	int32_t lsm6dsox_sh_write_mode_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8510	lsm6dsox_write_once_t val)
cparata	0:f27ce43dee4f	8511	{
cparata	0:f27ce43dee4f	8512	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8513	int32_t ret;
cparata	0:f27ce43dee4f	8514
cparata	0:f27ce43dee4f	8515	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8516	if (ret == 0) {
cparata	0:f27ce43dee4f	8517	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8518	}
cparata	0:f27ce43dee4f	8519	if (ret == 0) {
cparata	0:f27ce43dee4f	8520	reg.write_once = (uint8_t)val;
cparata	0:f27ce43dee4f	8521	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8522	}
cparata	0:f27ce43dee4f	8523	if (ret == 0) {
cparata	0:f27ce43dee4f	8524	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8525	}
cparata	0:f27ce43dee4f	8526
cparata	0:f27ce43dee4f	8527	return ret;
cparata	0:f27ce43dee4f	8528	}
cparata	0:f27ce43dee4f	8529
cparata	0:f27ce43dee4f	8530	/**
cparata	0:f27ce43dee4f	8531	* @brief Slave 0 write operation is performed only at the first sensor
cparata	0:f27ce43dee4f	8532	* hub cycle.[get]
cparata	0:f27ce43dee4f	8533	*
cparata	0:f27ce43dee4f	8534	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8535	* @param val Get the values of write_once in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8536	*
cparata	0:f27ce43dee4f	8537	*/
cparata	0:f27ce43dee4f	8538	int32_t lsm6dsox_sh_write_mode_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8539	lsm6dsox_write_once_t *val)
cparata	0:f27ce43dee4f	8540	{
cparata	0:f27ce43dee4f	8541	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8542	int32_t ret;
cparata	0:f27ce43dee4f	8543
cparata	0:f27ce43dee4f	8544	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8545	if (ret == 0) {
cparata	0:f27ce43dee4f	8546	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8547	}
cparata	0:f27ce43dee4f	8548	if (ret == 0) {
cparata	0:f27ce43dee4f	8549	switch (reg.write_once) {
cparata	0:f27ce43dee4f	8550	case LSM6DSOX_EACH_SH_CYCLE:
cparata	0:f27ce43dee4f	8551	*val = LSM6DSOX_EACH_SH_CYCLE;
cparata	0:f27ce43dee4f	8552	break;
cparata	0:f27ce43dee4f	8553	case LSM6DSOX_ONLY_FIRST_CYCLE:
cparata	0:f27ce43dee4f	8554	*val = LSM6DSOX_ONLY_FIRST_CYCLE;
cparata	0:f27ce43dee4f	8555	break;
cparata	0:f27ce43dee4f	8556	default:
cparata	0:f27ce43dee4f	8557	*val = LSM6DSOX_EACH_SH_CYCLE;
cparata	0:f27ce43dee4f	8558	break;
cparata	0:f27ce43dee4f	8559	}
cparata	0:f27ce43dee4f	8560	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8561	}
cparata	0:f27ce43dee4f	8562
cparata	0:f27ce43dee4f	8563	return ret;
cparata	0:f27ce43dee4f	8564	}
cparata	0:f27ce43dee4f	8565
cparata	0:f27ce43dee4f	8566	/**
cparata	0:f27ce43dee4f	8567	* @brief Reset Master logic and output registers.[set]
cparata	0:f27ce43dee4f	8568	*
cparata	0:f27ce43dee4f	8569	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8570	*
cparata	0:f27ce43dee4f	8571	*/
cparata	0:f27ce43dee4f	8572	int32_t lsm6dsox_sh_reset_set(lsm6dsox_ctx_t *ctx)
cparata	0:f27ce43dee4f	8573	{
cparata	0:f27ce43dee4f	8574	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8575	int32_t ret;
cparata	0:f27ce43dee4f	8576
cparata	0:f27ce43dee4f	8577	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8578	if (ret == 0) {
cparata	0:f27ce43dee4f	8579	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8580	}
cparata	0:f27ce43dee4f	8581	if (ret == 0) {
cparata	0:f27ce43dee4f	8582	reg.rst_master_regs = PROPERTY_ENABLE;
cparata	0:f27ce43dee4f	8583	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8584	}
cparata	0:f27ce43dee4f	8585	if (ret == 0) {
cparata	0:f27ce43dee4f	8586	reg.rst_master_regs = PROPERTY_DISABLE;
cparata	0:f27ce43dee4f	8587	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8588	}
cparata	0:f27ce43dee4f	8589	if (ret == 0) {
cparata	0:f27ce43dee4f	8590	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8591	}
cparata	0:f27ce43dee4f	8592
cparata	0:f27ce43dee4f	8593	return ret;
cparata	0:f27ce43dee4f	8594	}
cparata	0:f27ce43dee4f	8595
cparata	0:f27ce43dee4f	8596	/**
cparata	0:f27ce43dee4f	8597	* @brief Reset Master logic and output registers.[get]
cparata	0:f27ce43dee4f	8598	*
cparata	0:f27ce43dee4f	8599	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8600	* @param val change the values of rst_master_regs in reg MASTER_CONFIG
cparata	0:f27ce43dee4f	8601	*
cparata	0:f27ce43dee4f	8602	*/
cparata	0:f27ce43dee4f	8603	int32_t lsm6dsox_sh_reset_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	8604	{
cparata	0:f27ce43dee4f	8605	lsm6dsox_master_config_t reg;
cparata	0:f27ce43dee4f	8606	int32_t ret;
cparata	0:f27ce43dee4f	8607
cparata	0:f27ce43dee4f	8608	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8609	if (ret == 0) {
cparata	0:f27ce43dee4f	8610	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8611	}
cparata	0:f27ce43dee4f	8612	if (ret == 0) {
cparata	0:f27ce43dee4f	8613	*val = reg.rst_master_regs;
cparata	0:f27ce43dee4f	8614	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8615	}
cparata	0:f27ce43dee4f	8616	return ret;
cparata	0:f27ce43dee4f	8617	}
cparata	0:f27ce43dee4f	8618
cparata	0:f27ce43dee4f	8619	/**
cparata	0:f27ce43dee4f	8620	* @brief Rate at which the master communicates.[set]
cparata	0:f27ce43dee4f	8621	*
cparata	0:f27ce43dee4f	8622	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8623	* @param val change the values of shub_odr in reg slv1_CONFIG
cparata	0:f27ce43dee4f	8624	*
cparata	0:f27ce43dee4f	8625	*/
cparata	0:f27ce43dee4f	8626	int32_t lsm6dsox_sh_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_odr_t val)
cparata	0:f27ce43dee4f	8627	{
cparata	0:f27ce43dee4f	8628	lsm6dsox_slv0_config_t reg;
cparata	0:f27ce43dee4f	8629	int32_t ret;
cparata	0:f27ce43dee4f	8630
cparata	0:f27ce43dee4f	8631	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8632	if (ret == 0) {
cparata	1:fe40aec6e97a	8633	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8634	}
cparata	0:f27ce43dee4f	8635	if (ret == 0) {
cparata	0:f27ce43dee4f	8636	reg.shub_odr = (uint8_t)val;
cparata	1:fe40aec6e97a	8637	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8638	}
cparata	0:f27ce43dee4f	8639	if (ret == 0) {
cparata	0:f27ce43dee4f	8640	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8641	}
cparata	0:f27ce43dee4f	8642
cparata	0:f27ce43dee4f	8643	return ret;
cparata	0:f27ce43dee4f	8644	}
cparata	0:f27ce43dee4f	8645
cparata	0:f27ce43dee4f	8646	/**
cparata	0:f27ce43dee4f	8647	* @brief Rate at which the master communicates.[get]
cparata	0:f27ce43dee4f	8648	*
cparata	0:f27ce43dee4f	8649	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8650	* @param val Get the values of shub_odr in reg slv1_CONFIG
cparata	0:f27ce43dee4f	8651	*
cparata	0:f27ce43dee4f	8652	*/
cparata	0:f27ce43dee4f	8653	int32_t lsm6dsox_sh_data_rate_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8654	lsm6dsox_shub_odr_t *val)
cparata	0:f27ce43dee4f	8655	{
cparata	0:f27ce43dee4f	8656	lsm6dsox_slv0_config_t reg;
cparata	0:f27ce43dee4f	8657	int32_t ret;
cparata	0:f27ce43dee4f	8658
cparata	0:f27ce43dee4f	8659	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8660	if (ret == 0) {
cparata	1:fe40aec6e97a	8661	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8662	}
cparata	0:f27ce43dee4f	8663	if (ret == 0) {
cparata	0:f27ce43dee4f	8664	switch (reg.shub_odr) {
cparata	0:f27ce43dee4f	8665	case LSM6DSOX_SH_ODR_104Hz:
cparata	0:f27ce43dee4f	8666	*val = LSM6DSOX_SH_ODR_104Hz;
cparata	0:f27ce43dee4f	8667	break;
cparata	0:f27ce43dee4f	8668	case LSM6DSOX_SH_ODR_52Hz:
cparata	0:f27ce43dee4f	8669	*val = LSM6DSOX_SH_ODR_52Hz;
cparata	0:f27ce43dee4f	8670	break;
cparata	0:f27ce43dee4f	8671	case LSM6DSOX_SH_ODR_26Hz:
cparata	0:f27ce43dee4f	8672	*val = LSM6DSOX_SH_ODR_26Hz;
cparata	0:f27ce43dee4f	8673	break;
cparata	0:f27ce43dee4f	8674	case LSM6DSOX_SH_ODR_13Hz:
cparata	0:f27ce43dee4f	8675	*val = LSM6DSOX_SH_ODR_13Hz;
cparata	0:f27ce43dee4f	8676	break;
cparata	0:f27ce43dee4f	8677	default:
cparata	0:f27ce43dee4f	8678	*val = LSM6DSOX_SH_ODR_104Hz;
cparata	0:f27ce43dee4f	8679	break;
cparata	0:f27ce43dee4f	8680	}
cparata	0:f27ce43dee4f	8681	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8682	}
cparata	0:f27ce43dee4f	8683
cparata	0:f27ce43dee4f	8684	return ret;
cparata	0:f27ce43dee4f	8685	}
cparata	0:f27ce43dee4f	8686
cparata	0:f27ce43dee4f	8687	/**
cparata	0:f27ce43dee4f	8688	* @brief Configure slave 0 for perform a write.[set]
cparata	0:f27ce43dee4f	8689	*
cparata	0:f27ce43dee4f	8690	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8691	* @param val a structure that contain
cparata	0:f27ce43dee4f	8692	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:f27ce43dee4f	8693	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:f27ce43dee4f	8694	* - uint8_t slv1_data; 8 bit data to write
cparata	0:f27ce43dee4f	8695	*
cparata	0:f27ce43dee4f	8696	*/
cparata	0:f27ce43dee4f	8697	int32_t lsm6dsox_sh_cfg_write(lsm6dsox_ctx_t ctx, lsm6dsox_sh_cfg_write_t val)
cparata	0:f27ce43dee4f	8698	{
cparata	0:f27ce43dee4f	8699	lsm6dsox_slv0_add_t reg;
cparata	0:f27ce43dee4f	8700	int32_t ret;
cparata	0:f27ce43dee4f	8701
cparata	0:f27ce43dee4f	8702	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8703	if (ret == 0) {
cparata	0:f27ce43dee4f	8704	reg.slave0 = val->slv0_add;
cparata	0:f27ce43dee4f	8705	reg.rw_0 = 0;
cparata	0:f27ce43dee4f	8706	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8707	}
cparata	0:f27ce43dee4f	8708	if (ret == 0) {
cparata	0:f27ce43dee4f	8709	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD,
cparata	0:f27ce43dee4f	8710	&(val->slv0_subadd), 1);
cparata	0:f27ce43dee4f	8711	}
cparata	0:f27ce43dee4f	8712	if (ret == 0) {
cparata	0:f27ce43dee4f	8713	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_DATAWRITE_SLV0,
cparata	0:f27ce43dee4f	8714	&(val->slv0_data), 1);
cparata	0:f27ce43dee4f	8715	}
cparata	0:f27ce43dee4f	8716	if (ret == 0) {
cparata	0:f27ce43dee4f	8717	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8718	}
cparata	0:f27ce43dee4f	8719	return ret;
cparata	0:f27ce43dee4f	8720	}
cparata	0:f27ce43dee4f	8721
cparata	0:f27ce43dee4f	8722	/**
cparata	0:f27ce43dee4f	8723	* @brief Configure slave 0 for perform a read.[set]
cparata	0:f27ce43dee4f	8724	*
cparata	0:f27ce43dee4f	8725	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8726	* @param val Structure that contain
cparata	0:f27ce43dee4f	8727	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:f27ce43dee4f	8728	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:f27ce43dee4f	8729	* - uint8_t slv1_len; num of bit to read
cparata	0:f27ce43dee4f	8730	*
cparata	0:f27ce43dee4f	8731	*/
cparata	0:f27ce43dee4f	8732	int32_t lsm6dsox_sh_slv0_cfg_read(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8733	lsm6dsox_sh_cfg_read_t *val)
cparata	0:f27ce43dee4f	8734	{
cparata	0:f27ce43dee4f	8735	lsm6dsox_slv0_add_t slv0_add;
cparata	0:f27ce43dee4f	8736	lsm6dsox_slv0_config_t slv0_config;
cparata	0:f27ce43dee4f	8737	int32_t ret;
cparata	0:f27ce43dee4f	8738
cparata	0:f27ce43dee4f	8739	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8740	if (ret == 0) {
cparata	0:f27ce43dee4f	8741	slv0_add.slave0 = val->slv_add;
cparata	0:f27ce43dee4f	8742	slv0_add.rw_0 = 1;
cparata	0:f27ce43dee4f	8743	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)&slv0_add, 1);
cparata	0:f27ce43dee4f	8744	}
cparata	0:f27ce43dee4f	8745	if (ret == 0) {
cparata	0:f27ce43dee4f	8746	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD,
cparata	0:f27ce43dee4f	8747	&(val->slv_subadd), 1);
cparata	0:f27ce43dee4f	8748	}
cparata	0:f27ce43dee4f	8749	if (ret == 0) {
cparata	0:f27ce43dee4f	8750	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG,
cparata	0:f27ce43dee4f	8751	(uint8_t*)&slv0_config, 1);
cparata	0:f27ce43dee4f	8752	}
cparata	0:f27ce43dee4f	8753	if (ret == 0) {
cparata	0:f27ce43dee4f	8754	slv0_config.slave0_numop = val->slv_len;
cparata	0:f27ce43dee4f	8755	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG,
cparata	0:f27ce43dee4f	8756	(uint8_t*)&slv0_config, 1);
cparata	0:f27ce43dee4f	8757	}
cparata	0:f27ce43dee4f	8758	if (ret == 0) {
cparata	0:f27ce43dee4f	8759	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8760	}
cparata	0:f27ce43dee4f	8761
cparata	0:f27ce43dee4f	8762	return ret;
cparata	0:f27ce43dee4f	8763	}
cparata	0:f27ce43dee4f	8764
cparata	0:f27ce43dee4f	8765	/**
cparata	0:f27ce43dee4f	8766	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:f27ce43dee4f	8767	*
cparata	0:f27ce43dee4f	8768	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8769	* @param val Structure that contain
cparata	0:f27ce43dee4f	8770	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:f27ce43dee4f	8771	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:f27ce43dee4f	8772	* - uint8_t slv1_len; num of bit to read
cparata	0:f27ce43dee4f	8773	*
cparata	0:f27ce43dee4f	8774	*/
cparata	0:f27ce43dee4f	8775	int32_t lsm6dsox_sh_slv1_cfg_read(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8776	lsm6dsox_sh_cfg_read_t *val)
cparata	0:f27ce43dee4f	8777	{
cparata	0:f27ce43dee4f	8778	lsm6dsox_slv1_add_t slv1_add;
cparata	0:f27ce43dee4f	8779	lsm6dsox_slv1_config_t slv1_config;
cparata	0:f27ce43dee4f	8780	int32_t ret;
cparata	0:f27ce43dee4f	8781
cparata	0:f27ce43dee4f	8782	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8783	if (ret == 0) {
cparata	0:f27ce43dee4f	8784	slv1_add.slave1_add = val->slv_add;
cparata	0:f27ce43dee4f	8785	slv1_add.r_1 = 1;
cparata	0:f27ce43dee4f	8786	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_ADD, (uint8_t*)&slv1_add, 1);
cparata	0:f27ce43dee4f	8787	}
cparata	0:f27ce43dee4f	8788	if (ret == 0) {
cparata	0:f27ce43dee4f	8789	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_SUBADD,
cparata	0:f27ce43dee4f	8790	&(val->slv_subadd), 1);
cparata	0:f27ce43dee4f	8791	}
cparata	0:f27ce43dee4f	8792	if (ret == 0) {
cparata	0:f27ce43dee4f	8793	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG,
cparata	0:f27ce43dee4f	8794	(uint8_t*)&slv1_config, 1);
cparata	0:f27ce43dee4f	8795	}
cparata	0:f27ce43dee4f	8796	if (ret == 0) {
cparata	0:f27ce43dee4f	8797	slv1_config.slave1_numop = val->slv_len;
cparata	0:f27ce43dee4f	8798	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG,
cparata	0:f27ce43dee4f	8799	(uint8_t*)&slv1_config, 1);
cparata	0:f27ce43dee4f	8800	}
cparata	0:f27ce43dee4f	8801	if (ret == 0) {
cparata	0:f27ce43dee4f	8802	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8803	}
cparata	0:f27ce43dee4f	8804
cparata	0:f27ce43dee4f	8805	return ret;
cparata	0:f27ce43dee4f	8806	}
cparata	0:f27ce43dee4f	8807
cparata	0:f27ce43dee4f	8808	/**
cparata	0:f27ce43dee4f	8809	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:f27ce43dee4f	8810	*
cparata	0:f27ce43dee4f	8811	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8812	* @param val Structure that contain
cparata	0:f27ce43dee4f	8813	* - uint8_t slv2_add; 8 bit i2c device address
cparata	0:f27ce43dee4f	8814	* - uint8_t slv2_subadd; 8 bit register device address
cparata	0:f27ce43dee4f	8815	* - uint8_t slv2_len; num of bit to read
cparata	0:f27ce43dee4f	8816	*
cparata	0:f27ce43dee4f	8817	*/
cparata	0:f27ce43dee4f	8818	int32_t lsm6dsox_sh_slv2_cfg_read(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8819	lsm6dsox_sh_cfg_read_t *val)
cparata	0:f27ce43dee4f	8820	{
cparata	0:f27ce43dee4f	8821	lsm6dsox_slv2_add_t slv2_add;
cparata	0:f27ce43dee4f	8822	lsm6dsox_slv2_config_t slv2_config;
cparata	0:f27ce43dee4f	8823	int32_t ret;
cparata	0:f27ce43dee4f	8824
cparata	0:f27ce43dee4f	8825	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8826	if (ret == 0) {
cparata	0:f27ce43dee4f	8827	slv2_add.slave2_add = val->slv_add;
cparata	0:f27ce43dee4f	8828	slv2_add.r_2 = 1;
cparata	0:f27ce43dee4f	8829	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_ADD, (uint8_t*)&slv2_add, 1);
cparata	0:f27ce43dee4f	8830	}
cparata	0:f27ce43dee4f	8831	if (ret == 0) {
cparata	0:f27ce43dee4f	8832	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_SUBADD,
cparata	0:f27ce43dee4f	8833	&(val->slv_subadd), 1);
cparata	0:f27ce43dee4f	8834	}
cparata	0:f27ce43dee4f	8835	if (ret == 0) {
cparata	0:f27ce43dee4f	8836	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG,
cparata	0:f27ce43dee4f	8837	(uint8_t*)&slv2_config, 1);
cparata	0:f27ce43dee4f	8838	}
cparata	0:f27ce43dee4f	8839	if (ret == 0) {
cparata	0:f27ce43dee4f	8840	slv2_config.slave2_numop = val->slv_len;
cparata	0:f27ce43dee4f	8841	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG,
cparata	0:f27ce43dee4f	8842	(uint8_t*)&slv2_config, 1);
cparata	0:f27ce43dee4f	8843	}
cparata	0:f27ce43dee4f	8844	if (ret == 0) {
cparata	0:f27ce43dee4f	8845	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8846	}
cparata	0:f27ce43dee4f	8847	return ret;
cparata	0:f27ce43dee4f	8848	}
cparata	0:f27ce43dee4f	8849
cparata	0:f27ce43dee4f	8850	/**
cparata	0:f27ce43dee4f	8851	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:f27ce43dee4f	8852	*
cparata	0:f27ce43dee4f	8853	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8854	* @param val Structure that contain
cparata	0:f27ce43dee4f	8855	* - uint8_t slv3_add; 8 bit i2c device address
cparata	0:f27ce43dee4f	8856	* - uint8_t slv3_subadd; 8 bit register device address
cparata	0:f27ce43dee4f	8857	* - uint8_t slv3_len; num of bit to read
cparata	0:f27ce43dee4f	8858	*
cparata	0:f27ce43dee4f	8859	*/
cparata	0:f27ce43dee4f	8860	int32_t lsm6dsox_sh_slv3_cfg_read(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8861	lsm6dsox_sh_cfg_read_t *val)
cparata	0:f27ce43dee4f	8862	{
cparata	0:f27ce43dee4f	8863	lsm6dsox_slv3_add_t slv3_add;
cparata	0:f27ce43dee4f	8864	lsm6dsox_slv3_config_t slv3_config;
cparata	0:f27ce43dee4f	8865	int32_t ret;
cparata	0:f27ce43dee4f	8866
cparata	0:f27ce43dee4f	8867	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8868	if (ret == 0) {
cparata	0:f27ce43dee4f	8869	slv3_add.slave3_add = val->slv_add;
cparata	0:f27ce43dee4f	8870	slv3_add.r_3 = 1;
cparata	0:f27ce43dee4f	8871	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_ADD, (uint8_t*)&slv3_add, 1);
cparata	0:f27ce43dee4f	8872	}
cparata	0:f27ce43dee4f	8873	if (ret == 0) {
cparata	0:f27ce43dee4f	8874	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_SUBADD,
cparata	0:f27ce43dee4f	8875	&(val->slv_subadd), 1);
cparata	0:f27ce43dee4f	8876	}
cparata	0:f27ce43dee4f	8877	if (ret == 0) {
cparata	0:f27ce43dee4f	8878	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG,
cparata	0:f27ce43dee4f	8879	(uint8_t*)&slv3_config, 1);
cparata	0:f27ce43dee4f	8880	}
cparata	0:f27ce43dee4f	8881	if (ret == 0) {
cparata	0:f27ce43dee4f	8882	slv3_config.slave3_numop = val->slv_len;
cparata	0:f27ce43dee4f	8883	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG,
cparata	0:f27ce43dee4f	8884	(uint8_t*)&slv3_config, 1);
cparata	0:f27ce43dee4f	8885	}
cparata	0:f27ce43dee4f	8886	if (ret == 0) {
cparata	0:f27ce43dee4f	8887	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8888	}
cparata	0:f27ce43dee4f	8889	return ret;
cparata	0:f27ce43dee4f	8890	}
cparata	0:f27ce43dee4f	8891
cparata	0:f27ce43dee4f	8892	/**
cparata	0:f27ce43dee4f	8893	* @brief Sensor hub source register.[get]
cparata	0:f27ce43dee4f	8894	*
cparata	0:f27ce43dee4f	8895	* @param ctx read / write interface definitions
cparata	0:f27ce43dee4f	8896	* @param val union of registers from STATUS_MASTER to
cparata	0:f27ce43dee4f	8897	*
cparata	0:f27ce43dee4f	8898	*/
cparata	0:f27ce43dee4f	8899	int32_t lsm6dsox_sh_status_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8900	lsm6dsox_status_master_t *val)
cparata	0:f27ce43dee4f	8901	{
cparata	0:f27ce43dee4f	8902	int32_t ret;
cparata	0:f27ce43dee4f	8903
cparata	0:f27ce43dee4f	8904	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata	0:f27ce43dee4f	8905	if (ret == 0) {
cparata	0:f27ce43dee4f	8906	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_MASTER, (uint8_t*) val, 1);
cparata	0:f27ce43dee4f	8907	}
cparata	0:f27ce43dee4f	8908	if (ret == 0) {
cparata	0:f27ce43dee4f	8909	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	0:f27ce43dee4f	8910	}
cparata	0:f27ce43dee4f	8911
cparata	0:f27ce43dee4f	8912	return ret;
cparata	0:f27ce43dee4f	8913	}
cparata	0:f27ce43dee4f	8914
cparata	0:f27ce43dee4f	8915	/**
cparata	0:f27ce43dee4f	8916	* @}
cparata	0:f27ce43dee4f	8917	*
cparata	0:f27ce43dee4f	8918	*/
cparata	0:f27ce43dee4f	8919
cparata	0:f27ce43dee4f	8920	/**
cparata	0:f27ce43dee4f	8921	* @addtogroup Sensors for Smart Mobile Devices
cparata	0:f27ce43dee4f	8922	* @brief This section groups all the functions that manage the
cparata	0:f27ce43dee4f	8923	* Sensors for Smart Mobile Devices.
cparata	0:f27ce43dee4f	8924	* @{
cparata	0:f27ce43dee4f	8925	*
cparata	0:f27ce43dee4f	8926	*/
cparata	0:f27ce43dee4f	8927
cparata	0:f27ce43dee4f	8928	/**
cparata	0:f27ce43dee4f	8929	* @brief s4s_tph_res: [set] Sensor synchronization time frame resolution
cparata	0:f27ce43dee4f	8930	*
cparata	0:f27ce43dee4f	8931	* @param *ctx read / write interface definitions
cparata	0:f27ce43dee4f	8932	* @param val change the values of tph_h_sel in LSM6DSOX_S4S_TPH_L
cparata	0:f27ce43dee4f	8933	*
cparata	0:f27ce43dee4f	8934	*/
cparata	0:f27ce43dee4f	8935	int32_t lsm6dsox_s4s_tph_res_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8936	lsm6dsox_s4s_tph_res_t val)
cparata	0:f27ce43dee4f	8937	{
cparata	0:f27ce43dee4f	8938	lsm6dsox_s4s_tph_l_t reg;
cparata	0:f27ce43dee4f	8939	int32_t ret;
cparata	0:f27ce43dee4f	8940
cparata	0:f27ce43dee4f	8941	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8942	if (ret == 0) {
cparata	0:f27ce43dee4f	8943	reg.tph_h_sel = (uint8_t)val;
cparata	0:f27ce43dee4f	8944	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8945	}
cparata	0:f27ce43dee4f	8946	return ret;
cparata	0:f27ce43dee4f	8947	}
cparata	0:f27ce43dee4f	8948
cparata	0:f27ce43dee4f	8949	/**
cparata	0:f27ce43dee4f	8950	* @brief s4s_tph_res: [get] Sensor synchronization time frame resolution
cparata	0:f27ce43dee4f	8951	*
cparata	0:f27ce43dee4f	8952	* @param *ctx read / write interface definitions
cparata	0:f27ce43dee4f	8953	* @param val get the values of tph_h_sel in LSM6DSOX_S4S_TPH_L
cparata	0:f27ce43dee4f	8954	*
cparata	0:f27ce43dee4f	8955	*/
cparata	0:f27ce43dee4f	8956	int32_t lsm6dsox_s4s_tph_res_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	8957	lsm6dsox_s4s_tph_res_t *val)
cparata	0:f27ce43dee4f	8958	{
cparata	0:f27ce43dee4f	8959	lsm6dsox_s4s_tph_l_t reg;
cparata	0:f27ce43dee4f	8960	int32_t ret;
cparata	0:f27ce43dee4f	8961
cparata	0:f27ce43dee4f	8962	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	8963	switch (reg.tph_h_sel) {
cparata	0:f27ce43dee4f	8964	case LSM6DSOX_S4S_TPH_7bit:
cparata	0:f27ce43dee4f	8965	*val = LSM6DSOX_S4S_TPH_7bit;
cparata	0:f27ce43dee4f	8966	break;
cparata	0:f27ce43dee4f	8967	case LSM6DSOX_S4S_TPH_15bit:
cparata	0:f27ce43dee4f	8968	*val = LSM6DSOX_S4S_TPH_15bit;
cparata	0:f27ce43dee4f	8969	break;
cparata	0:f27ce43dee4f	8970	default:
cparata	0:f27ce43dee4f	8971	*val = LSM6DSOX_S4S_TPH_7bit;
cparata	0:f27ce43dee4f	8972	break;
cparata	0:f27ce43dee4f	8973	}
cparata	0:f27ce43dee4f	8974
cparata	0:f27ce43dee4f	8975	return ret;
cparata	0:f27ce43dee4f	8976	}
cparata	0:f27ce43dee4f	8977
cparata	0:f27ce43dee4f	8978	/**
cparata	0:f27ce43dee4f	8979	* @brief s4s_tph_val: [set] Sensor synchronization time frame
cparata	0:f27ce43dee4f	8980	*
cparata	0:f27ce43dee4f	8981	* @param *ctx read / write interface definitions
cparata	0:f27ce43dee4f	8982	* @param val change the values of tph_l in S4S_TPH_L and
cparata	0:f27ce43dee4f	8983	* tph_h in S4S_TPH_H
cparata	0:f27ce43dee4f	8984	*
cparata	0:f27ce43dee4f	8985	*/
cparata	0:f27ce43dee4f	8986	int32_t lsm6dsox_s4s_tph_val_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata	0:f27ce43dee4f	8987	{
cparata	0:f27ce43dee4f	8988	lsm6dsox_s4s_tph_l_t s4s_tph_l;
cparata	0:f27ce43dee4f	8989	lsm6dsox_s4s_tph_h_t s4s_tph_h;
cparata	0:f27ce43dee4f	8990	int32_t ret;
cparata	0:f27ce43dee4f	8991
cparata	0:f27ce43dee4f	8992	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
cparata	0:f27ce43dee4f	8993	if (ret == 0) {
cparata	0:f27ce43dee4f	8994	s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
cparata	0:f27ce43dee4f	8995	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
cparata	0:f27ce43dee4f	8996	}
cparata	0:f27ce43dee4f	8997	if (ret == 0) {
cparata	0:f27ce43dee4f	8998	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1);
cparata	0:f27ce43dee4f	8999	s4s_tph_h.tph_h = (uint8_t)(val & 0x7F80U) >> 7;
cparata	0:f27ce43dee4f	9000	}
cparata	0:f27ce43dee4f	9001	if (ret == 0) {
cparata	0:f27ce43dee4f	9002	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1);
cparata	0:f27ce43dee4f	9003	}
cparata	0:f27ce43dee4f	9004	return ret;
cparata	0:f27ce43dee4f	9005	}
cparata	0:f27ce43dee4f	9006
cparata	0:f27ce43dee4f	9007	/**
cparata	0:f27ce43dee4f	9008	* @brief s4s_tph_val: [get] Sensor synchronization time frame.
cparata	0:f27ce43dee4f	9009	*
cparata	0:f27ce43dee4f	9010	* @param *ctx read / write interface definitions
cparata	0:f27ce43dee4f	9011	* @param val get the values of tph_l in S4S_TPH_L and
cparata	0:f27ce43dee4f	9012	* tph_h in S4S_TPH_H
cparata	0:f27ce43dee4f	9013	*
cparata	0:f27ce43dee4f	9014	*/
cparata	0:f27ce43dee4f	9015	int32_t lsm6dsox_s4s_tph_val_get(lsm6dsox_ctx_t ctx, uint16_t val)
cparata	0:f27ce43dee4f	9016	{
cparata	0:f27ce43dee4f	9017	lsm6dsox_s4s_tph_l_t s4s_tph_l;
cparata	0:f27ce43dee4f	9018	lsm6dsox_s4s_tph_h_t s4s_tph_h;
cparata	0:f27ce43dee4f	9019	int32_t ret;
cparata	0:f27ce43dee4f	9020
cparata	0:f27ce43dee4f	9021	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
cparata	0:f27ce43dee4f	9022	if (ret == 0) {
cparata	0:f27ce43dee4f	9023	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1);
cparata	0:f27ce43dee4f	9024	*val = s4s_tph_h.tph_h;
cparata	0:f27ce43dee4f	9025	val = val << 7;
cparata	0:f27ce43dee4f	9026	*val += s4s_tph_l.tph_l;
cparata	0:f27ce43dee4f	9027	}
cparata	0:f27ce43dee4f	9028	return ret;
cparata	0:f27ce43dee4f	9029	}
cparata	0:f27ce43dee4f	9030
cparata	0:f27ce43dee4f	9031	/**
cparata	0:f27ce43dee4f	9032	* @brief s4s_res_ratio: [set]Sensor synchronization resolution
cparata	0:f27ce43dee4f	9033	* ratio register.
cparata	0:f27ce43dee4f	9034	*
cparata	0:f27ce43dee4f	9035	* @param *ctx read / write interface definitions.
cparata	0:f27ce43dee4f	9036	* @param val change the values of rr in S4S_RR.
cparata	0:f27ce43dee4f	9037	*
cparata	0:f27ce43dee4f	9038	*/
cparata	0:f27ce43dee4f	9039	int32_t lsm6dsox_s4s_res_ratio_set(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	9040	lsm6dsox_s4s_res_ratio_t val)
cparata	0:f27ce43dee4f	9041	{
cparata	0:f27ce43dee4f	9042	lsm6dsox_s4s_rr_t reg;
cparata	0:f27ce43dee4f	9043	int32_t ret;
cparata	0:f27ce43dee4f	9044
cparata	0:f27ce43dee4f	9045	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	9046	if (ret == 0) {
cparata	0:f27ce43dee4f	9047	reg.rr = (uint8_t)val;
cparata	0:f27ce43dee4f	9048	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	9049	}
cparata	0:f27ce43dee4f	9050	return ret;
cparata	0:f27ce43dee4f	9051	}
cparata	0:f27ce43dee4f	9052
cparata	0:f27ce43dee4f	9053	/**
cparata	0:f27ce43dee4f	9054	* @brief s4s_res_ratio: [get]Sensor synchronization resolution
cparata	0:f27ce43dee4f	9055	* ratio register.
cparata	0:f27ce43dee4f	9056	*
cparata	0:f27ce43dee4f	9057	* @param *ctx read / write interface definitions
cparata	0:f27ce43dee4f	9058	* @param val get the values of rr in S4S_RR
cparata	0:f27ce43dee4f	9059	*
cparata	0:f27ce43dee4f	9060	*/
cparata	0:f27ce43dee4f	9061	int32_t lsm6dsox_s4s_res_ratio_get(lsm6dsox_ctx_t *ctx,
cparata	0:f27ce43dee4f	9062	lsm6dsox_s4s_res_ratio_t *val)
cparata	0:f27ce43dee4f	9063	{
cparata	0:f27ce43dee4f	9064	lsm6dsox_s4s_rr_t reg;
cparata	0:f27ce43dee4f	9065	int32_t ret;
cparata	0:f27ce43dee4f	9066
cparata	0:f27ce43dee4f	9067	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	9068	switch (reg.rr) {
cparata	0:f27ce43dee4f	9069	case LSM6DSOX_S4S_DT_RES_11:
cparata	0:f27ce43dee4f	9070	*val = LSM6DSOX_S4S_DT_RES_11;
cparata	0:f27ce43dee4f	9071	break;
cparata	0:f27ce43dee4f	9072	case LSM6DSOX_S4S_DT_RES_12:
cparata	0:f27ce43dee4f	9073	*val = LSM6DSOX_S4S_DT_RES_12;
cparata	0:f27ce43dee4f	9074	break;
cparata	0:f27ce43dee4f	9075	case LSM6DSOX_S4S_DT_RES_13:
cparata	0:f27ce43dee4f	9076	*val = LSM6DSOX_S4S_DT_RES_13;
cparata	0:f27ce43dee4f	9077	break;
cparata	0:f27ce43dee4f	9078	case LSM6DSOX_S4S_DT_RES_14:
cparata	0:f27ce43dee4f	9079	*val = LSM6DSOX_S4S_DT_RES_14;
cparata	0:f27ce43dee4f	9080	break;
cparata	0:f27ce43dee4f	9081	default:
cparata	0:f27ce43dee4f	9082	*val = LSM6DSOX_S4S_DT_RES_11;
cparata	0:f27ce43dee4f	9083	break;
cparata	0:f27ce43dee4f	9084	}
cparata	0:f27ce43dee4f	9085	return ret;
cparata	0:f27ce43dee4f	9086	}
cparata	0:f27ce43dee4f	9087
cparata	0:f27ce43dee4f	9088	/**
cparata	0:f27ce43dee4f	9089	* @brief s4s_command: [set] s4s master command.
cparata	0:f27ce43dee4f	9090	*
cparata	0:f27ce43dee4f	9091	* @param *ctx read / write interface definitions.
cparata	0:f27ce43dee4f	9092	* @param val change the values of S4S_ST_CMD_CODE.
cparata	0:f27ce43dee4f	9093	*
cparata	0:f27ce43dee4f	9094	*/
cparata	0:f27ce43dee4f	9095	int32_t lsm6dsox_s4s_command_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	9096	{
cparata	0:f27ce43dee4f	9097	lsm6dsox_s4s_st_cmd_code_t reg;
cparata	0:f27ce43dee4f	9098	int32_t ret;
cparata	0:f27ce43dee4f	9099
cparata	0:f27ce43dee4f	9100	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)&reg, 1);
cparata	1:fe40aec6e97a	9101
cparata	0:f27ce43dee4f	9102	if (ret == 0) {
cparata	0:f27ce43dee4f	9103	reg.s4s_st_cmd_code = val;
cparata	0:f27ce43dee4f	9104	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	9105	}
cparata	0:f27ce43dee4f	9106	return ret;
cparata	0:f27ce43dee4f	9107	}
cparata	0:f27ce43dee4f	9108
cparata	0:f27ce43dee4f	9109	/**
cparata	0:f27ce43dee4f	9110	* @brief s4s_command: [get] s4s master command.
cparata	0:f27ce43dee4f	9111	*
cparata	0:f27ce43dee4f	9112	* @param *ctx read / write interface definitions.
cparata	0:f27ce43dee4f	9113	* @param val get the values of S4S_ST_CMD_CODE.
cparata	0:f27ce43dee4f	9114	*
cparata	0:f27ce43dee4f	9115	*/
cparata	0:f27ce43dee4f	9116	int32_t lsm6dsox_s4s_command_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	9117	{
cparata	0:f27ce43dee4f	9118	lsm6dsox_s4s_st_cmd_code_t reg;
cparata	0:f27ce43dee4f	9119	int32_t ret;
cparata	0:f27ce43dee4f	9120
cparata	0:f27ce43dee4f	9121	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	9122	*val = reg.s4s_st_cmd_code;
cparata	0:f27ce43dee4f	9123
cparata	0:f27ce43dee4f	9124	return ret;
cparata	0:f27ce43dee4f	9125	}
cparata	0:f27ce43dee4f	9126
cparata	0:f27ce43dee4f	9127	/**
cparata	0:f27ce43dee4f	9128	* @brief s4s_dt: [set] S4S DT register.
cparata	0:f27ce43dee4f	9129	*
cparata	0:f27ce43dee4f	9130	* @param *ctx read / write interface definitions.
cparata	0:f27ce43dee4f	9131	* @param val change the values of S4S_DT_REG.
cparata	0:f27ce43dee4f	9132	*
cparata	0:f27ce43dee4f	9133	*/
cparata	0:f27ce43dee4f	9134	int32_t lsm6dsox_s4s_dt_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata	0:f27ce43dee4f	9135	{
cparata	0:f27ce43dee4f	9136	lsm6dsox_s4s_dt_reg_t reg;
cparata	0:f27ce43dee4f	9137	int32_t ret;
cparata	0:f27ce43dee4f	9138
cparata	0:f27ce43dee4f	9139	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	9140	if (ret == 0) {
cparata	0:f27ce43dee4f	9141	reg.dt = val;
cparata	0:f27ce43dee4f	9142	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	9143	}
cparata	0:f27ce43dee4f	9144	return ret;
cparata	0:f27ce43dee4f	9145	}
cparata	0:f27ce43dee4f	9146
cparata	0:f27ce43dee4f	9147	/**
cparata	0:f27ce43dee4f	9148	* @brief s4s_dt: [get] S4S DT register.
cparata	0:f27ce43dee4f	9149	*
cparata	0:f27ce43dee4f	9150	* @param *ctx read / write interface definitions.
cparata	0:f27ce43dee4f	9151	* @param val get the values of S4S_DT_REG.
cparata	0:f27ce43dee4f	9152	*
cparata	0:f27ce43dee4f	9153	*/
cparata	0:f27ce43dee4f	9154	int32_t lsm6dsox_s4s_dt_get(lsm6dsox_ctx_t ctx, uint8_t val)
cparata	0:f27ce43dee4f	9155	{
cparata	0:f27ce43dee4f	9156	lsm6dsox_s4s_dt_reg_t reg;
cparata	0:f27ce43dee4f	9157	int32_t ret;
cparata	0:f27ce43dee4f	9158
cparata	0:f27ce43dee4f	9159	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)&reg, 1);
cparata	0:f27ce43dee4f	9160	*val = reg.dt;
cparata	0:f27ce43dee4f	9161
cparata	0:f27ce43dee4f	9162	return ret;
cparata	0:f27ce43dee4f	9163	}
cparata	0:f27ce43dee4f	9164
cparata	0:f27ce43dee4f	9165	/**
cparata	0:f27ce43dee4f	9166	* @}
cparata	0:f27ce43dee4f	9167	*
cparata	0:f27ce43dee4f	9168	*/
cparata	0:f27ce43dee4f	9169
cparata	0:f27ce43dee4f	9170	/**
cparata	1:fe40aec6e97a	9171	* @defgroup Basic configuration
cparata	1:fe40aec6e97a	9172	* @brief This section groups all the functions concerning
cparata	1:fe40aec6e97a	9173	* device basic configuration.
cparata	1:fe40aec6e97a	9174	* @{
cparata	1:fe40aec6e97a	9175	*
cparata	1:fe40aec6e97a	9176	*/
cparata	1:fe40aec6e97a	9177
cparata	1:fe40aec6e97a	9178	/**
cparata	1:fe40aec6e97a	9179	* @brief Device "Who am I".[get]
cparata	1:fe40aec6e97a	9180	*
cparata	1:fe40aec6e97a	9181	* @param ctx communication interface handler. Use NULL to ingnore
cparata	1:fe40aec6e97a	9182	* this interface.(ptr)
cparata	1:fe40aec6e97a	9183	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	1:fe40aec6e97a	9184	* to ingnore this interface.(ptr)
cparata	1:fe40aec6e97a	9185	* @param val ID values read from the two interfaces. ID values
cparata	1:fe40aec6e97a	9186	* will be the same.(ptr)
cparata	1:fe40aec6e97a	9187	*
cparata	1:fe40aec6e97a	9188	*/
cparata	1:fe40aec6e97a	9189	int32_t lsm6dsox_id_get(lsm6dsox_ctx_t ctx, lsm6dsox_ctx_t aux_ctx,
cparata	1:fe40aec6e97a	9190	lsm6dsox_id_t *val)
cparata	1:fe40aec6e97a	9191	{
cparata	1:fe40aec6e97a	9192	int32_t ret = 0;
cparata	1:fe40aec6e97a	9193
cparata	1:fe40aec6e97a	9194	if (ctx != NULL){
cparata	1:fe40aec6e97a	9195	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I,
cparata	1:fe40aec6e97a	9196	(uint8_t*)&(val->ui), 1);
cparata	1:fe40aec6e97a	9197	}
cparata	1:fe40aec6e97a	9198	if (aux_ctx != NULL){
cparata	1:fe40aec6e97a	9199	if (ret == 0) {
cparata	1:fe40aec6e97a	9200	ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_WHO_AM_I,
cparata	1:fe40aec6e97a	9201	(uint8_t*)&(val->aux), 1);
cparata	1:fe40aec6e97a	9202	}
cparata	1:fe40aec6e97a	9203	}
cparata	1:fe40aec6e97a	9204	return ret;
cparata	1:fe40aec6e97a	9205	}
cparata	1:fe40aec6e97a	9206
cparata	1:fe40aec6e97a	9207	/**
cparata	1:fe40aec6e97a	9208	* @brief Re-initialize the device.[set]
cparata	1:fe40aec6e97a	9209	*
cparata	1:fe40aec6e97a	9210	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	9211	* @param val re-initialization mode. Refer to datasheet
cparata	1:fe40aec6e97a	9212	* and application note for more information
cparata	1:fe40aec6e97a	9213	* about differencies beetween boot and sw_reset
cparata	1:fe40aec6e97a	9214	* procedure.
cparata	1:fe40aec6e97a	9215	*
cparata	1:fe40aec6e97a	9216	*/
cparata	1:fe40aec6e97a	9217	int32_t lsm6dsox_init_set(lsm6dsox_ctx_t *ctx, lsm6dsox_init_t val)
cparata	1:fe40aec6e97a	9218	{
cparata	1:fe40aec6e97a	9219	lsm6dsox_emb_func_init_a_t emb_func_init_a;
cparata	1:fe40aec6e97a	9220	lsm6dsox_emb_func_init_b_t emb_func_init_b;
cparata	1:fe40aec6e97a	9221	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	9222	int32_t ret;
cparata	1:fe40aec6e97a	9223
cparata	1:fe40aec6e97a	9224	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	9225	if (ret == 0) {
cparata	1:fe40aec6e97a	9226	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
cparata	1:fe40aec6e97a	9227	(uint8_t*)&emb_func_init_b, 1);
cparata	1:fe40aec6e97a	9228	}
cparata	1:fe40aec6e97a	9229	if (ret == 0) {
cparata	1:fe40aec6e97a	9230	emb_func_init_b.fifo_compr_init = (uint8_t)val
cparata	1:fe40aec6e97a	9231	& ( (uint8_t)LSM6DSOX_FIFO_COMP >> 2 );
cparata	1:fe40aec6e97a	9232	emb_func_init_b.fsm_init = (uint8_t)val
cparata	1:fe40aec6e97a	9233	& ( (uint8_t)LSM6DSOX_FSM >> 3 );
cparata	1:fe40aec6e97a	9234	emb_func_init_b.mlc_init = (uint8_t)val
cparata	1:fe40aec6e97a	9235	& ( (uint8_t)LSM6DSOX_MLC >> 4 );
cparata	1:fe40aec6e97a	9236	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
cparata	1:fe40aec6e97a	9237	(uint8_t*)&emb_func_init_b, 1);
cparata	1:fe40aec6e97a	9238	}
cparata	1:fe40aec6e97a	9239	if (ret == 0) {
cparata	1:fe40aec6e97a	9240	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_A,
cparata	1:fe40aec6e97a	9241	(uint8_t*)&emb_func_init_a, 1);
cparata	1:fe40aec6e97a	9242	}
cparata	1:fe40aec6e97a	9243	if (ret == 0) {
cparata	1:fe40aec6e97a	9244	emb_func_init_a.step_det_init = ( (uint8_t)val
cparata	1:fe40aec6e97a	9245	& (uint8_t)LSM6DSOX_PEDO ) >> 5;
cparata	1:fe40aec6e97a	9246	emb_func_init_a.tilt_init = ( (uint8_t)val
cparata	1:fe40aec6e97a	9247	& (uint8_t)LSM6DSOX_TILT ) >> 6;
cparata	1:fe40aec6e97a	9248	emb_func_init_a.sig_mot_init = ( (uint8_t)val
cparata	1:fe40aec6e97a	9249	& (uint8_t)LSM6DSOX_SMOTION ) >> 7;
cparata	1:fe40aec6e97a	9250	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_A,
cparata	1:fe40aec6e97a	9251	(uint8_t*)&emb_func_init_a, 1);
cparata	1:fe40aec6e97a	9252	}
cparata	1:fe40aec6e97a	9253	if (ret == 0) {
cparata	1:fe40aec6e97a	9254	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	9255	}
cparata	1:fe40aec6e97a	9256
cparata	1:fe40aec6e97a	9257	if (ret == 0) {
cparata	1:fe40aec6e97a	9258	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9259	}
cparata	1:fe40aec6e97a	9260	if ( ( (val == LSM6DSOX_BOOT) \|\| (val == LSM6DSOX_RESET) ) && (ret == 0) ) {
cparata	1:fe40aec6e97a	9261	ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSOX_BOOT;
cparata	1:fe40aec6e97a	9262	ctrl3_c.sw_reset = ( (uint8_t)val & (uint8_t)LSM6DSOX_RESET) >> 1;
cparata	1:fe40aec6e97a	9263	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9264	}
cparata	1:fe40aec6e97a	9265	if ( ( val == LSM6DSOX_DRV_RDY )
cparata	1:fe40aec6e97a	9266	&& ( (ctrl3_c.bdu == PROPERTY_DISABLE)
cparata	1:fe40aec6e97a	9267	\|\| (ctrl3_c.if_inc == PROPERTY_DISABLE) ) && (ret == 0) ) {
cparata	1:fe40aec6e97a	9268	ctrl3_c.bdu = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	9269	ctrl3_c.if_inc = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	9270	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9271	}
cparata	1:fe40aec6e97a	9272
cparata	1:fe40aec6e97a	9273	return ret;
cparata	1:fe40aec6e97a	9274	}
cparata	1:fe40aec6e97a	9275
cparata	1:fe40aec6e97a	9276	/**
cparata	1:fe40aec6e97a	9277	* @brief Configures the bus operating mode.[set]
cparata	1:fe40aec6e97a	9278	*
cparata	1:fe40aec6e97a	9279	* @param ctx communication interface handler. Use NULL to ingnore
cparata	1:fe40aec6e97a	9280	* this interface.(ptr)
cparata	1:fe40aec6e97a	9281	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	1:fe40aec6e97a	9282	* to ingnore this interface.(ptr)
cparata	1:fe40aec6e97a	9283	* @param val configures the bus operating mode for both the
cparata	1:fe40aec6e97a	9284	* main and the auxiliary interface.
cparata	1:fe40aec6e97a	9285	*
cparata	1:fe40aec6e97a	9286	*/
cparata	1:fe40aec6e97a	9287	int32_t lsm6dsox_bus_mode_set(lsm6dsox_ctx_t ctx, lsm6dsox_ctx_t aux_ctx,
cparata	1:fe40aec6e97a	9288	lsm6dsox_bus_mode_t val)
cparata	1:fe40aec6e97a	9289	{
cparata	1:fe40aec6e97a	9290	lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois;
cparata	1:fe40aec6e97a	9291	lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata	1:fe40aec6e97a	9292	lsm6dsox_ctrl9_xl_t ctrl9_xl;
cparata	1:fe40aec6e97a	9293	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	9294	lsm6dsox_ctrl4_c_t ctrl4_c;
cparata	1:fe40aec6e97a	9295	uint8_t bit_val;
cparata	1:fe40aec6e97a	9296	int32_t ret;
cparata	1:fe40aec6e97a	9297
cparata	1:fe40aec6e97a	9298	ret = 0;
cparata	1:fe40aec6e97a	9299
cparata	1:fe40aec6e97a	9300	if (aux_ctx != NULL) {
cparata	1:fe40aec6e97a	9301	ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS,
cparata	1:fe40aec6e97a	9302	(uint8_t*)&spi2_ctrl1_ois, 1);
cparata	1:fe40aec6e97a	9303
cparata	1:fe40aec6e97a	9304	bit_val = ( (uint8_t)val.aux_bus_md & 0x04U ) >> 2;
cparata	1:fe40aec6e97a	9305	if ( ( ret == 0 ) && ( spi2_ctrl1_ois.sim_ois != bit_val ) ) {
cparata	1:fe40aec6e97a	9306	spi2_ctrl1_ois.sim_ois = bit_val;
cparata	1:fe40aec6e97a	9307	ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS,
cparata	1:fe40aec6e97a	9308	(uint8_t*)&spi2_ctrl1_ois, 1);
cparata	1:fe40aec6e97a	9309	}
cparata	1:fe40aec6e97a	9310	}
cparata	1:fe40aec6e97a	9311
cparata	1:fe40aec6e97a	9312	if (ctx != NULL) {
cparata	1:fe40aec6e97a	9313	if (ret == 0) {
cparata	1:fe40aec6e97a	9314	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL,
cparata	1:fe40aec6e97a	9315	(uint8_t*)&ctrl9_xl, 1);
cparata	1:fe40aec6e97a	9316	}
cparata	1:fe40aec6e97a	9317
cparata	1:fe40aec6e97a	9318	bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
cparata	1:fe40aec6e97a	9319	if ( ( ret == 0 ) && ( ctrl9_xl.i3c_disable != bit_val ) ) {
cparata	1:fe40aec6e97a	9320	ctrl9_xl.i3c_disable = bit_val;
cparata	1:fe40aec6e97a	9321	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL,
cparata	1:fe40aec6e97a	9322	(uint8_t*)&ctrl9_xl, 1);
cparata	1:fe40aec6e97a	9323	}
cparata	1:fe40aec6e97a	9324
cparata	1:fe40aec6e97a	9325	if (ret == 0) {
cparata	1:fe40aec6e97a	9326	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	1:fe40aec6e97a	9327	(uint8_t*)&i3c_bus_avb, 1);
cparata	1:fe40aec6e97a	9328	}
cparata	1:fe40aec6e97a	9329
cparata	1:fe40aec6e97a	9330	bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
cparata	1:fe40aec6e97a	9331	if ( ( ret == 0 ) && ( i3c_bus_avb.i3c_bus_avb_sel != bit_val ) ) {
cparata	1:fe40aec6e97a	9332	i3c_bus_avb.i3c_bus_avb_sel = bit_val;
cparata	1:fe40aec6e97a	9333	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	1:fe40aec6e97a	9334	(uint8_t*)&i3c_bus_avb, 1);
cparata	1:fe40aec6e97a	9335	}
cparata	1:fe40aec6e97a	9336	if (ret == 0) {
cparata	1:fe40aec6e97a	9337	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C,
cparata	1:fe40aec6e97a	9338	(uint8_t*)&ctrl4_c, 1);
cparata	1:fe40aec6e97a	9339	}
cparata	1:fe40aec6e97a	9340	bit_val = ( (uint8_t)val.ui_bus_md & 0x02U ) >> 1;
cparata	1:fe40aec6e97a	9341	if ( ( ret == 0 ) && ( ctrl4_c.i2c_disable != bit_val ) ) {
cparata	1:fe40aec6e97a	9342	ctrl4_c.i2c_disable = bit_val;
cparata	1:fe40aec6e97a	9343	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C,
cparata	1:fe40aec6e97a	9344	(uint8_t*)&ctrl4_c, 1);
cparata	1:fe40aec6e97a	9345	}
cparata	1:fe40aec6e97a	9346	if (ret == 0) {
cparata	1:fe40aec6e97a	9347	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C,
cparata	1:fe40aec6e97a	9348	(uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9349	}
cparata	1:fe40aec6e97a	9350	bit_val = (uint8_t)val.ui_bus_md & 0x01U;
cparata	1:fe40aec6e97a	9351	if ( ( ret == 0 ) && ( ctrl3_c.sim != bit_val ) ) {
cparata	1:fe40aec6e97a	9352	ctrl3_c.sim = bit_val;
cparata	1:fe40aec6e97a	9353	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C,
cparata	1:fe40aec6e97a	9354	(uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9355	}
cparata	1:fe40aec6e97a	9356	}
cparata	1:fe40aec6e97a	9357
cparata	1:fe40aec6e97a	9358	return ret;
cparata	1:fe40aec6e97a	9359
cparata	1:fe40aec6e97a	9360	}
cparata	1:fe40aec6e97a	9361
cparata	1:fe40aec6e97a	9362	/**
cparata	1:fe40aec6e97a	9363	* @brief Get the bus operating mode.[get]
cparata	1:fe40aec6e97a	9364	*
cparata	1:fe40aec6e97a	9365	* @param ctx communication interface handler. Use NULL to ingnore
cparata	1:fe40aec6e97a	9366	* this interface.(ptr)
cparata	1:fe40aec6e97a	9367	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	1:fe40aec6e97a	9368	* to ingnore this interface.(ptr)
cparata	1:fe40aec6e97a	9369	* @param val retrieves the bus operating mode for both the main
cparata	1:fe40aec6e97a	9370	* and the auxiliary interface.(ptr)
cparata	1:fe40aec6e97a	9371	*
cparata	1:fe40aec6e97a	9372	*/
cparata	1:fe40aec6e97a	9373	int32_t lsm6dsox_bus_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_ctx_t aux_ctx,
cparata	1:fe40aec6e97a	9374	lsm6dsox_bus_mode_t *val)
cparata	1:fe40aec6e97a	9375	{
cparata	1:fe40aec6e97a	9376	lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois;
cparata	1:fe40aec6e97a	9377	lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata	1:fe40aec6e97a	9378	lsm6dsox_ctrl9_xl_t ctrl9_xl;
cparata	1:fe40aec6e97a	9379	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	9380	lsm6dsox_ctrl4_c_t ctrl4_c;
cparata	1:fe40aec6e97a	9381
cparata	1:fe40aec6e97a	9382	int32_t ret = 0;
cparata	1:fe40aec6e97a	9383
cparata	1:fe40aec6e97a	9384	if (aux_ctx != NULL) {
cparata	1:fe40aec6e97a	9385	ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS,
cparata	1:fe40aec6e97a	9386	(uint8_t*)&spi2_ctrl1_ois, 1);
cparata	1:fe40aec6e97a	9387	switch ( spi2_ctrl1_ois.sim_ois ) {
cparata	1:fe40aec6e97a	9388	case LSM6DSOX_SPI_4W_AUX:
cparata	1:fe40aec6e97a	9389	val->aux_bus_md = LSM6DSOX_SPI_4W_AUX;
cparata	1:fe40aec6e97a	9390	break;
cparata	1:fe40aec6e97a	9391	case LSM6DSOX_SPI_3W_AUX:
cparata	1:fe40aec6e97a	9392	val->aux_bus_md = LSM6DSOX_SPI_3W_AUX;
cparata	1:fe40aec6e97a	9393	break;
cparata	1:fe40aec6e97a	9394	default:
cparata	1:fe40aec6e97a	9395	val->aux_bus_md = LSM6DSOX_SPI_4W_AUX;
cparata	1:fe40aec6e97a	9396	break;
cparata	1:fe40aec6e97a	9397	}
cparata	1:fe40aec6e97a	9398	}
cparata	1:fe40aec6e97a	9399
cparata	1:fe40aec6e97a	9400	if (ctx != NULL) {
cparata	1:fe40aec6e97a	9401	if (ret == 0) {
cparata	1:fe40aec6e97a	9402	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL,
cparata	1:fe40aec6e97a	9403	(uint8_t*)&ctrl9_xl, 1);
cparata	1:fe40aec6e97a	9404	}
cparata	1:fe40aec6e97a	9405	if (ret == 0) {
cparata	1:fe40aec6e97a	9406	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	1:fe40aec6e97a	9407	(uint8_t*)&i3c_bus_avb, 1);
cparata	1:fe40aec6e97a	9408	}
cparata	1:fe40aec6e97a	9409	if (ret == 0) {
cparata	1:fe40aec6e97a	9410	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C,
cparata	1:fe40aec6e97a	9411	(uint8_t*)&ctrl4_c, 1);
cparata	1:fe40aec6e97a	9412	}
cparata	1:fe40aec6e97a	9413	if (ret == 0) {
cparata	1:fe40aec6e97a	9414	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C,
cparata	1:fe40aec6e97a	9415	(uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9416
cparata	1:fe40aec6e97a	9417	switch ( ( i3c_bus_avb.i3c_bus_avb_sel << 4 ) &
cparata	1:fe40aec6e97a	9418	( ctrl9_xl.i3c_disable << 2 ) &
cparata	1:fe40aec6e97a	9419	( ctrl4_c.i2c_disable << 1) & ctrl3_c.sim ) {
cparata	1:fe40aec6e97a	9420	case LSM6DSOX_SEL_BY_HW:
cparata	1:fe40aec6e97a	9421	val->ui_bus_md = LSM6DSOX_SEL_BY_HW;
cparata	1:fe40aec6e97a	9422	break;
cparata	1:fe40aec6e97a	9423	case LSM6DSOX_SPI_4W:
cparata	1:fe40aec6e97a	9424	val->ui_bus_md = LSM6DSOX_SPI_4W;
cparata	1:fe40aec6e97a	9425	break;
cparata	1:fe40aec6e97a	9426	case LSM6DSOX_SPI_3W:
cparata	1:fe40aec6e97a	9427	val->ui_bus_md = LSM6DSOX_SPI_3W;
cparata	1:fe40aec6e97a	9428	break;
cparata	1:fe40aec6e97a	9429	case LSM6DSOX_I2C:
cparata	1:fe40aec6e97a	9430	val->ui_bus_md = LSM6DSOX_I2C;
cparata	1:fe40aec6e97a	9431	break;
cparata	1:fe40aec6e97a	9432	case LSM6DSOX_I3C_T_50us:
cparata	1:fe40aec6e97a	9433	val->ui_bus_md = LSM6DSOX_I3C_T_50us;
cparata	1:fe40aec6e97a	9434	break;
cparata	1:fe40aec6e97a	9435	case LSM6DSOX_I3C_T_2us:
cparata	1:fe40aec6e97a	9436	val->ui_bus_md = LSM6DSOX_I3C_T_2us;
cparata	1:fe40aec6e97a	9437	break;
cparata	1:fe40aec6e97a	9438	case LSM6DSOX_I3C_T_1ms:
cparata	1:fe40aec6e97a	9439	val->ui_bus_md = LSM6DSOX_I3C_T_1ms;
cparata	1:fe40aec6e97a	9440	break;
cparata	1:fe40aec6e97a	9441	case LSM6DSOX_I3C_T_25ms:
cparata	1:fe40aec6e97a	9442	val->ui_bus_md = LSM6DSOX_I3C_T_25ms;
cparata	1:fe40aec6e97a	9443	break;
cparata	1:fe40aec6e97a	9444	default:
cparata	1:fe40aec6e97a	9445	val->ui_bus_md = LSM6DSOX_SEL_BY_HW;
cparata	1:fe40aec6e97a	9446	break;
cparata	1:fe40aec6e97a	9447	}
cparata	1:fe40aec6e97a	9448	}
cparata	1:fe40aec6e97a	9449	}
cparata	1:fe40aec6e97a	9450	return ret;
cparata	1:fe40aec6e97a	9451	}
cparata	1:fe40aec6e97a	9452
cparata	1:fe40aec6e97a	9453	/**
cparata	1:fe40aec6e97a	9454	* @brief Get the status of the device.[get]
cparata	1:fe40aec6e97a	9455	*
cparata	1:fe40aec6e97a	9456	* @param ctx communication interface handler. Use NULL to ingnore
cparata	1:fe40aec6e97a	9457	* this interface.(ptr)
cparata	1:fe40aec6e97a	9458	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	1:fe40aec6e97a	9459	* to ingnore this interface.(ptr)
cparata	1:fe40aec6e97a	9460	* @param val the status of the device.(ptr)
cparata	1:fe40aec6e97a	9461	*
cparata	1:fe40aec6e97a	9462	*/
cparata	1:fe40aec6e97a	9463	int32_t lsm6dsox_status_get(lsm6dsox_ctx_t ctx, lsm6dsox_ctx_t aux_ctx,
cparata	1:fe40aec6e97a	9464	lsm6dsox_status_t *val)
cparata	1:fe40aec6e97a	9465	{
cparata	1:fe40aec6e97a	9466	lsm6dsox_spi2_status_reg_ois_t spi2_status_reg_ois;
cparata	1:fe40aec6e97a	9467	lsm6dsox_ui_status_reg_ois_t ui_status_reg_ois;
cparata	1:fe40aec6e97a	9468	lsm6dsox_status_reg_t status_reg;
cparata	1:fe40aec6e97a	9469	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	9470	int32_t ret;
cparata	1:fe40aec6e97a	9471
cparata	1:fe40aec6e97a	9472	ret = 0;
cparata	1:fe40aec6e97a	9473
cparata	1:fe40aec6e97a	9474	if (aux_ctx != NULL){
cparata	1:fe40aec6e97a	9475	ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
cparata	1:fe40aec6e97a	9476	(uint8_t*)&spi2_status_reg_ois, 1);
cparata	1:fe40aec6e97a	9477	val->ois_drdy_xl = spi2_status_reg_ois.xlda;
cparata	1:fe40aec6e97a	9478	val->ois_drdy_g = spi2_status_reg_ois.gda;
cparata	1:fe40aec6e97a	9479	val->ois_gyro_settling = spi2_status_reg_ois.gyro_settling;
cparata	1:fe40aec6e97a	9480	}
cparata	1:fe40aec6e97a	9481
cparata	1:fe40aec6e97a	9482	if (ctx != NULL){
cparata	1:fe40aec6e97a	9483	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9484	val->sw_reset = ctrl3_c.sw_reset;
cparata	1:fe40aec6e97a	9485	val->boot = ctrl3_c.boot;
cparata	1:fe40aec6e97a	9486
cparata	1:fe40aec6e97a	9487	if ( (ret == 0) && ( ctrl3_c.sw_reset == PROPERTY_DISABLE ) &&
cparata	1:fe40aec6e97a	9488	( ctrl3_c.boot == PROPERTY_DISABLE ) ) {
cparata	1:fe40aec6e97a	9489	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG,
cparata	1:fe40aec6e97a	9490	(uint8_t*)&status_reg, 1);
cparata	1:fe40aec6e97a	9491	val->drdy_xl = status_reg.xlda;
cparata	1:fe40aec6e97a	9492	val->drdy_g = status_reg.gda;
cparata	1:fe40aec6e97a	9493	val->drdy_temp = status_reg.tda;
cparata	1:fe40aec6e97a	9494	}
cparata	1:fe40aec6e97a	9495	if (aux_ctx == NULL){
cparata	1:fe40aec6e97a	9496	if (ret == 0) {
cparata	1:fe40aec6e97a	9497	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_STATUS_REG_OIS,
cparata	1:fe40aec6e97a	9498	(uint8_t*)&ui_status_reg_ois, 1);
cparata	1:fe40aec6e97a	9499	val->ois_drdy_xl = ui_status_reg_ois.xlda;
cparata	1:fe40aec6e97a	9500	val->ois_drdy_g = ui_status_reg_ois.gda;
cparata	1:fe40aec6e97a	9501	val->ois_gyro_settling = ui_status_reg_ois.gyro_settling;
cparata	1:fe40aec6e97a	9502	}
cparata	1:fe40aec6e97a	9503	}
cparata	1:fe40aec6e97a	9504	}
cparata	1:fe40aec6e97a	9505	return ret;
cparata	1:fe40aec6e97a	9506	}
cparata	1:fe40aec6e97a	9507
cparata	1:fe40aec6e97a	9508	/**
cparata	1:fe40aec6e97a	9509	* @brief Electrical pin configuration.[set]
cparata	1:fe40aec6e97a	9510	*
cparata	1:fe40aec6e97a	9511	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	9512	* @param val the electrical settings for the configurable
cparata	1:fe40aec6e97a	9513	* pins.
cparata	1:fe40aec6e97a	9514	*
cparata	1:fe40aec6e97a	9515	*/
cparata	1:fe40aec6e97a	9516	int32_t lsm6dsox_pin_conf_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pin_conf_t val)
cparata	1:fe40aec6e97a	9517	{
cparata	1:fe40aec6e97a	9518	lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata	1:fe40aec6e97a	9519	lsm6dsox_pin_ctrl_t pin_ctrl;
cparata	1:fe40aec6e97a	9520	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	9521	int32_t ret;
cparata	1:fe40aec6e97a	9522
cparata	1:fe40aec6e97a	9523	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
cparata	1:fe40aec6e97a	9524	if (ret == 0) {
cparata	1:fe40aec6e97a	9525	pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up;
cparata	1:fe40aec6e97a	9526	pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
cparata	1:fe40aec6e97a	9527	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
cparata	1:fe40aec6e97a	9528	}
cparata	1:fe40aec6e97a	9529	if (ret == 0) {
cparata	1:fe40aec6e97a	9530	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9531	}
cparata	1:fe40aec6e97a	9532	if (ret == 0) {
cparata	1:fe40aec6e97a	9533	ctrl3_c.pp_od = ~val.int1_int2_push_pull;
cparata	1:fe40aec6e97a	9534	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9535	}
cparata	1:fe40aec6e97a	9536	if (ret == 0) {
cparata	1:fe40aec6e97a	9537	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	1:fe40aec6e97a	9538	(uint8_t*)&i3c_bus_avb, 1);
cparata	1:fe40aec6e97a	9539	}
cparata	1:fe40aec6e97a	9540	if (ret == 0) {
cparata	1:fe40aec6e97a	9541	i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
cparata	1:fe40aec6e97a	9542	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	1:fe40aec6e97a	9543	(uint8_t*)&i3c_bus_avb, 1);
cparata	1:fe40aec6e97a	9544	}
cparata	1:fe40aec6e97a	9545	return ret;
cparata	1:fe40aec6e97a	9546	}
cparata	1:fe40aec6e97a	9547
cparata	1:fe40aec6e97a	9548	/**
cparata	1:fe40aec6e97a	9549	* @brief Electrical pin configuration.[get]
cparata	1:fe40aec6e97a	9550	*
cparata	1:fe40aec6e97a	9551	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	9552	* @param val the electrical settings for the configurable
cparata	1:fe40aec6e97a	9553	* pins.(ptr)
cparata	1:fe40aec6e97a	9554	*
cparata	1:fe40aec6e97a	9555	*/
cparata	1:fe40aec6e97a	9556	int32_t lsm6dsox_pin_conf_get(lsm6dsox_ctx_t ctx, lsm6dsox_pin_conf_t val)
cparata	1:fe40aec6e97a	9557	{
cparata	1:fe40aec6e97a	9558	lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata	1:fe40aec6e97a	9559	lsm6dsox_pin_ctrl_t pin_ctrl;
cparata	1:fe40aec6e97a	9560	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	9561	int32_t ret;
cparata	1:fe40aec6e97a	9562
cparata	1:fe40aec6e97a	9563	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
cparata	1:fe40aec6e97a	9564	if (ret == 0) {
cparata	1:fe40aec6e97a	9565	val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis;
cparata	1:fe40aec6e97a	9566	val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
cparata	1:fe40aec6e97a	9567	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9568	}
cparata	1:fe40aec6e97a	9569	if (ret == 0) {
cparata	1:fe40aec6e97a	9570	val->int1_int2_push_pull = ~ctrl3_c.pp_od;
cparata	1:fe40aec6e97a	9571	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata	1:fe40aec6e97a	9572	(uint8_t*)&i3c_bus_avb, 1);
cparata	1:fe40aec6e97a	9573	}
cparata	1:fe40aec6e97a	9574	if (ret == 0) {
cparata	1:fe40aec6e97a	9575	val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
cparata	1:fe40aec6e97a	9576	}
cparata	1:fe40aec6e97a	9577	return ret;
cparata	1:fe40aec6e97a	9578	}
cparata	1:fe40aec6e97a	9579
cparata	1:fe40aec6e97a	9580	/**
cparata	1:fe40aec6e97a	9581	* @brief Interrupt pins hardware signal configuration.[set]
cparata	1:fe40aec6e97a	9582	*
cparata	1:fe40aec6e97a	9583	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	9584	* @param val the pins hardware signal settings.
cparata	1:fe40aec6e97a	9585	*
cparata	1:fe40aec6e97a	9586	*/
cparata	1:fe40aec6e97a	9587	int32_t lsm6dsox_interrupt_mode_set(lsm6dsox_ctx_t *ctx,
cparata	1:fe40aec6e97a	9588	lsm6dsox_int_mode_t val)
cparata	1:fe40aec6e97a	9589	{
cparata	1:fe40aec6e97a	9590	lsm6dsox_tap_cfg0_t tap_cfg0;
cparata	1:fe40aec6e97a	9591	lsm6dsox_page_rw_t page_rw;
cparata	1:fe40aec6e97a	9592	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	9593	int32_t ret;
cparata	1:fe40aec6e97a	9594
cparata	1:fe40aec6e97a	9595	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9596	if (ret == 0) {
cparata	1:fe40aec6e97a	9597	ctrl3_c.h_lactive = val.active_low;
cparata	1:fe40aec6e97a	9598	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9599	}
cparata	1:fe40aec6e97a	9600	if (ret == 0) {
cparata	1:fe40aec6e97a	9601	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	1:fe40aec6e97a	9602	}
cparata	1:fe40aec6e97a	9603	if (ret == 0) {
cparata	1:fe40aec6e97a	9604	tap_cfg0.lir = val.base_latched;
cparata	1:fe40aec6e97a	9605	tap_cfg0.int_clr_on_read = val.base_latched \| val.emb_latched;
cparata	1:fe40aec6e97a	9606	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	1:fe40aec6e97a	9607	}
cparata	1:fe40aec6e97a	9608	if (ret == 0) {
cparata	1:fe40aec6e97a	9609	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	9610	}
cparata	1:fe40aec6e97a	9611	if (ret == 0) {
cparata	1:fe40aec6e97a	9612	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	1:fe40aec6e97a	9613	}
cparata	1:fe40aec6e97a	9614	if (ret == 0) {
cparata	1:fe40aec6e97a	9615	page_rw.emb_func_lir = val.emb_latched;
cparata	1:fe40aec6e97a	9616	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	1:fe40aec6e97a	9617	}
cparata	1:fe40aec6e97a	9618	if (ret == 0) {
cparata	1:fe40aec6e97a	9619	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	9620	}
cparata	1:fe40aec6e97a	9621	return ret;
cparata	1:fe40aec6e97a	9622	}
cparata	1:fe40aec6e97a	9623
cparata	1:fe40aec6e97a	9624	/**
cparata	1:fe40aec6e97a	9625	* @brief Interrupt pins hardware signal configuration.[get]
cparata	1:fe40aec6e97a	9626	*
cparata	1:fe40aec6e97a	9627	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	9628	* @param val the pins hardware signal settings.(ptr)
cparata	1:fe40aec6e97a	9629	*
cparata	1:fe40aec6e97a	9630	*/
cparata	1:fe40aec6e97a	9631	int32_t lsm6dsox_interrupt_mode_get(lsm6dsox_ctx_t *ctx,
cparata	1:fe40aec6e97a	9632	lsm6dsox_int_mode_t *val)
cparata	1:fe40aec6e97a	9633	{
cparata	1:fe40aec6e97a	9634	lsm6dsox_tap_cfg0_t tap_cfg0;
cparata	1:fe40aec6e97a	9635	lsm6dsox_page_rw_t page_rw;
cparata	1:fe40aec6e97a	9636	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	9637	int32_t ret;
cparata	1:fe40aec6e97a	9638
cparata	1:fe40aec6e97a	9639	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	1:fe40aec6e97a	9640	if (ret == 0) {
cparata	1:fe40aec6e97a	9641	ctrl3_c.h_lactive = val->active_low;
cparata	1:fe40aec6e97a	9642	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	1:fe40aec6e97a	9643	}
cparata	1:fe40aec6e97a	9644	if (ret == 0) {
cparata	1:fe40aec6e97a	9645	tap_cfg0.lir = val->base_latched;
cparata	1:fe40aec6e97a	9646	tap_cfg0.int_clr_on_read = val->base_latched \| val->emb_latched;
cparata	1:fe40aec6e97a	9647	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	9648	}
cparata	1:fe40aec6e97a	9649	if (ret == 0) {
cparata	1:fe40aec6e97a	9650	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	1:fe40aec6e97a	9651	}
cparata	1:fe40aec6e97a	9652	if (ret == 0) {
cparata	1:fe40aec6e97a	9653	page_rw.emb_func_lir = val->emb_latched;
cparata	1:fe40aec6e97a	9654	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	1:fe40aec6e97a	9655	}
cparata	1:fe40aec6e97a	9656	if (ret == 0) {
cparata	1:fe40aec6e97a	9657	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	9658	}
cparata	1:fe40aec6e97a	9659	return ret;
cparata	1:fe40aec6e97a	9660	}
cparata	1:fe40aec6e97a	9661
cparata	1:fe40aec6e97a	9662	/**
cparata	1:fe40aec6e97a	9663	* @brief Route interrupt signals on int1 pin.[set]
cparata	1:fe40aec6e97a	9664	*
cparata	1:fe40aec6e97a	9665	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	9666	* @param val the signals to route on int1 pin.
cparata	1:fe40aec6e97a	9667	*
cparata	1:fe40aec6e97a	9668	*/
cparata	1:fe40aec6e97a	9669	int32_t lsm6dsox_pin_int1_route_set(lsm6dsox_ctx_t *ctx,
cparata	1:fe40aec6e97a	9670	lsm6dsox_pin_int1_route_t val)
cparata	1:fe40aec6e97a	9671	{
cparata	1:fe40aec6e97a	9672	lsm6dsox_pin_int2_route_t pin_int2_route;
cparata	1:fe40aec6e97a	9673	lsm6dsox_emb_func_int1_t emb_func_int1;
cparata	1:fe40aec6e97a	9674	lsm6dsox_fsm_int1_a_t fsm_int1_a;
cparata	1:fe40aec6e97a	9675	lsm6dsox_fsm_int1_b_t fsm_int1_b;
cparata	1:fe40aec6e97a	9676	lsm6dsox_int1_ctrl_t int1_ctrl;
cparata	1:fe40aec6e97a	9677	lsm6dsox_int2_ctrl_t int2_ctrl;
cparata	1:fe40aec6e97a	9678	lsm6dsox_mlc_int1_t mlc_int1;
cparata	1:fe40aec6e97a	9679	lsm6dsox_tap_cfg2_t tap_cfg2;
cparata	1:fe40aec6e97a	9680	lsm6dsox_md2_cfg_t md2_cfg;
cparata	1:fe40aec6e97a	9681	lsm6dsox_md1_cfg_t md1_cfg;
cparata	1:fe40aec6e97a	9682	lsm6dsox_ctrl4_c_t ctrl4_c;
cparata	1:fe40aec6e97a	9683	int32_t ret;
cparata	1:fe40aec6e97a	9684
cparata	1:fe40aec6e97a	9685	int1_ctrl.int1_drdy_xl = val.drdy_xl;
cparata	1:fe40aec6e97a	9686	int1_ctrl.int1_drdy_g = val.drdy_g;
cparata	1:fe40aec6e97a	9687	int1_ctrl.int1_boot = val.boot;
cparata	1:fe40aec6e97a	9688	int1_ctrl.int1_fifo_th = val.fifo_th;
cparata	1:fe40aec6e97a	9689	int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
cparata	1:fe40aec6e97a	9690	int1_ctrl.int1_fifo_full = val.fifo_full;
cparata	1:fe40aec6e97a	9691	int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
cparata	1:fe40aec6e97a	9692	int1_ctrl.den_drdy_flag = val.den_flag;
cparata	1:fe40aec6e97a	9693
cparata	1:fe40aec6e97a	9694	md1_cfg.int1_shub = val.sh_endop;
cparata	1:fe40aec6e97a	9695	md1_cfg.int1_6d = val.six_d;
cparata	1:fe40aec6e97a	9696	md1_cfg.int1_double_tap = val.double_tap;
cparata	1:fe40aec6e97a	9697	md1_cfg.int1_ff = val.free_fall;
cparata	1:fe40aec6e97a	9698	md1_cfg.int1_wu = val.wake_up;
cparata	1:fe40aec6e97a	9699	md1_cfg.int1_single_tap = val.single_tap;
cparata	1:fe40aec6e97a	9700	md1_cfg.int1_sleep_change = val.sleep_change;
cparata	1:fe40aec6e97a	9701
cparata	1:fe40aec6e97a	9702	emb_func_int1.int1_step_detector = val.step_detector;
cparata	1:fe40aec6e97a	9703	emb_func_int1.int1_tilt = val.tilt;
cparata	1:fe40aec6e97a	9704	emb_func_int1.int1_sig_mot = val.sig_mot;
cparata	1:fe40aec6e97a	9705	emb_func_int1.int1_fsm_lc = val.fsm_lc;
cparata	1:fe40aec6e97a	9706
cparata	1:fe40aec6e97a	9707	fsm_int1_a.int1_fsm1 = val.fsm1;
cparata	1:fe40aec6e97a	9708	fsm_int1_a.int1_fsm2 = val.fsm2;
cparata	1:fe40aec6e97a	9709	fsm_int1_a.int1_fsm3 = val.fsm3;
cparata	1:fe40aec6e97a	9710	fsm_int1_a.int1_fsm4 = val.fsm4;
cparata	1:fe40aec6e97a	9711	fsm_int1_a.int1_fsm5 = val.fsm5;
cparata	1:fe40aec6e97a	9712	fsm_int1_a.int1_fsm6 = val.fsm6;
cparata	1:fe40aec6e97a	9713	fsm_int1_a.int1_fsm7 = val.fsm7;
cparata	1:fe40aec6e97a	9714	fsm_int1_a.int1_fsm8 = val.fsm8;
cparata	1:fe40aec6e97a	9715
cparata	1:fe40aec6e97a	9716	fsm_int1_b.int1_fsm9 = val.fsm9 ;
cparata	1:fe40aec6e97a	9717	fsm_int1_b.int1_fsm10 = val.fsm10;
cparata	1:fe40aec6e97a	9718	fsm_int1_b.int1_fsm11 = val.fsm11;
cparata	1:fe40aec6e97a	9719	fsm_int1_b.int1_fsm12 = val.fsm12;
cparata	1:fe40aec6e97a	9720	fsm_int1_b.int1_fsm13 = val.fsm13;
cparata	1:fe40aec6e97a	9721	fsm_int1_b.int1_fsm14 = val.fsm14;
cparata	1:fe40aec6e97a	9722	fsm_int1_b.int1_fsm15 = val.fsm15;
cparata	1:fe40aec6e97a	9723	fsm_int1_b.int1_fsm16 = val.fsm16;
cparata	1:fe40aec6e97a	9724
cparata	1:fe40aec6e97a	9725	mlc_int1.int1_mlc1 = val.mlc1;
cparata	1:fe40aec6e97a	9726	mlc_int1.int1_mlc2 = val.mlc2;
cparata	1:fe40aec6e97a	9727	mlc_int1.int1_mlc3 = val.mlc3;
cparata	1:fe40aec6e97a	9728	mlc_int1.int1_mlc4 = val.mlc4;
cparata	1:fe40aec6e97a	9729	mlc_int1.int1_mlc5 = val.mlc5;
cparata	1:fe40aec6e97a	9730	mlc_int1.int1_mlc6 = val.mlc6;
cparata	1:fe40aec6e97a	9731	mlc_int1.int1_mlc7 = val.mlc7;
cparata	1:fe40aec6e97a	9732	mlc_int1.int1_mlc8 = val.mlc8;
cparata	1:fe40aec6e97a	9733
cparata	1:fe40aec6e97a	9734	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	1:fe40aec6e97a	9735	if (ret == 0) {
cparata	1:fe40aec6e97a	9736	if( ( val.drdy_temp \| val.timestamp ) != PROPERTY_DISABLE) {
cparata	1:fe40aec6e97a	9737	ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	9738	}
cparata	1:fe40aec6e97a	9739	else{
cparata	1:fe40aec6e97a	9740	ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	9741	}
cparata	1:fe40aec6e97a	9742	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	1:fe40aec6e97a	9743	}
cparata	1:fe40aec6e97a	9744
cparata	1:fe40aec6e97a	9745	if (ret == 0) {
cparata	1:fe40aec6e97a	9746	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	9747	}
cparata	1:fe40aec6e97a	9748	if (ret == 0) {
cparata	1:fe40aec6e97a	9749	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1,
cparata	1:fe40aec6e97a	9750	(uint8_t*)&mlc_int1, 1);
cparata	1:fe40aec6e97a	9751	}
cparata	1:fe40aec6e97a	9752	if (ret == 0) {
cparata	1:fe40aec6e97a	9753	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT1,
cparata	1:fe40aec6e97a	9754	(uint8_t*)&emb_func_int1, 1);
cparata	1:fe40aec6e97a	9755	}
cparata	1:fe40aec6e97a	9756	if (ret == 0) {
cparata	1:fe40aec6e97a	9757	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_A,
cparata	1:fe40aec6e97a	9758	(uint8_t*)&fsm_int1_a, 1);
cparata	1:fe40aec6e97a	9759	}
cparata	1:fe40aec6e97a	9760	if (ret == 0) {
cparata	1:fe40aec6e97a	9761	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_B,
cparata	1:fe40aec6e97a	9762	(uint8_t*)&fsm_int1_b, 1);
cparata	1:fe40aec6e97a	9763	}
cparata	1:fe40aec6e97a	9764	if (ret == 0) {
cparata	1:fe40aec6e97a	9765	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	9766	}
cparata	1:fe40aec6e97a	9767
cparata	1:fe40aec6e97a	9768	if (ret == 0) {
cparata	1:fe40aec6e97a	9769	if ( ( emb_func_int1.int1_fsm_lc
cparata	1:fe40aec6e97a	9770	\| emb_func_int1.int1_sig_mot
cparata	1:fe40aec6e97a	9771	\| emb_func_int1.int1_step_detector
cparata	1:fe40aec6e97a	9772	\| emb_func_int1.int1_tilt
cparata	1:fe40aec6e97a	9773	\| fsm_int1_a.int1_fsm1
cparata	1:fe40aec6e97a	9774	\| fsm_int1_a.int1_fsm2
cparata	1:fe40aec6e97a	9775	\| fsm_int1_a.int1_fsm3
cparata	1:fe40aec6e97a	9776	\| fsm_int1_a.int1_fsm4
cparata	1:fe40aec6e97a	9777	\| fsm_int1_a.int1_fsm5
cparata	1:fe40aec6e97a	9778	\| fsm_int1_a.int1_fsm6
cparata	1:fe40aec6e97a	9779	\| fsm_int1_a.int1_fsm7
cparata	1:fe40aec6e97a	9780	\| fsm_int1_a.int1_fsm8
cparata	1:fe40aec6e97a	9781	\| fsm_int1_b.int1_fsm9
cparata	1:fe40aec6e97a	9782	\| fsm_int1_b.int1_fsm10
cparata	1:fe40aec6e97a	9783	\| fsm_int1_b.int1_fsm11
cparata	1:fe40aec6e97a	9784	\| fsm_int1_b.int1_fsm12
cparata	1:fe40aec6e97a	9785	\| fsm_int1_b.int1_fsm13
cparata	1:fe40aec6e97a	9786	\| fsm_int1_b.int1_fsm14
cparata	1:fe40aec6e97a	9787	\| fsm_int1_b.int1_fsm15
cparata	1:fe40aec6e97a	9788	\| fsm_int1_b.int1_fsm16
cparata	1:fe40aec6e97a	9789	\| mlc_int1.int1_mlc1
cparata	1:fe40aec6e97a	9790	\| mlc_int1.int1_mlc2
cparata	1:fe40aec6e97a	9791	\| mlc_int1.int1_mlc3
cparata	1:fe40aec6e97a	9792	\| mlc_int1.int1_mlc4
cparata	1:fe40aec6e97a	9793	\| mlc_int1.int1_mlc5
cparata	1:fe40aec6e97a	9794	\| mlc_int1.int1_mlc6
cparata	1:fe40aec6e97a	9795	\| mlc_int1.int1_mlc7
cparata	1:fe40aec6e97a	9796	\| mlc_int1.int1_mlc8) != PROPERTY_DISABLE){
cparata	1:fe40aec6e97a	9797	md1_cfg.int1_emb_func = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	9798	}
cparata	1:fe40aec6e97a	9799	else{
cparata	1:fe40aec6e97a	9800	md1_cfg.int1_emb_func = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	9801	}
cparata	1:fe40aec6e97a	9802	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT1_CTRL,
cparata	1:fe40aec6e97a	9803	(uint8_t*)&int1_ctrl, 1);
cparata	1:fe40aec6e97a	9804	}
cparata	1:fe40aec6e97a	9805	if (ret == 0) {
cparata	1:fe40aec6e97a	9806	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&md1_cfg, 1);
cparata	1:fe40aec6e97a	9807	}
cparata	1:fe40aec6e97a	9808
cparata	1:fe40aec6e97a	9809	if (ret == 0) {
cparata	1:fe40aec6e97a	9810	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
cparata	1:fe40aec6e97a	9811	}
cparata	1:fe40aec6e97a	9812	if (ret == 0) {
cparata	1:fe40aec6e97a	9813	int2_ctrl.int2_drdy_temp = val.drdy_temp;
cparata	1:fe40aec6e97a	9814	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
cparata	1:fe40aec6e97a	9815	}
cparata	1:fe40aec6e97a	9816	if (ret == 0) {
cparata	1:fe40aec6e97a	9817	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	1:fe40aec6e97a	9818	}
cparata	1:fe40aec6e97a	9819	if (ret == 0) {
cparata	1:fe40aec6e97a	9820	md2_cfg.int2_timestamp = val.timestamp;
cparata	1:fe40aec6e97a	9821	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	1:fe40aec6e97a	9822	}
cparata	1:fe40aec6e97a	9823
cparata	1:fe40aec6e97a	9824	if (ret == 0) {
cparata	1:fe40aec6e97a	9825	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	1:fe40aec6e97a	9826	}
cparata	1:fe40aec6e97a	9827	if (ret == 0) {
cparata	1:fe40aec6e97a	9828	ret = lsm6dsox_pin_int2_route_get(ctx, NULL, &pin_int2_route);
cparata	1:fe40aec6e97a	9829	}
cparata	1:fe40aec6e97a	9830	if (ret == 0) {
cparata	1:fe40aec6e97a	9831	if ( ( pin_int2_route.fifo_bdr
cparata	1:fe40aec6e97a	9832	\| pin_int2_route.drdy_g
cparata	1:fe40aec6e97a	9833	\| pin_int2_route.drdy_temp
cparata	1:fe40aec6e97a	9834	\| pin_int2_route.drdy_xl
cparata	1:fe40aec6e97a	9835	\| pin_int2_route.fifo_full
cparata	1:fe40aec6e97a	9836	\| pin_int2_route.fifo_ovr
cparata	1:fe40aec6e97a	9837	\| pin_int2_route.fifo_th
cparata	1:fe40aec6e97a	9838	\| pin_int2_route.six_d
cparata	1:fe40aec6e97a	9839	\| pin_int2_route.double_tap
cparata	1:fe40aec6e97a	9840	\| pin_int2_route.free_fall
cparata	1:fe40aec6e97a	9841	\| pin_int2_route.wake_up
cparata	1:fe40aec6e97a	9842	\| pin_int2_route.single_tap
cparata	1:fe40aec6e97a	9843	\| pin_int2_route.sleep_change
cparata	1:fe40aec6e97a	9844	\| int1_ctrl.den_drdy_flag
cparata	1:fe40aec6e97a	9845	\| int1_ctrl.int1_boot
cparata	1:fe40aec6e97a	9846	\| int1_ctrl.int1_cnt_bdr
cparata	1:fe40aec6e97a	9847	\| int1_ctrl.int1_drdy_g
cparata	1:fe40aec6e97a	9848	\| int1_ctrl.int1_drdy_xl
cparata	1:fe40aec6e97a	9849	\| int1_ctrl.int1_fifo_full
cparata	1:fe40aec6e97a	9850	\| int1_ctrl.int1_fifo_ovr
cparata	1:fe40aec6e97a	9851	\| int1_ctrl.int1_fifo_th
cparata	1:fe40aec6e97a	9852	\| md1_cfg.int1_shub
cparata	1:fe40aec6e97a	9853	\| md1_cfg.int1_6d
cparata	1:fe40aec6e97a	9854	\| md1_cfg.int1_double_tap
cparata	1:fe40aec6e97a	9855	\| md1_cfg.int1_ff
cparata	1:fe40aec6e97a	9856	\| md1_cfg.int1_wu
cparata	1:fe40aec6e97a	9857	\| md1_cfg.int1_single_tap
cparata	1:fe40aec6e97a	9858	\| md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
cparata	1:fe40aec6e97a	9859	tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	9860	}
cparata	1:fe40aec6e97a	9861	else{
cparata	1:fe40aec6e97a	9862	tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	9863	}
cparata	1:fe40aec6e97a	9864	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	1:fe40aec6e97a	9865	}
cparata	1:fe40aec6e97a	9866	return ret;
cparata	1:fe40aec6e97a	9867	}
cparata	1:fe40aec6e97a	9868
cparata	1:fe40aec6e97a	9869	/**
cparata	1:fe40aec6e97a	9870	* @brief Route interrupt signals on int1 pin.[get]
cparata	1:fe40aec6e97a	9871	*
cparata	1:fe40aec6e97a	9872	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	9873	* @param val the signals that are routed on int1 pin.(ptr)
cparata	1:fe40aec6e97a	9874	*
cparata	1:fe40aec6e97a	9875	*/
cparata	1:fe40aec6e97a	9876	int32_t lsm6dsox_pin_int1_route_get(lsm6dsox_ctx_t *ctx,
cparata	1:fe40aec6e97a	9877	lsm6dsox_pin_int1_route_t *val)
cparata	1:fe40aec6e97a	9878	{
cparata	1:fe40aec6e97a	9879	lsm6dsox_emb_func_int1_t emb_func_int1;
cparata	1:fe40aec6e97a	9880	lsm6dsox_fsm_int1_a_t fsm_int1_a;
cparata	1:fe40aec6e97a	9881	lsm6dsox_fsm_int1_b_t fsm_int1_b;
cparata	1:fe40aec6e97a	9882	lsm6dsox_int1_ctrl_t int1_ctrl;
cparata	1:fe40aec6e97a	9883	lsm6dsox_int2_ctrl_t int2_ctrl;
cparata	1:fe40aec6e97a	9884	lsm6dsox_mlc_int1_t mlc_int1;
cparata	1:fe40aec6e97a	9885	lsm6dsox_md2_cfg_t md2_cfg;
cparata	1:fe40aec6e97a	9886	lsm6dsox_md1_cfg_t md1_cfg;
cparata	1:fe40aec6e97a	9887	lsm6dsox_ctrl4_c_t ctrl4_c;
cparata	1:fe40aec6e97a	9888	int32_t ret;
cparata	1:fe40aec6e97a	9889
cparata	1:fe40aec6e97a	9890	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	9891	if (ret == 0) {
cparata	1:fe40aec6e97a	9892	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT1,
cparata	1:fe40aec6e97a	9893	(uint8_t*)&mlc_int1, 1);
cparata	1:fe40aec6e97a	9894	}
cparata	1:fe40aec6e97a	9895	if (ret == 0) {
cparata	1:fe40aec6e97a	9896	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT1,
cparata	1:fe40aec6e97a	9897	(uint8_t*)&emb_func_int1, 1);
cparata	1:fe40aec6e97a	9898	}
cparata	1:fe40aec6e97a	9899	if (ret == 0) {
cparata	1:fe40aec6e97a	9900	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_A,
cparata	1:fe40aec6e97a	9901	(uint8_t*)&fsm_int1_a, 1);
cparata	1:fe40aec6e97a	9902	}
cparata	1:fe40aec6e97a	9903	if (ret == 0) {
cparata	1:fe40aec6e97a	9904	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_B,
cparata	1:fe40aec6e97a	9905	(uint8_t*)&fsm_int1_b, 1);
cparata	1:fe40aec6e97a	9906	}
cparata	1:fe40aec6e97a	9907	if (ret == 0) {
cparata	1:fe40aec6e97a	9908	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	9909	}
cparata	1:fe40aec6e97a	9910	if (ret == 0) {
cparata	1:fe40aec6e97a	9911	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT1_CTRL,
cparata	1:fe40aec6e97a	9912	(uint8_t*)&int1_ctrl, 1);
cparata	1:fe40aec6e97a	9913	}
cparata	1:fe40aec6e97a	9914	if (ret == 0) {
cparata	1:fe40aec6e97a	9915	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&md1_cfg, 1);
cparata	1:fe40aec6e97a	9916	}
cparata	1:fe40aec6e97a	9917	if (ret == 0) {
cparata	1:fe40aec6e97a	9918	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	1:fe40aec6e97a	9919	}
cparata	1:fe40aec6e97a	9920	if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE){
cparata	1:fe40aec6e97a	9921	if (ret == 0) {
cparata	1:fe40aec6e97a	9922	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
cparata	1:fe40aec6e97a	9923	val->drdy_temp = int2_ctrl.int2_drdy_temp;
cparata	1:fe40aec6e97a	9924	}
cparata	1:fe40aec6e97a	9925	if (ret == 0) {
cparata	1:fe40aec6e97a	9926	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	1:fe40aec6e97a	9927	val->timestamp = md2_cfg.int2_timestamp;
cparata	1:fe40aec6e97a	9928	}
cparata	1:fe40aec6e97a	9929	}
cparata	1:fe40aec6e97a	9930	else {
cparata	1:fe40aec6e97a	9931	val->drdy_temp = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	9932	val->timestamp = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	9933	}
cparata	1:fe40aec6e97a	9934
cparata	1:fe40aec6e97a	9935	val->drdy_xl = int1_ctrl.int1_drdy_xl;
cparata	1:fe40aec6e97a	9936	val->drdy_g = int1_ctrl.int1_drdy_g;
cparata	1:fe40aec6e97a	9937	val->boot = int1_ctrl.int1_boot;
cparata	1:fe40aec6e97a	9938	val->fifo_th = int1_ctrl.int1_fifo_th;
cparata	1:fe40aec6e97a	9939	val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
cparata	1:fe40aec6e97a	9940	val->fifo_full = int1_ctrl.int1_fifo_full;
cparata	1:fe40aec6e97a	9941	val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
cparata	1:fe40aec6e97a	9942	val->den_flag = int1_ctrl.den_drdy_flag;
cparata	1:fe40aec6e97a	9943
cparata	1:fe40aec6e97a	9944	val->sh_endop = md1_cfg.int1_shub;
cparata	1:fe40aec6e97a	9945	val->six_d = md1_cfg.int1_6d;
cparata	1:fe40aec6e97a	9946	val->double_tap = md1_cfg.int1_double_tap;
cparata	1:fe40aec6e97a	9947	val->free_fall = md1_cfg.int1_ff;
cparata	1:fe40aec6e97a	9948	val->wake_up = md1_cfg.int1_wu;
cparata	1:fe40aec6e97a	9949	val->single_tap = md1_cfg.int1_single_tap;
cparata	1:fe40aec6e97a	9950	val->sleep_change = md1_cfg.int1_sleep_change;
cparata	1:fe40aec6e97a	9951
cparata	1:fe40aec6e97a	9952	val->step_detector = emb_func_int1.int1_step_detector;
cparata	1:fe40aec6e97a	9953	val->tilt = emb_func_int1.int1_tilt;
cparata	1:fe40aec6e97a	9954	val->sig_mot = emb_func_int1.int1_sig_mot;
cparata	1:fe40aec6e97a	9955	val->fsm_lc = emb_func_int1.int1_fsm_lc;
cparata	1:fe40aec6e97a	9956
cparata	1:fe40aec6e97a	9957	val->fsm1 = fsm_int1_a.int1_fsm1;
cparata	1:fe40aec6e97a	9958	val->fsm2 = fsm_int1_a.int1_fsm2;
cparata	1:fe40aec6e97a	9959	val->fsm3 = fsm_int1_a.int1_fsm3;
cparata	1:fe40aec6e97a	9960	val->fsm4 = fsm_int1_a.int1_fsm4;
cparata	1:fe40aec6e97a	9961	val->fsm5 = fsm_int1_a.int1_fsm5;
cparata	1:fe40aec6e97a	9962	val->fsm6 = fsm_int1_a.int1_fsm6;
cparata	1:fe40aec6e97a	9963	val->fsm7 = fsm_int1_a.int1_fsm7;
cparata	1:fe40aec6e97a	9964	val->fsm8 = fsm_int1_a.int1_fsm8;
cparata	1:fe40aec6e97a	9965
cparata	1:fe40aec6e97a	9966	val->fsm9 = fsm_int1_b.int1_fsm9;
cparata	1:fe40aec6e97a	9967	val->fsm10 = fsm_int1_b.int1_fsm10;
cparata	1:fe40aec6e97a	9968	val->fsm11 = fsm_int1_b.int1_fsm11;
cparata	1:fe40aec6e97a	9969	val->fsm12 = fsm_int1_b.int1_fsm12;
cparata	1:fe40aec6e97a	9970	val->fsm13 = fsm_int1_b.int1_fsm13;
cparata	1:fe40aec6e97a	9971	val->fsm14 = fsm_int1_b.int1_fsm14;
cparata	1:fe40aec6e97a	9972	val->fsm15 = fsm_int1_b.int1_fsm15;
cparata	1:fe40aec6e97a	9973	val->fsm16 = fsm_int1_b.int1_fsm16;
cparata	1:fe40aec6e97a	9974
cparata	1:fe40aec6e97a	9975	val->mlc1 = mlc_int1.int1_mlc1;
cparata	1:fe40aec6e97a	9976	val->mlc2 = mlc_int1.int1_mlc2;
cparata	1:fe40aec6e97a	9977	val->mlc3 = mlc_int1.int1_mlc3;
cparata	1:fe40aec6e97a	9978	val->mlc4 = mlc_int1.int1_mlc4;
cparata	1:fe40aec6e97a	9979	val->mlc5 = mlc_int1.int1_mlc5;
cparata	1:fe40aec6e97a	9980	val->mlc6 = mlc_int1.int1_mlc6;
cparata	1:fe40aec6e97a	9981	val->mlc7 = mlc_int1.int1_mlc7;
cparata	1:fe40aec6e97a	9982	val->mlc8 = mlc_int1.int1_mlc8;
cparata	1:fe40aec6e97a	9983
cparata	1:fe40aec6e97a	9984	return ret;
cparata	1:fe40aec6e97a	9985	}
cparata	1:fe40aec6e97a	9986
cparata	1:fe40aec6e97a	9987	/**
cparata	1:fe40aec6e97a	9988	* @brief Route interrupt signals on int2 pin.[set]
cparata	1:fe40aec6e97a	9989	*
cparata	1:fe40aec6e97a	9990	* @param ctx communication interface handler. Use NULL to ingnore
cparata	1:fe40aec6e97a	9991	* this interface.(ptr)
cparata	1:fe40aec6e97a	9992	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	1:fe40aec6e97a	9993	* to ingnore this interface.(ptr)
cparata	1:fe40aec6e97a	9994	* @param val the signals to route on int2 pin.
cparata	1:fe40aec6e97a	9995	*
cparata	1:fe40aec6e97a	9996	*/
cparata	1:fe40aec6e97a	9997	int32_t lsm6dsox_pin_int2_route_set(lsm6dsox_ctx_t ctx, lsm6dsox_ctx_t aux_ctx,
cparata	1:fe40aec6e97a	9998	lsm6dsox_pin_int2_route_t val)
cparata	1:fe40aec6e97a	9999	{
cparata	1:fe40aec6e97a	10000	lsm6dsox_pin_int1_route_t pin_int1_route;
cparata	1:fe40aec6e97a	10001	lsm6dsox_emb_func_int2_t emb_func_int2;
cparata	1:fe40aec6e97a	10002	lsm6dsox_spi2_int_ois_t spi2_int_ois;
cparata	1:fe40aec6e97a	10003	lsm6dsox_fsm_int2_a_t fsm_int2_a;
cparata	1:fe40aec6e97a	10004	lsm6dsox_fsm_int2_b_t fsm_int2_b;
cparata	1:fe40aec6e97a	10005	lsm6dsox_int2_ctrl_t int2_ctrl;
cparata	1:fe40aec6e97a	10006	lsm6dsox_mlc_int2_t mlc_int2;
cparata	1:fe40aec6e97a	10007	lsm6dsox_tap_cfg2_t tap_cfg2;
cparata	1:fe40aec6e97a	10008	lsm6dsox_md2_cfg_t md2_cfg;
cparata	1:fe40aec6e97a	10009	lsm6dsox_ctrl4_c_t ctrl4_c;
cparata	1:fe40aec6e97a	10010	int32_t ret;
cparata	1:fe40aec6e97a	10011
cparata	1:fe40aec6e97a	10012	ret = 0;
cparata	1:fe40aec6e97a	10013
cparata	1:fe40aec6e97a	10014	if( aux_ctx != NULL ) {
cparata	1:fe40aec6e97a	10015	ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS,
cparata	1:fe40aec6e97a	10016	(uint8_t*)&spi2_int_ois, 1);
cparata	1:fe40aec6e97a	10017	if (ret == 0) {
cparata	1:fe40aec6e97a	10018	spi2_int_ois.int2_drdy_ois = val.drdy_ois;
cparata	1:fe40aec6e97a	10019	ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS,
cparata	1:fe40aec6e97a	10020	(uint8_t*)&spi2_int_ois, 1);
cparata	1:fe40aec6e97a	10021	}
cparata	1:fe40aec6e97a	10022	}
cparata	1:fe40aec6e97a	10023
cparata	1:fe40aec6e97a	10024	if( ctx != NULL ) {
cparata	1:fe40aec6e97a	10025	int2_ctrl.int2_drdy_xl = val.drdy_xl;
cparata	1:fe40aec6e97a	10026	int2_ctrl.int2_drdy_g = val.drdy_g;
cparata	1:fe40aec6e97a	10027	int2_ctrl.int2_drdy_temp = val.drdy_temp;
cparata	1:fe40aec6e97a	10028	int2_ctrl.int2_fifo_th = val.fifo_th;
cparata	1:fe40aec6e97a	10029	int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
cparata	1:fe40aec6e97a	10030	int2_ctrl.int2_fifo_full = val.fifo_full;
cparata	1:fe40aec6e97a	10031	int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
cparata	1:fe40aec6e97a	10032
cparata	1:fe40aec6e97a	10033	md2_cfg.int2_timestamp = val.timestamp;
cparata	1:fe40aec6e97a	10034	md2_cfg.int2_6d = val.six_d;
cparata	1:fe40aec6e97a	10035	md2_cfg.int2_double_tap = val.double_tap;
cparata	1:fe40aec6e97a	10036	md2_cfg.int2_ff = val.free_fall;
cparata	1:fe40aec6e97a	10037	md2_cfg.int2_wu = val.wake_up;
cparata	1:fe40aec6e97a	10038	md2_cfg.int2_single_tap = val.single_tap;
cparata	1:fe40aec6e97a	10039	md2_cfg.int2_sleep_change = val.sleep_change;
cparata	1:fe40aec6e97a	10040
cparata	1:fe40aec6e97a	10041	emb_func_int2. int2_step_detector = val.step_detector;
cparata	1:fe40aec6e97a	10042	emb_func_int2.int2_tilt = val.tilt;
cparata	1:fe40aec6e97a	10043	emb_func_int2.int2_fsm_lc = val.fsm_lc;
cparata	1:fe40aec6e97a	10044
cparata	1:fe40aec6e97a	10045	fsm_int2_a.int2_fsm1 = val.fsm1;
cparata	1:fe40aec6e97a	10046	fsm_int2_a.int2_fsm2 = val.fsm2;
cparata	1:fe40aec6e97a	10047	fsm_int2_a.int2_fsm3 = val.fsm3;
cparata	1:fe40aec6e97a	10048	fsm_int2_a.int2_fsm4 = val.fsm4;
cparata	1:fe40aec6e97a	10049	fsm_int2_a.int2_fsm5 = val.fsm5;
cparata	1:fe40aec6e97a	10050	fsm_int2_a.int2_fsm6 = val.fsm6;
cparata	1:fe40aec6e97a	10051	fsm_int2_a.int2_fsm7 = val.fsm7;
cparata	1:fe40aec6e97a	10052	fsm_int2_a.int2_fsm8 = val.fsm8;
cparata	1:fe40aec6e97a	10053
cparata	1:fe40aec6e97a	10054	fsm_int2_b.int2_fsm9 = val.fsm9 ;
cparata	1:fe40aec6e97a	10055	fsm_int2_b.int2_fsm10 = val.fsm10;
cparata	1:fe40aec6e97a	10056	fsm_int2_b.int2_fsm11 = val.fsm11;
cparata	1:fe40aec6e97a	10057	fsm_int2_b.int2_fsm12 = val.fsm12;
cparata	1:fe40aec6e97a	10058	fsm_int2_b.int2_fsm13 = val.fsm13;
cparata	1:fe40aec6e97a	10059	fsm_int2_b.int2_fsm14 = val.fsm14;
cparata	1:fe40aec6e97a	10060	fsm_int2_b.int2_fsm15 = val.fsm15;
cparata	1:fe40aec6e97a	10061	fsm_int2_b.int2_fsm16 = val.fsm16;
cparata	1:fe40aec6e97a	10062
cparata	1:fe40aec6e97a	10063	mlc_int2.int2_mlc1 = val.mlc1;
cparata	1:fe40aec6e97a	10064	mlc_int2.int2_mlc2 = val.mlc2;
cparata	1:fe40aec6e97a	10065	mlc_int2.int2_mlc3 = val.mlc3;
cparata	1:fe40aec6e97a	10066	mlc_int2.int2_mlc4 = val.mlc4;
cparata	1:fe40aec6e97a	10067	mlc_int2.int2_mlc5 = val.mlc5;
cparata	1:fe40aec6e97a	10068	mlc_int2.int2_mlc6 = val.mlc6;
cparata	1:fe40aec6e97a	10069	mlc_int2.int2_mlc7 = val.mlc7;
cparata	1:fe40aec6e97a	10070	mlc_int2.int2_mlc8 = val.mlc8;
cparata	1:fe40aec6e97a	10071
cparata	1:fe40aec6e97a	10072	if (ret == 0) {
cparata	1:fe40aec6e97a	10073	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	1:fe40aec6e97a	10074	if (ret == 0) {
cparata	1:fe40aec6e97a	10075	if ( ( val.drdy_temp \| val.timestamp ) != PROPERTY_DISABLE ) {
cparata	1:fe40aec6e97a	10076	ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10077	}
cparata	1:fe40aec6e97a	10078	else{
cparata	1:fe40aec6e97a	10079	ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	10080	}
cparata	1:fe40aec6e97a	10081	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	1:fe40aec6e97a	10082	}
cparata	1:fe40aec6e97a	10083	}
cparata	1:fe40aec6e97a	10084
cparata	1:fe40aec6e97a	10085	if (ret == 0) {
cparata	1:fe40aec6e97a	10086	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	10087	}
cparata	1:fe40aec6e97a	10088	if (ret == 0) {
cparata	1:fe40aec6e97a	10089	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT2,
cparata	1:fe40aec6e97a	10090	(uint8_t*)&mlc_int2, 1);
cparata	1:fe40aec6e97a	10091	}
cparata	1:fe40aec6e97a	10092	if (ret == 0) {
cparata	1:fe40aec6e97a	10093	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT2,
cparata	1:fe40aec6e97a	10094	(uint8_t*)&emb_func_int2, 1);
cparata	1:fe40aec6e97a	10095	}
cparata	1:fe40aec6e97a	10096	if (ret == 0) {
cparata	1:fe40aec6e97a	10097	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_A,
cparata	1:fe40aec6e97a	10098	(uint8_t*)&fsm_int2_a, 1);
cparata	1:fe40aec6e97a	10099	}
cparata	1:fe40aec6e97a	10100	if (ret == 0) {
cparata	1:fe40aec6e97a	10101	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_B,
cparata	1:fe40aec6e97a	10102	(uint8_t*)&fsm_int2_b, 1);
cparata	1:fe40aec6e97a	10103	}
cparata	1:fe40aec6e97a	10104	if (ret == 0) {
cparata	1:fe40aec6e97a	10105	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	10106	}
cparata	1:fe40aec6e97a	10107
cparata	1:fe40aec6e97a	10108	if (ret == 0) {
cparata	1:fe40aec6e97a	10109	if (( emb_func_int2.int2_fsm_lc
cparata	1:fe40aec6e97a	10110	\| emb_func_int2.int2_sig_mot
cparata	1:fe40aec6e97a	10111	\| emb_func_int2.int2_step_detector
cparata	1:fe40aec6e97a	10112	\| emb_func_int2.int2_tilt
cparata	1:fe40aec6e97a	10113	\| fsm_int2_a.int2_fsm1
cparata	1:fe40aec6e97a	10114	\| fsm_int2_a.int2_fsm2
cparata	1:fe40aec6e97a	10115	\| fsm_int2_a.int2_fsm3
cparata	1:fe40aec6e97a	10116	\| fsm_int2_a.int2_fsm4
cparata	1:fe40aec6e97a	10117	\| fsm_int2_a.int2_fsm5
cparata	1:fe40aec6e97a	10118	\| fsm_int2_a.int2_fsm6
cparata	1:fe40aec6e97a	10119	\| fsm_int2_a.int2_fsm7
cparata	1:fe40aec6e97a	10120	\| fsm_int2_a.int2_fsm8
cparata	1:fe40aec6e97a	10121	\| fsm_int2_b.int2_fsm9
cparata	1:fe40aec6e97a	10122	\| fsm_int2_b.int2_fsm10
cparata	1:fe40aec6e97a	10123	\| fsm_int2_b.int2_fsm11
cparata	1:fe40aec6e97a	10124	\| fsm_int2_b.int2_fsm12
cparata	1:fe40aec6e97a	10125	\| fsm_int2_b.int2_fsm13
cparata	1:fe40aec6e97a	10126	\| fsm_int2_b.int2_fsm14
cparata	1:fe40aec6e97a	10127	\| fsm_int2_b.int2_fsm15
cparata	1:fe40aec6e97a	10128	\| fsm_int2_b.int2_fsm16
cparata	1:fe40aec6e97a	10129	\| mlc_int2.int2_mlc1
cparata	1:fe40aec6e97a	10130	\| mlc_int2.int2_mlc2
cparata	1:fe40aec6e97a	10131	\| mlc_int2.int2_mlc3
cparata	1:fe40aec6e97a	10132	\| mlc_int2.int2_mlc4
cparata	1:fe40aec6e97a	10133	\| mlc_int2.int2_mlc5
cparata	1:fe40aec6e97a	10134	\| mlc_int2.int2_mlc6
cparata	1:fe40aec6e97a	10135	\| mlc_int2.int2_mlc7
cparata	1:fe40aec6e97a	10136	\| mlc_int2.int2_mlc8)!= PROPERTY_DISABLE ){
cparata	1:fe40aec6e97a	10137	md2_cfg.int2_emb_func = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	10138	}
cparata	1:fe40aec6e97a	10139	else{
cparata	1:fe40aec6e97a	10140	md2_cfg.int2_emb_func = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10141	}
cparata	1:fe40aec6e97a	10142	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL,
cparata	1:fe40aec6e97a	10143	(uint8_t*)&int2_ctrl, 1);
cparata	1:fe40aec6e97a	10144	}
cparata	1:fe40aec6e97a	10145	if (ret == 0) {
cparata	1:fe40aec6e97a	10146	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	1:fe40aec6e97a	10147	}
cparata	1:fe40aec6e97a	10148	if (ret == 0) {
cparata	1:fe40aec6e97a	10149	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	1:fe40aec6e97a	10150	}
cparata	1:fe40aec6e97a	10151
cparata	1:fe40aec6e97a	10152	if (ret == 0) {
cparata	1:fe40aec6e97a	10153	ret = lsm6dsox_pin_int1_route_get(ctx, &pin_int1_route);
cparata	1:fe40aec6e97a	10154	}
cparata	1:fe40aec6e97a	10155
cparata	1:fe40aec6e97a	10156	if (ret == 0) {
cparata	1:fe40aec6e97a	10157	if ( ( val.fifo_bdr
cparata	1:fe40aec6e97a	10158	\| val.drdy_g
cparata	1:fe40aec6e97a	10159	\| val.drdy_temp
cparata	1:fe40aec6e97a	10160	\| val.drdy_xl
cparata	1:fe40aec6e97a	10161	\| val.fifo_full
cparata	1:fe40aec6e97a	10162	\| val.fifo_ovr
cparata	1:fe40aec6e97a	10163	\| val.fifo_th
cparata	1:fe40aec6e97a	10164	\| val.six_d
cparata	1:fe40aec6e97a	10165	\| val.double_tap
cparata	1:fe40aec6e97a	10166	\| val.free_fall
cparata	1:fe40aec6e97a	10167	\| val.wake_up
cparata	1:fe40aec6e97a	10168	\| val.single_tap
cparata	1:fe40aec6e97a	10169	\| val.sleep_change
cparata	1:fe40aec6e97a	10170	\| pin_int1_route.den_flag
cparata	1:fe40aec6e97a	10171	\| pin_int1_route.boot
cparata	1:fe40aec6e97a	10172	\| pin_int1_route.fifo_bdr
cparata	1:fe40aec6e97a	10173	\| pin_int1_route.drdy_g
cparata	1:fe40aec6e97a	10174	\| pin_int1_route.drdy_xl
cparata	1:fe40aec6e97a	10175	\| pin_int1_route.fifo_full
cparata	1:fe40aec6e97a	10176	\| pin_int1_route.fifo_ovr
cparata	1:fe40aec6e97a	10177	\| pin_int1_route.fifo_th
cparata	1:fe40aec6e97a	10178	\| pin_int1_route.six_d
cparata	1:fe40aec6e97a	10179	\| pin_int1_route.double_tap
cparata	1:fe40aec6e97a	10180	\| pin_int1_route.free_fall
cparata	1:fe40aec6e97a	10181	\| pin_int1_route.wake_up
cparata	1:fe40aec6e97a	10182	\| pin_int1_route.single_tap
cparata	1:fe40aec6e97a	10183	\| pin_int1_route.sleep_change ) != PROPERTY_DISABLE) {
cparata	1:fe40aec6e97a	10184	tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	10185	}
cparata	1:fe40aec6e97a	10186	else{
cparata	1:fe40aec6e97a	10187	tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10188	}
cparata	1:fe40aec6e97a	10189	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	1:fe40aec6e97a	10190	}
cparata	1:fe40aec6e97a	10191	}
cparata	1:fe40aec6e97a	10192	return ret;
cparata	1:fe40aec6e97a	10193	}
cparata	1:fe40aec6e97a	10194
cparata	1:fe40aec6e97a	10195	/**
cparata	1:fe40aec6e97a	10196	* @brief Route interrupt signals on int2 pin.[get]
cparata	1:fe40aec6e97a	10197	*
cparata	1:fe40aec6e97a	10198	* @param ctx communication interface handler. Use NULL to ingnore
cparata	1:fe40aec6e97a	10199	* this interface.(ptr)
cparata	1:fe40aec6e97a	10200	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	1:fe40aec6e97a	10201	* to ingnore this interface.(ptr)
cparata	1:fe40aec6e97a	10202	* @param val the signals that are routed on int2 pin.(ptr)
cparata	1:fe40aec6e97a	10203	*
cparata	1:fe40aec6e97a	10204	*/
cparata	1:fe40aec6e97a	10205	int32_t lsm6dsox_pin_int2_route_get(lsm6dsox_ctx_t ctx, lsm6dsox_ctx_t aux_ctx,
cparata	1:fe40aec6e97a	10206	lsm6dsox_pin_int2_route_t *val)
cparata	1:fe40aec6e97a	10207	{
cparata	1:fe40aec6e97a	10208	lsm6dsox_emb_func_int2_t emb_func_int2;
cparata	1:fe40aec6e97a	10209	lsm6dsox_spi2_int_ois_t spi2_int_ois;
cparata	1:fe40aec6e97a	10210	lsm6dsox_fsm_int2_a_t fsm_int2_a;
cparata	1:fe40aec6e97a	10211	lsm6dsox_fsm_int2_b_t fsm_int2_b;
cparata	1:fe40aec6e97a	10212	lsm6dsox_int2_ctrl_t int2_ctrl;
cparata	1:fe40aec6e97a	10213	lsm6dsox_mlc_int2_t mlc_int2;
cparata	1:fe40aec6e97a	10214	lsm6dsox_md2_cfg_t md2_cfg;
cparata	1:fe40aec6e97a	10215	lsm6dsox_ctrl4_c_t ctrl4_c;
cparata	1:fe40aec6e97a	10216	int32_t ret;
cparata	1:fe40aec6e97a	10217
cparata	1:fe40aec6e97a	10218	ret = 0;
cparata	1:fe40aec6e97a	10219
cparata	1:fe40aec6e97a	10220	if( aux_ctx != NULL ) {
cparata	1:fe40aec6e97a	10221	ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS,
cparata	1:fe40aec6e97a	10222	(uint8_t*)&spi2_int_ois, 1);
cparata	1:fe40aec6e97a	10223	val->drdy_ois = spi2_int_ois.int2_drdy_ois;
cparata	1:fe40aec6e97a	10224	}
cparata	1:fe40aec6e97a	10225
cparata	1:fe40aec6e97a	10226	if( ctx != NULL ) {
cparata	1:fe40aec6e97a	10227	if (ret == 0) {
cparata	1:fe40aec6e97a	10228	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	10229	}
cparata	1:fe40aec6e97a	10230	if (ret == 0) {
cparata	1:fe40aec6e97a	10231	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT2,
cparata	1:fe40aec6e97a	10232	(uint8_t*)&mlc_int2, 1);
cparata	1:fe40aec6e97a	10233	}
cparata	1:fe40aec6e97a	10234	if (ret == 0) {
cparata	1:fe40aec6e97a	10235	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT2,
cparata	1:fe40aec6e97a	10236	(uint8_t*)&emb_func_int2, 1);
cparata	1:fe40aec6e97a	10237	}
cparata	1:fe40aec6e97a	10238	if (ret == 0) {
cparata	1:fe40aec6e97a	10239	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_A,
cparata	1:fe40aec6e97a	10240	(uint8_t*)&fsm_int2_a, 1);
cparata	1:fe40aec6e97a	10241	}
cparata	1:fe40aec6e97a	10242	if (ret == 0) {
cparata	1:fe40aec6e97a	10243	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_B,
cparata	1:fe40aec6e97a	10244	(uint8_t*)&fsm_int2_b, 1);
cparata	1:fe40aec6e97a	10245	}
cparata	1:fe40aec6e97a	10246	if (ret == 0) {
cparata	1:fe40aec6e97a	10247	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	10248	}
cparata	1:fe40aec6e97a	10249	if (ret == 0) {
cparata	1:fe40aec6e97a	10250
cparata	1:fe40aec6e97a	10251	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
cparata	1:fe40aec6e97a	10252	(uint8_t*)&int2_ctrl, 1);
cparata	1:fe40aec6e97a	10253	}
cparata	1:fe40aec6e97a	10254	if (ret == 0) {
cparata	1:fe40aec6e97a	10255	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG,
cparata	1:fe40aec6e97a	10256	(uint8_t*)&md2_cfg, 1);
cparata	1:fe40aec6e97a	10257	}
cparata	1:fe40aec6e97a	10258
cparata	1:fe40aec6e97a	10259	if (ret == 0) {
cparata	1:fe40aec6e97a	10260	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	1:fe40aec6e97a	10261	}
cparata	1:fe40aec6e97a	10262	if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE){
cparata	1:fe40aec6e97a	10263	if (ret == 0) {
cparata	1:fe40aec6e97a	10264	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
cparata	1:fe40aec6e97a	10265	(uint8_t*)&int2_ctrl, 1);
cparata	1:fe40aec6e97a	10266	val->drdy_temp = int2_ctrl.int2_drdy_temp;
cparata	1:fe40aec6e97a	10267	}
cparata	1:fe40aec6e97a	10268	if (ret == 0) {
cparata	1:fe40aec6e97a	10269	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	1:fe40aec6e97a	10270	val->timestamp = md2_cfg.int2_timestamp;
cparata	1:fe40aec6e97a	10271	}
cparata	1:fe40aec6e97a	10272	}
cparata	1:fe40aec6e97a	10273	else {
cparata	1:fe40aec6e97a	10274	val->drdy_temp = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10275	val->timestamp = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10276	}
cparata	1:fe40aec6e97a	10277
cparata	1:fe40aec6e97a	10278	val->drdy_xl = int2_ctrl.int2_drdy_xl;
cparata	1:fe40aec6e97a	10279	val->drdy_g = int2_ctrl.int2_drdy_g;
cparata	1:fe40aec6e97a	10280	val->drdy_temp = int2_ctrl.int2_drdy_temp;
cparata	1:fe40aec6e97a	10281	val->fifo_th = int2_ctrl.int2_fifo_th;
cparata	1:fe40aec6e97a	10282	val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
cparata	1:fe40aec6e97a	10283	val->fifo_full = int2_ctrl.int2_fifo_full;
cparata	1:fe40aec6e97a	10284	val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
cparata	1:fe40aec6e97a	10285
cparata	1:fe40aec6e97a	10286	val->timestamp = md2_cfg.int2_timestamp;
cparata	1:fe40aec6e97a	10287	val->six_d = md2_cfg.int2_6d;
cparata	1:fe40aec6e97a	10288	val->double_tap = md2_cfg.int2_double_tap;
cparata	1:fe40aec6e97a	10289	val->free_fall = md2_cfg.int2_ff;
cparata	1:fe40aec6e97a	10290	val->wake_up = md2_cfg.int2_wu;
cparata	1:fe40aec6e97a	10291	val->single_tap = md2_cfg.int2_single_tap;
cparata	1:fe40aec6e97a	10292	val->sleep_change = md2_cfg.int2_sleep_change;
cparata	1:fe40aec6e97a	10293
cparata	1:fe40aec6e97a	10294	val->step_detector = emb_func_int2. int2_step_detector;
cparata	1:fe40aec6e97a	10295	val->tilt = emb_func_int2.int2_tilt;
cparata	1:fe40aec6e97a	10296	val->fsm_lc = emb_func_int2.int2_fsm_lc;
cparata	1:fe40aec6e97a	10297
cparata	1:fe40aec6e97a	10298	val->fsm1 = fsm_int2_a.int2_fsm1;
cparata	1:fe40aec6e97a	10299	val->fsm2 = fsm_int2_a.int2_fsm2;
cparata	1:fe40aec6e97a	10300	val->fsm3 = fsm_int2_a.int2_fsm3;
cparata	1:fe40aec6e97a	10301	val->fsm4 = fsm_int2_a.int2_fsm4;
cparata	1:fe40aec6e97a	10302	val->fsm5 = fsm_int2_a.int2_fsm5;
cparata	1:fe40aec6e97a	10303	val->fsm6 = fsm_int2_a.int2_fsm6;
cparata	1:fe40aec6e97a	10304	val->fsm7 = fsm_int2_a.int2_fsm7;
cparata	1:fe40aec6e97a	10305	val->fsm8 = fsm_int2_a.int2_fsm8;
cparata	1:fe40aec6e97a	10306
cparata	1:fe40aec6e97a	10307	val->fsm9 = fsm_int2_b.int2_fsm9;
cparata	1:fe40aec6e97a	10308	val->fsm10 = fsm_int2_b.int2_fsm10;
cparata	1:fe40aec6e97a	10309	val->fsm11 = fsm_int2_b.int2_fsm11;
cparata	1:fe40aec6e97a	10310	val->fsm12 = fsm_int2_b.int2_fsm12;
cparata	1:fe40aec6e97a	10311	val->fsm13 = fsm_int2_b.int2_fsm13;
cparata	1:fe40aec6e97a	10312	val->fsm14 = fsm_int2_b.int2_fsm14;
cparata	1:fe40aec6e97a	10313	val->fsm15 = fsm_int2_b.int2_fsm15;
cparata	1:fe40aec6e97a	10314	val->fsm16 = fsm_int2_b.int2_fsm16;
cparata	1:fe40aec6e97a	10315
cparata	1:fe40aec6e97a	10316	val->mlc1 = mlc_int2.int2_mlc1;
cparata	1:fe40aec6e97a	10317	val->mlc2 = mlc_int2.int2_mlc2;
cparata	1:fe40aec6e97a	10318	val->mlc3 = mlc_int2.int2_mlc3;
cparata	1:fe40aec6e97a	10319	val->mlc4 = mlc_int2.int2_mlc4;
cparata	1:fe40aec6e97a	10320	val->mlc5 = mlc_int2.int2_mlc5;
cparata	1:fe40aec6e97a	10321	val->mlc6 = mlc_int2.int2_mlc6;
cparata	1:fe40aec6e97a	10322	val->mlc7 = mlc_int2.int2_mlc7;
cparata	1:fe40aec6e97a	10323	val->mlc8 = mlc_int2.int2_mlc8;
cparata	1:fe40aec6e97a	10324	}
cparata	1:fe40aec6e97a	10325
cparata	1:fe40aec6e97a	10326	return ret;
cparata	1:fe40aec6e97a	10327	}
cparata	1:fe40aec6e97a	10328
cparata	1:fe40aec6e97a	10329	/**
cparata	1:fe40aec6e97a	10330	* @brief Get the status of all the interrupt sources.[get]
cparata	1:fe40aec6e97a	10331	*
cparata	1:fe40aec6e97a	10332	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	10333	* @param val the status of all the interrupt sources.(ptr)
cparata	1:fe40aec6e97a	10334	*
cparata	1:fe40aec6e97a	10335	*/
cparata	1:fe40aec6e97a	10336	int32_t lsm6dsox_all_sources_get(lsm6dsox_ctx_t *ctx,
cparata	1:fe40aec6e97a	10337	lsm6dsox_all_sources_t *val)
cparata	1:fe40aec6e97a	10338	{
cparata	1:fe40aec6e97a	10339	lsm6dsox_emb_func_status_mainpage_t emb_func_status_mainpage;
cparata	1:fe40aec6e97a	10340	lsm6dsox_status_master_mainpage_t status_master_mainpage;
cparata	1:fe40aec6e97a	10341	lsm6dsox_fsm_status_a_mainpage_t fsm_status_a_mainpage;
cparata	1:fe40aec6e97a	10342	lsm6dsox_fsm_status_b_mainpage_t fsm_status_b_mainpage;
cparata	1:fe40aec6e97a	10343	lsm6dsox_mlc_status_mainpage_t mlc_status_mainpage;
cparata	1:fe40aec6e97a	10344	lsm6dsox_fifo_status1_t fifo_status1;
cparata	1:fe40aec6e97a	10345	lsm6dsox_fifo_status2_t fifo_status2;
cparata	1:fe40aec6e97a	10346	lsm6dsox_all_int_src_t all_int_src;
cparata	1:fe40aec6e97a	10347	lsm6dsox_wake_up_src_t wake_up_src;
cparata	1:fe40aec6e97a	10348	lsm6dsox_status_reg_t status_reg;
cparata	1:fe40aec6e97a	10349	lsm6dsox_tap_src_t tap_src;
cparata	1:fe40aec6e97a	10350	lsm6dsox_d6d_src_t d6d_src;
cparata	1:fe40aec6e97a	10351	lsm6dsox_ctrl5_c_t ctrl5_c;
cparata	1:fe40aec6e97a	10352	uint8_t reg[12];
cparata	1:fe40aec6e97a	10353	int32_t ret;
cparata	1:fe40aec6e97a	10354
cparata	1:fe40aec6e97a	10355	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
cparata	1:fe40aec6e97a	10356	if (ret == 0) {
cparata	1:fe40aec6e97a	10357	ctrl5_c.rounding_status = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	10358	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
cparata	1:fe40aec6e97a	10359	}
cparata	1:fe40aec6e97a	10360	if (ret == 0) {
cparata	1:fe40aec6e97a	10361	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_ALL_INT_SRC, reg, 12);
cparata	1:fe40aec6e97a	10362	}
cparata	1:fe40aec6e97a	10363
cparata	1:fe40aec6e97a	10364	if (ret == 0) {
cparata	1:fe40aec6e97a	10365	bytecpy(( uint8_t*)&all_int_src, &reg[0]);
cparata	1:fe40aec6e97a	10366	bytecpy(( uint8_t*)&wake_up_src, &reg[1]);
cparata	1:fe40aec6e97a	10367	bytecpy(( uint8_t*)&tap_src, &reg[2]);
cparata	1:fe40aec6e97a	10368	bytecpy(( uint8_t*)&d6d_src, &reg[3]);
cparata	1:fe40aec6e97a	10369	bytecpy(( uint8_t*)&status_reg, &reg[4]);
cparata	1:fe40aec6e97a	10370	bytecpy(( uint8_t*)&emb_func_status_mainpage, &reg[5]);
cparata	1:fe40aec6e97a	10371	bytecpy(( uint8_t*)&fsm_status_a_mainpage, &reg[6]);
cparata	1:fe40aec6e97a	10372	bytecpy(( uint8_t*)&fsm_status_b_mainpage, &reg[7]);
cparata	1:fe40aec6e97a	10373	bytecpy(( uint8_t*)&mlc_status_mainpage, &reg[8]);
cparata	1:fe40aec6e97a	10374	bytecpy(( uint8_t*)&status_master_mainpage, &reg[9]);
cparata	1:fe40aec6e97a	10375	bytecpy(( uint8_t*)&fifo_status1, &reg[10]);
cparata	1:fe40aec6e97a	10376	bytecpy(( uint8_t*)&fifo_status2, &reg[11]);
cparata	1:fe40aec6e97a	10377
cparata	1:fe40aec6e97a	10378	val->timestamp = all_int_src.timestamp_endcount;
cparata	1:fe40aec6e97a	10379
cparata	1:fe40aec6e97a	10380	val->wake_up_z = wake_up_src.z_wu;
cparata	1:fe40aec6e97a	10381	val->wake_up_y = wake_up_src.y_wu;
cparata	1:fe40aec6e97a	10382	val->wake_up_x = wake_up_src.x_wu;
cparata	1:fe40aec6e97a	10383	val->wake_up = wake_up_src.wu_ia;
cparata	1:fe40aec6e97a	10384	val->sleep_state = wake_up_src.sleep_state;
cparata	1:fe40aec6e97a	10385	val->free_fall = wake_up_src.ff_ia;
cparata	1:fe40aec6e97a	10386	val->sleep_change = wake_up_src.sleep_change_ia;
cparata	1:fe40aec6e97a	10387
cparata	1:fe40aec6e97a	10388	val->tap_x = tap_src.x_tap;
cparata	1:fe40aec6e97a	10389	val->tap_y = tap_src.y_tap;
cparata	1:fe40aec6e97a	10390	val->tap_z = tap_src.z_tap;
cparata	1:fe40aec6e97a	10391	val->tap_sign = tap_src.tap_sign;
cparata	1:fe40aec6e97a	10392	val->double_tap = tap_src.double_tap;
cparata	1:fe40aec6e97a	10393	val->single_tap = tap_src.single_tap;
cparata	1:fe40aec6e97a	10394
cparata	1:fe40aec6e97a	10395	val->six_d_xl = d6d_src.xl;
cparata	1:fe40aec6e97a	10396	val->six_d_xh = d6d_src.xh;
cparata	1:fe40aec6e97a	10397	val->six_d_yl = d6d_src.yl;
cparata	1:fe40aec6e97a	10398	val->six_d_yh = d6d_src.yh;
cparata	1:fe40aec6e97a	10399	val->six_d_zl = d6d_src.zl;
cparata	1:fe40aec6e97a	10400	val->six_d_zh = d6d_src.zh;
cparata	1:fe40aec6e97a	10401	val->six_d = d6d_src.d6d_ia;
cparata	1:fe40aec6e97a	10402	val->den_flag = d6d_src.den_drdy;
cparata	1:fe40aec6e97a	10403
cparata	1:fe40aec6e97a	10404	val->drdy_xl = status_reg.xlda;
cparata	1:fe40aec6e97a	10405	val->drdy_g = status_reg.gda;
cparata	1:fe40aec6e97a	10406	val->drdy_temp = status_reg.tda;
cparata	1:fe40aec6e97a	10407
cparata	1:fe40aec6e97a	10408	val->step_detector = emb_func_status_mainpage.is_step_det;
cparata	1:fe40aec6e97a	10409	val->tilt = emb_func_status_mainpage.is_tilt;
cparata	1:fe40aec6e97a	10410	val->sig_mot = emb_func_status_mainpage.is_sigmot;
cparata	1:fe40aec6e97a	10411	val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
cparata	1:fe40aec6e97a	10412
cparata	1:fe40aec6e97a	10413	val->fsm1 = fsm_status_a_mainpage.is_fsm1;
cparata	1:fe40aec6e97a	10414	val->fsm2 = fsm_status_a_mainpage.is_fsm2;
cparata	1:fe40aec6e97a	10415	val->fsm3 = fsm_status_a_mainpage.is_fsm3;
cparata	1:fe40aec6e97a	10416	val->fsm4 = fsm_status_a_mainpage.is_fsm4;
cparata	1:fe40aec6e97a	10417	val->fsm5 = fsm_status_a_mainpage.is_fsm5;
cparata	1:fe40aec6e97a	10418	val->fsm6 = fsm_status_a_mainpage.is_fsm6;
cparata	1:fe40aec6e97a	10419	val->fsm7 = fsm_status_a_mainpage.is_fsm7;
cparata	1:fe40aec6e97a	10420	val->fsm8 = fsm_status_a_mainpage.is_fsm8;
cparata	1:fe40aec6e97a	10421
cparata	1:fe40aec6e97a	10422	val->fsm9 = fsm_status_b_mainpage.is_fsm9;
cparata	1:fe40aec6e97a	10423	val->fsm10 = fsm_status_b_mainpage.is_fsm10;
cparata	1:fe40aec6e97a	10424	val->fsm11 = fsm_status_b_mainpage.is_fsm11;
cparata	1:fe40aec6e97a	10425	val->fsm12 = fsm_status_b_mainpage.is_fsm12;
cparata	1:fe40aec6e97a	10426	val->fsm13 = fsm_status_b_mainpage.is_fsm13;
cparata	1:fe40aec6e97a	10427	val->fsm14 = fsm_status_b_mainpage.is_fsm14;
cparata	1:fe40aec6e97a	10428	val->fsm15 = fsm_status_b_mainpage.is_fsm15;
cparata	1:fe40aec6e97a	10429	val->fsm16 = fsm_status_b_mainpage.is_fsm16;
cparata	1:fe40aec6e97a	10430
cparata	1:fe40aec6e97a	10431	val->mlc1 = mlc_status_mainpage.is_mlc1;
cparata	1:fe40aec6e97a	10432	val->mlc2 = mlc_status_mainpage.is_mlc2;
cparata	1:fe40aec6e97a	10433	val->mlc3 = mlc_status_mainpage.is_mlc3;
cparata	1:fe40aec6e97a	10434	val->mlc4 = mlc_status_mainpage.is_mlc4;
cparata	1:fe40aec6e97a	10435	val->mlc5 = mlc_status_mainpage.is_mlc5;
cparata	1:fe40aec6e97a	10436	val->mlc6 = mlc_status_mainpage.is_mlc6;
cparata	1:fe40aec6e97a	10437	val->mlc7 = mlc_status_mainpage.is_mlc7;
cparata	1:fe40aec6e97a	10438	val->mlc8 = mlc_status_mainpage.is_mlc8;
cparata	1:fe40aec6e97a	10439
cparata	1:fe40aec6e97a	10440	val->sh_endop = status_master_mainpage.sens_hub_endop;
cparata	1:fe40aec6e97a	10441	val->sh_slave0_nack = status_master_mainpage.slave0_nack;
cparata	1:fe40aec6e97a	10442	val->sh_slave1_nack = status_master_mainpage.slave1_nack;
cparata	1:fe40aec6e97a	10443	val->sh_slave2_nack = status_master_mainpage.slave2_nack;
cparata	1:fe40aec6e97a	10444	val->sh_slave3_nack = status_master_mainpage.slave3_nack;
cparata	1:fe40aec6e97a	10445	val->sh_wr_once = status_master_mainpage.wr_once_done;
cparata	1:fe40aec6e97a	10446
cparata	1:fe40aec6e97a	10447	val->fifo_diff = (256U * fifo_status2.diff_fifo) + fifo_status1.diff_fifo;
cparata	1:fe40aec6e97a	10448
cparata	1:fe40aec6e97a	10449	val->fifo_ovr_latched = fifo_status2.over_run_latched;
cparata	1:fe40aec6e97a	10450	val->fifo_bdr = fifo_status2.counter_bdr_ia;
cparata	1:fe40aec6e97a	10451	val->fifo_full = fifo_status2.fifo_full_ia;
cparata	1:fe40aec6e97a	10452	val->fifo_ovr = fifo_status2.fifo_ovr_ia;
cparata	1:fe40aec6e97a	10453	val->fifo_th = fifo_status2.fifo_wtm_ia;
cparata	1:fe40aec6e97a	10454
cparata	1:fe40aec6e97a	10455	ctrl5_c.rounding_status = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10456	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
cparata	1:fe40aec6e97a	10457
cparata	1:fe40aec6e97a	10458	}
cparata	1:fe40aec6e97a	10459
cparata	1:fe40aec6e97a	10460	return ret;
cparata	1:fe40aec6e97a	10461	}
cparata	1:fe40aec6e97a	10462
cparata	1:fe40aec6e97a	10463	/**
cparata	1:fe40aec6e97a	10464	* @brief Sensor conversion parameters selection.[set]
cparata	1:fe40aec6e97a	10465	*
cparata	1:fe40aec6e97a	10466	* @param ctx communication interface handler. Use NULL to ingnore
cparata	1:fe40aec6e97a	10467	* this interface.(ptr)
cparata	1:fe40aec6e97a	10468	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	1:fe40aec6e97a	10469	* to ingnore this interface.(ptr)
cparata	1:fe40aec6e97a	10470	* @param val set the sensor conversion parameters by checking
cparata	1:fe40aec6e97a	10471	* the constraints of the device.(ptr)
cparata	1:fe40aec6e97a	10472	*
cparata	1:fe40aec6e97a	10473	*/
cparata	1:fe40aec6e97a	10474	int32_t lsm6dsox_mode_set(lsm6dsox_ctx_t ctx, lsm6dsox_ctx_t aux_ctx,
cparata	1:fe40aec6e97a	10475	lsm6dsox_md_t *val)
cparata	1:fe40aec6e97a	10476	{
cparata	1:fe40aec6e97a	10477	lsm6dsox_func_cfg_access_t func_cfg_access;
cparata	1:fe40aec6e97a	10478	lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois;
cparata	1:fe40aec6e97a	10479	lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois;
cparata	1:fe40aec6e97a	10480	lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois;
cparata	1:fe40aec6e97a	10481	lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois;
cparata	1:fe40aec6e97a	10482	lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois;
cparata	1:fe40aec6e97a	10483	lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois;
cparata	1:fe40aec6e97a	10484	lsm6dsox_ctrl1_xl_t ctrl1_xl;
cparata	1:fe40aec6e97a	10485	lsm6dsox_ctrl8_xl_t ctrl8_xl;
cparata	1:fe40aec6e97a	10486	lsm6dsox_ctrl2_g_t ctrl2_g;
cparata	1:fe40aec6e97a	10487	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	10488	lsm6dsox_ctrl4_c_t ctrl4_c;
cparata	1:fe40aec6e97a	10489	lsm6dsox_ctrl5_c_t ctrl5_c;
cparata	1:fe40aec6e97a	10490	lsm6dsox_ctrl6_c_t ctrl6_c;
cparata	1:fe40aec6e97a	10491	lsm6dsox_ctrl7_g_t ctrl7_g;
cparata	1:fe40aec6e97a	10492	uint8_t xl_hm_mode;
cparata	1:fe40aec6e97a	10493	uint8_t g_hm_mode;
cparata	1:fe40aec6e97a	10494	uint8_t xl_ulp_en;
cparata	1:fe40aec6e97a	10495	uint8_t odr_gy;
cparata	1:fe40aec6e97a	10496	uint8_t odr_xl;
cparata	1:fe40aec6e97a	10497	uint8_t reg[8];
cparata	1:fe40aec6e97a	10498	int32_t ret;
cparata	1:fe40aec6e97a	10499
cparata	1:fe40aec6e97a	10500	ret = 0;
cparata	1:fe40aec6e97a	10501
cparata	1:fe40aec6e97a	10502	/* reading input configuration */
cparata	1:fe40aec6e97a	10503	xl_hm_mode = ( (uint8_t)val->ui.xl.odr & 0x10U ) >> 4;
cparata	1:fe40aec6e97a	10504	xl_ulp_en = ( (uint8_t)val->ui.xl.odr & 0x20U ) >> 5;
cparata	1:fe40aec6e97a	10505	odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
cparata	1:fe40aec6e97a	10506
cparata	1:fe40aec6e97a	10507	/* if enable xl ultra low power mode disable gy and OIS chain */
cparata	1:fe40aec6e97a	10508	if (xl_ulp_en == PROPERTY_ENABLE) {
cparata	1:fe40aec6e97a	10509	val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
cparata	1:fe40aec6e97a	10510	val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
cparata	1:fe40aec6e97a	10511	val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
cparata	1:fe40aec6e97a	10512	}
cparata	1:fe40aec6e97a	10513	/* if OIS xl is enabled also gyro OIS is enabled */
cparata	1:fe40aec6e97a	10514	if (val->ois.xl.odr == LSM6DSOX_XL_OIS_6667Hz_HP){
cparata	1:fe40aec6e97a	10515	val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
cparata	1:fe40aec6e97a	10516	}
cparata	1:fe40aec6e97a	10517	g_hm_mode = ( (uint8_t)val->ui.gy.odr & 0x10U ) >> 4;
cparata	1:fe40aec6e97a	10518	odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
cparata	1:fe40aec6e97a	10519
cparata	1:fe40aec6e97a	10520	/* reading registers to be configured */
cparata	1:fe40aec6e97a	10521	if( ctx != NULL ) {
cparata	1:fe40aec6e97a	10522	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, reg, 8);
cparata	1:fe40aec6e97a	10523	bytecpy(( uint8_t*)&ctrl1_xl, &reg[0]);
cparata	1:fe40aec6e97a	10524	bytecpy(( uint8_t*)&ctrl2_g, &reg[1]);
cparata	1:fe40aec6e97a	10525	bytecpy(( uint8_t*)&ctrl3_c, &reg[2]);
cparata	1:fe40aec6e97a	10526	bytecpy(( uint8_t*)&ctrl4_c, &reg[3]);
cparata	1:fe40aec6e97a	10527	bytecpy(( uint8_t*)&ctrl5_c, &reg[4]);
cparata	1:fe40aec6e97a	10528	bytecpy(( uint8_t*)&ctrl6_c, &reg[5]);
cparata	1:fe40aec6e97a	10529	bytecpy(( uint8_t*)&ctrl7_g, &reg[6]);
cparata	1:fe40aec6e97a	10530	bytecpy(( uint8_t*)&ctrl8_xl, &reg[7]);
cparata	1:fe40aec6e97a	10531	if ( ret == 0 ) {
cparata	1:fe40aec6e97a	10532	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
cparata	1:fe40aec6e97a	10533	(uint8_t*)&func_cfg_access, 1);
cparata	1:fe40aec6e97a	10534	}
cparata	1:fe40aec6e97a	10535	/* if toggle xl ultra low power mode, turn off xl before reconfigure */
cparata	1:fe40aec6e97a	10536	if (ctrl5_c.xl_ulp_en != xl_ulp_en) {
cparata	1:fe40aec6e97a	10537	ctrl1_xl.odr_xl = (uint8_t) 0x00U;
cparata	1:fe40aec6e97a	10538	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL,
cparata	1:fe40aec6e97a	10539	(uint8_t*)&ctrl1_xl, 1);
cparata	1:fe40aec6e97a	10540	}
cparata	1:fe40aec6e97a	10541	}
cparata	1:fe40aec6e97a	10542
cparata	1:fe40aec6e97a	10543	/* reading OIS registers to be configured */
cparata	1:fe40aec6e97a	10544	if( aux_ctx != NULL ) {
cparata	1:fe40aec6e97a	10545	if (ret == 0) {
cparata	1:fe40aec6e97a	10546	ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3);
cparata	1:fe40aec6e97a	10547	}
cparata	1:fe40aec6e97a	10548	bytecpy(( uint8_t*)&spi2_ctrl1_ois, &reg[0]);
cparata	1:fe40aec6e97a	10549	bytecpy(( uint8_t*)&spi2_ctrl2_ois, &reg[1]);
cparata	1:fe40aec6e97a	10550	bytecpy(( uint8_t*)&spi2_ctrl3_ois, &reg[2]);
cparata	1:fe40aec6e97a	10551	}
cparata	1:fe40aec6e97a	10552	else {
cparata	1:fe40aec6e97a	10553	if( ctx != NULL ) {
cparata	1:fe40aec6e97a	10554	if (ret == 0) {
cparata	1:fe40aec6e97a	10555	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3);
cparata	1:fe40aec6e97a	10556	}
cparata	1:fe40aec6e97a	10557	bytecpy(( uint8_t*)&ui_ctrl1_ois, &reg[0]);
cparata	1:fe40aec6e97a	10558	bytecpy(( uint8_t*)&ui_ctrl2_ois, &reg[1]);
cparata	1:fe40aec6e97a	10559	bytecpy(( uint8_t*)&ui_ctrl3_ois, &reg[2]);
cparata	1:fe40aec6e97a	10560	}
cparata	1:fe40aec6e97a	10561	}
cparata	1:fe40aec6e97a	10562
cparata	1:fe40aec6e97a	10563	/* Check the Finite State Machine data rate constraints */
cparata	1:fe40aec6e97a	10564	if (val->fsm.sens != LSM6DSOX_FSM_DISABLE) {
cparata	1:fe40aec6e97a	10565	switch (val->fsm.odr) {
cparata	1:fe40aec6e97a	10566	case LSM6DSOX_FSM_12Hz5:
cparata	1:fe40aec6e97a	10567	if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl == 0x00U) ) {
cparata	1:fe40aec6e97a	10568	odr_xl = 0x01U;
cparata	1:fe40aec6e97a	10569	}
cparata	1:fe40aec6e97a	10570	if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy == 0x00U) ) {
cparata	1:fe40aec6e97a	10571	xl_ulp_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10572	odr_gy = 0x01U;
cparata	1:fe40aec6e97a	10573	}
cparata	1:fe40aec6e97a	10574	break;
cparata	1:fe40aec6e97a	10575	case LSM6DSOX_FSM_26Hz:
cparata	1:fe40aec6e97a	10576	if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x02U) ) {
cparata	1:fe40aec6e97a	10577	odr_xl = 0x02U;
cparata	1:fe40aec6e97a	10578	}
cparata	1:fe40aec6e97a	10579	if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x02U) ) {
cparata	1:fe40aec6e97a	10580	xl_ulp_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10581	odr_gy = 0x02U;
cparata	1:fe40aec6e97a	10582	}
cparata	1:fe40aec6e97a	10583	break;
cparata	1:fe40aec6e97a	10584	case LSM6DSOX_FSM_52Hz:
cparata	1:fe40aec6e97a	10585	if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x03U) ) {
cparata	1:fe40aec6e97a	10586	odr_xl = 0x03U;
cparata	1:fe40aec6e97a	10587	}
cparata	1:fe40aec6e97a	10588	if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x03U) ) {
cparata	1:fe40aec6e97a	10589	xl_ulp_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10590	odr_gy = 0x03U;
cparata	1:fe40aec6e97a	10591	}
cparata	1:fe40aec6e97a	10592	break;
cparata	1:fe40aec6e97a	10593	case LSM6DSOX_FSM_104Hz:
cparata	1:fe40aec6e97a	10594	if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x04U) ) {
cparata	1:fe40aec6e97a	10595	odr_xl = 0x04U;
cparata	1:fe40aec6e97a	10596	}
cparata	1:fe40aec6e97a	10597	if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x04U) ) {
cparata	1:fe40aec6e97a	10598	xl_ulp_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10599	odr_gy = 0x04U;
cparata	1:fe40aec6e97a	10600	}
cparata	1:fe40aec6e97a	10601	break;
cparata	1:fe40aec6e97a	10602	default:
cparata	1:fe40aec6e97a	10603	odr_xl = 0x00U;
cparata	1:fe40aec6e97a	10604	odr_gy = 0x00U;
cparata	1:fe40aec6e97a	10605	break;
cparata	1:fe40aec6e97a	10606	}
cparata	1:fe40aec6e97a	10607	}
cparata	1:fe40aec6e97a	10608
cparata	1:fe40aec6e97a	10609	/* Check the Machine Learning Core data rate constraints */
cparata	1:fe40aec6e97a	10610	if (val->mlc.sens != LSM6DSOX_MLC_DISABLE) {
cparata	1:fe40aec6e97a	10611	switch (val->mlc.odr) {
cparata	1:fe40aec6e97a	10612	case LSM6DSOX_MLC_12Hz5:
cparata	1:fe40aec6e97a	10613	if (odr_xl == 0x00U) {
cparata	1:fe40aec6e97a	10614	odr_xl = 0x01U;
cparata	1:fe40aec6e97a	10615	}
cparata	1:fe40aec6e97a	10616	if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy == 0x00U) ) {
cparata	1:fe40aec6e97a	10617	xl_ulp_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10618	odr_gy = 0x01U;
cparata	1:fe40aec6e97a	10619	}
cparata	1:fe40aec6e97a	10620	break;
cparata	1:fe40aec6e97a	10621	case LSM6DSOX_MLC_26Hz:
cparata	1:fe40aec6e97a	10622	if (odr_xl < 0x02U) {
cparata	1:fe40aec6e97a	10623	odr_xl = 0x02U;
cparata	1:fe40aec6e97a	10624	}
cparata	1:fe40aec6e97a	10625	if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x02U) ) {
cparata	1:fe40aec6e97a	10626	xl_ulp_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10627	odr_gy = 0x02U;
cparata	1:fe40aec6e97a	10628	}
cparata	1:fe40aec6e97a	10629	break;
cparata	1:fe40aec6e97a	10630	case LSM6DSOX_MLC_52Hz:
cparata	1:fe40aec6e97a	10631	if (odr_xl < 0x03U) {
cparata	1:fe40aec6e97a	10632	odr_xl = 0x03U;
cparata	1:fe40aec6e97a	10633	}
cparata	1:fe40aec6e97a	10634	if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x03U) ) {
cparata	1:fe40aec6e97a	10635	xl_ulp_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10636	odr_gy = 0x03U;
cparata	1:fe40aec6e97a	10637	}
cparata	1:fe40aec6e97a	10638	break;
cparata	1:fe40aec6e97a	10639	case LSM6DSOX_MLC_104Hz:
cparata	1:fe40aec6e97a	10640	if (odr_xl < 0x04U) {
cparata	1:fe40aec6e97a	10641	odr_xl = 0x04U;
cparata	1:fe40aec6e97a	10642	}
cparata	1:fe40aec6e97a	10643	if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x04U) ) {
cparata	1:fe40aec6e97a	10644	xl_ulp_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10645	odr_gy = 0x04U;
cparata	1:fe40aec6e97a	10646	}
cparata	1:fe40aec6e97a	10647	break;
cparata	1:fe40aec6e97a	10648	default:
cparata	1:fe40aec6e97a	10649	odr_xl = 0x00U;
cparata	1:fe40aec6e97a	10650	odr_gy = 0x00U;
cparata	1:fe40aec6e97a	10651	break;
cparata	1:fe40aec6e97a	10652	}
cparata	1:fe40aec6e97a	10653	}
cparata	1:fe40aec6e97a	10654
cparata	1:fe40aec6e97a	10655	/* Updating the accelerometer data rate configuration */
cparata	1:fe40aec6e97a	10656	switch ( ( ctrl5_c.xl_ulp_en << 5 ) \| ( ctrl6_c.xl_hm_mode << 4 ) \|
cparata	1:fe40aec6e97a	10657	ctrl1_xl.odr_xl ) {
cparata	1:fe40aec6e97a	10658	case LSM6DSOX_XL_UI_OFF:
cparata	1:fe40aec6e97a	10659	val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
cparata	1:fe40aec6e97a	10660	break;
cparata	1:fe40aec6e97a	10661	case LSM6DSOX_XL_UI_12Hz5_HP:
cparata	1:fe40aec6e97a	10662	val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_HP;
cparata	1:fe40aec6e97a	10663	break;
cparata	1:fe40aec6e97a	10664	case LSM6DSOX_XL_UI_26Hz_HP:
cparata	1:fe40aec6e97a	10665	val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_HP;
cparata	1:fe40aec6e97a	10666	break;
cparata	1:fe40aec6e97a	10667	case LSM6DSOX_XL_UI_52Hz_HP:
cparata	1:fe40aec6e97a	10668	val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_HP;
cparata	1:fe40aec6e97a	10669	break;
cparata	1:fe40aec6e97a	10670	case LSM6DSOX_XL_UI_104Hz_HP:
cparata	1:fe40aec6e97a	10671	val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_HP;
cparata	1:fe40aec6e97a	10672	break;
cparata	1:fe40aec6e97a	10673	case LSM6DSOX_XL_UI_208Hz_HP:
cparata	1:fe40aec6e97a	10674	val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_HP;
cparata	1:fe40aec6e97a	10675	break;
cparata	1:fe40aec6e97a	10676	case LSM6DSOX_XL_UI_416Hz_HP:
cparata	1:fe40aec6e97a	10677	val->ui.xl.odr = LSM6DSOX_XL_UI_416Hz_HP;
cparata	1:fe40aec6e97a	10678	break;
cparata	1:fe40aec6e97a	10679	case LSM6DSOX_XL_UI_833Hz_HP:
cparata	1:fe40aec6e97a	10680	val->ui.xl.odr = LSM6DSOX_XL_UI_833Hz_HP;
cparata	1:fe40aec6e97a	10681	break;
cparata	1:fe40aec6e97a	10682	case LSM6DSOX_XL_UI_1667Hz_HP:
cparata	1:fe40aec6e97a	10683	val->ui.xl.odr = LSM6DSOX_XL_UI_1667Hz_HP;
cparata	1:fe40aec6e97a	10684	break;
cparata	1:fe40aec6e97a	10685	case LSM6DSOX_XL_UI_3333Hz_HP:
cparata	1:fe40aec6e97a	10686	val->ui.xl.odr = LSM6DSOX_XL_UI_3333Hz_HP;
cparata	1:fe40aec6e97a	10687	break;
cparata	1:fe40aec6e97a	10688	case LSM6DSOX_XL_UI_6667Hz_HP:
cparata	1:fe40aec6e97a	10689	val->ui.xl.odr = LSM6DSOX_XL_UI_6667Hz_HP;
cparata	1:fe40aec6e97a	10690	break;
cparata	1:fe40aec6e97a	10691	case LSM6DSOX_XL_UI_1Hz6_LP:
cparata	1:fe40aec6e97a	10692	val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_LP;
cparata	1:fe40aec6e97a	10693	break;
cparata	1:fe40aec6e97a	10694	case LSM6DSOX_XL_UI_12Hz5_LP:
cparata	1:fe40aec6e97a	10695	val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_LP;
cparata	1:fe40aec6e97a	10696	break;
cparata	1:fe40aec6e97a	10697	case LSM6DSOX_XL_UI_26Hz_LP:
cparata	1:fe40aec6e97a	10698	val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_LP;
cparata	1:fe40aec6e97a	10699	break;
cparata	1:fe40aec6e97a	10700	case LSM6DSOX_XL_UI_52Hz_LP:
cparata	1:fe40aec6e97a	10701	val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_LP;
cparata	1:fe40aec6e97a	10702	break;
cparata	1:fe40aec6e97a	10703	case LSM6DSOX_XL_UI_104Hz_NM:
cparata	1:fe40aec6e97a	10704	val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_NM;
cparata	1:fe40aec6e97a	10705	break;
cparata	1:fe40aec6e97a	10706	case LSM6DSOX_XL_UI_208Hz_NM:
cparata	1:fe40aec6e97a	10707	val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_NM;
cparata	1:fe40aec6e97a	10708	break;
cparata	1:fe40aec6e97a	10709	case LSM6DSOX_XL_UI_1Hz6_ULP:
cparata	1:fe40aec6e97a	10710	val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_ULP;
cparata	1:fe40aec6e97a	10711	break;
cparata	1:fe40aec6e97a	10712	case LSM6DSOX_XL_UI_12Hz5_ULP:
cparata	1:fe40aec6e97a	10713	val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_ULP;
cparata	1:fe40aec6e97a	10714	break;
cparata	1:fe40aec6e97a	10715	case LSM6DSOX_XL_UI_26Hz_ULP:
cparata	1:fe40aec6e97a	10716	val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_ULP;
cparata	1:fe40aec6e97a	10717	break;
cparata	1:fe40aec6e97a	10718	case LSM6DSOX_XL_UI_52Hz_ULP:
cparata	1:fe40aec6e97a	10719	val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_ULP;
cparata	1:fe40aec6e97a	10720	break;
cparata	1:fe40aec6e97a	10721	case LSM6DSOX_XL_UI_104Hz_ULP:
cparata	1:fe40aec6e97a	10722	val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_ULP;
cparata	1:fe40aec6e97a	10723	break;
cparata	1:fe40aec6e97a	10724	case LSM6DSOX_XL_UI_208Hz_ULP:
cparata	1:fe40aec6e97a	10725	val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_ULP;
cparata	1:fe40aec6e97a	10726	break;
cparata	1:fe40aec6e97a	10727	default:
cparata	1:fe40aec6e97a	10728	val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
cparata	1:fe40aec6e97a	10729	break;
cparata	1:fe40aec6e97a	10730	}
cparata	1:fe40aec6e97a	10731
cparata	1:fe40aec6e97a	10732	/* Updating the accelerometer data rate configuration */
cparata	1:fe40aec6e97a	10733	switch ( (ctrl7_g.g_hm_mode << 4) \| ctrl2_g.odr_g) {
cparata	1:fe40aec6e97a	10734	case LSM6DSOX_GY_UI_OFF:
cparata	1:fe40aec6e97a	10735	val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
cparata	1:fe40aec6e97a	10736	break;
cparata	1:fe40aec6e97a	10737	case LSM6DSOX_GY_UI_12Hz5_LP:
cparata	1:fe40aec6e97a	10738	val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_LP;
cparata	1:fe40aec6e97a	10739	break;
cparata	1:fe40aec6e97a	10740	case LSM6DSOX_GY_UI_12Hz5_HP:
cparata	1:fe40aec6e97a	10741	val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_HP;
cparata	1:fe40aec6e97a	10742	break;
cparata	1:fe40aec6e97a	10743	case LSM6DSOX_GY_UI_26Hz_LP:
cparata	1:fe40aec6e97a	10744	val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_LP;
cparata	1:fe40aec6e97a	10745	break;
cparata	1:fe40aec6e97a	10746	case LSM6DSOX_GY_UI_26Hz_HP:
cparata	1:fe40aec6e97a	10747	val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_HP;
cparata	1:fe40aec6e97a	10748	break;
cparata	1:fe40aec6e97a	10749	case LSM6DSOX_GY_UI_52Hz_LP:
cparata	1:fe40aec6e97a	10750	val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_LP;
cparata	1:fe40aec6e97a	10751	break;
cparata	1:fe40aec6e97a	10752	case LSM6DSOX_GY_UI_52Hz_HP:
cparata	1:fe40aec6e97a	10753	val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_HP;
cparata	1:fe40aec6e97a	10754	break;
cparata	1:fe40aec6e97a	10755	case LSM6DSOX_GY_UI_104Hz_NM:
cparata	1:fe40aec6e97a	10756	val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_NM;
cparata	1:fe40aec6e97a	10757	break;
cparata	1:fe40aec6e97a	10758	case LSM6DSOX_GY_UI_104Hz_HP:
cparata	1:fe40aec6e97a	10759	val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_HP;
cparata	1:fe40aec6e97a	10760	break;
cparata	1:fe40aec6e97a	10761	case LSM6DSOX_GY_UI_208Hz_NM:
cparata	1:fe40aec6e97a	10762	val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_NM;
cparata	1:fe40aec6e97a	10763	break;
cparata	1:fe40aec6e97a	10764	case LSM6DSOX_GY_UI_208Hz_HP:
cparata	1:fe40aec6e97a	10765	val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_HP;
cparata	1:fe40aec6e97a	10766	break;
cparata	1:fe40aec6e97a	10767	case LSM6DSOX_GY_UI_416Hz_HP:
cparata	1:fe40aec6e97a	10768	val->ui.gy.odr = LSM6DSOX_GY_UI_416Hz_HP;
cparata	1:fe40aec6e97a	10769	break;
cparata	1:fe40aec6e97a	10770	case LSM6DSOX_GY_UI_833Hz_HP:
cparata	1:fe40aec6e97a	10771	val->ui.gy.odr = LSM6DSOX_GY_UI_833Hz_HP;
cparata	1:fe40aec6e97a	10772	break;
cparata	1:fe40aec6e97a	10773	case LSM6DSOX_GY_UI_1667Hz_HP:
cparata	1:fe40aec6e97a	10774	val->ui.gy.odr = LSM6DSOX_GY_UI_1667Hz_HP;
cparata	1:fe40aec6e97a	10775	break;
cparata	1:fe40aec6e97a	10776	case LSM6DSOX_GY_UI_3333Hz_HP:
cparata	1:fe40aec6e97a	10777	val->ui.gy.odr = LSM6DSOX_GY_UI_3333Hz_HP;
cparata	1:fe40aec6e97a	10778	break;
cparata	1:fe40aec6e97a	10779	case LSM6DSOX_GY_UI_6667Hz_HP:
cparata	1:fe40aec6e97a	10780	val->ui.gy.odr = LSM6DSOX_GY_UI_6667Hz_HP;
cparata	1:fe40aec6e97a	10781	break;
cparata	1:fe40aec6e97a	10782	default:
cparata	1:fe40aec6e97a	10783	val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
cparata	1:fe40aec6e97a	10784	break;
cparata	1:fe40aec6e97a	10785	}
cparata	1:fe40aec6e97a	10786
cparata	1:fe40aec6e97a	10787	/* Check accelerometer full scale constraints */
cparata	1:fe40aec6e97a	10788	/* Full scale of 16g must be the same for UI and OIS */
cparata	1:fe40aec6e97a	10789	if ( (val->ui.xl.fs == LSM6DSOX_XL_UI_16g) \|\|
cparata	1:fe40aec6e97a	10790	(val->ois.xl.fs == LSM6DSOX_XL_OIS_16g) ){
cparata	1:fe40aec6e97a	10791	val->ui.xl.fs = LSM6DSOX_XL_UI_16g;
cparata	1:fe40aec6e97a	10792	val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
cparata	1:fe40aec6e97a	10793	}
cparata	1:fe40aec6e97a	10794
cparata	1:fe40aec6e97a	10795	/* prapare new configuration */
cparata	1:fe40aec6e97a	10796
cparata	1:fe40aec6e97a	10797	/* Full scale of 16g must be the same for UI and OIS */
cparata	1:fe40aec6e97a	10798	if (val->ui.xl.fs == LSM6DSOX_XL_UI_16g) {
cparata	1:fe40aec6e97a	10799	ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	10800	}
cparata	1:fe40aec6e97a	10801	else {
cparata	1:fe40aec6e97a	10802	ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE;
cparata	1:fe40aec6e97a	10803	}
cparata	1:fe40aec6e97a	10804
cparata	1:fe40aec6e97a	10805	/* OIS new configuration */
cparata	1:fe40aec6e97a	10806	ctrl7_g.ois_on_en = val->ois.ctrl_md & 0x01U;
cparata	1:fe40aec6e97a	10807	func_cfg_access.ois_ctrl_from_ui = (val->ois.ctrl_md & 0x02U) >> 1;
cparata	1:fe40aec6e97a	10808
cparata	1:fe40aec6e97a	10809	switch (val->ois.ctrl_md) {
cparata	1:fe40aec6e97a	10810	case LSM6DSOX_OIS_ONLY_AUX:
cparata	1:fe40aec6e97a	10811	spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
cparata	1:fe40aec6e97a	10812	spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr \| (uint8_t)val->ois.xl.odr;
cparata	1:fe40aec6e97a	10813	spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
cparata	1:fe40aec6e97a	10814	spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
cparata	1:fe40aec6e97a	10815	break;
cparata	1:fe40aec6e97a	10816	case LSM6DSOX_OIS_ONLY_UI:
cparata	1:fe40aec6e97a	10817	ui_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
cparata	1:fe40aec6e97a	10818	ui_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr \| (uint8_t)val->ois.xl.odr;
cparata	1:fe40aec6e97a	10819	ui_ctrl1_ois.mode4_en = (uint8_t)val->ois.xl.odr;
cparata	1:fe40aec6e97a	10820	ui_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
cparata	1:fe40aec6e97a	10821	break;
cparata	1:fe40aec6e97a	10822	case LSM6DSOX_OIS_MIXED:
cparata	1:fe40aec6e97a	10823	spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
cparata	1:fe40aec6e97a	10824	ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr \| (uint8_t)val->ois.xl.odr;
cparata	1:fe40aec6e97a	10825	spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
cparata	1:fe40aec6e97a	10826	spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
cparata	1:fe40aec6e97a	10827	break;
cparata	1:fe40aec6e97a	10828	default:
cparata	1:fe40aec6e97a	10829	spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
cparata	1:fe40aec6e97a	10830	spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr \| (uint8_t)val->ois.xl.odr;
cparata	1:fe40aec6e97a	10831	spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
cparata	1:fe40aec6e97a	10832	spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
cparata	1:fe40aec6e97a	10833	break;
cparata	1:fe40aec6e97a	10834	}
cparata	1:fe40aec6e97a	10835
cparata	1:fe40aec6e97a	10836	/* UI new configuration */
cparata	1:fe40aec6e97a	10837	ctrl1_xl.odr_xl = odr_xl;
cparata	1:fe40aec6e97a	10838	ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs;
cparata	1:fe40aec6e97a	10839	ctrl5_c.xl_ulp_en = xl_ulp_en;
cparata	1:fe40aec6e97a	10840	ctrl6_c.xl_hm_mode = xl_hm_mode;
cparata	1:fe40aec6e97a	10841	ctrl7_g.g_hm_mode = g_hm_mode;
cparata	1:fe40aec6e97a	10842	ctrl2_g.odr_g = odr_gy;
cparata	1:fe40aec6e97a	10843	ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
cparata	1:fe40aec6e97a	10844
cparata	1:fe40aec6e97a	10845	/* writing checked configuration */
cparata	1:fe40aec6e97a	10846	if( ctx != NULL ) {
cparata	1:fe40aec6e97a	10847	bytecpy(&reg[0], ( uint8_t*)&ctrl1_xl);
cparata	1:fe40aec6e97a	10848	bytecpy(&reg[1], ( uint8_t*)&ctrl2_g);
cparata	1:fe40aec6e97a	10849	bytecpy(&reg[2], ( uint8_t*)&ctrl3_c);
cparata	1:fe40aec6e97a	10850	bytecpy(&reg[3], ( uint8_t*)&ctrl4_c);
cparata	1:fe40aec6e97a	10851	bytecpy(&reg[4], ( uint8_t*)&ctrl5_c);
cparata	1:fe40aec6e97a	10852	bytecpy(&reg[5], ( uint8_t*)&ctrl6_c);
cparata	1:fe40aec6e97a	10853	bytecpy(&reg[6], ( uint8_t*)&ctrl7_g);
cparata	1:fe40aec6e97a	10854	bytecpy(&reg[7], ( uint8_t*)&ctrl8_xl);
cparata	1:fe40aec6e97a	10855	if ( ret == 0 ) {
cparata	1:fe40aec6e97a	10856	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 8);
cparata	1:fe40aec6e97a	10857	}
cparata	1:fe40aec6e97a	10858	if ( ret == 0 ) {
cparata	1:fe40aec6e97a	10859	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
cparata	1:fe40aec6e97a	10860	(uint8_t*)&func_cfg_access, 1);
cparata	1:fe40aec6e97a	10861	}
cparata	1:fe40aec6e97a	10862	}
cparata	1:fe40aec6e97a	10863
cparata	1:fe40aec6e97a	10864	/* writing OIS checked configuration */
cparata	1:fe40aec6e97a	10865	if( aux_ctx != NULL ) {
cparata	1:fe40aec6e97a	10866	bytecpy(&reg[0], ( uint8_t*)&spi2_ctrl1_ois);
cparata	1:fe40aec6e97a	10867	bytecpy(&reg[1], ( uint8_t*)&spi2_ctrl2_ois);
cparata	1:fe40aec6e97a	10868	bytecpy(&reg[2], ( uint8_t*)&spi2_ctrl3_ois);
cparata	1:fe40aec6e97a	10869	if (ret == 0) {
cparata	1:fe40aec6e97a	10870	ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3);
cparata	1:fe40aec6e97a	10871	}
cparata	1:fe40aec6e97a	10872	}
cparata	1:fe40aec6e97a	10873	else {
cparata	1:fe40aec6e97a	10874	if( ctx != NULL ) {
cparata	1:fe40aec6e97a	10875	bytecpy(&reg[0], ( uint8_t*)&ui_ctrl1_ois);
cparata	1:fe40aec6e97a	10876	bytecpy(&reg[1], ( uint8_t*)&ui_ctrl2_ois);
cparata	1:fe40aec6e97a	10877	bytecpy(&reg[2], ( uint8_t*)&ui_ctrl3_ois);
cparata	1:fe40aec6e97a	10878	if (ret == 0) {
cparata	1:fe40aec6e97a	10879	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3);
cparata	1:fe40aec6e97a	10880	}
cparata	1:fe40aec6e97a	10881	}
cparata	1:fe40aec6e97a	10882	}
cparata	1:fe40aec6e97a	10883
cparata	1:fe40aec6e97a	10884	return ret;
cparata	1:fe40aec6e97a	10885	}
cparata	1:fe40aec6e97a	10886
cparata	1:fe40aec6e97a	10887	/**
cparata	1:fe40aec6e97a	10888	* @brief Sensor conversion parameters selection.[get]
cparata	1:fe40aec6e97a	10889	*
cparata	1:fe40aec6e97a	10890	* @param ctx communication interface handler. Use NULL to ingnore
cparata	1:fe40aec6e97a	10891	* this interface.(ptr)
cparata	1:fe40aec6e97a	10892	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	1:fe40aec6e97a	10893	* to ingnore this interface.(ptr)
cparata	1:fe40aec6e97a	10894	* @param val get the sensor conversion parameters.(ptr)
cparata	1:fe40aec6e97a	10895	*
cparata	1:fe40aec6e97a	10896	*/
cparata	1:fe40aec6e97a	10897	int32_t lsm6dsox_mode_get(lsm6dsox_ctx_t ctx, lsm6dsox_ctx_t aux_ctx,
cparata	1:fe40aec6e97a	10898	lsm6dsox_md_t *val)
cparata	1:fe40aec6e97a	10899	{
cparata	1:fe40aec6e97a	10900
cparata	1:fe40aec6e97a	10901	lsm6dsox_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
cparata	1:fe40aec6e97a	10902	lsm6dsox_emb_func_odr_cfg_c_t emb_func_odr_cfg_c;
cparata	1:fe40aec6e97a	10903	lsm6dsox_func_cfg_access_t func_cfg_access;
cparata	1:fe40aec6e97a	10904	lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois;
cparata	1:fe40aec6e97a	10905	lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois;
cparata	1:fe40aec6e97a	10906	lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois;
cparata	1:fe40aec6e97a	10907	lsm6dsox_emb_func_en_b_t emb_func_en_b;
cparata	1:fe40aec6e97a	10908	lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois;
cparata	1:fe40aec6e97a	10909	lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois;
cparata	1:fe40aec6e97a	10910	lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois;
cparata	1:fe40aec6e97a	10911	lsm6dsox_fsm_enable_a_t fsm_enable_a;
cparata	1:fe40aec6e97a	10912	lsm6dsox_fsm_enable_b_t fsm_enable_b;
cparata	1:fe40aec6e97a	10913	lsm6dsox_ctrl1_xl_t ctrl1_xl;
cparata	1:fe40aec6e97a	10914	lsm6dsox_ctrl2_g_t ctrl2_g;
cparata	1:fe40aec6e97a	10915	lsm6dsox_ctrl3_c_t ctrl3_c;
cparata	1:fe40aec6e97a	10916	lsm6dsox_ctrl4_c_t ctrl4_c;
cparata	1:fe40aec6e97a	10917	lsm6dsox_ctrl5_c_t ctrl5_c;
cparata	1:fe40aec6e97a	10918	lsm6dsox_ctrl6_c_t ctrl6_c;
cparata	1:fe40aec6e97a	10919	lsm6dsox_ctrl7_g_t ctrl7_g;
cparata	1:fe40aec6e97a	10920
cparata	1:fe40aec6e97a	10921	uint8_t reg[8];
cparata	1:fe40aec6e97a	10922	int32_t ret;
cparata	1:fe40aec6e97a	10923
cparata	1:fe40aec6e97a	10924	ret = 0;
cparata	1:fe40aec6e97a	10925
cparata	1:fe40aec6e97a	10926	/* reading the registers of the device */
cparata	1:fe40aec6e97a	10927	if( ctx != NULL ) {
cparata	1:fe40aec6e97a	10928	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, reg, 7);
cparata	1:fe40aec6e97a	10929	bytecpy(( uint8_t*)&ctrl1_xl, &reg[0]);
cparata	1:fe40aec6e97a	10930	bytecpy(( uint8_t*)&ctrl2_g, &reg[1]);
cparata	1:fe40aec6e97a	10931	bytecpy(( uint8_t*)&ctrl3_c, &reg[2]);
cparata	1:fe40aec6e97a	10932	bytecpy(( uint8_t*)&ctrl4_c, &reg[3]);
cparata	1:fe40aec6e97a	10933	bytecpy(( uint8_t*)&ctrl5_c, &reg[4]);
cparata	1:fe40aec6e97a	10934	bytecpy(( uint8_t*)&ctrl6_c, &reg[5]);
cparata	1:fe40aec6e97a	10935	bytecpy(( uint8_t*)&ctrl7_g, &reg[6]);
cparata	1:fe40aec6e97a	10936	if ( ret == 0 ) {
cparata	1:fe40aec6e97a	10937	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
cparata	1:fe40aec6e97a	10938	(uint8_t*)&func_cfg_access, 1);
cparata	1:fe40aec6e97a	10939	}
cparata	1:fe40aec6e97a	10940	if (ret == 0) {
cparata	1:fe40aec6e97a	10941	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	10942	}
cparata	1:fe40aec6e97a	10943	if (ret == 0) {
cparata	1:fe40aec6e97a	10944	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, reg, 2);
cparata	1:fe40aec6e97a	10945	bytecpy(( uint8_t*)&emb_func_odr_cfg_b, &reg[0]);
cparata	1:fe40aec6e97a	10946	bytecpy(( uint8_t*)&emb_func_odr_cfg_c, &reg[1]);
cparata	1:fe40aec6e97a	10947	}
cparata	1:fe40aec6e97a	10948	if (ret == 0) {
cparata	1:fe40aec6e97a	10949	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata	1:fe40aec6e97a	10950	(uint8_t*)&emb_func_en_b, 1);
cparata	1:fe40aec6e97a	10951	}
cparata	1:fe40aec6e97a	10952	if (ret == 0) {
cparata	1:fe40aec6e97a	10953	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, reg, 2);
cparata	1:fe40aec6e97a	10954	bytecpy(( uint8_t*)&fsm_enable_a, &reg[0]);
cparata	1:fe40aec6e97a	10955	bytecpy(( uint8_t*)&fsm_enable_b, &reg[1]);
cparata	1:fe40aec6e97a	10956	}
cparata	1:fe40aec6e97a	10957	if (ret == 0) {
cparata	1:fe40aec6e97a	10958	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	10959	}
cparata	1:fe40aec6e97a	10960	}
cparata	1:fe40aec6e97a	10961
cparata	1:fe40aec6e97a	10962	if( aux_ctx != NULL ) {
cparata	1:fe40aec6e97a	10963	if (ret == 0) {
cparata	1:fe40aec6e97a	10964	ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3);
cparata	1:fe40aec6e97a	10965	}
cparata	1:fe40aec6e97a	10966	bytecpy(( uint8_t*)&spi2_ctrl1_ois, &reg[0]);
cparata	1:fe40aec6e97a	10967	bytecpy(( uint8_t*)&spi2_ctrl2_ois, &reg[1]);
cparata	1:fe40aec6e97a	10968	bytecpy(( uint8_t*)&spi2_ctrl3_ois, &reg[2]);
cparata	1:fe40aec6e97a	10969	}
cparata	1:fe40aec6e97a	10970	else {
cparata	1:fe40aec6e97a	10971	if( ctx != NULL ) {
cparata	1:fe40aec6e97a	10972	if (ret == 0) {
cparata	1:fe40aec6e97a	10973	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3);
cparata	1:fe40aec6e97a	10974	}
cparata	1:fe40aec6e97a	10975	bytecpy(( uint8_t*)&ui_ctrl1_ois, &reg[0]);
cparata	1:fe40aec6e97a	10976	bytecpy(( uint8_t*)&ui_ctrl2_ois, &reg[1]);
cparata	1:fe40aec6e97a	10977	bytecpy(( uint8_t*)&ui_ctrl3_ois, &reg[2]);
cparata	1:fe40aec6e97a	10978	}
cparata	1:fe40aec6e97a	10979	}
cparata	1:fe40aec6e97a	10980
cparata	1:fe40aec6e97a	10981	/* fill the input structure */
cparata	1:fe40aec6e97a	10982
cparata	1:fe40aec6e97a	10983	/* get accelerometer configuration */
cparata	1:fe40aec6e97a	10984	switch ( (ctrl5_c.xl_ulp_en << 5) \| (ctrl6_c.xl_hm_mode << 4) \|
cparata	1:fe40aec6e97a	10985	ctrl1_xl.odr_xl ) {
cparata	1:fe40aec6e97a	10986	case LSM6DSOX_XL_UI_OFF:
cparata	1:fe40aec6e97a	10987	val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
cparata	1:fe40aec6e97a	10988	break;
cparata	1:fe40aec6e97a	10989	case LSM6DSOX_XL_UI_12Hz5_HP:
cparata	1:fe40aec6e97a	10990	val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_HP;
cparata	1:fe40aec6e97a	10991	break;
cparata	1:fe40aec6e97a	10992	case LSM6DSOX_XL_UI_26Hz_HP:
cparata	1:fe40aec6e97a	10993	val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_HP;
cparata	1:fe40aec6e97a	10994	break;
cparata	1:fe40aec6e97a	10995	case LSM6DSOX_XL_UI_52Hz_HP:
cparata	1:fe40aec6e97a	10996	val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_HP;
cparata	1:fe40aec6e97a	10997	break;
cparata	1:fe40aec6e97a	10998	case LSM6DSOX_XL_UI_104Hz_HP:
cparata	1:fe40aec6e97a	10999	val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_HP;
cparata	1:fe40aec6e97a	11000	break;
cparata	1:fe40aec6e97a	11001	case LSM6DSOX_XL_UI_208Hz_HP:
cparata	1:fe40aec6e97a	11002	val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_HP;
cparata	1:fe40aec6e97a	11003	break;
cparata	1:fe40aec6e97a	11004	case LSM6DSOX_XL_UI_416Hz_HP:
cparata	1:fe40aec6e97a	11005	val->ui.xl.odr = LSM6DSOX_XL_UI_416Hz_HP;
cparata	1:fe40aec6e97a	11006	break;
cparata	1:fe40aec6e97a	11007	case LSM6DSOX_XL_UI_833Hz_HP:
cparata	1:fe40aec6e97a	11008	val->ui.xl.odr = LSM6DSOX_XL_UI_833Hz_HP;
cparata	1:fe40aec6e97a	11009	break;
cparata	1:fe40aec6e97a	11010	case LSM6DSOX_XL_UI_1667Hz_HP:
cparata	1:fe40aec6e97a	11011	val->ui.xl.odr = LSM6DSOX_XL_UI_1667Hz_HP;
cparata	1:fe40aec6e97a	11012	break;
cparata	1:fe40aec6e97a	11013	case LSM6DSOX_XL_UI_3333Hz_HP:
cparata	1:fe40aec6e97a	11014	val->ui.xl.odr = LSM6DSOX_XL_UI_3333Hz_HP;
cparata	1:fe40aec6e97a	11015	break;
cparata	1:fe40aec6e97a	11016	case LSM6DSOX_XL_UI_6667Hz_HP:
cparata	1:fe40aec6e97a	11017	val->ui.xl.odr = LSM6DSOX_XL_UI_6667Hz_HP;
cparata	1:fe40aec6e97a	11018	break;
cparata	1:fe40aec6e97a	11019	case LSM6DSOX_XL_UI_1Hz6_LP:
cparata	1:fe40aec6e97a	11020	val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_LP;
cparata	1:fe40aec6e97a	11021	break;
cparata	1:fe40aec6e97a	11022	case LSM6DSOX_XL_UI_12Hz5_LP:
cparata	1:fe40aec6e97a	11023	val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_LP;
cparata	1:fe40aec6e97a	11024	break;
cparata	1:fe40aec6e97a	11025	case LSM6DSOX_XL_UI_26Hz_LP:
cparata	1:fe40aec6e97a	11026	val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_LP;
cparata	1:fe40aec6e97a	11027	break;
cparata	1:fe40aec6e97a	11028	case LSM6DSOX_XL_UI_52Hz_LP:
cparata	1:fe40aec6e97a	11029	val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_LP;
cparata	1:fe40aec6e97a	11030	break;
cparata	1:fe40aec6e97a	11031	case LSM6DSOX_XL_UI_104Hz_NM:
cparata	1:fe40aec6e97a	11032	val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_NM;
cparata	1:fe40aec6e97a	11033	break;
cparata	1:fe40aec6e97a	11034	case LSM6DSOX_XL_UI_208Hz_NM:
cparata	1:fe40aec6e97a	11035	val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_NM;
cparata	1:fe40aec6e97a	11036	break;
cparata	1:fe40aec6e97a	11037	case LSM6DSOX_XL_UI_1Hz6_ULP:
cparata	1:fe40aec6e97a	11038	val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_ULP;
cparata	1:fe40aec6e97a	11039	break;
cparata	1:fe40aec6e97a	11040	case LSM6DSOX_XL_UI_12Hz5_ULP:
cparata	1:fe40aec6e97a	11041	val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_ULP;
cparata	1:fe40aec6e97a	11042	break;
cparata	1:fe40aec6e97a	11043	case LSM6DSOX_XL_UI_26Hz_ULP:
cparata	1:fe40aec6e97a	11044	val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_ULP;
cparata	1:fe40aec6e97a	11045	break;
cparata	1:fe40aec6e97a	11046	case LSM6DSOX_XL_UI_52Hz_ULP:
cparata	1:fe40aec6e97a	11047	val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_ULP;
cparata	1:fe40aec6e97a	11048	break;
cparata	1:fe40aec6e97a	11049	case LSM6DSOX_XL_UI_104Hz_ULP:
cparata	1:fe40aec6e97a	11050	val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_ULP;
cparata	1:fe40aec6e97a	11051	break;
cparata	1:fe40aec6e97a	11052	case LSM6DSOX_XL_UI_208Hz_ULP:
cparata	1:fe40aec6e97a	11053	val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_ULP;
cparata	1:fe40aec6e97a	11054	break;
cparata	1:fe40aec6e97a	11055	default:
cparata	1:fe40aec6e97a	11056	val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
cparata	1:fe40aec6e97a	11057	break;
cparata	1:fe40aec6e97a	11058	}
cparata	1:fe40aec6e97a	11059
cparata	1:fe40aec6e97a	11060	switch ( ctrl1_xl.fs_xl ) {
cparata	1:fe40aec6e97a	11061	case LSM6DSOX_XL_UI_2g:
cparata	1:fe40aec6e97a	11062	val->ui.xl.fs = LSM6DSOX_XL_UI_2g;
cparata	1:fe40aec6e97a	11063	break;
cparata	1:fe40aec6e97a	11064	case LSM6DSOX_XL_UI_4g:
cparata	1:fe40aec6e97a	11065	val->ui.xl.fs = LSM6DSOX_XL_UI_4g;
cparata	1:fe40aec6e97a	11066	break;
cparata	1:fe40aec6e97a	11067	case LSM6DSOX_XL_UI_8g:
cparata	1:fe40aec6e97a	11068	val->ui.xl.fs = LSM6DSOX_XL_UI_8g;
cparata	1:fe40aec6e97a	11069	break;
cparata	1:fe40aec6e97a	11070	case LSM6DSOX_XL_UI_16g:
cparata	1:fe40aec6e97a	11071	val->ui.xl.fs = LSM6DSOX_XL_UI_16g;
cparata	1:fe40aec6e97a	11072	break;
cparata	1:fe40aec6e97a	11073	default:
cparata	1:fe40aec6e97a	11074	val->ui.xl.fs = LSM6DSOX_XL_UI_2g;
cparata	1:fe40aec6e97a	11075	break;
cparata	1:fe40aec6e97a	11076	}
cparata	1:fe40aec6e97a	11077
cparata	1:fe40aec6e97a	11078	/* get gyroscope configuration */
cparata	1:fe40aec6e97a	11079	switch ( (ctrl7_g.g_hm_mode << 4) \| ctrl2_g.odr_g) {
cparata	1:fe40aec6e97a	11080	case LSM6DSOX_GY_UI_OFF:
cparata	1:fe40aec6e97a	11081	val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
cparata	1:fe40aec6e97a	11082	break;
cparata	1:fe40aec6e97a	11083	case LSM6DSOX_GY_UI_12Hz5_LP:
cparata	1:fe40aec6e97a	11084	val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_LP;
cparata	1:fe40aec6e97a	11085	break;
cparata	1:fe40aec6e97a	11086	case LSM6DSOX_GY_UI_12Hz5_HP:
cparata	1:fe40aec6e97a	11087	val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_HP;
cparata	1:fe40aec6e97a	11088	break;
cparata	1:fe40aec6e97a	11089	case LSM6DSOX_GY_UI_26Hz_LP:
cparata	1:fe40aec6e97a	11090	val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_LP;
cparata	1:fe40aec6e97a	11091	break;
cparata	1:fe40aec6e97a	11092	case LSM6DSOX_GY_UI_26Hz_HP:
cparata	1:fe40aec6e97a	11093	val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_HP;
cparata	1:fe40aec6e97a	11094	break;
cparata	1:fe40aec6e97a	11095	case LSM6DSOX_GY_UI_52Hz_LP:
cparata	1:fe40aec6e97a	11096	val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_LP;
cparata	1:fe40aec6e97a	11097	break;
cparata	1:fe40aec6e97a	11098	case LSM6DSOX_GY_UI_52Hz_HP:
cparata	1:fe40aec6e97a	11099	val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_HP;
cparata	1:fe40aec6e97a	11100	break;
cparata	1:fe40aec6e97a	11101	case LSM6DSOX_GY_UI_104Hz_NM:
cparata	1:fe40aec6e97a	11102	val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_NM;
cparata	1:fe40aec6e97a	11103	break;
cparata	1:fe40aec6e97a	11104	case LSM6DSOX_GY_UI_104Hz_HP:
cparata	1:fe40aec6e97a	11105	val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_HP;
cparata	1:fe40aec6e97a	11106	break;
cparata	1:fe40aec6e97a	11107	case LSM6DSOX_GY_UI_208Hz_NM:
cparata	1:fe40aec6e97a	11108	val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_NM;
cparata	1:fe40aec6e97a	11109	break;
cparata	1:fe40aec6e97a	11110	case LSM6DSOX_GY_UI_208Hz_HP:
cparata	1:fe40aec6e97a	11111	val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_HP;
cparata	1:fe40aec6e97a	11112	break;
cparata	1:fe40aec6e97a	11113	case LSM6DSOX_GY_UI_416Hz_HP:
cparata	1:fe40aec6e97a	11114	val->ui.gy.odr = LSM6DSOX_GY_UI_416Hz_HP;
cparata	1:fe40aec6e97a	11115	break;
cparata	1:fe40aec6e97a	11116	case LSM6DSOX_GY_UI_833Hz_HP:
cparata	1:fe40aec6e97a	11117	val->ui.gy.odr = LSM6DSOX_GY_UI_833Hz_HP;
cparata	1:fe40aec6e97a	11118	break;
cparata	1:fe40aec6e97a	11119	case LSM6DSOX_GY_UI_1667Hz_HP:
cparata	1:fe40aec6e97a	11120	val->ui.gy.odr = LSM6DSOX_GY_UI_1667Hz_HP;
cparata	1:fe40aec6e97a	11121	break;
cparata	1:fe40aec6e97a	11122	case LSM6DSOX_GY_UI_3333Hz_HP:
cparata	1:fe40aec6e97a	11123	val->ui.gy.odr = LSM6DSOX_GY_UI_3333Hz_HP;
cparata	1:fe40aec6e97a	11124	break;
cparata	1:fe40aec6e97a	11125	case LSM6DSOX_GY_UI_6667Hz_HP:
cparata	1:fe40aec6e97a	11126	val->ui.gy.odr = LSM6DSOX_GY_UI_6667Hz_HP;
cparata	1:fe40aec6e97a	11127	break;
cparata	1:fe40aec6e97a	11128	default:
cparata	1:fe40aec6e97a	11129	val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
cparata	1:fe40aec6e97a	11130	break;
cparata	1:fe40aec6e97a	11131	}
cparata	1:fe40aec6e97a	11132
cparata	1:fe40aec6e97a	11133	switch (ctrl2_g.fs_g) {
cparata	1:fe40aec6e97a	11134	case LSM6DSOX_GY_UI_125dps:
cparata	1:fe40aec6e97a	11135	val->ui.gy.fs = LSM6DSOX_GY_UI_125dps;
cparata	1:fe40aec6e97a	11136	break;
cparata	1:fe40aec6e97a	11137	case LSM6DSOX_GY_UI_250dps:
cparata	1:fe40aec6e97a	11138	val->ui.gy.fs = LSM6DSOX_GY_UI_250dps;
cparata	1:fe40aec6e97a	11139	break;
cparata	1:fe40aec6e97a	11140	case LSM6DSOX_GY_UI_500dps:
cparata	1:fe40aec6e97a	11141	val->ui.gy.fs = LSM6DSOX_GY_UI_500dps;
cparata	1:fe40aec6e97a	11142	break;
cparata	1:fe40aec6e97a	11143	case LSM6DSOX_GY_UI_1000dps:
cparata	1:fe40aec6e97a	11144	val->ui.gy.fs = LSM6DSOX_GY_UI_1000dps;
cparata	1:fe40aec6e97a	11145	break;
cparata	1:fe40aec6e97a	11146	case LSM6DSOX_GY_UI_2000dps:
cparata	1:fe40aec6e97a	11147	val->ui.gy.fs = LSM6DSOX_GY_UI_2000dps;
cparata	1:fe40aec6e97a	11148	break;
cparata	1:fe40aec6e97a	11149	default:
cparata	1:fe40aec6e97a	11150	val->ui.gy.fs = LSM6DSOX_GY_UI_125dps;
cparata	1:fe40aec6e97a	11151	break;
cparata	1:fe40aec6e97a	11152	}
cparata	1:fe40aec6e97a	11153
cparata	1:fe40aec6e97a	11154	/* get finite state machine configuration */
cparata	1:fe40aec6e97a	11155	if ( (fsm_enable_a.fsm1_en \| fsm_enable_a.fsm2_en \| fsm_enable_a.fsm3_en \|
cparata	1:fe40aec6e97a	11156	fsm_enable_a.fsm4_en \| fsm_enable_a.fsm5_en \| fsm_enable_a.fsm6_en \|
cparata	1:fe40aec6e97a	11157	fsm_enable_a.fsm7_en \| fsm_enable_a.fsm8_en \| fsm_enable_b.fsm9_en \|
cparata	1:fe40aec6e97a	11158	fsm_enable_b.fsm10_en \| fsm_enable_b.fsm11_en \|
cparata	1:fe40aec6e97a	11159	fsm_enable_b.fsm12_en \| fsm_enable_b.fsm13_en \|
cparata	1:fe40aec6e97a	11160	fsm_enable_b.fsm14_en \| fsm_enable_b.fsm15_en \|
cparata	1:fe40aec6e97a	11161	fsm_enable_b.fsm16_en) == PROPERTY_ENABLE ){
cparata	1:fe40aec6e97a	11162	switch (emb_func_odr_cfg_b.fsm_odr) {
cparata	1:fe40aec6e97a	11163	case LSM6DSOX_FSM_12Hz5:
cparata	1:fe40aec6e97a	11164	val->fsm.odr = LSM6DSOX_FSM_12Hz5;
cparata	1:fe40aec6e97a	11165	break;
cparata	1:fe40aec6e97a	11166	case LSM6DSOX_FSM_26Hz:
cparata	1:fe40aec6e97a	11167	val->fsm.odr = LSM6DSOX_FSM_26Hz;
cparata	1:fe40aec6e97a	11168	break;
cparata	1:fe40aec6e97a	11169	case LSM6DSOX_FSM_52Hz:
cparata	1:fe40aec6e97a	11170	val->fsm.odr = LSM6DSOX_FSM_52Hz;
cparata	1:fe40aec6e97a	11171	break;
cparata	1:fe40aec6e97a	11172	case LSM6DSOX_FSM_104Hz:
cparata	1:fe40aec6e97a	11173	val->fsm.odr = LSM6DSOX_FSM_104Hz;
cparata	1:fe40aec6e97a	11174	break;
cparata	1:fe40aec6e97a	11175	default:
cparata	1:fe40aec6e97a	11176	val->fsm.odr = LSM6DSOX_FSM_12Hz5;
cparata	1:fe40aec6e97a	11177	break;
cparata	1:fe40aec6e97a	11178	}
cparata	1:fe40aec6e97a	11179
cparata	1:fe40aec6e97a	11180	val->fsm.sens = LSM6DSOX_FSM_XL_GY;
cparata	1:fe40aec6e97a	11181	if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF) {
cparata	1:fe40aec6e97a	11182	val->fsm.sens = LSM6DSOX_FSM_XL;
cparata	1:fe40aec6e97a	11183	}
cparata	1:fe40aec6e97a	11184	if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF) {
cparata	1:fe40aec6e97a	11185	val->fsm.sens = LSM6DSOX_FSM_GY;
cparata	1:fe40aec6e97a	11186	}
cparata	1:fe40aec6e97a	11187	}
cparata	1:fe40aec6e97a	11188	else {
cparata	1:fe40aec6e97a	11189	val->fsm.sens = LSM6DSOX_FSM_DISABLE;
cparata	1:fe40aec6e97a	11190	}
cparata	1:fe40aec6e97a	11191
cparata	1:fe40aec6e97a	11192	/* get machine learning core configuration */
cparata	1:fe40aec6e97a	11193	if (emb_func_en_b.mlc_en == PROPERTY_ENABLE) {
cparata	1:fe40aec6e97a	11194	switch (emb_func_odr_cfg_c.mlc_odr) {
cparata	1:fe40aec6e97a	11195	case LSM6DSOX_MLC_12Hz5:
cparata	1:fe40aec6e97a	11196	val->mlc.odr = LSM6DSOX_MLC_12Hz5;
cparata	1:fe40aec6e97a	11197	break;
cparata	1:fe40aec6e97a	11198	case LSM6DSOX_MLC_26Hz:
cparata	1:fe40aec6e97a	11199	val->mlc.odr = LSM6DSOX_MLC_26Hz;
cparata	1:fe40aec6e97a	11200	break;
cparata	1:fe40aec6e97a	11201	case LSM6DSOX_MLC_52Hz:
cparata	1:fe40aec6e97a	11202	val->mlc.odr = LSM6DSOX_MLC_52Hz;
cparata	1:fe40aec6e97a	11203	break;
cparata	1:fe40aec6e97a	11204	case LSM6DSOX_MLC_104Hz:
cparata	1:fe40aec6e97a	11205	val->mlc.odr = LSM6DSOX_MLC_104Hz;
cparata	1:fe40aec6e97a	11206	break;
cparata	1:fe40aec6e97a	11207	default:
cparata	1:fe40aec6e97a	11208	val->mlc.odr = LSM6DSOX_MLC_12Hz5;
cparata	1:fe40aec6e97a	11209	break;
cparata	1:fe40aec6e97a	11210	}
cparata	1:fe40aec6e97a	11211
cparata	1:fe40aec6e97a	11212	val->mlc.sens = LSM6DSOX_MLC_XL_GY;
cparata	1:fe40aec6e97a	11213	if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF) {
cparata	1:fe40aec6e97a	11214	val->mlc.sens = LSM6DSOX_MLC_XL;
cparata	1:fe40aec6e97a	11215	}
cparata	1:fe40aec6e97a	11216	if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF) {
cparata	1:fe40aec6e97a	11217	val->mlc.sens = LSM6DSOX_MLC_DISABLE;
cparata	1:fe40aec6e97a	11218	}
cparata	1:fe40aec6e97a	11219	}
cparata	1:fe40aec6e97a	11220	else {
cparata	1:fe40aec6e97a	11221	val->mlc.sens = LSM6DSOX_MLC_DISABLE;
cparata	1:fe40aec6e97a	11222	}
cparata	1:fe40aec6e97a	11223
cparata	1:fe40aec6e97a	11224	/* get ois configuration */
cparata	1:fe40aec6e97a	11225
cparata	1:fe40aec6e97a	11226	/* OIS configuration mode */
cparata	1:fe40aec6e97a	11227	switch ( (func_cfg_access.ois_ctrl_from_ui << 1) + ctrl7_g.ois_on_en ) {
cparata	1:fe40aec6e97a	11228	case LSM6DSOX_OIS_ONLY_AUX:
cparata	1:fe40aec6e97a	11229	switch ( spi2_ctrl3_ois.fs_xl_ois ) {
cparata	1:fe40aec6e97a	11230	case LSM6DSOX_XL_OIS_2g:
cparata	1:fe40aec6e97a	11231	val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
cparata	1:fe40aec6e97a	11232	break;
cparata	1:fe40aec6e97a	11233	case LSM6DSOX_XL_OIS_4g:
cparata	1:fe40aec6e97a	11234	val->ois.xl.fs = LSM6DSOX_XL_OIS_4g;
cparata	1:fe40aec6e97a	11235	break;
cparata	1:fe40aec6e97a	11236	case LSM6DSOX_XL_OIS_8g:
cparata	1:fe40aec6e97a	11237	val->ois.xl.fs = LSM6DSOX_XL_OIS_8g;
cparata	1:fe40aec6e97a	11238	break;
cparata	1:fe40aec6e97a	11239	case LSM6DSOX_XL_OIS_16g:
cparata	1:fe40aec6e97a	11240	val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
cparata	1:fe40aec6e97a	11241	break;
cparata	1:fe40aec6e97a	11242	default:
cparata	1:fe40aec6e97a	11243	val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
cparata	1:fe40aec6e97a	11244	break;
cparata	1:fe40aec6e97a	11245	}
cparata	1:fe40aec6e97a	11246	switch ( spi2_ctrl1_ois.mode4_en ) {
cparata	1:fe40aec6e97a	11247	case LSM6DSOX_XL_OIS_OFF:
cparata	1:fe40aec6e97a	11248	val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
cparata	1:fe40aec6e97a	11249	break;
cparata	1:fe40aec6e97a	11250	case LSM6DSOX_XL_OIS_6667Hz_HP:
cparata	1:fe40aec6e97a	11251	val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP;
cparata	1:fe40aec6e97a	11252	break;
cparata	1:fe40aec6e97a	11253	default:
cparata	1:fe40aec6e97a	11254	val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
cparata	1:fe40aec6e97a	11255	break;
cparata	1:fe40aec6e97a	11256	}
cparata	1:fe40aec6e97a	11257	switch ( spi2_ctrl1_ois.fs_g_ois ) {
cparata	1:fe40aec6e97a	11258	case LSM6DSOX_GY_OIS_250dps:
cparata	1:fe40aec6e97a	11259	val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
cparata	1:fe40aec6e97a	11260	break;
cparata	1:fe40aec6e97a	11261	case LSM6DSOX_GY_OIS_500dps:
cparata	1:fe40aec6e97a	11262	val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps;
cparata	1:fe40aec6e97a	11263	break;
cparata	1:fe40aec6e97a	11264	case LSM6DSOX_GY_OIS_1000dps:
cparata	1:fe40aec6e97a	11265	val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps;
cparata	1:fe40aec6e97a	11266	break;
cparata	1:fe40aec6e97a	11267	case LSM6DSOX_GY_OIS_2000dps:
cparata	1:fe40aec6e97a	11268	val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps;
cparata	1:fe40aec6e97a	11269	break;
cparata	1:fe40aec6e97a	11270	default:
cparata	1:fe40aec6e97a	11271	val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
cparata	1:fe40aec6e97a	11272	break;
cparata	1:fe40aec6e97a	11273	}
cparata	1:fe40aec6e97a	11274	switch ( spi2_ctrl1_ois.ois_en_spi2 ) {
cparata	1:fe40aec6e97a	11275	case LSM6DSOX_GY_OIS_OFF:
cparata	1:fe40aec6e97a	11276	val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
cparata	1:fe40aec6e97a	11277	break;
cparata	1:fe40aec6e97a	11278	case LSM6DSOX_GY_OIS_6667Hz_HP:
cparata	1:fe40aec6e97a	11279	val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
cparata	1:fe40aec6e97a	11280	break;
cparata	1:fe40aec6e97a	11281	default:
cparata	1:fe40aec6e97a	11282	val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
cparata	1:fe40aec6e97a	11283	break;
cparata	1:fe40aec6e97a	11284	}
cparata	1:fe40aec6e97a	11285	val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_AUX;
cparata	1:fe40aec6e97a	11286	break;
cparata	1:fe40aec6e97a	11287	case LSM6DSOX_OIS_ONLY_UI:
cparata	1:fe40aec6e97a	11288	switch ( ui_ctrl3_ois.fs_xl_ois ) {
cparata	1:fe40aec6e97a	11289	case LSM6DSOX_XL_OIS_2g:
cparata	1:fe40aec6e97a	11290	val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
cparata	1:fe40aec6e97a	11291	break;
cparata	1:fe40aec6e97a	11292	case LSM6DSOX_XL_OIS_4g:
cparata	1:fe40aec6e97a	11293	val->ois.xl.fs = LSM6DSOX_XL_OIS_4g;
cparata	1:fe40aec6e97a	11294	break;
cparata	1:fe40aec6e97a	11295	case LSM6DSOX_XL_OIS_8g:
cparata	1:fe40aec6e97a	11296	val->ois.xl.fs = LSM6DSOX_XL_OIS_8g;
cparata	1:fe40aec6e97a	11297	break;
cparata	1:fe40aec6e97a	11298	case LSM6DSOX_XL_OIS_16g:
cparata	1:fe40aec6e97a	11299	val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
cparata	1:fe40aec6e97a	11300	break;
cparata	1:fe40aec6e97a	11301	default:
cparata	1:fe40aec6e97a	11302	val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
cparata	1:fe40aec6e97a	11303	break;
cparata	1:fe40aec6e97a	11304	}
cparata	1:fe40aec6e97a	11305	switch ( ui_ctrl1_ois.ois_en_spi2 ) {
cparata	1:fe40aec6e97a	11306	case LSM6DSOX_GY_OIS_OFF:
cparata	1:fe40aec6e97a	11307	val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
cparata	1:fe40aec6e97a	11308	break;
cparata	1:fe40aec6e97a	11309	case LSM6DSOX_GY_OIS_6667Hz_HP:
cparata	1:fe40aec6e97a	11310	val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
cparata	1:fe40aec6e97a	11311	break;
cparata	1:fe40aec6e97a	11312	default:
cparata	1:fe40aec6e97a	11313	val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
cparata	1:fe40aec6e97a	11314	break;
cparata	1:fe40aec6e97a	11315	}
cparata	1:fe40aec6e97a	11316	switch ( ui_ctrl1_ois.fs_g_ois ) {
cparata	1:fe40aec6e97a	11317	case LSM6DSOX_GY_OIS_250dps:
cparata	1:fe40aec6e97a	11318	val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
cparata	1:fe40aec6e97a	11319	break;
cparata	1:fe40aec6e97a	11320	case LSM6DSOX_GY_OIS_125dps:
cparata	1:fe40aec6e97a	11321	val->ois.gy.fs = LSM6DSOX_GY_OIS_125dps;
cparata	1:fe40aec6e97a	11322	break;
cparata	1:fe40aec6e97a	11323	case LSM6DSOX_GY_OIS_500dps:
cparata	1:fe40aec6e97a	11324	val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps;
cparata	1:fe40aec6e97a	11325	break;
cparata	1:fe40aec6e97a	11326	case LSM6DSOX_GY_OIS_1000dps:
cparata	1:fe40aec6e97a	11327	val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps;
cparata	1:fe40aec6e97a	11328	break;
cparata	1:fe40aec6e97a	11329	case LSM6DSOX_GY_OIS_2000dps:
cparata	1:fe40aec6e97a	11330	val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps;
cparata	1:fe40aec6e97a	11331	break;
cparata	1:fe40aec6e97a	11332	default:
cparata	1:fe40aec6e97a	11333	val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
cparata	1:fe40aec6e97a	11334	break;
cparata	1:fe40aec6e97a	11335	}
cparata	1:fe40aec6e97a	11336	switch ( ui_ctrl1_ois.mode4_en ) {
cparata	1:fe40aec6e97a	11337	case LSM6DSOX_XL_OIS_OFF:
cparata	1:fe40aec6e97a	11338	val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
cparata	1:fe40aec6e97a	11339	break;
cparata	1:fe40aec6e97a	11340	case LSM6DSOX_XL_OIS_6667Hz_HP:
cparata	1:fe40aec6e97a	11341	val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP;
cparata	1:fe40aec6e97a	11342	break;
cparata	1:fe40aec6e97a	11343	default:
cparata	1:fe40aec6e97a	11344	val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
cparata	1:fe40aec6e97a	11345	break;
cparata	1:fe40aec6e97a	11346	}
cparata	1:fe40aec6e97a	11347	val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_UI;
cparata	1:fe40aec6e97a	11348	break;
cparata	1:fe40aec6e97a	11349	case LSM6DSOX_OIS_MIXED:
cparata	1:fe40aec6e97a	11350	switch ( spi2_ctrl3_ois.fs_xl_ois ) {
cparata	1:fe40aec6e97a	11351	case LSM6DSOX_XL_OIS_2g:
cparata	1:fe40aec6e97a	11352	val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
cparata	1:fe40aec6e97a	11353	break;
cparata	1:fe40aec6e97a	11354	case LSM6DSOX_XL_OIS_4g:
cparata	1:fe40aec6e97a	11355	val->ois.xl.fs = LSM6DSOX_XL_OIS_4g;
cparata	1:fe40aec6e97a	11356	break;
cparata	1:fe40aec6e97a	11357	case LSM6DSOX_XL_OIS_8g:
cparata	1:fe40aec6e97a	11358	val->ois.xl.fs = LSM6DSOX_XL_OIS_8g;
cparata	1:fe40aec6e97a	11359	break;
cparata	1:fe40aec6e97a	11360	case LSM6DSOX_XL_OIS_16g:
cparata	1:fe40aec6e97a	11361	val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
cparata	1:fe40aec6e97a	11362	break;
cparata	1:fe40aec6e97a	11363	default:
cparata	1:fe40aec6e97a	11364	val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
cparata	1:fe40aec6e97a	11365	break;
cparata	1:fe40aec6e97a	11366	}
cparata	1:fe40aec6e97a	11367	switch ( spi2_ctrl1_ois.mode4_en ) {
cparata	1:fe40aec6e97a	11368	case LSM6DSOX_XL_OIS_OFF:
cparata	1:fe40aec6e97a	11369	val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
cparata	1:fe40aec6e97a	11370	break;
cparata	1:fe40aec6e97a	11371	case LSM6DSOX_XL_OIS_6667Hz_HP:
cparata	1:fe40aec6e97a	11372	val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP;
cparata	1:fe40aec6e97a	11373	break;
cparata	1:fe40aec6e97a	11374	default:
cparata	1:fe40aec6e97a	11375	val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
cparata	1:fe40aec6e97a	11376	break;
cparata	1:fe40aec6e97a	11377	}
cparata	1:fe40aec6e97a	11378	switch ( spi2_ctrl1_ois.fs_g_ois ) {
cparata	1:fe40aec6e97a	11379	case LSM6DSOX_GY_OIS_250dps:
cparata	1:fe40aec6e97a	11380	val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
cparata	1:fe40aec6e97a	11381	break;
cparata	1:fe40aec6e97a	11382	case LSM6DSOX_GY_OIS_500dps:
cparata	1:fe40aec6e97a	11383	val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps;
cparata	1:fe40aec6e97a	11384	break;
cparata	1:fe40aec6e97a	11385	case LSM6DSOX_GY_OIS_1000dps:
cparata	1:fe40aec6e97a	11386	val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps;
cparata	1:fe40aec6e97a	11387	break;
cparata	1:fe40aec6e97a	11388	case LSM6DSOX_GY_OIS_2000dps:
cparata	1:fe40aec6e97a	11389	val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps;
cparata	1:fe40aec6e97a	11390	break;
cparata	1:fe40aec6e97a	11391	default:
cparata	1:fe40aec6e97a	11392	val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
cparata	1:fe40aec6e97a	11393	break;
cparata	1:fe40aec6e97a	11394	}
cparata	1:fe40aec6e97a	11395	switch ( ui_ctrl1_ois.ois_en_spi2 ) {
cparata	1:fe40aec6e97a	11396	case LSM6DSOX_GY_OIS_OFF:
cparata	1:fe40aec6e97a	11397	val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
cparata	1:fe40aec6e97a	11398	break;
cparata	1:fe40aec6e97a	11399	case LSM6DSOX_GY_OIS_6667Hz_HP:
cparata	1:fe40aec6e97a	11400	val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
cparata	1:fe40aec6e97a	11401	break;
cparata	1:fe40aec6e97a	11402	default:
cparata	1:fe40aec6e97a	11403	val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
cparata	1:fe40aec6e97a	11404	break;
cparata	1:fe40aec6e97a	11405	}
cparata	1:fe40aec6e97a	11406	val->ois.ctrl_md = LSM6DSOX_OIS_MIXED;
cparata	1:fe40aec6e97a	11407	break;
cparata	1:fe40aec6e97a	11408	default:
cparata	1:fe40aec6e97a	11409	spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
cparata	1:fe40aec6e97a	11410	spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr \| (uint8_t)val->ois.xl.odr;
cparata	1:fe40aec6e97a	11411	spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
cparata	1:fe40aec6e97a	11412	spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
cparata	1:fe40aec6e97a	11413	val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_AUX;
cparata	1:fe40aec6e97a	11414	break;
cparata	1:fe40aec6e97a	11415	}
cparata	1:fe40aec6e97a	11416
cparata	1:fe40aec6e97a	11417	return ret;
cparata	1:fe40aec6e97a	11418	}
cparata	1:fe40aec6e97a	11419
cparata	1:fe40aec6e97a	11420	/**
cparata	1:fe40aec6e97a	11421	* @brief Read data in engineering unit.[get]
cparata	1:fe40aec6e97a	11422	*
cparata	1:fe40aec6e97a	11423	* @param ctx communication interface handler.(ptr)
cparata	1:fe40aec6e97a	11424	* @param md the sensor conversion parameters.(ptr)
cparata	1:fe40aec6e97a	11425	*
cparata	1:fe40aec6e97a	11426	*/
cparata	1:fe40aec6e97a	11427	int32_t lsm6dsox_data_get(lsm6dsox_ctx_t ctx, lsm6dsox_ctx_t aux_ctx,
cparata	1:fe40aec6e97a	11428	lsm6dsox_md_t md, lsm6dsox_data_t data)
cparata	1:fe40aec6e97a	11429	{
cparata	1:fe40aec6e97a	11430	uint8_t buff[14];
cparata	1:fe40aec6e97a	11431	int32_t ret;
cparata	1:fe40aec6e97a	11432	uint8_t i;
cparata	1:fe40aec6e97a	11433	uint8_t j;
cparata	1:fe40aec6e97a	11434
cparata	1:fe40aec6e97a	11435	ret = 0;
cparata	1:fe40aec6e97a	11436
cparata	1:fe40aec6e97a	11437	/* read data */
cparata	1:fe40aec6e97a	11438	if( ctx != NULL ) {
cparata	1:fe40aec6e97a	11439	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 14);
cparata	1:fe40aec6e97a	11440	}
cparata	1:fe40aec6e97a	11441	j = 0;
cparata	1:fe40aec6e97a	11442
cparata	1:fe40aec6e97a	11443	/* temperature conversion */
cparata	1:fe40aec6e97a	11444	data->ui.heat.raw = (int16_t)buff[j+1U];
cparata	1:fe40aec6e97a	11445	data->ui.heat.raw = ( ((int16_t)data->ui.heat.raw * (int16_t)256) +
cparata	1:fe40aec6e97a	11446	(int16_t)buff[j] );
cparata	1:fe40aec6e97a	11447	j+=2U;
cparata	1:fe40aec6e97a	11448	data->ui.heat.deg_c = lsm6dsox_from_lsb_to_celsius((int16_t)data->ui.heat.raw);
cparata	1:fe40aec6e97a	11449
cparata	1:fe40aec6e97a	11450	/* angular rate conversion */
cparata	1:fe40aec6e97a	11451	for (i = 0U; i < 3U; i++) {
cparata	1:fe40aec6e97a	11452	data->ui.gy.raw[i] = (int16_t)buff[j+1U];
cparata	1:fe40aec6e97a	11453	data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
cparata	1:fe40aec6e97a	11454	j+=2U;
cparata	1:fe40aec6e97a	11455	switch ( md->ui.gy.fs ) {
cparata	1:fe40aec6e97a	11456	case LSM6DSOX_GY_UI_250dps:
cparata	1:fe40aec6e97a	11457	data->ui.gy.mdps[i] = lsm6dsox_from_fs250_to_mdps(data->ui.gy.raw[i]);
cparata	1:fe40aec6e97a	11458	break;
cparata	1:fe40aec6e97a	11459	case LSM6DSOX_GY_UI_125dps:
cparata	1:fe40aec6e97a	11460	data->ui.gy.mdps[i] = lsm6dsox_from_fs125_to_mdps(data->ui.gy.raw[i]);
cparata	1:fe40aec6e97a	11461	break;
cparata	1:fe40aec6e97a	11462	case LSM6DSOX_GY_UI_500dps:
cparata	1:fe40aec6e97a	11463	data->ui.gy.mdps[i] = lsm6dsox_from_fs500_to_mdps(data->ui.gy.raw[i]);
cparata	1:fe40aec6e97a	11464	break;
cparata	1:fe40aec6e97a	11465	case LSM6DSOX_GY_UI_1000dps:
cparata	1:fe40aec6e97a	11466	data->ui.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(data->ui.gy.raw[i]);
cparata	1:fe40aec6e97a	11467	break;
cparata	1:fe40aec6e97a	11468	case LSM6DSOX_GY_UI_2000dps:
cparata	1:fe40aec6e97a	11469	data->ui.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(data->ui.gy.raw[i]);
cparata	1:fe40aec6e97a	11470	break;
cparata	1:fe40aec6e97a	11471	default:
cparata	1:fe40aec6e97a	11472	data->ui.gy.mdps[i] = 0.0f;
cparata	1:fe40aec6e97a	11473	break;
cparata	1:fe40aec6e97a	11474	}
cparata	1:fe40aec6e97a	11475	}
cparata	1:fe40aec6e97a	11476
cparata	1:fe40aec6e97a	11477	/* acceleration conversion */
cparata	1:fe40aec6e97a	11478	for (i = 0U; i < 3U; i++) {
cparata	1:fe40aec6e97a	11479	data->ui.xl.raw[i] = (int16_t)buff[j+1U];
cparata	1:fe40aec6e97a	11480	data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
cparata	1:fe40aec6e97a	11481	j+=2U;
cparata	1:fe40aec6e97a	11482	switch ( md->ui.xl.fs ) {
cparata	1:fe40aec6e97a	11483	case LSM6DSOX_XL_UI_2g:
cparata	1:fe40aec6e97a	11484	data->ui.xl.mg[i] =lsm6dsox_from_fs2_to_mg(data->ui.xl.raw[i]);
cparata	1:fe40aec6e97a	11485	break;
cparata	1:fe40aec6e97a	11486	case LSM6DSOX_XL_UI_4g:
cparata	1:fe40aec6e97a	11487	data->ui.xl.mg[i] =lsm6dsox_from_fs4_to_mg(data->ui.xl.raw[i]);
cparata	1:fe40aec6e97a	11488	break;
cparata	1:fe40aec6e97a	11489	case LSM6DSOX_XL_UI_8g:
cparata	1:fe40aec6e97a	11490	data->ui.xl.mg[i] =lsm6dsox_from_fs8_to_mg(data->ui.xl.raw[i]);
cparata	1:fe40aec6e97a	11491	break;
cparata	1:fe40aec6e97a	11492	case LSM6DSOX_XL_UI_16g:
cparata	1:fe40aec6e97a	11493	data->ui.xl.mg[i] =lsm6dsox_from_fs16_to_mg(data->ui.xl.raw[i]);
cparata	1:fe40aec6e97a	11494	break;
cparata	1:fe40aec6e97a	11495	default:
cparata	1:fe40aec6e97a	11496	data->ui.xl.mg[i] = 0.0f;
cparata	1:fe40aec6e97a	11497	break;
cparata	1:fe40aec6e97a	11498	}
cparata	1:fe40aec6e97a	11499
cparata	1:fe40aec6e97a	11500	}
cparata	1:fe40aec6e97a	11501
cparata	1:fe40aec6e97a	11502	/* read data from ois chain */
cparata	1:fe40aec6e97a	11503	if (aux_ctx != NULL) {
cparata	1:fe40aec6e97a	11504	if (ret == 0) {
cparata	1:fe40aec6e97a	11505	ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 12);
cparata	1:fe40aec6e97a	11506	}
cparata	1:fe40aec6e97a	11507	}
cparata	1:fe40aec6e97a	11508	else {
cparata	1:fe40aec6e97a	11509	if ((ctx != NULL) && (md->ois.ctrl_md == LSM6DSOX_OIS_ONLY_UI)) {
cparata	1:fe40aec6e97a	11510	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 12);
cparata	1:fe40aec6e97a	11511	}
cparata	1:fe40aec6e97a	11512	}
cparata	1:fe40aec6e97a	11513	j = 0;
cparata	1:fe40aec6e97a	11514
cparata	1:fe40aec6e97a	11515	/* ois angular rate conversion */
cparata	1:fe40aec6e97a	11516	for (i = 0U; i < 3U; i++) {
cparata	1:fe40aec6e97a	11517	data->ois.gy.raw[i] = (int16_t) buff[j+1U];
cparata	1:fe40aec6e97a	11518	data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j];
cparata	1:fe40aec6e97a	11519	j+=2U;
cparata	1:fe40aec6e97a	11520	switch ( md->ois.gy.fs ) {
cparata	1:fe40aec6e97a	11521	case LSM6DSOX_GY_UI_250dps:
cparata	1:fe40aec6e97a	11522	data->ois.gy.mdps[i] = lsm6dsox_from_fs250_to_mdps(data->ois.gy.raw[i]);
cparata	1:fe40aec6e97a	11523	break;
cparata	1:fe40aec6e97a	11524	case LSM6DSOX_GY_UI_125dps:
cparata	1:fe40aec6e97a	11525	data->ois.gy.mdps[i] = lsm6dsox_from_fs125_to_mdps(data->ois.gy.raw[i]);
cparata	1:fe40aec6e97a	11526	break;
cparata	1:fe40aec6e97a	11527	case LSM6DSOX_GY_UI_500dps:
cparata	1:fe40aec6e97a	11528	data->ois.gy.mdps[i] = lsm6dsox_from_fs500_to_mdps(data->ois.gy.raw[i]);
cparata	1:fe40aec6e97a	11529	break;
cparata	1:fe40aec6e97a	11530	case LSM6DSOX_GY_UI_1000dps:
cparata	1:fe40aec6e97a	11531	data->ois.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(data->ois.gy.raw[i]);
cparata	1:fe40aec6e97a	11532	break;
cparata	1:fe40aec6e97a	11533	case LSM6DSOX_GY_UI_2000dps:
cparata	1:fe40aec6e97a	11534	data->ois.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(data->ois.gy.raw[i]);
cparata	1:fe40aec6e97a	11535	break;
cparata	1:fe40aec6e97a	11536	default:
cparata	1:fe40aec6e97a	11537	data->ois.gy.mdps[i] = 0.0f;
cparata	1:fe40aec6e97a	11538	break;
cparata	1:fe40aec6e97a	11539	}
cparata	1:fe40aec6e97a	11540	}
cparata	1:fe40aec6e97a	11541
cparata	1:fe40aec6e97a	11542	/* ois acceleration conversion */
cparata	1:fe40aec6e97a	11543	for (i = 0U; i < 3U; i++) {
cparata	1:fe40aec6e97a	11544	data->ois.xl.raw[i] = (int16_t) buff[j+1U];
cparata	1:fe40aec6e97a	11545	data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j];
cparata	1:fe40aec6e97a	11546	j+=2U;
cparata	1:fe40aec6e97a	11547	switch ( md->ois.xl.fs ) {
cparata	1:fe40aec6e97a	11548	case LSM6DSOX_XL_UI_2g:
cparata	1:fe40aec6e97a	11549	data->ois.xl.mg[i] =lsm6dsox_from_fs2_to_mg(data->ois.xl.raw[i]);
cparata	1:fe40aec6e97a	11550	break;
cparata	1:fe40aec6e97a	11551	case LSM6DSOX_XL_UI_4g:
cparata	1:fe40aec6e97a	11552	data->ois.xl.mg[i] =lsm6dsox_from_fs4_to_mg(data->ois.xl.raw[i]);
cparata	1:fe40aec6e97a	11553	break;
cparata	1:fe40aec6e97a	11554	case LSM6DSOX_XL_UI_8g:
cparata	1:fe40aec6e97a	11555	data->ois.xl.mg[i] =lsm6dsox_from_fs8_to_mg(data->ois.xl.raw[i]);
cparata	1:fe40aec6e97a	11556	break;
cparata	1:fe40aec6e97a	11557	case LSM6DSOX_XL_UI_16g:
cparata	1:fe40aec6e97a	11558	data->ois.xl.mg[i] =lsm6dsox_from_fs16_to_mg(data->ois.xl.raw[i]);
cparata	1:fe40aec6e97a	11559	break;
cparata	1:fe40aec6e97a	11560	default:
cparata	1:fe40aec6e97a	11561	data->ois.xl.mg[i] = 0.0f;
cparata	1:fe40aec6e97a	11562	break;
cparata	1:fe40aec6e97a	11563	}
cparata	1:fe40aec6e97a	11564	}
cparata	1:fe40aec6e97a	11565
cparata	1:fe40aec6e97a	11566	return ret;
cparata	1:fe40aec6e97a	11567	}
cparata	1:fe40aec6e97a	11568
cparata	1:fe40aec6e97a	11569	/**
cparata	1:fe40aec6e97a	11570	* @brief Embedded functions.[set]
cparata	1:fe40aec6e97a	11571	*
cparata	1:fe40aec6e97a	11572	* @param ctx read / write interface definitions
cparata	1:fe40aec6e97a	11573	* @param val change the values of registers
cparata	1:fe40aec6e97a	11574	* EMB_FUNC_EN_A e EMB_FUNC_EN_B.
cparata	1:fe40aec6e97a	11575	*
cparata	1:fe40aec6e97a	11576	*/
cparata	1:fe40aec6e97a	11577	int32_t lsm6dsox_embedded_sens_set(lsm6dsox_ctx_t *ctx,
cparata	1:fe40aec6e97a	11578	lsm6dsox_emb_sens_t *val)
cparata	1:fe40aec6e97a	11579	{
cparata	1:fe40aec6e97a	11580	lsm6dsox_emb_func_en_a_t emb_func_en_a;
cparata	1:fe40aec6e97a	11581	lsm6dsox_emb_func_en_b_t emb_func_en_b;
cparata	1:fe40aec6e97a	11582	int32_t ret;
cparata	1:fe40aec6e97a	11583
cparata	1:fe40aec6e97a	11584	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	11585	if (ret == 0) {
cparata	1:fe40aec6e97a	11586	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
cparata	1:fe40aec6e97a	11587	(uint8_t*)&emb_func_en_a, 1);
cparata	1:fe40aec6e97a	11588	}
cparata	1:fe40aec6e97a	11589	if (ret == 0) {
cparata	1:fe40aec6e97a	11590	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata	1:fe40aec6e97a	11591	(uint8_t*)&emb_func_en_b, 1);
cparata	1:fe40aec6e97a	11592
cparata	1:fe40aec6e97a	11593	emb_func_en_b.mlc_en = val->mlc;
cparata	1:fe40aec6e97a	11594	emb_func_en_b.fsm_en = val->fsm;
cparata	1:fe40aec6e97a	11595	emb_func_en_a.tilt_en = val->tilt;
cparata	1:fe40aec6e97a	11596	emb_func_en_a.pedo_en = val->step;
cparata	1:fe40aec6e97a	11597	emb_func_en_a.sign_motion_en = val->sig_mot;
cparata	1:fe40aec6e97a	11598	emb_func_en_b.fifo_compr_en = val->fifo_compr;
cparata	1:fe40aec6e97a	11599
cparata	1:fe40aec6e97a	11600	}
cparata	1:fe40aec6e97a	11601	if (ret == 0) {
cparata	1:fe40aec6e97a	11602	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
cparata	1:fe40aec6e97a	11603	(uint8_t*)&emb_func_en_a, 1);
cparata	1:fe40aec6e97a	11604	}
cparata	1:fe40aec6e97a	11605	if (ret == 0) {
cparata	1:fe40aec6e97a	11606	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata	1:fe40aec6e97a	11607	(uint8_t*)&emb_func_en_b, 1);
cparata	1:fe40aec6e97a	11608	}
cparata	1:fe40aec6e97a	11609	if (ret == 0) {
cparata	1:fe40aec6e97a	11610	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	11611	}
cparata	1:fe40aec6e97a	11612
cparata	1:fe40aec6e97a	11613	return ret;
cparata	1:fe40aec6e97a	11614	}
cparata	1:fe40aec6e97a	11615
cparata	1:fe40aec6e97a	11616	/**
cparata	1:fe40aec6e97a	11617	* @brief Embedded functions.[get]
cparata	1:fe40aec6e97a	11618	*
cparata	1:fe40aec6e97a	11619	* @param ctx read / write interface definitions
cparata	1:fe40aec6e97a	11620	* @param val get the values of registers
cparata	1:fe40aec6e97a	11621	* EMB_FUNC_EN_A e EMB_FUNC_EN_B.
cparata	1:fe40aec6e97a	11622	*
cparata	1:fe40aec6e97a	11623	*/
cparata	1:fe40aec6e97a	11624	int32_t lsm6dsox_embedded_sens_get(lsm6dsox_ctx_t *ctx,
cparata	1:fe40aec6e97a	11625	lsm6dsox_emb_sens_t *emb_sens)
cparata	1:fe40aec6e97a	11626	{
cparata	1:fe40aec6e97a	11627	lsm6dsox_emb_func_en_a_t emb_func_en_a;
cparata	1:fe40aec6e97a	11628	lsm6dsox_emb_func_en_b_t emb_func_en_b;
cparata	1:fe40aec6e97a	11629	int32_t ret;
cparata	1:fe40aec6e97a	11630
cparata	1:fe40aec6e97a	11631	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	11632	if (ret == 0) {
cparata	1:fe40aec6e97a	11633	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
cparata	1:fe40aec6e97a	11634	(uint8_t*)&emb_func_en_a, 1);
cparata	1:fe40aec6e97a	11635	}
cparata	1:fe40aec6e97a	11636	if (ret == 0) {
cparata	1:fe40aec6e97a	11637	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata	1:fe40aec6e97a	11638	(uint8_t*)&emb_func_en_b, 1);
cparata	1:fe40aec6e97a	11639
cparata	1:fe40aec6e97a	11640	emb_sens->mlc = emb_func_en_b.mlc_en;
cparata	1:fe40aec6e97a	11641	emb_sens->fsm = emb_func_en_b.fsm_en;
cparata	1:fe40aec6e97a	11642	emb_sens->tilt = emb_func_en_a.tilt_en;
cparata	1:fe40aec6e97a	11643	emb_sens->step = emb_func_en_a.pedo_en;
cparata	1:fe40aec6e97a	11644	emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
cparata	1:fe40aec6e97a	11645	emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
cparata	1:fe40aec6e97a	11646
cparata	1:fe40aec6e97a	11647	}
cparata	1:fe40aec6e97a	11648	if (ret == 0) {
cparata	1:fe40aec6e97a	11649	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	11650	}
cparata	1:fe40aec6e97a	11651
cparata	1:fe40aec6e97a	11652	return ret;
cparata	1:fe40aec6e97a	11653	}
cparata	1:fe40aec6e97a	11654
cparata	1:fe40aec6e97a	11655	/**
cparata	1:fe40aec6e97a	11656	* @brief turn off all embedded functions.[get]
cparata	1:fe40aec6e97a	11657	*
cparata	1:fe40aec6e97a	11658	* @param ctx read / write interface definitions
cparata	1:fe40aec6e97a	11659	* @param val get the values of registers
cparata	1:fe40aec6e97a	11660	* EMB_FUNC_EN_A e EMB_FUNC_EN_B.
cparata	1:fe40aec6e97a	11661	*
cparata	1:fe40aec6e97a	11662	*/
cparata	1:fe40aec6e97a	11663	int32_t lsm6dsox_embedded_sens_off(lsm6dsox_ctx_t *ctx)
cparata	1:fe40aec6e97a	11664	{
cparata	1:fe40aec6e97a	11665	lsm6dsox_emb_func_en_a_t emb_func_en_a;
cparata	1:fe40aec6e97a	11666	lsm6dsox_emb_func_en_b_t emb_func_en_b;
cparata	1:fe40aec6e97a	11667	int32_t ret;
cparata	1:fe40aec6e97a	11668
cparata	1:fe40aec6e97a	11669	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata	1:fe40aec6e97a	11670	if (ret == 0) {
cparata	1:fe40aec6e97a	11671	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
cparata	1:fe40aec6e97a	11672	(uint8_t*)&emb_func_en_a, 1);
cparata	1:fe40aec6e97a	11673	}
cparata	1:fe40aec6e97a	11674	if (ret == 0) {
cparata	1:fe40aec6e97a	11675	ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata	1:fe40aec6e97a	11676	(uint8_t*)&emb_func_en_b, 1);
cparata	1:fe40aec6e97a	11677
cparata	1:fe40aec6e97a	11678	emb_func_en_b.mlc_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	11679	emb_func_en_b.fsm_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	11680	emb_func_en_a.tilt_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	11681	emb_func_en_a.pedo_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	11682	emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	11683	emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
cparata	1:fe40aec6e97a	11684
cparata	1:fe40aec6e97a	11685	}
cparata	1:fe40aec6e97a	11686	if (ret == 0) {
cparata	1:fe40aec6e97a	11687	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
cparata	1:fe40aec6e97a	11688	(uint8_t*)&emb_func_en_a, 1);
cparata	1:fe40aec6e97a	11689	}
cparata	1:fe40aec6e97a	11690	if (ret == 0) {
cparata	1:fe40aec6e97a	11691	ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata	1:fe40aec6e97a	11692	(uint8_t*)&emb_func_en_b, 1);
cparata	1:fe40aec6e97a	11693	}
cparata	1:fe40aec6e97a	11694	if (ret == 0) {
cparata	1:fe40aec6e97a	11695	ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata	1:fe40aec6e97a	11696	}
cparata	1:fe40aec6e97a	11697
cparata	1:fe40aec6e97a	11698	return ret;
cparata	1:fe40aec6e97a	11699	}
cparata	1:fe40aec6e97a	11700
cparata	1:fe40aec6e97a	11701	/**
cparata	1:fe40aec6e97a	11702	* @}
cparata	1:fe40aec6e97a	11703	*
cparata	1:fe40aec6e97a	11704	*/
cparata	1:fe40aec6e97a	11705
cparata	1:fe40aec6e97a	11706	/**
cparata	0:f27ce43dee4f	11707	* @}
cparata	0:f27ce43dee4f	11708	*
cparata	0:f27ce43dee4f	11709	*/
cparata	0:f27ce43dee4f	11710
cparata	0:f27ce43dee4f	11711	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	10 Jul 2019
Imports:	13
Forks:	0
Commits:	6
Dependents:	0
Dependencies:	2
Followers:	403

The code in this repository is Apache licensed.

lsm6dsox_reg.c@1:fe40aec6e97a, 2020-10-29 (annotated)

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