ST / LSM6DSOX

iNEMO inertial module: 3D accelerometer and 3D gyroscope.

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

lsm6dsox_reg.c@0:f27ce43dee4f, 2019-07-10 (annotated)

Committer:
cparata
Date:
Wed Jul 10 12:08:49 2019 +0000
Revision:
0:f27ce43dee4f
Child:
1:fe40aec6e97a
First release of LSM6DSOX mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cparata 0:f27ce43dee4f 1 /*
cparata 0:f27ce43dee4f 2 ******************************************************************************
cparata 0:f27ce43dee4f 3 * @file lsm6dsox_reg.c
cparata 0:f27ce43dee4f 4 * @author Sensor Solutions Software Team
cparata 0:f27ce43dee4f 5 * @brief LSM6DSOX driver file
cparata 0:f27ce43dee4f 6 ******************************************************************************
cparata 0:f27ce43dee4f 7 * @attention
cparata 0:f27ce43dee4f 8 *
cparata 0:f27ce43dee4f 9 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
cparata 0:f27ce43dee4f 10 * All rights reserved.</center></h2>
cparata 0:f27ce43dee4f 11 *
cparata 0:f27ce43dee4f 12 * This software component is licensed by ST under BSD 3-Clause license,
cparata 0:f27ce43dee4f 13 * the "License"; You may not use this file except in compliance with the
cparata 0:f27ce43dee4f 14 * License. You may obtain a copy of the License at:
cparata 0:f27ce43dee4f 15 * opensource.org/licenses/BSD-3-Clause
cparata 0:f27ce43dee4f 16 *
cparata 0:f27ce43dee4f 17 ******************************************************************************
cparata 0:f27ce43dee4f 18 */
cparata 0:f27ce43dee4f 19
cparata 0:f27ce43dee4f 20 #include "lsm6dsox_reg.h"
cparata 0:f27ce43dee4f 21
cparata 0:f27ce43dee4f 22 /**
cparata 0:f27ce43dee4f 23 * @defgroup LSM6DSOX
cparata 0:f27ce43dee4f 24 * @brief This file provides a set of functions needed to drive the
cparata 0:f27ce43dee4f 25 * lsm6dsox enhanced inertial module.
cparata 0:f27ce43dee4f 26 * @{
cparata 0:f27ce43dee4f 27 *
cparata 0:f27ce43dee4f 28 */
cparata 0:f27ce43dee4f 29
cparata 0:f27ce43dee4f 30 /**
cparata 0:f27ce43dee4f 31 * @defgroup LSM6DSOX_Interfaces_Functions
cparata 0:f27ce43dee4f 32 * @brief This section provide a set of functions used to read and
cparata 0:f27ce43dee4f 33 * write a generic register of the device.
cparata 0:f27ce43dee4f 34 * MANDATORY: return 0 -> no Error.
cparata 0:f27ce43dee4f 35 * @{
cparata 0:f27ce43dee4f 36 *
cparata 0:f27ce43dee4f 37 */
cparata 0:f27ce43dee4f 38
cparata 0:f27ce43dee4f 39 /**
cparata 0:f27ce43dee4f 40 * @brief Read generic device register
cparata 0:f27ce43dee4f 41 *
cparata 0:f27ce43dee4f 42 * @param ctx read / write interface definitions(ptr)
cparata 0:f27ce43dee4f 43 * @param reg register to read
cparata 0:f27ce43dee4f 44 * @param data pointer to buffer that store the data read(ptr)
cparata 0:f27ce43dee4f 45 * @param len number of consecutive register to read
cparata 0:f27ce43dee4f 46 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:f27ce43dee4f 47 *
cparata 0:f27ce43dee4f 48 */
cparata 0:f27ce43dee4f 49 int32_t lsm6dsox_read_reg(lsm6dsox_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata 0:f27ce43dee4f 50 uint16_t len)
cparata 0:f27ce43dee4f 51 {
cparata 0:f27ce43dee4f 52 int32_t ret;
cparata 0:f27ce43dee4f 53 ret = ctx->read_reg(ctx->handle, reg, data, len);
cparata 0:f27ce43dee4f 54 return ret;
cparata 0:f27ce43dee4f 55 }
cparata 0:f27ce43dee4f 56
cparata 0:f27ce43dee4f 57 /**
cparata 0:f27ce43dee4f 58 * @brief Write generic device register
cparata 0:f27ce43dee4f 59 *
cparata 0:f27ce43dee4f 60 * @param ctx read / write interface definitions(ptr)
cparata 0:f27ce43dee4f 61 * @param reg register to write
cparata 0:f27ce43dee4f 62 * @param data pointer to data to write in register reg(ptr)
cparata 0:f27ce43dee4f 63 * @param len number of consecutive register to write
cparata 0:f27ce43dee4f 64 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:f27ce43dee4f 65 *
cparata 0:f27ce43dee4f 66 */
cparata 0:f27ce43dee4f 67 int32_t lsm6dsox_write_reg(lsm6dsox_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata 0:f27ce43dee4f 68 uint16_t len)
cparata 0:f27ce43dee4f 69 {
cparata 0:f27ce43dee4f 70 int32_t ret;
cparata 0:f27ce43dee4f 71 ret = ctx->write_reg(ctx->handle, reg, data, len);
cparata 0:f27ce43dee4f 72 return ret;
cparata 0:f27ce43dee4f 73 }
cparata 0:f27ce43dee4f 74
cparata 0:f27ce43dee4f 75 /**
cparata 0:f27ce43dee4f 76 * @}
cparata 0:f27ce43dee4f 77 *
cparata 0:f27ce43dee4f 78 */
cparata 0:f27ce43dee4f 79
cparata 0:f27ce43dee4f 80 /**
cparata 0:f27ce43dee4f 81 * @defgroup LSM6DSOX_Sensitivity
cparata 0:f27ce43dee4f 82 * @brief These functions convert raw-data into engineering units.
cparata 0:f27ce43dee4f 83 * @{
cparata 0:f27ce43dee4f 84 *
cparata 0:f27ce43dee4f 85 */
cparata 0:f27ce43dee4f 86 float_t lsm6dsox_from_fs2_to_mg(int16_t lsb)
cparata 0:f27ce43dee4f 87 {
cparata 0:f27ce43dee4f 88 return ((float_t)lsb) * 0.061f;
cparata 0:f27ce43dee4f 89 }
cparata 0:f27ce43dee4f 90
cparata 0:f27ce43dee4f 91 float_t lsm6dsox_from_fs4_to_mg(int16_t lsb)
cparata 0:f27ce43dee4f 92 {
cparata 0:f27ce43dee4f 93 return ((float_t)lsb) * 0.122f;
cparata 0:f27ce43dee4f 94 }
cparata 0:f27ce43dee4f 95
cparata 0:f27ce43dee4f 96 float_t lsm6dsox_from_fs8_to_mg(int16_t lsb)
cparata 0:f27ce43dee4f 97 {
cparata 0:f27ce43dee4f 98 return ((float_t)lsb) * 0.244f;
cparata 0:f27ce43dee4f 99 }
cparata 0:f27ce43dee4f 100
cparata 0:f27ce43dee4f 101 float_t lsm6dsox_from_fs16_to_mg(int16_t lsb)
cparata 0:f27ce43dee4f 102 {
cparata 0:f27ce43dee4f 103 return ((float_t)lsb) *0.488f;
cparata 0:f27ce43dee4f 104 }
cparata 0:f27ce43dee4f 105
cparata 0:f27ce43dee4f 106 float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb)
cparata 0:f27ce43dee4f 107 {
cparata 0:f27ce43dee4f 108 return ((float_t)lsb) *4.375f;
cparata 0:f27ce43dee4f 109 }
cparata 0:f27ce43dee4f 110
cparata 0:f27ce43dee4f 111 float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb)
cparata 0:f27ce43dee4f 112 {
cparata 0:f27ce43dee4f 113 return ((float_t)lsb) *17.50f;
cparata 0:f27ce43dee4f 114 }
cparata 0:f27ce43dee4f 115
cparata 0:f27ce43dee4f 116 float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb)
cparata 0:f27ce43dee4f 117 {
cparata 0:f27ce43dee4f 118 return ((float_t)lsb) *8.750f;
cparata 0:f27ce43dee4f 119 }
cparata 0:f27ce43dee4f 120
cparata 0:f27ce43dee4f 121 float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb)
cparata 0:f27ce43dee4f 122 {
cparata 0:f27ce43dee4f 123 return ((float_t)lsb) *35.0f;
cparata 0:f27ce43dee4f 124 }
cparata 0:f27ce43dee4f 125
cparata 0:f27ce43dee4f 126 float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb)
cparata 0:f27ce43dee4f 127 {
cparata 0:f27ce43dee4f 128 return ((float_t)lsb) *70.0f;
cparata 0:f27ce43dee4f 129 }
cparata 0:f27ce43dee4f 130
cparata 0:f27ce43dee4f 131 float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb)
cparata 0:f27ce43dee4f 132 {
cparata 0:f27ce43dee4f 133 return (((float_t)lsb / 256.0f) + 25.0f);
cparata 0:f27ce43dee4f 134 }
cparata 0:f27ce43dee4f 135
cparata 0:f27ce43dee4f 136 float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb)
cparata 0:f27ce43dee4f 137 {
cparata 0:f27ce43dee4f 138 return ((float_t)lsb * 25000.0f);
cparata 0:f27ce43dee4f 139 }
cparata 0:f27ce43dee4f 140
cparata 0:f27ce43dee4f 141 /**
cparata 0:f27ce43dee4f 142 * @}
cparata 0:f27ce43dee4f 143 *
cparata 0:f27ce43dee4f 144 */
cparata 0:f27ce43dee4f 145
cparata 0:f27ce43dee4f 146 /**
cparata 0:f27ce43dee4f 147 * @defgroup LSM6DSOX_Data_Generation
cparata 0:f27ce43dee4f 148 * @brief This section groups all the functions concerning
cparata 0:f27ce43dee4f 149 * data generation.
cparata 0:f27ce43dee4f 150 *
cparata 0:f27ce43dee4f 151 */
cparata 0:f27ce43dee4f 152
cparata 0:f27ce43dee4f 153 /**
cparata 0:f27ce43dee4f 154 * @brief Accelerometer full-scale selection.[set]
cparata 0:f27ce43dee4f 155 *
cparata 0:f27ce43dee4f 156 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 157 * @param val change the values of fs_xl in reg CTRL1_XL
cparata 0:f27ce43dee4f 158 *
cparata 0:f27ce43dee4f 159 */
cparata 0:f27ce43dee4f 160 int32_t lsm6dsox_xl_full_scale_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 161 lsm6dsox_fs_xl_t val)
cparata 0:f27ce43dee4f 162 {
cparata 0:f27ce43dee4f 163 lsm6dsox_ctrl1_xl_t reg;
cparata 0:f27ce43dee4f 164 int32_t ret;
cparata 0:f27ce43dee4f 165
cparata 0:f27ce43dee4f 166 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 167 if (ret == 0) {
cparata 0:f27ce43dee4f 168 reg.fs_xl = (uint8_t) val;
cparata 0:f27ce43dee4f 169 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 170 }
cparata 0:f27ce43dee4f 171 return ret;
cparata 0:f27ce43dee4f 172 }
cparata 0:f27ce43dee4f 173
cparata 0:f27ce43dee4f 174 /**
cparata 0:f27ce43dee4f 175 * @brief Accelerometer full-scale selection.[get]
cparata 0:f27ce43dee4f 176 *
cparata 0:f27ce43dee4f 177 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 178 * @param val Get the values of fs_xl in reg CTRL1_XL
cparata 0:f27ce43dee4f 179 *
cparata 0:f27ce43dee4f 180 */
cparata 0:f27ce43dee4f 181 int32_t lsm6dsox_xl_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_xl_t *val)
cparata 0:f27ce43dee4f 182 {
cparata 0:f27ce43dee4f 183 lsm6dsox_ctrl1_xl_t reg;
cparata 0:f27ce43dee4f 184 int32_t ret;
cparata 0:f27ce43dee4f 185
cparata 0:f27ce43dee4f 186 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 187 switch (reg.fs_xl) {
cparata 0:f27ce43dee4f 188 case LSM6DSOX_2g:
cparata 0:f27ce43dee4f 189 *val = LSM6DSOX_2g;
cparata 0:f27ce43dee4f 190 break;
cparata 0:f27ce43dee4f 191 case LSM6DSOX_16g:
cparata 0:f27ce43dee4f 192 *val = LSM6DSOX_16g;
cparata 0:f27ce43dee4f 193 break;
cparata 0:f27ce43dee4f 194 case LSM6DSOX_4g:
cparata 0:f27ce43dee4f 195 *val = LSM6DSOX_4g;
cparata 0:f27ce43dee4f 196 break;
cparata 0:f27ce43dee4f 197 case LSM6DSOX_8g:
cparata 0:f27ce43dee4f 198 *val = LSM6DSOX_8g;
cparata 0:f27ce43dee4f 199 break;
cparata 0:f27ce43dee4f 200 default:
cparata 0:f27ce43dee4f 201 *val = LSM6DSOX_2g;
cparata 0:f27ce43dee4f 202 break;
cparata 0:f27ce43dee4f 203 }
cparata 0:f27ce43dee4f 204
cparata 0:f27ce43dee4f 205 return ret;
cparata 0:f27ce43dee4f 206 }
cparata 0:f27ce43dee4f 207
cparata 0:f27ce43dee4f 208 /**
cparata 0:f27ce43dee4f 209 * @brief Accelerometer UI data rate selection.[set]
cparata 0:f27ce43dee4f 210 *
cparata 0:f27ce43dee4f 211 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 212 * @param val change the values of odr_xl in reg CTRL1_XL
cparata 0:f27ce43dee4f 213 *
cparata 0:f27ce43dee4f 214 */
cparata 0:f27ce43dee4f 215 int32_t lsm6dsox_xl_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t val)
cparata 0:f27ce43dee4f 216 {
cparata 0:f27ce43dee4f 217 lsm6dsox_ctrl1_xl_t reg;
cparata 0:f27ce43dee4f 218 int32_t ret;
cparata 0:f27ce43dee4f 219
cparata 0:f27ce43dee4f 220 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 221 if (ret == 0) {
cparata 0:f27ce43dee4f 222 reg.odr_xl = (uint8_t) val;
cparata 0:f27ce43dee4f 223 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 224 }
cparata 0:f27ce43dee4f 225 return ret;
cparata 0:f27ce43dee4f 226 }
cparata 0:f27ce43dee4f 227
cparata 0:f27ce43dee4f 228 /**
cparata 0:f27ce43dee4f 229 * @brief Accelerometer UI data rate selection.[get]
cparata 0:f27ce43dee4f 230 *
cparata 0:f27ce43dee4f 231 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 232 * @param val Get the values of odr_xl in reg CTRL1_XL
cparata 0:f27ce43dee4f 233 *
cparata 0:f27ce43dee4f 234 */
cparata 0:f27ce43dee4f 235 int32_t lsm6dsox_xl_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t *val)
cparata 0:f27ce43dee4f 236 {
cparata 0:f27ce43dee4f 237 lsm6dsox_ctrl1_xl_t reg;
cparata 0:f27ce43dee4f 238 int32_t ret;
cparata 0:f27ce43dee4f 239
cparata 0:f27ce43dee4f 240 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 241
cparata 0:f27ce43dee4f 242 switch (reg.odr_xl) {
cparata 0:f27ce43dee4f 243 case LSM6DSOX_XL_ODR_OFF:
cparata 0:f27ce43dee4f 244 *val = LSM6DSOX_XL_ODR_OFF;
cparata 0:f27ce43dee4f 245 break;
cparata 0:f27ce43dee4f 246 case LSM6DSOX_XL_ODR_12Hz5:
cparata 0:f27ce43dee4f 247 *val = LSM6DSOX_XL_ODR_12Hz5;
cparata 0:f27ce43dee4f 248 break;
cparata 0:f27ce43dee4f 249 case LSM6DSOX_XL_ODR_26Hz:
cparata 0:f27ce43dee4f 250 *val = LSM6DSOX_XL_ODR_26Hz;
cparata 0:f27ce43dee4f 251 break;
cparata 0:f27ce43dee4f 252 case LSM6DSOX_XL_ODR_52Hz:
cparata 0:f27ce43dee4f 253 *val = LSM6DSOX_XL_ODR_52Hz;
cparata 0:f27ce43dee4f 254 break;
cparata 0:f27ce43dee4f 255 case LSM6DSOX_XL_ODR_104Hz:
cparata 0:f27ce43dee4f 256 *val = LSM6DSOX_XL_ODR_104Hz;
cparata 0:f27ce43dee4f 257 break;
cparata 0:f27ce43dee4f 258 case LSM6DSOX_XL_ODR_208Hz:
cparata 0:f27ce43dee4f 259 *val = LSM6DSOX_XL_ODR_208Hz;
cparata 0:f27ce43dee4f 260 break;
cparata 0:f27ce43dee4f 261 case LSM6DSOX_XL_ODR_417Hz:
cparata 0:f27ce43dee4f 262 *val = LSM6DSOX_XL_ODR_417Hz;
cparata 0:f27ce43dee4f 263 break;
cparata 0:f27ce43dee4f 264 case LSM6DSOX_XL_ODR_833Hz:
cparata 0:f27ce43dee4f 265 *val = LSM6DSOX_XL_ODR_833Hz;
cparata 0:f27ce43dee4f 266 break;
cparata 0:f27ce43dee4f 267 case LSM6DSOX_XL_ODR_1667Hz:
cparata 0:f27ce43dee4f 268 *val = LSM6DSOX_XL_ODR_1667Hz;
cparata 0:f27ce43dee4f 269 break;
cparata 0:f27ce43dee4f 270 case LSM6DSOX_XL_ODR_3333Hz:
cparata 0:f27ce43dee4f 271 *val = LSM6DSOX_XL_ODR_3333Hz;
cparata 0:f27ce43dee4f 272 break;
cparata 0:f27ce43dee4f 273 case LSM6DSOX_XL_ODR_6667Hz:
cparata 0:f27ce43dee4f 274 *val = LSM6DSOX_XL_ODR_6667Hz;
cparata 0:f27ce43dee4f 275 break;
cparata 0:f27ce43dee4f 276 case LSM6DSOX_XL_ODR_6Hz5:
cparata 0:f27ce43dee4f 277 *val = LSM6DSOX_XL_ODR_6Hz5;
cparata 0:f27ce43dee4f 278 break;
cparata 0:f27ce43dee4f 279 default:
cparata 0:f27ce43dee4f 280 *val = LSM6DSOX_XL_ODR_OFF;
cparata 0:f27ce43dee4f 281 break;
cparata 0:f27ce43dee4f 282 }
cparata 0:f27ce43dee4f 283 return ret;
cparata 0:f27ce43dee4f 284 }
cparata 0:f27ce43dee4f 285
cparata 0:f27ce43dee4f 286 /**
cparata 0:f27ce43dee4f 287 * @brief Gyroscope UI chain full-scale selection.[set]
cparata 0:f27ce43dee4f 288 *
cparata 0:f27ce43dee4f 289 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 290 * @param val change the values of fs_g in reg CTRL2_G
cparata 0:f27ce43dee4f 291 *
cparata 0:f27ce43dee4f 292 */
cparata 0:f27ce43dee4f 293 int32_t lsm6dsox_gy_full_scale_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t val)
cparata 0:f27ce43dee4f 294 {
cparata 0:f27ce43dee4f 295 lsm6dsox_ctrl2_g_t reg;
cparata 0:f27ce43dee4f 296 int32_t ret;
cparata 0:f27ce43dee4f 297
cparata 0:f27ce43dee4f 298 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 299 if (ret == 0) {
cparata 0:f27ce43dee4f 300 reg.fs_g = (uint8_t) val;
cparata 0:f27ce43dee4f 301 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 302 }
cparata 0:f27ce43dee4f 303
cparata 0:f27ce43dee4f 304 return ret;
cparata 0:f27ce43dee4f 305 }
cparata 0:f27ce43dee4f 306
cparata 0:f27ce43dee4f 307 /**
cparata 0:f27ce43dee4f 308 * @brief Gyroscope UI chain full-scale selection.[get]
cparata 0:f27ce43dee4f 309 *
cparata 0:f27ce43dee4f 310 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 311 * @param val Get the values of fs_g in reg CTRL2_G
cparata 0:f27ce43dee4f 312 *
cparata 0:f27ce43dee4f 313 */
cparata 0:f27ce43dee4f 314 int32_t lsm6dsox_gy_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t *val)
cparata 0:f27ce43dee4f 315 {
cparata 0:f27ce43dee4f 316 lsm6dsox_ctrl2_g_t reg;
cparata 0:f27ce43dee4f 317 int32_t ret;
cparata 0:f27ce43dee4f 318
cparata 0:f27ce43dee4f 319 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 320 switch (reg.fs_g) {
cparata 0:f27ce43dee4f 321 case LSM6DSOX_250dps:
cparata 0:f27ce43dee4f 322 *val = LSM6DSOX_250dps;
cparata 0:f27ce43dee4f 323 break;
cparata 0:f27ce43dee4f 324 case LSM6DSOX_125dps:
cparata 0:f27ce43dee4f 325 *val = LSM6DSOX_125dps;
cparata 0:f27ce43dee4f 326 break;
cparata 0:f27ce43dee4f 327 case LSM6DSOX_500dps:
cparata 0:f27ce43dee4f 328 *val = LSM6DSOX_500dps;
cparata 0:f27ce43dee4f 329 break;
cparata 0:f27ce43dee4f 330 case LSM6DSOX_1000dps:
cparata 0:f27ce43dee4f 331 *val = LSM6DSOX_1000dps;
cparata 0:f27ce43dee4f 332 break;
cparata 0:f27ce43dee4f 333 case LSM6DSOX_2000dps:
cparata 0:f27ce43dee4f 334 *val = LSM6DSOX_2000dps;
cparata 0:f27ce43dee4f 335 break;
cparata 0:f27ce43dee4f 336 default:
cparata 0:f27ce43dee4f 337 *val = LSM6DSOX_250dps;
cparata 0:f27ce43dee4f 338 break;
cparata 0:f27ce43dee4f 339 }
cparata 0:f27ce43dee4f 340
cparata 0:f27ce43dee4f 341 return ret;
cparata 0:f27ce43dee4f 342 }
cparata 0:f27ce43dee4f 343
cparata 0:f27ce43dee4f 344 /**
cparata 0:f27ce43dee4f 345 * @brief Gyroscope UI data rate selection.[set]
cparata 0:f27ce43dee4f 346 *
cparata 0:f27ce43dee4f 347 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 348 * @param val change the values of odr_g in reg CTRL2_G
cparata 0:f27ce43dee4f 349 *
cparata 0:f27ce43dee4f 350 */
cparata 0:f27ce43dee4f 351 int32_t lsm6dsox_gy_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t val)
cparata 0:f27ce43dee4f 352 {
cparata 0:f27ce43dee4f 353 lsm6dsox_ctrl2_g_t reg;
cparata 0:f27ce43dee4f 354 int32_t ret;
cparata 0:f27ce43dee4f 355
cparata 0:f27ce43dee4f 356 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 357 if (ret == 0) {
cparata 0:f27ce43dee4f 358 reg.odr_g = (uint8_t) val;
cparata 0:f27ce43dee4f 359 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 360 }
cparata 0:f27ce43dee4f 361
cparata 0:f27ce43dee4f 362 return ret;
cparata 0:f27ce43dee4f 363 }
cparata 0:f27ce43dee4f 364
cparata 0:f27ce43dee4f 365 /**
cparata 0:f27ce43dee4f 366 * @brief Gyroscope UI data rate selection.[get]
cparata 0:f27ce43dee4f 367 *
cparata 0:f27ce43dee4f 368 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 369 * @param val Get the values of odr_g in reg CTRL2_G
cparata 0:f27ce43dee4f 370 *
cparata 0:f27ce43dee4f 371 */
cparata 0:f27ce43dee4f 372 int32_t lsm6dsox_gy_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t *val)
cparata 0:f27ce43dee4f 373 {
cparata 0:f27ce43dee4f 374 lsm6dsox_ctrl2_g_t reg;
cparata 0:f27ce43dee4f 375 int32_t ret;
cparata 0:f27ce43dee4f 376
cparata 0:f27ce43dee4f 377 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 378 switch (reg.odr_g) {
cparata 0:f27ce43dee4f 379 case LSM6DSOX_GY_ODR_OFF:
cparata 0:f27ce43dee4f 380 *val = LSM6DSOX_GY_ODR_OFF;
cparata 0:f27ce43dee4f 381 break;
cparata 0:f27ce43dee4f 382 case LSM6DSOX_GY_ODR_12Hz5:
cparata 0:f27ce43dee4f 383 *val = LSM6DSOX_GY_ODR_12Hz5;
cparata 0:f27ce43dee4f 384 break;
cparata 0:f27ce43dee4f 385 case LSM6DSOX_GY_ODR_26Hz:
cparata 0:f27ce43dee4f 386 *val = LSM6DSOX_GY_ODR_26Hz;
cparata 0:f27ce43dee4f 387 break;
cparata 0:f27ce43dee4f 388 case LSM6DSOX_GY_ODR_52Hz:
cparata 0:f27ce43dee4f 389 *val = LSM6DSOX_GY_ODR_52Hz;
cparata 0:f27ce43dee4f 390 break;
cparata 0:f27ce43dee4f 391 case LSM6DSOX_GY_ODR_104Hz:
cparata 0:f27ce43dee4f 392 *val = LSM6DSOX_GY_ODR_104Hz;
cparata 0:f27ce43dee4f 393 break;
cparata 0:f27ce43dee4f 394 case LSM6DSOX_GY_ODR_208Hz:
cparata 0:f27ce43dee4f 395 *val = LSM6DSOX_GY_ODR_208Hz;
cparata 0:f27ce43dee4f 396 break;
cparata 0:f27ce43dee4f 397 case LSM6DSOX_GY_ODR_417Hz:
cparata 0:f27ce43dee4f 398 *val = LSM6DSOX_GY_ODR_417Hz;
cparata 0:f27ce43dee4f 399 break;
cparata 0:f27ce43dee4f 400 case LSM6DSOX_GY_ODR_833Hz:
cparata 0:f27ce43dee4f 401 *val = LSM6DSOX_GY_ODR_833Hz;
cparata 0:f27ce43dee4f 402 break;
cparata 0:f27ce43dee4f 403 case LSM6DSOX_GY_ODR_1667Hz:
cparata 0:f27ce43dee4f 404 *val = LSM6DSOX_GY_ODR_1667Hz;
cparata 0:f27ce43dee4f 405 break;
cparata 0:f27ce43dee4f 406 case LSM6DSOX_GY_ODR_3333Hz:
cparata 0:f27ce43dee4f 407 *val = LSM6DSOX_GY_ODR_3333Hz;
cparata 0:f27ce43dee4f 408 break;
cparata 0:f27ce43dee4f 409 case LSM6DSOX_GY_ODR_6667Hz:
cparata 0:f27ce43dee4f 410 *val = LSM6DSOX_GY_ODR_6667Hz;
cparata 0:f27ce43dee4f 411 break;
cparata 0:f27ce43dee4f 412 default:
cparata 0:f27ce43dee4f 413 *val = LSM6DSOX_GY_ODR_OFF;
cparata 0:f27ce43dee4f 414 break;
cparata 0:f27ce43dee4f 415 }
cparata 0:f27ce43dee4f 416 return ret;
cparata 0:f27ce43dee4f 417 }
cparata 0:f27ce43dee4f 418
cparata 0:f27ce43dee4f 419 /**
cparata 0:f27ce43dee4f 420 * @brief Block data update.[set]
cparata 0:f27ce43dee4f 421 *
cparata 0:f27ce43dee4f 422 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 423 * @param val change the values of bdu in reg CTRL3_C
cparata 0:f27ce43dee4f 424 *
cparata 0:f27ce43dee4f 425 */
cparata 0:f27ce43dee4f 426 int32_t lsm6dsox_block_data_update_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 427 {
cparata 0:f27ce43dee4f 428 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 429 int32_t ret;
cparata 0:f27ce43dee4f 430
cparata 0:f27ce43dee4f 431 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 432 if (ret == 0) {
cparata 0:f27ce43dee4f 433 reg.bdu = val;
cparata 0:f27ce43dee4f 434 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 435 }
cparata 0:f27ce43dee4f 436 return ret;
cparata 0:f27ce43dee4f 437 }
cparata 0:f27ce43dee4f 438
cparata 0:f27ce43dee4f 439 /**
cparata 0:f27ce43dee4f 440 * @brief Block data update.[get]
cparata 0:f27ce43dee4f 441 *
cparata 0:f27ce43dee4f 442 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 443 * @param val change the values of bdu in reg CTRL3_C
cparata 0:f27ce43dee4f 444 *
cparata 0:f27ce43dee4f 445 */
cparata 0:f27ce43dee4f 446 int32_t lsm6dsox_block_data_update_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 447 {
cparata 0:f27ce43dee4f 448 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 449 int32_t ret;
cparata 0:f27ce43dee4f 450
cparata 0:f27ce43dee4f 451 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 452 *val = reg.bdu;
cparata 0:f27ce43dee4f 453
cparata 0:f27ce43dee4f 454 return ret;
cparata 0:f27ce43dee4f 455 }
cparata 0:f27ce43dee4f 456
cparata 0:f27ce43dee4f 457 /**
cparata 0:f27ce43dee4f 458 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata 0:f27ce43dee4f 459 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
cparata 0:f27ce43dee4f 460 *
cparata 0:f27ce43dee4f 461 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 462 * @param val change the values of usr_off_w in reg CTRL6_C
cparata 0:f27ce43dee4f 463 *
cparata 0:f27ce43dee4f 464 */
cparata 0:f27ce43dee4f 465 int32_t lsm6dsox_xl_offset_weight_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 466 lsm6dsox_usr_off_w_t val)
cparata 0:f27ce43dee4f 467 {
cparata 0:f27ce43dee4f 468 lsm6dsox_ctrl6_c_t reg;
cparata 0:f27ce43dee4f 469 int32_t ret;
cparata 0:f27ce43dee4f 470
cparata 0:f27ce43dee4f 471 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 472 if (ret == 0) {
cparata 0:f27ce43dee4f 473 reg.usr_off_w = (uint8_t)val;
cparata 0:f27ce43dee4f 474 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 475 }
cparata 0:f27ce43dee4f 476 return ret;
cparata 0:f27ce43dee4f 477 }
cparata 0:f27ce43dee4f 478
cparata 0:f27ce43dee4f 479 /**
cparata 0:f27ce43dee4f 480 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata 0:f27ce43dee4f 481 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
cparata 0:f27ce43dee4f 482 *
cparata 0:f27ce43dee4f 483 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 484 * @param val Get the values of usr_off_w in reg CTRL6_C
cparata 0:f27ce43dee4f 485 *
cparata 0:f27ce43dee4f 486 */
cparata 0:f27ce43dee4f 487 int32_t lsm6dsox_xl_offset_weight_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 488 lsm6dsox_usr_off_w_t *val)
cparata 0:f27ce43dee4f 489 {
cparata 0:f27ce43dee4f 490 lsm6dsox_ctrl6_c_t reg;
cparata 0:f27ce43dee4f 491 int32_t ret;
cparata 0:f27ce43dee4f 492
cparata 0:f27ce43dee4f 493 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 494
cparata 0:f27ce43dee4f 495 switch (reg.usr_off_w) {
cparata 0:f27ce43dee4f 496 case LSM6DSOX_LSb_1mg:
cparata 0:f27ce43dee4f 497 *val = LSM6DSOX_LSb_1mg;
cparata 0:f27ce43dee4f 498 break;
cparata 0:f27ce43dee4f 499 case LSM6DSOX_LSb_16mg:
cparata 0:f27ce43dee4f 500 *val = LSM6DSOX_LSb_16mg;
cparata 0:f27ce43dee4f 501 break;
cparata 0:f27ce43dee4f 502 default:
cparata 0:f27ce43dee4f 503 *val = LSM6DSOX_LSb_1mg;
cparata 0:f27ce43dee4f 504 break;
cparata 0:f27ce43dee4f 505 }
cparata 0:f27ce43dee4f 506 return ret;
cparata 0:f27ce43dee4f 507 }
cparata 0:f27ce43dee4f 508
cparata 0:f27ce43dee4f 509 /**
cparata 0:f27ce43dee4f 510 * @brief Accelerometer power mode.[set]
cparata 0:f27ce43dee4f 511 *
cparata 0:f27ce43dee4f 512 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 513 * @param val change the values of xl_hm_mode in
cparata 0:f27ce43dee4f 514 * reg CTRL6_C
cparata 0:f27ce43dee4f 515 *
cparata 0:f27ce43dee4f 516 */
cparata 0:f27ce43dee4f 517 int32_t lsm6dsox_xl_power_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 518 lsm6dsox_xl_hm_mode_t val)
cparata 0:f27ce43dee4f 519 {
cparata 0:f27ce43dee4f 520 lsm6dsox_ctrl5_c_t ctrl5_c;
cparata 0:f27ce43dee4f 521 lsm6dsox_ctrl6_c_t ctrl6_c;
cparata 0:f27ce43dee4f 522 int32_t ret;
cparata 0:f27ce43dee4f 523
cparata 0:f27ce43dee4f 524 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata 0:f27ce43dee4f 525 if (ret == 0) {
cparata 0:f27ce43dee4f 526 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
cparata 0:f27ce43dee4f 527 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata 0:f27ce43dee4f 528 }
cparata 0:f27ce43dee4f 529 if (ret == 0) {
cparata 0:f27ce43dee4f 530 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata 0:f27ce43dee4f 531 }
cparata 0:f27ce43dee4f 532 if (ret == 0) {
cparata 0:f27ce43dee4f 533 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
cparata 0:f27ce43dee4f 534 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata 0:f27ce43dee4f 535 }
cparata 0:f27ce43dee4f 536 return ret;
cparata 0:f27ce43dee4f 537 }
cparata 0:f27ce43dee4f 538
cparata 0:f27ce43dee4f 539 /**
cparata 0:f27ce43dee4f 540 * @brief Accelerometer power mode.[get]
cparata 0:f27ce43dee4f 541 *
cparata 0:f27ce43dee4f 542 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 543 * @param val Get the values of xl_hm_mode in reg CTRL6_C
cparata 0:f27ce43dee4f 544 *
cparata 0:f27ce43dee4f 545 */
cparata 0:f27ce43dee4f 546 int32_t lsm6dsox_xl_power_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 547 lsm6dsox_xl_hm_mode_t *val)
cparata 0:f27ce43dee4f 548 {
cparata 0:f27ce43dee4f 549 lsm6dsox_ctrl5_c_t ctrl5_c;
cparata 0:f27ce43dee4f 550 lsm6dsox_ctrl6_c_t ctrl6_c;
cparata 0:f27ce43dee4f 551 int32_t ret;
cparata 0:f27ce43dee4f 552
cparata 0:f27ce43dee4f 553 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata 0:f27ce43dee4f 554 if (ret == 0) {
cparata 0:f27ce43dee4f 555 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata 0:f27ce43dee4f 556 switch ( (ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode) {
cparata 0:f27ce43dee4f 557 case LSM6DSOX_HIGH_PERFORMANCE_MD:
cparata 0:f27ce43dee4f 558 *val = LSM6DSOX_HIGH_PERFORMANCE_MD;
cparata 0:f27ce43dee4f 559 break;
cparata 0:f27ce43dee4f 560 case LSM6DSOX_LOW_NORMAL_POWER_MD:
cparata 0:f27ce43dee4f 561 *val = LSM6DSOX_LOW_NORMAL_POWER_MD;
cparata 0:f27ce43dee4f 562 break;
cparata 0:f27ce43dee4f 563 case LSM6DSOX_ULTRA_LOW_POWER_MD:
cparata 0:f27ce43dee4f 564 *val = LSM6DSOX_ULTRA_LOW_POWER_MD;
cparata 0:f27ce43dee4f 565 break;
cparata 0:f27ce43dee4f 566 default:
cparata 0:f27ce43dee4f 567 *val = LSM6DSOX_HIGH_PERFORMANCE_MD;
cparata 0:f27ce43dee4f 568 break;
cparata 0:f27ce43dee4f 569 }
cparata 0:f27ce43dee4f 570 }
cparata 0:f27ce43dee4f 571 return ret;
cparata 0:f27ce43dee4f 572 }
cparata 0:f27ce43dee4f 573
cparata 0:f27ce43dee4f 574 /**
cparata 0:f27ce43dee4f 575 * @brief Operating mode for gyroscope.[set]
cparata 0:f27ce43dee4f 576 *
cparata 0:f27ce43dee4f 577 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 578 * @param val change the values of g_hm_mode in reg CTRL7_G
cparata 0:f27ce43dee4f 579 *
cparata 0:f27ce43dee4f 580 */
cparata 0:f27ce43dee4f 581 int32_t lsm6dsox_gy_power_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 582 lsm6dsox_g_hm_mode_t val)
cparata 0:f27ce43dee4f 583 {
cparata 0:f27ce43dee4f 584 lsm6dsox_ctrl7_g_t reg;
cparata 0:f27ce43dee4f 585 int32_t ret;
cparata 0:f27ce43dee4f 586
cparata 0:f27ce43dee4f 587 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 588 if (ret == 0) {
cparata 0:f27ce43dee4f 589 reg.g_hm_mode = (uint8_t)val;
cparata 0:f27ce43dee4f 590 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 591 }
cparata 0:f27ce43dee4f 592 return ret;
cparata 0:f27ce43dee4f 593 }
cparata 0:f27ce43dee4f 594
cparata 0:f27ce43dee4f 595 /**
cparata 0:f27ce43dee4f 596 * @brief Operating mode for gyroscope.[get]
cparata 0:f27ce43dee4f 597 *
cparata 0:f27ce43dee4f 598 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 599 * @param val Get the values of g_hm_mode in reg CTRL7_G
cparata 0:f27ce43dee4f 600 *
cparata 0:f27ce43dee4f 601 */
cparata 0:f27ce43dee4f 602 int32_t lsm6dsox_gy_power_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 603 lsm6dsox_g_hm_mode_t *val)
cparata 0:f27ce43dee4f 604 {
cparata 0:f27ce43dee4f 605 lsm6dsox_ctrl7_g_t reg;
cparata 0:f27ce43dee4f 606 int32_t ret;
cparata 0:f27ce43dee4f 607
cparata 0:f27ce43dee4f 608 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 609 switch (reg.g_hm_mode) {
cparata 0:f27ce43dee4f 610 case LSM6DSOX_GY_HIGH_PERFORMANCE:
cparata 0:f27ce43dee4f 611 *val = LSM6DSOX_GY_HIGH_PERFORMANCE;
cparata 0:f27ce43dee4f 612 break;
cparata 0:f27ce43dee4f 613 case LSM6DSOX_GY_NORMAL:
cparata 0:f27ce43dee4f 614 *val = LSM6DSOX_GY_NORMAL;
cparata 0:f27ce43dee4f 615 break;
cparata 0:f27ce43dee4f 616 default:
cparata 0:f27ce43dee4f 617 *val = LSM6DSOX_GY_HIGH_PERFORMANCE;
cparata 0:f27ce43dee4f 618 break;
cparata 0:f27ce43dee4f 619 }
cparata 0:f27ce43dee4f 620 return ret;
cparata 0:f27ce43dee4f 621 }
cparata 0:f27ce43dee4f 622
cparata 0:f27ce43dee4f 623 /**
cparata 0:f27ce43dee4f 624 * @brief Read all the interrupt flag of the device.[get]
cparata 0:f27ce43dee4f 625 *
cparata 0:f27ce43dee4f 626 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 627 * @param val registers ALL_INT_SRC; WAKE_UP_SRC;
cparata 0:f27ce43dee4f 628 * TAP_SRC; D6D_SRC; STATUS_REG;
cparata 0:f27ce43dee4f 629 * EMB_FUNC_STATUS; FSM_STATUS_A/B
cparata 0:f27ce43dee4f 630 *
cparata 0:f27ce43dee4f 631 */
cparata 0:f27ce43dee4f 632 int32_t lsm6dsox_all_sources_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 633 lsm6dsox_all_sources_t *val)
cparata 0:f27ce43dee4f 634 {
cparata 0:f27ce43dee4f 635 int32_t ret;
cparata 0:f27ce43dee4f 636
cparata 0:f27ce43dee4f 637 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_ALL_INT_SRC,
cparata 0:f27ce43dee4f 638 (uint8_t*)&val->all_int_src, 1);
cparata 0:f27ce43dee4f 639 if (ret == 0) {
cparata 0:f27ce43dee4f 640 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_SRC,
cparata 0:f27ce43dee4f 641 (uint8_t*)&val->wake_up_src, 1);
cparata 0:f27ce43dee4f 642 }
cparata 0:f27ce43dee4f 643 if (ret == 0) {
cparata 0:f27ce43dee4f 644 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_SRC,
cparata 0:f27ce43dee4f 645 (uint8_t*)&val->tap_src, 1);
cparata 0:f27ce43dee4f 646 }
cparata 0:f27ce43dee4f 647 if (ret == 0) {
cparata 0:f27ce43dee4f 648 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_D6D_SRC,
cparata 0:f27ce43dee4f 649 (uint8_t*)&val->d6d_src, 1);
cparata 0:f27ce43dee4f 650 }
cparata 0:f27ce43dee4f 651 if (ret == 0) {
cparata 0:f27ce43dee4f 652 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG,
cparata 0:f27ce43dee4f 653 (uint8_t*)&val->status_reg, 1);
cparata 0:f27ce43dee4f 654 }
cparata 0:f27ce43dee4f 655 if (ret == 0) {
cparata 0:f27ce43dee4f 656
cparata 0:f27ce43dee4f 657 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 658 }
cparata 0:f27ce43dee4f 659 if (ret == 0) {
cparata 0:f27ce43dee4f 660 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS,
cparata 0:f27ce43dee4f 661 (uint8_t*)&val->emb_func_status, 1);
cparata 0:f27ce43dee4f 662 }
cparata 0:f27ce43dee4f 663 if (ret == 0) {
cparata 0:f27ce43dee4f 664 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_STATUS_A,
cparata 0:f27ce43dee4f 665 (uint8_t*)&val->fsm_status_a, 1);
cparata 0:f27ce43dee4f 666 }
cparata 0:f27ce43dee4f 667 if (ret == 0) {
cparata 0:f27ce43dee4f 668 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_STATUS_B,
cparata 0:f27ce43dee4f 669 (uint8_t*)&val->fsm_status_b, 1);
cparata 0:f27ce43dee4f 670 }
cparata 0:f27ce43dee4f 671 if (ret == 0) {
cparata 0:f27ce43dee4f 672 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_STATUS,
cparata 0:f27ce43dee4f 673 (uint8_t*)&val->mlc_status, 1);
cparata 0:f27ce43dee4f 674 }
cparata 0:f27ce43dee4f 675 if (ret == 0) {
cparata 0:f27ce43dee4f 676 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 677 }
cparata 0:f27ce43dee4f 678
cparata 0:f27ce43dee4f 679 return ret;
cparata 0:f27ce43dee4f 680 }
cparata 0:f27ce43dee4f 681
cparata 0:f27ce43dee4f 682 /**
cparata 0:f27ce43dee4f 683 * @brief The STATUS_REG register is read by the primary interface.[get]
cparata 0:f27ce43dee4f 684 *
cparata 0:f27ce43dee4f 685 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 686 * @param val register STATUS_REG
cparata 0:f27ce43dee4f 687 *
cparata 0:f27ce43dee4f 688 */
cparata 0:f27ce43dee4f 689 int32_t lsm6dsox_status_reg_get(lsm6dsox_ctx_t *ctx, lsm6dsox_status_reg_t *val)
cparata 0:f27ce43dee4f 690 {
cparata 0:f27ce43dee4f 691 int32_t ret;
cparata 0:f27ce43dee4f 692 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*) val, 1);
cparata 0:f27ce43dee4f 693 return ret;
cparata 0:f27ce43dee4f 694 }
cparata 0:f27ce43dee4f 695
cparata 0:f27ce43dee4f 696 /**
cparata 0:f27ce43dee4f 697 * @brief Accelerometer new data available.[get]
cparata 0:f27ce43dee4f 698 *
cparata 0:f27ce43dee4f 699 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 700 * @param val change the values of xlda in reg STATUS_REG
cparata 0:f27ce43dee4f 701 *
cparata 0:f27ce43dee4f 702 */
cparata 0:f27ce43dee4f 703 int32_t lsm6dsox_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 704 {
cparata 0:f27ce43dee4f 705 lsm6dsox_status_reg_t reg;
cparata 0:f27ce43dee4f 706 int32_t ret;
cparata 0:f27ce43dee4f 707
cparata 0:f27ce43dee4f 708 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 709 *val = reg.xlda;
cparata 0:f27ce43dee4f 710
cparata 0:f27ce43dee4f 711 return ret;
cparata 0:f27ce43dee4f 712 }
cparata 0:f27ce43dee4f 713
cparata 0:f27ce43dee4f 714 /**
cparata 0:f27ce43dee4f 715 * @brief Gyroscope new data available.[get]
cparata 0:f27ce43dee4f 716 *
cparata 0:f27ce43dee4f 717 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 718 * @param val change the values of gda in reg STATUS_REG
cparata 0:f27ce43dee4f 719 *
cparata 0:f27ce43dee4f 720 */
cparata 0:f27ce43dee4f 721 int32_t lsm6dsox_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 722 {
cparata 0:f27ce43dee4f 723 lsm6dsox_status_reg_t reg;
cparata 0:f27ce43dee4f 724 int32_t ret;
cparata 0:f27ce43dee4f 725
cparata 0:f27ce43dee4f 726 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 727 *val = reg.gda;
cparata 0:f27ce43dee4f 728
cparata 0:f27ce43dee4f 729 return ret;
cparata 0:f27ce43dee4f 730 }
cparata 0:f27ce43dee4f 731
cparata 0:f27ce43dee4f 732 /**
cparata 0:f27ce43dee4f 733 * @brief Temperature new data available.[get]
cparata 0:f27ce43dee4f 734 *
cparata 0:f27ce43dee4f 735 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 736 * @param val change the values of tda in reg STATUS_REG
cparata 0:f27ce43dee4f 737 *
cparata 0:f27ce43dee4f 738 */
cparata 0:f27ce43dee4f 739 int32_t lsm6dsox_temp_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 740 {
cparata 0:f27ce43dee4f 741 lsm6dsox_status_reg_t reg;
cparata 0:f27ce43dee4f 742 int32_t ret;
cparata 0:f27ce43dee4f 743
cparata 0:f27ce43dee4f 744 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 745 *val = reg.tda;
cparata 0:f27ce43dee4f 746
cparata 0:f27ce43dee4f 747 return ret;
cparata 0:f27ce43dee4f 748 }
cparata 0:f27ce43dee4f 749
cparata 0:f27ce43dee4f 750 /**
cparata 0:f27ce43dee4f 751 * @brief Accelerometer X-axis user offset correction expressed in
cparata 0:f27ce43dee4f 752 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata 0:f27ce43dee4f 753 * The value must be in the range [-127 127].[set]
cparata 0:f27ce43dee4f 754 *
cparata 0:f27ce43dee4f 755 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 756 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 757 *
cparata 0:f27ce43dee4f 758 */
cparata 0:f27ce43dee4f 759 int32_t lsm6dsox_xl_usr_offset_x_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 760 {
cparata 0:f27ce43dee4f 761 int32_t ret;
cparata 0:f27ce43dee4f 762 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1);
cparata 0:f27ce43dee4f 763 return ret;
cparata 0:f27ce43dee4f 764 }
cparata 0:f27ce43dee4f 765
cparata 0:f27ce43dee4f 766 /**
cparata 0:f27ce43dee4f 767 * @brief Accelerometer X-axis user offset correction expressed in two’s
cparata 0:f27ce43dee4f 768 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata 0:f27ce43dee4f 769 * The value must be in the range [-127 127].[get]
cparata 0:f27ce43dee4f 770 *
cparata 0:f27ce43dee4f 771 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 772 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 773 *
cparata 0:f27ce43dee4f 774 */
cparata 0:f27ce43dee4f 775 int32_t lsm6dsox_xl_usr_offset_x_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 776 {
cparata 0:f27ce43dee4f 777 int32_t ret;
cparata 0:f27ce43dee4f 778 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1);
cparata 0:f27ce43dee4f 779 return ret;
cparata 0:f27ce43dee4f 780 }
cparata 0:f27ce43dee4f 781
cparata 0:f27ce43dee4f 782 /**
cparata 0:f27ce43dee4f 783 * @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata 0:f27ce43dee4f 784 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata 0:f27ce43dee4f 785 * The value must be in the range [-127 127].[set]
cparata 0:f27ce43dee4f 786 *
cparata 0:f27ce43dee4f 787 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 788 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 789 *
cparata 0:f27ce43dee4f 790 */
cparata 0:f27ce43dee4f 791 int32_t lsm6dsox_xl_usr_offset_y_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 792 {
cparata 0:f27ce43dee4f 793 int32_t ret;
cparata 0:f27ce43dee4f 794 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1);
cparata 0:f27ce43dee4f 795 return ret;
cparata 0:f27ce43dee4f 796 }
cparata 0:f27ce43dee4f 797
cparata 0:f27ce43dee4f 798 /**
cparata 0:f27ce43dee4f 799 * @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata 0:f27ce43dee4f 800 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata 0:f27ce43dee4f 801 * The value must be in the range [-127 127].[get]
cparata 0:f27ce43dee4f 802 *
cparata 0:f27ce43dee4f 803 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 804 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 805 *
cparata 0:f27ce43dee4f 806 */
cparata 0:f27ce43dee4f 807 int32_t lsm6dsox_xl_usr_offset_y_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 808 {
cparata 0:f27ce43dee4f 809 int32_t ret;
cparata 0:f27ce43dee4f 810 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1);
cparata 0:f27ce43dee4f 811 return ret;
cparata 0:f27ce43dee4f 812 }
cparata 0:f27ce43dee4f 813
cparata 0:f27ce43dee4f 814 /**
cparata 0:f27ce43dee4f 815 * @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata 0:f27ce43dee4f 816 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata 0:f27ce43dee4f 817 * The value must be in the range [-127 127].[set]
cparata 0:f27ce43dee4f 818 *
cparata 0:f27ce43dee4f 819 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 820 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 821 *
cparata 0:f27ce43dee4f 822 */
cparata 0:f27ce43dee4f 823 int32_t lsm6dsox_xl_usr_offset_z_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 824 {
cparata 0:f27ce43dee4f 825 int32_t ret;
cparata 0:f27ce43dee4f 826 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1);
cparata 0:f27ce43dee4f 827 return ret;
cparata 0:f27ce43dee4f 828 }
cparata 0:f27ce43dee4f 829
cparata 0:f27ce43dee4f 830 /**
cparata 0:f27ce43dee4f 831 * @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata 0:f27ce43dee4f 832 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata 0:f27ce43dee4f 833 * The value must be in the range [-127 127].[get]
cparata 0:f27ce43dee4f 834 *
cparata 0:f27ce43dee4f 835 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 836 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 837 *
cparata 0:f27ce43dee4f 838 */
cparata 0:f27ce43dee4f 839 int32_t lsm6dsox_xl_usr_offset_z_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 840 {
cparata 0:f27ce43dee4f 841 int32_t ret;
cparata 0:f27ce43dee4f 842 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1);
cparata 0:f27ce43dee4f 843 return ret;
cparata 0:f27ce43dee4f 844 }
cparata 0:f27ce43dee4f 845
cparata 0:f27ce43dee4f 846 /**
cparata 0:f27ce43dee4f 847 * @brief Enables user offset on out.[set]
cparata 0:f27ce43dee4f 848 *
cparata 0:f27ce43dee4f 849 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 850 * @param val change the values of usr_off_on_out in reg CTRL7_G
cparata 0:f27ce43dee4f 851 *
cparata 0:f27ce43dee4f 852 */
cparata 0:f27ce43dee4f 853 int32_t lsm6dsox_xl_usr_offset_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 854 {
cparata 0:f27ce43dee4f 855 lsm6dsox_ctrl7_g_t reg;
cparata 0:f27ce43dee4f 856 int32_t ret;
cparata 0:f27ce43dee4f 857
cparata 0:f27ce43dee4f 858 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 859 if (ret == 0) {
cparata 0:f27ce43dee4f 860 reg.usr_off_on_out = val;
cparata 0:f27ce43dee4f 861 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 862 }
cparata 0:f27ce43dee4f 863 return ret;
cparata 0:f27ce43dee4f 864 }
cparata 0:f27ce43dee4f 865
cparata 0:f27ce43dee4f 866 /**
cparata 0:f27ce43dee4f 867 * @brief User offset on out flag.[get]
cparata 0:f27ce43dee4f 868 *
cparata 0:f27ce43dee4f 869 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 870 * @param val values of usr_off_on_out in reg CTRL7_G
cparata 0:f27ce43dee4f 871 *
cparata 0:f27ce43dee4f 872 */
cparata 0:f27ce43dee4f 873 int32_t lsm6dsox_xl_usr_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 874 {
cparata 0:f27ce43dee4f 875 lsm6dsox_ctrl7_g_t reg;
cparata 0:f27ce43dee4f 876 int32_t ret;
cparata 0:f27ce43dee4f 877
cparata 0:f27ce43dee4f 878 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 879 *val = reg.usr_off_on_out;
cparata 0:f27ce43dee4f 880
cparata 0:f27ce43dee4f 881 return ret;
cparata 0:f27ce43dee4f 882 }
cparata 0:f27ce43dee4f 883
cparata 0:f27ce43dee4f 884 /**
cparata 0:f27ce43dee4f 885 * @}
cparata 0:f27ce43dee4f 886 *
cparata 0:f27ce43dee4f 887 */
cparata 0:f27ce43dee4f 888
cparata 0:f27ce43dee4f 889 /**
cparata 0:f27ce43dee4f 890 * @defgroup LSM6DSOX_Timestamp
cparata 0:f27ce43dee4f 891 * @brief This section groups all the functions that manage the
cparata 0:f27ce43dee4f 892 * timestamp generation.
cparata 0:f27ce43dee4f 893 * @{
cparata 0:f27ce43dee4f 894 *
cparata 0:f27ce43dee4f 895 */
cparata 0:f27ce43dee4f 896
cparata 0:f27ce43dee4f 897 /**
cparata 0:f27ce43dee4f 898 * @brief Enables timestamp counter.[set]
cparata 0:f27ce43dee4f 899 *
cparata 0:f27ce43dee4f 900 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 901 * @param val change the values of timestamp_en in reg CTRL10_C
cparata 0:f27ce43dee4f 902 *
cparata 0:f27ce43dee4f 903 */
cparata 0:f27ce43dee4f 904 int32_t lsm6dsox_timestamp_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 905 {
cparata 0:f27ce43dee4f 906 lsm6dsox_ctrl10_c_t reg;
cparata 0:f27ce43dee4f 907 int32_t ret;
cparata 0:f27ce43dee4f 908
cparata 0:f27ce43dee4f 909 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 910 if (ret == 0) {
cparata 0:f27ce43dee4f 911 reg.timestamp_en = val;
cparata 0:f27ce43dee4f 912 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 913 }
cparata 0:f27ce43dee4f 914 return ret;
cparata 0:f27ce43dee4f 915 }
cparata 0:f27ce43dee4f 916
cparata 0:f27ce43dee4f 917 /**
cparata 0:f27ce43dee4f 918 * @brief Enables timestamp counter.[get]
cparata 0:f27ce43dee4f 919 *
cparata 0:f27ce43dee4f 920 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 921 * @param val change the values of timestamp_en in reg CTRL10_C
cparata 0:f27ce43dee4f 922 *
cparata 0:f27ce43dee4f 923 */
cparata 0:f27ce43dee4f 924 int32_t lsm6dsox_timestamp_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 925 {
cparata 0:f27ce43dee4f 926 lsm6dsox_ctrl10_c_t reg;
cparata 0:f27ce43dee4f 927 int32_t ret;
cparata 0:f27ce43dee4f 928
cparata 0:f27ce43dee4f 929 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 930 *val = reg.timestamp_en;
cparata 0:f27ce43dee4f 931
cparata 0:f27ce43dee4f 932 return ret;
cparata 0:f27ce43dee4f 933 }
cparata 0:f27ce43dee4f 934
cparata 0:f27ce43dee4f 935 /**
cparata 0:f27ce43dee4f 936 * @brief Timestamp first data output register (r).
cparata 0:f27ce43dee4f 937 * The value is expressed as a 32-bit word and the bit
cparata 0:f27ce43dee4f 938 * resolution is 25 μs.[get]
cparata 0:f27ce43dee4f 939 *
cparata 0:f27ce43dee4f 940 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 941 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 942 *
cparata 0:f27ce43dee4f 943 */
cparata 0:f27ce43dee4f 944 int32_t lsm6dsox_timestamp_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 945 {
cparata 0:f27ce43dee4f 946 int32_t ret;
cparata 0:f27ce43dee4f 947 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TIMESTAMP0, buff, 4);
cparata 0:f27ce43dee4f 948 return ret;
cparata 0:f27ce43dee4f 949 }
cparata 0:f27ce43dee4f 950
cparata 0:f27ce43dee4f 951 /**
cparata 0:f27ce43dee4f 952 * @}
cparata 0:f27ce43dee4f 953 *
cparata 0:f27ce43dee4f 954 */
cparata 0:f27ce43dee4f 955
cparata 0:f27ce43dee4f 956 /**
cparata 0:f27ce43dee4f 957 * @defgroup LSM6DSOX_Data output
cparata 0:f27ce43dee4f 958 * @brief This section groups all the data output functions.
cparata 0:f27ce43dee4f 959 * @{
cparata 0:f27ce43dee4f 960 *
cparata 0:f27ce43dee4f 961 */
cparata 0:f27ce43dee4f 962
cparata 0:f27ce43dee4f 963 /**
cparata 0:f27ce43dee4f 964 * @brief Circular burst-mode (rounding) read of the output
cparata 0:f27ce43dee4f 965 * registers.[set]
cparata 0:f27ce43dee4f 966 *
cparata 0:f27ce43dee4f 967 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 968 * @param val change the values of rounding in reg CTRL5_C
cparata 0:f27ce43dee4f 969 *
cparata 0:f27ce43dee4f 970 */
cparata 0:f27ce43dee4f 971 int32_t lsm6dsox_rounding_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 972 lsm6dsox_rounding_t val)
cparata 0:f27ce43dee4f 973 {
cparata 0:f27ce43dee4f 974 lsm6dsox_ctrl5_c_t reg;
cparata 0:f27ce43dee4f 975 int32_t ret;
cparata 0:f27ce43dee4f 976
cparata 0:f27ce43dee4f 977 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 978 if (ret == 0) {
cparata 0:f27ce43dee4f 979 reg.rounding = (uint8_t)val;
cparata 0:f27ce43dee4f 980 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 981 }
cparata 0:f27ce43dee4f 982 return ret;
cparata 0:f27ce43dee4f 983 }
cparata 0:f27ce43dee4f 984
cparata 0:f27ce43dee4f 985 /**
cparata 0:f27ce43dee4f 986 * @brief Gyroscope UI chain full-scale selection.[get]
cparata 0:f27ce43dee4f 987 *
cparata 0:f27ce43dee4f 988 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 989 * @param val Get the values of rounding in reg CTRL5_C
cparata 0:f27ce43dee4f 990 *
cparata 0:f27ce43dee4f 991 */
cparata 0:f27ce43dee4f 992 int32_t lsm6dsox_rounding_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 993 lsm6dsox_rounding_t *val)
cparata 0:f27ce43dee4f 994 {
cparata 0:f27ce43dee4f 995 lsm6dsox_ctrl5_c_t reg;
cparata 0:f27ce43dee4f 996 int32_t ret;
cparata 0:f27ce43dee4f 997
cparata 0:f27ce43dee4f 998 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 999 switch (reg.rounding) {
cparata 0:f27ce43dee4f 1000 case LSM6DSOX_NO_ROUND:
cparata 0:f27ce43dee4f 1001 *val = LSM6DSOX_NO_ROUND;
cparata 0:f27ce43dee4f 1002 break;
cparata 0:f27ce43dee4f 1003 case LSM6DSOX_ROUND_XL:
cparata 0:f27ce43dee4f 1004 *val = LSM6DSOX_ROUND_XL;
cparata 0:f27ce43dee4f 1005 break;
cparata 0:f27ce43dee4f 1006 case LSM6DSOX_ROUND_GY:
cparata 0:f27ce43dee4f 1007 *val = LSM6DSOX_ROUND_GY;
cparata 0:f27ce43dee4f 1008 break;
cparata 0:f27ce43dee4f 1009 case LSM6DSOX_ROUND_GY_XL:
cparata 0:f27ce43dee4f 1010 *val = LSM6DSOX_ROUND_GY_XL;
cparata 0:f27ce43dee4f 1011 break;
cparata 0:f27ce43dee4f 1012 default:
cparata 0:f27ce43dee4f 1013 *val = LSM6DSOX_NO_ROUND;
cparata 0:f27ce43dee4f 1014 break;
cparata 0:f27ce43dee4f 1015 }
cparata 0:f27ce43dee4f 1016 return ret;
cparata 0:f27ce43dee4f 1017 }
cparata 0:f27ce43dee4f 1018
cparata 0:f27ce43dee4f 1019 /**
cparata 0:f27ce43dee4f 1020 * @brief rounding_on_status: [set] Source register rounding function in
cparata 0:f27ce43dee4f 1021 * ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh),
cparata 0:f27ce43dee4f 1022 * TAP_SRC (1Ch), D6D_SRC (1Dh),
cparata 0:f27ce43dee4f 1023 * STATUS_REG (1Eh) and
cparata 0:f27ce43dee4f 1024 * EMB_FUNC_STATUS_MAINPAGE(35h),
cparata 0:f27ce43dee4f 1025 * FSM_STATUS_A_MAINPAGE (36h),
cparata 0:f27ce43dee4f 1026 * FSM_STATUS_B_MAINPAGE (37h),
cparata 0:f27ce43dee4f 1027 * MLC_STATUS_MAINPAGE (38h),
cparata 0:f27ce43dee4f 1028 * STATUS_MASTER_MAINPAGE (39h),
cparata 0:f27ce43dee4f 1029 * FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh).
cparata 0:f27ce43dee4f 1030 *
cparata 0:f27ce43dee4f 1031 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1032 * @param lsm6dsox_rounding_status_t: change the values of rounding_status
cparata 0:f27ce43dee4f 1033 * in reg CTRL7_G
cparata 0:f27ce43dee4f 1034 *
cparata 0:f27ce43dee4f 1035 */
cparata 0:f27ce43dee4f 1036 int32_t lsm6dsox_rounding_on_status_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 1037 lsm6dsox_rounding_status_t val)
cparata 0:f27ce43dee4f 1038 {
cparata 0:f27ce43dee4f 1039 lsm6dsox_ctrl5_c_t reg;
cparata 0:f27ce43dee4f 1040 int32_t ret;
cparata 0:f27ce43dee4f 1041
cparata 0:f27ce43dee4f 1042 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1043 if (ret == 0) {
cparata 0:f27ce43dee4f 1044 reg.rounding_status = (uint8_t)val;
cparata 0:f27ce43dee4f 1045 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1046 }
cparata 0:f27ce43dee4f 1047
cparata 0:f27ce43dee4f 1048 return ret;
cparata 0:f27ce43dee4f 1049 }
cparata 0:f27ce43dee4f 1050
cparata 0:f27ce43dee4f 1051 /**
cparata 0:f27ce43dee4f 1052 * @brief rounding_on_status: [get] Source register rounding function in
cparata 0:f27ce43dee4f 1053 * ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh),
cparata 0:f27ce43dee4f 1054 * TAP_SRC (1Ch), D6D_SRC (1Dh),
cparata 0:f27ce43dee4f 1055 * STATUS_REG (1Eh) and
cparata 0:f27ce43dee4f 1056 * EMB_FUNC_STATUS_MAINPAGE(35h),
cparata 0:f27ce43dee4f 1057 * FSM_STATUS_A_MAINPAGE (36h),
cparata 0:f27ce43dee4f 1058 * FSM_STATUS_B_MAINPAGE (37h),
cparata 0:f27ce43dee4f 1059 * MLC_STATUS_MAINPAGE (38h),
cparata 0:f27ce43dee4f 1060 * STATUS_MASTER_MAINPAGE (39h),
cparata 0:f27ce43dee4f 1061 * FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh).
cparata 0:f27ce43dee4f 1062 *
cparata 0:f27ce43dee4f 1063 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1064 * @param lsm6dsox_rounding_status_t: Get the values of rounding_status
cparata 0:f27ce43dee4f 1065 * in reg CTRL7_G
cparata 0:f27ce43dee4f 1066 *
cparata 0:f27ce43dee4f 1067 */
cparata 0:f27ce43dee4f 1068 int32_t lsm6dsox_rounding_on_status_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 1069 lsm6dsox_rounding_status_t *val)
cparata 0:f27ce43dee4f 1070 {
cparata 0:f27ce43dee4f 1071 lsm6dsox_ctrl5_c_t reg;
cparata 0:f27ce43dee4f 1072 int32_t ret;
cparata 0:f27ce43dee4f 1073
cparata 0:f27ce43dee4f 1074 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1075 switch (reg.rounding_status) {
cparata 0:f27ce43dee4f 1076 case LSM6DSOX_STAT_RND_DISABLE:
cparata 0:f27ce43dee4f 1077 *val = LSM6DSOX_STAT_RND_DISABLE;
cparata 0:f27ce43dee4f 1078 break;
cparata 0:f27ce43dee4f 1079 case LSM6DSOX_STAT_RND_ENABLE:
cparata 0:f27ce43dee4f 1080 *val = LSM6DSOX_STAT_RND_ENABLE;
cparata 0:f27ce43dee4f 1081 break;
cparata 0:f27ce43dee4f 1082 default:
cparata 0:f27ce43dee4f 1083 *val = LSM6DSOX_STAT_RND_DISABLE;
cparata 0:f27ce43dee4f 1084 break;
cparata 0:f27ce43dee4f 1085 }
cparata 0:f27ce43dee4f 1086 return ret;
cparata 0:f27ce43dee4f 1087 }
cparata 0:f27ce43dee4f 1088
cparata 0:f27ce43dee4f 1089 /**
cparata 0:f27ce43dee4f 1090 * @brief Temperature data output register (r).
cparata 0:f27ce43dee4f 1091 * L and H registers together express a 16-bit word in two’s
cparata 0:f27ce43dee4f 1092 * complement.[get]
cparata 0:f27ce43dee4f 1093 *
cparata 0:f27ce43dee4f 1094 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1095 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 1096 *
cparata 0:f27ce43dee4f 1097 */
cparata 0:f27ce43dee4f 1098 int32_t lsm6dsox_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1099 {
cparata 0:f27ce43dee4f 1100 int32_t ret;
cparata 0:f27ce43dee4f 1101 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 2);
cparata 0:f27ce43dee4f 1102 return ret;
cparata 0:f27ce43dee4f 1103 }
cparata 0:f27ce43dee4f 1104
cparata 0:f27ce43dee4f 1105 /**
cparata 0:f27ce43dee4f 1106 * @brief Angular rate sensor. The value is expressed as a 16-bit
cparata 0:f27ce43dee4f 1107 * word in two’s complement.[get]
cparata 0:f27ce43dee4f 1108 *
cparata 0:f27ce43dee4f 1109 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1110 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 1111 *
cparata 0:f27ce43dee4f 1112 */
cparata 0:f27ce43dee4f 1113 int32_t lsm6dsox_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1114 {
cparata 0:f27ce43dee4f 1115 int32_t ret;
cparata 0:f27ce43dee4f 1116 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_G, buff, 6);
cparata 0:f27ce43dee4f 1117 return ret;
cparata 0:f27ce43dee4f 1118 }
cparata 0:f27ce43dee4f 1119
cparata 0:f27ce43dee4f 1120 /**
cparata 0:f27ce43dee4f 1121 * @brief Linear acceleration output register.
cparata 0:f27ce43dee4f 1122 * The value is expressed as a 16-bit word in two’s complement.[get]
cparata 0:f27ce43dee4f 1123 *
cparata 0:f27ce43dee4f 1124 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1125 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 1126 *
cparata 0:f27ce43dee4f 1127 */
cparata 0:f27ce43dee4f 1128 int32_t lsm6dsox_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1129 {
cparata 0:f27ce43dee4f 1130 int32_t ret;
cparata 0:f27ce43dee4f 1131 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_A, buff, 6);
cparata 0:f27ce43dee4f 1132 return ret;
cparata 0:f27ce43dee4f 1133 }
cparata 0:f27ce43dee4f 1134
cparata 0:f27ce43dee4f 1135 /**
cparata 0:f27ce43dee4f 1136 * @brief FIFO data output [get]
cparata 0:f27ce43dee4f 1137 *
cparata 0:f27ce43dee4f 1138 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1139 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 1140 *
cparata 0:f27ce43dee4f 1141 */
cparata 0:f27ce43dee4f 1142 int32_t lsm6dsox_fifo_out_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1143 {
cparata 0:f27ce43dee4f 1144 int32_t ret;
cparata 0:f27ce43dee4f 1145 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_X_L, buff, 6);
cparata 0:f27ce43dee4f 1146 return ret;
cparata 0:f27ce43dee4f 1147 }
cparata 0:f27ce43dee4f 1148
cparata 0:f27ce43dee4f 1149 /**
cparata 0:f27ce43dee4f 1150 * @brief ois_angular_rate_raw: [get] OIS angular rate sensor.
cparata 0:f27ce43dee4f 1151 * The value is expressed as a
cparata 0:f27ce43dee4f 1152 * 16-bit word in two’s complement.
cparata 0:f27ce43dee4f 1153 *
cparata 0:f27ce43dee4f 1154 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1155 * @param uint8_t * : buffer that stores data read
cparata 0:f27ce43dee4f 1156 *
cparata 0:f27ce43dee4f 1157 */
cparata 0:f27ce43dee4f 1158 int32_t lsm6dsox_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1159 {
cparata 0:f27ce43dee4f 1160 return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 6);
cparata 0:f27ce43dee4f 1161 }
cparata 0:f27ce43dee4f 1162
cparata 0:f27ce43dee4f 1163 /**
cparata 0:f27ce43dee4f 1164 * @brief ois_acceleration_raw: [get] OIS Linear acceleration output register.
cparata 0:f27ce43dee4f 1165 * The value is expressed as a
cparata 0:f27ce43dee4f 1166 * 16-bit word in two’s complement.
cparata 0:f27ce43dee4f 1167 *
cparata 0:f27ce43dee4f 1168 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1169 * @param uint8_t * : buffer that stores data read
cparata 0:f27ce43dee4f 1170 *
cparata 0:f27ce43dee4f 1171 */
cparata 0:f27ce43dee4f 1172 int32_t lsm6dsox_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1173 {
cparata 0:f27ce43dee4f 1174 return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_A_OIS, buff, 6);
cparata 0:f27ce43dee4f 1175 }
cparata 0:f27ce43dee4f 1176
cparata 0:f27ce43dee4f 1177 /**
cparata 0:f27ce43dee4f 1178 * @brief aux_temperature_raw: [get] Temperature from auxiliary
cparata 0:f27ce43dee4f 1179 * interface.
cparata 0:f27ce43dee4f 1180 * The value is expressed as a
cparata 0:f27ce43dee4f 1181 * 16-bit word in two’s complement.
cparata 0:f27ce43dee4f 1182 *
cparata 0:f27ce43dee4f 1183 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1184 * @param uint8_t * : buffer that stores data read
cparata 0:f27ce43dee4f 1185 *
cparata 0:f27ce43dee4f 1186 */
cparata 0:f27ce43dee4f 1187 int32_t lsm6dsox_aux_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1188 {
cparata 0:f27ce43dee4f 1189 return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUT_TEMP_L, buff, 2);
cparata 0:f27ce43dee4f 1190 }
cparata 0:f27ce43dee4f 1191
cparata 0:f27ce43dee4f 1192 /**
cparata 0:f27ce43dee4f 1193 * @brief aux_ois_angular_rate_raw: [get] OIS angular rate sensor from
cparata 0:f27ce43dee4f 1194 * auxiliary interface.
cparata 0:f27ce43dee4f 1195 * The value is expressed as a
cparata 0:f27ce43dee4f 1196 * 16-bit word in two’s complement.
cparata 0:f27ce43dee4f 1197 *
cparata 0:f27ce43dee4f 1198 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1199 * @param uint8_t * : buffer that stores data read
cparata 0:f27ce43dee4f 1200 *
cparata 0:f27ce43dee4f 1201 */
cparata 0:f27ce43dee4f 1202 int32_t lsm6dsox_aux_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1203 {
cparata 0:f27ce43dee4f 1204 return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 6);
cparata 0:f27ce43dee4f 1205 }
cparata 0:f27ce43dee4f 1206
cparata 0:f27ce43dee4f 1207 /**
cparata 0:f27ce43dee4f 1208 * @brief aux_ois_acceleration_raw: [get] OIS linear acceleration output
cparata 0:f27ce43dee4f 1209 * register from auxiliary interface.
cparata 0:f27ce43dee4f 1210 * The value is expressed as a
cparata 0:f27ce43dee4f 1211 * 16-bit word in two’s complement.
cparata 0:f27ce43dee4f 1212 *
cparata 0:f27ce43dee4f 1213 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1214 * @param uint8_t * : buffer that stores data read
cparata 0:f27ce43dee4f 1215 *
cparata 0:f27ce43dee4f 1216 */
cparata 0:f27ce43dee4f 1217 int32_t lsm6dsox_aux_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1218 {
cparata 0:f27ce43dee4f 1219 return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_A_OIS, buff, 6);
cparata 0:f27ce43dee4f 1220 }
cparata 0:f27ce43dee4f 1221
cparata 0:f27ce43dee4f 1222 /**
cparata 0:f27ce43dee4f 1223 * @brief Step counter output register.[get]
cparata 0:f27ce43dee4f 1224 *
cparata 0:f27ce43dee4f 1225 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1226 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 1227 *
cparata 0:f27ce43dee4f 1228 */
cparata 0:f27ce43dee4f 1229 int32_t lsm6dsox_number_of_steps_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1230 {
cparata 0:f27ce43dee4f 1231 int32_t ret;
cparata 0:f27ce43dee4f 1232
cparata 0:f27ce43dee4f 1233 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 1234 if (ret == 0) {
cparata 0:f27ce43dee4f 1235 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STEP_COUNTER_L, buff, 2);
cparata 0:f27ce43dee4f 1236 }
cparata 0:f27ce43dee4f 1237 if (ret == 0) {
cparata 0:f27ce43dee4f 1238 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 1239 }
cparata 0:f27ce43dee4f 1240 return ret;
cparata 0:f27ce43dee4f 1241 }
cparata 0:f27ce43dee4f 1242
cparata 0:f27ce43dee4f 1243 /**
cparata 0:f27ce43dee4f 1244 * @brief Reset step counter register.[get]
cparata 0:f27ce43dee4f 1245 *
cparata 0:f27ce43dee4f 1246 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1247 *
cparata 0:f27ce43dee4f 1248 */
cparata 0:f27ce43dee4f 1249 int32_t lsm6dsox_steps_reset(lsm6dsox_ctx_t *ctx)
cparata 0:f27ce43dee4f 1250 {
cparata 0:f27ce43dee4f 1251 lsm6dsox_emb_func_src_t reg;
cparata 0:f27ce43dee4f 1252 int32_t ret;
cparata 0:f27ce43dee4f 1253
cparata 0:f27ce43dee4f 1254 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 1255 if (ret == 0) {
cparata 0:f27ce43dee4f 1256 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1257 }
cparata 0:f27ce43dee4f 1258 if (ret == 0) {
cparata 0:f27ce43dee4f 1259 reg.pedo_rst_step = PROPERTY_ENABLE;
cparata 0:f27ce43dee4f 1260 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1261 }
cparata 0:f27ce43dee4f 1262 if (ret == 0) {
cparata 0:f27ce43dee4f 1263 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 1264 }
cparata 0:f27ce43dee4f 1265 return ret;
cparata 0:f27ce43dee4f 1266 }
cparata 0:f27ce43dee4f 1267
cparata 0:f27ce43dee4f 1268 /**
cparata 0:f27ce43dee4f 1269 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
cparata 0:f27ce43dee4f 1270 *
cparata 0:f27ce43dee4f 1271 * @param ctx_t *ctx: read / write interface definitions
cparata 0:f27ce43dee4f 1272 * @param uint8_t * : buffer that stores data read
cparata 0:f27ce43dee4f 1273 *
cparata 0:f27ce43dee4f 1274 */
cparata 0:f27ce43dee4f 1275 int32_t lsm6dsox_mlc_out_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1276 {
cparata 0:f27ce43dee4f 1277 int32_t ret;
cparata 0:f27ce43dee4f 1278 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 1279 if (ret == 0) {
cparata 0:f27ce43dee4f 1280 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC0_SRC, buff, 8);
cparata 0:f27ce43dee4f 1281 }
cparata 0:f27ce43dee4f 1282 if (ret == 0) {
cparata 0:f27ce43dee4f 1283 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 1284 }
cparata 0:f27ce43dee4f 1285 return ret;
cparata 0:f27ce43dee4f 1286 }
cparata 0:f27ce43dee4f 1287
cparata 0:f27ce43dee4f 1288 /**
cparata 0:f27ce43dee4f 1289 * @}
cparata 0:f27ce43dee4f 1290 *
cparata 0:f27ce43dee4f 1291 */
cparata 0:f27ce43dee4f 1292
cparata 0:f27ce43dee4f 1293 /**
cparata 0:f27ce43dee4f 1294 * @defgroup LSM6DSOX_common
cparata 0:f27ce43dee4f 1295 * @brief This section groups common usefull functions.
cparata 0:f27ce43dee4f 1296 * @{
cparata 0:f27ce43dee4f 1297 *
cparata 0:f27ce43dee4f 1298 */
cparata 0:f27ce43dee4f 1299
cparata 0:f27ce43dee4f 1300 /**
cparata 0:f27ce43dee4f 1301 * @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata 0:f27ce43dee4f 1302 * with respect to the typical.
cparata 0:f27ce43dee4f 1303 * Step: 0.15%. 8-bit format, 2's complement.[set]
cparata 0:f27ce43dee4f 1304 *
cparata 0:f27ce43dee4f 1305 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1306 * @param val change the values of freq_fine in reg
cparata 0:f27ce43dee4f 1307 * INTERNAL_FREQ_FINE
cparata 0:f27ce43dee4f 1308 *
cparata 0:f27ce43dee4f 1309 */
cparata 0:f27ce43dee4f 1310 int32_t lsm6dsox_odr_cal_reg_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 1311 {
cparata 0:f27ce43dee4f 1312 lsm6dsox_internal_freq_fine_t reg;
cparata 0:f27ce43dee4f 1313 int32_t ret;
cparata 0:f27ce43dee4f 1314
cparata 0:f27ce43dee4f 1315 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1316 if (ret == 0) {
cparata 0:f27ce43dee4f 1317 reg.freq_fine = val;
cparata 0:f27ce43dee4f 1318 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE,
cparata 0:f27ce43dee4f 1319 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1320 }
cparata 0:f27ce43dee4f 1321 return ret;
cparata 0:f27ce43dee4f 1322 }
cparata 0:f27ce43dee4f 1323
cparata 0:f27ce43dee4f 1324 /**
cparata 0:f27ce43dee4f 1325 * @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata 0:f27ce43dee4f 1326 * with respect to the typical.
cparata 0:f27ce43dee4f 1327 * Step: 0.15%. 8-bit format, 2's complement.[get]
cparata 0:f27ce43dee4f 1328 *
cparata 0:f27ce43dee4f 1329 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1330 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
cparata 0:f27ce43dee4f 1331 *
cparata 0:f27ce43dee4f 1332 */
cparata 0:f27ce43dee4f 1333 int32_t lsm6dsox_odr_cal_reg_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 1334 {
cparata 0:f27ce43dee4f 1335 lsm6dsox_internal_freq_fine_t reg;
cparata 0:f27ce43dee4f 1336 int32_t ret;
cparata 0:f27ce43dee4f 1337
cparata 0:f27ce43dee4f 1338 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1339 *val = reg.freq_fine;
cparata 0:f27ce43dee4f 1340
cparata 0:f27ce43dee4f 1341 return ret;
cparata 0:f27ce43dee4f 1342 }
cparata 0:f27ce43dee4f 1343
cparata 0:f27ce43dee4f 1344
cparata 0:f27ce43dee4f 1345 /**
cparata 0:f27ce43dee4f 1346 * @brief Enable access to the embedded functions/sensor
cparata 0:f27ce43dee4f 1347 * hub configuration registers.[set]
cparata 0:f27ce43dee4f 1348 *
cparata 0:f27ce43dee4f 1349 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1350 * @param val change the values of reg_access in
cparata 0:f27ce43dee4f 1351 * reg FUNC_CFG_ACCESS
cparata 0:f27ce43dee4f 1352 *
cparata 0:f27ce43dee4f 1353 */
cparata 0:f27ce43dee4f 1354 int32_t lsm6dsox_mem_bank_set(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t val)
cparata 0:f27ce43dee4f 1355 {
cparata 0:f27ce43dee4f 1356 lsm6dsox_func_cfg_access_t reg;
cparata 0:f27ce43dee4f 1357 int32_t ret;
cparata 0:f27ce43dee4f 1358
cparata 0:f27ce43dee4f 1359 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1360 if (ret == 0) {
cparata 0:f27ce43dee4f 1361 reg.reg_access = (uint8_t)val;
cparata 0:f27ce43dee4f 1362 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1363 }
cparata 0:f27ce43dee4f 1364 return ret;
cparata 0:f27ce43dee4f 1365 }
cparata 0:f27ce43dee4f 1366
cparata 0:f27ce43dee4f 1367 /**
cparata 0:f27ce43dee4f 1368 * @brief Enable access to the embedded functions/sensor
cparata 0:f27ce43dee4f 1369 * hub configuration registers.[get]
cparata 0:f27ce43dee4f 1370 *
cparata 0:f27ce43dee4f 1371 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1372 * @param val Get the values of reg_access in
cparata 0:f27ce43dee4f 1373 * reg FUNC_CFG_ACCESS
cparata 0:f27ce43dee4f 1374 *
cparata 0:f27ce43dee4f 1375 */
cparata 0:f27ce43dee4f 1376 int32_t lsm6dsox_mem_bank_get(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t *val)
cparata 0:f27ce43dee4f 1377 {
cparata 0:f27ce43dee4f 1378 lsm6dsox_func_cfg_access_t reg;
cparata 0:f27ce43dee4f 1379 int32_t ret;
cparata 0:f27ce43dee4f 1380
cparata 0:f27ce43dee4f 1381 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1382 switch (reg.reg_access) {
cparata 0:f27ce43dee4f 1383 case LSM6DSOX_USER_BANK:
cparata 0:f27ce43dee4f 1384 *val = LSM6DSOX_USER_BANK;
cparata 0:f27ce43dee4f 1385 break;
cparata 0:f27ce43dee4f 1386 case LSM6DSOX_SENSOR_HUB_BANK:
cparata 0:f27ce43dee4f 1387 *val = LSM6DSOX_SENSOR_HUB_BANK;
cparata 0:f27ce43dee4f 1388 break;
cparata 0:f27ce43dee4f 1389 case LSM6DSOX_EMBEDDED_FUNC_BANK:
cparata 0:f27ce43dee4f 1390 *val = LSM6DSOX_EMBEDDED_FUNC_BANK;
cparata 0:f27ce43dee4f 1391 break;
cparata 0:f27ce43dee4f 1392 default:
cparata 0:f27ce43dee4f 1393 *val = LSM6DSOX_USER_BANK;
cparata 0:f27ce43dee4f 1394 break;
cparata 0:f27ce43dee4f 1395 }
cparata 0:f27ce43dee4f 1396 return ret;
cparata 0:f27ce43dee4f 1397 }
cparata 0:f27ce43dee4f 1398
cparata 0:f27ce43dee4f 1399 /**
cparata 0:f27ce43dee4f 1400 * @brief Write a line(byte) in a page.[set]
cparata 0:f27ce43dee4f 1401 *
cparata 0:f27ce43dee4f 1402 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1403 * @param uint8_t address: page line address
cparata 0:f27ce43dee4f 1404 * @param val value to write
cparata 0:f27ce43dee4f 1405 *
cparata 0:f27ce43dee4f 1406 */
cparata 0:f27ce43dee4f 1407 int32_t lsm6dsox_ln_pg_write_byte(lsm6dsox_ctx_t *ctx, uint16_t address,
cparata 0:f27ce43dee4f 1408 uint8_t *val)
cparata 0:f27ce43dee4f 1409 {
cparata 0:f27ce43dee4f 1410 lsm6dsox_page_rw_t page_rw;
cparata 0:f27ce43dee4f 1411 lsm6dsox_page_sel_t page_sel;
cparata 0:f27ce43dee4f 1412 lsm6dsox_page_address_t page_address;
cparata 0:f27ce43dee4f 1413 int32_t ret;
cparata 0:f27ce43dee4f 1414
cparata 0:f27ce43dee4f 1415 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 1416
cparata 0:f27ce43dee4f 1417 if (ret == 0) {
cparata 0:f27ce43dee4f 1418 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1419 }
cparata 0:f27ce43dee4f 1420 if (ret == 0) {
cparata 0:f27ce43dee4f 1421 page_rw.page_rw = 0x02; /* page_write enable */
cparata 0:f27ce43dee4f 1422 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1423 }
cparata 0:f27ce43dee4f 1424 if (ret == 0) {
cparata 0:f27ce43dee4f 1425 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata 0:f27ce43dee4f 1426 }
cparata 0:f27ce43dee4f 1427
cparata 0:f27ce43dee4f 1428 if (ret == 0) {
cparata 0:f27ce43dee4f 1429 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata 0:f27ce43dee4f 1430 page_sel.not_used_01 = 1;
cparata 0:f27ce43dee4f 1431 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata 0:f27ce43dee4f 1432 }
cparata 0:f27ce43dee4f 1433 if (ret == 0) {
cparata 0:f27ce43dee4f 1434 page_address.page_addr = (uint8_t)address & 0xFFU;
cparata 0:f27ce43dee4f 1435 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
cparata 0:f27ce43dee4f 1436 (uint8_t*)&page_address, 1);
cparata 0:f27ce43dee4f 1437 }
cparata 0:f27ce43dee4f 1438 if (ret == 0) {
cparata 0:f27ce43dee4f 1439 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1);
cparata 0:f27ce43dee4f 1440 }
cparata 0:f27ce43dee4f 1441 if (ret == 0) {
cparata 0:f27ce43dee4f 1442 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1443 }
cparata 0:f27ce43dee4f 1444 if (ret == 0) {
cparata 0:f27ce43dee4f 1445 page_rw.page_rw = 0x00; /* page_write disable */
cparata 0:f27ce43dee4f 1446 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1447 }
cparata 0:f27ce43dee4f 1448 if (ret == 0) {
cparata 0:f27ce43dee4f 1449
cparata 0:f27ce43dee4f 1450 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 1451 }
cparata 0:f27ce43dee4f 1452 return ret;
cparata 0:f27ce43dee4f 1453 }
cparata 0:f27ce43dee4f 1454
cparata 0:f27ce43dee4f 1455 /**
cparata 0:f27ce43dee4f 1456 * @brief Write buffer in a page.[set]
cparata 0:f27ce43dee4f 1457 *
cparata 0:f27ce43dee4f 1458 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1459 * @param uint8_t address: page line address
cparata 0:f27ce43dee4f 1460 * @param uint8_t *buf: buffer to write
cparata 0:f27ce43dee4f 1461 * @param uint8_t len: buffer len
cparata 0:f27ce43dee4f 1462 *
cparata 0:f27ce43dee4f 1463 */
cparata 0:f27ce43dee4f 1464 int32_t lsm6dsox_ln_pg_write(lsm6dsox_ctx_t *ctx, uint16_t address,
cparata 0:f27ce43dee4f 1465 uint8_t *buf, uint8_t len)
cparata 0:f27ce43dee4f 1466 {
cparata 0:f27ce43dee4f 1467 lsm6dsox_page_rw_t page_rw;
cparata 0:f27ce43dee4f 1468 lsm6dsox_page_sel_t page_sel;
cparata 0:f27ce43dee4f 1469 lsm6dsox_page_address_t page_address;
cparata 0:f27ce43dee4f 1470 int32_t ret;
cparata 0:f27ce43dee4f 1471 uint8_t msb, lsb;
cparata 0:f27ce43dee4f 1472 uint8_t i ;
cparata 0:f27ce43dee4f 1473
cparata 0:f27ce43dee4f 1474 msb = ((uint8_t)(address >> 8) & 0x0FU);
cparata 0:f27ce43dee4f 1475 lsb = (uint8_t)address & 0xFFU;
cparata 0:f27ce43dee4f 1476
cparata 0:f27ce43dee4f 1477 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 1478 if (ret == 0) {
cparata 0:f27ce43dee4f 1479
cparata 0:f27ce43dee4f 1480 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1481 }
cparata 0:f27ce43dee4f 1482 if (ret == 0) {
cparata 0:f27ce43dee4f 1483 page_rw.page_rw = 0x02; /* page_write enable*/
cparata 0:f27ce43dee4f 1484 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1485 }
cparata 0:f27ce43dee4f 1486 if (ret == 0) {
cparata 0:f27ce43dee4f 1487 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata 0:f27ce43dee4f 1488 }
cparata 0:f27ce43dee4f 1489 if (ret == 0) {
cparata 0:f27ce43dee4f 1490 page_sel.page_sel = msb;
cparata 0:f27ce43dee4f 1491 page_sel.not_used_01 = 1;
cparata 0:f27ce43dee4f 1492 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata 0:f27ce43dee4f 1493 }
cparata 0:f27ce43dee4f 1494 if (ret == 0) {
cparata 0:f27ce43dee4f 1495 page_address.page_addr = lsb;
cparata 0:f27ce43dee4f 1496 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
cparata 0:f27ce43dee4f 1497 (uint8_t*)&page_address, 1);
cparata 0:f27ce43dee4f 1498 }
cparata 0:f27ce43dee4f 1499
cparata 0:f27ce43dee4f 1500 if (ret == 0) {
cparata 0:f27ce43dee4f 1501
cparata 0:f27ce43dee4f 1502 for (i = 0; ( (i < len) && (ret == 0) ); i++)
cparata 0:f27ce43dee4f 1503 {
cparata 0:f27ce43dee4f 1504 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, &buf[i], 1);
cparata 0:f27ce43dee4f 1505
cparata 0:f27ce43dee4f 1506 /* Check if page wrap */
cparata 0:f27ce43dee4f 1507 if ( (lsb == 0x00U) && (ret == 0) ) {
cparata 0:f27ce43dee4f 1508 lsb++;
cparata 0:f27ce43dee4f 1509 msb++;
cparata 0:f27ce43dee4f 1510 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*)&page_sel, 1);
cparata 0:f27ce43dee4f 1511 if (ret == 0) {
cparata 0:f27ce43dee4f 1512 page_sel.page_sel = msb;
cparata 0:f27ce43dee4f 1513 page_sel.not_used_01 = 1;
cparata 0:f27ce43dee4f 1514 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
cparata 0:f27ce43dee4f 1515 (uint8_t*)&page_sel, 1);
cparata 0:f27ce43dee4f 1516 }
cparata 0:f27ce43dee4f 1517 }
cparata 0:f27ce43dee4f 1518 }
cparata 0:f27ce43dee4f 1519 page_sel.page_sel = 0;
cparata 0:f27ce43dee4f 1520 page_sel.not_used_01 = 1;
cparata 0:f27ce43dee4f 1521 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata 0:f27ce43dee4f 1522 }
cparata 0:f27ce43dee4f 1523 if (ret == 0) {
cparata 0:f27ce43dee4f 1524
cparata 0:f27ce43dee4f 1525 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1526 }
cparata 0:f27ce43dee4f 1527 if (ret == 0) {
cparata 0:f27ce43dee4f 1528 page_rw.page_rw = 0x00; /* page_write disable */
cparata 0:f27ce43dee4f 1529 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1530 }
cparata 0:f27ce43dee4f 1531
cparata 0:f27ce43dee4f 1532 if (ret == 0) {
cparata 0:f27ce43dee4f 1533
cparata 0:f27ce43dee4f 1534 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 1535 }
cparata 0:f27ce43dee4f 1536 return ret;
cparata 0:f27ce43dee4f 1537 }
cparata 0:f27ce43dee4f 1538
cparata 0:f27ce43dee4f 1539 /**
cparata 0:f27ce43dee4f 1540 * @brief Read a line(byte) in a page.[get]
cparata 0:f27ce43dee4f 1541 *
cparata 0:f27ce43dee4f 1542 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1543 * @param uint8_t address: page line address
cparata 0:f27ce43dee4f 1544 * @param val read value
cparata 0:f27ce43dee4f 1545 *
cparata 0:f27ce43dee4f 1546 */
cparata 0:f27ce43dee4f 1547 int32_t lsm6dsox_ln_pg_read_byte(lsm6dsox_ctx_t *ctx, uint16_t address,
cparata 0:f27ce43dee4f 1548 uint8_t *val)
cparata 0:f27ce43dee4f 1549 {
cparata 0:f27ce43dee4f 1550 lsm6dsox_page_rw_t page_rw;
cparata 0:f27ce43dee4f 1551 lsm6dsox_page_sel_t page_sel;
cparata 0:f27ce43dee4f 1552 lsm6dsox_page_address_t page_address;
cparata 0:f27ce43dee4f 1553 int32_t ret;
cparata 0:f27ce43dee4f 1554
cparata 0:f27ce43dee4f 1555 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 1556 if (ret == 0) {
cparata 0:f27ce43dee4f 1557
cparata 0:f27ce43dee4f 1558 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1559 }
cparata 0:f27ce43dee4f 1560 if (ret == 0) {
cparata 0:f27ce43dee4f 1561 page_rw.page_rw = 0x01; /* page_read enable*/
cparata 0:f27ce43dee4f 1562 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1563 }
cparata 0:f27ce43dee4f 1564 if (ret == 0) {
cparata 0:f27ce43dee4f 1565
cparata 0:f27ce43dee4f 1566 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata 0:f27ce43dee4f 1567 }
cparata 0:f27ce43dee4f 1568 if (ret == 0) {
cparata 0:f27ce43dee4f 1569 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata 0:f27ce43dee4f 1570 page_sel.not_used_01 = 1;
cparata 0:f27ce43dee4f 1571 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata 0:f27ce43dee4f 1572 }
cparata 0:f27ce43dee4f 1573 if (ret == 0) {
cparata 0:f27ce43dee4f 1574 page_address.page_addr = (uint8_t)address & 0x00FFU;
cparata 0:f27ce43dee4f 1575 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
cparata 0:f27ce43dee4f 1576 (uint8_t*)&page_address, 1);
cparata 0:f27ce43dee4f 1577 }
cparata 0:f27ce43dee4f 1578 if (ret == 0) {
cparata 0:f27ce43dee4f 1579
cparata 0:f27ce43dee4f 1580 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 2);
cparata 0:f27ce43dee4f 1581 }
cparata 0:f27ce43dee4f 1582 if (ret == 0) {
cparata 0:f27ce43dee4f 1583 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1584 }
cparata 0:f27ce43dee4f 1585 if (ret == 0) {
cparata 0:f27ce43dee4f 1586 page_rw.page_rw = 0x00; /* page_read disable */
cparata 0:f27ce43dee4f 1587 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 1588 }
cparata 0:f27ce43dee4f 1589 if (ret == 0) {
cparata 0:f27ce43dee4f 1590 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 1591 }
cparata 0:f27ce43dee4f 1592
cparata 0:f27ce43dee4f 1593 return ret;
cparata 0:f27ce43dee4f 1594 }
cparata 0:f27ce43dee4f 1595
cparata 0:f27ce43dee4f 1596 /**
cparata 0:f27ce43dee4f 1597 * @brief Data-ready pulsed / letched mode.[set]
cparata 0:f27ce43dee4f 1598 *
cparata 0:f27ce43dee4f 1599 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1600 * @param val change the values of
cparata 0:f27ce43dee4f 1601 * dataready_pulsed in
cparata 0:f27ce43dee4f 1602 * reg COUNTER_BDR_REG1
cparata 0:f27ce43dee4f 1603 *
cparata 0:f27ce43dee4f 1604 */
cparata 0:f27ce43dee4f 1605 int32_t lsm6dsox_data_ready_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 1606 lsm6dsox_dataready_pulsed_t val)
cparata 0:f27ce43dee4f 1607 {
cparata 0:f27ce43dee4f 1608 lsm6dsox_counter_bdr_reg1_t reg;
cparata 0:f27ce43dee4f 1609 int32_t ret;
cparata 0:f27ce43dee4f 1610
cparata 0:f27ce43dee4f 1611 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1612 if (ret == 0) {
cparata 0:f27ce43dee4f 1613 reg.dataready_pulsed = (uint8_t)val;
cparata 0:f27ce43dee4f 1614 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1615 }
cparata 0:f27ce43dee4f 1616 return ret;
cparata 0:f27ce43dee4f 1617 }
cparata 0:f27ce43dee4f 1618
cparata 0:f27ce43dee4f 1619 /**
cparata 0:f27ce43dee4f 1620 * @brief Data-ready pulsed / letched mode.[get]
cparata 0:f27ce43dee4f 1621 *
cparata 0:f27ce43dee4f 1622 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1623 * @param val Get the values of
cparata 0:f27ce43dee4f 1624 * dataready_pulsed in
cparata 0:f27ce43dee4f 1625 * reg COUNTER_BDR_REG1
cparata 0:f27ce43dee4f 1626 *
cparata 0:f27ce43dee4f 1627 */
cparata 0:f27ce43dee4f 1628 int32_t lsm6dsox_data_ready_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 1629 lsm6dsox_dataready_pulsed_t *val)
cparata 0:f27ce43dee4f 1630 {
cparata 0:f27ce43dee4f 1631 lsm6dsox_counter_bdr_reg1_t reg;
cparata 0:f27ce43dee4f 1632 int32_t ret;
cparata 0:f27ce43dee4f 1633
cparata 0:f27ce43dee4f 1634 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1635 switch (reg.dataready_pulsed) {
cparata 0:f27ce43dee4f 1636 case LSM6DSOX_DRDY_LATCHED:
cparata 0:f27ce43dee4f 1637 *val = LSM6DSOX_DRDY_LATCHED;
cparata 0:f27ce43dee4f 1638 break;
cparata 0:f27ce43dee4f 1639 case LSM6DSOX_DRDY_PULSED:
cparata 0:f27ce43dee4f 1640 *val = LSM6DSOX_DRDY_PULSED;
cparata 0:f27ce43dee4f 1641 break;
cparata 0:f27ce43dee4f 1642 default:
cparata 0:f27ce43dee4f 1643 *val = LSM6DSOX_DRDY_LATCHED;
cparata 0:f27ce43dee4f 1644 break;
cparata 0:f27ce43dee4f 1645 }
cparata 0:f27ce43dee4f 1646 return ret;
cparata 0:f27ce43dee4f 1647 }
cparata 0:f27ce43dee4f 1648
cparata 0:f27ce43dee4f 1649 /**
cparata 0:f27ce43dee4f 1650 * @brief Device "Who am I".[get]
cparata 0:f27ce43dee4f 1651 *
cparata 0:f27ce43dee4f 1652 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1653 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 1654 *
cparata 0:f27ce43dee4f 1655 */
cparata 0:f27ce43dee4f 1656 int32_t lsm6dsox_device_id_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 1657 {
cparata 0:f27ce43dee4f 1658 int32_t ret;
cparata 0:f27ce43dee4f 1659 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I, buff, 1);
cparata 0:f27ce43dee4f 1660 return ret;
cparata 0:f27ce43dee4f 1661 }
cparata 0:f27ce43dee4f 1662
cparata 0:f27ce43dee4f 1663 /**
cparata 0:f27ce43dee4f 1664 * @brief Software reset. Restore the default values
cparata 0:f27ce43dee4f 1665 * in user registers[set]
cparata 0:f27ce43dee4f 1666 *
cparata 0:f27ce43dee4f 1667 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1668 * @param val change the values of sw_reset in reg CTRL3_C
cparata 0:f27ce43dee4f 1669 *
cparata 0:f27ce43dee4f 1670 */
cparata 0:f27ce43dee4f 1671 int32_t lsm6dsox_reset_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 1672 {
cparata 0:f27ce43dee4f 1673 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 1674 int32_t ret;
cparata 0:f27ce43dee4f 1675
cparata 0:f27ce43dee4f 1676 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1677 if (ret == 0) {
cparata 0:f27ce43dee4f 1678 reg.sw_reset = val;
cparata 0:f27ce43dee4f 1679 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1680 }
cparata 0:f27ce43dee4f 1681
cparata 0:f27ce43dee4f 1682 return ret;
cparata 0:f27ce43dee4f 1683 }
cparata 0:f27ce43dee4f 1684
cparata 0:f27ce43dee4f 1685 /**
cparata 0:f27ce43dee4f 1686 * @brief Software reset. Restore the default values in user registers.[get]
cparata 0:f27ce43dee4f 1687 *
cparata 0:f27ce43dee4f 1688 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1689 * @param val change the values of sw_reset in reg CTRL3_C
cparata 0:f27ce43dee4f 1690 *
cparata 0:f27ce43dee4f 1691 */
cparata 0:f27ce43dee4f 1692 int32_t lsm6dsox_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 1693 {
cparata 0:f27ce43dee4f 1694 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 1695 int32_t ret;
cparata 0:f27ce43dee4f 1696
cparata 0:f27ce43dee4f 1697 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1698 *val = reg.sw_reset;
cparata 0:f27ce43dee4f 1699
cparata 0:f27ce43dee4f 1700 return ret;
cparata 0:f27ce43dee4f 1701 }
cparata 0:f27ce43dee4f 1702
cparata 0:f27ce43dee4f 1703 /**
cparata 0:f27ce43dee4f 1704 * @brief Register address automatically incremented during a multiple byte
cparata 0:f27ce43dee4f 1705 * access with a serial interface.[set]
cparata 0:f27ce43dee4f 1706 *
cparata 0:f27ce43dee4f 1707 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1708 * @param val change the values of if_inc in reg CTRL3_C
cparata 0:f27ce43dee4f 1709 *
cparata 0:f27ce43dee4f 1710 */
cparata 0:f27ce43dee4f 1711 int32_t lsm6dsox_auto_increment_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 1712 {
cparata 0:f27ce43dee4f 1713 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 1714 int32_t ret;
cparata 0:f27ce43dee4f 1715
cparata 0:f27ce43dee4f 1716 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1717 if (ret == 0) {
cparata 0:f27ce43dee4f 1718 reg.if_inc = val;
cparata 0:f27ce43dee4f 1719 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1720 }
cparata 0:f27ce43dee4f 1721 return ret;
cparata 0:f27ce43dee4f 1722 }
cparata 0:f27ce43dee4f 1723
cparata 0:f27ce43dee4f 1724 /**
cparata 0:f27ce43dee4f 1725 * @brief Register address automatically incremented during a multiple byte
cparata 0:f27ce43dee4f 1726 * access with a serial interface.[get]
cparata 0:f27ce43dee4f 1727 *
cparata 0:f27ce43dee4f 1728 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1729 * @param val change the values of if_inc in reg CTRL3_C
cparata 0:f27ce43dee4f 1730 *
cparata 0:f27ce43dee4f 1731 */
cparata 0:f27ce43dee4f 1732 int32_t lsm6dsox_auto_increment_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 1733 {
cparata 0:f27ce43dee4f 1734 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 1735 int32_t ret;
cparata 0:f27ce43dee4f 1736
cparata 0:f27ce43dee4f 1737 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1738 *val = reg.if_inc;
cparata 0:f27ce43dee4f 1739
cparata 0:f27ce43dee4f 1740 return ret;
cparata 0:f27ce43dee4f 1741 }
cparata 0:f27ce43dee4f 1742
cparata 0:f27ce43dee4f 1743 /**
cparata 0:f27ce43dee4f 1744 * @brief Reboot memory content. Reload the calibration parameters.[set]
cparata 0:f27ce43dee4f 1745 *
cparata 0:f27ce43dee4f 1746 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1747 * @param val change the values of boot in reg CTRL3_C
cparata 0:f27ce43dee4f 1748 *
cparata 0:f27ce43dee4f 1749 */
cparata 0:f27ce43dee4f 1750 int32_t lsm6dsox_boot_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 1751 {
cparata 0:f27ce43dee4f 1752 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 1753 int32_t ret;
cparata 0:f27ce43dee4f 1754
cparata 0:f27ce43dee4f 1755 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1756 if (ret == 0) {
cparata 0:f27ce43dee4f 1757 reg.boot = val;
cparata 0:f27ce43dee4f 1758 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1759 }
cparata 0:f27ce43dee4f 1760 return ret;
cparata 0:f27ce43dee4f 1761 }
cparata 0:f27ce43dee4f 1762
cparata 0:f27ce43dee4f 1763 /**
cparata 0:f27ce43dee4f 1764 * @brief Reboot memory content. Reload the calibration parameters.[get]
cparata 0:f27ce43dee4f 1765 *
cparata 0:f27ce43dee4f 1766 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1767 * @param val change the values of boot in reg CTRL3_C
cparata 0:f27ce43dee4f 1768 *
cparata 0:f27ce43dee4f 1769 */
cparata 0:f27ce43dee4f 1770 int32_t lsm6dsox_boot_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 1771 {
cparata 0:f27ce43dee4f 1772 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 1773 int32_t ret;
cparata 0:f27ce43dee4f 1774
cparata 0:f27ce43dee4f 1775 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1776 *val = reg.boot;
cparata 0:f27ce43dee4f 1777
cparata 0:f27ce43dee4f 1778 return ret;
cparata 0:f27ce43dee4f 1779 }
cparata 0:f27ce43dee4f 1780
cparata 0:f27ce43dee4f 1781 /**
cparata 0:f27ce43dee4f 1782 * @brief Linear acceleration sensor self-test enable.[set]
cparata 0:f27ce43dee4f 1783 *
cparata 0:f27ce43dee4f 1784 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1785 * @param val change the values of st_xl in reg CTRL5_C
cparata 0:f27ce43dee4f 1786 *
cparata 0:f27ce43dee4f 1787 */
cparata 0:f27ce43dee4f 1788 int32_t lsm6dsox_xl_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t val)
cparata 0:f27ce43dee4f 1789 {
cparata 0:f27ce43dee4f 1790 lsm6dsox_ctrl5_c_t reg;
cparata 0:f27ce43dee4f 1791 int32_t ret;
cparata 0:f27ce43dee4f 1792
cparata 0:f27ce43dee4f 1793 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1794 if (ret == 0) {
cparata 0:f27ce43dee4f 1795 reg.st_xl = (uint8_t)val;
cparata 0:f27ce43dee4f 1796 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1797 }
cparata 0:f27ce43dee4f 1798 return ret;
cparata 0:f27ce43dee4f 1799 }
cparata 0:f27ce43dee4f 1800
cparata 0:f27ce43dee4f 1801 /**
cparata 0:f27ce43dee4f 1802 * @brief Linear acceleration sensor self-test enable.[get]
cparata 0:f27ce43dee4f 1803 *
cparata 0:f27ce43dee4f 1804 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1805 * @param val Get the values of st_xl in reg CTRL5_C
cparata 0:f27ce43dee4f 1806 *
cparata 0:f27ce43dee4f 1807 */
cparata 0:f27ce43dee4f 1808 int32_t lsm6dsox_xl_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t *val)
cparata 0:f27ce43dee4f 1809 {
cparata 0:f27ce43dee4f 1810 lsm6dsox_ctrl5_c_t reg;
cparata 0:f27ce43dee4f 1811 int32_t ret;
cparata 0:f27ce43dee4f 1812
cparata 0:f27ce43dee4f 1813 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1814 switch (reg.st_xl) {
cparata 0:f27ce43dee4f 1815 case LSM6DSOX_XL_ST_DISABLE:
cparata 0:f27ce43dee4f 1816 *val = LSM6DSOX_XL_ST_DISABLE;
cparata 0:f27ce43dee4f 1817 break;
cparata 0:f27ce43dee4f 1818 case LSM6DSOX_XL_ST_POSITIVE:
cparata 0:f27ce43dee4f 1819 *val = LSM6DSOX_XL_ST_POSITIVE;
cparata 0:f27ce43dee4f 1820 break;
cparata 0:f27ce43dee4f 1821 case LSM6DSOX_XL_ST_NEGATIVE:
cparata 0:f27ce43dee4f 1822 *val = LSM6DSOX_XL_ST_NEGATIVE;
cparata 0:f27ce43dee4f 1823 break;
cparata 0:f27ce43dee4f 1824 default:
cparata 0:f27ce43dee4f 1825 *val = LSM6DSOX_XL_ST_DISABLE;
cparata 0:f27ce43dee4f 1826 break;
cparata 0:f27ce43dee4f 1827 }
cparata 0:f27ce43dee4f 1828 return ret;
cparata 0:f27ce43dee4f 1829 }
cparata 0:f27ce43dee4f 1830
cparata 0:f27ce43dee4f 1831 /**
cparata 0:f27ce43dee4f 1832 * @brief Angular rate sensor self-test enable.[set]
cparata 0:f27ce43dee4f 1833 *
cparata 0:f27ce43dee4f 1834 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1835 * @param val change the values of st_g in reg CTRL5_C
cparata 0:f27ce43dee4f 1836 *
cparata 0:f27ce43dee4f 1837 */
cparata 0:f27ce43dee4f 1838 int32_t lsm6dsox_gy_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t val)
cparata 0:f27ce43dee4f 1839 {
cparata 0:f27ce43dee4f 1840 lsm6dsox_ctrl5_c_t reg;
cparata 0:f27ce43dee4f 1841 int32_t ret;
cparata 0:f27ce43dee4f 1842
cparata 0:f27ce43dee4f 1843 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1844 if (ret == 0) {
cparata 0:f27ce43dee4f 1845 reg.st_g = (uint8_t)val;
cparata 0:f27ce43dee4f 1846 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1847 }
cparata 0:f27ce43dee4f 1848 return ret;
cparata 0:f27ce43dee4f 1849 }
cparata 0:f27ce43dee4f 1850
cparata 0:f27ce43dee4f 1851 /**
cparata 0:f27ce43dee4f 1852 * @brief Angular rate sensor self-test enable.[get]
cparata 0:f27ce43dee4f 1853 *
cparata 0:f27ce43dee4f 1854 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1855 * @param val Get the values of st_g in reg CTRL5_C
cparata 0:f27ce43dee4f 1856 *
cparata 0:f27ce43dee4f 1857 */
cparata 0:f27ce43dee4f 1858 int32_t lsm6dsox_gy_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t *val)
cparata 0:f27ce43dee4f 1859 {
cparata 0:f27ce43dee4f 1860 lsm6dsox_ctrl5_c_t reg;
cparata 0:f27ce43dee4f 1861 int32_t ret;
cparata 0:f27ce43dee4f 1862
cparata 0:f27ce43dee4f 1863 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1864 switch (reg.st_g) {
cparata 0:f27ce43dee4f 1865 case LSM6DSOX_GY_ST_DISABLE:
cparata 0:f27ce43dee4f 1866 *val = LSM6DSOX_GY_ST_DISABLE;
cparata 0:f27ce43dee4f 1867 break;
cparata 0:f27ce43dee4f 1868 case LSM6DSOX_GY_ST_POSITIVE:
cparata 0:f27ce43dee4f 1869 *val = LSM6DSOX_GY_ST_POSITIVE;
cparata 0:f27ce43dee4f 1870 break;
cparata 0:f27ce43dee4f 1871 case LSM6DSOX_GY_ST_NEGATIVE:
cparata 0:f27ce43dee4f 1872 *val = LSM6DSOX_GY_ST_NEGATIVE;
cparata 0:f27ce43dee4f 1873 break;
cparata 0:f27ce43dee4f 1874 default:
cparata 0:f27ce43dee4f 1875 *val = LSM6DSOX_GY_ST_DISABLE;
cparata 0:f27ce43dee4f 1876 break;
cparata 0:f27ce43dee4f 1877 }
cparata 0:f27ce43dee4f 1878 return ret;
cparata 0:f27ce43dee4f 1879 }
cparata 0:f27ce43dee4f 1880
cparata 0:f27ce43dee4f 1881 /**
cparata 0:f27ce43dee4f 1882 * @}
cparata 0:f27ce43dee4f 1883 *
cparata 0:f27ce43dee4f 1884 */
cparata 0:f27ce43dee4f 1885
cparata 0:f27ce43dee4f 1886 /**
cparata 0:f27ce43dee4f 1887 * @defgroup LSM6DSOX_filters
cparata 0:f27ce43dee4f 1888 * @brief This section group all the functions concerning the
cparata 0:f27ce43dee4f 1889 * filters configuration
cparata 0:f27ce43dee4f 1890 * @{
cparata 0:f27ce43dee4f 1891 *
cparata 0:f27ce43dee4f 1892 */
cparata 0:f27ce43dee4f 1893
cparata 0:f27ce43dee4f 1894 /**
cparata 0:f27ce43dee4f 1895 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
cparata 0:f27ce43dee4f 1896 *
cparata 0:f27ce43dee4f 1897 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1898 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata 0:f27ce43dee4f 1899 *
cparata 0:f27ce43dee4f 1900 */
cparata 0:f27ce43dee4f 1901 int32_t lsm6dsox_xl_filter_lp2_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 1902 {
cparata 0:f27ce43dee4f 1903 lsm6dsox_ctrl1_xl_t reg;
cparata 0:f27ce43dee4f 1904 int32_t ret;
cparata 0:f27ce43dee4f 1905
cparata 0:f27ce43dee4f 1906 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1907 if (ret == 0) {
cparata 0:f27ce43dee4f 1908 reg.lpf2_xl_en = val;
cparata 0:f27ce43dee4f 1909 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1910 }
cparata 0:f27ce43dee4f 1911 return ret;
cparata 0:f27ce43dee4f 1912 }
cparata 0:f27ce43dee4f 1913
cparata 0:f27ce43dee4f 1914 /**
cparata 0:f27ce43dee4f 1915 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
cparata 0:f27ce43dee4f 1916 *
cparata 0:f27ce43dee4f 1917 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1918 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata 0:f27ce43dee4f 1919 *
cparata 0:f27ce43dee4f 1920 */
cparata 0:f27ce43dee4f 1921 int32_t lsm6dsox_xl_filter_lp2_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 1922 {
cparata 0:f27ce43dee4f 1923 lsm6dsox_ctrl1_xl_t reg;
cparata 0:f27ce43dee4f 1924 int32_t ret;
cparata 0:f27ce43dee4f 1925
cparata 0:f27ce43dee4f 1926 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1927 *val = reg.lpf2_xl_en;
cparata 0:f27ce43dee4f 1928
cparata 0:f27ce43dee4f 1929 return ret;
cparata 0:f27ce43dee4f 1930 }
cparata 0:f27ce43dee4f 1931
cparata 0:f27ce43dee4f 1932 /**
cparata 0:f27ce43dee4f 1933 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata 0:f27ce43dee4f 1934 * the bandwidth can be selected through FTYPE [2:0]
cparata 0:f27ce43dee4f 1935 * in CTRL6_C (15h).[set]
cparata 0:f27ce43dee4f 1936 *
cparata 0:f27ce43dee4f 1937 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1938 * @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata 0:f27ce43dee4f 1939 *
cparata 0:f27ce43dee4f 1940 */
cparata 0:f27ce43dee4f 1941 int32_t lsm6dsox_gy_filter_lp1_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 1942 {
cparata 0:f27ce43dee4f 1943 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 1944 int32_t ret;
cparata 0:f27ce43dee4f 1945
cparata 0:f27ce43dee4f 1946 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1947 if (ret == 0) {
cparata 0:f27ce43dee4f 1948 reg.lpf1_sel_g = val;
cparata 0:f27ce43dee4f 1949 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1950 }
cparata 0:f27ce43dee4f 1951 return ret;
cparata 0:f27ce43dee4f 1952 }
cparata 0:f27ce43dee4f 1953
cparata 0:f27ce43dee4f 1954 /**
cparata 0:f27ce43dee4f 1955 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata 0:f27ce43dee4f 1956 * the bandwidth can be selected through FTYPE [2:0]
cparata 0:f27ce43dee4f 1957 * in CTRL6_C (15h).[get]
cparata 0:f27ce43dee4f 1958 *
cparata 0:f27ce43dee4f 1959 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1960 * @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata 0:f27ce43dee4f 1961 *
cparata 0:f27ce43dee4f 1962 */
cparata 0:f27ce43dee4f 1963 int32_t lsm6dsox_gy_filter_lp1_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 1964 {
cparata 0:f27ce43dee4f 1965 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 1966 int32_t ret;
cparata 0:f27ce43dee4f 1967
cparata 0:f27ce43dee4f 1968 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1969 *val = reg.lpf1_sel_g;
cparata 0:f27ce43dee4f 1970
cparata 0:f27ce43dee4f 1971 return ret;
cparata 0:f27ce43dee4f 1972 }
cparata 0:f27ce43dee4f 1973
cparata 0:f27ce43dee4f 1974 /**
cparata 0:f27ce43dee4f 1975 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata 0:f27ce43dee4f 1976 * (XL and Gyro independently masked).[set]
cparata 0:f27ce43dee4f 1977 *
cparata 0:f27ce43dee4f 1978 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 1979 * @param val change the values of drdy_mask in reg CTRL4_C
cparata 0:f27ce43dee4f 1980 *
cparata 0:f27ce43dee4f 1981 */
cparata 0:f27ce43dee4f 1982 int32_t lsm6dsox_filter_settling_mask_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 1983 {
cparata 0:f27ce43dee4f 1984 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 1985 int32_t ret;
cparata 0:f27ce43dee4f 1986
cparata 0:f27ce43dee4f 1987 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1988 if (ret == 0) {
cparata 0:f27ce43dee4f 1989 reg.drdy_mask = val;
cparata 0:f27ce43dee4f 1990 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 1991 }
cparata 0:f27ce43dee4f 1992 return ret;
cparata 0:f27ce43dee4f 1993 }
cparata 0:f27ce43dee4f 1994
cparata 0:f27ce43dee4f 1995 /**
cparata 0:f27ce43dee4f 1996 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata 0:f27ce43dee4f 1997 * (XL and Gyro independently masked).[get]
cparata 0:f27ce43dee4f 1998 *
cparata 0:f27ce43dee4f 1999 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2000 * @param val change the values of drdy_mask in reg CTRL4_C
cparata 0:f27ce43dee4f 2001 *
cparata 0:f27ce43dee4f 2002 */
cparata 0:f27ce43dee4f 2003 int32_t lsm6dsox_filter_settling_mask_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 2004 {
cparata 0:f27ce43dee4f 2005 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 2006 int32_t ret;
cparata 0:f27ce43dee4f 2007
cparata 0:f27ce43dee4f 2008 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2009 *val = reg.drdy_mask;
cparata 0:f27ce43dee4f 2010
cparata 0:f27ce43dee4f 2011 return ret;
cparata 0:f27ce43dee4f 2012 }
cparata 0:f27ce43dee4f 2013
cparata 0:f27ce43dee4f 2014 /**
cparata 0:f27ce43dee4f 2015 * @brief Gyroscope lp1 bandwidth.[set]
cparata 0:f27ce43dee4f 2016 *
cparata 0:f27ce43dee4f 2017 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2018 * @param val change the values of ftype in reg CTRL6_C
cparata 0:f27ce43dee4f 2019 *
cparata 0:f27ce43dee4f 2020 */
cparata 0:f27ce43dee4f 2021 int32_t lsm6dsox_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ftype_t val)
cparata 0:f27ce43dee4f 2022 {
cparata 0:f27ce43dee4f 2023 lsm6dsox_ctrl6_c_t reg;
cparata 0:f27ce43dee4f 2024 int32_t ret;
cparata 0:f27ce43dee4f 2025
cparata 0:f27ce43dee4f 2026 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2027 if (ret == 0) {
cparata 0:f27ce43dee4f 2028 reg.ftype = (uint8_t)val;
cparata 0:f27ce43dee4f 2029 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2030 }
cparata 0:f27ce43dee4f 2031 return ret;
cparata 0:f27ce43dee4f 2032 }
cparata 0:f27ce43dee4f 2033
cparata 0:f27ce43dee4f 2034 /**
cparata 0:f27ce43dee4f 2035 * @brief Gyroscope lp1 bandwidth.[get]
cparata 0:f27ce43dee4f 2036 *
cparata 0:f27ce43dee4f 2037 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2038 * @param val Get the values of ftype in reg CTRL6_C
cparata 0:f27ce43dee4f 2039 *
cparata 0:f27ce43dee4f 2040 */
cparata 0:f27ce43dee4f 2041 int32_t lsm6dsox_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ftype_t *val)
cparata 0:f27ce43dee4f 2042 {
cparata 0:f27ce43dee4f 2043 lsm6dsox_ctrl6_c_t reg;
cparata 0:f27ce43dee4f 2044 int32_t ret;
cparata 0:f27ce43dee4f 2045
cparata 0:f27ce43dee4f 2046 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2047 switch (reg.ftype) {
cparata 0:f27ce43dee4f 2048 case LSM6DSOX_ULTRA_LIGHT:
cparata 0:f27ce43dee4f 2049 *val = LSM6DSOX_ULTRA_LIGHT;
cparata 0:f27ce43dee4f 2050 break;
cparata 0:f27ce43dee4f 2051 case LSM6DSOX_VERY_LIGHT:
cparata 0:f27ce43dee4f 2052 *val = LSM6DSOX_VERY_LIGHT;
cparata 0:f27ce43dee4f 2053 break;
cparata 0:f27ce43dee4f 2054 case LSM6DSOX_LIGHT:
cparata 0:f27ce43dee4f 2055 *val = LSM6DSOX_LIGHT;
cparata 0:f27ce43dee4f 2056 break;
cparata 0:f27ce43dee4f 2057 case LSM6DSOX_MEDIUM:
cparata 0:f27ce43dee4f 2058 *val = LSM6DSOX_MEDIUM;
cparata 0:f27ce43dee4f 2059 break;
cparata 0:f27ce43dee4f 2060 case LSM6DSOX_STRONG:
cparata 0:f27ce43dee4f 2061 *val = LSM6DSOX_STRONG;
cparata 0:f27ce43dee4f 2062 break;
cparata 0:f27ce43dee4f 2063 case LSM6DSOX_VERY_STRONG:
cparata 0:f27ce43dee4f 2064 *val = LSM6DSOX_VERY_STRONG;
cparata 0:f27ce43dee4f 2065 break;
cparata 0:f27ce43dee4f 2066 case LSM6DSOX_AGGRESSIVE:
cparata 0:f27ce43dee4f 2067 *val = LSM6DSOX_AGGRESSIVE;
cparata 0:f27ce43dee4f 2068 break;
cparata 0:f27ce43dee4f 2069 case LSM6DSOX_XTREME:
cparata 0:f27ce43dee4f 2070 *val = LSM6DSOX_XTREME;
cparata 0:f27ce43dee4f 2071 break;
cparata 0:f27ce43dee4f 2072 default:
cparata 0:f27ce43dee4f 2073 *val = LSM6DSOX_ULTRA_LIGHT;
cparata 0:f27ce43dee4f 2074 break;
cparata 0:f27ce43dee4f 2075 }
cparata 0:f27ce43dee4f 2076 return ret;
cparata 0:f27ce43dee4f 2077 }
cparata 0:f27ce43dee4f 2078
cparata 0:f27ce43dee4f 2079 /**
cparata 0:f27ce43dee4f 2080 * @brief Low pass filter 2 on 6D function selection.[set]
cparata 0:f27ce43dee4f 2081 *
cparata 0:f27ce43dee4f 2082 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2083 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata 0:f27ce43dee4f 2084 *
cparata 0:f27ce43dee4f 2085 */
cparata 0:f27ce43dee4f 2086 int32_t lsm6dsox_xl_lp2_on_6d_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 2087 {
cparata 0:f27ce43dee4f 2088 lsm6dsox_ctrl8_xl_t reg;
cparata 0:f27ce43dee4f 2089 int32_t ret;
cparata 0:f27ce43dee4f 2090
cparata 0:f27ce43dee4f 2091 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2092 if (ret == 0) {
cparata 0:f27ce43dee4f 2093 reg.low_pass_on_6d = val;
cparata 0:f27ce43dee4f 2094 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2095 }
cparata 0:f27ce43dee4f 2096 return ret;
cparata 0:f27ce43dee4f 2097 }
cparata 0:f27ce43dee4f 2098
cparata 0:f27ce43dee4f 2099 /**
cparata 0:f27ce43dee4f 2100 * @brief Low pass filter 2 on 6D function selection.[get]
cparata 0:f27ce43dee4f 2101 *
cparata 0:f27ce43dee4f 2102 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2103 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata 0:f27ce43dee4f 2104 *
cparata 0:f27ce43dee4f 2105 */
cparata 0:f27ce43dee4f 2106 int32_t lsm6dsox_xl_lp2_on_6d_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 2107 {
cparata 0:f27ce43dee4f 2108 lsm6dsox_ctrl8_xl_t reg;
cparata 0:f27ce43dee4f 2109 int32_t ret;
cparata 0:f27ce43dee4f 2110
cparata 0:f27ce43dee4f 2111 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2112 *val = reg.low_pass_on_6d;
cparata 0:f27ce43dee4f 2113
cparata 0:f27ce43dee4f 2114 return ret;
cparata 0:f27ce43dee4f 2115 }
cparata 0:f27ce43dee4f 2116
cparata 0:f27ce43dee4f 2117 /**
cparata 0:f27ce43dee4f 2118 * @brief Accelerometer slope filter / high-pass filter selection
cparata 0:f27ce43dee4f 2119 * on output.[set]
cparata 0:f27ce43dee4f 2120 *
cparata 0:f27ce43dee4f 2121 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2122 * @param val change the values of hp_slope_xl_en
cparata 0:f27ce43dee4f 2123 * in reg CTRL8_XL
cparata 0:f27ce43dee4f 2124 *
cparata 0:f27ce43dee4f 2125 */
cparata 0:f27ce43dee4f 2126 int32_t lsm6dsox_xl_hp_path_on_out_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2127 lsm6dsox_hp_slope_xl_en_t val)
cparata 0:f27ce43dee4f 2128 {
cparata 0:f27ce43dee4f 2129 lsm6dsox_ctrl8_xl_t reg;
cparata 0:f27ce43dee4f 2130 int32_t ret;
cparata 0:f27ce43dee4f 2131
cparata 0:f27ce43dee4f 2132 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2133 if (ret == 0) {
cparata 0:f27ce43dee4f 2134 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
cparata 0:f27ce43dee4f 2135 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
cparata 0:f27ce43dee4f 2136 reg.hpcf_xl = (uint8_t)val & 0x07U;
cparata 0:f27ce43dee4f 2137 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2138 }
cparata 0:f27ce43dee4f 2139 return ret;
cparata 0:f27ce43dee4f 2140 }
cparata 0:f27ce43dee4f 2141
cparata 0:f27ce43dee4f 2142 /**
cparata 0:f27ce43dee4f 2143 * @brief Accelerometer slope filter / high-pass filter selection
cparata 0:f27ce43dee4f 2144 * on output.[get]
cparata 0:f27ce43dee4f 2145 *
cparata 0:f27ce43dee4f 2146 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2147 * @param val Get the values of hp_slope_xl_en
cparata 0:f27ce43dee4f 2148 * in reg CTRL8_XL
cparata 0:f27ce43dee4f 2149 *
cparata 0:f27ce43dee4f 2150 */
cparata 0:f27ce43dee4f 2151 int32_t lsm6dsox_xl_hp_path_on_out_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2152 lsm6dsox_hp_slope_xl_en_t *val)
cparata 0:f27ce43dee4f 2153 {
cparata 0:f27ce43dee4f 2154 lsm6dsox_ctrl8_xl_t reg;
cparata 0:f27ce43dee4f 2155 int32_t ret;
cparata 0:f27ce43dee4f 2156
cparata 0:f27ce43dee4f 2157 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2158 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
cparata 0:f27ce43dee4f 2159 reg.hpcf_xl) {
cparata 0:f27ce43dee4f 2160 case LSM6DSOX_HP_PATH_DISABLE_ON_OUT:
cparata 0:f27ce43dee4f 2161 *val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT;
cparata 0:f27ce43dee4f 2162 break;
cparata 0:f27ce43dee4f 2163 case LSM6DSOX_SLOPE_ODR_DIV_4:
cparata 0:f27ce43dee4f 2164 *val = LSM6DSOX_SLOPE_ODR_DIV_4;
cparata 0:f27ce43dee4f 2165 break;
cparata 0:f27ce43dee4f 2166 case LSM6DSOX_HP_ODR_DIV_10:
cparata 0:f27ce43dee4f 2167 *val = LSM6DSOX_HP_ODR_DIV_10;
cparata 0:f27ce43dee4f 2168 break;
cparata 0:f27ce43dee4f 2169 case LSM6DSOX_HP_ODR_DIV_20:
cparata 0:f27ce43dee4f 2170 *val = LSM6DSOX_HP_ODR_DIV_20;
cparata 0:f27ce43dee4f 2171 break;
cparata 0:f27ce43dee4f 2172 case LSM6DSOX_HP_ODR_DIV_45:
cparata 0:f27ce43dee4f 2173 *val = LSM6DSOX_HP_ODR_DIV_45;
cparata 0:f27ce43dee4f 2174 break;
cparata 0:f27ce43dee4f 2175 case LSM6DSOX_HP_ODR_DIV_100:
cparata 0:f27ce43dee4f 2176 *val = LSM6DSOX_HP_ODR_DIV_100;
cparata 0:f27ce43dee4f 2177 break;
cparata 0:f27ce43dee4f 2178 case LSM6DSOX_HP_ODR_DIV_200:
cparata 0:f27ce43dee4f 2179 *val = LSM6DSOX_HP_ODR_DIV_200;
cparata 0:f27ce43dee4f 2180 break;
cparata 0:f27ce43dee4f 2181 case LSM6DSOX_HP_ODR_DIV_400:
cparata 0:f27ce43dee4f 2182 *val = LSM6DSOX_HP_ODR_DIV_400;
cparata 0:f27ce43dee4f 2183 break;
cparata 0:f27ce43dee4f 2184 case LSM6DSOX_HP_ODR_DIV_800:
cparata 0:f27ce43dee4f 2185 *val = LSM6DSOX_HP_ODR_DIV_800;
cparata 0:f27ce43dee4f 2186 break;
cparata 0:f27ce43dee4f 2187 case LSM6DSOX_HP_REF_MD_ODR_DIV_10:
cparata 0:f27ce43dee4f 2188 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_10;
cparata 0:f27ce43dee4f 2189 break;
cparata 0:f27ce43dee4f 2190 case LSM6DSOX_HP_REF_MD_ODR_DIV_20:
cparata 0:f27ce43dee4f 2191 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_20;
cparata 0:f27ce43dee4f 2192 break;
cparata 0:f27ce43dee4f 2193 case LSM6DSOX_HP_REF_MD_ODR_DIV_45:
cparata 0:f27ce43dee4f 2194 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_45;
cparata 0:f27ce43dee4f 2195 break;
cparata 0:f27ce43dee4f 2196 case LSM6DSOX_HP_REF_MD_ODR_DIV_100:
cparata 0:f27ce43dee4f 2197 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_100;
cparata 0:f27ce43dee4f 2198 break;
cparata 0:f27ce43dee4f 2199 case LSM6DSOX_HP_REF_MD_ODR_DIV_200:
cparata 0:f27ce43dee4f 2200 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_200;
cparata 0:f27ce43dee4f 2201 break;
cparata 0:f27ce43dee4f 2202 case LSM6DSOX_HP_REF_MD_ODR_DIV_400:
cparata 0:f27ce43dee4f 2203 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_400;
cparata 0:f27ce43dee4f 2204 break;
cparata 0:f27ce43dee4f 2205 case LSM6DSOX_HP_REF_MD_ODR_DIV_800:
cparata 0:f27ce43dee4f 2206 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_800;
cparata 0:f27ce43dee4f 2207 break;
cparata 0:f27ce43dee4f 2208 case LSM6DSOX_LP_ODR_DIV_10:
cparata 0:f27ce43dee4f 2209 *val = LSM6DSOX_LP_ODR_DIV_10;
cparata 0:f27ce43dee4f 2210 break;
cparata 0:f27ce43dee4f 2211 case LSM6DSOX_LP_ODR_DIV_20:
cparata 0:f27ce43dee4f 2212 *val = LSM6DSOX_LP_ODR_DIV_20;
cparata 0:f27ce43dee4f 2213 break;
cparata 0:f27ce43dee4f 2214 case LSM6DSOX_LP_ODR_DIV_45:
cparata 0:f27ce43dee4f 2215 *val = LSM6DSOX_LP_ODR_DIV_45;
cparata 0:f27ce43dee4f 2216 break;
cparata 0:f27ce43dee4f 2217 case LSM6DSOX_LP_ODR_DIV_100:
cparata 0:f27ce43dee4f 2218 *val = LSM6DSOX_LP_ODR_DIV_100;
cparata 0:f27ce43dee4f 2219 break;
cparata 0:f27ce43dee4f 2220 case LSM6DSOX_LP_ODR_DIV_200:
cparata 0:f27ce43dee4f 2221 *val = LSM6DSOX_LP_ODR_DIV_200;
cparata 0:f27ce43dee4f 2222 break;
cparata 0:f27ce43dee4f 2223 case LSM6DSOX_LP_ODR_DIV_400:
cparata 0:f27ce43dee4f 2224 *val = LSM6DSOX_LP_ODR_DIV_400;
cparata 0:f27ce43dee4f 2225 break;
cparata 0:f27ce43dee4f 2226 case LSM6DSOX_LP_ODR_DIV_800:
cparata 0:f27ce43dee4f 2227 *val = LSM6DSOX_LP_ODR_DIV_800;
cparata 0:f27ce43dee4f 2228 break;
cparata 0:f27ce43dee4f 2229 default:
cparata 0:f27ce43dee4f 2230 *val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT;
cparata 0:f27ce43dee4f 2231 break;
cparata 0:f27ce43dee4f 2232 }
cparata 0:f27ce43dee4f 2233
cparata 0:f27ce43dee4f 2234 return ret;
cparata 0:f27ce43dee4f 2235 }
cparata 0:f27ce43dee4f 2236
cparata 0:f27ce43dee4f 2237 /**
cparata 0:f27ce43dee4f 2238 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata 0:f27ce43dee4f 2239 * The filter sets the second samples after writing this bit.
cparata 0:f27ce43dee4f 2240 * Active only during device exit from power-down mode.[set]
cparata 0:f27ce43dee4f 2241 *
cparata 0:f27ce43dee4f 2242 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2243 * @param val change the values of fastsettl_mode_xl in
cparata 0:f27ce43dee4f 2244 * reg CTRL8_XL
cparata 0:f27ce43dee4f 2245 *
cparata 0:f27ce43dee4f 2246 */
cparata 0:f27ce43dee4f 2247 int32_t lsm6dsox_xl_fast_settling_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 2248 {
cparata 0:f27ce43dee4f 2249 lsm6dsox_ctrl8_xl_t reg;
cparata 0:f27ce43dee4f 2250 int32_t ret;
cparata 0:f27ce43dee4f 2251
cparata 0:f27ce43dee4f 2252 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2253 if (ret == 0) {
cparata 0:f27ce43dee4f 2254 reg.fastsettl_mode_xl = val;
cparata 0:f27ce43dee4f 2255 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2256 }
cparata 0:f27ce43dee4f 2257 return ret;
cparata 0:f27ce43dee4f 2258 }
cparata 0:f27ce43dee4f 2259
cparata 0:f27ce43dee4f 2260 /**
cparata 0:f27ce43dee4f 2261 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata 0:f27ce43dee4f 2262 * The filter sets the second samples after writing this bit.
cparata 0:f27ce43dee4f 2263 * Active only during device exit from power-down mode.[get]
cparata 0:f27ce43dee4f 2264 *
cparata 0:f27ce43dee4f 2265 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2266 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
cparata 0:f27ce43dee4f 2267 *
cparata 0:f27ce43dee4f 2268 */
cparata 0:f27ce43dee4f 2269 int32_t lsm6dsox_xl_fast_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 2270 {
cparata 0:f27ce43dee4f 2271 lsm6dsox_ctrl8_xl_t reg;
cparata 0:f27ce43dee4f 2272 int32_t ret;
cparata 0:f27ce43dee4f 2273
cparata 0:f27ce43dee4f 2274 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2275 *val = reg.fastsettl_mode_xl;
cparata 0:f27ce43dee4f 2276
cparata 0:f27ce43dee4f 2277 return ret;
cparata 0:f27ce43dee4f 2278 }
cparata 0:f27ce43dee4f 2279
cparata 0:f27ce43dee4f 2280 /**
cparata 0:f27ce43dee4f 2281 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata 0:f27ce43dee4f 2282 * functions.[set]
cparata 0:f27ce43dee4f 2283 *
cparata 0:f27ce43dee4f 2284 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2285 * @param val change the values of slope_fds in reg TAP_CFG0
cparata 0:f27ce43dee4f 2286 *
cparata 0:f27ce43dee4f 2287 */
cparata 0:f27ce43dee4f 2288 int32_t lsm6dsox_xl_hp_path_internal_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2289 lsm6dsox_slope_fds_t val)
cparata 0:f27ce43dee4f 2290 {
cparata 0:f27ce43dee4f 2291 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 2292 int32_t ret;
cparata 0:f27ce43dee4f 2293
cparata 0:f27ce43dee4f 2294 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2295 if (ret == 0) {
cparata 0:f27ce43dee4f 2296 reg.slope_fds = (uint8_t)val;
cparata 0:f27ce43dee4f 2297 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2298 }
cparata 0:f27ce43dee4f 2299 return ret;
cparata 0:f27ce43dee4f 2300 }
cparata 0:f27ce43dee4f 2301
cparata 0:f27ce43dee4f 2302 /**
cparata 0:f27ce43dee4f 2303 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata 0:f27ce43dee4f 2304 * functions.[get]
cparata 0:f27ce43dee4f 2305 *
cparata 0:f27ce43dee4f 2306 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2307 * @param val Change the values of slope_fds in reg TAP_CFG0
cparata 0:f27ce43dee4f 2308 *
cparata 0:f27ce43dee4f 2309 */
cparata 0:f27ce43dee4f 2310 int32_t lsm6dsox_xl_hp_path_internal_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2311 lsm6dsox_slope_fds_t *val)
cparata 0:f27ce43dee4f 2312 {
cparata 0:f27ce43dee4f 2313 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 2314 int32_t ret;
cparata 0:f27ce43dee4f 2315
cparata 0:f27ce43dee4f 2316 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2317 switch (reg.slope_fds) {
cparata 0:f27ce43dee4f 2318 case LSM6DSOX_USE_SLOPE:
cparata 0:f27ce43dee4f 2319 *val = LSM6DSOX_USE_SLOPE;
cparata 0:f27ce43dee4f 2320 break;
cparata 0:f27ce43dee4f 2321 case LSM6DSOX_USE_HPF:
cparata 0:f27ce43dee4f 2322 *val = LSM6DSOX_USE_HPF;
cparata 0:f27ce43dee4f 2323 break;
cparata 0:f27ce43dee4f 2324 default:
cparata 0:f27ce43dee4f 2325 *val = LSM6DSOX_USE_SLOPE;
cparata 0:f27ce43dee4f 2326 break;
cparata 0:f27ce43dee4f 2327 }
cparata 0:f27ce43dee4f 2328 return ret;
cparata 0:f27ce43dee4f 2329 }
cparata 0:f27ce43dee4f 2330
cparata 0:f27ce43dee4f 2331 /**
cparata 0:f27ce43dee4f 2332 * @brief Enables gyroscope digital high-pass filter. The filter is
cparata 0:f27ce43dee4f 2333 * enabled only if the gyro is in HP mode.[set]
cparata 0:f27ce43dee4f 2334 *
cparata 0:f27ce43dee4f 2335 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2336 * @param val Get the values of hp_en_g and hp_en_g
cparata 0:f27ce43dee4f 2337 * in reg CTRL7_G
cparata 0:f27ce43dee4f 2338 *
cparata 0:f27ce43dee4f 2339 */
cparata 0:f27ce43dee4f 2340 int32_t lsm6dsox_gy_hp_path_internal_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2341 lsm6dsox_hpm_g_t val)
cparata 0:f27ce43dee4f 2342 {
cparata 0:f27ce43dee4f 2343 lsm6dsox_ctrl7_g_t reg;
cparata 0:f27ce43dee4f 2344 int32_t ret;
cparata 0:f27ce43dee4f 2345
cparata 0:f27ce43dee4f 2346 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2347 if (ret == 0) {
cparata 0:f27ce43dee4f 2348 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
cparata 0:f27ce43dee4f 2349 reg.hpm_g = (uint8_t)val & 0x03U;
cparata 0:f27ce43dee4f 2350 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2351 }
cparata 0:f27ce43dee4f 2352 return ret;
cparata 0:f27ce43dee4f 2353 }
cparata 0:f27ce43dee4f 2354
cparata 0:f27ce43dee4f 2355 /**
cparata 0:f27ce43dee4f 2356 * @brief Enables gyroscope digital high-pass filter. The filter is
cparata 0:f27ce43dee4f 2357 * enabled only if the gyro is in HP mode.[get]
cparata 0:f27ce43dee4f 2358 *
cparata 0:f27ce43dee4f 2359 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2360 * @param val Get the values of hp_en_g and hp_en_g
cparata 0:f27ce43dee4f 2361 * in reg CTRL7_G
cparata 0:f27ce43dee4f 2362 *
cparata 0:f27ce43dee4f 2363 */
cparata 0:f27ce43dee4f 2364 int32_t lsm6dsox_gy_hp_path_internal_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2365 lsm6dsox_hpm_g_t *val)
cparata 0:f27ce43dee4f 2366 {
cparata 0:f27ce43dee4f 2367 lsm6dsox_ctrl7_g_t reg;
cparata 0:f27ce43dee4f 2368 int32_t ret;
cparata 0:f27ce43dee4f 2369
cparata 0:f27ce43dee4f 2370 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2371 switch ((reg.hp_en_g << 7) + reg.hpm_g) {
cparata 0:f27ce43dee4f 2372 case LSM6DSOX_HP_FILTER_NONE:
cparata 0:f27ce43dee4f 2373 *val = LSM6DSOX_HP_FILTER_NONE;
cparata 0:f27ce43dee4f 2374 break;
cparata 0:f27ce43dee4f 2375 case LSM6DSOX_HP_FILTER_16mHz:
cparata 0:f27ce43dee4f 2376 *val = LSM6DSOX_HP_FILTER_16mHz;
cparata 0:f27ce43dee4f 2377 break;
cparata 0:f27ce43dee4f 2378 case LSM6DSOX_HP_FILTER_65mHz:
cparata 0:f27ce43dee4f 2379 *val = LSM6DSOX_HP_FILTER_65mHz;
cparata 0:f27ce43dee4f 2380 break;
cparata 0:f27ce43dee4f 2381 case LSM6DSOX_HP_FILTER_260mHz:
cparata 0:f27ce43dee4f 2382 *val = LSM6DSOX_HP_FILTER_260mHz;
cparata 0:f27ce43dee4f 2383 break;
cparata 0:f27ce43dee4f 2384 case LSM6DSOX_HP_FILTER_1Hz04:
cparata 0:f27ce43dee4f 2385 *val = LSM6DSOX_HP_FILTER_1Hz04;
cparata 0:f27ce43dee4f 2386 break;
cparata 0:f27ce43dee4f 2387 default:
cparata 0:f27ce43dee4f 2388 *val = LSM6DSOX_HP_FILTER_NONE;
cparata 0:f27ce43dee4f 2389 break;
cparata 0:f27ce43dee4f 2390 }
cparata 0:f27ce43dee4f 2391 return ret;
cparata 0:f27ce43dee4f 2392 }
cparata 0:f27ce43dee4f 2393
cparata 0:f27ce43dee4f 2394 /**
cparata 0:f27ce43dee4f 2395 * @}
cparata 0:f27ce43dee4f 2396 *
cparata 0:f27ce43dee4f 2397 */
cparata 0:f27ce43dee4f 2398
cparata 0:f27ce43dee4f 2399 /**
cparata 0:f27ce43dee4f 2400 * @defgroup LSM6DSOX_ Auxiliary_interface
cparata 0:f27ce43dee4f 2401 * @brief This section groups all the functions concerning
cparata 0:f27ce43dee4f 2402 * auxiliary interface.
cparata 0:f27ce43dee4f 2403 * @{
cparata 0:f27ce43dee4f 2404 *
cparata 0:f27ce43dee4f 2405 */
cparata 0:f27ce43dee4f 2406
cparata 0:f27ce43dee4f 2407 /**
cparata 0:f27ce43dee4f 2408 * @brief OIS data reading from Auxiliary / Main SPI.[set]
cparata 0:f27ce43dee4f 2409 *
cparata 0:f27ce43dee4f 2410 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2411 * @param val change the values of spi2_read_en in reg UI_INT_OIS
cparata 0:f27ce43dee4f 2412 *
cparata 0:f27ce43dee4f 2413 */
cparata 0:f27ce43dee4f 2414 int32_t lsm6dsox_ois_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_spi2_read_en_t val)
cparata 0:f27ce43dee4f 2415 {
cparata 0:f27ce43dee4f 2416 lsm6dsox_func_cfg_access_t func_cfg_access;
cparata 0:f27ce43dee4f 2417 lsm6dsox_ui_int_ois_t ui_int_ois;
cparata 0:f27ce43dee4f 2418 int32_t ret;
cparata 0:f27ce43dee4f 2419
cparata 0:f27ce43dee4f 2420 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1);
cparata 0:f27ce43dee4f 2421 if (ret == 0) {
cparata 0:f27ce43dee4f 2422 ui_int_ois.spi2_read_en = ((uint8_t)val & 0x01U);
cparata 0:f27ce43dee4f 2423 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS,
cparata 0:f27ce43dee4f 2424 (uint8_t*)&ui_int_ois, 1);
cparata 0:f27ce43dee4f 2425 }
cparata 0:f27ce43dee4f 2426 if (ret == 0) {
cparata 0:f27ce43dee4f 2427 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
cparata 0:f27ce43dee4f 2428 (uint8_t*)&func_cfg_access, 1);
cparata 0:f27ce43dee4f 2429 }
cparata 0:f27ce43dee4f 2430 if (ret == 0) {
cparata 0:f27ce43dee4f 2431 func_cfg_access.ois_ctrl_from_ui = ( ((uint8_t)val & 0x02U) >> 1 );
cparata 0:f27ce43dee4f 2432 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
cparata 0:f27ce43dee4f 2433 (uint8_t*)&func_cfg_access, 1);
cparata 0:f27ce43dee4f 2434 }
cparata 0:f27ce43dee4f 2435 return ret;
cparata 0:f27ce43dee4f 2436 }
cparata 0:f27ce43dee4f 2437
cparata 0:f27ce43dee4f 2438 /**
cparata 0:f27ce43dee4f 2439 * @brief aux_ois_data: [get] OIS data reading from Auxiliary / Main SPI
cparata 0:f27ce43dee4f 2440 *
cparata 0:f27ce43dee4f 2441 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2442 * @param val Get the values of spi2_read_en
cparata 0:f27ce43dee4f 2443 * in reg UI_INT_OIS
cparata 0:f27ce43dee4f 2444 *
cparata 0:f27ce43dee4f 2445 */
cparata 0:f27ce43dee4f 2446 int32_t lsm6dsox_ois_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2447 lsm6dsox_spi2_read_en_t *val)
cparata 0:f27ce43dee4f 2448 {
cparata 0:f27ce43dee4f 2449 lsm6dsox_func_cfg_access_t func_cfg_access;
cparata 0:f27ce43dee4f 2450 lsm6dsox_ui_int_ois_t ui_int_ois;
cparata 0:f27ce43dee4f 2451 int32_t ret;
cparata 0:f27ce43dee4f 2452
cparata 0:f27ce43dee4f 2453 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1);
cparata 0:f27ce43dee4f 2454 if (ret == 0) {
cparata 0:f27ce43dee4f 2455 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
cparata 0:f27ce43dee4f 2456 (uint8_t*)&func_cfg_access, 1);
cparata 0:f27ce43dee4f 2457 }
cparata 0:f27ce43dee4f 2458 switch ((func_cfg_access.ois_ctrl_from_ui << 1) + ui_int_ois.spi2_read_en) {
cparata 0:f27ce43dee4f 2459 case LSM6DSOX_OIS_CTRL_AUX_DATA_UI:
cparata 0:f27ce43dee4f 2460 *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI;
cparata 0:f27ce43dee4f 2461 break;
cparata 0:f27ce43dee4f 2462 case LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX:
cparata 0:f27ce43dee4f 2463 *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX;
cparata 0:f27ce43dee4f 2464 break;
cparata 0:f27ce43dee4f 2465 case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI:
cparata 0:f27ce43dee4f 2466 *val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI;
cparata 0:f27ce43dee4f 2467 break;
cparata 0:f27ce43dee4f 2468 case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX:
cparata 0:f27ce43dee4f 2469 *val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX;
cparata 0:f27ce43dee4f 2470 break;
cparata 0:f27ce43dee4f 2471 default:
cparata 0:f27ce43dee4f 2472 *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI;
cparata 0:f27ce43dee4f 2473 break;
cparata 0:f27ce43dee4f 2474 }
cparata 0:f27ce43dee4f 2475 return ret;
cparata 0:f27ce43dee4f 2476 }
cparata 0:f27ce43dee4f 2477
cparata 0:f27ce43dee4f 2478 /**
cparata 0:f27ce43dee4f 2479 * @brief aOn auxiliary interface connect/disconnect SDO and OCS
cparata 0:f27ce43dee4f 2480 * internal pull-up.[set]
cparata 0:f27ce43dee4f 2481 *
cparata 0:f27ce43dee4f 2482 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2483 * @param val change the values of ois_pu_dis in
cparata 0:f27ce43dee4f 2484 * reg PIN_CTRL
cparata 0:f27ce43dee4f 2485 *
cparata 0:f27ce43dee4f 2486 */
cparata 0:f27ce43dee4f 2487 int32_t lsm6dsox_aux_sdo_ocs_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2488 lsm6dsox_ois_pu_dis_t val)
cparata 0:f27ce43dee4f 2489 {
cparata 0:f27ce43dee4f 2490 lsm6dsox_pin_ctrl_t reg;
cparata 0:f27ce43dee4f 2491 int32_t ret;
cparata 0:f27ce43dee4f 2492
cparata 0:f27ce43dee4f 2493 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2494 if (ret == 0) {
cparata 0:f27ce43dee4f 2495 reg.ois_pu_dis = (uint8_t)val;
cparata 0:f27ce43dee4f 2496 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2497 }
cparata 0:f27ce43dee4f 2498 return ret;
cparata 0:f27ce43dee4f 2499 }
cparata 0:f27ce43dee4f 2500
cparata 0:f27ce43dee4f 2501 /**
cparata 0:f27ce43dee4f 2502 * @brief On auxiliary interface connect/disconnect SDO and OCS
cparata 0:f27ce43dee4f 2503 * internal pull-up.[get]
cparata 0:f27ce43dee4f 2504 *
cparata 0:f27ce43dee4f 2505 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2506 * @param val Get the values of ois_pu_dis in reg PIN_CTRL
cparata 0:f27ce43dee4f 2507 *
cparata 0:f27ce43dee4f 2508 */
cparata 0:f27ce43dee4f 2509 int32_t lsm6dsox_aux_sdo_ocs_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2510 lsm6dsox_ois_pu_dis_t *val)
cparata 0:f27ce43dee4f 2511 {
cparata 0:f27ce43dee4f 2512 lsm6dsox_pin_ctrl_t reg;
cparata 0:f27ce43dee4f 2513 int32_t ret;
cparata 0:f27ce43dee4f 2514
cparata 0:f27ce43dee4f 2515 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2516 switch (reg.ois_pu_dis) {
cparata 0:f27ce43dee4f 2517 case LSM6DSOX_AUX_PULL_UP_DISC:
cparata 0:f27ce43dee4f 2518 *val = LSM6DSOX_AUX_PULL_UP_DISC;
cparata 0:f27ce43dee4f 2519 break;
cparata 0:f27ce43dee4f 2520 case LSM6DSOX_AUX_PULL_UP_CONNECT:
cparata 0:f27ce43dee4f 2521 *val = LSM6DSOX_AUX_PULL_UP_CONNECT;
cparata 0:f27ce43dee4f 2522 break;
cparata 0:f27ce43dee4f 2523 default:
cparata 0:f27ce43dee4f 2524 *val = LSM6DSOX_AUX_PULL_UP_DISC;
cparata 0:f27ce43dee4f 2525 break;
cparata 0:f27ce43dee4f 2526 }
cparata 0:f27ce43dee4f 2527 return ret;
cparata 0:f27ce43dee4f 2528 }
cparata 0:f27ce43dee4f 2529
cparata 0:f27ce43dee4f 2530 /**
cparata 0:f27ce43dee4f 2531 * @brief OIS chain on aux interface power on mode.[set]
cparata 0:f27ce43dee4f 2532 *
cparata 0:f27ce43dee4f 2533 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2534 * @param val change the values of ois_on in reg CTRL7_G
cparata 0:f27ce43dee4f 2535 *
cparata 0:f27ce43dee4f 2536 */
cparata 0:f27ce43dee4f 2537 int32_t lsm6dsox_aux_pw_on_ctrl_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t val)
cparata 0:f27ce43dee4f 2538 {
cparata 0:f27ce43dee4f 2539 lsm6dsox_ctrl7_g_t reg;
cparata 0:f27ce43dee4f 2540 int32_t ret;
cparata 0:f27ce43dee4f 2541
cparata 0:f27ce43dee4f 2542 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2543 if (ret == 0) {
cparata 0:f27ce43dee4f 2544 reg.ois_on_en = (uint8_t)val & 0x01U;
cparata 0:f27ce43dee4f 2545 reg.ois_on = (uint8_t)val & 0x01U;
cparata 0:f27ce43dee4f 2546 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2547 }
cparata 0:f27ce43dee4f 2548 return ret;
cparata 0:f27ce43dee4f 2549 }
cparata 0:f27ce43dee4f 2550
cparata 0:f27ce43dee4f 2551 /**
cparata 0:f27ce43dee4f 2552 * @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode
cparata 0:f27ce43dee4f 2553 *
cparata 0:f27ce43dee4f 2554 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2555 * @param val Get the values of ois_on in reg CTRL7_G
cparata 0:f27ce43dee4f 2556 *
cparata 0:f27ce43dee4f 2557 */
cparata 0:f27ce43dee4f 2558 int32_t lsm6dsox_aux_pw_on_ctrl_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t *val)
cparata 0:f27ce43dee4f 2559 {
cparata 0:f27ce43dee4f 2560 lsm6dsox_ctrl7_g_t reg;
cparata 0:f27ce43dee4f 2561 int32_t ret;
cparata 0:f27ce43dee4f 2562
cparata 0:f27ce43dee4f 2563 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2564 switch (reg.ois_on) {
cparata 0:f27ce43dee4f 2565 case LSM6DSOX_AUX_ON:
cparata 0:f27ce43dee4f 2566 *val = LSM6DSOX_AUX_ON;
cparata 0:f27ce43dee4f 2567 break;
cparata 0:f27ce43dee4f 2568 case LSM6DSOX_AUX_ON_BY_AUX_INTERFACE:
cparata 0:f27ce43dee4f 2569 *val = LSM6DSOX_AUX_ON_BY_AUX_INTERFACE;
cparata 0:f27ce43dee4f 2570 break;
cparata 0:f27ce43dee4f 2571 default:
cparata 0:f27ce43dee4f 2572 *val = LSM6DSOX_AUX_ON;
cparata 0:f27ce43dee4f 2573 break;
cparata 0:f27ce43dee4f 2574 }
cparata 0:f27ce43dee4f 2575
cparata 0:f27ce43dee4f 2576 return ret;
cparata 0:f27ce43dee4f 2577 }
cparata 0:f27ce43dee4f 2578
cparata 0:f27ce43dee4f 2579 /**
cparata 0:f27ce43dee4f 2580 * @brief Accelerometer full-scale management between UI chain and
cparata 0:f27ce43dee4f 2581 * OIS chain. When XL UI is on, the full scale is the same
cparata 0:f27ce43dee4f 2582 * between UI/OIS and is chosen by the UI CTRL registers;
cparata 0:f27ce43dee4f 2583 * when XL UI is in PD, the OIS can choose the FS.
cparata 0:f27ce43dee4f 2584 * Full scales are independent between the UI/OIS chain
cparata 0:f27ce43dee4f 2585 * but both bound to 8 g.[set]
cparata 0:f27ce43dee4f 2586 *
cparata 0:f27ce43dee4f 2587 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2588 * @param val change the values of xl_fs_mode in
cparata 0:f27ce43dee4f 2589 * reg CTRL8_XL
cparata 0:f27ce43dee4f 2590 *
cparata 0:f27ce43dee4f 2591 */
cparata 0:f27ce43dee4f 2592 int32_t lsm6dsox_aux_xl_fs_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2593 lsm6dsox_xl_fs_mode_t val)
cparata 0:f27ce43dee4f 2594 {
cparata 0:f27ce43dee4f 2595 lsm6dsox_ctrl8_xl_t reg;
cparata 0:f27ce43dee4f 2596 int32_t ret;
cparata 0:f27ce43dee4f 2597
cparata 0:f27ce43dee4f 2598 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2599 if (ret == 0) {
cparata 0:f27ce43dee4f 2600 reg.xl_fs_mode = (uint8_t)val;
cparata 0:f27ce43dee4f 2601 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2602 }
cparata 0:f27ce43dee4f 2603 return ret;
cparata 0:f27ce43dee4f 2604 }
cparata 0:f27ce43dee4f 2605
cparata 0:f27ce43dee4f 2606 /**
cparata 0:f27ce43dee4f 2607 * @brief Accelerometer full-scale management between UI chain and
cparata 0:f27ce43dee4f 2608 * OIS chain. When XL UI is on, the full scale is the same
cparata 0:f27ce43dee4f 2609 * between UI/OIS and is chosen by the UI CTRL registers;
cparata 0:f27ce43dee4f 2610 * when XL UI is in PD, the OIS can choose the FS.
cparata 0:f27ce43dee4f 2611 * Full scales are independent between the UI/OIS chain
cparata 0:f27ce43dee4f 2612 * but both bound to 8 g.[get]
cparata 0:f27ce43dee4f 2613 *
cparata 0:f27ce43dee4f 2614 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2615 * @param val Get the values of xl_fs_mode in reg CTRL8_XL
cparata 0:f27ce43dee4f 2616 *
cparata 0:f27ce43dee4f 2617 */
cparata 0:f27ce43dee4f 2618 int32_t lsm6dsox_aux_xl_fs_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2619 lsm6dsox_xl_fs_mode_t *val)
cparata 0:f27ce43dee4f 2620 {
cparata 0:f27ce43dee4f 2621 lsm6dsox_ctrl8_xl_t reg;
cparata 0:f27ce43dee4f 2622 int32_t ret;
cparata 0:f27ce43dee4f 2623
cparata 0:f27ce43dee4f 2624 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2625 switch (reg.xl_fs_mode) {
cparata 0:f27ce43dee4f 2626 case LSM6DSOX_USE_SAME_XL_FS:
cparata 0:f27ce43dee4f 2627 *val = LSM6DSOX_USE_SAME_XL_FS;
cparata 0:f27ce43dee4f 2628 break;
cparata 0:f27ce43dee4f 2629 case LSM6DSOX_USE_DIFFERENT_XL_FS:
cparata 0:f27ce43dee4f 2630 *val = LSM6DSOX_USE_DIFFERENT_XL_FS;
cparata 0:f27ce43dee4f 2631 break;
cparata 0:f27ce43dee4f 2632 default:
cparata 0:f27ce43dee4f 2633 *val = LSM6DSOX_USE_SAME_XL_FS;
cparata 0:f27ce43dee4f 2634 break;
cparata 0:f27ce43dee4f 2635 }
cparata 0:f27ce43dee4f 2636
cparata 0:f27ce43dee4f 2637 return ret;
cparata 0:f27ce43dee4f 2638 }
cparata 0:f27ce43dee4f 2639
cparata 0:f27ce43dee4f 2640 /**
cparata 0:f27ce43dee4f 2641 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
cparata 0:f27ce43dee4f 2642 *
cparata 0:f27ce43dee4f 2643 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2644 * @param val Get registers STATUS_SPIAUX
cparata 0:f27ce43dee4f 2645 *
cparata 0:f27ce43dee4f 2646 */
cparata 0:f27ce43dee4f 2647 int32_t lsm6dsox_aux_status_reg_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2648 lsm6dsox_spi2_status_reg_ois_t *val)
cparata 0:f27ce43dee4f 2649 {
cparata 0:f27ce43dee4f 2650 int32_t ret;
cparata 0:f27ce43dee4f 2651 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*) val, 1);
cparata 0:f27ce43dee4f 2652 return ret;
cparata 0:f27ce43dee4f 2653 }
cparata 0:f27ce43dee4f 2654
cparata 0:f27ce43dee4f 2655 /**
cparata 0:f27ce43dee4f 2656 * @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available
cparata 0:f27ce43dee4f 2657 *
cparata 0:f27ce43dee4f 2658 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2659 * @param val change the values of xlda in reg STATUS_SPIAUX
cparata 0:f27ce43dee4f 2660 *
cparata 0:f27ce43dee4f 2661 */
cparata 0:f27ce43dee4f 2662 int32_t lsm6dsox_aux_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 2663 {
cparata 0:f27ce43dee4f 2664 lsm6dsox_spi2_status_reg_ois_t reg;
cparata 0:f27ce43dee4f 2665 int32_t ret;
cparata 0:f27ce43dee4f 2666
cparata 0:f27ce43dee4f 2667 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2668 *val = reg.xlda;
cparata 0:f27ce43dee4f 2669
cparata 0:f27ce43dee4f 2670 return ret;
cparata 0:f27ce43dee4f 2671 }
cparata 0:f27ce43dee4f 2672
cparata 0:f27ce43dee4f 2673 /**
cparata 0:f27ce43dee4f 2674 * @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available.
cparata 0:f27ce43dee4f 2675 *
cparata 0:f27ce43dee4f 2676 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2677 * @param val change the values of gda in reg STATUS_SPIAUX
cparata 0:f27ce43dee4f 2678 *
cparata 0:f27ce43dee4f 2679 */
cparata 0:f27ce43dee4f 2680 int32_t lsm6dsox_aux_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 2681 {
cparata 0:f27ce43dee4f 2682 lsm6dsox_spi2_status_reg_ois_t reg;
cparata 0:f27ce43dee4f 2683 int32_t ret;
cparata 0:f27ce43dee4f 2684
cparata 0:f27ce43dee4f 2685 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2686 *val = reg.gda;
cparata 0:f27ce43dee4f 2687
cparata 0:f27ce43dee4f 2688 return ret;
cparata 0:f27ce43dee4f 2689 }
cparata 0:f27ce43dee4f 2690
cparata 0:f27ce43dee4f 2691 /**
cparata 0:f27ce43dee4f 2692 * @brief High when the gyroscope output is in the settling phase.[get]
cparata 0:f27ce43dee4f 2693 *
cparata 0:f27ce43dee4f 2694 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2695 * @param val change the values of gyro_settling in reg STATUS_SPIAUX
cparata 0:f27ce43dee4f 2696 *
cparata 0:f27ce43dee4f 2697 */
cparata 0:f27ce43dee4f 2698 int32_t lsm6dsox_aux_gy_flag_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 2699 {
cparata 0:f27ce43dee4f 2700 lsm6dsox_spi2_status_reg_ois_t reg;
cparata 0:f27ce43dee4f 2701 int32_t ret;
cparata 0:f27ce43dee4f 2702
cparata 0:f27ce43dee4f 2703 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2704 *val = reg.gyro_settling;
cparata 0:f27ce43dee4f 2705
cparata 0:f27ce43dee4f 2706 return ret;
cparata 0:f27ce43dee4f 2707 }
cparata 0:f27ce43dee4f 2708
cparata 0:f27ce43dee4f 2709 /**
cparata 0:f27ce43dee4f 2710 * @brief Indicates polarity of DEN signal on OIS chain.[set]
cparata 0:f27ce43dee4f 2711 *
cparata 0:f27ce43dee4f 2712 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2713 * @param val change the values of den_lh_ois in
cparata 0:f27ce43dee4f 2714 * reg INT_OIS
cparata 0:f27ce43dee4f 2715 *
cparata 0:f27ce43dee4f 2716 */
cparata 0:f27ce43dee4f 2717 int32_t lsm6dsox_aux_den_polarity_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2718 lsm6dsox_den_lh_ois_t val)
cparata 0:f27ce43dee4f 2719 {
cparata 0:f27ce43dee4f 2720 lsm6dsox_ui_int_ois_t reg;
cparata 0:f27ce43dee4f 2721 int32_t ret;
cparata 0:f27ce43dee4f 2722
cparata 0:f27ce43dee4f 2723 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2724 if (ret == 0) {
cparata 0:f27ce43dee4f 2725 reg.den_lh_ois = (uint8_t)val;
cparata 0:f27ce43dee4f 2726 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2727 }
cparata 0:f27ce43dee4f 2728 return ret;
cparata 0:f27ce43dee4f 2729 }
cparata 0:f27ce43dee4f 2730
cparata 0:f27ce43dee4f 2731 /**
cparata 0:f27ce43dee4f 2732 * @brief Indicates polarity of DEN signal on OIS chain.[get]
cparata 0:f27ce43dee4f 2733 *
cparata 0:f27ce43dee4f 2734 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2735 * @param val Get the values of den_lh_ois in reg INT_OIS
cparata 0:f27ce43dee4f 2736 *
cparata 0:f27ce43dee4f 2737 */
cparata 0:f27ce43dee4f 2738 int32_t lsm6dsox_aux_den_polarity_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2739 lsm6dsox_den_lh_ois_t *val)
cparata 0:f27ce43dee4f 2740 {
cparata 0:f27ce43dee4f 2741 lsm6dsox_ui_int_ois_t reg;
cparata 0:f27ce43dee4f 2742 int32_t ret;
cparata 0:f27ce43dee4f 2743
cparata 0:f27ce43dee4f 2744 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2745 switch (reg.den_lh_ois) {
cparata 0:f27ce43dee4f 2746 case LSM6DSOX_AUX_DEN_ACTIVE_LOW:
cparata 0:f27ce43dee4f 2747 *val = LSM6DSOX_AUX_DEN_ACTIVE_LOW;
cparata 0:f27ce43dee4f 2748 break;
cparata 0:f27ce43dee4f 2749 case LSM6DSOX_AUX_DEN_ACTIVE_HIGH:
cparata 0:f27ce43dee4f 2750 *val = LSM6DSOX_AUX_DEN_ACTIVE_HIGH;
cparata 0:f27ce43dee4f 2751 break;
cparata 0:f27ce43dee4f 2752 default:
cparata 0:f27ce43dee4f 2753 *val = LSM6DSOX_AUX_DEN_ACTIVE_LOW;
cparata 0:f27ce43dee4f 2754 break;
cparata 0:f27ce43dee4f 2755 }
cparata 0:f27ce43dee4f 2756 return ret;
cparata 0:f27ce43dee4f 2757 }
cparata 0:f27ce43dee4f 2758
cparata 0:f27ce43dee4f 2759 /**
cparata 0:f27ce43dee4f 2760 * @brief Configure DEN mode on the OIS chain.[set]
cparata 0:f27ce43dee4f 2761 *
cparata 0:f27ce43dee4f 2762 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2763 * @param val change the values of lvl2_ois in reg INT_OIS
cparata 0:f27ce43dee4f 2764 *
cparata 0:f27ce43dee4f 2765 */
cparata 0:f27ce43dee4f 2766 int32_t lsm6dsox_aux_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lvl2_ois_t val)
cparata 0:f27ce43dee4f 2767 {
cparata 0:f27ce43dee4f 2768 lsm6dsox_ui_ctrl1_ois_t ctrl1_ois;
cparata 0:f27ce43dee4f 2769 lsm6dsox_ui_int_ois_t int_ois;
cparata 0:f27ce43dee4f 2770 int32_t ret;
cparata 0:f27ce43dee4f 2771
cparata 0:f27ce43dee4f 2772 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1);
cparata 0:f27ce43dee4f 2773 if (ret == 0) {
cparata 0:f27ce43dee4f 2774 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
cparata 0:f27ce43dee4f 2775 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1);
cparata 0:f27ce43dee4f 2776 }
cparata 0:f27ce43dee4f 2777 if (ret == 0) {
cparata 0:f27ce43dee4f 2778 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata 0:f27ce43dee4f 2779 }
cparata 0:f27ce43dee4f 2780 if (ret == 0) {
cparata 0:f27ce43dee4f 2781 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
cparata 0:f27ce43dee4f 2782 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata 0:f27ce43dee4f 2783 }
cparata 0:f27ce43dee4f 2784 return ret;
cparata 0:f27ce43dee4f 2785 }
cparata 0:f27ce43dee4f 2786
cparata 0:f27ce43dee4f 2787 /**
cparata 0:f27ce43dee4f 2788 * @brief Configure DEN mode on the OIS chain.[get]
cparata 0:f27ce43dee4f 2789 *
cparata 0:f27ce43dee4f 2790 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2791 * @param val Get the values of lvl2_ois in reg INT_OIS
cparata 0:f27ce43dee4f 2792 *
cparata 0:f27ce43dee4f 2793 */
cparata 0:f27ce43dee4f 2794 int32_t lsm6dsox_aux_den_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_lvl2_ois_t *val)
cparata 0:f27ce43dee4f 2795 {
cparata 0:f27ce43dee4f 2796 lsm6dsox_ui_ctrl1_ois_t ctrl1_ois;
cparata 0:f27ce43dee4f 2797 lsm6dsox_ui_int_ois_t int_ois;
cparata 0:f27ce43dee4f 2798 int32_t ret;
cparata 0:f27ce43dee4f 2799
cparata 0:f27ce43dee4f 2800 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1);
cparata 0:f27ce43dee4f 2801 if (ret == 0) {
cparata 0:f27ce43dee4f 2802 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata 0:f27ce43dee4f 2803 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) {
cparata 0:f27ce43dee4f 2804 case LSM6DSOX_AUX_DEN_DISABLE:
cparata 0:f27ce43dee4f 2805 *val = LSM6DSOX_AUX_DEN_DISABLE;
cparata 0:f27ce43dee4f 2806 break;
cparata 0:f27ce43dee4f 2807 case LSM6DSOX_AUX_DEN_LEVEL_LATCH:
cparata 0:f27ce43dee4f 2808 *val = LSM6DSOX_AUX_DEN_LEVEL_LATCH;
cparata 0:f27ce43dee4f 2809 break;
cparata 0:f27ce43dee4f 2810 case LSM6DSOX_AUX_DEN_LEVEL_TRIG:
cparata 0:f27ce43dee4f 2811 *val = LSM6DSOX_AUX_DEN_LEVEL_TRIG;
cparata 0:f27ce43dee4f 2812 break;
cparata 0:f27ce43dee4f 2813 default:
cparata 0:f27ce43dee4f 2814 *val = LSM6DSOX_AUX_DEN_DISABLE;
cparata 0:f27ce43dee4f 2815 break;
cparata 0:f27ce43dee4f 2816 }
cparata 0:f27ce43dee4f 2817 }
cparata 0:f27ce43dee4f 2818 return ret;
cparata 0:f27ce43dee4f 2819 }
cparata 0:f27ce43dee4f 2820
cparata 0:f27ce43dee4f 2821 /**
cparata 0:f27ce43dee4f 2822 * @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata 0:f27ce43dee4f 2823 * This setting has priority over all other INT2 settings.[set]
cparata 0:f27ce43dee4f 2824 *
cparata 0:f27ce43dee4f 2825 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2826 * @param val change the values of int2_drdy_ois in reg INT_OIS
cparata 0:f27ce43dee4f 2827 *
cparata 0:f27ce43dee4f 2828 */
cparata 0:f27ce43dee4f 2829 int32_t lsm6dsox_aux_drdy_on_int2_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 2830 {
cparata 0:f27ce43dee4f 2831 lsm6dsox_ui_int_ois_t reg;
cparata 0:f27ce43dee4f 2832 int32_t ret;
cparata 0:f27ce43dee4f 2833
cparata 0:f27ce43dee4f 2834 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2835 if (ret == 0) {
cparata 0:f27ce43dee4f 2836 reg.int2_drdy_ois = val;
cparata 0:f27ce43dee4f 2837 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2838 }
cparata 0:f27ce43dee4f 2839 return ret;
cparata 0:f27ce43dee4f 2840 }
cparata 0:f27ce43dee4f 2841
cparata 0:f27ce43dee4f 2842 /**
cparata 0:f27ce43dee4f 2843 * @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata 0:f27ce43dee4f 2844 * This setting has priority over all other INT2 settings.[get]
cparata 0:f27ce43dee4f 2845 *
cparata 0:f27ce43dee4f 2846 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2847 * @param val change the values of int2_drdy_ois in reg INT_OIS
cparata 0:f27ce43dee4f 2848 *
cparata 0:f27ce43dee4f 2849 */
cparata 0:f27ce43dee4f 2850 int32_t lsm6dsox_aux_drdy_on_int2_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 2851 {
cparata 0:f27ce43dee4f 2852 lsm6dsox_ui_int_ois_t reg;
cparata 0:f27ce43dee4f 2853 int32_t ret;
cparata 0:f27ce43dee4f 2854
cparata 0:f27ce43dee4f 2855 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2856 *val = reg.int2_drdy_ois;
cparata 0:f27ce43dee4f 2857
cparata 0:f27ce43dee4f 2858 return ret;
cparata 0:f27ce43dee4f 2859 }
cparata 0:f27ce43dee4f 2860
cparata 0:f27ce43dee4f 2861 /**
cparata 0:f27ce43dee4f 2862 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata 0:f27ce43dee4f 2863 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata 0:f27ce43dee4f 2864 * When the OIS chain is enabled, the OIS outputs are available
cparata 0:f27ce43dee4f 2865 * through the SPI2 in registers OUTX_L_G (22h) through
cparata 0:f27ce43dee4f 2866 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata 0:f27ce43dee4f 2867 * LPF1 is dedicated to this chain.[set]
cparata 0:f27ce43dee4f 2868 *
cparata 0:f27ce43dee4f 2869 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2870 * @param val change the values of ois_en_spi2 in
cparata 0:f27ce43dee4f 2871 * reg CTRL1_OIS
cparata 0:f27ce43dee4f 2872 *
cparata 0:f27ce43dee4f 2873 */
cparata 0:f27ce43dee4f 2874 int32_t lsm6dsox_aux_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_en_spi2_t val)
cparata 0:f27ce43dee4f 2875 {
cparata 0:f27ce43dee4f 2876 lsm6dsox_ui_ctrl1_ois_t reg;
cparata 0:f27ce43dee4f 2877 int32_t ret;
cparata 0:f27ce43dee4f 2878
cparata 0:f27ce43dee4f 2879 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2880 if (ret == 0) {
cparata 0:f27ce43dee4f 2881 reg.ois_en_spi2 = (uint8_t)val & 0x01U;
cparata 0:f27ce43dee4f 2882 reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
cparata 0:f27ce43dee4f 2883 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2884 }
cparata 0:f27ce43dee4f 2885 return ret;
cparata 0:f27ce43dee4f 2886 }
cparata 0:f27ce43dee4f 2887
cparata 0:f27ce43dee4f 2888 /**
cparata 0:f27ce43dee4f 2889 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata 0:f27ce43dee4f 2890 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata 0:f27ce43dee4f 2891 * When the OIS chain is enabled, the OIS outputs are available
cparata 0:f27ce43dee4f 2892 * through the SPI2 in registers OUTX_L_G (22h) through
cparata 0:f27ce43dee4f 2893 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata 0:f27ce43dee4f 2894 * LPF1 is dedicated to this chain.[get]
cparata 0:f27ce43dee4f 2895 *
cparata 0:f27ce43dee4f 2896 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2897 * @param val Get the values of ois_en_spi2 in
cparata 0:f27ce43dee4f 2898 * reg CTRL1_OIS
cparata 0:f27ce43dee4f 2899 *
cparata 0:f27ce43dee4f 2900 */
cparata 0:f27ce43dee4f 2901 int32_t lsm6dsox_aux_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_en_spi2_t *val)
cparata 0:f27ce43dee4f 2902 {
cparata 0:f27ce43dee4f 2903 lsm6dsox_ui_ctrl1_ois_t reg;
cparata 0:f27ce43dee4f 2904 int32_t ret;
cparata 0:f27ce43dee4f 2905
cparata 0:f27ce43dee4f 2906 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2907 switch ((reg.mode4_en << 1) | reg.ois_en_spi2) {
cparata 0:f27ce43dee4f 2908 case LSM6DSOX_AUX_DISABLE:
cparata 0:f27ce43dee4f 2909 *val = LSM6DSOX_AUX_DISABLE;
cparata 0:f27ce43dee4f 2910 break;
cparata 0:f27ce43dee4f 2911 case LSM6DSOX_MODE_3_GY:
cparata 0:f27ce43dee4f 2912 *val = LSM6DSOX_MODE_3_GY;
cparata 0:f27ce43dee4f 2913 break;
cparata 0:f27ce43dee4f 2914 case LSM6DSOX_MODE_4_GY_XL:
cparata 0:f27ce43dee4f 2915 *val = LSM6DSOX_MODE_4_GY_XL;
cparata 0:f27ce43dee4f 2916 break;
cparata 0:f27ce43dee4f 2917 default:
cparata 0:f27ce43dee4f 2918 *val = LSM6DSOX_AUX_DISABLE;
cparata 0:f27ce43dee4f 2919 break;
cparata 0:f27ce43dee4f 2920 }
cparata 0:f27ce43dee4f 2921 return ret;
cparata 0:f27ce43dee4f 2922 }
cparata 0:f27ce43dee4f 2923
cparata 0:f27ce43dee4f 2924 /**
cparata 0:f27ce43dee4f 2925 * @brief Selects gyroscope OIS chain full-scale.[set]
cparata 0:f27ce43dee4f 2926 *
cparata 0:f27ce43dee4f 2927 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2928 * @param val change the values of fs_g_ois in reg CTRL1_OIS
cparata 0:f27ce43dee4f 2929 *
cparata 0:f27ce43dee4f 2930 */
cparata 0:f27ce43dee4f 2931 int32_t lsm6dsox_aux_gy_full_scale_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2932 lsm6dsox_fs_g_ois_t val)
cparata 0:f27ce43dee4f 2933 {
cparata 0:f27ce43dee4f 2934 lsm6dsox_ui_ctrl1_ois_t reg;
cparata 0:f27ce43dee4f 2935 int32_t ret;
cparata 0:f27ce43dee4f 2936
cparata 0:f27ce43dee4f 2937 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2938 if (ret == 0) {
cparata 0:f27ce43dee4f 2939 reg.fs_g_ois = (uint8_t)val;
cparata 0:f27ce43dee4f 2940 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2941 }
cparata 0:f27ce43dee4f 2942 return ret;
cparata 0:f27ce43dee4f 2943 }
cparata 0:f27ce43dee4f 2944
cparata 0:f27ce43dee4f 2945 /**
cparata 0:f27ce43dee4f 2946 * @brief Selects gyroscope OIS chain full-scale.[get]
cparata 0:f27ce43dee4f 2947 *
cparata 0:f27ce43dee4f 2948 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2949 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
cparata 0:f27ce43dee4f 2950 *
cparata 0:f27ce43dee4f 2951 */
cparata 0:f27ce43dee4f 2952 int32_t lsm6dsox_aux_gy_full_scale_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 2953 lsm6dsox_fs_g_ois_t *val)
cparata 0:f27ce43dee4f 2954 {
cparata 0:f27ce43dee4f 2955 lsm6dsox_ui_ctrl1_ois_t reg;
cparata 0:f27ce43dee4f 2956 int32_t ret;
cparata 0:f27ce43dee4f 2957
cparata 0:f27ce43dee4f 2958 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2959 switch (reg.fs_g_ois) {
cparata 0:f27ce43dee4f 2960 case LSM6DSOX_250dps_AUX:
cparata 0:f27ce43dee4f 2961 *val = LSM6DSOX_250dps_AUX;
cparata 0:f27ce43dee4f 2962 break;
cparata 0:f27ce43dee4f 2963 case LSM6DSOX_125dps_AUX:
cparata 0:f27ce43dee4f 2964 *val = LSM6DSOX_125dps_AUX;
cparata 0:f27ce43dee4f 2965 break;
cparata 0:f27ce43dee4f 2966 case LSM6DSOX_500dps_AUX:
cparata 0:f27ce43dee4f 2967 *val = LSM6DSOX_500dps_AUX;
cparata 0:f27ce43dee4f 2968 break;
cparata 0:f27ce43dee4f 2969 case LSM6DSOX_1000dps_AUX:
cparata 0:f27ce43dee4f 2970 *val = LSM6DSOX_1000dps_AUX;
cparata 0:f27ce43dee4f 2971 break;
cparata 0:f27ce43dee4f 2972 case LSM6DSOX_2000dps_AUX:
cparata 0:f27ce43dee4f 2973 *val = LSM6DSOX_2000dps_AUX;
cparata 0:f27ce43dee4f 2974 break;
cparata 0:f27ce43dee4f 2975 default:
cparata 0:f27ce43dee4f 2976 *val = LSM6DSOX_250dps_AUX;
cparata 0:f27ce43dee4f 2977 break;
cparata 0:f27ce43dee4f 2978 }
cparata 0:f27ce43dee4f 2979 return ret;
cparata 0:f27ce43dee4f 2980 }
cparata 0:f27ce43dee4f 2981
cparata 0:f27ce43dee4f 2982 /**
cparata 0:f27ce43dee4f 2983 * @brief SPI2 3- or 4-wire interface.[set]
cparata 0:f27ce43dee4f 2984 *
cparata 0:f27ce43dee4f 2985 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 2986 * @param val change the values of sim_ois in reg CTRL1_OIS
cparata 0:f27ce43dee4f 2987 *
cparata 0:f27ce43dee4f 2988 */
cparata 0:f27ce43dee4f 2989 int32_t lsm6dsox_aux_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_ois_t val)
cparata 0:f27ce43dee4f 2990 {
cparata 0:f27ce43dee4f 2991 lsm6dsox_ui_ctrl1_ois_t reg;
cparata 0:f27ce43dee4f 2992 int32_t ret;
cparata 0:f27ce43dee4f 2993
cparata 0:f27ce43dee4f 2994 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2995 if (ret == 0) {
cparata 0:f27ce43dee4f 2996 reg.sim_ois = (uint8_t)val;
cparata 0:f27ce43dee4f 2997 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 2998 }
cparata 0:f27ce43dee4f 2999 return ret;
cparata 0:f27ce43dee4f 3000 }
cparata 0:f27ce43dee4f 3001
cparata 0:f27ce43dee4f 3002 /**
cparata 0:f27ce43dee4f 3003 * @brief SPI2 3- or 4-wire interface.[get]
cparata 0:f27ce43dee4f 3004 *
cparata 0:f27ce43dee4f 3005 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3006 * @param val Get the values of sim_ois in reg CTRL1_OIS
cparata 0:f27ce43dee4f 3007 *
cparata 0:f27ce43dee4f 3008 */
cparata 0:f27ce43dee4f 3009 int32_t lsm6dsox_aux_spi_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_ois_t *val)
cparata 0:f27ce43dee4f 3010 {
cparata 0:f27ce43dee4f 3011 lsm6dsox_ui_ctrl1_ois_t reg;
cparata 0:f27ce43dee4f 3012 int32_t ret;
cparata 0:f27ce43dee4f 3013
cparata 0:f27ce43dee4f 3014 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3015 switch (reg.sim_ois) {
cparata 0:f27ce43dee4f 3016 case LSM6DSOX_AUX_SPI_4_WIRE:
cparata 0:f27ce43dee4f 3017 *val = LSM6DSOX_AUX_SPI_4_WIRE;
cparata 0:f27ce43dee4f 3018 break;
cparata 0:f27ce43dee4f 3019 case LSM6DSOX_AUX_SPI_3_WIRE:
cparata 0:f27ce43dee4f 3020 *val = LSM6DSOX_AUX_SPI_3_WIRE;
cparata 0:f27ce43dee4f 3021 break;
cparata 0:f27ce43dee4f 3022 default:
cparata 0:f27ce43dee4f 3023 *val = LSM6DSOX_AUX_SPI_4_WIRE;
cparata 0:f27ce43dee4f 3024 break;
cparata 0:f27ce43dee4f 3025 }
cparata 0:f27ce43dee4f 3026 return ret;
cparata 0:f27ce43dee4f 3027 }
cparata 0:f27ce43dee4f 3028
cparata 0:f27ce43dee4f 3029 /**
cparata 0:f27ce43dee4f 3030 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
cparata 0:f27ce43dee4f 3031 *
cparata 0:f27ce43dee4f 3032 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3033 * @param val change the values of ftype_ois in
cparata 0:f27ce43dee4f 3034 * reg CTRL2_OIS
cparata 0:f27ce43dee4f 3035 *
cparata 0:f27ce43dee4f 3036 */
cparata 0:f27ce43dee4f 3037 int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3038 lsm6dsox_ftype_ois_t val)
cparata 0:f27ce43dee4f 3039 {
cparata 0:f27ce43dee4f 3040 lsm6dsox_ui_ctrl2_ois_t reg;
cparata 0:f27ce43dee4f 3041 int32_t ret;
cparata 0:f27ce43dee4f 3042
cparata 0:f27ce43dee4f 3043 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3044 if (ret == 0) {
cparata 0:f27ce43dee4f 3045 reg.ftype_ois = (uint8_t)val;
cparata 0:f27ce43dee4f 3046 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3047 }
cparata 0:f27ce43dee4f 3048 return ret;
cparata 0:f27ce43dee4f 3049 }
cparata 0:f27ce43dee4f 3050
cparata 0:f27ce43dee4f 3051 /**
cparata 0:f27ce43dee4f 3052 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
cparata 0:f27ce43dee4f 3053 *
cparata 0:f27ce43dee4f 3054 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3055 * @param val Get the values of ftype_ois in reg CTRL2_OIS
cparata 0:f27ce43dee4f 3056 *
cparata 0:f27ce43dee4f 3057 */
cparata 0:f27ce43dee4f 3058 int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3059 lsm6dsox_ftype_ois_t *val)
cparata 0:f27ce43dee4f 3060 {
cparata 0:f27ce43dee4f 3061 lsm6dsox_ui_ctrl2_ois_t reg;
cparata 0:f27ce43dee4f 3062 int32_t ret;
cparata 0:f27ce43dee4f 3063
cparata 0:f27ce43dee4f 3064 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3065 switch (reg.ftype_ois) {
cparata 0:f27ce43dee4f 3066 case LSM6DSOX_351Hz39:
cparata 0:f27ce43dee4f 3067 *val = LSM6DSOX_351Hz39;
cparata 0:f27ce43dee4f 3068 break;
cparata 0:f27ce43dee4f 3069 case LSM6DSOX_236Hz63:
cparata 0:f27ce43dee4f 3070 *val = LSM6DSOX_236Hz63;
cparata 0:f27ce43dee4f 3071 break;
cparata 0:f27ce43dee4f 3072 case LSM6DSOX_172Hz70:
cparata 0:f27ce43dee4f 3073 *val = LSM6DSOX_172Hz70;
cparata 0:f27ce43dee4f 3074 break;
cparata 0:f27ce43dee4f 3075 case LSM6DSOX_937Hz91:
cparata 0:f27ce43dee4f 3076 *val = LSM6DSOX_937Hz91;
cparata 0:f27ce43dee4f 3077 break;
cparata 0:f27ce43dee4f 3078 default:
cparata 0:f27ce43dee4f 3079 *val = LSM6DSOX_351Hz39;
cparata 0:f27ce43dee4f 3080 break;
cparata 0:f27ce43dee4f 3081 }
cparata 0:f27ce43dee4f 3082 return ret;
cparata 0:f27ce43dee4f 3083 }
cparata 0:f27ce43dee4f 3084
cparata 0:f27ce43dee4f 3085 /**
cparata 0:f27ce43dee4f 3086 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
cparata 0:f27ce43dee4f 3087 *
cparata 0:f27ce43dee4f 3088 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3089 * @param val change the values of hpm_ois in reg CTRL2_OIS
cparata 0:f27ce43dee4f 3090 *
cparata 0:f27ce43dee4f 3091 */
cparata 0:f27ce43dee4f 3092 int32_t lsm6dsox_aux_gy_hp_bandwidth_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3093 lsm6dsox_hpm_ois_t val)
cparata 0:f27ce43dee4f 3094 {
cparata 0:f27ce43dee4f 3095 lsm6dsox_ui_ctrl2_ois_t reg;
cparata 0:f27ce43dee4f 3096 int32_t ret;
cparata 0:f27ce43dee4f 3097
cparata 0:f27ce43dee4f 3098 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3099 if (ret == 0) {
cparata 0:f27ce43dee4f 3100 reg.hpm_ois = (uint8_t)val & 0x03U;
cparata 0:f27ce43dee4f 3101 reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
cparata 0:f27ce43dee4f 3102 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3103 }
cparata 0:f27ce43dee4f 3104 return ret;
cparata 0:f27ce43dee4f 3105 }
cparata 0:f27ce43dee4f 3106
cparata 0:f27ce43dee4f 3107 /**
cparata 0:f27ce43dee4f 3108 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
cparata 0:f27ce43dee4f 3109 *
cparata 0:f27ce43dee4f 3110 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3111 * @param val Get the values of hpm_ois in reg CTRL2_OIS
cparata 0:f27ce43dee4f 3112 *
cparata 0:f27ce43dee4f 3113 */
cparata 0:f27ce43dee4f 3114 int32_t lsm6dsox_aux_gy_hp_bandwidth_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3115 lsm6dsox_hpm_ois_t *val)
cparata 0:f27ce43dee4f 3116 {
cparata 0:f27ce43dee4f 3117 lsm6dsox_ui_ctrl2_ois_t reg;
cparata 0:f27ce43dee4f 3118 int32_t ret;
cparata 0:f27ce43dee4f 3119
cparata 0:f27ce43dee4f 3120 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3121 switch ((reg.hp_en_ois << 4) | reg.hpm_ois) {
cparata 0:f27ce43dee4f 3122 case LSM6DSOX_AUX_HP_DISABLE:
cparata 0:f27ce43dee4f 3123 *val = LSM6DSOX_AUX_HP_DISABLE;
cparata 0:f27ce43dee4f 3124 break;
cparata 0:f27ce43dee4f 3125 case LSM6DSOX_AUX_HP_Hz016:
cparata 0:f27ce43dee4f 3126 *val = LSM6DSOX_AUX_HP_Hz016;
cparata 0:f27ce43dee4f 3127 break;
cparata 0:f27ce43dee4f 3128 case LSM6DSOX_AUX_HP_Hz065:
cparata 0:f27ce43dee4f 3129 *val = LSM6DSOX_AUX_HP_Hz065;
cparata 0:f27ce43dee4f 3130 break;
cparata 0:f27ce43dee4f 3131 case LSM6DSOX_AUX_HP_Hz260:
cparata 0:f27ce43dee4f 3132 *val = LSM6DSOX_AUX_HP_Hz260;
cparata 0:f27ce43dee4f 3133 break;
cparata 0:f27ce43dee4f 3134 case LSM6DSOX_AUX_HP_1Hz040:
cparata 0:f27ce43dee4f 3135 *val = LSM6DSOX_AUX_HP_1Hz040;
cparata 0:f27ce43dee4f 3136 break;
cparata 0:f27ce43dee4f 3137 default:
cparata 0:f27ce43dee4f 3138 *val = LSM6DSOX_AUX_HP_DISABLE;
cparata 0:f27ce43dee4f 3139 break;
cparata 0:f27ce43dee4f 3140 }
cparata 0:f27ce43dee4f 3141 return ret;
cparata 0:f27ce43dee4f 3142 }
cparata 0:f27ce43dee4f 3143
cparata 0:f27ce43dee4f 3144 /**
cparata 0:f27ce43dee4f 3145 * @brief Enable / Disables OIS chain clamp.
cparata 0:f27ce43dee4f 3146 * Enable: All OIS chain outputs = 8000h
cparata 0:f27ce43dee4f 3147 * during self-test; Disable: OIS chain self-test
cparata 0:f27ce43dee4f 3148 * outputs dependent from the aux gyro full
cparata 0:f27ce43dee4f 3149 * scale selected.[set]
cparata 0:f27ce43dee4f 3150 *
cparata 0:f27ce43dee4f 3151 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3152 * @param val change the values of st_ois_clampdis in
cparata 0:f27ce43dee4f 3153 * reg CTRL3_OIS
cparata 0:f27ce43dee4f 3154 *
cparata 0:f27ce43dee4f 3155 */
cparata 0:f27ce43dee4f 3156 int32_t lsm6dsox_aux_gy_clamp_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3157 lsm6dsox_st_ois_clampdis_t val)
cparata 0:f27ce43dee4f 3158 {
cparata 0:f27ce43dee4f 3159 lsm6dsox_ui_ctrl3_ois_t reg;
cparata 0:f27ce43dee4f 3160 int32_t ret;
cparata 0:f27ce43dee4f 3161
cparata 0:f27ce43dee4f 3162 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3163 if (ret == 0) {
cparata 0:f27ce43dee4f 3164 reg.st_ois_clampdis = (uint8_t)val;
cparata 0:f27ce43dee4f 3165 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3166 }
cparata 0:f27ce43dee4f 3167 return ret;
cparata 0:f27ce43dee4f 3168 }
cparata 0:f27ce43dee4f 3169
cparata 0:f27ce43dee4f 3170 /**
cparata 0:f27ce43dee4f 3171 * @brief Enable / Disables OIS chain clamp.
cparata 0:f27ce43dee4f 3172 * Enable: All OIS chain outputs = 8000h
cparata 0:f27ce43dee4f 3173 * during self-test; Disable: OIS chain self-test
cparata 0:f27ce43dee4f 3174 * outputs dependent from the aux gyro full
cparata 0:f27ce43dee4f 3175 * scale selected.[set]
cparata 0:f27ce43dee4f 3176 *
cparata 0:f27ce43dee4f 3177 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3178 * @param val Get the values of st_ois_clampdis in
cparata 0:f27ce43dee4f 3179 * reg CTRL3_OIS
cparata 0:f27ce43dee4f 3180 *
cparata 0:f27ce43dee4f 3181 */
cparata 0:f27ce43dee4f 3182 int32_t lsm6dsox_aux_gy_clamp_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3183 lsm6dsox_st_ois_clampdis_t *val)
cparata 0:f27ce43dee4f 3184 {
cparata 0:f27ce43dee4f 3185 lsm6dsox_ui_ctrl3_ois_t reg;
cparata 0:f27ce43dee4f 3186 int32_t ret;
cparata 0:f27ce43dee4f 3187
cparata 0:f27ce43dee4f 3188 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3189 switch (reg.st_ois_clampdis) {
cparata 0:f27ce43dee4f 3190 case LSM6DSOX_ENABLE_CLAMP:
cparata 0:f27ce43dee4f 3191 *val = LSM6DSOX_ENABLE_CLAMP;
cparata 0:f27ce43dee4f 3192 break;
cparata 0:f27ce43dee4f 3193 case LSM6DSOX_DISABLE_CLAMP:
cparata 0:f27ce43dee4f 3194 *val = LSM6DSOX_DISABLE_CLAMP;
cparata 0:f27ce43dee4f 3195 break;
cparata 0:f27ce43dee4f 3196 default:
cparata 0:f27ce43dee4f 3197 *val = LSM6DSOX_ENABLE_CLAMP;
cparata 0:f27ce43dee4f 3198 break;
cparata 0:f27ce43dee4f 3199 }
cparata 0:f27ce43dee4f 3200 return ret;
cparata 0:f27ce43dee4f 3201 }
cparata 0:f27ce43dee4f 3202
cparata 0:f27ce43dee4f 3203 /**
cparata 0:f27ce43dee4f 3204 * @brief Selects accelerometer OIS channel bandwidth.[set]
cparata 0:f27ce43dee4f 3205 *
cparata 0:f27ce43dee4f 3206 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3207 * @param val change the values of
cparata 0:f27ce43dee4f 3208 * filter_xl_conf_ois in reg CTRL3_OIS
cparata 0:f27ce43dee4f 3209 *
cparata 0:f27ce43dee4f 3210 */
cparata 0:f27ce43dee4f 3211 int32_t lsm6dsox_aux_xl_bandwidth_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3212 lsm6dsox_filter_xl_conf_ois_t val)
cparata 0:f27ce43dee4f 3213 {
cparata 0:f27ce43dee4f 3214 lsm6dsox_ui_ctrl3_ois_t reg;
cparata 0:f27ce43dee4f 3215 int32_t ret;
cparata 0:f27ce43dee4f 3216
cparata 0:f27ce43dee4f 3217 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3218 if (ret == 0) {
cparata 0:f27ce43dee4f 3219 reg.filter_xl_conf_ois = (uint8_t)val;
cparata 0:f27ce43dee4f 3220 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3221 }
cparata 0:f27ce43dee4f 3222 return ret;
cparata 0:f27ce43dee4f 3223 }
cparata 0:f27ce43dee4f 3224
cparata 0:f27ce43dee4f 3225 /**
cparata 0:f27ce43dee4f 3226 * @brief Selects accelerometer OIS channel bandwidth.[get]
cparata 0:f27ce43dee4f 3227 *
cparata 0:f27ce43dee4f 3228 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3229 * @param val Get the values of
cparata 0:f27ce43dee4f 3230 * filter_xl_conf_ois in reg CTRL3_OIS
cparata 0:f27ce43dee4f 3231 *
cparata 0:f27ce43dee4f 3232 */
cparata 0:f27ce43dee4f 3233 int32_t lsm6dsox_aux_xl_bandwidth_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3234 lsm6dsox_filter_xl_conf_ois_t *val)
cparata 0:f27ce43dee4f 3235 {
cparata 0:f27ce43dee4f 3236 lsm6dsox_ui_ctrl3_ois_t reg;
cparata 0:f27ce43dee4f 3237 int32_t ret;
cparata 0:f27ce43dee4f 3238
cparata 0:f27ce43dee4f 3239 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3240
cparata 0:f27ce43dee4f 3241 switch (reg.filter_xl_conf_ois) {
cparata 0:f27ce43dee4f 3242 case LSM6DSOX_289Hz:
cparata 0:f27ce43dee4f 3243 *val = LSM6DSOX_289Hz;
cparata 0:f27ce43dee4f 3244 break;
cparata 0:f27ce43dee4f 3245 case LSM6DSOX_258Hz:
cparata 0:f27ce43dee4f 3246 *val = LSM6DSOX_258Hz;
cparata 0:f27ce43dee4f 3247 break;
cparata 0:f27ce43dee4f 3248 case LSM6DSOX_120Hz:
cparata 0:f27ce43dee4f 3249 *val = LSM6DSOX_120Hz;
cparata 0:f27ce43dee4f 3250 break;
cparata 0:f27ce43dee4f 3251 case LSM6DSOX_65Hz2:
cparata 0:f27ce43dee4f 3252 *val = LSM6DSOX_65Hz2;
cparata 0:f27ce43dee4f 3253 break;
cparata 0:f27ce43dee4f 3254 case LSM6DSOX_33Hz2:
cparata 0:f27ce43dee4f 3255 *val = LSM6DSOX_33Hz2;
cparata 0:f27ce43dee4f 3256 break;
cparata 0:f27ce43dee4f 3257 case LSM6DSOX_16Hz6:
cparata 0:f27ce43dee4f 3258 *val = LSM6DSOX_16Hz6;
cparata 0:f27ce43dee4f 3259 break;
cparata 0:f27ce43dee4f 3260 case LSM6DSOX_8Hz30:
cparata 0:f27ce43dee4f 3261 *val = LSM6DSOX_8Hz30;
cparata 0:f27ce43dee4f 3262 break;
cparata 0:f27ce43dee4f 3263 case LSM6DSOX_4Hz15:
cparata 0:f27ce43dee4f 3264 *val = LSM6DSOX_4Hz15;
cparata 0:f27ce43dee4f 3265 break;
cparata 0:f27ce43dee4f 3266 default:
cparata 0:f27ce43dee4f 3267 *val = LSM6DSOX_289Hz;
cparata 0:f27ce43dee4f 3268 break;
cparata 0:f27ce43dee4f 3269 }
cparata 0:f27ce43dee4f 3270 return ret;
cparata 0:f27ce43dee4f 3271 }
cparata 0:f27ce43dee4f 3272
cparata 0:f27ce43dee4f 3273 /**
cparata 0:f27ce43dee4f 3274 * @brief Selects accelerometer OIS channel full-scale.[set]
cparata 0:f27ce43dee4f 3275 *
cparata 0:f27ce43dee4f 3276 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3277 * @param val change the values of fs_xl_ois in
cparata 0:f27ce43dee4f 3278 * reg CTRL3_OIS
cparata 0:f27ce43dee4f 3279 *
cparata 0:f27ce43dee4f 3280 */
cparata 0:f27ce43dee4f 3281 int32_t lsm6dsox_aux_xl_full_scale_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3282 lsm6dsox_fs_xl_ois_t val)
cparata 0:f27ce43dee4f 3283 {
cparata 0:f27ce43dee4f 3284 lsm6dsox_ui_ctrl3_ois_t reg;
cparata 0:f27ce43dee4f 3285 int32_t ret;
cparata 0:f27ce43dee4f 3286
cparata 0:f27ce43dee4f 3287 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3288 if (ret == 0) {
cparata 0:f27ce43dee4f 3289 reg.fs_xl_ois = (uint8_t)val;
cparata 0:f27ce43dee4f 3290 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3291 }
cparata 0:f27ce43dee4f 3292 return ret;
cparata 0:f27ce43dee4f 3293 }
cparata 0:f27ce43dee4f 3294
cparata 0:f27ce43dee4f 3295 /**
cparata 0:f27ce43dee4f 3296 * @brief Selects accelerometer OIS channel full-scale.[get]
cparata 0:f27ce43dee4f 3297 *
cparata 0:f27ce43dee4f 3298 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3299 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
cparata 0:f27ce43dee4f 3300 *
cparata 0:f27ce43dee4f 3301 */
cparata 0:f27ce43dee4f 3302 int32_t lsm6dsox_aux_xl_full_scale_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3303 lsm6dsox_fs_xl_ois_t *val)
cparata 0:f27ce43dee4f 3304 {
cparata 0:f27ce43dee4f 3305 lsm6dsox_ui_ctrl3_ois_t reg;
cparata 0:f27ce43dee4f 3306 int32_t ret;
cparata 0:f27ce43dee4f 3307
cparata 0:f27ce43dee4f 3308 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3309 switch (reg.fs_xl_ois) {
cparata 0:f27ce43dee4f 3310 case LSM6DSOX_AUX_2g:
cparata 0:f27ce43dee4f 3311 *val = LSM6DSOX_AUX_2g;
cparata 0:f27ce43dee4f 3312 break;
cparata 0:f27ce43dee4f 3313 case LSM6DSOX_AUX_16g:
cparata 0:f27ce43dee4f 3314 *val = LSM6DSOX_AUX_16g;
cparata 0:f27ce43dee4f 3315 break;
cparata 0:f27ce43dee4f 3316 case LSM6DSOX_AUX_4g:
cparata 0:f27ce43dee4f 3317 *val = LSM6DSOX_AUX_4g;
cparata 0:f27ce43dee4f 3318 break;
cparata 0:f27ce43dee4f 3319 case LSM6DSOX_AUX_8g:
cparata 0:f27ce43dee4f 3320 *val = LSM6DSOX_AUX_8g;
cparata 0:f27ce43dee4f 3321 break;
cparata 0:f27ce43dee4f 3322 default:
cparata 0:f27ce43dee4f 3323 *val = LSM6DSOX_AUX_2g;
cparata 0:f27ce43dee4f 3324 break;
cparata 0:f27ce43dee4f 3325 }
cparata 0:f27ce43dee4f 3326 return ret;
cparata 0:f27ce43dee4f 3327 }
cparata 0:f27ce43dee4f 3328
cparata 0:f27ce43dee4f 3329 /**
cparata 0:f27ce43dee4f 3330 * @}
cparata 0:f27ce43dee4f 3331 *
cparata 0:f27ce43dee4f 3332 */
cparata 0:f27ce43dee4f 3333
cparata 0:f27ce43dee4f 3334 /**
cparata 0:f27ce43dee4f 3335 * @defgroup LSM6DSOX_ main_serial_interface
cparata 0:f27ce43dee4f 3336 * @brief This section groups all the functions concerning main
cparata 0:f27ce43dee4f 3337 * serial interface management (not auxiliary)
cparata 0:f27ce43dee4f 3338 * @{
cparata 0:f27ce43dee4f 3339 *
cparata 0:f27ce43dee4f 3340 */
cparata 0:f27ce43dee4f 3341
cparata 0:f27ce43dee4f 3342 /**
cparata 0:f27ce43dee4f 3343 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
cparata 0:f27ce43dee4f 3344 *
cparata 0:f27ce43dee4f 3345 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3346 * @param val change the values of sdo_pu_en in
cparata 0:f27ce43dee4f 3347 * reg PIN_CTRL
cparata 0:f27ce43dee4f 3348 *
cparata 0:f27ce43dee4f 3349 */
cparata 0:f27ce43dee4f 3350 int32_t lsm6dsox_sdo_sa0_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sdo_pu_en_t val)
cparata 0:f27ce43dee4f 3351 {
cparata 0:f27ce43dee4f 3352 lsm6dsox_pin_ctrl_t reg;
cparata 0:f27ce43dee4f 3353 int32_t ret;
cparata 0:f27ce43dee4f 3354
cparata 0:f27ce43dee4f 3355 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3356 if (ret == 0) {
cparata 0:f27ce43dee4f 3357 reg.sdo_pu_en = (uint8_t)val;
cparata 0:f27ce43dee4f 3358 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3359 }
cparata 0:f27ce43dee4f 3360 return ret;
cparata 0:f27ce43dee4f 3361 }
cparata 0:f27ce43dee4f 3362
cparata 0:f27ce43dee4f 3363 /**
cparata 0:f27ce43dee4f 3364 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
cparata 0:f27ce43dee4f 3365 *
cparata 0:f27ce43dee4f 3366 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3367 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
cparata 0:f27ce43dee4f 3368 *
cparata 0:f27ce43dee4f 3369 */
cparata 0:f27ce43dee4f 3370 int32_t lsm6dsox_sdo_sa0_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sdo_pu_en_t *val)
cparata 0:f27ce43dee4f 3371 {
cparata 0:f27ce43dee4f 3372 lsm6dsox_pin_ctrl_t reg;
cparata 0:f27ce43dee4f 3373 int32_t ret;
cparata 0:f27ce43dee4f 3374
cparata 0:f27ce43dee4f 3375 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3376 switch (reg.sdo_pu_en) {
cparata 0:f27ce43dee4f 3377 case LSM6DSOX_PULL_UP_DISC:
cparata 0:f27ce43dee4f 3378 *val = LSM6DSOX_PULL_UP_DISC;
cparata 0:f27ce43dee4f 3379 break;
cparata 0:f27ce43dee4f 3380 case LSM6DSOX_PULL_UP_CONNECT:
cparata 0:f27ce43dee4f 3381 *val = LSM6DSOX_PULL_UP_CONNECT;
cparata 0:f27ce43dee4f 3382 break;
cparata 0:f27ce43dee4f 3383 default:
cparata 0:f27ce43dee4f 3384 *val = LSM6DSOX_PULL_UP_DISC;
cparata 0:f27ce43dee4f 3385 break;
cparata 0:f27ce43dee4f 3386 }
cparata 0:f27ce43dee4f 3387 return ret;
cparata 0:f27ce43dee4f 3388 }
cparata 0:f27ce43dee4f 3389
cparata 0:f27ce43dee4f 3390 /**
cparata 0:f27ce43dee4f 3391 * @brief SPI Serial Interface Mode selection.[set]
cparata 0:f27ce43dee4f 3392 *
cparata 0:f27ce43dee4f 3393 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3394 * @param val change the values of sim in reg CTRL3_C
cparata 0:f27ce43dee4f 3395 *
cparata 0:f27ce43dee4f 3396 */
cparata 0:f27ce43dee4f 3397 int32_t lsm6dsox_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t val)
cparata 0:f27ce43dee4f 3398 {
cparata 0:f27ce43dee4f 3399 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 3400 int32_t ret;
cparata 0:f27ce43dee4f 3401
cparata 0:f27ce43dee4f 3402 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3403 if (ret == 0) {
cparata 0:f27ce43dee4f 3404 reg.sim = (uint8_t)val;
cparata 0:f27ce43dee4f 3405 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3406 }
cparata 0:f27ce43dee4f 3407 return ret;
cparata 0:f27ce43dee4f 3408 }
cparata 0:f27ce43dee4f 3409
cparata 0:f27ce43dee4f 3410 /**
cparata 0:f27ce43dee4f 3411 * @brief SPI Serial Interface Mode selection.[get]
cparata 0:f27ce43dee4f 3412 *
cparata 0:f27ce43dee4f 3413 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3414 * @param val Get the values of sim in reg CTRL3_C
cparata 0:f27ce43dee4f 3415 *
cparata 0:f27ce43dee4f 3416 */
cparata 0:f27ce43dee4f 3417 int32_t lsm6dsox_spi_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t *val)
cparata 0:f27ce43dee4f 3418 {
cparata 0:f27ce43dee4f 3419 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 3420 int32_t ret;
cparata 0:f27ce43dee4f 3421
cparata 0:f27ce43dee4f 3422 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3423 switch (reg.sim) {
cparata 0:f27ce43dee4f 3424 case LSM6DSOX_SPI_4_WIRE:
cparata 0:f27ce43dee4f 3425 *val = LSM6DSOX_SPI_4_WIRE;
cparata 0:f27ce43dee4f 3426 break;
cparata 0:f27ce43dee4f 3427 case LSM6DSOX_SPI_3_WIRE:
cparata 0:f27ce43dee4f 3428 *val = LSM6DSOX_SPI_3_WIRE;
cparata 0:f27ce43dee4f 3429 break;
cparata 0:f27ce43dee4f 3430 default:
cparata 0:f27ce43dee4f 3431 *val = LSM6DSOX_SPI_4_WIRE;
cparata 0:f27ce43dee4f 3432 break;
cparata 0:f27ce43dee4f 3433 }
cparata 0:f27ce43dee4f 3434 return ret;
cparata 0:f27ce43dee4f 3435 }
cparata 0:f27ce43dee4f 3436
cparata 0:f27ce43dee4f 3437 /**
cparata 0:f27ce43dee4f 3438 * @brief Disable / Enable I2C interface.[set]
cparata 0:f27ce43dee4f 3439 *
cparata 0:f27ce43dee4f 3440 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3441 * @param val change the values of i2c_disable in
cparata 0:f27ce43dee4f 3442 * reg CTRL4_C
cparata 0:f27ce43dee4f 3443 *
cparata 0:f27ce43dee4f 3444 */
cparata 0:f27ce43dee4f 3445 int32_t lsm6dsox_i2c_interface_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3446 lsm6dsox_i2c_disable_t val)
cparata 0:f27ce43dee4f 3447 {
cparata 0:f27ce43dee4f 3448 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 3449 int32_t ret;
cparata 0:f27ce43dee4f 3450
cparata 0:f27ce43dee4f 3451 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3452 if (ret == 0) {
cparata 0:f27ce43dee4f 3453 reg.i2c_disable = (uint8_t)val;
cparata 0:f27ce43dee4f 3454 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3455 }
cparata 0:f27ce43dee4f 3456 return ret;
cparata 0:f27ce43dee4f 3457 }
cparata 0:f27ce43dee4f 3458
cparata 0:f27ce43dee4f 3459 /**
cparata 0:f27ce43dee4f 3460 * @brief Disable / Enable I2C interface.[get]
cparata 0:f27ce43dee4f 3461 *
cparata 0:f27ce43dee4f 3462 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3463 * @param val Get the values of i2c_disable in
cparata 0:f27ce43dee4f 3464 * reg CTRL4_C
cparata 0:f27ce43dee4f 3465 *
cparata 0:f27ce43dee4f 3466 */
cparata 0:f27ce43dee4f 3467 int32_t lsm6dsox_i2c_interface_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3468 lsm6dsox_i2c_disable_t *val)
cparata 0:f27ce43dee4f 3469 {
cparata 0:f27ce43dee4f 3470 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 3471 int32_t ret;
cparata 0:f27ce43dee4f 3472
cparata 0:f27ce43dee4f 3473 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3474 switch (reg.i2c_disable) {
cparata 0:f27ce43dee4f 3475 case LSM6DSOX_I2C_ENABLE:
cparata 0:f27ce43dee4f 3476 *val = LSM6DSOX_I2C_ENABLE;
cparata 0:f27ce43dee4f 3477 break;
cparata 0:f27ce43dee4f 3478 case LSM6DSOX_I2C_DISABLE:
cparata 0:f27ce43dee4f 3479 *val = LSM6DSOX_I2C_DISABLE;
cparata 0:f27ce43dee4f 3480 break;
cparata 0:f27ce43dee4f 3481 default:
cparata 0:f27ce43dee4f 3482 *val = LSM6DSOX_I2C_ENABLE;
cparata 0:f27ce43dee4f 3483 break;
cparata 0:f27ce43dee4f 3484 }
cparata 0:f27ce43dee4f 3485 return ret;
cparata 0:f27ce43dee4f 3486 }
cparata 0:f27ce43dee4f 3487
cparata 0:f27ce43dee4f 3488 /**
cparata 0:f27ce43dee4f 3489 * @brief I3C Enable/Disable communication protocol[.set]
cparata 0:f27ce43dee4f 3490 *
cparata 0:f27ce43dee4f 3491 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3492 * @param val change the values of i3c_disable
cparata 0:f27ce43dee4f 3493 * in reg CTRL9_XL
cparata 0:f27ce43dee4f 3494 *
cparata 0:f27ce43dee4f 3495 */
cparata 0:f27ce43dee4f 3496 int32_t lsm6dsox_i3c_disable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_i3c_disable_t val)
cparata 0:f27ce43dee4f 3497 {
cparata 0:f27ce43dee4f 3498 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata 0:f27ce43dee4f 3499 lsm6dsox_ctrl9_xl_t ctrl9_xl;
cparata 0:f27ce43dee4f 3500 int32_t ret;
cparata 0:f27ce43dee4f 3501
cparata 0:f27ce43dee4f 3502 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata 0:f27ce43dee4f 3503 if (ret == 0) {
cparata 0:f27ce43dee4f 3504 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
cparata 0:f27ce43dee4f 3505 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata 0:f27ce43dee4f 3506 }
cparata 0:f27ce43dee4f 3507 if (ret == 0) {
cparata 0:f27ce43dee4f 3508
cparata 0:f27ce43dee4f 3509 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata 0:f27ce43dee4f 3510 (uint8_t*)&i3c_bus_avb, 1);
cparata 0:f27ce43dee4f 3511 }
cparata 0:f27ce43dee4f 3512 if (ret == 0) {
cparata 0:f27ce43dee4f 3513 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
cparata 0:f27ce43dee4f 3514 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata 0:f27ce43dee4f 3515 (uint8_t*)&i3c_bus_avb, 1);
cparata 0:f27ce43dee4f 3516 }
cparata 0:f27ce43dee4f 3517
cparata 0:f27ce43dee4f 3518 return ret;
cparata 0:f27ce43dee4f 3519 }
cparata 0:f27ce43dee4f 3520
cparata 0:f27ce43dee4f 3521 /**
cparata 0:f27ce43dee4f 3522 * @brief I3C Enable/Disable communication protocol.[get]
cparata 0:f27ce43dee4f 3523 *
cparata 0:f27ce43dee4f 3524 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3525 * @param val change the values of i3c_disable in
cparata 0:f27ce43dee4f 3526 * reg CTRL9_XL
cparata 0:f27ce43dee4f 3527 *
cparata 0:f27ce43dee4f 3528 */
cparata 0:f27ce43dee4f 3529 int32_t lsm6dsox_i3c_disable_get(lsm6dsox_ctx_t *ctx, lsm6dsox_i3c_disable_t *val)
cparata 0:f27ce43dee4f 3530 {
cparata 0:f27ce43dee4f 3531 lsm6dsox_ctrl9_xl_t ctrl9_xl;
cparata 0:f27ce43dee4f 3532 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata 0:f27ce43dee4f 3533 int32_t ret;
cparata 0:f27ce43dee4f 3534
cparata 0:f27ce43dee4f 3535 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata 0:f27ce43dee4f 3536 if (ret == 0) {
cparata 0:f27ce43dee4f 3537 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata 0:f27ce43dee4f 3538 (uint8_t*)&i3c_bus_avb, 1);
cparata 0:f27ce43dee4f 3539
cparata 0:f27ce43dee4f 3540 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) {
cparata 0:f27ce43dee4f 3541 case LSM6DSOX_I3C_DISABLE:
cparata 0:f27ce43dee4f 3542 *val = LSM6DSOX_I3C_DISABLE;
cparata 0:f27ce43dee4f 3543 break;
cparata 0:f27ce43dee4f 3544 case LSM6DSOX_I3C_ENABLE_T_50us:
cparata 0:f27ce43dee4f 3545 *val = LSM6DSOX_I3C_ENABLE_T_50us;
cparata 0:f27ce43dee4f 3546 break;
cparata 0:f27ce43dee4f 3547 case LSM6DSOX_I3C_ENABLE_T_2us:
cparata 0:f27ce43dee4f 3548 *val = LSM6DSOX_I3C_ENABLE_T_2us;
cparata 0:f27ce43dee4f 3549 break;
cparata 0:f27ce43dee4f 3550 case LSM6DSOX_I3C_ENABLE_T_1ms:
cparata 0:f27ce43dee4f 3551 *val = LSM6DSOX_I3C_ENABLE_T_1ms;
cparata 0:f27ce43dee4f 3552 break;
cparata 0:f27ce43dee4f 3553 case LSM6DSOX_I3C_ENABLE_T_25ms:
cparata 0:f27ce43dee4f 3554 *val = LSM6DSOX_I3C_ENABLE_T_25ms;
cparata 0:f27ce43dee4f 3555 break;
cparata 0:f27ce43dee4f 3556 default:
cparata 0:f27ce43dee4f 3557 *val = LSM6DSOX_I3C_DISABLE;
cparata 0:f27ce43dee4f 3558 break;
cparata 0:f27ce43dee4f 3559 }
cparata 0:f27ce43dee4f 3560 }
cparata 0:f27ce43dee4f 3561 return ret;
cparata 0:f27ce43dee4f 3562 }
cparata 0:f27ce43dee4f 3563
cparata 0:f27ce43dee4f 3564 /**
cparata 0:f27ce43dee4f 3565 * @}
cparata 0:f27ce43dee4f 3566 *
cparata 0:f27ce43dee4f 3567 */
cparata 0:f27ce43dee4f 3568
cparata 0:f27ce43dee4f 3569 /**
cparata 0:f27ce43dee4f 3570 * @defgroup LSM6DSOX_interrupt_pins
cparata 0:f27ce43dee4f 3571 * @brief This section groups all the functions that manage interrup pins
cparata 0:f27ce43dee4f 3572 * @{
cparata 0:f27ce43dee4f 3573 *
cparata 0:f27ce43dee4f 3574 */
cparata 0:f27ce43dee4f 3575
cparata 0:f27ce43dee4f 3576 /**
cparata 0:f27ce43dee4f 3577 * @brief Select the signal that need to route on int1 pad.[set]
cparata 0:f27ce43dee4f 3578 *
cparata 0:f27ce43dee4f 3579 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3580 * @param val struct of registers: INT1_CTRL,
cparata 0:f27ce43dee4f 3581 * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
cparata 0:f27ce43dee4f 3582 * FSM_INT1_B
cparata 0:f27ce43dee4f 3583 *
cparata 0:f27ce43dee4f 3584 */
cparata 0:f27ce43dee4f 3585 int32_t lsm6dsox_pin_int1_route_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3586 lsm6dsox_pin_int1_route_t *val)
cparata 0:f27ce43dee4f 3587 {
cparata 0:f27ce43dee4f 3588 lsm6dsox_pin_int2_route_t pin_int2_route;
cparata 0:f27ce43dee4f 3589 lsm6dsox_tap_cfg2_t tap_cfg2;
cparata 0:f27ce43dee4f 3590 int32_t ret;
cparata 0:f27ce43dee4f 3591
cparata 0:f27ce43dee4f 3592 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 3593 if (ret == 0) {
cparata 0:f27ce43dee4f 3594 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1,
cparata 0:f27ce43dee4f 3595 (uint8_t*)&val->mlc_int1, 1);
cparata 0:f27ce43dee4f 3596 }
cparata 0:f27ce43dee4f 3597 if (ret == 0) {
cparata 0:f27ce43dee4f 3598 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT1,
cparata 0:f27ce43dee4f 3599 (uint8_t*)&val->emb_func_int1, 1);
cparata 0:f27ce43dee4f 3600 }
cparata 0:f27ce43dee4f 3601 if (ret == 0) {
cparata 0:f27ce43dee4f 3602 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_A,
cparata 0:f27ce43dee4f 3603 (uint8_t*)&val->fsm_int1_a, 1);
cparata 0:f27ce43dee4f 3604 }
cparata 0:f27ce43dee4f 3605 if (ret == 0) {
cparata 0:f27ce43dee4f 3606 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_B,
cparata 0:f27ce43dee4f 3607 (uint8_t*)&val->fsm_int1_b, 1);
cparata 0:f27ce43dee4f 3608 }
cparata 0:f27ce43dee4f 3609 if (ret == 0) {
cparata 0:f27ce43dee4f 3610 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 3611 }
cparata 0:f27ce43dee4f 3612
cparata 0:f27ce43dee4f 3613 if (ret == 0) {
cparata 0:f27ce43dee4f 3614 if ( ( val->emb_func_int1.int1_fsm_lc
cparata 0:f27ce43dee4f 3615 | val->emb_func_int1.int1_sig_mot
cparata 0:f27ce43dee4f 3616 | val->emb_func_int1.int1_step_detector
cparata 0:f27ce43dee4f 3617 | val->emb_func_int1.int1_tilt
cparata 0:f27ce43dee4f 3618 | val->fsm_int1_a.int1_fsm1
cparata 0:f27ce43dee4f 3619 | val->fsm_int1_a.int1_fsm2
cparata 0:f27ce43dee4f 3620 | val->fsm_int1_a.int1_fsm3
cparata 0:f27ce43dee4f 3621 | val->fsm_int1_a.int1_fsm4
cparata 0:f27ce43dee4f 3622 | val->fsm_int1_a.int1_fsm5
cparata 0:f27ce43dee4f 3623 | val->fsm_int1_a.int1_fsm6
cparata 0:f27ce43dee4f 3624 | val->fsm_int1_a.int1_fsm7
cparata 0:f27ce43dee4f 3625 | val->fsm_int1_a.int1_fsm8
cparata 0:f27ce43dee4f 3626 | val->fsm_int1_b.int1_fsm9
cparata 0:f27ce43dee4f 3627 | val->fsm_int1_b.int1_fsm10
cparata 0:f27ce43dee4f 3628 | val->fsm_int1_b.int1_fsm11
cparata 0:f27ce43dee4f 3629 | val->fsm_int1_b.int1_fsm12
cparata 0:f27ce43dee4f 3630 | val->fsm_int1_b.int1_fsm13
cparata 0:f27ce43dee4f 3631 | val->fsm_int1_b.int1_fsm14
cparata 0:f27ce43dee4f 3632 | val->fsm_int1_b.int1_fsm15
cparata 0:f27ce43dee4f 3633 | val->fsm_int1_b.int1_fsm16
cparata 0:f27ce43dee4f 3634 | val->mlc_int1.int1_mlc1
cparata 0:f27ce43dee4f 3635 | val->mlc_int1.int1_mlc2
cparata 0:f27ce43dee4f 3636 | val->mlc_int1.int1_mlc3
cparata 0:f27ce43dee4f 3637 | val->mlc_int1.int1_mlc4
cparata 0:f27ce43dee4f 3638 | val->mlc_int1.int1_mlc5
cparata 0:f27ce43dee4f 3639 | val->mlc_int1.int1_mlc6
cparata 0:f27ce43dee4f 3640 | val->mlc_int1.int1_mlc7
cparata 0:f27ce43dee4f 3641 | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE){
cparata 0:f27ce43dee4f 3642 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
cparata 0:f27ce43dee4f 3643 }
cparata 0:f27ce43dee4f 3644 else{
cparata 0:f27ce43dee4f 3645 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
cparata 0:f27ce43dee4f 3646 }
cparata 0:f27ce43dee4f 3647 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT1_CTRL,
cparata 0:f27ce43dee4f 3648 (uint8_t*)&val->int1_ctrl, 1);
cparata 0:f27ce43dee4f 3649 }
cparata 0:f27ce43dee4f 3650 if (ret == 0) {
cparata 0:f27ce43dee4f 3651 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&val->md1_cfg, 1);
cparata 0:f27ce43dee4f 3652 }
cparata 0:f27ce43dee4f 3653 if (ret == 0) {
cparata 0:f27ce43dee4f 3654 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata 0:f27ce43dee4f 3655 }
cparata 0:f27ce43dee4f 3656
cparata 0:f27ce43dee4f 3657 if (ret == 0) {
cparata 0:f27ce43dee4f 3658 ret = lsm6dsox_pin_int2_route_get(ctx, &pin_int2_route);
cparata 0:f27ce43dee4f 3659 }
cparata 0:f27ce43dee4f 3660 if (ret == 0) {
cparata 0:f27ce43dee4f 3661 if ( ( pin_int2_route.int2_ctrl.int2_cnt_bdr
cparata 0:f27ce43dee4f 3662 | pin_int2_route.int2_ctrl.int2_drdy_g
cparata 0:f27ce43dee4f 3663 | pin_int2_route.int2_ctrl.int2_drdy_temp
cparata 0:f27ce43dee4f 3664 | pin_int2_route.int2_ctrl.int2_drdy_xl
cparata 0:f27ce43dee4f 3665 | pin_int2_route.int2_ctrl.int2_fifo_full
cparata 0:f27ce43dee4f 3666 | pin_int2_route.int2_ctrl.int2_fifo_ovr
cparata 0:f27ce43dee4f 3667 | pin_int2_route.int2_ctrl.int2_fifo_th
cparata 0:f27ce43dee4f 3668 | pin_int2_route.md2_cfg.int2_6d
cparata 0:f27ce43dee4f 3669 | pin_int2_route.md2_cfg.int2_double_tap
cparata 0:f27ce43dee4f 3670 | pin_int2_route.md2_cfg.int2_ff
cparata 0:f27ce43dee4f 3671 | pin_int2_route.md2_cfg.int2_wu
cparata 0:f27ce43dee4f 3672 | pin_int2_route.md2_cfg.int2_single_tap
cparata 0:f27ce43dee4f 3673 | pin_int2_route.md2_cfg.int2_sleep_change
cparata 0:f27ce43dee4f 3674 | val->int1_ctrl.den_drdy_flag
cparata 0:f27ce43dee4f 3675 | val->int1_ctrl.int1_boot
cparata 0:f27ce43dee4f 3676 | val->int1_ctrl.int1_cnt_bdr
cparata 0:f27ce43dee4f 3677 | val->int1_ctrl.int1_drdy_g
cparata 0:f27ce43dee4f 3678 | val->int1_ctrl.int1_drdy_xl
cparata 0:f27ce43dee4f 3679 | val->int1_ctrl.int1_fifo_full
cparata 0:f27ce43dee4f 3680 | val->int1_ctrl.int1_fifo_ovr
cparata 0:f27ce43dee4f 3681 | val->int1_ctrl.int1_fifo_th
cparata 0:f27ce43dee4f 3682 | val->md1_cfg.int1_shub
cparata 0:f27ce43dee4f 3683 | val->md1_cfg.int1_6d
cparata 0:f27ce43dee4f 3684 | val->md1_cfg.int1_double_tap
cparata 0:f27ce43dee4f 3685 | val->md1_cfg.int1_ff
cparata 0:f27ce43dee4f 3686 | val->md1_cfg.int1_wu
cparata 0:f27ce43dee4f 3687 | val->md1_cfg.int1_single_tap
cparata 0:f27ce43dee4f 3688 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
cparata 0:f27ce43dee4f 3689 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata 0:f27ce43dee4f 3690 }
cparata 0:f27ce43dee4f 3691 else{
cparata 0:f27ce43dee4f 3692 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata 0:f27ce43dee4f 3693 }
cparata 0:f27ce43dee4f 3694 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata 0:f27ce43dee4f 3695 }
cparata 0:f27ce43dee4f 3696 return ret;
cparata 0:f27ce43dee4f 3697 }
cparata 0:f27ce43dee4f 3698
cparata 0:f27ce43dee4f 3699 /**
cparata 0:f27ce43dee4f 3700 * @brief Select the signal that need to route on int1 pad.[get]
cparata 0:f27ce43dee4f 3701 *
cparata 0:f27ce43dee4f 3702 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3703 * @param val struct of registers: INT1_CTRL, MD1_CFG,
cparata 0:f27ce43dee4f 3704 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
cparata 0:f27ce43dee4f 3705 *
cparata 0:f27ce43dee4f 3706 */
cparata 0:f27ce43dee4f 3707 int32_t lsm6dsox_pin_int1_route_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3708 lsm6dsox_pin_int1_route_t *val)
cparata 0:f27ce43dee4f 3709 {
cparata 0:f27ce43dee4f 3710 int32_t ret;
cparata 0:f27ce43dee4f 3711
cparata 0:f27ce43dee4f 3712 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 3713 if (ret == 0) {
cparata 0:f27ce43dee4f 3714 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT1,
cparata 0:f27ce43dee4f 3715 (uint8_t*)&val->mlc_int1, 1);
cparata 0:f27ce43dee4f 3716 }
cparata 0:f27ce43dee4f 3717 if (ret == 0) {
cparata 0:f27ce43dee4f 3718 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT1,
cparata 0:f27ce43dee4f 3719 (uint8_t*)&val->emb_func_int1, 1);
cparata 0:f27ce43dee4f 3720 }
cparata 0:f27ce43dee4f 3721 if (ret == 0) {
cparata 0:f27ce43dee4f 3722 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_A,
cparata 0:f27ce43dee4f 3723 (uint8_t*)&val->fsm_int1_a, 1);
cparata 0:f27ce43dee4f 3724 }
cparata 0:f27ce43dee4f 3725 if (ret == 0) {
cparata 0:f27ce43dee4f 3726 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_B,
cparata 0:f27ce43dee4f 3727 (uint8_t*)&val->fsm_int1_b, 1);
cparata 0:f27ce43dee4f 3728 }
cparata 0:f27ce43dee4f 3729 if (ret == 0) {
cparata 0:f27ce43dee4f 3730 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 3731 }
cparata 0:f27ce43dee4f 3732 if (ret == 0) {
cparata 0:f27ce43dee4f 3733
cparata 0:f27ce43dee4f 3734 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT1_CTRL,
cparata 0:f27ce43dee4f 3735 (uint8_t*)&val->int1_ctrl, 1);
cparata 0:f27ce43dee4f 3736 }
cparata 0:f27ce43dee4f 3737 if (ret == 0) {
cparata 0:f27ce43dee4f 3738 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&val->md1_cfg, 1);
cparata 0:f27ce43dee4f 3739 }
cparata 0:f27ce43dee4f 3740
cparata 0:f27ce43dee4f 3741 return ret;
cparata 0:f27ce43dee4f 3742 }
cparata 0:f27ce43dee4f 3743
cparata 0:f27ce43dee4f 3744 /**
cparata 0:f27ce43dee4f 3745 * @brief Select the signal that need to route on int2 pad.[set]
cparata 0:f27ce43dee4f 3746 *
cparata 0:f27ce43dee4f 3747 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3748 * @param val union of registers INT2_CTRL, MD2_CFG,
cparata 0:f27ce43dee4f 3749 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
cparata 0:f27ce43dee4f 3750 *
cparata 0:f27ce43dee4f 3751 */
cparata 0:f27ce43dee4f 3752 int32_t lsm6dsox_pin_int2_route_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3753 lsm6dsox_pin_int2_route_t *val)
cparata 0:f27ce43dee4f 3754 {
cparata 0:f27ce43dee4f 3755 lsm6dsox_pin_int1_route_t pin_int1_route;
cparata 0:f27ce43dee4f 3756 lsm6dsox_tap_cfg2_t tap_cfg2;
cparata 0:f27ce43dee4f 3757 int32_t ret;
cparata 0:f27ce43dee4f 3758
cparata 0:f27ce43dee4f 3759 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 3760 if (ret == 0) {
cparata 0:f27ce43dee4f 3761 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1,
cparata 0:f27ce43dee4f 3762 (uint8_t*)&val->mlc_int2, 1);
cparata 0:f27ce43dee4f 3763 }
cparata 0:f27ce43dee4f 3764 if (ret == 0) {
cparata 0:f27ce43dee4f 3765 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT2,
cparata 0:f27ce43dee4f 3766 (uint8_t*)&val->emb_func_int2, 1);
cparata 0:f27ce43dee4f 3767 }
cparata 0:f27ce43dee4f 3768 if (ret == 0) {
cparata 0:f27ce43dee4f 3769 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_A,
cparata 0:f27ce43dee4f 3770 (uint8_t*)&val->fsm_int2_a, 1);
cparata 0:f27ce43dee4f 3771 }
cparata 0:f27ce43dee4f 3772 if (ret == 0) {
cparata 0:f27ce43dee4f 3773 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_B,
cparata 0:f27ce43dee4f 3774 (uint8_t*)&val->fsm_int2_b, 1);
cparata 0:f27ce43dee4f 3775 }
cparata 0:f27ce43dee4f 3776 if (ret == 0) {
cparata 0:f27ce43dee4f 3777 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 3778 }
cparata 0:f27ce43dee4f 3779
cparata 0:f27ce43dee4f 3780 if (ret == 0) {
cparata 0:f27ce43dee4f 3781 if (( val->emb_func_int2.int2_fsm_lc
cparata 0:f27ce43dee4f 3782 | val->emb_func_int2.int2_sig_mot
cparata 0:f27ce43dee4f 3783 | val->emb_func_int2.int2_step_detector
cparata 0:f27ce43dee4f 3784 | val->emb_func_int2.int2_tilt
cparata 0:f27ce43dee4f 3785 | val->fsm_int2_a.int2_fsm1
cparata 0:f27ce43dee4f 3786 | val->fsm_int2_a.int2_fsm2
cparata 0:f27ce43dee4f 3787 | val->fsm_int2_a.int2_fsm3
cparata 0:f27ce43dee4f 3788 | val->fsm_int2_a.int2_fsm4
cparata 0:f27ce43dee4f 3789 | val->fsm_int2_a.int2_fsm5
cparata 0:f27ce43dee4f 3790 | val->fsm_int2_a.int2_fsm6
cparata 0:f27ce43dee4f 3791 | val->fsm_int2_a.int2_fsm7
cparata 0:f27ce43dee4f 3792 | val->fsm_int2_a.int2_fsm8
cparata 0:f27ce43dee4f 3793 | val->fsm_int2_b.int2_fsm9
cparata 0:f27ce43dee4f 3794 | val->fsm_int2_b.int2_fsm10
cparata 0:f27ce43dee4f 3795 | val->fsm_int2_b.int2_fsm11
cparata 0:f27ce43dee4f 3796 | val->fsm_int2_b.int2_fsm12
cparata 0:f27ce43dee4f 3797 | val->fsm_int2_b.int2_fsm13
cparata 0:f27ce43dee4f 3798 | val->fsm_int2_b.int2_fsm14
cparata 0:f27ce43dee4f 3799 | val->fsm_int2_b.int2_fsm15
cparata 0:f27ce43dee4f 3800 | val->fsm_int2_b.int2_fsm16
cparata 0:f27ce43dee4f 3801 | val->mlc_int2.int2_mlc1
cparata 0:f27ce43dee4f 3802 | val->mlc_int2.int2_mlc2
cparata 0:f27ce43dee4f 3803 | val->mlc_int2.int2_mlc3
cparata 0:f27ce43dee4f 3804 | val->mlc_int2.int2_mlc4
cparata 0:f27ce43dee4f 3805 | val->mlc_int2.int2_mlc5
cparata 0:f27ce43dee4f 3806 | val->mlc_int2.int2_mlc6
cparata 0:f27ce43dee4f 3807 | val->mlc_int2.int2_mlc7
cparata 0:f27ce43dee4f 3808 | val->mlc_int2.int2_mlc8)!= PROPERTY_DISABLE ){
cparata 0:f27ce43dee4f 3809 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
cparata 0:f27ce43dee4f 3810 }
cparata 0:f27ce43dee4f 3811 else{
cparata 0:f27ce43dee4f 3812 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
cparata 0:f27ce43dee4f 3813 }
cparata 0:f27ce43dee4f 3814 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL,
cparata 0:f27ce43dee4f 3815 (uint8_t*)&val->int2_ctrl, 1);
cparata 0:f27ce43dee4f 3816 }
cparata 0:f27ce43dee4f 3817 if (ret == 0) {
cparata 0:f27ce43dee4f 3818 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&val->md2_cfg, 1);
cparata 0:f27ce43dee4f 3819 }
cparata 0:f27ce43dee4f 3820 if (ret == 0) {
cparata 0:f27ce43dee4f 3821 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata 0:f27ce43dee4f 3822 }
cparata 0:f27ce43dee4f 3823
cparata 0:f27ce43dee4f 3824 if (ret == 0) {
cparata 0:f27ce43dee4f 3825 ret = lsm6dsox_pin_int1_route_get(ctx, &pin_int1_route);
cparata 0:f27ce43dee4f 3826 }
cparata 0:f27ce43dee4f 3827
cparata 0:f27ce43dee4f 3828 if (ret == 0) {
cparata 0:f27ce43dee4f 3829 if ( ( val->int2_ctrl.int2_cnt_bdr
cparata 0:f27ce43dee4f 3830 | val->int2_ctrl.int2_drdy_g
cparata 0:f27ce43dee4f 3831 | val->int2_ctrl.int2_drdy_temp
cparata 0:f27ce43dee4f 3832 | val->int2_ctrl.int2_drdy_xl
cparata 0:f27ce43dee4f 3833 | val->int2_ctrl.int2_fifo_full
cparata 0:f27ce43dee4f 3834 | val->int2_ctrl.int2_fifo_ovr
cparata 0:f27ce43dee4f 3835 | val->int2_ctrl.int2_fifo_th
cparata 0:f27ce43dee4f 3836 | val->md2_cfg.int2_6d
cparata 0:f27ce43dee4f 3837 | val->md2_cfg.int2_double_tap
cparata 0:f27ce43dee4f 3838 | val->md2_cfg.int2_ff
cparata 0:f27ce43dee4f 3839 | val->md2_cfg.int2_wu
cparata 0:f27ce43dee4f 3840 | val->md2_cfg.int2_single_tap
cparata 0:f27ce43dee4f 3841 | val->md2_cfg.int2_sleep_change
cparata 0:f27ce43dee4f 3842 | pin_int1_route.int1_ctrl.den_drdy_flag
cparata 0:f27ce43dee4f 3843 | pin_int1_route.int1_ctrl.int1_boot
cparata 0:f27ce43dee4f 3844 | pin_int1_route.int1_ctrl.int1_cnt_bdr
cparata 0:f27ce43dee4f 3845 | pin_int1_route.int1_ctrl.int1_drdy_g
cparata 0:f27ce43dee4f 3846 | pin_int1_route.int1_ctrl.int1_drdy_xl
cparata 0:f27ce43dee4f 3847 | pin_int1_route.int1_ctrl.int1_fifo_full
cparata 0:f27ce43dee4f 3848 | pin_int1_route.int1_ctrl.int1_fifo_ovr
cparata 0:f27ce43dee4f 3849 | pin_int1_route.int1_ctrl.int1_fifo_th
cparata 0:f27ce43dee4f 3850 | pin_int1_route.md1_cfg.int1_6d
cparata 0:f27ce43dee4f 3851 | pin_int1_route.md1_cfg.int1_double_tap
cparata 0:f27ce43dee4f 3852 | pin_int1_route.md1_cfg.int1_ff
cparata 0:f27ce43dee4f 3853 | pin_int1_route.md1_cfg.int1_wu
cparata 0:f27ce43dee4f 3854 | pin_int1_route.md1_cfg.int1_single_tap
cparata 0:f27ce43dee4f 3855 | pin_int1_route.md1_cfg.int1_sleep_change ) != PROPERTY_DISABLE) {
cparata 0:f27ce43dee4f 3856 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata 0:f27ce43dee4f 3857 }
cparata 0:f27ce43dee4f 3858 else{
cparata 0:f27ce43dee4f 3859 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata 0:f27ce43dee4f 3860 }
cparata 0:f27ce43dee4f 3861 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata 0:f27ce43dee4f 3862 }
cparata 0:f27ce43dee4f 3863 return ret;
cparata 0:f27ce43dee4f 3864 }
cparata 0:f27ce43dee4f 3865
cparata 0:f27ce43dee4f 3866 /**
cparata 0:f27ce43dee4f 3867 * @brief Select the signal that need to route on int2 pad.[get]
cparata 0:f27ce43dee4f 3868 *
cparata 0:f27ce43dee4f 3869 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3870 * @param val union of registers INT2_CTRL, MD2_CFG,
cparata 0:f27ce43dee4f 3871 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
cparata 0:f27ce43dee4f 3872 *
cparata 0:f27ce43dee4f 3873 */
cparata 0:f27ce43dee4f 3874 int32_t lsm6dsox_pin_int2_route_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 3875 lsm6dsox_pin_int2_route_t *val)
cparata 0:f27ce43dee4f 3876 {
cparata 0:f27ce43dee4f 3877 int32_t ret;
cparata 0:f27ce43dee4f 3878
cparata 0:f27ce43dee4f 3879 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 3880 if (ret == 0) {
cparata 0:f27ce43dee4f 3881 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT2,
cparata 0:f27ce43dee4f 3882 (uint8_t*)&val->mlc_int2, 1);
cparata 0:f27ce43dee4f 3883 }
cparata 0:f27ce43dee4f 3884 if (ret == 0) {
cparata 0:f27ce43dee4f 3885 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT2,
cparata 0:f27ce43dee4f 3886 (uint8_t*)&val->emb_func_int2, 1);
cparata 0:f27ce43dee4f 3887 }
cparata 0:f27ce43dee4f 3888 if (ret == 0) {
cparata 0:f27ce43dee4f 3889 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_A,
cparata 0:f27ce43dee4f 3890 (uint8_t*)&val->fsm_int2_a, 1);
cparata 0:f27ce43dee4f 3891 }
cparata 0:f27ce43dee4f 3892 if (ret == 0) {
cparata 0:f27ce43dee4f 3893 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_B,
cparata 0:f27ce43dee4f 3894 (uint8_t*)&val->fsm_int2_b, 1);
cparata 0:f27ce43dee4f 3895 }
cparata 0:f27ce43dee4f 3896 if (ret == 0) {
cparata 0:f27ce43dee4f 3897 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 3898 }
cparata 0:f27ce43dee4f 3899 if (ret == 0) {
cparata 0:f27ce43dee4f 3900
cparata 0:f27ce43dee4f 3901 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
cparata 0:f27ce43dee4f 3902 (uint8_t*)&val->int2_ctrl, 1);
cparata 0:f27ce43dee4f 3903 }
cparata 0:f27ce43dee4f 3904 if (ret == 0) {
cparata 0:f27ce43dee4f 3905 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&val->md2_cfg, 1);
cparata 0:f27ce43dee4f 3906 }
cparata 0:f27ce43dee4f 3907 return ret;
cparata 0:f27ce43dee4f 3908 }
cparata 0:f27ce43dee4f 3909
cparata 0:f27ce43dee4f 3910 /**
cparata 0:f27ce43dee4f 3911 * @brief Push-pull/open drain selection on interrupt pads.[set]
cparata 0:f27ce43dee4f 3912 *
cparata 0:f27ce43dee4f 3913 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3914 * @param val change the values of pp_od in reg CTRL3_C
cparata 0:f27ce43dee4f 3915 *
cparata 0:f27ce43dee4f 3916 */
cparata 0:f27ce43dee4f 3917 int32_t lsm6dsox_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t val)
cparata 0:f27ce43dee4f 3918 {
cparata 0:f27ce43dee4f 3919 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata 0:f27ce43dee4f 3920 lsm6dsox_ctrl3_c_t ctrl3_c;
cparata 0:f27ce43dee4f 3921 int32_t ret;
cparata 0:f27ce43dee4f 3922
cparata 0:f27ce43dee4f 3923 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata 0:f27ce43dee4f 3924 if (ret == 0) {
cparata 0:f27ce43dee4f 3925 ctrl3_c.pp_od = (uint8_t)val;
cparata 0:f27ce43dee4f 3926 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata 0:f27ce43dee4f 3927 }
cparata 0:f27ce43dee4f 3928 if (ret == 0) {
cparata 0:f27ce43dee4f 3929 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata 0:f27ce43dee4f 3930 (uint8_t*)&i3c_bus_avb, 1);
cparata 0:f27ce43dee4f 3931 }
cparata 0:f27ce43dee4f 3932 if (ret == 0) {
cparata 0:f27ce43dee4f 3933 i3c_bus_avb.pd_dis_int1 = ( (uint8_t) val & 0x02U ) >> 1;
cparata 0:f27ce43dee4f 3934 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata 0:f27ce43dee4f 3935 (uint8_t*)&i3c_bus_avb, 1);
cparata 0:f27ce43dee4f 3936 }
cparata 0:f27ce43dee4f 3937 return ret;
cparata 0:f27ce43dee4f 3938 }
cparata 0:f27ce43dee4f 3939
cparata 0:f27ce43dee4f 3940 /**
cparata 0:f27ce43dee4f 3941 * @brief Push-pull/open drain selection on interrupt pads.[get]
cparata 0:f27ce43dee4f 3942 *
cparata 0:f27ce43dee4f 3943 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3944 * @param val Get the values of pp_od in reg CTRL3_C
cparata 0:f27ce43dee4f 3945 *
cparata 0:f27ce43dee4f 3946 */
cparata 0:f27ce43dee4f 3947 int32_t lsm6dsox_pin_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t *val)
cparata 0:f27ce43dee4f 3948 {
cparata 0:f27ce43dee4f 3949 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
cparata 0:f27ce43dee4f 3950 lsm6dsox_ctrl3_c_t ctrl3_c;
cparata 0:f27ce43dee4f 3951 int32_t ret;
cparata 0:f27ce43dee4f 3952
cparata 0:f27ce43dee4f 3953 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata 0:f27ce43dee4f 3954 if (ret == 0) {
cparata 0:f27ce43dee4f 3955 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
cparata 0:f27ce43dee4f 3956 (uint8_t*)&i3c_bus_avb, 1);
cparata 0:f27ce43dee4f 3957 }
cparata 0:f27ce43dee4f 3958
cparata 0:f27ce43dee4f 3959 switch ( (i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od) {
cparata 0:f27ce43dee4f 3960 case LSM6DSOX_PUSH_PULL:
cparata 0:f27ce43dee4f 3961 *val = LSM6DSOX_PUSH_PULL;
cparata 0:f27ce43dee4f 3962 break;
cparata 0:f27ce43dee4f 3963 case LSM6DSOX_OPEN_DRAIN:
cparata 0:f27ce43dee4f 3964 *val = LSM6DSOX_OPEN_DRAIN;
cparata 0:f27ce43dee4f 3965 break;
cparata 0:f27ce43dee4f 3966 case LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL:
cparata 0:f27ce43dee4f 3967 *val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL;
cparata 0:f27ce43dee4f 3968 break;
cparata 0:f27ce43dee4f 3969 case LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN:
cparata 0:f27ce43dee4f 3970 *val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN;
cparata 0:f27ce43dee4f 3971 break;
cparata 0:f27ce43dee4f 3972 default:
cparata 0:f27ce43dee4f 3973 *val = LSM6DSOX_PUSH_PULL;
cparata 0:f27ce43dee4f 3974 break;
cparata 0:f27ce43dee4f 3975 }
cparata 0:f27ce43dee4f 3976 return ret;
cparata 0:f27ce43dee4f 3977 }
cparata 0:f27ce43dee4f 3978
cparata 0:f27ce43dee4f 3979 /**
cparata 0:f27ce43dee4f 3980 * @brief Interrupt active-high/low.[set]
cparata 0:f27ce43dee4f 3981 *
cparata 0:f27ce43dee4f 3982 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 3983 * @param val change the values of h_lactive in reg CTRL3_C
cparata 0:f27ce43dee4f 3984 *
cparata 0:f27ce43dee4f 3985 */
cparata 0:f27ce43dee4f 3986 int32_t lsm6dsox_pin_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_h_lactive_t val)
cparata 0:f27ce43dee4f 3987 {
cparata 0:f27ce43dee4f 3988 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 3989 int32_t ret;
cparata 0:f27ce43dee4f 3990
cparata 0:f27ce43dee4f 3991 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3992 if (ret == 0) {
cparata 0:f27ce43dee4f 3993 reg.h_lactive = (uint8_t)val;
cparata 0:f27ce43dee4f 3994 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 3995 }
cparata 0:f27ce43dee4f 3996
cparata 0:f27ce43dee4f 3997 return ret;
cparata 0:f27ce43dee4f 3998 }
cparata 0:f27ce43dee4f 3999
cparata 0:f27ce43dee4f 4000 /**
cparata 0:f27ce43dee4f 4001 * @brief Interrupt active-high/low.[get]
cparata 0:f27ce43dee4f 4002 *
cparata 0:f27ce43dee4f 4003 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4004 * @param val Get the values of h_lactive in reg CTRL3_C
cparata 0:f27ce43dee4f 4005 *
cparata 0:f27ce43dee4f 4006 */
cparata 0:f27ce43dee4f 4007 int32_t lsm6dsox_pin_polarity_get(lsm6dsox_ctx_t *ctx, lsm6dsox_h_lactive_t *val)
cparata 0:f27ce43dee4f 4008 {
cparata 0:f27ce43dee4f 4009 lsm6dsox_ctrl3_c_t reg;
cparata 0:f27ce43dee4f 4010 int32_t ret;
cparata 0:f27ce43dee4f 4011
cparata 0:f27ce43dee4f 4012 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4013
cparata 0:f27ce43dee4f 4014 switch (reg.h_lactive) {
cparata 0:f27ce43dee4f 4015 case LSM6DSOX_ACTIVE_HIGH:
cparata 0:f27ce43dee4f 4016 *val = LSM6DSOX_ACTIVE_HIGH;
cparata 0:f27ce43dee4f 4017 break;
cparata 0:f27ce43dee4f 4018 case LSM6DSOX_ACTIVE_LOW:
cparata 0:f27ce43dee4f 4019 *val = LSM6DSOX_ACTIVE_LOW;
cparata 0:f27ce43dee4f 4020 break;
cparata 0:f27ce43dee4f 4021 default:
cparata 0:f27ce43dee4f 4022 *val = LSM6DSOX_ACTIVE_HIGH;
cparata 0:f27ce43dee4f 4023 break;
cparata 0:f27ce43dee4f 4024 }
cparata 0:f27ce43dee4f 4025 return ret;
cparata 0:f27ce43dee4f 4026 }
cparata 0:f27ce43dee4f 4027
cparata 0:f27ce43dee4f 4028 /**
cparata 0:f27ce43dee4f 4029 * @brief All interrupt signals become available on INT1 pin.[set]
cparata 0:f27ce43dee4f 4030 *
cparata 0:f27ce43dee4f 4031 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4032 * @param val change the values of int2_on_int1 in reg CTRL4_C
cparata 0:f27ce43dee4f 4033 *
cparata 0:f27ce43dee4f 4034 */
cparata 0:f27ce43dee4f 4035 int32_t lsm6dsox_all_on_int1_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4036 {
cparata 0:f27ce43dee4f 4037 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 4038 int32_t ret;
cparata 0:f27ce43dee4f 4039
cparata 0:f27ce43dee4f 4040 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4041 if (ret == 0) {
cparata 0:f27ce43dee4f 4042 reg.int2_on_int1 = val;
cparata 0:f27ce43dee4f 4043 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4044 }
cparata 0:f27ce43dee4f 4045
cparata 0:f27ce43dee4f 4046 return ret;
cparata 0:f27ce43dee4f 4047 }
cparata 0:f27ce43dee4f 4048
cparata 0:f27ce43dee4f 4049 /**
cparata 0:f27ce43dee4f 4050 * @brief All interrupt signals become available on INT1 pin.[get]
cparata 0:f27ce43dee4f 4051 *
cparata 0:f27ce43dee4f 4052 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4053 * @param val change the values of int2_on_int1 in reg CTRL4_C
cparata 0:f27ce43dee4f 4054 *
cparata 0:f27ce43dee4f 4055 */
cparata 0:f27ce43dee4f 4056 int32_t lsm6dsox_all_on_int1_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4057 {
cparata 0:f27ce43dee4f 4058 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 4059 int32_t ret;
cparata 0:f27ce43dee4f 4060
cparata 0:f27ce43dee4f 4061 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4062 *val = reg.int2_on_int1;
cparata 0:f27ce43dee4f 4063
cparata 0:f27ce43dee4f 4064 return ret;
cparata 0:f27ce43dee4f 4065 }
cparata 0:f27ce43dee4f 4066
cparata 0:f27ce43dee4f 4067 /**
cparata 0:f27ce43dee4f 4068 * @brief Interrupt notification mode.[set]
cparata 0:f27ce43dee4f 4069 *
cparata 0:f27ce43dee4f 4070 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4071 * @param val change the values of lir in reg TAP_CFG0
cparata 0:f27ce43dee4f 4072 *
cparata 0:f27ce43dee4f 4073 */
cparata 0:f27ce43dee4f 4074 int32_t lsm6dsox_int_notification_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t val)
cparata 0:f27ce43dee4f 4075 {
cparata 0:f27ce43dee4f 4076 lsm6dsox_tap_cfg0_t tap_cfg0;
cparata 0:f27ce43dee4f 4077 lsm6dsox_page_rw_t page_rw;
cparata 0:f27ce43dee4f 4078 int32_t ret;
cparata 0:f27ce43dee4f 4079
cparata 0:f27ce43dee4f 4080 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata 0:f27ce43dee4f 4081 if (ret == 0) {
cparata 0:f27ce43dee4f 4082 tap_cfg0.lir = (uint8_t)val & 0x01U;
cparata 0:f27ce43dee4f 4083 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
cparata 0:f27ce43dee4f 4084 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata 0:f27ce43dee4f 4085 }
cparata 0:f27ce43dee4f 4086 if (ret == 0) {
cparata 0:f27ce43dee4f 4087
cparata 0:f27ce43dee4f 4088 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 4089 }
cparata 0:f27ce43dee4f 4090 if (ret == 0) {
cparata 0:f27ce43dee4f 4091 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 4092 }
cparata 0:f27ce43dee4f 4093 if (ret == 0) {
cparata 0:f27ce43dee4f 4094 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
cparata 0:f27ce43dee4f 4095 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 4096 }
cparata 0:f27ce43dee4f 4097 if (ret == 0) {
cparata 0:f27ce43dee4f 4098 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 4099 }
cparata 0:f27ce43dee4f 4100
cparata 0:f27ce43dee4f 4101 return ret;
cparata 0:f27ce43dee4f 4102 }
cparata 0:f27ce43dee4f 4103
cparata 0:f27ce43dee4f 4104 /**
cparata 0:f27ce43dee4f 4105 * @brief Interrupt notification mode.[get]
cparata 0:f27ce43dee4f 4106 *
cparata 0:f27ce43dee4f 4107 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4108 * @param val Get the values of lir in reg TAP_CFG0
cparata 0:f27ce43dee4f 4109 *
cparata 0:f27ce43dee4f 4110 */
cparata 0:f27ce43dee4f 4111 int32_t lsm6dsox_int_notification_get(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t *val)
cparata 0:f27ce43dee4f 4112 {
cparata 0:f27ce43dee4f 4113 lsm6dsox_tap_cfg0_t tap_cfg0;
cparata 0:f27ce43dee4f 4114 lsm6dsox_page_rw_t page_rw;
cparata 0:f27ce43dee4f 4115 int32_t ret;
cparata 0:f27ce43dee4f 4116
cparata 0:f27ce43dee4f 4117
cparata 0:f27ce43dee4f 4118 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata 0:f27ce43dee4f 4119 if (ret == 0) {
cparata 0:f27ce43dee4f 4120
cparata 0:f27ce43dee4f 4121 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 4122 }
cparata 0:f27ce43dee4f 4123 if (ret == 0) {
cparata 0:f27ce43dee4f 4124 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 4125 }
cparata 0:f27ce43dee4f 4126 if (ret == 0) {
cparata 0:f27ce43dee4f 4127 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 4128 }
cparata 0:f27ce43dee4f 4129 if (ret == 0) {
cparata 0:f27ce43dee4f 4130 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir) {
cparata 0:f27ce43dee4f 4131 case LSM6DSOX_ALL_INT_PULSED:
cparata 0:f27ce43dee4f 4132 *val = LSM6DSOX_ALL_INT_PULSED;
cparata 0:f27ce43dee4f 4133 break;
cparata 0:f27ce43dee4f 4134 case LSM6DSOX_BASE_LATCHED_EMB_PULSED:
cparata 0:f27ce43dee4f 4135 *val = LSM6DSOX_BASE_LATCHED_EMB_PULSED;
cparata 0:f27ce43dee4f 4136 break;
cparata 0:f27ce43dee4f 4137 case LSM6DSOX_BASE_PULSED_EMB_LATCHED:
cparata 0:f27ce43dee4f 4138 *val = LSM6DSOX_BASE_PULSED_EMB_LATCHED;
cparata 0:f27ce43dee4f 4139 break;
cparata 0:f27ce43dee4f 4140 case LSM6DSOX_ALL_INT_LATCHED:
cparata 0:f27ce43dee4f 4141 *val = LSM6DSOX_ALL_INT_LATCHED;
cparata 0:f27ce43dee4f 4142 break;
cparata 0:f27ce43dee4f 4143 default:
cparata 0:f27ce43dee4f 4144 *val = LSM6DSOX_ALL_INT_PULSED;
cparata 0:f27ce43dee4f 4145 break;
cparata 0:f27ce43dee4f 4146 }
cparata 0:f27ce43dee4f 4147 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 4148 }
cparata 0:f27ce43dee4f 4149 if (ret == 0) {
cparata 0:f27ce43dee4f 4150 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata 0:f27ce43dee4f 4151 }
cparata 0:f27ce43dee4f 4152 if (ret == 0) {
cparata 0:f27ce43dee4f 4153 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 4154 }
cparata 0:f27ce43dee4f 4155
cparata 0:f27ce43dee4f 4156 return ret;
cparata 0:f27ce43dee4f 4157 }
cparata 0:f27ce43dee4f 4158
cparata 0:f27ce43dee4f 4159 /**
cparata 0:f27ce43dee4f 4160 * @}
cparata 0:f27ce43dee4f 4161 *
cparata 0:f27ce43dee4f 4162 */
cparata 0:f27ce43dee4f 4163
cparata 0:f27ce43dee4f 4164 /**
cparata 0:f27ce43dee4f 4165 * @defgroup LSM6DSOX_Wake_Up_event
cparata 0:f27ce43dee4f 4166 * @brief This section groups all the functions that manage the Wake Up
cparata 0:f27ce43dee4f 4167 * event generation.
cparata 0:f27ce43dee4f 4168 * @{
cparata 0:f27ce43dee4f 4169 *
cparata 0:f27ce43dee4f 4170 */
cparata 0:f27ce43dee4f 4171
cparata 0:f27ce43dee4f 4172 /**
cparata 0:f27ce43dee4f 4173 * @brief Weight of 1 LSB of wakeup threshold.[set]
cparata 0:f27ce43dee4f 4174 * 0: 1 LSB =FS_XL / 64
cparata 0:f27ce43dee4f 4175 * 1: 1 LSB = FS_XL / 256
cparata 0:f27ce43dee4f 4176 *
cparata 0:f27ce43dee4f 4177 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4178 * @param val change the values of wake_ths_w in
cparata 0:f27ce43dee4f 4179 * reg WAKE_UP_DUR
cparata 0:f27ce43dee4f 4180 *
cparata 0:f27ce43dee4f 4181 */
cparata 0:f27ce43dee4f 4182 int32_t lsm6dsox_wkup_ths_weight_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 4183 lsm6dsox_wake_ths_w_t val)
cparata 0:f27ce43dee4f 4184 {
cparata 0:f27ce43dee4f 4185 lsm6dsox_wake_up_dur_t reg;
cparata 0:f27ce43dee4f 4186 int32_t ret;
cparata 0:f27ce43dee4f 4187
cparata 0:f27ce43dee4f 4188 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4189 if (ret == 0) {
cparata 0:f27ce43dee4f 4190 reg.wake_ths_w = (uint8_t)val;
cparata 0:f27ce43dee4f 4191 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4192 }
cparata 0:f27ce43dee4f 4193 return ret;
cparata 0:f27ce43dee4f 4194 }
cparata 0:f27ce43dee4f 4195
cparata 0:f27ce43dee4f 4196 /**
cparata 0:f27ce43dee4f 4197 * @brief Weight of 1 LSB of wakeup threshold.[get]
cparata 0:f27ce43dee4f 4198 * 0: 1 LSB =FS_XL / 64
cparata 0:f27ce43dee4f 4199 * 1: 1 LSB = FS_XL / 256
cparata 0:f27ce43dee4f 4200 *
cparata 0:f27ce43dee4f 4201 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4202 * @param val Get the values of wake_ths_w in
cparata 0:f27ce43dee4f 4203 * reg WAKE_UP_DUR
cparata 0:f27ce43dee4f 4204 *
cparata 0:f27ce43dee4f 4205 */
cparata 0:f27ce43dee4f 4206 int32_t lsm6dsox_wkup_ths_weight_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 4207 lsm6dsox_wake_ths_w_t *val)
cparata 0:f27ce43dee4f 4208 {
cparata 0:f27ce43dee4f 4209 lsm6dsox_wake_up_dur_t reg;
cparata 0:f27ce43dee4f 4210 int32_t ret;
cparata 0:f27ce43dee4f 4211
cparata 0:f27ce43dee4f 4212 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4213
cparata 0:f27ce43dee4f 4214 switch (reg.wake_ths_w) {
cparata 0:f27ce43dee4f 4215 case LSM6DSOX_LSb_FS_DIV_64:
cparata 0:f27ce43dee4f 4216 *val = LSM6DSOX_LSb_FS_DIV_64;
cparata 0:f27ce43dee4f 4217 break;
cparata 0:f27ce43dee4f 4218 case LSM6DSOX_LSb_FS_DIV_256:
cparata 0:f27ce43dee4f 4219 *val = LSM6DSOX_LSb_FS_DIV_256;
cparata 0:f27ce43dee4f 4220 break;
cparata 0:f27ce43dee4f 4221 default:
cparata 0:f27ce43dee4f 4222 *val = LSM6DSOX_LSb_FS_DIV_64;
cparata 0:f27ce43dee4f 4223 break;
cparata 0:f27ce43dee4f 4224 }
cparata 0:f27ce43dee4f 4225 return ret;
cparata 0:f27ce43dee4f 4226 }
cparata 0:f27ce43dee4f 4227
cparata 0:f27ce43dee4f 4228 /**
cparata 0:f27ce43dee4f 4229 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata 0:f27ce43dee4f 4230 * WAKE_UP_DUR.[set]
cparata 0:f27ce43dee4f 4231 *
cparata 0:f27ce43dee4f 4232 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4233 * @param val change the values of wk_ths in reg WAKE_UP_THS
cparata 0:f27ce43dee4f 4234 *
cparata 0:f27ce43dee4f 4235 */
cparata 0:f27ce43dee4f 4236 int32_t lsm6dsox_wkup_threshold_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4237 {
cparata 0:f27ce43dee4f 4238 lsm6dsox_wake_up_ths_t reg;
cparata 0:f27ce43dee4f 4239 int32_t ret;
cparata 0:f27ce43dee4f 4240
cparata 0:f27ce43dee4f 4241 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4242 if (ret == 0) {
cparata 0:f27ce43dee4f 4243 reg.wk_ths = val;
cparata 0:f27ce43dee4f 4244 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4245 }
cparata 0:f27ce43dee4f 4246 return ret;
cparata 0:f27ce43dee4f 4247 }
cparata 0:f27ce43dee4f 4248
cparata 0:f27ce43dee4f 4249 /**
cparata 0:f27ce43dee4f 4250 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata 0:f27ce43dee4f 4251 * WAKE_UP_DUR.[get]
cparata 0:f27ce43dee4f 4252 *
cparata 0:f27ce43dee4f 4253 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4254 * @param val change the values of wk_ths in reg WAKE_UP_THS
cparata 0:f27ce43dee4f 4255 *
cparata 0:f27ce43dee4f 4256 */
cparata 0:f27ce43dee4f 4257 int32_t lsm6dsox_wkup_threshold_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4258 {
cparata 0:f27ce43dee4f 4259 lsm6dsox_wake_up_ths_t reg;
cparata 0:f27ce43dee4f 4260 int32_t ret;
cparata 0:f27ce43dee4f 4261
cparata 0:f27ce43dee4f 4262 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4263 *val = reg.wk_ths;
cparata 0:f27ce43dee4f 4264
cparata 0:f27ce43dee4f 4265 return ret;
cparata 0:f27ce43dee4f 4266 }
cparata 0:f27ce43dee4f 4267
cparata 0:f27ce43dee4f 4268 /**
cparata 0:f27ce43dee4f 4269 * @brief Wake up duration event.[set]
cparata 0:f27ce43dee4f 4270 * 1LSb = 1 / ODR
cparata 0:f27ce43dee4f 4271 *
cparata 0:f27ce43dee4f 4272 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4273 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata 0:f27ce43dee4f 4274 *
cparata 0:f27ce43dee4f 4275 */
cparata 0:f27ce43dee4f 4276 int32_t lsm6dsox_xl_usr_offset_on_wkup_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4277 {
cparata 0:f27ce43dee4f 4278 lsm6dsox_wake_up_ths_t reg;
cparata 0:f27ce43dee4f 4279 int32_t ret;
cparata 0:f27ce43dee4f 4280
cparata 0:f27ce43dee4f 4281 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4282 if (ret == 0) {
cparata 0:f27ce43dee4f 4283 reg.usr_off_on_wu = val;
cparata 0:f27ce43dee4f 4284 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4285 }
cparata 0:f27ce43dee4f 4286 return ret;
cparata 0:f27ce43dee4f 4287 }
cparata 0:f27ce43dee4f 4288
cparata 0:f27ce43dee4f 4289 /**
cparata 0:f27ce43dee4f 4290 * @brief Wake up duration event.[get]
cparata 0:f27ce43dee4f 4291 * 1LSb = 1 / ODR
cparata 0:f27ce43dee4f 4292 *
cparata 0:f27ce43dee4f 4293 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4294 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata 0:f27ce43dee4f 4295 *
cparata 0:f27ce43dee4f 4296 */
cparata 0:f27ce43dee4f 4297 int32_t lsm6dsox_xl_usr_offset_on_wkup_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4298 {
cparata 0:f27ce43dee4f 4299 lsm6dsox_wake_up_ths_t reg;
cparata 0:f27ce43dee4f 4300 int32_t ret;
cparata 0:f27ce43dee4f 4301
cparata 0:f27ce43dee4f 4302 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4303 *val = reg.usr_off_on_wu;
cparata 0:f27ce43dee4f 4304
cparata 0:f27ce43dee4f 4305 return ret;
cparata 0:f27ce43dee4f 4306 }
cparata 0:f27ce43dee4f 4307
cparata 0:f27ce43dee4f 4308 /**
cparata 0:f27ce43dee4f 4309 * @brief Wake up duration event.[set]
cparata 0:f27ce43dee4f 4310 * 1LSb = 1 / ODR
cparata 0:f27ce43dee4f 4311 *
cparata 0:f27ce43dee4f 4312 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4313 * @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata 0:f27ce43dee4f 4314 *
cparata 0:f27ce43dee4f 4315 */
cparata 0:f27ce43dee4f 4316 int32_t lsm6dsox_wkup_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4317 {
cparata 0:f27ce43dee4f 4318 lsm6dsox_wake_up_dur_t reg;
cparata 0:f27ce43dee4f 4319 int32_t ret;
cparata 0:f27ce43dee4f 4320
cparata 0:f27ce43dee4f 4321 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4322 if (ret == 0) {
cparata 0:f27ce43dee4f 4323 reg.wake_dur = val;
cparata 0:f27ce43dee4f 4324 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4325 }
cparata 0:f27ce43dee4f 4326 return ret;
cparata 0:f27ce43dee4f 4327 }
cparata 0:f27ce43dee4f 4328
cparata 0:f27ce43dee4f 4329 /**
cparata 0:f27ce43dee4f 4330 * @brief Wake up duration event.[get]
cparata 0:f27ce43dee4f 4331 * 1LSb = 1 / ODR
cparata 0:f27ce43dee4f 4332 *
cparata 0:f27ce43dee4f 4333 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4334 * @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata 0:f27ce43dee4f 4335 *
cparata 0:f27ce43dee4f 4336 */
cparata 0:f27ce43dee4f 4337 int32_t lsm6dsox_wkup_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4338 {
cparata 0:f27ce43dee4f 4339 lsm6dsox_wake_up_dur_t reg;
cparata 0:f27ce43dee4f 4340 int32_t ret;
cparata 0:f27ce43dee4f 4341
cparata 0:f27ce43dee4f 4342 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4343 *val = reg.wake_dur;
cparata 0:f27ce43dee4f 4344
cparata 0:f27ce43dee4f 4345 return ret;
cparata 0:f27ce43dee4f 4346 }
cparata 0:f27ce43dee4f 4347
cparata 0:f27ce43dee4f 4348 /**
cparata 0:f27ce43dee4f 4349 * @}
cparata 0:f27ce43dee4f 4350 *
cparata 0:f27ce43dee4f 4351 */
cparata 0:f27ce43dee4f 4352
cparata 0:f27ce43dee4f 4353 /**
cparata 0:f27ce43dee4f 4354 * @defgroup LSM6DSOX_ Activity/Inactivity_detection
cparata 0:f27ce43dee4f 4355 * @brief This section groups all the functions concerning
cparata 0:f27ce43dee4f 4356 * activity/inactivity detection.
cparata 0:f27ce43dee4f 4357 * @{
cparata 0:f27ce43dee4f 4358 *
cparata 0:f27ce43dee4f 4359 */
cparata 0:f27ce43dee4f 4360
cparata 0:f27ce43dee4f 4361 /**
cparata 0:f27ce43dee4f 4362 * @brief Enables gyroscope Sleep mode.[set]
cparata 0:f27ce43dee4f 4363 *
cparata 0:f27ce43dee4f 4364 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4365 * @param val change the values of sleep_g in reg CTRL4_C
cparata 0:f27ce43dee4f 4366 *
cparata 0:f27ce43dee4f 4367 */
cparata 0:f27ce43dee4f 4368 int32_t lsm6dsox_gy_sleep_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4369 {
cparata 0:f27ce43dee4f 4370 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 4371 int32_t ret;
cparata 0:f27ce43dee4f 4372
cparata 0:f27ce43dee4f 4373 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4374 if (ret == 0) {
cparata 0:f27ce43dee4f 4375 reg.sleep_g = val;
cparata 0:f27ce43dee4f 4376 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4377 }
cparata 0:f27ce43dee4f 4378 return ret;
cparata 0:f27ce43dee4f 4379 }
cparata 0:f27ce43dee4f 4380
cparata 0:f27ce43dee4f 4381 /**
cparata 0:f27ce43dee4f 4382 * @brief Enables gyroscope Sleep mode.[get]
cparata 0:f27ce43dee4f 4383 *
cparata 0:f27ce43dee4f 4384 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4385 * @param val change the values of sleep_g in reg CTRL4_C
cparata 0:f27ce43dee4f 4386 *
cparata 0:f27ce43dee4f 4387 */
cparata 0:f27ce43dee4f 4388 int32_t lsm6dsox_gy_sleep_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4389 {
cparata 0:f27ce43dee4f 4390 lsm6dsox_ctrl4_c_t reg;
cparata 0:f27ce43dee4f 4391 int32_t ret;
cparata 0:f27ce43dee4f 4392
cparata 0:f27ce43dee4f 4393 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4394 *val = reg.sleep_g;
cparata 0:f27ce43dee4f 4395
cparata 0:f27ce43dee4f 4396 return ret;
cparata 0:f27ce43dee4f 4397 }
cparata 0:f27ce43dee4f 4398
cparata 0:f27ce43dee4f 4399 /**
cparata 0:f27ce43dee4f 4400 * @brief Drives the sleep status instead of
cparata 0:f27ce43dee4f 4401 * sleep change on INT pins
cparata 0:f27ce43dee4f 4402 * (only if INT1_SLEEP_CHANGE or
cparata 0:f27ce43dee4f 4403 * INT2_SLEEP_CHANGE bits are enabled).[set]
cparata 0:f27ce43dee4f 4404 *
cparata 0:f27ce43dee4f 4405 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4406 * @param val change the values of sleep_status_on_int in reg TAP_CFG0
cparata 0:f27ce43dee4f 4407 *
cparata 0:f27ce43dee4f 4408 */
cparata 0:f27ce43dee4f 4409 int32_t lsm6dsox_act_pin_notification_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 4410 lsm6dsox_sleep_status_on_int_t val)
cparata 0:f27ce43dee4f 4411 {
cparata 0:f27ce43dee4f 4412 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 4413 int32_t ret;
cparata 0:f27ce43dee4f 4414
cparata 0:f27ce43dee4f 4415 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4416 if (ret == 0) {
cparata 0:f27ce43dee4f 4417 reg.sleep_status_on_int = (uint8_t)val;
cparata 0:f27ce43dee4f 4418 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4419 }
cparata 0:f27ce43dee4f 4420 return ret;
cparata 0:f27ce43dee4f 4421 }
cparata 0:f27ce43dee4f 4422
cparata 0:f27ce43dee4f 4423 /**
cparata 0:f27ce43dee4f 4424 * @brief Drives the sleep status instead of
cparata 0:f27ce43dee4f 4425 * sleep change on INT pins (only if
cparata 0:f27ce43dee4f 4426 * INT1_SLEEP_CHANGE or
cparata 0:f27ce43dee4f 4427 * INT2_SLEEP_CHANGE bits are enabled).[get]
cparata 0:f27ce43dee4f 4428 *
cparata 0:f27ce43dee4f 4429 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4430 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
cparata 0:f27ce43dee4f 4431 *
cparata 0:f27ce43dee4f 4432 */
cparata 0:f27ce43dee4f 4433 int32_t lsm6dsox_act_pin_notification_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 4434 lsm6dsox_sleep_status_on_int_t *val)
cparata 0:f27ce43dee4f 4435 {
cparata 0:f27ce43dee4f 4436 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 4437 int32_t ret;
cparata 0:f27ce43dee4f 4438
cparata 0:f27ce43dee4f 4439 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4440 switch (reg.sleep_status_on_int) {
cparata 0:f27ce43dee4f 4441 case LSM6DSOX_DRIVE_SLEEP_CHG_EVENT:
cparata 0:f27ce43dee4f 4442 *val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT;
cparata 0:f27ce43dee4f 4443 break;
cparata 0:f27ce43dee4f 4444 case LSM6DSOX_DRIVE_SLEEP_STATUS:
cparata 0:f27ce43dee4f 4445 *val = LSM6DSOX_DRIVE_SLEEP_STATUS;
cparata 0:f27ce43dee4f 4446 break;
cparata 0:f27ce43dee4f 4447 default:
cparata 0:f27ce43dee4f 4448 *val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT;
cparata 0:f27ce43dee4f 4449 break;
cparata 0:f27ce43dee4f 4450 }
cparata 0:f27ce43dee4f 4451 return ret;
cparata 0:f27ce43dee4f 4452 }
cparata 0:f27ce43dee4f 4453
cparata 0:f27ce43dee4f 4454 /**
cparata 0:f27ce43dee4f 4455 * @brief Enable inactivity function.[set]
cparata 0:f27ce43dee4f 4456 *
cparata 0:f27ce43dee4f 4457 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4458 * @param val change the values of inact_en in reg TAP_CFG2
cparata 0:f27ce43dee4f 4459 *
cparata 0:f27ce43dee4f 4460 */
cparata 0:f27ce43dee4f 4461 int32_t lsm6dsox_act_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t val)
cparata 0:f27ce43dee4f 4462 {
cparata 0:f27ce43dee4f 4463 lsm6dsox_tap_cfg2_t reg;
cparata 0:f27ce43dee4f 4464 int32_t ret;
cparata 0:f27ce43dee4f 4465
cparata 0:f27ce43dee4f 4466 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4467 if (ret == 0) {
cparata 0:f27ce43dee4f 4468 reg.inact_en = (uint8_t)val;
cparata 0:f27ce43dee4f 4469 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4470 }
cparata 0:f27ce43dee4f 4471 return ret;
cparata 0:f27ce43dee4f 4472 }
cparata 0:f27ce43dee4f 4473
cparata 0:f27ce43dee4f 4474 /**
cparata 0:f27ce43dee4f 4475 * @brief Enable inactivity function.[get]
cparata 0:f27ce43dee4f 4476 *
cparata 0:f27ce43dee4f 4477 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4478 * @param val Get the values of inact_en in reg TAP_CFG2
cparata 0:f27ce43dee4f 4479 *
cparata 0:f27ce43dee4f 4480 */
cparata 0:f27ce43dee4f 4481 int32_t lsm6dsox_act_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t *val)
cparata 0:f27ce43dee4f 4482 {
cparata 0:f27ce43dee4f 4483 lsm6dsox_tap_cfg2_t reg;
cparata 0:f27ce43dee4f 4484 int32_t ret;
cparata 0:f27ce43dee4f 4485
cparata 0:f27ce43dee4f 4486 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4487 switch (reg.inact_en) {
cparata 0:f27ce43dee4f 4488 case LSM6DSOX_XL_AND_GY_NOT_AFFECTED:
cparata 0:f27ce43dee4f 4489 *val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED;
cparata 0:f27ce43dee4f 4490 break;
cparata 0:f27ce43dee4f 4491 case LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED:
cparata 0:f27ce43dee4f 4492 *val = LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED;
cparata 0:f27ce43dee4f 4493 break;
cparata 0:f27ce43dee4f 4494 case LSM6DSOX_XL_12Hz5_GY_SLEEP:
cparata 0:f27ce43dee4f 4495 *val = LSM6DSOX_XL_12Hz5_GY_SLEEP;
cparata 0:f27ce43dee4f 4496 break;
cparata 0:f27ce43dee4f 4497 case LSM6DSOX_XL_12Hz5_GY_PD:
cparata 0:f27ce43dee4f 4498 *val = LSM6DSOX_XL_12Hz5_GY_PD;
cparata 0:f27ce43dee4f 4499 break;
cparata 0:f27ce43dee4f 4500 default:
cparata 0:f27ce43dee4f 4501 *val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED;
cparata 0:f27ce43dee4f 4502 break;
cparata 0:f27ce43dee4f 4503 }
cparata 0:f27ce43dee4f 4504 return ret;
cparata 0:f27ce43dee4f 4505 }
cparata 0:f27ce43dee4f 4506
cparata 0:f27ce43dee4f 4507 /**
cparata 0:f27ce43dee4f 4508 * @brief Duration to go in sleep mode.[set]
cparata 0:f27ce43dee4f 4509 * 1 LSb = 512 / ODR
cparata 0:f27ce43dee4f 4510 *
cparata 0:f27ce43dee4f 4511 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4512 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata 0:f27ce43dee4f 4513 *
cparata 0:f27ce43dee4f 4514 */
cparata 0:f27ce43dee4f 4515 int32_t lsm6dsox_act_sleep_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4516 {
cparata 0:f27ce43dee4f 4517 lsm6dsox_wake_up_dur_t reg;
cparata 0:f27ce43dee4f 4518 int32_t ret;
cparata 0:f27ce43dee4f 4519
cparata 0:f27ce43dee4f 4520 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4521 if (ret == 0) {
cparata 0:f27ce43dee4f 4522 reg.sleep_dur = val;
cparata 0:f27ce43dee4f 4523 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4524 }
cparata 0:f27ce43dee4f 4525 return ret;
cparata 0:f27ce43dee4f 4526 }
cparata 0:f27ce43dee4f 4527
cparata 0:f27ce43dee4f 4528 /**
cparata 0:f27ce43dee4f 4529 * @brief Duration to go in sleep mode.[get]
cparata 0:f27ce43dee4f 4530 * 1 LSb = 512 / ODR
cparata 0:f27ce43dee4f 4531 *
cparata 0:f27ce43dee4f 4532 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4533 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata 0:f27ce43dee4f 4534 *
cparata 0:f27ce43dee4f 4535 */
cparata 0:f27ce43dee4f 4536 int32_t lsm6dsox_act_sleep_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4537 {
cparata 0:f27ce43dee4f 4538 lsm6dsox_wake_up_dur_t reg;
cparata 0:f27ce43dee4f 4539 int32_t ret;
cparata 0:f27ce43dee4f 4540
cparata 0:f27ce43dee4f 4541 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4542 *val = reg.sleep_dur;
cparata 0:f27ce43dee4f 4543
cparata 0:f27ce43dee4f 4544 return ret;
cparata 0:f27ce43dee4f 4545 }
cparata 0:f27ce43dee4f 4546
cparata 0:f27ce43dee4f 4547 /**
cparata 0:f27ce43dee4f 4548 * @}
cparata 0:f27ce43dee4f 4549 *
cparata 0:f27ce43dee4f 4550 */
cparata 0:f27ce43dee4f 4551
cparata 0:f27ce43dee4f 4552 /**
cparata 0:f27ce43dee4f 4553 * @defgroup LSM6DSOX_tap_generator
cparata 0:f27ce43dee4f 4554 * @brief This section groups all the functions that manage the
cparata 0:f27ce43dee4f 4555 * tap and double tap event generation.
cparata 0:f27ce43dee4f 4556 * @{
cparata 0:f27ce43dee4f 4557 *
cparata 0:f27ce43dee4f 4558 */
cparata 0:f27ce43dee4f 4559
cparata 0:f27ce43dee4f 4560 /**
cparata 0:f27ce43dee4f 4561 * @brief Enable Z direction in tap recognition.[set]
cparata 0:f27ce43dee4f 4562 *
cparata 0:f27ce43dee4f 4563 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4564 * @param val change the values of tap_z_en in reg TAP_CFG0
cparata 0:f27ce43dee4f 4565 *
cparata 0:f27ce43dee4f 4566 */
cparata 0:f27ce43dee4f 4567 int32_t lsm6dsox_tap_detection_on_z_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4568 {
cparata 0:f27ce43dee4f 4569 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 4570 int32_t ret;
cparata 0:f27ce43dee4f 4571
cparata 0:f27ce43dee4f 4572 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4573 if (ret == 0) {
cparata 0:f27ce43dee4f 4574 reg.tap_z_en = val;
cparata 0:f27ce43dee4f 4575 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4576 }
cparata 0:f27ce43dee4f 4577 return ret;
cparata 0:f27ce43dee4f 4578 }
cparata 0:f27ce43dee4f 4579
cparata 0:f27ce43dee4f 4580 /**
cparata 0:f27ce43dee4f 4581 * @brief Enable Z direction in tap recognition.[get]
cparata 0:f27ce43dee4f 4582 *
cparata 0:f27ce43dee4f 4583 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4584 * @param val change the values of tap_z_en in reg TAP_CFG0
cparata 0:f27ce43dee4f 4585 *
cparata 0:f27ce43dee4f 4586 */
cparata 0:f27ce43dee4f 4587 int32_t lsm6dsox_tap_detection_on_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4588 {
cparata 0:f27ce43dee4f 4589 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 4590 int32_t ret;
cparata 0:f27ce43dee4f 4591
cparata 0:f27ce43dee4f 4592 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4593 *val = reg.tap_z_en;
cparata 0:f27ce43dee4f 4594
cparata 0:f27ce43dee4f 4595 return ret;
cparata 0:f27ce43dee4f 4596 }
cparata 0:f27ce43dee4f 4597
cparata 0:f27ce43dee4f 4598 /**
cparata 0:f27ce43dee4f 4599 * @brief Enable Y direction in tap recognition.[set]
cparata 0:f27ce43dee4f 4600 *
cparata 0:f27ce43dee4f 4601 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4602 * @param val change the values of tap_y_en in reg TAP_CFG0
cparata 0:f27ce43dee4f 4603 *
cparata 0:f27ce43dee4f 4604 */
cparata 0:f27ce43dee4f 4605 int32_t lsm6dsox_tap_detection_on_y_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4606 {
cparata 0:f27ce43dee4f 4607 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 4608 int32_t ret;
cparata 0:f27ce43dee4f 4609
cparata 0:f27ce43dee4f 4610 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4611 if (ret == 0) {
cparata 0:f27ce43dee4f 4612 reg.tap_y_en = val;
cparata 0:f27ce43dee4f 4613 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4614 }
cparata 0:f27ce43dee4f 4615 return ret;
cparata 0:f27ce43dee4f 4616 }
cparata 0:f27ce43dee4f 4617
cparata 0:f27ce43dee4f 4618 /**
cparata 0:f27ce43dee4f 4619 * @brief Enable Y direction in tap recognition.[get]
cparata 0:f27ce43dee4f 4620 *
cparata 0:f27ce43dee4f 4621 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4622 * @param val change the values of tap_y_en in reg TAP_CFG0
cparata 0:f27ce43dee4f 4623 *
cparata 0:f27ce43dee4f 4624 */
cparata 0:f27ce43dee4f 4625 int32_t lsm6dsox_tap_detection_on_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4626 {
cparata 0:f27ce43dee4f 4627 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 4628 int32_t ret;
cparata 0:f27ce43dee4f 4629
cparata 0:f27ce43dee4f 4630 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4631 *val = reg.tap_y_en;
cparata 0:f27ce43dee4f 4632
cparata 0:f27ce43dee4f 4633 return ret;
cparata 0:f27ce43dee4f 4634 }
cparata 0:f27ce43dee4f 4635
cparata 0:f27ce43dee4f 4636 /**
cparata 0:f27ce43dee4f 4637 * @brief Enable X direction in tap recognition.[set]
cparata 0:f27ce43dee4f 4638 *
cparata 0:f27ce43dee4f 4639 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4640 * @param val change the values of tap_x_en in reg TAP_CFG0
cparata 0:f27ce43dee4f 4641 *
cparata 0:f27ce43dee4f 4642 */
cparata 0:f27ce43dee4f 4643 int32_t lsm6dsox_tap_detection_on_x_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4644 {
cparata 0:f27ce43dee4f 4645 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 4646 int32_t ret;
cparata 0:f27ce43dee4f 4647
cparata 0:f27ce43dee4f 4648 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4649 if (ret == 0) {
cparata 0:f27ce43dee4f 4650 reg.tap_x_en = val;
cparata 0:f27ce43dee4f 4651 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4652 }
cparata 0:f27ce43dee4f 4653 return ret;
cparata 0:f27ce43dee4f 4654 }
cparata 0:f27ce43dee4f 4655
cparata 0:f27ce43dee4f 4656 /**
cparata 0:f27ce43dee4f 4657 * @brief Enable X direction in tap recognition.[get]
cparata 0:f27ce43dee4f 4658 *
cparata 0:f27ce43dee4f 4659 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4660 * @param val change the values of tap_x_en in reg TAP_CFG0
cparata 0:f27ce43dee4f 4661 *
cparata 0:f27ce43dee4f 4662 */
cparata 0:f27ce43dee4f 4663 int32_t lsm6dsox_tap_detection_on_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4664 {
cparata 0:f27ce43dee4f 4665 lsm6dsox_tap_cfg0_t reg;
cparata 0:f27ce43dee4f 4666 int32_t ret;
cparata 0:f27ce43dee4f 4667
cparata 0:f27ce43dee4f 4668 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4669 *val = reg.tap_x_en;
cparata 0:f27ce43dee4f 4670
cparata 0:f27ce43dee4f 4671 return ret;
cparata 0:f27ce43dee4f 4672 }
cparata 0:f27ce43dee4f 4673
cparata 0:f27ce43dee4f 4674 /**
cparata 0:f27ce43dee4f 4675 * @brief X-axis tap recognition threshold.[set]
cparata 0:f27ce43dee4f 4676 *
cparata 0:f27ce43dee4f 4677 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4678 * @param val change the values of tap_ths_x in reg TAP_CFG1
cparata 0:f27ce43dee4f 4679 *
cparata 0:f27ce43dee4f 4680 */
cparata 0:f27ce43dee4f 4681 int32_t lsm6dsox_tap_threshold_x_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4682 {
cparata 0:f27ce43dee4f 4683 lsm6dsox_tap_cfg1_t reg;
cparata 0:f27ce43dee4f 4684 int32_t ret;
cparata 0:f27ce43dee4f 4685
cparata 0:f27ce43dee4f 4686 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4687 if (ret == 0) {
cparata 0:f27ce43dee4f 4688 reg.tap_ths_x = val;
cparata 0:f27ce43dee4f 4689 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4690 }
cparata 0:f27ce43dee4f 4691 return ret;
cparata 0:f27ce43dee4f 4692 }
cparata 0:f27ce43dee4f 4693
cparata 0:f27ce43dee4f 4694 /**
cparata 0:f27ce43dee4f 4695 * @brief X-axis tap recognition threshold.[get]
cparata 0:f27ce43dee4f 4696 *
cparata 0:f27ce43dee4f 4697 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4698 * @param val change the values of tap_ths_x in reg TAP_CFG1
cparata 0:f27ce43dee4f 4699 *
cparata 0:f27ce43dee4f 4700 */
cparata 0:f27ce43dee4f 4701 int32_t lsm6dsox_tap_threshold_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4702 {
cparata 0:f27ce43dee4f 4703 lsm6dsox_tap_cfg1_t reg;
cparata 0:f27ce43dee4f 4704 int32_t ret;
cparata 0:f27ce43dee4f 4705
cparata 0:f27ce43dee4f 4706 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4707 *val = reg.tap_ths_x;
cparata 0:f27ce43dee4f 4708
cparata 0:f27ce43dee4f 4709 return ret;
cparata 0:f27ce43dee4f 4710 }
cparata 0:f27ce43dee4f 4711
cparata 0:f27ce43dee4f 4712 /**
cparata 0:f27ce43dee4f 4713 * @brief Selection of axis priority for TAP detection.[set]
cparata 0:f27ce43dee4f 4714 *
cparata 0:f27ce43dee4f 4715 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4716 * @param val change the values of tap_priority in
cparata 0:f27ce43dee4f 4717 * reg TAP_CFG1
cparata 0:f27ce43dee4f 4718 *
cparata 0:f27ce43dee4f 4719 */
cparata 0:f27ce43dee4f 4720 int32_t lsm6dsox_tap_axis_priority_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 4721 lsm6dsox_tap_priority_t val)
cparata 0:f27ce43dee4f 4722 {
cparata 0:f27ce43dee4f 4723 lsm6dsox_tap_cfg1_t reg;
cparata 0:f27ce43dee4f 4724 int32_t ret;
cparata 0:f27ce43dee4f 4725
cparata 0:f27ce43dee4f 4726 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4727 if (ret == 0) {
cparata 0:f27ce43dee4f 4728 reg.tap_priority = (uint8_t)val;
cparata 0:f27ce43dee4f 4729 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4730 }
cparata 0:f27ce43dee4f 4731 return ret;
cparata 0:f27ce43dee4f 4732 }
cparata 0:f27ce43dee4f 4733
cparata 0:f27ce43dee4f 4734 /**
cparata 0:f27ce43dee4f 4735 * @brief Selection of axis priority for TAP detection.[get]
cparata 0:f27ce43dee4f 4736 *
cparata 0:f27ce43dee4f 4737 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4738 * @param val Get the values of tap_priority in
cparata 0:f27ce43dee4f 4739 * reg TAP_CFG1
cparata 0:f27ce43dee4f 4740 *
cparata 0:f27ce43dee4f 4741 */
cparata 0:f27ce43dee4f 4742 int32_t lsm6dsox_tap_axis_priority_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 4743 lsm6dsox_tap_priority_t *val)
cparata 0:f27ce43dee4f 4744 {
cparata 0:f27ce43dee4f 4745 lsm6dsox_tap_cfg1_t reg;
cparata 0:f27ce43dee4f 4746 int32_t ret;
cparata 0:f27ce43dee4f 4747
cparata 0:f27ce43dee4f 4748 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4749 switch (reg.tap_priority) {
cparata 0:f27ce43dee4f 4750 case LSM6DSOX_XYZ:
cparata 0:f27ce43dee4f 4751 *val = LSM6DSOX_XYZ;
cparata 0:f27ce43dee4f 4752 break;
cparata 0:f27ce43dee4f 4753 case LSM6DSOX_YXZ:
cparata 0:f27ce43dee4f 4754 *val = LSM6DSOX_YXZ;
cparata 0:f27ce43dee4f 4755 break;
cparata 0:f27ce43dee4f 4756 case LSM6DSOX_XZY:
cparata 0:f27ce43dee4f 4757 *val = LSM6DSOX_XZY;
cparata 0:f27ce43dee4f 4758 break;
cparata 0:f27ce43dee4f 4759 case LSM6DSOX_ZYX:
cparata 0:f27ce43dee4f 4760 *val = LSM6DSOX_ZYX;
cparata 0:f27ce43dee4f 4761 break;
cparata 0:f27ce43dee4f 4762 case LSM6DSOX_YZX:
cparata 0:f27ce43dee4f 4763 *val = LSM6DSOX_YZX;
cparata 0:f27ce43dee4f 4764 break;
cparata 0:f27ce43dee4f 4765 case LSM6DSOX_ZXY:
cparata 0:f27ce43dee4f 4766 *val = LSM6DSOX_ZXY;
cparata 0:f27ce43dee4f 4767 break;
cparata 0:f27ce43dee4f 4768 default:
cparata 0:f27ce43dee4f 4769 *val = LSM6DSOX_XYZ;
cparata 0:f27ce43dee4f 4770 break;
cparata 0:f27ce43dee4f 4771 }
cparata 0:f27ce43dee4f 4772 return ret;
cparata 0:f27ce43dee4f 4773 }
cparata 0:f27ce43dee4f 4774
cparata 0:f27ce43dee4f 4775 /**
cparata 0:f27ce43dee4f 4776 * @brief Y-axis tap recognition threshold.[set]
cparata 0:f27ce43dee4f 4777 *
cparata 0:f27ce43dee4f 4778 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4779 * @param val change the values of tap_ths_y in reg TAP_CFG2
cparata 0:f27ce43dee4f 4780 *
cparata 0:f27ce43dee4f 4781 */
cparata 0:f27ce43dee4f 4782 int32_t lsm6dsox_tap_threshold_y_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4783 {
cparata 0:f27ce43dee4f 4784 lsm6dsox_tap_cfg2_t reg;
cparata 0:f27ce43dee4f 4785 int32_t ret;
cparata 0:f27ce43dee4f 4786
cparata 0:f27ce43dee4f 4787 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4788 if (ret == 0) {
cparata 0:f27ce43dee4f 4789 reg.tap_ths_y = val;
cparata 0:f27ce43dee4f 4790 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4791 }
cparata 0:f27ce43dee4f 4792 return ret;
cparata 0:f27ce43dee4f 4793 }
cparata 0:f27ce43dee4f 4794
cparata 0:f27ce43dee4f 4795 /**
cparata 0:f27ce43dee4f 4796 * @brief Y-axis tap recognition threshold.[get]
cparata 0:f27ce43dee4f 4797 *
cparata 0:f27ce43dee4f 4798 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4799 * @param val change the values of tap_ths_y in reg TAP_CFG2
cparata 0:f27ce43dee4f 4800 *
cparata 0:f27ce43dee4f 4801 */
cparata 0:f27ce43dee4f 4802 int32_t lsm6dsox_tap_threshold_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4803 {
cparata 0:f27ce43dee4f 4804 lsm6dsox_tap_cfg2_t reg;
cparata 0:f27ce43dee4f 4805 int32_t ret;
cparata 0:f27ce43dee4f 4806
cparata 0:f27ce43dee4f 4807 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4808 *val = reg.tap_ths_y;
cparata 0:f27ce43dee4f 4809
cparata 0:f27ce43dee4f 4810 return ret;
cparata 0:f27ce43dee4f 4811 }
cparata 0:f27ce43dee4f 4812
cparata 0:f27ce43dee4f 4813 /**
cparata 0:f27ce43dee4f 4814 * @brief Z-axis recognition threshold.[set]
cparata 0:f27ce43dee4f 4815 *
cparata 0:f27ce43dee4f 4816 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4817 * @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata 0:f27ce43dee4f 4818 *
cparata 0:f27ce43dee4f 4819 */
cparata 0:f27ce43dee4f 4820 int32_t lsm6dsox_tap_threshold_z_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4821 {
cparata 0:f27ce43dee4f 4822 lsm6dsox_tap_ths_6d_t reg;
cparata 0:f27ce43dee4f 4823 int32_t ret;
cparata 0:f27ce43dee4f 4824
cparata 0:f27ce43dee4f 4825 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4826 if (ret == 0) {
cparata 0:f27ce43dee4f 4827 reg.tap_ths_z = val;
cparata 0:f27ce43dee4f 4828 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4829 }
cparata 0:f27ce43dee4f 4830 return ret;
cparata 0:f27ce43dee4f 4831 }
cparata 0:f27ce43dee4f 4832
cparata 0:f27ce43dee4f 4833 /**
cparata 0:f27ce43dee4f 4834 * @brief Z-axis recognition threshold.[get]
cparata 0:f27ce43dee4f 4835 *
cparata 0:f27ce43dee4f 4836 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4837 * @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata 0:f27ce43dee4f 4838 *
cparata 0:f27ce43dee4f 4839 */
cparata 0:f27ce43dee4f 4840 int32_t lsm6dsox_tap_threshold_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4841 {
cparata 0:f27ce43dee4f 4842 lsm6dsox_tap_ths_6d_t reg;
cparata 0:f27ce43dee4f 4843 int32_t ret;
cparata 0:f27ce43dee4f 4844
cparata 0:f27ce43dee4f 4845 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4846 *val = reg.tap_ths_z;
cparata 0:f27ce43dee4f 4847
cparata 0:f27ce43dee4f 4848 return ret;
cparata 0:f27ce43dee4f 4849 }
cparata 0:f27ce43dee4f 4850
cparata 0:f27ce43dee4f 4851 /**
cparata 0:f27ce43dee4f 4852 * @brief Maximum duration is the maximum time of an
cparata 0:f27ce43dee4f 4853 * over threshold signal detection to be recognized
cparata 0:f27ce43dee4f 4854 * as a tap event. The default value of these bits
cparata 0:f27ce43dee4f 4855 * is 00b which corresponds to 4*ODR_XL time.
cparata 0:f27ce43dee4f 4856 * If the SHOCK[1:0] bits are set to a different
cparata 0:f27ce43dee4f 4857 * value, 1LSB corresponds to 8*ODR_XL time.[set]
cparata 0:f27ce43dee4f 4858 *
cparata 0:f27ce43dee4f 4859 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4860 * @param val change the values of shock in reg INT_DUR2
cparata 0:f27ce43dee4f 4861 *
cparata 0:f27ce43dee4f 4862 */
cparata 0:f27ce43dee4f 4863 int32_t lsm6dsox_tap_shock_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4864 {
cparata 0:f27ce43dee4f 4865 lsm6dsox_int_dur2_t reg;
cparata 0:f27ce43dee4f 4866 int32_t ret;
cparata 0:f27ce43dee4f 4867
cparata 0:f27ce43dee4f 4868 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4869 if (ret == 0) {
cparata 0:f27ce43dee4f 4870 reg.shock = val;
cparata 0:f27ce43dee4f 4871 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4872 }
cparata 0:f27ce43dee4f 4873 return ret;
cparata 0:f27ce43dee4f 4874 }
cparata 0:f27ce43dee4f 4875
cparata 0:f27ce43dee4f 4876 /**
cparata 0:f27ce43dee4f 4877 * @brief Maximum duration is the maximum time of an
cparata 0:f27ce43dee4f 4878 * over threshold signal detection to be recognized
cparata 0:f27ce43dee4f 4879 * as a tap event. The default value of these bits
cparata 0:f27ce43dee4f 4880 * is 00b which corresponds to 4*ODR_XL time.
cparata 0:f27ce43dee4f 4881 * If the SHOCK[1:0] bits are set to a different
cparata 0:f27ce43dee4f 4882 * value, 1LSB corresponds to 8*ODR_XL time.[get]
cparata 0:f27ce43dee4f 4883 *
cparata 0:f27ce43dee4f 4884 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4885 * @param val change the values of shock in reg INT_DUR2
cparata 0:f27ce43dee4f 4886 *
cparata 0:f27ce43dee4f 4887 */
cparata 0:f27ce43dee4f 4888 int32_t lsm6dsox_tap_shock_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4889 {
cparata 0:f27ce43dee4f 4890 lsm6dsox_int_dur2_t reg;
cparata 0:f27ce43dee4f 4891 int32_t ret;
cparata 0:f27ce43dee4f 4892
cparata 0:f27ce43dee4f 4893 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4894 *val = reg.shock;
cparata 0:f27ce43dee4f 4895
cparata 0:f27ce43dee4f 4896 return ret;
cparata 0:f27ce43dee4f 4897 }
cparata 0:f27ce43dee4f 4898
cparata 0:f27ce43dee4f 4899 /**
cparata 0:f27ce43dee4f 4900 * @brief Quiet time is the time after the first detected
cparata 0:f27ce43dee4f 4901 * tap in which there must not be any over threshold
cparata 0:f27ce43dee4f 4902 * event.
cparata 0:f27ce43dee4f 4903 * The default value of these bits is 00b which
cparata 0:f27ce43dee4f 4904 * corresponds to 2*ODR_XL time. If the QUIET[1:0]
cparata 0:f27ce43dee4f 4905 * bits are set to a different value,
cparata 0:f27ce43dee4f 4906 * 1LSB corresponds to 4*ODR_XL time.[set]
cparata 0:f27ce43dee4f 4907 *
cparata 0:f27ce43dee4f 4908 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4909 * @param val change the values of quiet in reg INT_DUR2
cparata 0:f27ce43dee4f 4910 *
cparata 0:f27ce43dee4f 4911 */
cparata 0:f27ce43dee4f 4912 int32_t lsm6dsox_tap_quiet_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4913 {
cparata 0:f27ce43dee4f 4914 lsm6dsox_int_dur2_t reg;
cparata 0:f27ce43dee4f 4915 int32_t ret;
cparata 0:f27ce43dee4f 4916
cparata 0:f27ce43dee4f 4917 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4918 if (ret == 0) {
cparata 0:f27ce43dee4f 4919 reg.quiet = val;
cparata 0:f27ce43dee4f 4920 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4921 }
cparata 0:f27ce43dee4f 4922 return ret;
cparata 0:f27ce43dee4f 4923 }
cparata 0:f27ce43dee4f 4924
cparata 0:f27ce43dee4f 4925 /**
cparata 0:f27ce43dee4f 4926 * @brief Quiet time is the time after the first detected
cparata 0:f27ce43dee4f 4927 * tap in which there must not be any over threshold
cparata 0:f27ce43dee4f 4928 * event.
cparata 0:f27ce43dee4f 4929 * The default value of these bits is 00b which
cparata 0:f27ce43dee4f 4930 * corresponds to 2*ODR_XL time.
cparata 0:f27ce43dee4f 4931 * If the QUIET[1:0] bits are set to a different
cparata 0:f27ce43dee4f 4932 * value, 1LSB corresponds to 4*ODR_XL time.[get]
cparata 0:f27ce43dee4f 4933 *
cparata 0:f27ce43dee4f 4934 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4935 * @param val change the values of quiet in reg INT_DUR2
cparata 0:f27ce43dee4f 4936 *
cparata 0:f27ce43dee4f 4937 */
cparata 0:f27ce43dee4f 4938 int32_t lsm6dsox_tap_quiet_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4939 {
cparata 0:f27ce43dee4f 4940 lsm6dsox_int_dur2_t reg;
cparata 0:f27ce43dee4f 4941 int32_t ret;
cparata 0:f27ce43dee4f 4942
cparata 0:f27ce43dee4f 4943 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4944 *val = reg.quiet;
cparata 0:f27ce43dee4f 4945
cparata 0:f27ce43dee4f 4946 return ret;
cparata 0:f27ce43dee4f 4947 }
cparata 0:f27ce43dee4f 4948
cparata 0:f27ce43dee4f 4949 /**
cparata 0:f27ce43dee4f 4950 * @brief When double tap recognition is enabled,
cparata 0:f27ce43dee4f 4951 * this register expresses the maximum time
cparata 0:f27ce43dee4f 4952 * between two consecutive detected taps to
cparata 0:f27ce43dee4f 4953 * determine a double tap event.
cparata 0:f27ce43dee4f 4954 * The default value of these bits is 0000b which
cparata 0:f27ce43dee4f 4955 * corresponds to 16*ODR_XL time.
cparata 0:f27ce43dee4f 4956 * If the DUR[3:0] bits are set to a different value,
cparata 0:f27ce43dee4f 4957 * 1LSB corresponds to 32*ODR_XL time.[set]
cparata 0:f27ce43dee4f 4958 *
cparata 0:f27ce43dee4f 4959 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4960 * @param val change the values of dur in reg INT_DUR2
cparata 0:f27ce43dee4f 4961 *
cparata 0:f27ce43dee4f 4962 */
cparata 0:f27ce43dee4f 4963 int32_t lsm6dsox_tap_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 4964 {
cparata 0:f27ce43dee4f 4965 lsm6dsox_int_dur2_t reg;
cparata 0:f27ce43dee4f 4966 int32_t ret;
cparata 0:f27ce43dee4f 4967
cparata 0:f27ce43dee4f 4968 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4969 if (ret == 0) {
cparata 0:f27ce43dee4f 4970 reg.dur = val;
cparata 0:f27ce43dee4f 4971 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4972 }
cparata 0:f27ce43dee4f 4973 return ret;
cparata 0:f27ce43dee4f 4974 }
cparata 0:f27ce43dee4f 4975
cparata 0:f27ce43dee4f 4976 /**
cparata 0:f27ce43dee4f 4977 * @brief When double tap recognition is enabled,
cparata 0:f27ce43dee4f 4978 * this register expresses the maximum time
cparata 0:f27ce43dee4f 4979 * between two consecutive detected taps to
cparata 0:f27ce43dee4f 4980 * determine a double tap event.
cparata 0:f27ce43dee4f 4981 * The default value of these bits is 0000b which
cparata 0:f27ce43dee4f 4982 * corresponds to 16*ODR_XL time. If the DUR[3:0]
cparata 0:f27ce43dee4f 4983 * bits are set to a different value,
cparata 0:f27ce43dee4f 4984 * 1LSB corresponds to 32*ODR_XL time.[get]
cparata 0:f27ce43dee4f 4985 *
cparata 0:f27ce43dee4f 4986 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 4987 * @param val change the values of dur in reg INT_DUR2
cparata 0:f27ce43dee4f 4988 *
cparata 0:f27ce43dee4f 4989 */
cparata 0:f27ce43dee4f 4990 int32_t lsm6dsox_tap_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 4991 {
cparata 0:f27ce43dee4f 4992 lsm6dsox_int_dur2_t reg;
cparata 0:f27ce43dee4f 4993 int32_t ret;
cparata 0:f27ce43dee4f 4994
cparata 0:f27ce43dee4f 4995 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 4996 *val = reg.dur;
cparata 0:f27ce43dee4f 4997
cparata 0:f27ce43dee4f 4998 return ret;
cparata 0:f27ce43dee4f 4999 }
cparata 0:f27ce43dee4f 5000
cparata 0:f27ce43dee4f 5001 /**
cparata 0:f27ce43dee4f 5002 * @brief Single/double-tap event enable.[set]
cparata 0:f27ce43dee4f 5003 *
cparata 0:f27ce43dee4f 5004 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5005 * @param val change the values of single_double_tap in reg WAKE_UP_THS
cparata 0:f27ce43dee4f 5006 *
cparata 0:f27ce43dee4f 5007 */
cparata 0:f27ce43dee4f 5008 int32_t lsm6dsox_tap_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5009 lsm6dsox_single_double_tap_t val)
cparata 0:f27ce43dee4f 5010 {
cparata 0:f27ce43dee4f 5011 lsm6dsox_wake_up_ths_t reg;
cparata 0:f27ce43dee4f 5012 int32_t ret;
cparata 0:f27ce43dee4f 5013
cparata 0:f27ce43dee4f 5014 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5015 if (ret == 0) {
cparata 0:f27ce43dee4f 5016 reg.single_double_tap = (uint8_t)val;
cparata 0:f27ce43dee4f 5017 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5018 }
cparata 0:f27ce43dee4f 5019 return ret;
cparata 0:f27ce43dee4f 5020 }
cparata 0:f27ce43dee4f 5021
cparata 0:f27ce43dee4f 5022 /**
cparata 0:f27ce43dee4f 5023 * @brief Single/double-tap event enable.[get]
cparata 0:f27ce43dee4f 5024 *
cparata 0:f27ce43dee4f 5025 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5026 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
cparata 0:f27ce43dee4f 5027 *
cparata 0:f27ce43dee4f 5028 */
cparata 0:f27ce43dee4f 5029 int32_t lsm6dsox_tap_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5030 lsm6dsox_single_double_tap_t *val)
cparata 0:f27ce43dee4f 5031 {
cparata 0:f27ce43dee4f 5032 lsm6dsox_wake_up_ths_t reg;
cparata 0:f27ce43dee4f 5033 int32_t ret;
cparata 0:f27ce43dee4f 5034
cparata 0:f27ce43dee4f 5035 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5036
cparata 0:f27ce43dee4f 5037 switch (reg.single_double_tap) {
cparata 0:f27ce43dee4f 5038 case LSM6DSOX_ONLY_SINGLE:
cparata 0:f27ce43dee4f 5039 *val = LSM6DSOX_ONLY_SINGLE;
cparata 0:f27ce43dee4f 5040 break;
cparata 0:f27ce43dee4f 5041 case LSM6DSOX_BOTH_SINGLE_DOUBLE:
cparata 0:f27ce43dee4f 5042 *val = LSM6DSOX_BOTH_SINGLE_DOUBLE;
cparata 0:f27ce43dee4f 5043 break;
cparata 0:f27ce43dee4f 5044 default:
cparata 0:f27ce43dee4f 5045 *val = LSM6DSOX_ONLY_SINGLE;
cparata 0:f27ce43dee4f 5046 break;
cparata 0:f27ce43dee4f 5047 }
cparata 0:f27ce43dee4f 5048
cparata 0:f27ce43dee4f 5049 return ret;
cparata 0:f27ce43dee4f 5050 }
cparata 0:f27ce43dee4f 5051
cparata 0:f27ce43dee4f 5052 /**
cparata 0:f27ce43dee4f 5053 * @}
cparata 0:f27ce43dee4f 5054 *
cparata 0:f27ce43dee4f 5055 */
cparata 0:f27ce43dee4f 5056
cparata 0:f27ce43dee4f 5057 /**
cparata 0:f27ce43dee4f 5058 * @defgroup LSM6DSOX_ Six_position_detection(6D/4D)
cparata 0:f27ce43dee4f 5059 * @brief This section groups all the functions concerning six position
cparata 0:f27ce43dee4f 5060 * detection (6D).
cparata 0:f27ce43dee4f 5061 * @{
cparata 0:f27ce43dee4f 5062 *
cparata 0:f27ce43dee4f 5063 */
cparata 0:f27ce43dee4f 5064
cparata 0:f27ce43dee4f 5065 /**
cparata 0:f27ce43dee4f 5066 * @brief Threshold for 4D/6D function.[set]
cparata 0:f27ce43dee4f 5067 *
cparata 0:f27ce43dee4f 5068 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5069 * @param val change the values of sixd_ths in reg TAP_THS_6D
cparata 0:f27ce43dee4f 5070 *
cparata 0:f27ce43dee4f 5071 */
cparata 0:f27ce43dee4f 5072 int32_t lsm6dsox_6d_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sixd_ths_t val)
cparata 0:f27ce43dee4f 5073 {
cparata 0:f27ce43dee4f 5074 lsm6dsox_tap_ths_6d_t reg;
cparata 0:f27ce43dee4f 5075 int32_t ret;
cparata 0:f27ce43dee4f 5076
cparata 0:f27ce43dee4f 5077 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5078 if (ret == 0) {
cparata 0:f27ce43dee4f 5079 reg.sixd_ths = (uint8_t)val;
cparata 0:f27ce43dee4f 5080 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5081 }
cparata 0:f27ce43dee4f 5082 return ret;
cparata 0:f27ce43dee4f 5083 }
cparata 0:f27ce43dee4f 5084
cparata 0:f27ce43dee4f 5085 /**
cparata 0:f27ce43dee4f 5086 * @brief Threshold for 4D/6D function.[get]
cparata 0:f27ce43dee4f 5087 *
cparata 0:f27ce43dee4f 5088 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5089 * @param val Get the values of sixd_ths in reg TAP_THS_6D
cparata 0:f27ce43dee4f 5090 *
cparata 0:f27ce43dee4f 5091 */
cparata 0:f27ce43dee4f 5092 int32_t lsm6dsox_6d_threshold_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sixd_ths_t *val)
cparata 0:f27ce43dee4f 5093 {
cparata 0:f27ce43dee4f 5094 lsm6dsox_tap_ths_6d_t reg;
cparata 0:f27ce43dee4f 5095 int32_t ret;
cparata 0:f27ce43dee4f 5096
cparata 0:f27ce43dee4f 5097 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5098 switch (reg.sixd_ths) {
cparata 0:f27ce43dee4f 5099 case LSM6DSOX_DEG_80:
cparata 0:f27ce43dee4f 5100 *val = LSM6DSOX_DEG_80;
cparata 0:f27ce43dee4f 5101 break;
cparata 0:f27ce43dee4f 5102 case LSM6DSOX_DEG_70:
cparata 0:f27ce43dee4f 5103 *val = LSM6DSOX_DEG_70;
cparata 0:f27ce43dee4f 5104 break;
cparata 0:f27ce43dee4f 5105 case LSM6DSOX_DEG_60:
cparata 0:f27ce43dee4f 5106 *val = LSM6DSOX_DEG_60;
cparata 0:f27ce43dee4f 5107 break;
cparata 0:f27ce43dee4f 5108 case LSM6DSOX_DEG_50:
cparata 0:f27ce43dee4f 5109 *val = LSM6DSOX_DEG_50;
cparata 0:f27ce43dee4f 5110 break;
cparata 0:f27ce43dee4f 5111 default:
cparata 0:f27ce43dee4f 5112 *val = LSM6DSOX_DEG_80;
cparata 0:f27ce43dee4f 5113 break;
cparata 0:f27ce43dee4f 5114 }
cparata 0:f27ce43dee4f 5115 return ret;
cparata 0:f27ce43dee4f 5116 }
cparata 0:f27ce43dee4f 5117
cparata 0:f27ce43dee4f 5118 /**
cparata 0:f27ce43dee4f 5119 * @brief 4D orientation detection enable.[set]
cparata 0:f27ce43dee4f 5120 *
cparata 0:f27ce43dee4f 5121 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5122 * @param val change the values of d4d_en in reg TAP_THS_6D
cparata 0:f27ce43dee4f 5123 *
cparata 0:f27ce43dee4f 5124 */
cparata 0:f27ce43dee4f 5125 int32_t lsm6dsox_4d_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 5126 {
cparata 0:f27ce43dee4f 5127 lsm6dsox_tap_ths_6d_t reg;
cparata 0:f27ce43dee4f 5128 int32_t ret;
cparata 0:f27ce43dee4f 5129
cparata 0:f27ce43dee4f 5130 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5131 if (ret == 0) {
cparata 0:f27ce43dee4f 5132 reg.d4d_en = val;
cparata 0:f27ce43dee4f 5133 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5134 }
cparata 0:f27ce43dee4f 5135 return ret;
cparata 0:f27ce43dee4f 5136 }
cparata 0:f27ce43dee4f 5137
cparata 0:f27ce43dee4f 5138 /**
cparata 0:f27ce43dee4f 5139 * @brief 4D orientation detection enable.[get]
cparata 0:f27ce43dee4f 5140 *
cparata 0:f27ce43dee4f 5141 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5142 * @param val change the values of d4d_en in reg TAP_THS_6D
cparata 0:f27ce43dee4f 5143 *
cparata 0:f27ce43dee4f 5144 */
cparata 0:f27ce43dee4f 5145 int32_t lsm6dsox_4d_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 5146 {
cparata 0:f27ce43dee4f 5147 lsm6dsox_tap_ths_6d_t reg;
cparata 0:f27ce43dee4f 5148 int32_t ret;
cparata 0:f27ce43dee4f 5149
cparata 0:f27ce43dee4f 5150 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5151 *val = reg.d4d_en;
cparata 0:f27ce43dee4f 5152
cparata 0:f27ce43dee4f 5153 return ret;
cparata 0:f27ce43dee4f 5154 }
cparata 0:f27ce43dee4f 5155
cparata 0:f27ce43dee4f 5156 /**
cparata 0:f27ce43dee4f 5157 * @}
cparata 0:f27ce43dee4f 5158 *
cparata 0:f27ce43dee4f 5159 */
cparata 0:f27ce43dee4f 5160
cparata 0:f27ce43dee4f 5161 /**
cparata 0:f27ce43dee4f 5162 * @defgroup LSM6DSOX_free_fall
cparata 0:f27ce43dee4f 5163 * @brief This section group all the functions concerning the free
cparata 0:f27ce43dee4f 5164 * fall detection.
cparata 0:f27ce43dee4f 5165 * @{
cparata 0:f27ce43dee4f 5166 *
cparata 0:f27ce43dee4f 5167 */
cparata 0:f27ce43dee4f 5168 /**
cparata 0:f27ce43dee4f 5169 * @brief Free fall threshold setting.[set]
cparata 0:f27ce43dee4f 5170 *
cparata 0:f27ce43dee4f 5171 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5172 * @param val change the values of ff_ths in reg FREE_FALL
cparata 0:f27ce43dee4f 5173 *
cparata 0:f27ce43dee4f 5174 */
cparata 0:f27ce43dee4f 5175 int32_t lsm6dsox_ff_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t val)
cparata 0:f27ce43dee4f 5176 {
cparata 0:f27ce43dee4f 5177 lsm6dsox_free_fall_t reg;
cparata 0:f27ce43dee4f 5178 int32_t ret;
cparata 0:f27ce43dee4f 5179
cparata 0:f27ce43dee4f 5180 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5181 if (ret == 0) {
cparata 0:f27ce43dee4f 5182 reg.ff_ths = (uint8_t)val;
cparata 0:f27ce43dee4f 5183 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5184 }
cparata 0:f27ce43dee4f 5185 return ret;
cparata 0:f27ce43dee4f 5186 }
cparata 0:f27ce43dee4f 5187
cparata 0:f27ce43dee4f 5188 /**
cparata 0:f27ce43dee4f 5189 * @brief Free fall threshold setting.[get]
cparata 0:f27ce43dee4f 5190 *
cparata 0:f27ce43dee4f 5191 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5192 * @param val Get the values of ff_ths in reg FREE_FALL
cparata 0:f27ce43dee4f 5193 *
cparata 0:f27ce43dee4f 5194 */
cparata 0:f27ce43dee4f 5195 int32_t lsm6dsox_ff_threshold_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t *val)
cparata 0:f27ce43dee4f 5196 {
cparata 0:f27ce43dee4f 5197 lsm6dsox_free_fall_t reg;
cparata 0:f27ce43dee4f 5198 int32_t ret;
cparata 0:f27ce43dee4f 5199
cparata 0:f27ce43dee4f 5200 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5201 switch (reg.ff_ths) {
cparata 0:f27ce43dee4f 5202 case LSM6DSOX_FF_TSH_156mg:
cparata 0:f27ce43dee4f 5203 *val = LSM6DSOX_FF_TSH_156mg;
cparata 0:f27ce43dee4f 5204 break;
cparata 0:f27ce43dee4f 5205 case LSM6DSOX_FF_TSH_219mg:
cparata 0:f27ce43dee4f 5206 *val = LSM6DSOX_FF_TSH_219mg;
cparata 0:f27ce43dee4f 5207 break;
cparata 0:f27ce43dee4f 5208 case LSM6DSOX_FF_TSH_250mg:
cparata 0:f27ce43dee4f 5209 *val = LSM6DSOX_FF_TSH_250mg;
cparata 0:f27ce43dee4f 5210 break;
cparata 0:f27ce43dee4f 5211 case LSM6DSOX_FF_TSH_312mg:
cparata 0:f27ce43dee4f 5212 *val = LSM6DSOX_FF_TSH_312mg;
cparata 0:f27ce43dee4f 5213 break;
cparata 0:f27ce43dee4f 5214 case LSM6DSOX_FF_TSH_344mg:
cparata 0:f27ce43dee4f 5215 *val = LSM6DSOX_FF_TSH_344mg;
cparata 0:f27ce43dee4f 5216 break;
cparata 0:f27ce43dee4f 5217 case LSM6DSOX_FF_TSH_406mg:
cparata 0:f27ce43dee4f 5218 *val = LSM6DSOX_FF_TSH_406mg;
cparata 0:f27ce43dee4f 5219 break;
cparata 0:f27ce43dee4f 5220 case LSM6DSOX_FF_TSH_469mg:
cparata 0:f27ce43dee4f 5221 *val = LSM6DSOX_FF_TSH_469mg;
cparata 0:f27ce43dee4f 5222 break;
cparata 0:f27ce43dee4f 5223 case LSM6DSOX_FF_TSH_500mg:
cparata 0:f27ce43dee4f 5224 *val = LSM6DSOX_FF_TSH_500mg;
cparata 0:f27ce43dee4f 5225 break;
cparata 0:f27ce43dee4f 5226 default:
cparata 0:f27ce43dee4f 5227 *val = LSM6DSOX_FF_TSH_156mg;
cparata 0:f27ce43dee4f 5228 break;
cparata 0:f27ce43dee4f 5229 }
cparata 0:f27ce43dee4f 5230 return ret;
cparata 0:f27ce43dee4f 5231 }
cparata 0:f27ce43dee4f 5232
cparata 0:f27ce43dee4f 5233 /**
cparata 0:f27ce43dee4f 5234 * @brief Free-fall duration event.[set]
cparata 0:f27ce43dee4f 5235 * 1LSb = 1 / ODR
cparata 0:f27ce43dee4f 5236 *
cparata 0:f27ce43dee4f 5237 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5238 * @param val change the values of ff_dur in reg FREE_FALL
cparata 0:f27ce43dee4f 5239 *
cparata 0:f27ce43dee4f 5240 */
cparata 0:f27ce43dee4f 5241 int32_t lsm6dsox_ff_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 5242 {
cparata 0:f27ce43dee4f 5243 lsm6dsox_wake_up_dur_t wake_up_dur;
cparata 0:f27ce43dee4f 5244 lsm6dsox_free_fall_t free_fall;
cparata 0:f27ce43dee4f 5245 int32_t ret;
cparata 0:f27ce43dee4f 5246
cparata 0:f27ce43dee4f 5247 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
cparata 0:f27ce43dee4f 5248 if (ret == 0) {
cparata 0:f27ce43dee4f 5249 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata 0:f27ce43dee4f 5250 }
cparata 0:f27ce43dee4f 5251 if (ret == 0) {
cparata 0:f27ce43dee4f 5252 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
cparata 0:f27ce43dee4f 5253 free_fall.ff_dur = (uint8_t)val & 0x1FU;
cparata 0:f27ce43dee4f 5254 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR,
cparata 0:f27ce43dee4f 5255 (uint8_t*)&wake_up_dur, 1);
cparata 0:f27ce43dee4f 5256 }
cparata 0:f27ce43dee4f 5257 if (ret == 0) {
cparata 0:f27ce43dee4f 5258 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata 0:f27ce43dee4f 5259 }
cparata 0:f27ce43dee4f 5260 return ret;
cparata 0:f27ce43dee4f 5261 }
cparata 0:f27ce43dee4f 5262
cparata 0:f27ce43dee4f 5263 /**
cparata 0:f27ce43dee4f 5264 * @brief Free-fall duration event.[get]
cparata 0:f27ce43dee4f 5265 * 1LSb = 1 / ODR
cparata 0:f27ce43dee4f 5266 *
cparata 0:f27ce43dee4f 5267 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5268 * @param val change the values of ff_dur in reg FREE_FALL
cparata 0:f27ce43dee4f 5269 *
cparata 0:f27ce43dee4f 5270 */
cparata 0:f27ce43dee4f 5271 int32_t lsm6dsox_ff_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 5272 {
cparata 0:f27ce43dee4f 5273 lsm6dsox_wake_up_dur_t wake_up_dur;
cparata 0:f27ce43dee4f 5274 lsm6dsox_free_fall_t free_fall;
cparata 0:f27ce43dee4f 5275 int32_t ret;
cparata 0:f27ce43dee4f 5276
cparata 0:f27ce43dee4f 5277 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
cparata 0:f27ce43dee4f 5278 if (ret == 0) {
cparata 0:f27ce43dee4f 5279 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata 0:f27ce43dee4f 5280 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
cparata 0:f27ce43dee4f 5281 }
cparata 0:f27ce43dee4f 5282 return ret;
cparata 0:f27ce43dee4f 5283 }
cparata 0:f27ce43dee4f 5284
cparata 0:f27ce43dee4f 5285 /**
cparata 0:f27ce43dee4f 5286 * @}
cparata 0:f27ce43dee4f 5287 *
cparata 0:f27ce43dee4f 5288 */
cparata 0:f27ce43dee4f 5289
cparata 0:f27ce43dee4f 5290 /**
cparata 0:f27ce43dee4f 5291 * @defgroup LSM6DSOX_fifo
cparata 0:f27ce43dee4f 5292 * @brief This section group all the functions concerning the fifo usage
cparata 0:f27ce43dee4f 5293 * @{
cparata 0:f27ce43dee4f 5294 *
cparata 0:f27ce43dee4f 5295 */
cparata 0:f27ce43dee4f 5296
cparata 0:f27ce43dee4f 5297 /**
cparata 0:f27ce43dee4f 5298 * @brief FIFO watermark level selection.[set]
cparata 0:f27ce43dee4f 5299 *
cparata 0:f27ce43dee4f 5300 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5301 * @param val change the values of wtm in reg FIFO_CTRL1
cparata 0:f27ce43dee4f 5302 *
cparata 0:f27ce43dee4f 5303 */
cparata 0:f27ce43dee4f 5304 int32_t lsm6dsox_fifo_watermark_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata 0:f27ce43dee4f 5305 {
cparata 0:f27ce43dee4f 5306 lsm6dsox_fifo_ctrl1_t fifo_ctrl1;
cparata 0:f27ce43dee4f 5307 lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
cparata 0:f27ce43dee4f 5308 int32_t ret;
cparata 0:f27ce43dee4f 5309
cparata 0:f27ce43dee4f 5310 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata 0:f27ce43dee4f 5311 if (ret == 0) {
cparata 0:f27ce43dee4f 5312 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
cparata 0:f27ce43dee4f 5313 fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
cparata 0:f27ce43dee4f 5314 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
cparata 0:f27ce43dee4f 5315 }
cparata 0:f27ce43dee4f 5316 if (ret == 0) {
cparata 0:f27ce43dee4f 5317 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata 0:f27ce43dee4f 5318 }
cparata 0:f27ce43dee4f 5319 return ret;
cparata 0:f27ce43dee4f 5320 }
cparata 0:f27ce43dee4f 5321
cparata 0:f27ce43dee4f 5322 /**
cparata 0:f27ce43dee4f 5323 * @brief FIFO watermark level selection.[get]
cparata 0:f27ce43dee4f 5324 *
cparata 0:f27ce43dee4f 5325 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5326 * @param val change the values of wtm in reg FIFO_CTRL1
cparata 0:f27ce43dee4f 5327 *
cparata 0:f27ce43dee4f 5328 */
cparata 0:f27ce43dee4f 5329 int32_t lsm6dsox_fifo_watermark_get(lsm6dsox_ctx_t *ctx, uint16_t *val)
cparata 0:f27ce43dee4f 5330 {
cparata 0:f27ce43dee4f 5331 lsm6dsox_fifo_ctrl1_t fifo_ctrl1;
cparata 0:f27ce43dee4f 5332 lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
cparata 0:f27ce43dee4f 5333 int32_t ret;
cparata 0:f27ce43dee4f 5334
cparata 0:f27ce43dee4f 5335 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
cparata 0:f27ce43dee4f 5336 if (ret == 0) {
cparata 0:f27ce43dee4f 5337 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata 0:f27ce43dee4f 5338 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
cparata 0:f27ce43dee4f 5339 }
cparata 0:f27ce43dee4f 5340 return ret;
cparata 0:f27ce43dee4f 5341 }
cparata 0:f27ce43dee4f 5342
cparata 0:f27ce43dee4f 5343 /**
cparata 0:f27ce43dee4f 5344 * @brief FIFO compression feature initialization request [set].
cparata 0:f27ce43dee4f 5345 *
cparata 0:f27ce43dee4f 5346 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5347 * @param val change the values of FIFO_COMPR_INIT in
cparata 0:f27ce43dee4f 5348 * reg EMB_FUNC_INIT_B
cparata 0:f27ce43dee4f 5349 *
cparata 0:f27ce43dee4f 5350 */
cparata 0:f27ce43dee4f 5351 int32_t lsm6dsox_compression_algo_init_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 5352 {
cparata 0:f27ce43dee4f 5353 lsm6dsox_emb_func_init_b_t reg;
cparata 0:f27ce43dee4f 5354 int32_t ret;
cparata 0:f27ce43dee4f 5355
cparata 0:f27ce43dee4f 5356 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 5357 if (ret == 0) {
cparata 0:f27ce43dee4f 5358 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5359 }
cparata 0:f27ce43dee4f 5360 if (ret == 0) {
cparata 0:f27ce43dee4f 5361 reg.fifo_compr_init = val;
cparata 0:f27ce43dee4f 5362 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5363 }
cparata 0:f27ce43dee4f 5364 if (ret == 0) {
cparata 0:f27ce43dee4f 5365 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 5366 }
cparata 0:f27ce43dee4f 5367
cparata 0:f27ce43dee4f 5368 return ret;
cparata 0:f27ce43dee4f 5369 }
cparata 0:f27ce43dee4f 5370
cparata 0:f27ce43dee4f 5371 /**
cparata 0:f27ce43dee4f 5372 * @brief FIFO compression feature initialization request [get].
cparata 0:f27ce43dee4f 5373 *
cparata 0:f27ce43dee4f 5374 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5375 * @param val change the values of FIFO_COMPR_INIT in
cparata 0:f27ce43dee4f 5376 * reg EMB_FUNC_INIT_B
cparata 0:f27ce43dee4f 5377 *
cparata 0:f27ce43dee4f 5378 */
cparata 0:f27ce43dee4f 5379 int32_t lsm6dsox_compression_algo_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 5380 {
cparata 0:f27ce43dee4f 5381 lsm6dsox_emb_func_init_b_t reg;
cparata 0:f27ce43dee4f 5382 int32_t ret;
cparata 0:f27ce43dee4f 5383
cparata 0:f27ce43dee4f 5384 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 5385 if (ret == 0) {
cparata 0:f27ce43dee4f 5386 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5387 }
cparata 0:f27ce43dee4f 5388 if (ret == 0) {
cparata 0:f27ce43dee4f 5389 *val = reg.fifo_compr_init;
cparata 0:f27ce43dee4f 5390 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 5391 }
cparata 0:f27ce43dee4f 5392
cparata 0:f27ce43dee4f 5393 return ret;
cparata 0:f27ce43dee4f 5394 }
cparata 0:f27ce43dee4f 5395
cparata 0:f27ce43dee4f 5396 /**
cparata 0:f27ce43dee4f 5397 * @brief Enable and configure compression algo.[set]
cparata 0:f27ce43dee4f 5398 *
cparata 0:f27ce43dee4f 5399 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5400 * @param val change the values of uncoptr_rate in
cparata 0:f27ce43dee4f 5401 * reg FIFO_CTRL2
cparata 0:f27ce43dee4f 5402 *
cparata 0:f27ce43dee4f 5403 */
cparata 0:f27ce43dee4f 5404 int32_t lsm6dsox_compression_algo_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5405 lsm6dsox_uncoptr_rate_t val)
cparata 0:f27ce43dee4f 5406 {
cparata 0:f27ce43dee4f 5407 lsm6dsox_emb_func_en_b_t emb_func_en_b;
cparata 0:f27ce43dee4f 5408 lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
cparata 0:f27ce43dee4f 5409 int32_t ret;
cparata 0:f27ce43dee4f 5410
cparata 0:f27ce43dee4f 5411 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 5412 if (ret == 0) {
cparata 0:f27ce43dee4f 5413 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata 0:f27ce43dee4f 5414 (uint8_t*)&emb_func_en_b, 1);
cparata 0:f27ce43dee4f 5415 }
cparata 0:f27ce43dee4f 5416 if (ret == 0) {
cparata 0:f27ce43dee4f 5417 emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
cparata 0:f27ce43dee4f 5418 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata 0:f27ce43dee4f 5419 (uint8_t*)&emb_func_en_b, 1);
cparata 0:f27ce43dee4f 5420 }
cparata 0:f27ce43dee4f 5421 if (ret == 0) {
cparata 0:f27ce43dee4f 5422 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 5423 }
cparata 0:f27ce43dee4f 5424 if (ret == 0) {
cparata 0:f27ce43dee4f 5425
cparata 0:f27ce43dee4f 5426 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2,
cparata 0:f27ce43dee4f 5427 (uint8_t*)&fifo_ctrl2, 1);
cparata 0:f27ce43dee4f 5428 }
cparata 0:f27ce43dee4f 5429 if (ret == 0) {
cparata 0:f27ce43dee4f 5430 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
cparata 0:f27ce43dee4f 5431 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
cparata 0:f27ce43dee4f 5432 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2,
cparata 0:f27ce43dee4f 5433 (uint8_t*)&fifo_ctrl2, 1);
cparata 0:f27ce43dee4f 5434 }
cparata 0:f27ce43dee4f 5435 return ret;
cparata 0:f27ce43dee4f 5436 }
cparata 0:f27ce43dee4f 5437
cparata 0:f27ce43dee4f 5438 /**
cparata 0:f27ce43dee4f 5439 * @brief Enable and configure compression algo.[get]
cparata 0:f27ce43dee4f 5440 *
cparata 0:f27ce43dee4f 5441 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5442 * @param val Get the values of uncoptr_rate in
cparata 0:f27ce43dee4f 5443 * reg FIFO_CTRL2
cparata 0:f27ce43dee4f 5444 *
cparata 0:f27ce43dee4f 5445 */
cparata 0:f27ce43dee4f 5446 int32_t lsm6dsox_compression_algo_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5447 lsm6dsox_uncoptr_rate_t *val)
cparata 0:f27ce43dee4f 5448 {
cparata 0:f27ce43dee4f 5449 lsm6dsox_fifo_ctrl2_t reg;
cparata 0:f27ce43dee4f 5450 int32_t ret;
cparata 0:f27ce43dee4f 5451
cparata 0:f27ce43dee4f 5452 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5453
cparata 0:f27ce43dee4f 5454 switch ((reg.fifo_compr_rt_en<<2) | reg.uncoptr_rate) {
cparata 0:f27ce43dee4f 5455 case LSM6DSOX_CMP_DISABLE:
cparata 0:f27ce43dee4f 5456 *val = LSM6DSOX_CMP_DISABLE;
cparata 0:f27ce43dee4f 5457 break;
cparata 0:f27ce43dee4f 5458 case LSM6DSOX_CMP_ALWAYS:
cparata 0:f27ce43dee4f 5459 *val = LSM6DSOX_CMP_ALWAYS;
cparata 0:f27ce43dee4f 5460 break;
cparata 0:f27ce43dee4f 5461 case LSM6DSOX_CMP_8_TO_1:
cparata 0:f27ce43dee4f 5462 *val = LSM6DSOX_CMP_8_TO_1;
cparata 0:f27ce43dee4f 5463 break;
cparata 0:f27ce43dee4f 5464 case LSM6DSOX_CMP_16_TO_1:
cparata 0:f27ce43dee4f 5465 *val = LSM6DSOX_CMP_16_TO_1;
cparata 0:f27ce43dee4f 5466 break;
cparata 0:f27ce43dee4f 5467 case LSM6DSOX_CMP_32_TO_1:
cparata 0:f27ce43dee4f 5468 *val = LSM6DSOX_CMP_32_TO_1;
cparata 0:f27ce43dee4f 5469 break;
cparata 0:f27ce43dee4f 5470 default:
cparata 0:f27ce43dee4f 5471 *val = LSM6DSOX_CMP_DISABLE;
cparata 0:f27ce43dee4f 5472 break;
cparata 0:f27ce43dee4f 5473 }
cparata 0:f27ce43dee4f 5474 return ret;
cparata 0:f27ce43dee4f 5475 }
cparata 0:f27ce43dee4f 5476
cparata 0:f27ce43dee4f 5477 /**
cparata 0:f27ce43dee4f 5478 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
cparata 0:f27ce43dee4f 5479 *
cparata 0:f27ce43dee4f 5480 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5481 * @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata 0:f27ce43dee4f 5482 *
cparata 0:f27ce43dee4f 5483 */
cparata 0:f27ce43dee4f 5484 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5485 uint8_t val)
cparata 0:f27ce43dee4f 5486 {
cparata 0:f27ce43dee4f 5487 lsm6dsox_fifo_ctrl2_t reg;
cparata 0:f27ce43dee4f 5488 int32_t ret;
cparata 0:f27ce43dee4f 5489
cparata 0:f27ce43dee4f 5490 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5491 if (ret == 0) {
cparata 0:f27ce43dee4f 5492 reg.odrchg_en = val;
cparata 0:f27ce43dee4f 5493 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5494 }
cparata 0:f27ce43dee4f 5495 return ret;
cparata 0:f27ce43dee4f 5496 }
cparata 0:f27ce43dee4f 5497
cparata 0:f27ce43dee4f 5498 /**
cparata 0:f27ce43dee4f 5499 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
cparata 0:f27ce43dee4f 5500 *
cparata 0:f27ce43dee4f 5501 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5502 * @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata 0:f27ce43dee4f 5503 *
cparata 0:f27ce43dee4f 5504 */
cparata 0:f27ce43dee4f 5505 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5506 uint8_t *val)
cparata 0:f27ce43dee4f 5507 {
cparata 0:f27ce43dee4f 5508 lsm6dsox_fifo_ctrl2_t reg;
cparata 0:f27ce43dee4f 5509 int32_t ret;
cparata 0:f27ce43dee4f 5510
cparata 0:f27ce43dee4f 5511 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5512 *val = reg.odrchg_en;
cparata 0:f27ce43dee4f 5513
cparata 0:f27ce43dee4f 5514 return ret;
cparata 0:f27ce43dee4f 5515 }
cparata 0:f27ce43dee4f 5516
cparata 0:f27ce43dee4f 5517 /**
cparata 0:f27ce43dee4f 5518 * @brief Enables/Disables compression algorithm runtime.[set]
cparata 0:f27ce43dee4f 5519 *
cparata 0:f27ce43dee4f 5520 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5521 * @param val change the values of fifo_compr_rt_en in
cparata 0:f27ce43dee4f 5522 * reg FIFO_CTRL2
cparata 0:f27ce43dee4f 5523 *
cparata 0:f27ce43dee4f 5524 */
cparata 0:f27ce43dee4f 5525 int32_t lsm6dsox_compression_algo_real_time_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5526 uint8_t val)
cparata 0:f27ce43dee4f 5527 {
cparata 0:f27ce43dee4f 5528 lsm6dsox_fifo_ctrl2_t reg;
cparata 0:f27ce43dee4f 5529 int32_t ret;
cparata 0:f27ce43dee4f 5530
cparata 0:f27ce43dee4f 5531 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5532 if (ret == 0) {
cparata 0:f27ce43dee4f 5533 reg.fifo_compr_rt_en = val;
cparata 0:f27ce43dee4f 5534 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5535 }
cparata 0:f27ce43dee4f 5536 return ret;
cparata 0:f27ce43dee4f 5537 }
cparata 0:f27ce43dee4f 5538
cparata 0:f27ce43dee4f 5539 /**
cparata 0:f27ce43dee4f 5540 * @brief Enables/Disables compression algorithm runtime. [get]
cparata 0:f27ce43dee4f 5541 *
cparata 0:f27ce43dee4f 5542 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5543 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
cparata 0:f27ce43dee4f 5544 *
cparata 0:f27ce43dee4f 5545 */
cparata 0:f27ce43dee4f 5546 int32_t lsm6dsox_compression_algo_real_time_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5547 uint8_t *val)
cparata 0:f27ce43dee4f 5548 {
cparata 0:f27ce43dee4f 5549 lsm6dsox_fifo_ctrl2_t reg;
cparata 0:f27ce43dee4f 5550 int32_t ret;
cparata 0:f27ce43dee4f 5551
cparata 0:f27ce43dee4f 5552 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5553 *val = reg.fifo_compr_rt_en;
cparata 0:f27ce43dee4f 5554
cparata 0:f27ce43dee4f 5555 return ret;
cparata 0:f27ce43dee4f 5556 }
cparata 0:f27ce43dee4f 5557
cparata 0:f27ce43dee4f 5558 /**
cparata 0:f27ce43dee4f 5559 * @brief Sensing chain FIFO stop values memorization at
cparata 0:f27ce43dee4f 5560 * threshold level.[set]
cparata 0:f27ce43dee4f 5561 *
cparata 0:f27ce43dee4f 5562 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5563 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata 0:f27ce43dee4f 5564 *
cparata 0:f27ce43dee4f 5565 */
cparata 0:f27ce43dee4f 5566 int32_t lsm6dsox_fifo_stop_on_wtm_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 5567 {
cparata 0:f27ce43dee4f 5568 lsm6dsox_fifo_ctrl2_t reg;
cparata 0:f27ce43dee4f 5569 int32_t ret;
cparata 0:f27ce43dee4f 5570
cparata 0:f27ce43dee4f 5571 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5572 if (ret == 0) {
cparata 0:f27ce43dee4f 5573 reg.stop_on_wtm = val;
cparata 0:f27ce43dee4f 5574 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5575 }
cparata 0:f27ce43dee4f 5576 return ret;
cparata 0:f27ce43dee4f 5577 }
cparata 0:f27ce43dee4f 5578
cparata 0:f27ce43dee4f 5579 /**
cparata 0:f27ce43dee4f 5580 * @brief Sensing chain FIFO stop values memorization at
cparata 0:f27ce43dee4f 5581 * threshold level.[get]
cparata 0:f27ce43dee4f 5582 *
cparata 0:f27ce43dee4f 5583 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5584 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata 0:f27ce43dee4f 5585 *
cparata 0:f27ce43dee4f 5586 */
cparata 0:f27ce43dee4f 5587 int32_t lsm6dsox_fifo_stop_on_wtm_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 5588 {
cparata 0:f27ce43dee4f 5589 lsm6dsox_fifo_ctrl2_t reg;
cparata 0:f27ce43dee4f 5590 int32_t ret;
cparata 0:f27ce43dee4f 5591
cparata 0:f27ce43dee4f 5592 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5593 *val = reg.stop_on_wtm;
cparata 0:f27ce43dee4f 5594
cparata 0:f27ce43dee4f 5595 return ret;
cparata 0:f27ce43dee4f 5596 }
cparata 0:f27ce43dee4f 5597
cparata 0:f27ce43dee4f 5598 /**
cparata 0:f27ce43dee4f 5599 * @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata 0:f27ce43dee4f 5600 * for accelerometer data.[set]
cparata 0:f27ce43dee4f 5601 *
cparata 0:f27ce43dee4f 5602 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5603 * @param val change the values of bdr_xl in reg FIFO_CTRL3
cparata 0:f27ce43dee4f 5604 *
cparata 0:f27ce43dee4f 5605 */
cparata 0:f27ce43dee4f 5606 int32_t lsm6dsox_fifo_xl_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t val)
cparata 0:f27ce43dee4f 5607 {
cparata 0:f27ce43dee4f 5608 lsm6dsox_fifo_ctrl3_t reg;
cparata 0:f27ce43dee4f 5609 int32_t ret;
cparata 0:f27ce43dee4f 5610
cparata 0:f27ce43dee4f 5611 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5612 if (ret == 0) {
cparata 0:f27ce43dee4f 5613 reg.bdr_xl = (uint8_t)val;
cparata 0:f27ce43dee4f 5614 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5615 }
cparata 0:f27ce43dee4f 5616 return ret;
cparata 0:f27ce43dee4f 5617 }
cparata 0:f27ce43dee4f 5618
cparata 0:f27ce43dee4f 5619 /**
cparata 0:f27ce43dee4f 5620 * @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata 0:f27ce43dee4f 5621 * for accelerometer data.[get]
cparata 0:f27ce43dee4f 5622 *
cparata 0:f27ce43dee4f 5623 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5624 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
cparata 0:f27ce43dee4f 5625 *
cparata 0:f27ce43dee4f 5626 */
cparata 0:f27ce43dee4f 5627 int32_t lsm6dsox_fifo_xl_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t *val)
cparata 0:f27ce43dee4f 5628 {
cparata 0:f27ce43dee4f 5629 lsm6dsox_fifo_ctrl3_t reg;
cparata 0:f27ce43dee4f 5630 int32_t ret;
cparata 0:f27ce43dee4f 5631
cparata 0:f27ce43dee4f 5632 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5633 switch (reg.bdr_xl) {
cparata 0:f27ce43dee4f 5634 case LSM6DSOX_XL_NOT_BATCHED:
cparata 0:f27ce43dee4f 5635 *val = LSM6DSOX_XL_NOT_BATCHED;
cparata 0:f27ce43dee4f 5636 break;
cparata 0:f27ce43dee4f 5637 case LSM6DSOX_XL_BATCHED_AT_12Hz5:
cparata 0:f27ce43dee4f 5638 *val = LSM6DSOX_XL_BATCHED_AT_12Hz5;
cparata 0:f27ce43dee4f 5639 break;
cparata 0:f27ce43dee4f 5640 case LSM6DSOX_XL_BATCHED_AT_26Hz:
cparata 0:f27ce43dee4f 5641 *val = LSM6DSOX_XL_BATCHED_AT_26Hz;
cparata 0:f27ce43dee4f 5642 break;
cparata 0:f27ce43dee4f 5643 case LSM6DSOX_XL_BATCHED_AT_52Hz:
cparata 0:f27ce43dee4f 5644 *val = LSM6DSOX_XL_BATCHED_AT_52Hz;
cparata 0:f27ce43dee4f 5645 break;
cparata 0:f27ce43dee4f 5646 case LSM6DSOX_XL_BATCHED_AT_104Hz:
cparata 0:f27ce43dee4f 5647 *val = LSM6DSOX_XL_BATCHED_AT_104Hz;
cparata 0:f27ce43dee4f 5648 break;
cparata 0:f27ce43dee4f 5649 case LSM6DSOX_XL_BATCHED_AT_208Hz:
cparata 0:f27ce43dee4f 5650 *val = LSM6DSOX_XL_BATCHED_AT_208Hz;
cparata 0:f27ce43dee4f 5651 break;
cparata 0:f27ce43dee4f 5652 case LSM6DSOX_XL_BATCHED_AT_417Hz:
cparata 0:f27ce43dee4f 5653 *val = LSM6DSOX_XL_BATCHED_AT_417Hz;
cparata 0:f27ce43dee4f 5654 break;
cparata 0:f27ce43dee4f 5655 case LSM6DSOX_XL_BATCHED_AT_833Hz:
cparata 0:f27ce43dee4f 5656 *val = LSM6DSOX_XL_BATCHED_AT_833Hz;
cparata 0:f27ce43dee4f 5657 break;
cparata 0:f27ce43dee4f 5658 case LSM6DSOX_XL_BATCHED_AT_1667Hz:
cparata 0:f27ce43dee4f 5659 *val = LSM6DSOX_XL_BATCHED_AT_1667Hz;
cparata 0:f27ce43dee4f 5660 break;
cparata 0:f27ce43dee4f 5661 case LSM6DSOX_XL_BATCHED_AT_3333Hz:
cparata 0:f27ce43dee4f 5662 *val = LSM6DSOX_XL_BATCHED_AT_3333Hz;
cparata 0:f27ce43dee4f 5663 break;
cparata 0:f27ce43dee4f 5664 case LSM6DSOX_XL_BATCHED_AT_6667Hz:
cparata 0:f27ce43dee4f 5665 *val = LSM6DSOX_XL_BATCHED_AT_6667Hz;
cparata 0:f27ce43dee4f 5666 break;
cparata 0:f27ce43dee4f 5667 case LSM6DSOX_XL_BATCHED_AT_6Hz5:
cparata 0:f27ce43dee4f 5668 *val = LSM6DSOX_XL_BATCHED_AT_6Hz5;
cparata 0:f27ce43dee4f 5669 break;
cparata 0:f27ce43dee4f 5670 default:
cparata 0:f27ce43dee4f 5671 *val = LSM6DSOX_XL_NOT_BATCHED;
cparata 0:f27ce43dee4f 5672 break;
cparata 0:f27ce43dee4f 5673 }
cparata 0:f27ce43dee4f 5674
cparata 0:f27ce43dee4f 5675 return ret;
cparata 0:f27ce43dee4f 5676 }
cparata 0:f27ce43dee4f 5677
cparata 0:f27ce43dee4f 5678 /**
cparata 0:f27ce43dee4f 5679 * @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata 0:f27ce43dee4f 5680 * for gyroscope data.[set]
cparata 0:f27ce43dee4f 5681 *
cparata 0:f27ce43dee4f 5682 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5683 * @param val change the values of bdr_gy in reg FIFO_CTRL3
cparata 0:f27ce43dee4f 5684 *
cparata 0:f27ce43dee4f 5685 */
cparata 0:f27ce43dee4f 5686 int32_t lsm6dsox_fifo_gy_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t val)
cparata 0:f27ce43dee4f 5687 {
cparata 0:f27ce43dee4f 5688 lsm6dsox_fifo_ctrl3_t reg;
cparata 0:f27ce43dee4f 5689 int32_t ret;
cparata 0:f27ce43dee4f 5690
cparata 0:f27ce43dee4f 5691 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5692 if (ret == 0) {
cparata 0:f27ce43dee4f 5693 reg.bdr_gy = (uint8_t)val;
cparata 0:f27ce43dee4f 5694 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5695 }
cparata 0:f27ce43dee4f 5696 return ret;
cparata 0:f27ce43dee4f 5697 }
cparata 0:f27ce43dee4f 5698
cparata 0:f27ce43dee4f 5699 /**
cparata 0:f27ce43dee4f 5700 * @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata 0:f27ce43dee4f 5701 * for gyroscope data.[get]
cparata 0:f27ce43dee4f 5702 *
cparata 0:f27ce43dee4f 5703 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5704 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
cparata 0:f27ce43dee4f 5705 *
cparata 0:f27ce43dee4f 5706 */
cparata 0:f27ce43dee4f 5707 int32_t lsm6dsox_fifo_gy_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t *val)
cparata 0:f27ce43dee4f 5708 {
cparata 0:f27ce43dee4f 5709 lsm6dsox_fifo_ctrl3_t reg;
cparata 0:f27ce43dee4f 5710 int32_t ret;
cparata 0:f27ce43dee4f 5711
cparata 0:f27ce43dee4f 5712 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5713 switch (reg.bdr_gy) {
cparata 0:f27ce43dee4f 5714 case LSM6DSOX_GY_NOT_BATCHED:
cparata 0:f27ce43dee4f 5715 *val = LSM6DSOX_GY_NOT_BATCHED;
cparata 0:f27ce43dee4f 5716 break;
cparata 0:f27ce43dee4f 5717 case LSM6DSOX_GY_BATCHED_AT_12Hz5:
cparata 0:f27ce43dee4f 5718 *val = LSM6DSOX_GY_BATCHED_AT_12Hz5;
cparata 0:f27ce43dee4f 5719 break;
cparata 0:f27ce43dee4f 5720 case LSM6DSOX_GY_BATCHED_AT_26Hz:
cparata 0:f27ce43dee4f 5721 *val = LSM6DSOX_GY_BATCHED_AT_26Hz;
cparata 0:f27ce43dee4f 5722 break;
cparata 0:f27ce43dee4f 5723 case LSM6DSOX_GY_BATCHED_AT_52Hz:
cparata 0:f27ce43dee4f 5724 *val = LSM6DSOX_GY_BATCHED_AT_52Hz;
cparata 0:f27ce43dee4f 5725 break;
cparata 0:f27ce43dee4f 5726 case LSM6DSOX_GY_BATCHED_AT_104Hz:
cparata 0:f27ce43dee4f 5727 *val = LSM6DSOX_GY_BATCHED_AT_104Hz;
cparata 0:f27ce43dee4f 5728 break;
cparata 0:f27ce43dee4f 5729 case LSM6DSOX_GY_BATCHED_AT_208Hz:
cparata 0:f27ce43dee4f 5730 *val = LSM6DSOX_GY_BATCHED_AT_208Hz;
cparata 0:f27ce43dee4f 5731 break;
cparata 0:f27ce43dee4f 5732 case LSM6DSOX_GY_BATCHED_AT_417Hz:
cparata 0:f27ce43dee4f 5733 *val = LSM6DSOX_GY_BATCHED_AT_417Hz;
cparata 0:f27ce43dee4f 5734 break;
cparata 0:f27ce43dee4f 5735 case LSM6DSOX_GY_BATCHED_AT_833Hz:
cparata 0:f27ce43dee4f 5736 *val = LSM6DSOX_GY_BATCHED_AT_833Hz;
cparata 0:f27ce43dee4f 5737 break;
cparata 0:f27ce43dee4f 5738 case LSM6DSOX_GY_BATCHED_AT_1667Hz:
cparata 0:f27ce43dee4f 5739 *val = LSM6DSOX_GY_BATCHED_AT_1667Hz;
cparata 0:f27ce43dee4f 5740 break;
cparata 0:f27ce43dee4f 5741 case LSM6DSOX_GY_BATCHED_AT_3333Hz:
cparata 0:f27ce43dee4f 5742 *val = LSM6DSOX_GY_BATCHED_AT_3333Hz;
cparata 0:f27ce43dee4f 5743 break;
cparata 0:f27ce43dee4f 5744 case LSM6DSOX_GY_BATCHED_AT_6667Hz:
cparata 0:f27ce43dee4f 5745 *val = LSM6DSOX_GY_BATCHED_AT_6667Hz;
cparata 0:f27ce43dee4f 5746 break;
cparata 0:f27ce43dee4f 5747 case LSM6DSOX_GY_BATCHED_AT_6Hz5:
cparata 0:f27ce43dee4f 5748 *val = LSM6DSOX_GY_BATCHED_AT_6Hz5;
cparata 0:f27ce43dee4f 5749 break;
cparata 0:f27ce43dee4f 5750 default:
cparata 0:f27ce43dee4f 5751 *val = LSM6DSOX_GY_NOT_BATCHED;
cparata 0:f27ce43dee4f 5752 break;
cparata 0:f27ce43dee4f 5753 }
cparata 0:f27ce43dee4f 5754 return ret;
cparata 0:f27ce43dee4f 5755 }
cparata 0:f27ce43dee4f 5756
cparata 0:f27ce43dee4f 5757 /**
cparata 0:f27ce43dee4f 5758 * @brief FIFO mode selection.[set]
cparata 0:f27ce43dee4f 5759 *
cparata 0:f27ce43dee4f 5760 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5761 * @param val change the values of fifo_mode in reg FIFO_CTRL4
cparata 0:f27ce43dee4f 5762 *
cparata 0:f27ce43dee4f 5763 */
cparata 0:f27ce43dee4f 5764 int32_t lsm6dsox_fifo_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t val)
cparata 0:f27ce43dee4f 5765 {
cparata 0:f27ce43dee4f 5766 lsm6dsox_fifo_ctrl4_t reg;
cparata 0:f27ce43dee4f 5767 int32_t ret;
cparata 0:f27ce43dee4f 5768
cparata 0:f27ce43dee4f 5769 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5770 if (ret == 0) {
cparata 0:f27ce43dee4f 5771 reg.fifo_mode = (uint8_t)val;
cparata 0:f27ce43dee4f 5772 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5773 }
cparata 0:f27ce43dee4f 5774 return ret;
cparata 0:f27ce43dee4f 5775 }
cparata 0:f27ce43dee4f 5776
cparata 0:f27ce43dee4f 5777 /**
cparata 0:f27ce43dee4f 5778 * @brief FIFO mode selection.[get]
cparata 0:f27ce43dee4f 5779 *
cparata 0:f27ce43dee4f 5780 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5781 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
cparata 0:f27ce43dee4f 5782 *
cparata 0:f27ce43dee4f 5783 */
cparata 0:f27ce43dee4f 5784 int32_t lsm6dsox_fifo_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t *val)
cparata 0:f27ce43dee4f 5785 {
cparata 0:f27ce43dee4f 5786 lsm6dsox_fifo_ctrl4_t reg;
cparata 0:f27ce43dee4f 5787 int32_t ret;
cparata 0:f27ce43dee4f 5788
cparata 0:f27ce43dee4f 5789 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5790
cparata 0:f27ce43dee4f 5791 switch (reg.fifo_mode) {
cparata 0:f27ce43dee4f 5792 case LSM6DSOX_BYPASS_MODE:
cparata 0:f27ce43dee4f 5793 *val = LSM6DSOX_BYPASS_MODE;
cparata 0:f27ce43dee4f 5794 break;
cparata 0:f27ce43dee4f 5795 case LSM6DSOX_FIFO_MODE:
cparata 0:f27ce43dee4f 5796 *val = LSM6DSOX_FIFO_MODE;
cparata 0:f27ce43dee4f 5797 break;
cparata 0:f27ce43dee4f 5798 case LSM6DSOX_STREAM_TO_FIFO_MODE:
cparata 0:f27ce43dee4f 5799 *val = LSM6DSOX_STREAM_TO_FIFO_MODE;
cparata 0:f27ce43dee4f 5800 break;
cparata 0:f27ce43dee4f 5801 case LSM6DSOX_BYPASS_TO_STREAM_MODE:
cparata 0:f27ce43dee4f 5802 *val = LSM6DSOX_BYPASS_TO_STREAM_MODE;
cparata 0:f27ce43dee4f 5803 break;
cparata 0:f27ce43dee4f 5804 case LSM6DSOX_STREAM_MODE:
cparata 0:f27ce43dee4f 5805 *val = LSM6DSOX_STREAM_MODE;
cparata 0:f27ce43dee4f 5806 break;
cparata 0:f27ce43dee4f 5807 case LSM6DSOX_BYPASS_TO_FIFO_MODE:
cparata 0:f27ce43dee4f 5808 *val = LSM6DSOX_BYPASS_TO_FIFO_MODE;
cparata 0:f27ce43dee4f 5809 break;
cparata 0:f27ce43dee4f 5810 default:
cparata 0:f27ce43dee4f 5811 *val = LSM6DSOX_BYPASS_MODE;
cparata 0:f27ce43dee4f 5812 break;
cparata 0:f27ce43dee4f 5813 }
cparata 0:f27ce43dee4f 5814 return ret;
cparata 0:f27ce43dee4f 5815 }
cparata 0:f27ce43dee4f 5816
cparata 0:f27ce43dee4f 5817 /**
cparata 0:f27ce43dee4f 5818 * @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata 0:f27ce43dee4f 5819 * for temperature data.[set]
cparata 0:f27ce43dee4f 5820 *
cparata 0:f27ce43dee4f 5821 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5822 * @param val change the values of odr_t_batch in reg FIFO_CTRL4
cparata 0:f27ce43dee4f 5823 *
cparata 0:f27ce43dee4f 5824 */
cparata 0:f27ce43dee4f 5825 int32_t lsm6dsox_fifo_temp_batch_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5826 lsm6dsox_odr_t_batch_t val)
cparata 0:f27ce43dee4f 5827 {
cparata 0:f27ce43dee4f 5828 lsm6dsox_fifo_ctrl4_t reg;
cparata 0:f27ce43dee4f 5829 int32_t ret;
cparata 0:f27ce43dee4f 5830
cparata 0:f27ce43dee4f 5831 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5832 if (ret == 0) {
cparata 0:f27ce43dee4f 5833 reg.odr_t_batch = (uint8_t)val;
cparata 0:f27ce43dee4f 5834 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5835 }
cparata 0:f27ce43dee4f 5836 return ret;
cparata 0:f27ce43dee4f 5837 }
cparata 0:f27ce43dee4f 5838
cparata 0:f27ce43dee4f 5839 /**
cparata 0:f27ce43dee4f 5840 * @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata 0:f27ce43dee4f 5841 * for temperature data.[get]
cparata 0:f27ce43dee4f 5842 *
cparata 0:f27ce43dee4f 5843 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5844 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
cparata 0:f27ce43dee4f 5845 *
cparata 0:f27ce43dee4f 5846 */
cparata 0:f27ce43dee4f 5847 int32_t lsm6dsox_fifo_temp_batch_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5848 lsm6dsox_odr_t_batch_t *val)
cparata 0:f27ce43dee4f 5849 {
cparata 0:f27ce43dee4f 5850 lsm6dsox_fifo_ctrl4_t reg;
cparata 0:f27ce43dee4f 5851 int32_t ret;
cparata 0:f27ce43dee4f 5852
cparata 0:f27ce43dee4f 5853 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5854
cparata 0:f27ce43dee4f 5855 switch (reg.odr_t_batch) {
cparata 0:f27ce43dee4f 5856 case LSM6DSOX_TEMP_NOT_BATCHED:
cparata 0:f27ce43dee4f 5857 *val = LSM6DSOX_TEMP_NOT_BATCHED;
cparata 0:f27ce43dee4f 5858 break;
cparata 0:f27ce43dee4f 5859 case LSM6DSOX_TEMP_BATCHED_AT_1Hz6:
cparata 0:f27ce43dee4f 5860 *val = LSM6DSOX_TEMP_BATCHED_AT_1Hz6;
cparata 0:f27ce43dee4f 5861 break;
cparata 0:f27ce43dee4f 5862 case LSM6DSOX_TEMP_BATCHED_AT_12Hz5:
cparata 0:f27ce43dee4f 5863 *val = LSM6DSOX_TEMP_BATCHED_AT_12Hz5;
cparata 0:f27ce43dee4f 5864 break;
cparata 0:f27ce43dee4f 5865 case LSM6DSOX_TEMP_BATCHED_AT_52Hz:
cparata 0:f27ce43dee4f 5866 *val = LSM6DSOX_TEMP_BATCHED_AT_52Hz;
cparata 0:f27ce43dee4f 5867 break;
cparata 0:f27ce43dee4f 5868 default:
cparata 0:f27ce43dee4f 5869 *val = LSM6DSOX_TEMP_NOT_BATCHED;
cparata 0:f27ce43dee4f 5870 break;
cparata 0:f27ce43dee4f 5871 }
cparata 0:f27ce43dee4f 5872 return ret;
cparata 0:f27ce43dee4f 5873 }
cparata 0:f27ce43dee4f 5874
cparata 0:f27ce43dee4f 5875 /**
cparata 0:f27ce43dee4f 5876 * @brief Selects decimation for timestamp batching in FIFO.
cparata 0:f27ce43dee4f 5877 * Writing rate will be the maximum rate between XL and
cparata 0:f27ce43dee4f 5878 * GYRO BDR divided by decimation decoder.[set]
cparata 0:f27ce43dee4f 5879 *
cparata 0:f27ce43dee4f 5880 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5881 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4
cparata 0:f27ce43dee4f 5882 *
cparata 0:f27ce43dee4f 5883 */
cparata 0:f27ce43dee4f 5884 int32_t lsm6dsox_fifo_timestamp_decimation_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5885 lsm6dsox_odr_ts_batch_t val)
cparata 0:f27ce43dee4f 5886 {
cparata 0:f27ce43dee4f 5887 lsm6dsox_fifo_ctrl4_t reg;
cparata 0:f27ce43dee4f 5888 int32_t ret;
cparata 0:f27ce43dee4f 5889
cparata 0:f27ce43dee4f 5890 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5891 if (ret == 0) {
cparata 0:f27ce43dee4f 5892 reg.odr_ts_batch = (uint8_t)val;
cparata 0:f27ce43dee4f 5893 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5894 }
cparata 0:f27ce43dee4f 5895 return ret;
cparata 0:f27ce43dee4f 5896 }
cparata 0:f27ce43dee4f 5897
cparata 0:f27ce43dee4f 5898 /**
cparata 0:f27ce43dee4f 5899 * @brief Selects decimation for timestamp batching in FIFO.
cparata 0:f27ce43dee4f 5900 * Writing rate will be the maximum rate between XL and
cparata 0:f27ce43dee4f 5901 * GYRO BDR divided by decimation decoder.[get]
cparata 0:f27ce43dee4f 5902 *
cparata 0:f27ce43dee4f 5903 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5904 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
cparata 0:f27ce43dee4f 5905 *
cparata 0:f27ce43dee4f 5906 */
cparata 0:f27ce43dee4f 5907 int32_t lsm6dsox_fifo_timestamp_decimation_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5908 lsm6dsox_odr_ts_batch_t *val)
cparata 0:f27ce43dee4f 5909 {
cparata 0:f27ce43dee4f 5910 lsm6dsox_fifo_ctrl4_t reg;
cparata 0:f27ce43dee4f 5911 int32_t ret;
cparata 0:f27ce43dee4f 5912
cparata 0:f27ce43dee4f 5913 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5914 switch (reg.odr_ts_batch) {
cparata 0:f27ce43dee4f 5915 case LSM6DSOX_NO_DECIMATION:
cparata 0:f27ce43dee4f 5916 *val = LSM6DSOX_NO_DECIMATION;
cparata 0:f27ce43dee4f 5917 break;
cparata 0:f27ce43dee4f 5918 case LSM6DSOX_DEC_1:
cparata 0:f27ce43dee4f 5919 *val = LSM6DSOX_DEC_1;
cparata 0:f27ce43dee4f 5920 break;
cparata 0:f27ce43dee4f 5921 case LSM6DSOX_DEC_8:
cparata 0:f27ce43dee4f 5922 *val = LSM6DSOX_DEC_8;
cparata 0:f27ce43dee4f 5923 break;
cparata 0:f27ce43dee4f 5924 case LSM6DSOX_DEC_32:
cparata 0:f27ce43dee4f 5925 *val = LSM6DSOX_DEC_32;
cparata 0:f27ce43dee4f 5926 break;
cparata 0:f27ce43dee4f 5927 default:
cparata 0:f27ce43dee4f 5928 *val = LSM6DSOX_NO_DECIMATION;
cparata 0:f27ce43dee4f 5929 break;
cparata 0:f27ce43dee4f 5930 }
cparata 0:f27ce43dee4f 5931 return ret;
cparata 0:f27ce43dee4f 5932 }
cparata 0:f27ce43dee4f 5933
cparata 0:f27ce43dee4f 5934 /**
cparata 0:f27ce43dee4f 5935 * @brief Selects the trigger for the internal counter of batching events
cparata 0:f27ce43dee4f 5936 * between XL and gyro.[set]
cparata 0:f27ce43dee4f 5937 *
cparata 0:f27ce43dee4f 5938 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5939 * @param val change the values of trig_counter_bdr
cparata 0:f27ce43dee4f 5940 * in reg COUNTER_BDR_REG1
cparata 0:f27ce43dee4f 5941 *
cparata 0:f27ce43dee4f 5942 */
cparata 0:f27ce43dee4f 5943 int32_t lsm6dsox_fifo_cnt_event_batch_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5944 lsm6dsox_trig_counter_bdr_t val)
cparata 0:f27ce43dee4f 5945 {
cparata 0:f27ce43dee4f 5946 lsm6dsox_counter_bdr_reg1_t reg;
cparata 0:f27ce43dee4f 5947 int32_t ret;
cparata 0:f27ce43dee4f 5948
cparata 0:f27ce43dee4f 5949 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5950 if (ret == 0) {
cparata 0:f27ce43dee4f 5951 reg.trig_counter_bdr = (uint8_t)val;
cparata 0:f27ce43dee4f 5952 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5953 }
cparata 0:f27ce43dee4f 5954 return ret;
cparata 0:f27ce43dee4f 5955 }
cparata 0:f27ce43dee4f 5956
cparata 0:f27ce43dee4f 5957 /**
cparata 0:f27ce43dee4f 5958 * @brief Selects the trigger for the internal counter of batching events
cparata 0:f27ce43dee4f 5959 * between XL and gyro.[get]
cparata 0:f27ce43dee4f 5960 *
cparata 0:f27ce43dee4f 5961 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5962 * @param val Get the values of trig_counter_bdr
cparata 0:f27ce43dee4f 5963 * in reg COUNTER_BDR_REG1
cparata 0:f27ce43dee4f 5964 *
cparata 0:f27ce43dee4f 5965 */
cparata 0:f27ce43dee4f 5966 int32_t lsm6dsox_fifo_cnt_event_batch_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 5967 lsm6dsox_trig_counter_bdr_t *val)
cparata 0:f27ce43dee4f 5968 {
cparata 0:f27ce43dee4f 5969 lsm6dsox_counter_bdr_reg1_t reg;
cparata 0:f27ce43dee4f 5970 int32_t ret;
cparata 0:f27ce43dee4f 5971
cparata 0:f27ce43dee4f 5972 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 5973 switch (reg.trig_counter_bdr) {
cparata 0:f27ce43dee4f 5974 case LSM6DSOX_XL_BATCH_EVENT:
cparata 0:f27ce43dee4f 5975 *val = LSM6DSOX_XL_BATCH_EVENT;
cparata 0:f27ce43dee4f 5976 break;
cparata 0:f27ce43dee4f 5977 case LSM6DSOX_GYRO_BATCH_EVENT:
cparata 0:f27ce43dee4f 5978 *val = LSM6DSOX_GYRO_BATCH_EVENT;
cparata 0:f27ce43dee4f 5979 break;
cparata 0:f27ce43dee4f 5980 default:
cparata 0:f27ce43dee4f 5981 *val = LSM6DSOX_XL_BATCH_EVENT;
cparata 0:f27ce43dee4f 5982 break;
cparata 0:f27ce43dee4f 5983 }
cparata 0:f27ce43dee4f 5984 return ret;
cparata 0:f27ce43dee4f 5985 }
cparata 0:f27ce43dee4f 5986
cparata 0:f27ce43dee4f 5987 /**
cparata 0:f27ce43dee4f 5988 * @brief Resets the internal counter of batching vents for a single sensor.
cparata 0:f27ce43dee4f 5989 * This bit is automatically reset to zero if it was set to ‘1’.[set]
cparata 0:f27ce43dee4f 5990 *
cparata 0:f27ce43dee4f 5991 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 5992 * @param val change the values of rst_counter_bdr in
cparata 0:f27ce43dee4f 5993 * reg COUNTER_BDR_REG1
cparata 0:f27ce43dee4f 5994 *
cparata 0:f27ce43dee4f 5995 */
cparata 0:f27ce43dee4f 5996 int32_t lsm6dsox_rst_batch_counter_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 5997 {
cparata 0:f27ce43dee4f 5998 lsm6dsox_counter_bdr_reg1_t reg;
cparata 0:f27ce43dee4f 5999 int32_t ret;
cparata 0:f27ce43dee4f 6000
cparata 0:f27ce43dee4f 6001 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6002 if (ret == 0) {
cparata 0:f27ce43dee4f 6003 reg.rst_counter_bdr = val;
cparata 0:f27ce43dee4f 6004 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6005 }
cparata 0:f27ce43dee4f 6006 return ret;
cparata 0:f27ce43dee4f 6007 }
cparata 0:f27ce43dee4f 6008
cparata 0:f27ce43dee4f 6009 /**
cparata 0:f27ce43dee4f 6010 * @brief Resets the internal counter of batching events for a single sensor.
cparata 0:f27ce43dee4f 6011 * This bit is automatically reset to zero if it was set to ‘1’.[get]
cparata 0:f27ce43dee4f 6012 *
cparata 0:f27ce43dee4f 6013 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6014 * @param val change the values of rst_counter_bdr in
cparata 0:f27ce43dee4f 6015 * reg COUNTER_BDR_REG1
cparata 0:f27ce43dee4f 6016 *
cparata 0:f27ce43dee4f 6017 */
cparata 0:f27ce43dee4f 6018 int32_t lsm6dsox_rst_batch_counter_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6019 {
cparata 0:f27ce43dee4f 6020 lsm6dsox_counter_bdr_reg1_t reg;
cparata 0:f27ce43dee4f 6021 int32_t ret;
cparata 0:f27ce43dee4f 6022
cparata 0:f27ce43dee4f 6023 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6024 *val = reg.rst_counter_bdr;
cparata 0:f27ce43dee4f 6025
cparata 0:f27ce43dee4f 6026 return ret;
cparata 0:f27ce43dee4f 6027 }
cparata 0:f27ce43dee4f 6028
cparata 0:f27ce43dee4f 6029 /**
cparata 0:f27ce43dee4f 6030 * @brief Batch data rate counter.[set]
cparata 0:f27ce43dee4f 6031 *
cparata 0:f27ce43dee4f 6032 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6033 * @param val change the values of cnt_bdr_th in
cparata 0:f27ce43dee4f 6034 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata 0:f27ce43dee4f 6035 *
cparata 0:f27ce43dee4f 6036 */
cparata 0:f27ce43dee4f 6037 int32_t lsm6dsox_batch_counter_threshold_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata 0:f27ce43dee4f 6038 {
cparata 0:f27ce43dee4f 6039 lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1;
cparata 0:f27ce43dee4f 6040 lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2;
cparata 0:f27ce43dee4f 6041 int32_t ret;
cparata 0:f27ce43dee4f 6042
cparata 0:f27ce43dee4f 6043 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
cparata 0:f27ce43dee4f 6044 (uint8_t*)&counter_bdr_reg1, 1);
cparata 0:f27ce43dee4f 6045 if (ret == 0) {
cparata 0:f27ce43dee4f 6046 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
cparata 0:f27ce43dee4f 6047 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
cparata 0:f27ce43dee4f 6048 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
cparata 0:f27ce43dee4f 6049 (uint8_t*)&counter_bdr_reg1, 1);
cparata 0:f27ce43dee4f 6050 }
cparata 0:f27ce43dee4f 6051 if (ret == 0) {
cparata 0:f27ce43dee4f 6052 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2,
cparata 0:f27ce43dee4f 6053 (uint8_t*)&counter_bdr_reg2, 1);
cparata 0:f27ce43dee4f 6054 }
cparata 0:f27ce43dee4f 6055 return ret;
cparata 0:f27ce43dee4f 6056 }
cparata 0:f27ce43dee4f 6057
cparata 0:f27ce43dee4f 6058 /**
cparata 0:f27ce43dee4f 6059 * @brief Batch data rate counter.[get]
cparata 0:f27ce43dee4f 6060 *
cparata 0:f27ce43dee4f 6061 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6062 * @param val change the values of cnt_bdr_th in
cparata 0:f27ce43dee4f 6063 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata 0:f27ce43dee4f 6064 *
cparata 0:f27ce43dee4f 6065 */
cparata 0:f27ce43dee4f 6066 int32_t lsm6dsox_batch_counter_threshold_get(lsm6dsox_ctx_t *ctx, uint16_t *val)
cparata 0:f27ce43dee4f 6067 {
cparata 0:f27ce43dee4f 6068 lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1;
cparata 0:f27ce43dee4f 6069 lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2;
cparata 0:f27ce43dee4f 6070 int32_t ret;
cparata 0:f27ce43dee4f 6071
cparata 0:f27ce43dee4f 6072 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
cparata 0:f27ce43dee4f 6073 (uint8_t*)&counter_bdr_reg1, 1);
cparata 0:f27ce43dee4f 6074 if (ret == 0) {
cparata 0:f27ce43dee4f 6075 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2,
cparata 0:f27ce43dee4f 6076 (uint8_t*)&counter_bdr_reg2, 1);
cparata 0:f27ce43dee4f 6077
cparata 0:f27ce43dee4f 6078 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
cparata 0:f27ce43dee4f 6079 + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
cparata 0:f27ce43dee4f 6080 }
cparata 0:f27ce43dee4f 6081
cparata 0:f27ce43dee4f 6082 return ret;
cparata 0:f27ce43dee4f 6083 }
cparata 0:f27ce43dee4f 6084
cparata 0:f27ce43dee4f 6085 /**
cparata 0:f27ce43dee4f 6086 * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
cparata 0:f27ce43dee4f 6087 *
cparata 0:f27ce43dee4f 6088 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6089 * @param val change the values of diff_fifo in reg FIFO_STATUS1
cparata 0:f27ce43dee4f 6090 *
cparata 0:f27ce43dee4f 6091 */
cparata 0:f27ce43dee4f 6092 int32_t lsm6dsox_fifo_data_level_get(lsm6dsox_ctx_t *ctx, uint16_t *val)
cparata 0:f27ce43dee4f 6093 {
cparata 0:f27ce43dee4f 6094 lsm6dsox_fifo_status1_t fifo_status1;
cparata 0:f27ce43dee4f 6095 lsm6dsox_fifo_status2_t fifo_status2;
cparata 0:f27ce43dee4f 6096 int32_t ret;
cparata 0:f27ce43dee4f 6097
cparata 0:f27ce43dee4f 6098 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1,
cparata 0:f27ce43dee4f 6099 (uint8_t*)&fifo_status1, 1);
cparata 0:f27ce43dee4f 6100 if (ret == 0) {
cparata 0:f27ce43dee4f 6101 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2,
cparata 0:f27ce43dee4f 6102 (uint8_t*)&fifo_status2, 1);
cparata 0:f27ce43dee4f 6103 *val = ((uint16_t)fifo_status2.diff_fifo << 8) +
cparata 0:f27ce43dee4f 6104 (uint16_t)fifo_status1.diff_fifo;
cparata 0:f27ce43dee4f 6105 }
cparata 0:f27ce43dee4f 6106 return ret;
cparata 0:f27ce43dee4f 6107 }
cparata 0:f27ce43dee4f 6108
cparata 0:f27ce43dee4f 6109 /**
cparata 0:f27ce43dee4f 6110 * @brief FIFO status.[get]
cparata 0:f27ce43dee4f 6111 *
cparata 0:f27ce43dee4f 6112 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6113 * @param val registers FIFO_STATUS2
cparata 0:f27ce43dee4f 6114 *
cparata 0:f27ce43dee4f 6115 */
cparata 0:f27ce43dee4f 6116 int32_t lsm6dsox_fifo_status_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 6117 lsm6dsox_fifo_status2_t *val)
cparata 0:f27ce43dee4f 6118 {
cparata 0:f27ce43dee4f 6119 int32_t ret;
cparata 0:f27ce43dee4f 6120 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*) val, 1);
cparata 0:f27ce43dee4f 6121 return ret;
cparata 0:f27ce43dee4f 6122 }
cparata 0:f27ce43dee4f 6123
cparata 0:f27ce43dee4f 6124 /**
cparata 0:f27ce43dee4f 6125 * @brief Smart FIFO full status.[get]
cparata 0:f27ce43dee4f 6126 *
cparata 0:f27ce43dee4f 6127 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6128 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
cparata 0:f27ce43dee4f 6129 *
cparata 0:f27ce43dee4f 6130 */
cparata 0:f27ce43dee4f 6131 int32_t lsm6dsox_fifo_full_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6132 {
cparata 0:f27ce43dee4f 6133 lsm6dsox_fifo_status2_t reg;
cparata 0:f27ce43dee4f 6134 int32_t ret;
cparata 0:f27ce43dee4f 6135
cparata 0:f27ce43dee4f 6136 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6137 *val = reg.fifo_full_ia;
cparata 0:f27ce43dee4f 6138
cparata 0:f27ce43dee4f 6139 return ret;
cparata 0:f27ce43dee4f 6140 }
cparata 0:f27ce43dee4f 6141
cparata 0:f27ce43dee4f 6142 /**
cparata 0:f27ce43dee4f 6143 * @brief FIFO overrun status.[get]
cparata 0:f27ce43dee4f 6144 *
cparata 0:f27ce43dee4f 6145 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6146 * @param val change the values of fifo_over_run_latched in
cparata 0:f27ce43dee4f 6147 * reg FIFO_STATUS2
cparata 0:f27ce43dee4f 6148 *
cparata 0:f27ce43dee4f 6149 */
cparata 0:f27ce43dee4f 6150 int32_t lsm6dsox_fifo_ovr_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6151 {
cparata 0:f27ce43dee4f 6152 lsm6dsox_fifo_status2_t reg;
cparata 0:f27ce43dee4f 6153 int32_t ret;
cparata 0:f27ce43dee4f 6154
cparata 0:f27ce43dee4f 6155 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6156 *val = reg.fifo_ovr_ia;
cparata 0:f27ce43dee4f 6157
cparata 0:f27ce43dee4f 6158 return ret;
cparata 0:f27ce43dee4f 6159 }
cparata 0:f27ce43dee4f 6160
cparata 0:f27ce43dee4f 6161 /**
cparata 0:f27ce43dee4f 6162 * @brief FIFO watermark status.[get]
cparata 0:f27ce43dee4f 6163 *
cparata 0:f27ce43dee4f 6164 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6165 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
cparata 0:f27ce43dee4f 6166 *
cparata 0:f27ce43dee4f 6167 */
cparata 0:f27ce43dee4f 6168 int32_t lsm6dsox_fifo_wtm_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6169 {
cparata 0:f27ce43dee4f 6170 lsm6dsox_fifo_status2_t reg;
cparata 0:f27ce43dee4f 6171 int32_t ret;
cparata 0:f27ce43dee4f 6172
cparata 0:f27ce43dee4f 6173 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6174 *val = reg.fifo_wtm_ia;
cparata 0:f27ce43dee4f 6175
cparata 0:f27ce43dee4f 6176 return ret;
cparata 0:f27ce43dee4f 6177 }
cparata 0:f27ce43dee4f 6178
cparata 0:f27ce43dee4f 6179 /**
cparata 0:f27ce43dee4f 6180 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
cparata 0:f27ce43dee4f 6181 *
cparata 0:f27ce43dee4f 6182 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6183 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
cparata 0:f27ce43dee4f 6184 *
cparata 0:f27ce43dee4f 6185 */
cparata 0:f27ce43dee4f 6186 int32_t lsm6dsox_fifo_sensor_tag_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 6187 lsm6dsox_fifo_tag_t *val)
cparata 0:f27ce43dee4f 6188 {
cparata 0:f27ce43dee4f 6189 lsm6dsox_fifo_data_out_tag_t reg;
cparata 0:f27ce43dee4f 6190 int32_t ret;
cparata 0:f27ce43dee4f 6191
cparata 0:f27ce43dee4f 6192 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_TAG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6193 switch (reg.tag_sensor) {
cparata 0:f27ce43dee4f 6194 case LSM6DSOX_GYRO_NC_TAG:
cparata 0:f27ce43dee4f 6195 *val = LSM6DSOX_GYRO_NC_TAG;
cparata 0:f27ce43dee4f 6196 break;
cparata 0:f27ce43dee4f 6197 case LSM6DSOX_XL_NC_TAG:
cparata 0:f27ce43dee4f 6198 *val = LSM6DSOX_XL_NC_TAG;
cparata 0:f27ce43dee4f 6199 break;
cparata 0:f27ce43dee4f 6200 case LSM6DSOX_TEMPERATURE_TAG:
cparata 0:f27ce43dee4f 6201 *val = LSM6DSOX_TEMPERATURE_TAG;
cparata 0:f27ce43dee4f 6202 break;
cparata 0:f27ce43dee4f 6203 case LSM6DSOX_CFG_CHANGE_TAG:
cparata 0:f27ce43dee4f 6204 *val = LSM6DSOX_CFG_CHANGE_TAG;
cparata 0:f27ce43dee4f 6205 break;
cparata 0:f27ce43dee4f 6206 case LSM6DSOX_XL_NC_T_2_TAG:
cparata 0:f27ce43dee4f 6207 *val = LSM6DSOX_XL_NC_T_2_TAG;
cparata 0:f27ce43dee4f 6208 break;
cparata 0:f27ce43dee4f 6209 case LSM6DSOX_XL_NC_T_1_TAG:
cparata 0:f27ce43dee4f 6210 *val = LSM6DSOX_XL_NC_T_1_TAG;
cparata 0:f27ce43dee4f 6211 break;
cparata 0:f27ce43dee4f 6212 case LSM6DSOX_XL_2XC_TAG:
cparata 0:f27ce43dee4f 6213 *val = LSM6DSOX_XL_2XC_TAG;
cparata 0:f27ce43dee4f 6214 break;
cparata 0:f27ce43dee4f 6215 case LSM6DSOX_XL_3XC_TAG:
cparata 0:f27ce43dee4f 6216 *val = LSM6DSOX_XL_3XC_TAG;
cparata 0:f27ce43dee4f 6217 break;
cparata 0:f27ce43dee4f 6218 case LSM6DSOX_GYRO_NC_T_2_TAG:
cparata 0:f27ce43dee4f 6219 *val = LSM6DSOX_GYRO_NC_T_2_TAG;
cparata 0:f27ce43dee4f 6220 break;
cparata 0:f27ce43dee4f 6221 case LSM6DSOX_GYRO_NC_T_1_TAG:
cparata 0:f27ce43dee4f 6222 *val = LSM6DSOX_GYRO_NC_T_1_TAG;
cparata 0:f27ce43dee4f 6223 break;
cparata 0:f27ce43dee4f 6224 case LSM6DSOX_GYRO_2XC_TAG:
cparata 0:f27ce43dee4f 6225 *val = LSM6DSOX_GYRO_2XC_TAG;
cparata 0:f27ce43dee4f 6226 break;
cparata 0:f27ce43dee4f 6227 case LSM6DSOX_GYRO_3XC_TAG:
cparata 0:f27ce43dee4f 6228 *val = LSM6DSOX_GYRO_3XC_TAG;
cparata 0:f27ce43dee4f 6229 break;
cparata 0:f27ce43dee4f 6230 case LSM6DSOX_SENSORHUB_SLAVE0_TAG:
cparata 0:f27ce43dee4f 6231 *val = LSM6DSOX_SENSORHUB_SLAVE0_TAG;
cparata 0:f27ce43dee4f 6232 break;
cparata 0:f27ce43dee4f 6233 case LSM6DSOX_SENSORHUB_SLAVE1_TAG:
cparata 0:f27ce43dee4f 6234 *val = LSM6DSOX_SENSORHUB_SLAVE1_TAG;
cparata 0:f27ce43dee4f 6235 break;
cparata 0:f27ce43dee4f 6236 case LSM6DSOX_SENSORHUB_SLAVE2_TAG:
cparata 0:f27ce43dee4f 6237 *val = LSM6DSOX_SENSORHUB_SLAVE2_TAG;
cparata 0:f27ce43dee4f 6238 break;
cparata 0:f27ce43dee4f 6239 case LSM6DSOX_SENSORHUB_SLAVE3_TAG:
cparata 0:f27ce43dee4f 6240 *val = LSM6DSOX_SENSORHUB_SLAVE3_TAG;
cparata 0:f27ce43dee4f 6241 break;
cparata 0:f27ce43dee4f 6242 case LSM6DSOX_STEP_CPUNTER_TAG:
cparata 0:f27ce43dee4f 6243 *val = LSM6DSOX_STEP_CPUNTER_TAG;
cparata 0:f27ce43dee4f 6244 break;
cparata 0:f27ce43dee4f 6245 case LSM6DSOX_GAME_ROTATION_TAG:
cparata 0:f27ce43dee4f 6246 *val = LSM6DSOX_GAME_ROTATION_TAG;
cparata 0:f27ce43dee4f 6247 break;
cparata 0:f27ce43dee4f 6248 case LSM6DSOX_GEOMAG_ROTATION_TAG:
cparata 0:f27ce43dee4f 6249 *val = LSM6DSOX_GEOMAG_ROTATION_TAG;
cparata 0:f27ce43dee4f 6250 break;
cparata 0:f27ce43dee4f 6251 case LSM6DSOX_ROTATION_TAG:
cparata 0:f27ce43dee4f 6252 *val = LSM6DSOX_ROTATION_TAG;
cparata 0:f27ce43dee4f 6253 break;
cparata 0:f27ce43dee4f 6254 case LSM6DSOX_SENSORHUB_NACK_TAG:
cparata 0:f27ce43dee4f 6255 *val = LSM6DSOX_SENSORHUB_NACK_TAG;
cparata 0:f27ce43dee4f 6256 break;
cparata 0:f27ce43dee4f 6257 default:
cparata 0:f27ce43dee4f 6258 *val = LSM6DSOX_GYRO_NC_TAG;
cparata 0:f27ce43dee4f 6259 break;
cparata 0:f27ce43dee4f 6260 }
cparata 0:f27ce43dee4f 6261 return ret;
cparata 0:f27ce43dee4f 6262 }
cparata 0:f27ce43dee4f 6263
cparata 0:f27ce43dee4f 6264 /**
cparata 0:f27ce43dee4f 6265 * @brief : Enable FIFO batching of pedometer embedded
cparata 0:f27ce43dee4f 6266 * function values.[set]
cparata 0:f27ce43dee4f 6267 *
cparata 0:f27ce43dee4f 6268 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6269 * @param val change the values of gbias_fifo_en in
cparata 0:f27ce43dee4f 6270 * reg LSM6DSOX_EMB_FUNC_FIFO_CFG
cparata 0:f27ce43dee4f 6271 *
cparata 0:f27ce43dee4f 6272 */
cparata 0:f27ce43dee4f 6273 int32_t lsm6dsox_fifo_pedo_batch_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 6274 {
cparata 0:f27ce43dee4f 6275 lsm6dsox_emb_func_fifo_cfg_t reg;
cparata 0:f27ce43dee4f 6276 int32_t ret;
cparata 0:f27ce43dee4f 6277
cparata 0:f27ce43dee4f 6278 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 6279 if (ret == 0) {
cparata 0:f27ce43dee4f 6280 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6281 }
cparata 0:f27ce43dee4f 6282 if (ret == 0) {
cparata 0:f27ce43dee4f 6283 reg.pedo_fifo_en = val;
cparata 0:f27ce43dee4f 6284 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG,
cparata 0:f27ce43dee4f 6285 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6286 }
cparata 0:f27ce43dee4f 6287 if (ret == 0) {
cparata 0:f27ce43dee4f 6288 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6289 }
cparata 0:f27ce43dee4f 6290 return ret;
cparata 0:f27ce43dee4f 6291 }
cparata 0:f27ce43dee4f 6292
cparata 0:f27ce43dee4f 6293 /**
cparata 0:f27ce43dee4f 6294 * @brief Enable FIFO batching of pedometer embedded function values.[get]
cparata 0:f27ce43dee4f 6295 *
cparata 0:f27ce43dee4f 6296 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6297 * @param val change the values of pedo_fifo_en in
cparata 0:f27ce43dee4f 6298 * reg LSM6DSOX_EMB_FUNC_FIFO_CFG
cparata 0:f27ce43dee4f 6299 *
cparata 0:f27ce43dee4f 6300 */
cparata 0:f27ce43dee4f 6301 int32_t lsm6dsox_fifo_pedo_batch_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6302 {
cparata 0:f27ce43dee4f 6303 lsm6dsox_emb_func_fifo_cfg_t reg;
cparata 0:f27ce43dee4f 6304 int32_t ret;
cparata 0:f27ce43dee4f 6305
cparata 0:f27ce43dee4f 6306 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 6307 if (ret == 0) {
cparata 0:f27ce43dee4f 6308 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6309 }
cparata 0:f27ce43dee4f 6310 if (ret == 0) {
cparata 0:f27ce43dee4f 6311 *val = reg.pedo_fifo_en;
cparata 0:f27ce43dee4f 6312 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6313 }
cparata 0:f27ce43dee4f 6314 return ret;
cparata 0:f27ce43dee4f 6315 }
cparata 0:f27ce43dee4f 6316
cparata 0:f27ce43dee4f 6317 /**
cparata 0:f27ce43dee4f 6318 * @brief Enable FIFO batching data of first slave.[set]
cparata 0:f27ce43dee4f 6319 *
cparata 0:f27ce43dee4f 6320 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6321 * @param val change the values of batch_ext_sens_0_en in
cparata 0:f27ce43dee4f 6322 * reg SLV0_CONFIG
cparata 0:f27ce43dee4f 6323 *
cparata 0:f27ce43dee4f 6324 */
cparata 0:f27ce43dee4f 6325 int32_t lsm6dsox_sh_batch_slave_0_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 6326 {
cparata 0:f27ce43dee4f 6327 lsm6dsox_slv0_config_t reg;
cparata 0:f27ce43dee4f 6328 int32_t ret;
cparata 0:f27ce43dee4f 6329
cparata 0:f27ce43dee4f 6330 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 6331 if (ret == 0) {
cparata 0:f27ce43dee4f 6332 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6333 }
cparata 0:f27ce43dee4f 6334 if (ret == 0) {
cparata 0:f27ce43dee4f 6335 reg.batch_ext_sens_0_en = val;
cparata 0:f27ce43dee4f 6336 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6337 }
cparata 0:f27ce43dee4f 6338 if (ret == 0) {
cparata 0:f27ce43dee4f 6339 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6340 }
cparata 0:f27ce43dee4f 6341 return ret;
cparata 0:f27ce43dee4f 6342 }
cparata 0:f27ce43dee4f 6343
cparata 0:f27ce43dee4f 6344 /**
cparata 0:f27ce43dee4f 6345 * @brief Enable FIFO batching data of first slave.[get]
cparata 0:f27ce43dee4f 6346 *
cparata 0:f27ce43dee4f 6347 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6348 * @param val change the values of batch_ext_sens_0_en in
cparata 0:f27ce43dee4f 6349 * reg SLV0_CONFIG
cparata 0:f27ce43dee4f 6350 *
cparata 0:f27ce43dee4f 6351 */
cparata 0:f27ce43dee4f 6352 int32_t lsm6dsox_sh_batch_slave_0_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6353 {
cparata 0:f27ce43dee4f 6354 lsm6dsox_slv0_config_t reg;
cparata 0:f27ce43dee4f 6355 int32_t ret;
cparata 0:f27ce43dee4f 6356
cparata 0:f27ce43dee4f 6357 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 6358 if (ret == 0) {
cparata 0:f27ce43dee4f 6359 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6360 }
cparata 0:f27ce43dee4f 6361 if (ret == 0) {
cparata 0:f27ce43dee4f 6362 *val = reg.batch_ext_sens_0_en;
cparata 0:f27ce43dee4f 6363 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6364 }
cparata 0:f27ce43dee4f 6365 return ret;
cparata 0:f27ce43dee4f 6366 }
cparata 0:f27ce43dee4f 6367
cparata 0:f27ce43dee4f 6368 /**
cparata 0:f27ce43dee4f 6369 * @brief Enable FIFO batching data of second slave.[set]
cparata 0:f27ce43dee4f 6370 *
cparata 0:f27ce43dee4f 6371 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6372 * @param val change the values of batch_ext_sens_1_en in
cparata 0:f27ce43dee4f 6373 * reg SLV1_CONFIG
cparata 0:f27ce43dee4f 6374 *
cparata 0:f27ce43dee4f 6375 */
cparata 0:f27ce43dee4f 6376 int32_t lsm6dsox_sh_batch_slave_1_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 6377 {
cparata 0:f27ce43dee4f 6378 lsm6dsox_slv1_config_t reg;
cparata 0:f27ce43dee4f 6379 int32_t ret;
cparata 0:f27ce43dee4f 6380
cparata 0:f27ce43dee4f 6381 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 6382 if (ret == 0) {
cparata 0:f27ce43dee4f 6383 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6384 }
cparata 0:f27ce43dee4f 6385 if (ret == 0) {
cparata 0:f27ce43dee4f 6386 reg.batch_ext_sens_1_en = val;
cparata 0:f27ce43dee4f 6387 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6388 }
cparata 0:f27ce43dee4f 6389 if (ret == 0) {
cparata 0:f27ce43dee4f 6390 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6391 }
cparata 0:f27ce43dee4f 6392
cparata 0:f27ce43dee4f 6393 return ret;
cparata 0:f27ce43dee4f 6394 }
cparata 0:f27ce43dee4f 6395
cparata 0:f27ce43dee4f 6396 /**
cparata 0:f27ce43dee4f 6397 * @brief Enable FIFO batching data of second slave.[get]
cparata 0:f27ce43dee4f 6398 *
cparata 0:f27ce43dee4f 6399 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6400 * @param val change the values of batch_ext_sens_1_en in
cparata 0:f27ce43dee4f 6401 * reg SLV1_CONFIG
cparata 0:f27ce43dee4f 6402 *
cparata 0:f27ce43dee4f 6403 */
cparata 0:f27ce43dee4f 6404 int32_t lsm6dsox_sh_batch_slave_1_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6405 {
cparata 0:f27ce43dee4f 6406 lsm6dsox_slv1_config_t reg;
cparata 0:f27ce43dee4f 6407 int32_t ret;
cparata 0:f27ce43dee4f 6408
cparata 0:f27ce43dee4f 6409 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 6410 if (ret == 0) {
cparata 0:f27ce43dee4f 6411 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6412 *val = reg.batch_ext_sens_1_en;
cparata 0:f27ce43dee4f 6413 }
cparata 0:f27ce43dee4f 6414 if (ret == 0) {
cparata 0:f27ce43dee4f 6415 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6416 }
cparata 0:f27ce43dee4f 6417 return ret;
cparata 0:f27ce43dee4f 6418 }
cparata 0:f27ce43dee4f 6419
cparata 0:f27ce43dee4f 6420 /**
cparata 0:f27ce43dee4f 6421 * @brief Enable FIFO batching data of third slave.[set]
cparata 0:f27ce43dee4f 6422 *
cparata 0:f27ce43dee4f 6423 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6424 * @param val change the values of batch_ext_sens_2_en in
cparata 0:f27ce43dee4f 6425 * reg SLV2_CONFIG
cparata 0:f27ce43dee4f 6426 *
cparata 0:f27ce43dee4f 6427 */
cparata 0:f27ce43dee4f 6428 int32_t lsm6dsox_sh_batch_slave_2_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 6429 {
cparata 0:f27ce43dee4f 6430 lsm6dsox_slv2_config_t reg;
cparata 0:f27ce43dee4f 6431 int32_t ret;
cparata 0:f27ce43dee4f 6432
cparata 0:f27ce43dee4f 6433 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 6434
cparata 0:f27ce43dee4f 6435 if (ret == 0) {
cparata 0:f27ce43dee4f 6436 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6437 }
cparata 0:f27ce43dee4f 6438 if (ret == 0) {
cparata 0:f27ce43dee4f 6439 reg.batch_ext_sens_2_en = val;
cparata 0:f27ce43dee4f 6440 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6441 }
cparata 0:f27ce43dee4f 6442 if (ret == 0) {
cparata 0:f27ce43dee4f 6443 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6444 }
cparata 0:f27ce43dee4f 6445 return ret;
cparata 0:f27ce43dee4f 6446 }
cparata 0:f27ce43dee4f 6447
cparata 0:f27ce43dee4f 6448 /**
cparata 0:f27ce43dee4f 6449 * @brief Enable FIFO batching data of third slave.[get]
cparata 0:f27ce43dee4f 6450 *
cparata 0:f27ce43dee4f 6451 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6452 * @param val change the values of batch_ext_sens_2_en in
cparata 0:f27ce43dee4f 6453 * reg SLV2_CONFIG
cparata 0:f27ce43dee4f 6454 *
cparata 0:f27ce43dee4f 6455 */
cparata 0:f27ce43dee4f 6456 int32_t lsm6dsox_sh_batch_slave_2_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6457 {
cparata 0:f27ce43dee4f 6458 lsm6dsox_slv2_config_t reg;
cparata 0:f27ce43dee4f 6459 int32_t ret;
cparata 0:f27ce43dee4f 6460
cparata 0:f27ce43dee4f 6461 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 6462 if (ret == 0) {
cparata 0:f27ce43dee4f 6463 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6464 }
cparata 0:f27ce43dee4f 6465 if (ret == 0) {
cparata 0:f27ce43dee4f 6466 *val = reg.batch_ext_sens_2_en;
cparata 0:f27ce43dee4f 6467 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6468 }
cparata 0:f27ce43dee4f 6469
cparata 0:f27ce43dee4f 6470 return ret;
cparata 0:f27ce43dee4f 6471 }
cparata 0:f27ce43dee4f 6472
cparata 0:f27ce43dee4f 6473 /**
cparata 0:f27ce43dee4f 6474 * @brief Enable FIFO batching data of fourth slave.[set]
cparata 0:f27ce43dee4f 6475 *
cparata 0:f27ce43dee4f 6476 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6477 * @param val change the values of batch_ext_sens_3_en
cparata 0:f27ce43dee4f 6478 * in reg SLV3_CONFIG
cparata 0:f27ce43dee4f 6479 *
cparata 0:f27ce43dee4f 6480 */
cparata 0:f27ce43dee4f 6481 int32_t lsm6dsox_sh_batch_slave_3_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 6482 {
cparata 0:f27ce43dee4f 6483 lsm6dsox_slv3_config_t reg;
cparata 0:f27ce43dee4f 6484 int32_t ret;
cparata 0:f27ce43dee4f 6485
cparata 0:f27ce43dee4f 6486 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 6487 if (ret == 0) {
cparata 0:f27ce43dee4f 6488 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6489 }
cparata 0:f27ce43dee4f 6490 if (ret == 0) {
cparata 0:f27ce43dee4f 6491 reg.batch_ext_sens_3_en = val;
cparata 0:f27ce43dee4f 6492 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6493 }
cparata 0:f27ce43dee4f 6494 if (ret == 0) {
cparata 0:f27ce43dee4f 6495 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6496 }
cparata 0:f27ce43dee4f 6497
cparata 0:f27ce43dee4f 6498 return ret;
cparata 0:f27ce43dee4f 6499 }
cparata 0:f27ce43dee4f 6500
cparata 0:f27ce43dee4f 6501 /**
cparata 0:f27ce43dee4f 6502 * @brief Enable FIFO batching data of fourth slave.[get]
cparata 0:f27ce43dee4f 6503 *
cparata 0:f27ce43dee4f 6504 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6505 * @param val change the values of batch_ext_sens_3_en in
cparata 0:f27ce43dee4f 6506 * reg SLV3_CONFIG
cparata 0:f27ce43dee4f 6507 *
cparata 0:f27ce43dee4f 6508 */
cparata 0:f27ce43dee4f 6509 int32_t lsm6dsox_sh_batch_slave_3_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6510 {
cparata 0:f27ce43dee4f 6511 lsm6dsox_slv3_config_t reg;
cparata 0:f27ce43dee4f 6512 int32_t ret;
cparata 0:f27ce43dee4f 6513
cparata 0:f27ce43dee4f 6514 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 6515 if (ret == 0) {
cparata 0:f27ce43dee4f 6516 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6517 }
cparata 0:f27ce43dee4f 6518 if (ret == 0) {
cparata 0:f27ce43dee4f 6519 *val = reg.batch_ext_sens_3_en;
cparata 0:f27ce43dee4f 6520 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6521 }
cparata 0:f27ce43dee4f 6522
cparata 0:f27ce43dee4f 6523 return ret;
cparata 0:f27ce43dee4f 6524 }
cparata 0:f27ce43dee4f 6525
cparata 0:f27ce43dee4f 6526 /**
cparata 0:f27ce43dee4f 6527 * @}
cparata 0:f27ce43dee4f 6528 *
cparata 0:f27ce43dee4f 6529 */
cparata 0:f27ce43dee4f 6530
cparata 0:f27ce43dee4f 6531 /**
cparata 0:f27ce43dee4f 6532 * @defgroup LSM6DSOX_DEN_functionality
cparata 0:f27ce43dee4f 6533 * @brief This section groups all the functions concerning
cparata 0:f27ce43dee4f 6534 * DEN functionality.
cparata 0:f27ce43dee4f 6535 * @{
cparata 0:f27ce43dee4f 6536 *
cparata 0:f27ce43dee4f 6537 */
cparata 0:f27ce43dee4f 6538
cparata 0:f27ce43dee4f 6539 /**
cparata 0:f27ce43dee4f 6540 * @brief DEN functionality marking mode.[set]
cparata 0:f27ce43dee4f 6541 *
cparata 0:f27ce43dee4f 6542 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6543 * @param val change the values of den_mode in reg CTRL6_C
cparata 0:f27ce43dee4f 6544 *
cparata 0:f27ce43dee4f 6545 */
cparata 0:f27ce43dee4f 6546 int32_t lsm6dsox_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t val)
cparata 0:f27ce43dee4f 6547 {
cparata 0:f27ce43dee4f 6548 lsm6dsox_ctrl6_c_t reg;
cparata 0:f27ce43dee4f 6549 int32_t ret;
cparata 0:f27ce43dee4f 6550
cparata 0:f27ce43dee4f 6551 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6552 if (ret == 0) {
cparata 0:f27ce43dee4f 6553 reg.den_mode = (uint8_t)val;
cparata 0:f27ce43dee4f 6554 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6555 }
cparata 0:f27ce43dee4f 6556
cparata 0:f27ce43dee4f 6557 return ret;
cparata 0:f27ce43dee4f 6558 }
cparata 0:f27ce43dee4f 6559
cparata 0:f27ce43dee4f 6560 /**
cparata 0:f27ce43dee4f 6561 * @brief DEN functionality marking mode.[get]
cparata 0:f27ce43dee4f 6562 *
cparata 0:f27ce43dee4f 6563 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6564 * @param val Get the values of den_mode in reg CTRL6_C
cparata 0:f27ce43dee4f 6565 *
cparata 0:f27ce43dee4f 6566 */
cparata 0:f27ce43dee4f 6567 int32_t lsm6dsox_den_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t *val)
cparata 0:f27ce43dee4f 6568 {
cparata 0:f27ce43dee4f 6569 lsm6dsox_ctrl6_c_t reg;
cparata 0:f27ce43dee4f 6570 int32_t ret;
cparata 0:f27ce43dee4f 6571
cparata 0:f27ce43dee4f 6572 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6573
cparata 0:f27ce43dee4f 6574 switch (reg.den_mode) {
cparata 0:f27ce43dee4f 6575 case LSM6DSOX_DEN_DISABLE:
cparata 0:f27ce43dee4f 6576 *val = LSM6DSOX_DEN_DISABLE;
cparata 0:f27ce43dee4f 6577 break;
cparata 0:f27ce43dee4f 6578 case LSM6DSOX_LEVEL_FIFO:
cparata 0:f27ce43dee4f 6579 *val = LSM6DSOX_LEVEL_FIFO;
cparata 0:f27ce43dee4f 6580 break;
cparata 0:f27ce43dee4f 6581 case LSM6DSOX_LEVEL_LETCHED:
cparata 0:f27ce43dee4f 6582 *val = LSM6DSOX_LEVEL_LETCHED;
cparata 0:f27ce43dee4f 6583 break;
cparata 0:f27ce43dee4f 6584 case LSM6DSOX_LEVEL_TRIGGER:
cparata 0:f27ce43dee4f 6585 *val = LSM6DSOX_LEVEL_TRIGGER;
cparata 0:f27ce43dee4f 6586 break;
cparata 0:f27ce43dee4f 6587 case LSM6DSOX_EDGE_TRIGGER:
cparata 0:f27ce43dee4f 6588 *val = LSM6DSOX_EDGE_TRIGGER;
cparata 0:f27ce43dee4f 6589 break;
cparata 0:f27ce43dee4f 6590 default:
cparata 0:f27ce43dee4f 6591 *val = LSM6DSOX_DEN_DISABLE;
cparata 0:f27ce43dee4f 6592 break;
cparata 0:f27ce43dee4f 6593 }
cparata 0:f27ce43dee4f 6594 return ret;
cparata 0:f27ce43dee4f 6595 }
cparata 0:f27ce43dee4f 6596
cparata 0:f27ce43dee4f 6597 /**
cparata 0:f27ce43dee4f 6598 * @brief DEN active level configuration.[set]
cparata 0:f27ce43dee4f 6599 *
cparata 0:f27ce43dee4f 6600 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6601 * @param val change the values of den_lh in reg CTRL9_XL
cparata 0:f27ce43dee4f 6602 *
cparata 0:f27ce43dee4f 6603 */
cparata 0:f27ce43dee4f 6604 int32_t lsm6dsox_den_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t val)
cparata 0:f27ce43dee4f 6605 {
cparata 0:f27ce43dee4f 6606 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6607 int32_t ret;
cparata 0:f27ce43dee4f 6608
cparata 0:f27ce43dee4f 6609 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6610 if (ret == 0) {
cparata 0:f27ce43dee4f 6611 reg.den_lh = (uint8_t)val;
cparata 0:f27ce43dee4f 6612 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6613 }
cparata 0:f27ce43dee4f 6614
cparata 0:f27ce43dee4f 6615 return ret;
cparata 0:f27ce43dee4f 6616 }
cparata 0:f27ce43dee4f 6617
cparata 0:f27ce43dee4f 6618 /**
cparata 0:f27ce43dee4f 6619 * @brief DEN active level configuration.[get]
cparata 0:f27ce43dee4f 6620 *
cparata 0:f27ce43dee4f 6621 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6622 * @param val Get the values of den_lh in reg CTRL9_XL
cparata 0:f27ce43dee4f 6623 *
cparata 0:f27ce43dee4f 6624 */
cparata 0:f27ce43dee4f 6625 int32_t lsm6dsox_den_polarity_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t *val)
cparata 0:f27ce43dee4f 6626 {
cparata 0:f27ce43dee4f 6627 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6628 int32_t ret;
cparata 0:f27ce43dee4f 6629
cparata 0:f27ce43dee4f 6630 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6631
cparata 0:f27ce43dee4f 6632 switch (reg.den_lh) {
cparata 0:f27ce43dee4f 6633 case LSM6DSOX_DEN_ACT_LOW:
cparata 0:f27ce43dee4f 6634 *val = LSM6DSOX_DEN_ACT_LOW;
cparata 0:f27ce43dee4f 6635 break;
cparata 0:f27ce43dee4f 6636 case LSM6DSOX_DEN_ACT_HIGH:
cparata 0:f27ce43dee4f 6637 *val = LSM6DSOX_DEN_ACT_HIGH;
cparata 0:f27ce43dee4f 6638 break;
cparata 0:f27ce43dee4f 6639 default:
cparata 0:f27ce43dee4f 6640 *val = LSM6DSOX_DEN_ACT_LOW;
cparata 0:f27ce43dee4f 6641 break;
cparata 0:f27ce43dee4f 6642 }
cparata 0:f27ce43dee4f 6643 return ret;
cparata 0:f27ce43dee4f 6644 }
cparata 0:f27ce43dee4f 6645
cparata 0:f27ce43dee4f 6646 /**
cparata 0:f27ce43dee4f 6647 * @brief DEN enable.[set]
cparata 0:f27ce43dee4f 6648 *
cparata 0:f27ce43dee4f 6649 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6650 * @param val change the values of den_xl_g in reg CTRL9_XL
cparata 0:f27ce43dee4f 6651 *
cparata 0:f27ce43dee4f 6652 */
cparata 0:f27ce43dee4f 6653 int32_t lsm6dsox_den_enable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t val)
cparata 0:f27ce43dee4f 6654 {
cparata 0:f27ce43dee4f 6655 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6656 int32_t ret;
cparata 0:f27ce43dee4f 6657
cparata 0:f27ce43dee4f 6658 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6659 if (ret == 0) {
cparata 0:f27ce43dee4f 6660 reg.den_xl_g = (uint8_t)val;
cparata 0:f27ce43dee4f 6661 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6662 }
cparata 0:f27ce43dee4f 6663
cparata 0:f27ce43dee4f 6664 return ret;
cparata 0:f27ce43dee4f 6665 }
cparata 0:f27ce43dee4f 6666
cparata 0:f27ce43dee4f 6667 /**
cparata 0:f27ce43dee4f 6668 * @brief DEN enable.[get]
cparata 0:f27ce43dee4f 6669 *
cparata 0:f27ce43dee4f 6670 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6671 * @param val Get the values of den_xl_g in reg CTRL9_XL
cparata 0:f27ce43dee4f 6672 *
cparata 0:f27ce43dee4f 6673 */
cparata 0:f27ce43dee4f 6674 int32_t lsm6dsox_den_enable_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t *val)
cparata 0:f27ce43dee4f 6675 {
cparata 0:f27ce43dee4f 6676 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6677 int32_t ret;
cparata 0:f27ce43dee4f 6678
cparata 0:f27ce43dee4f 6679 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6680
cparata 0:f27ce43dee4f 6681 switch (reg.den_xl_g) {
cparata 0:f27ce43dee4f 6682 case LSM6DSOX_STAMP_IN_GY_DATA:
cparata 0:f27ce43dee4f 6683 *val = LSM6DSOX_STAMP_IN_GY_DATA;
cparata 0:f27ce43dee4f 6684 break;
cparata 0:f27ce43dee4f 6685 case LSM6DSOX_STAMP_IN_XL_DATA:
cparata 0:f27ce43dee4f 6686 *val = LSM6DSOX_STAMP_IN_XL_DATA;
cparata 0:f27ce43dee4f 6687 break;
cparata 0:f27ce43dee4f 6688 case LSM6DSOX_STAMP_IN_GY_XL_DATA:
cparata 0:f27ce43dee4f 6689 *val = LSM6DSOX_STAMP_IN_GY_XL_DATA;
cparata 0:f27ce43dee4f 6690 break;
cparata 0:f27ce43dee4f 6691 default:
cparata 0:f27ce43dee4f 6692 *val = LSM6DSOX_STAMP_IN_GY_DATA;
cparata 0:f27ce43dee4f 6693 break;
cparata 0:f27ce43dee4f 6694 }
cparata 0:f27ce43dee4f 6695 return ret;
cparata 0:f27ce43dee4f 6696 }
cparata 0:f27ce43dee4f 6697
cparata 0:f27ce43dee4f 6698 /**
cparata 0:f27ce43dee4f 6699 * @brief DEN value stored in LSB of X-axis.[set]
cparata 0:f27ce43dee4f 6700 *
cparata 0:f27ce43dee4f 6701 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6702 * @param val change the values of den_z in reg CTRL9_XL
cparata 0:f27ce43dee4f 6703 *
cparata 0:f27ce43dee4f 6704 */
cparata 0:f27ce43dee4f 6705 int32_t lsm6dsox_den_mark_axis_x_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 6706 {
cparata 0:f27ce43dee4f 6707 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6708 int32_t ret;
cparata 0:f27ce43dee4f 6709
cparata 0:f27ce43dee4f 6710 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6711 if (ret == 0) {
cparata 0:f27ce43dee4f 6712 reg.den_z = val;
cparata 0:f27ce43dee4f 6713 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6714 }
cparata 0:f27ce43dee4f 6715
cparata 0:f27ce43dee4f 6716 return ret;
cparata 0:f27ce43dee4f 6717 }
cparata 0:f27ce43dee4f 6718
cparata 0:f27ce43dee4f 6719 /**
cparata 0:f27ce43dee4f 6720 * @brief DEN value stored in LSB of X-axis.[get]
cparata 0:f27ce43dee4f 6721 *
cparata 0:f27ce43dee4f 6722 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6723 * @param val change the values of den_z in reg CTRL9_XL
cparata 0:f27ce43dee4f 6724 *
cparata 0:f27ce43dee4f 6725 */
cparata 0:f27ce43dee4f 6726 int32_t lsm6dsox_den_mark_axis_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6727 {
cparata 0:f27ce43dee4f 6728 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6729 int32_t ret;
cparata 0:f27ce43dee4f 6730
cparata 0:f27ce43dee4f 6731 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6732 *val = reg.den_z;
cparata 0:f27ce43dee4f 6733
cparata 0:f27ce43dee4f 6734 return ret;
cparata 0:f27ce43dee4f 6735 }
cparata 0:f27ce43dee4f 6736
cparata 0:f27ce43dee4f 6737 /**
cparata 0:f27ce43dee4f 6738 * @brief DEN value stored in LSB of Y-axis.[set]
cparata 0:f27ce43dee4f 6739 *
cparata 0:f27ce43dee4f 6740 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6741 * @param val change the values of den_y in reg CTRL9_XL
cparata 0:f27ce43dee4f 6742 *
cparata 0:f27ce43dee4f 6743 */
cparata 0:f27ce43dee4f 6744 int32_t lsm6dsox_den_mark_axis_y_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 6745 {
cparata 0:f27ce43dee4f 6746 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6747 int32_t ret;
cparata 0:f27ce43dee4f 6748
cparata 0:f27ce43dee4f 6749 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6750 if (ret == 0) {
cparata 0:f27ce43dee4f 6751 reg.den_y = val;
cparata 0:f27ce43dee4f 6752 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6753 }
cparata 0:f27ce43dee4f 6754
cparata 0:f27ce43dee4f 6755 return ret;
cparata 0:f27ce43dee4f 6756 }
cparata 0:f27ce43dee4f 6757
cparata 0:f27ce43dee4f 6758 /**
cparata 0:f27ce43dee4f 6759 * @brief DEN value stored in LSB of Y-axis.[get]
cparata 0:f27ce43dee4f 6760 *
cparata 0:f27ce43dee4f 6761 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6762 * @param val change the values of den_y in reg CTRL9_XL
cparata 0:f27ce43dee4f 6763 *
cparata 0:f27ce43dee4f 6764 */
cparata 0:f27ce43dee4f 6765 int32_t lsm6dsox_den_mark_axis_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6766 {
cparata 0:f27ce43dee4f 6767 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6768 int32_t ret;
cparata 0:f27ce43dee4f 6769
cparata 0:f27ce43dee4f 6770 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6771 *val = reg.den_y;
cparata 0:f27ce43dee4f 6772
cparata 0:f27ce43dee4f 6773 return ret;
cparata 0:f27ce43dee4f 6774 }
cparata 0:f27ce43dee4f 6775
cparata 0:f27ce43dee4f 6776 /**
cparata 0:f27ce43dee4f 6777 * @brief DEN value stored in LSB of Z-axis.[set]
cparata 0:f27ce43dee4f 6778 *
cparata 0:f27ce43dee4f 6779 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6780 * @param val change the values of den_x in reg CTRL9_XL
cparata 0:f27ce43dee4f 6781 *
cparata 0:f27ce43dee4f 6782 */
cparata 0:f27ce43dee4f 6783 int32_t lsm6dsox_den_mark_axis_z_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 6784 {
cparata 0:f27ce43dee4f 6785 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6786 int32_t ret;
cparata 0:f27ce43dee4f 6787
cparata 0:f27ce43dee4f 6788 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6789 if (ret == 0) {
cparata 0:f27ce43dee4f 6790 reg.den_x = val;
cparata 0:f27ce43dee4f 6791 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6792 }
cparata 0:f27ce43dee4f 6793
cparata 0:f27ce43dee4f 6794 return ret;
cparata 0:f27ce43dee4f 6795 }
cparata 0:f27ce43dee4f 6796
cparata 0:f27ce43dee4f 6797 /**
cparata 0:f27ce43dee4f 6798 * @brief DEN value stored in LSB of Z-axis.[get]
cparata 0:f27ce43dee4f 6799 *
cparata 0:f27ce43dee4f 6800 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6801 * @param val change the values of den_x in reg CTRL9_XL
cparata 0:f27ce43dee4f 6802 *
cparata 0:f27ce43dee4f 6803 */
cparata 0:f27ce43dee4f 6804 int32_t lsm6dsox_den_mark_axis_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6805 {
cparata 0:f27ce43dee4f 6806 lsm6dsox_ctrl9_xl_t reg;
cparata 0:f27ce43dee4f 6807 int32_t ret;
cparata 0:f27ce43dee4f 6808
cparata 0:f27ce43dee4f 6809 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6810 *val = reg.den_x;
cparata 0:f27ce43dee4f 6811
cparata 0:f27ce43dee4f 6812 return ret;
cparata 0:f27ce43dee4f 6813 }
cparata 0:f27ce43dee4f 6814
cparata 0:f27ce43dee4f 6815 /**
cparata 0:f27ce43dee4f 6816 * @}
cparata 0:f27ce43dee4f 6817 *
cparata 0:f27ce43dee4f 6818 */
cparata 0:f27ce43dee4f 6819
cparata 0:f27ce43dee4f 6820 /**
cparata 0:f27ce43dee4f 6821 * @defgroup LSM6DSOX_Pedometer
cparata 0:f27ce43dee4f 6822 * @brief This section groups all the functions that manage pedometer.
cparata 0:f27ce43dee4f 6823 * @{
cparata 0:f27ce43dee4f 6824 *
cparata 0:f27ce43dee4f 6825 */
cparata 0:f27ce43dee4f 6826
cparata 0:f27ce43dee4f 6827 /**
cparata 0:f27ce43dee4f 6828 * @brief Enable pedometer algorithm.[set]
cparata 0:f27ce43dee4f 6829 *
cparata 0:f27ce43dee4f 6830 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6831 * @param val turn on and configure pedometer
cparata 0:f27ce43dee4f 6832 *
cparata 0:f27ce43dee4f 6833 */
cparata 0:f27ce43dee4f 6834 int32_t lsm6dsox_pedo_sens_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t val)
cparata 0:f27ce43dee4f 6835 {
cparata 0:f27ce43dee4f 6836 lsm6dsox_emb_func_en_a_t emb_func_en_a;
cparata 0:f27ce43dee4f 6837 lsm6dsox_emb_func_en_b_t emb_func_en_b;
cparata 0:f27ce43dee4f 6838 lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg;
cparata 0:f27ce43dee4f 6839 int32_t ret;
cparata 0:f27ce43dee4f 6840
cparata 0:f27ce43dee4f 6841 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
cparata 0:f27ce43dee4f 6842 (uint8_t*)&pedo_cmd_reg);
cparata 0:f27ce43dee4f 6843 if (ret == 0) {
cparata 0:f27ce43dee4f 6844 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 6845 }
cparata 0:f27ce43dee4f 6846 if (ret == 0) {
cparata 0:f27ce43dee4f 6847 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
cparata 0:f27ce43dee4f 6848 (uint8_t*)&emb_func_en_a, 1);
cparata 0:f27ce43dee4f 6849 }
cparata 0:f27ce43dee4f 6850 if (ret == 0) {
cparata 0:f27ce43dee4f 6851 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata 0:f27ce43dee4f 6852 (uint8_t*)&emb_func_en_b, 1);
cparata 0:f27ce43dee4f 6853
cparata 0:f27ce43dee4f 6854 emb_func_en_a.pedo_en = (uint8_t)val & 0x01U;
cparata 0:f27ce43dee4f 6855 emb_func_en_b.mlc_en = ((uint8_t)val & 0x02U)>>1;
cparata 0:f27ce43dee4f 6856 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4;
cparata 0:f27ce43dee4f 6857 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5;
cparata 0:f27ce43dee4f 6858 }
cparata 0:f27ce43dee4f 6859 if (ret == 0) {
cparata 0:f27ce43dee4f 6860 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
cparata 0:f27ce43dee4f 6861 (uint8_t*)&emb_func_en_a, 1);
cparata 0:f27ce43dee4f 6862 }
cparata 0:f27ce43dee4f 6863 if (ret == 0) {
cparata 0:f27ce43dee4f 6864 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata 0:f27ce43dee4f 6865 (uint8_t*)&emb_func_en_b, 1);
cparata 0:f27ce43dee4f 6866 }
cparata 0:f27ce43dee4f 6867 if (ret == 0) {
cparata 0:f27ce43dee4f 6868 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6869 }
cparata 0:f27ce43dee4f 6870 if (ret == 0) {
cparata 0:f27ce43dee4f 6871 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
cparata 0:f27ce43dee4f 6872 (uint8_t*)&pedo_cmd_reg);
cparata 0:f27ce43dee4f 6873 }
cparata 0:f27ce43dee4f 6874 return ret;
cparata 0:f27ce43dee4f 6875 }
cparata 0:f27ce43dee4f 6876
cparata 0:f27ce43dee4f 6877 /**
cparata 0:f27ce43dee4f 6878 * @brief Enable pedometer algorithm.[get]
cparata 0:f27ce43dee4f 6879 *
cparata 0:f27ce43dee4f 6880 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6881 * @param val turn on and configure pedometer
cparata 0:f27ce43dee4f 6882 *
cparata 0:f27ce43dee4f 6883 */
cparata 0:f27ce43dee4f 6884 int32_t lsm6dsox_pedo_sens_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t *val)
cparata 0:f27ce43dee4f 6885 {
cparata 0:f27ce43dee4f 6886 lsm6dsox_emb_func_en_a_t emb_func_en_a;
cparata 0:f27ce43dee4f 6887 lsm6dsox_emb_func_en_b_t emb_func_en_b;
cparata 0:f27ce43dee4f 6888 lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg;
cparata 0:f27ce43dee4f 6889 int32_t ret;
cparata 0:f27ce43dee4f 6890
cparata 0:f27ce43dee4f 6891 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
cparata 0:f27ce43dee4f 6892 (uint8_t*)&pedo_cmd_reg);
cparata 0:f27ce43dee4f 6893 if (ret == 0) {
cparata 0:f27ce43dee4f 6894 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 6895 }
cparata 0:f27ce43dee4f 6896 if (ret == 0) {
cparata 0:f27ce43dee4f 6897 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
cparata 0:f27ce43dee4f 6898 (uint8_t*)&emb_func_en_a, 1);
cparata 0:f27ce43dee4f 6899 }
cparata 0:f27ce43dee4f 6900 if (ret == 0) {
cparata 0:f27ce43dee4f 6901 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata 0:f27ce43dee4f 6902 (uint8_t*)&emb_func_en_b, 1);
cparata 0:f27ce43dee4f 6903 }
cparata 0:f27ce43dee4f 6904 if (ret == 0) {
cparata 0:f27ce43dee4f 6905 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6906 }
cparata 0:f27ce43dee4f 6907 switch ( (pedo_cmd_reg.ad_det_en <<5) | (pedo_cmd_reg.fp_rejection_en << 4) |
cparata 0:f27ce43dee4f 6908 (emb_func_en_b.mlc_en << 1) | emb_func_en_a.pedo_en) {
cparata 0:f27ce43dee4f 6909 case LSM6DSOX_PEDO_DISABLE:
cparata 0:f27ce43dee4f 6910 *val = LSM6DSOX_PEDO_DISABLE;
cparata 0:f27ce43dee4f 6911 break;
cparata 0:f27ce43dee4f 6912 case LSM6DSOX_PEDO_BASE_MODE:
cparata 0:f27ce43dee4f 6913 *val = LSM6DSOX_PEDO_BASE_MODE;
cparata 0:f27ce43dee4f 6914 break;
cparata 0:f27ce43dee4f 6915 case LSM6DSOX_PEDO_ADV_MODE:
cparata 0:f27ce43dee4f 6916 *val = LSM6DSOX_PEDO_ADV_MODE;
cparata 0:f27ce43dee4f 6917 break;
cparata 0:f27ce43dee4f 6918 case LSM6DSOX_FALSE_STEP_REJ:
cparata 0:f27ce43dee4f 6919 *val = LSM6DSOX_FALSE_STEP_REJ;
cparata 0:f27ce43dee4f 6920 break;
cparata 0:f27ce43dee4f 6921 case LSM6DSOX_FALSE_STEP_REJ_ADV_MODE:
cparata 0:f27ce43dee4f 6922 *val = LSM6DSOX_FALSE_STEP_REJ_ADV_MODE;
cparata 0:f27ce43dee4f 6923 break;
cparata 0:f27ce43dee4f 6924 default:
cparata 0:f27ce43dee4f 6925 *val = LSM6DSOX_PEDO_DISABLE;
cparata 0:f27ce43dee4f 6926 break;
cparata 0:f27ce43dee4f 6927 }
cparata 0:f27ce43dee4f 6928 return ret;
cparata 0:f27ce43dee4f 6929 }
cparata 0:f27ce43dee4f 6930
cparata 0:f27ce43dee4f 6931 /**
cparata 0:f27ce43dee4f 6932 * @brief Interrupt status bit for step detection.[get]
cparata 0:f27ce43dee4f 6933 *
cparata 0:f27ce43dee4f 6934 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6935 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS
cparata 0:f27ce43dee4f 6936 *
cparata 0:f27ce43dee4f 6937 */
cparata 0:f27ce43dee4f 6938 int32_t lsm6dsox_pedo_step_detect_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 6939 {
cparata 0:f27ce43dee4f 6940 lsm6dsox_emb_func_status_t reg;
cparata 0:f27ce43dee4f 6941 int32_t ret;
cparata 0:f27ce43dee4f 6942
cparata 0:f27ce43dee4f 6943 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 6944 if (ret == 0) {
cparata 0:f27ce43dee4f 6945 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 6946 }
cparata 0:f27ce43dee4f 6947 if (ret == 0) {
cparata 0:f27ce43dee4f 6948 *val = reg.is_step_det;
cparata 0:f27ce43dee4f 6949 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 6950 }
cparata 0:f27ce43dee4f 6951
cparata 0:f27ce43dee4f 6952 return ret;
cparata 0:f27ce43dee4f 6953 }
cparata 0:f27ce43dee4f 6954
cparata 0:f27ce43dee4f 6955 /**
cparata 0:f27ce43dee4f 6956 * @brief Pedometer debounce configuration register (r/w).[set]
cparata 0:f27ce43dee4f 6957 *
cparata 0:f27ce43dee4f 6958 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6959 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 6960 *
cparata 0:f27ce43dee4f 6961 */
cparata 0:f27ce43dee4f 6962 int32_t lsm6dsox_pedo_debounce_steps_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 6963 {
cparata 0:f27ce43dee4f 6964 int32_t ret;
cparata 0:f27ce43dee4f 6965 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff);
cparata 0:f27ce43dee4f 6966 return ret;
cparata 0:f27ce43dee4f 6967 }
cparata 0:f27ce43dee4f 6968
cparata 0:f27ce43dee4f 6969 /**
cparata 0:f27ce43dee4f 6970 * @brief Pedometer debounce configuration register (r/w).[get]
cparata 0:f27ce43dee4f 6971 *
cparata 0:f27ce43dee4f 6972 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6973 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 6974 *
cparata 0:f27ce43dee4f 6975 */
cparata 0:f27ce43dee4f 6976 int32_t lsm6dsox_pedo_debounce_steps_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 6977 {
cparata 0:f27ce43dee4f 6978 int32_t ret;
cparata 0:f27ce43dee4f 6979 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff);
cparata 0:f27ce43dee4f 6980 return ret;
cparata 0:f27ce43dee4f 6981 }
cparata 0:f27ce43dee4f 6982
cparata 0:f27ce43dee4f 6983 /**
cparata 0:f27ce43dee4f 6984 * @brief Time period register for step detection on delta time (r/w).[set]
cparata 0:f27ce43dee4f 6985 *
cparata 0:f27ce43dee4f 6986 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 6987 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 6988 *
cparata 0:f27ce43dee4f 6989 */
cparata 0:f27ce43dee4f 6990 int32_t lsm6dsox_pedo_steps_period_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 6991 {
cparata 0:f27ce43dee4f 6992 int32_t ret;
cparata 0:f27ce43dee4f 6993 uint8_t index;
cparata 0:f27ce43dee4f 6994
cparata 0:f27ce43dee4f 6995 index = 0x00U;
cparata 0:f27ce43dee4f 6996 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]);
cparata 0:f27ce43dee4f 6997 if (ret == 0) {
cparata 0:f27ce43dee4f 6998 index++;
cparata 0:f27ce43dee4f 6999 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H,
cparata 0:f27ce43dee4f 7000 &buff[index]);
cparata 0:f27ce43dee4f 7001 }
cparata 0:f27ce43dee4f 7002 return ret;
cparata 0:f27ce43dee4f 7003 }
cparata 0:f27ce43dee4f 7004
cparata 0:f27ce43dee4f 7005 /**
cparata 0:f27ce43dee4f 7006 * @brief Time period register for step detection on delta time (r/w).[get]
cparata 0:f27ce43dee4f 7007 *
cparata 0:f27ce43dee4f 7008 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7009 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 7010 *
cparata 0:f27ce43dee4f 7011 */
cparata 0:f27ce43dee4f 7012 int32_t lsm6dsox_pedo_steps_period_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7013 {
cparata 0:f27ce43dee4f 7014 int32_t ret;
cparata 0:f27ce43dee4f 7015 uint8_t index;
cparata 0:f27ce43dee4f 7016
cparata 0:f27ce43dee4f 7017 index = 0x00U;
cparata 0:f27ce43dee4f 7018 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]);
cparata 0:f27ce43dee4f 7019 if (ret == 0) {
cparata 0:f27ce43dee4f 7020 index++;
cparata 0:f27ce43dee4f 7021 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H,
cparata 0:f27ce43dee4f 7022 &buff[index]);
cparata 0:f27ce43dee4f 7023 }
cparata 0:f27ce43dee4f 7024 return ret;
cparata 0:f27ce43dee4f 7025 }
cparata 0:f27ce43dee4f 7026
cparata 0:f27ce43dee4f 7027 /**
cparata 0:f27ce43dee4f 7028 * @brief Set when user wants to generate interrupt on count overflow
cparata 0:f27ce43dee4f 7029 * event/every step.[set]
cparata 0:f27ce43dee4f 7030 *
cparata 0:f27ce43dee4f 7031 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7032 * @param val change the values of carry_count_en in reg PEDO_CMD_REG
cparata 0:f27ce43dee4f 7033 *
cparata 0:f27ce43dee4f 7034 */
cparata 0:f27ce43dee4f 7035 int32_t lsm6dsox_pedo_int_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 7036 lsm6dsox_carry_count_en_t val)
cparata 0:f27ce43dee4f 7037 {
cparata 0:f27ce43dee4f 7038 lsm6dsox_pedo_cmd_reg_t reg;
cparata 0:f27ce43dee4f 7039 int32_t ret;
cparata 0:f27ce43dee4f 7040
cparata 0:f27ce43dee4f 7041 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7042 if (ret == 0) {
cparata 0:f27ce43dee4f 7043 reg.carry_count_en = (uint8_t)val;
cparata 0:f27ce43dee4f 7044 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
cparata 0:f27ce43dee4f 7045 (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7046 }
cparata 0:f27ce43dee4f 7047 return ret;
cparata 0:f27ce43dee4f 7048 }
cparata 0:f27ce43dee4f 7049
cparata 0:f27ce43dee4f 7050 /**
cparata 0:f27ce43dee4f 7051 * @brief Set when user wants to generate interrupt on count overflow
cparata 0:f27ce43dee4f 7052 * event/every step.[get]
cparata 0:f27ce43dee4f 7053 *
cparata 0:f27ce43dee4f 7054 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7055 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
cparata 0:f27ce43dee4f 7056 *
cparata 0:f27ce43dee4f 7057 */
cparata 0:f27ce43dee4f 7058 int32_t lsm6dsox_pedo_int_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 7059 lsm6dsox_carry_count_en_t *val)
cparata 0:f27ce43dee4f 7060 {
cparata 0:f27ce43dee4f 7061 lsm6dsox_pedo_cmd_reg_t reg;
cparata 0:f27ce43dee4f 7062 int32_t ret;
cparata 0:f27ce43dee4f 7063
cparata 0:f27ce43dee4f 7064 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7065 switch (reg.carry_count_en) {
cparata 0:f27ce43dee4f 7066 case LSM6DSOX_EVERY_STEP:
cparata 0:f27ce43dee4f 7067 *val = LSM6DSOX_EVERY_STEP;
cparata 0:f27ce43dee4f 7068 break;
cparata 0:f27ce43dee4f 7069 case LSM6DSOX_COUNT_OVERFLOW:
cparata 0:f27ce43dee4f 7070 *val = LSM6DSOX_COUNT_OVERFLOW;
cparata 0:f27ce43dee4f 7071 break;
cparata 0:f27ce43dee4f 7072 default:
cparata 0:f27ce43dee4f 7073 *val = LSM6DSOX_EVERY_STEP;
cparata 0:f27ce43dee4f 7074 break;
cparata 0:f27ce43dee4f 7075 }
cparata 0:f27ce43dee4f 7076 return ret;
cparata 0:f27ce43dee4f 7077 }
cparata 0:f27ce43dee4f 7078
cparata 0:f27ce43dee4f 7079 /**
cparata 0:f27ce43dee4f 7080 * @}
cparata 0:f27ce43dee4f 7081 *
cparata 0:f27ce43dee4f 7082 */
cparata 0:f27ce43dee4f 7083
cparata 0:f27ce43dee4f 7084 /**
cparata 0:f27ce43dee4f 7085 * @defgroup LSM6DSOX_significant_motion
cparata 0:f27ce43dee4f 7086 * @brief This section groups all the functions that manage the
cparata 0:f27ce43dee4f 7087 * significant motion detection.
cparata 0:f27ce43dee4f 7088 * @{
cparata 0:f27ce43dee4f 7089 *
cparata 0:f27ce43dee4f 7090 */
cparata 0:f27ce43dee4f 7091
cparata 0:f27ce43dee4f 7092 /**
cparata 0:f27ce43dee4f 7093 * @brief Enable significant motion detection function.[set]
cparata 0:f27ce43dee4f 7094 *
cparata 0:f27ce43dee4f 7095 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7096 * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
cparata 0:f27ce43dee4f 7097 *
cparata 0:f27ce43dee4f 7098 */
cparata 0:f27ce43dee4f 7099 int32_t lsm6dsox_motion_sens_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 7100 {
cparata 0:f27ce43dee4f 7101 lsm6dsox_emb_func_en_a_t reg;
cparata 0:f27ce43dee4f 7102 int32_t ret;
cparata 0:f27ce43dee4f 7103
cparata 0:f27ce43dee4f 7104 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7105 if (ret == 0) {
cparata 0:f27ce43dee4f 7106 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7107 }
cparata 0:f27ce43dee4f 7108 if (ret == 0) {
cparata 0:f27ce43dee4f 7109 reg.sign_motion_en = val;
cparata 0:f27ce43dee4f 7110 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7111 }
cparata 0:f27ce43dee4f 7112 if (ret == 0) {
cparata 0:f27ce43dee4f 7113 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7114 }
cparata 0:f27ce43dee4f 7115 return ret;
cparata 0:f27ce43dee4f 7116 }
cparata 0:f27ce43dee4f 7117
cparata 0:f27ce43dee4f 7118 /**
cparata 0:f27ce43dee4f 7119 * @brief Enable significant motion detection function.[get]
cparata 0:f27ce43dee4f 7120 *
cparata 0:f27ce43dee4f 7121 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7122 * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
cparata 0:f27ce43dee4f 7123 *
cparata 0:f27ce43dee4f 7124 */
cparata 0:f27ce43dee4f 7125 int32_t lsm6dsox_motion_sens_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 7126 {
cparata 0:f27ce43dee4f 7127 lsm6dsox_emb_func_en_a_t reg;
cparata 0:f27ce43dee4f 7128 int32_t ret;
cparata 0:f27ce43dee4f 7129
cparata 0:f27ce43dee4f 7130 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7131 if (ret == 0) {
cparata 0:f27ce43dee4f 7132 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7133 }
cparata 0:f27ce43dee4f 7134 if (ret == 0) {
cparata 0:f27ce43dee4f 7135 *val = reg.sign_motion_en;
cparata 0:f27ce43dee4f 7136 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7137 }
cparata 0:f27ce43dee4f 7138 return ret;
cparata 0:f27ce43dee4f 7139 }
cparata 0:f27ce43dee4f 7140
cparata 0:f27ce43dee4f 7141 /**
cparata 0:f27ce43dee4f 7142 * @brief Interrupt status bit for significant motion detection.[get]
cparata 0:f27ce43dee4f 7143 *
cparata 0:f27ce43dee4f 7144 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7145 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
cparata 0:f27ce43dee4f 7146 *
cparata 0:f27ce43dee4f 7147 */
cparata 0:f27ce43dee4f 7148 int32_t lsm6dsox_motion_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 7149 {
cparata 0:f27ce43dee4f 7150 lsm6dsox_emb_func_status_t reg;
cparata 0:f27ce43dee4f 7151 int32_t ret;
cparata 0:f27ce43dee4f 7152
cparata 0:f27ce43dee4f 7153 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7154 if (ret == 0) {
cparata 0:f27ce43dee4f 7155 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7156 }
cparata 0:f27ce43dee4f 7157 if (ret == 0) {
cparata 0:f27ce43dee4f 7158 *val = reg.is_sigmot;
cparata 0:f27ce43dee4f 7159 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7160 }
cparata 0:f27ce43dee4f 7161
cparata 0:f27ce43dee4f 7162 return ret;
cparata 0:f27ce43dee4f 7163 }
cparata 0:f27ce43dee4f 7164
cparata 0:f27ce43dee4f 7165 /**
cparata 0:f27ce43dee4f 7166 * @}
cparata 0:f27ce43dee4f 7167 *
cparata 0:f27ce43dee4f 7168 */
cparata 0:f27ce43dee4f 7169
cparata 0:f27ce43dee4f 7170 /**
cparata 0:f27ce43dee4f 7171 * @defgroup LSM6DSOX_tilt_detection
cparata 0:f27ce43dee4f 7172 * @brief This section groups all the functions that manage the tilt
cparata 0:f27ce43dee4f 7173 * event detection.
cparata 0:f27ce43dee4f 7174 * @{
cparata 0:f27ce43dee4f 7175 *
cparata 0:f27ce43dee4f 7176 */
cparata 0:f27ce43dee4f 7177
cparata 0:f27ce43dee4f 7178 /**
cparata 0:f27ce43dee4f 7179 * @brief Enable tilt calculation.[set]
cparata 0:f27ce43dee4f 7180 *
cparata 0:f27ce43dee4f 7181 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7182 * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
cparata 0:f27ce43dee4f 7183 *
cparata 0:f27ce43dee4f 7184 */
cparata 0:f27ce43dee4f 7185 int32_t lsm6dsox_tilt_sens_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 7186 {
cparata 0:f27ce43dee4f 7187 lsm6dsox_emb_func_en_a_t reg;
cparata 0:f27ce43dee4f 7188 int32_t ret;
cparata 0:f27ce43dee4f 7189
cparata 0:f27ce43dee4f 7190 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7191 if (ret == 0) {
cparata 0:f27ce43dee4f 7192 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7193 }
cparata 0:f27ce43dee4f 7194 if (ret == 0) {
cparata 0:f27ce43dee4f 7195 reg.tilt_en = val;
cparata 0:f27ce43dee4f 7196 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7197 }
cparata 0:f27ce43dee4f 7198 if (ret == 0) {
cparata 0:f27ce43dee4f 7199 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7200 }
cparata 0:f27ce43dee4f 7201 return ret;
cparata 0:f27ce43dee4f 7202 }
cparata 0:f27ce43dee4f 7203
cparata 0:f27ce43dee4f 7204 /**
cparata 0:f27ce43dee4f 7205 * @brief Enable tilt calculation.[get]
cparata 0:f27ce43dee4f 7206 *
cparata 0:f27ce43dee4f 7207 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7208 * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
cparata 0:f27ce43dee4f 7209 *
cparata 0:f27ce43dee4f 7210 */
cparata 0:f27ce43dee4f 7211 int32_t lsm6dsox_tilt_sens_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 7212 {
cparata 0:f27ce43dee4f 7213 lsm6dsox_emb_func_en_a_t reg;
cparata 0:f27ce43dee4f 7214 int32_t ret;
cparata 0:f27ce43dee4f 7215
cparata 0:f27ce43dee4f 7216 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7217 if (ret == 0) {
cparata 0:f27ce43dee4f 7218 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7219 }
cparata 0:f27ce43dee4f 7220 if (ret == 0) {
cparata 0:f27ce43dee4f 7221 *val = reg.tilt_en;
cparata 0:f27ce43dee4f 7222 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7223 }
cparata 0:f27ce43dee4f 7224
cparata 0:f27ce43dee4f 7225 return ret;
cparata 0:f27ce43dee4f 7226 }
cparata 0:f27ce43dee4f 7227
cparata 0:f27ce43dee4f 7228 /**
cparata 0:f27ce43dee4f 7229 * @brief Interrupt status bit for tilt detection.[get]
cparata 0:f27ce43dee4f 7230 *
cparata 0:f27ce43dee4f 7231 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7232 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS
cparata 0:f27ce43dee4f 7233 *
cparata 0:f27ce43dee4f 7234 */
cparata 0:f27ce43dee4f 7235 int32_t lsm6dsox_tilt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 7236 {
cparata 0:f27ce43dee4f 7237 lsm6dsox_emb_func_status_t reg;
cparata 0:f27ce43dee4f 7238 int32_t ret;
cparata 0:f27ce43dee4f 7239
cparata 0:f27ce43dee4f 7240 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7241 if (ret == 0) {
cparata 0:f27ce43dee4f 7242 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7243 }
cparata 0:f27ce43dee4f 7244 if (ret == 0) {
cparata 0:f27ce43dee4f 7245 *val = reg.is_tilt;
cparata 0:f27ce43dee4f 7246 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7247 }
cparata 0:f27ce43dee4f 7248
cparata 0:f27ce43dee4f 7249 return ret;
cparata 0:f27ce43dee4f 7250 }
cparata 0:f27ce43dee4f 7251
cparata 0:f27ce43dee4f 7252 /**
cparata 0:f27ce43dee4f 7253 * @}
cparata 0:f27ce43dee4f 7254 *
cparata 0:f27ce43dee4f 7255 */
cparata 0:f27ce43dee4f 7256
cparata 0:f27ce43dee4f 7257 /**
cparata 0:f27ce43dee4f 7258 * @defgroup LSM6DSOX_ magnetometer_sensor
cparata 0:f27ce43dee4f 7259 * @brief This section groups all the functions that manage additional
cparata 0:f27ce43dee4f 7260 * magnetometer sensor.
cparata 0:f27ce43dee4f 7261 * @{
cparata 0:f27ce43dee4f 7262 *
cparata 0:f27ce43dee4f 7263 */
cparata 0:f27ce43dee4f 7264
cparata 0:f27ce43dee4f 7265 /**
cparata 0:f27ce43dee4f 7266 * @brief External magnetometer sensitivity value register for
cparata 0:f27ce43dee4f 7267 * Sensor hub.[set]
cparata 0:f27ce43dee4f 7268 *
cparata 0:f27ce43dee4f 7269 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7270 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 7271 *
cparata 0:f27ce43dee4f 7272 */
cparata 0:f27ce43dee4f 7273 int32_t lsm6dsox_sh_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7274 {
cparata 0:f27ce43dee4f 7275 int32_t ret;
cparata 0:f27ce43dee4f 7276 uint8_t index;
cparata 0:f27ce43dee4f 7277
cparata 0:f27ce43dee4f 7278 index = 0x00U;
cparata 0:f27ce43dee4f 7279 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L,
cparata 0:f27ce43dee4f 7280 &buff[index]);
cparata 0:f27ce43dee4f 7281 if (ret == 0) {
cparata 0:f27ce43dee4f 7282 index++;
cparata 0:f27ce43dee4f 7283 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H,
cparata 0:f27ce43dee4f 7284 &buff[index]);
cparata 0:f27ce43dee4f 7285 }
cparata 0:f27ce43dee4f 7286
cparata 0:f27ce43dee4f 7287 return ret;
cparata 0:f27ce43dee4f 7288 }
cparata 0:f27ce43dee4f 7289
cparata 0:f27ce43dee4f 7290 /**
cparata 0:f27ce43dee4f 7291 * @brief External magnetometer sensitivity value register for
cparata 0:f27ce43dee4f 7292 * Sensor hub.[get]
cparata 0:f27ce43dee4f 7293 *
cparata 0:f27ce43dee4f 7294 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7295 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 7296 *
cparata 0:f27ce43dee4f 7297 */
cparata 0:f27ce43dee4f 7298 int32_t lsm6dsox_sh_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7299 {
cparata 0:f27ce43dee4f 7300 int32_t ret;
cparata 0:f27ce43dee4f 7301 uint8_t index;
cparata 0:f27ce43dee4f 7302
cparata 0:f27ce43dee4f 7303 index = 0x00U;
cparata 0:f27ce43dee4f 7304 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L,
cparata 0:f27ce43dee4f 7305 &buff[index]);
cparata 0:f27ce43dee4f 7306 if (ret == 0) {
cparata 0:f27ce43dee4f 7307 index++;
cparata 0:f27ce43dee4f 7308 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H,
cparata 0:f27ce43dee4f 7309 &buff[index]);
cparata 0:f27ce43dee4f 7310 }
cparata 0:f27ce43dee4f 7311
cparata 0:f27ce43dee4f 7312 return ret;
cparata 0:f27ce43dee4f 7313 }
cparata 0:f27ce43dee4f 7314
cparata 0:f27ce43dee4f 7315 /**
cparata 0:f27ce43dee4f 7316 * @brief External magnetometer sensitivity value register for
cparata 0:f27ce43dee4f 7317 * Machine Learning Core.[set]
cparata 0:f27ce43dee4f 7318 *
cparata 0:f27ce43dee4f 7319 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7320 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 7321 *
cparata 0:f27ce43dee4f 7322 */
cparata 0:f27ce43dee4f 7323 int32_t lsm6dsox_mlc_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7324 {
cparata 0:f27ce43dee4f 7325 int32_t ret;
cparata 0:f27ce43dee4f 7326 uint8_t index;
cparata 0:f27ce43dee4f 7327
cparata 0:f27ce43dee4f 7328 index = 0x00U;
cparata 0:f27ce43dee4f 7329 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L,
cparata 0:f27ce43dee4f 7330 &buff[index]);
cparata 0:f27ce43dee4f 7331 if (ret == 0) {
cparata 0:f27ce43dee4f 7332 index++;
cparata 0:f27ce43dee4f 7333 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H,
cparata 0:f27ce43dee4f 7334 &buff[index]);
cparata 0:f27ce43dee4f 7335 }
cparata 0:f27ce43dee4f 7336 return ret;
cparata 0:f27ce43dee4f 7337 }
cparata 0:f27ce43dee4f 7338
cparata 0:f27ce43dee4f 7339 /**
cparata 0:f27ce43dee4f 7340 * @brief External magnetometer sensitivity value register for
cparata 0:f27ce43dee4f 7341 * Machine Learning Core.[get]
cparata 0:f27ce43dee4f 7342 *
cparata 0:f27ce43dee4f 7343 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7344 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 7345 *
cparata 0:f27ce43dee4f 7346 */
cparata 0:f27ce43dee4f 7347 int32_t lsm6dsox_mlc_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7348 {
cparata 0:f27ce43dee4f 7349 int32_t ret;
cparata 0:f27ce43dee4f 7350 uint8_t index;
cparata 0:f27ce43dee4f 7351
cparata 0:f27ce43dee4f 7352 index = 0x00U;
cparata 0:f27ce43dee4f 7353 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L,
cparata 0:f27ce43dee4f 7354 &buff[index]);
cparata 0:f27ce43dee4f 7355 if (ret == 0) {
cparata 0:f27ce43dee4f 7356 index++;
cparata 0:f27ce43dee4f 7357 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H,
cparata 0:f27ce43dee4f 7358 &buff[index]);
cparata 0:f27ce43dee4f 7359 }
cparata 0:f27ce43dee4f 7360 return ret;
cparata 0:f27ce43dee4f 7361 }
cparata 0:f27ce43dee4f 7362
cparata 0:f27ce43dee4f 7363
cparata 0:f27ce43dee4f 7364 /**
cparata 0:f27ce43dee4f 7365 * @brief Offset for hard-iron compensation register (r/w).[set]
cparata 0:f27ce43dee4f 7366 *
cparata 0:f27ce43dee4f 7367 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7368 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 7369 *
cparata 0:f27ce43dee4f 7370 */
cparata 0:f27ce43dee4f 7371 int32_t lsm6dsox_mag_offset_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7372 {
cparata 0:f27ce43dee4f 7373 int32_t ret;
cparata 0:f27ce43dee4f 7374 uint8_t index;
cparata 0:f27ce43dee4f 7375
cparata 0:f27ce43dee4f 7376 index = 0x00U;
cparata 0:f27ce43dee4f 7377 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]);
cparata 0:f27ce43dee4f 7378 if (ret == 0) {
cparata 0:f27ce43dee4f 7379 index++;
cparata 0:f27ce43dee4f 7380 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]);
cparata 0:f27ce43dee4f 7381 }
cparata 0:f27ce43dee4f 7382 if (ret == 0) {
cparata 0:f27ce43dee4f 7383 index++;
cparata 0:f27ce43dee4f 7384 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]);
cparata 0:f27ce43dee4f 7385 }
cparata 0:f27ce43dee4f 7386 if (ret == 0) {
cparata 0:f27ce43dee4f 7387 index++;
cparata 0:f27ce43dee4f 7388 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]);
cparata 0:f27ce43dee4f 7389 }
cparata 0:f27ce43dee4f 7390 if (ret == 0) {
cparata 0:f27ce43dee4f 7391 index++;
cparata 0:f27ce43dee4f 7392
cparata 0:f27ce43dee4f 7393 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]);
cparata 0:f27ce43dee4f 7394 }
cparata 0:f27ce43dee4f 7395 if (ret == 0) {
cparata 0:f27ce43dee4f 7396 index++;
cparata 0:f27ce43dee4f 7397 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]);
cparata 0:f27ce43dee4f 7398 }
cparata 0:f27ce43dee4f 7399
cparata 0:f27ce43dee4f 7400 return ret;
cparata 0:f27ce43dee4f 7401 }
cparata 0:f27ce43dee4f 7402
cparata 0:f27ce43dee4f 7403 /**
cparata 0:f27ce43dee4f 7404 * @brief Offset for hard-iron compensation register (r/w).[get]
cparata 0:f27ce43dee4f 7405 *
cparata 0:f27ce43dee4f 7406 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7407 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 7408 *
cparata 0:f27ce43dee4f 7409 */
cparata 0:f27ce43dee4f 7410 int32_t lsm6dsox_mag_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7411 {
cparata 0:f27ce43dee4f 7412 int32_t ret;
cparata 0:f27ce43dee4f 7413 uint8_t index;
cparata 0:f27ce43dee4f 7414
cparata 0:f27ce43dee4f 7415 index = 0x00U;
cparata 0:f27ce43dee4f 7416 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]);
cparata 0:f27ce43dee4f 7417 if (ret == 0) {
cparata 0:f27ce43dee4f 7418 index++;
cparata 0:f27ce43dee4f 7419 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]);
cparata 0:f27ce43dee4f 7420 }
cparata 0:f27ce43dee4f 7421 if (ret == 0) {
cparata 0:f27ce43dee4f 7422 index++;
cparata 0:f27ce43dee4f 7423
cparata 0:f27ce43dee4f 7424 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]);
cparata 0:f27ce43dee4f 7425 }
cparata 0:f27ce43dee4f 7426 if (ret == 0) {
cparata 0:f27ce43dee4f 7427 index++;
cparata 0:f27ce43dee4f 7428 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]);
cparata 0:f27ce43dee4f 7429 }
cparata 0:f27ce43dee4f 7430 if (ret == 0) {
cparata 0:f27ce43dee4f 7431 index++;
cparata 0:f27ce43dee4f 7432
cparata 0:f27ce43dee4f 7433 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]);
cparata 0:f27ce43dee4f 7434 }
cparata 0:f27ce43dee4f 7435 if (ret == 0) {
cparata 0:f27ce43dee4f 7436 index++;
cparata 0:f27ce43dee4f 7437 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]);
cparata 0:f27ce43dee4f 7438 }
cparata 0:f27ce43dee4f 7439 return ret;
cparata 0:f27ce43dee4f 7440 }
cparata 0:f27ce43dee4f 7441
cparata 0:f27ce43dee4f 7442 /**
cparata 0:f27ce43dee4f 7443 * @brief Soft-iron (3x3 symmetric) matrix correction
cparata 0:f27ce43dee4f 7444 * register (r/w). The value is expressed as
cparata 0:f27ce43dee4f 7445 * half-precision floating-point format:
cparata 0:f27ce43dee4f 7446 * SEEEEEFFFFFFFFFF
cparata 0:f27ce43dee4f 7447 * S: 1 sign bit;
cparata 0:f27ce43dee4f 7448 * E: 5 exponent bits;
cparata 0:f27ce43dee4f 7449 * F: 10 fraction bits).[set]
cparata 0:f27ce43dee4f 7450 *
cparata 0:f27ce43dee4f 7451 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7452 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 7453 *
cparata 0:f27ce43dee4f 7454 */
cparata 0:f27ce43dee4f 7455 int32_t lsm6dsox_mag_soft_iron_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7456 {
cparata 0:f27ce43dee4f 7457 int32_t ret;
cparata 0:f27ce43dee4f 7458 uint8_t index;
cparata 0:f27ce43dee4f 7459
cparata 0:f27ce43dee4f 7460 index = 0x00U;
cparata 0:f27ce43dee4f 7461 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]);
cparata 0:f27ce43dee4f 7462 if (ret == 0) {
cparata 0:f27ce43dee4f 7463 index++;
cparata 0:f27ce43dee4f 7464 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]);
cparata 0:f27ce43dee4f 7465 }
cparata 0:f27ce43dee4f 7466 if (ret == 0) {
cparata 0:f27ce43dee4f 7467 index++;
cparata 0:f27ce43dee4f 7468
cparata 0:f27ce43dee4f 7469 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]);
cparata 0:f27ce43dee4f 7470 }
cparata 0:f27ce43dee4f 7471 if (ret == 0) {
cparata 0:f27ce43dee4f 7472 index++;
cparata 0:f27ce43dee4f 7473 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]);
cparata 0:f27ce43dee4f 7474 }
cparata 0:f27ce43dee4f 7475 if (ret == 0) {
cparata 0:f27ce43dee4f 7476 index++;
cparata 0:f27ce43dee4f 7477
cparata 0:f27ce43dee4f 7478 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]);
cparata 0:f27ce43dee4f 7479 }
cparata 0:f27ce43dee4f 7480 if (ret == 0) {
cparata 0:f27ce43dee4f 7481 index++;
cparata 0:f27ce43dee4f 7482 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]);
cparata 0:f27ce43dee4f 7483 }
cparata 0:f27ce43dee4f 7484 if (ret == 0) {
cparata 0:f27ce43dee4f 7485 index++;
cparata 0:f27ce43dee4f 7486
cparata 0:f27ce43dee4f 7487 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]);
cparata 0:f27ce43dee4f 7488 }
cparata 0:f27ce43dee4f 7489 if (ret == 0) {
cparata 0:f27ce43dee4f 7490 index++;
cparata 0:f27ce43dee4f 7491 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]);
cparata 0:f27ce43dee4f 7492 }
cparata 0:f27ce43dee4f 7493 if (ret == 0) {
cparata 0:f27ce43dee4f 7494 index++;
cparata 0:f27ce43dee4f 7495
cparata 0:f27ce43dee4f 7496 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]);
cparata 0:f27ce43dee4f 7497 }
cparata 0:f27ce43dee4f 7498 if (ret == 0) {
cparata 0:f27ce43dee4f 7499 index++;
cparata 0:f27ce43dee4f 7500 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]);
cparata 0:f27ce43dee4f 7501 }
cparata 0:f27ce43dee4f 7502 if (ret == 0) {
cparata 0:f27ce43dee4f 7503 index++;
cparata 0:f27ce43dee4f 7504
cparata 0:f27ce43dee4f 7505 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]);
cparata 0:f27ce43dee4f 7506 }
cparata 0:f27ce43dee4f 7507 if (ret == 0) {
cparata 0:f27ce43dee4f 7508 index++;
cparata 0:f27ce43dee4f 7509 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]);
cparata 0:f27ce43dee4f 7510 }
cparata 0:f27ce43dee4f 7511
cparata 0:f27ce43dee4f 7512 return ret;
cparata 0:f27ce43dee4f 7513 }
cparata 0:f27ce43dee4f 7514
cparata 0:f27ce43dee4f 7515 /**
cparata 0:f27ce43dee4f 7516 * @brief Soft-iron (3x3 symmetric) matrix
cparata 0:f27ce43dee4f 7517 * correction register (r/w).
cparata 0:f27ce43dee4f 7518 * The value is expressed as half-precision
cparata 0:f27ce43dee4f 7519 * floating-point format:
cparata 0:f27ce43dee4f 7520 * SEEEEEFFFFFFFFFF
cparata 0:f27ce43dee4f 7521 * S: 1 sign bit;
cparata 0:f27ce43dee4f 7522 * E: 5 exponent bits;
cparata 0:f27ce43dee4f 7523 * F: 10 fraction bits.[get]
cparata 0:f27ce43dee4f 7524 *
cparata 0:f27ce43dee4f 7525 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7526 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 7527 *
cparata 0:f27ce43dee4f 7528 */
cparata 0:f27ce43dee4f 7529 int32_t lsm6dsox_mag_soft_iron_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7530 {
cparata 0:f27ce43dee4f 7531 int32_t ret;
cparata 0:f27ce43dee4f 7532 uint8_t index;
cparata 0:f27ce43dee4f 7533
cparata 0:f27ce43dee4f 7534 index = 0x00U;
cparata 0:f27ce43dee4f 7535 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]);
cparata 0:f27ce43dee4f 7536 if (ret == 0) {
cparata 0:f27ce43dee4f 7537 index++;
cparata 0:f27ce43dee4f 7538 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]);
cparata 0:f27ce43dee4f 7539 }
cparata 0:f27ce43dee4f 7540 if (ret == 0) {
cparata 0:f27ce43dee4f 7541 index++;
cparata 0:f27ce43dee4f 7542
cparata 0:f27ce43dee4f 7543 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]);
cparata 0:f27ce43dee4f 7544 }
cparata 0:f27ce43dee4f 7545 if (ret == 0) {
cparata 0:f27ce43dee4f 7546 index++;
cparata 0:f27ce43dee4f 7547 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]);
cparata 0:f27ce43dee4f 7548 }
cparata 0:f27ce43dee4f 7549 if (ret == 0) {
cparata 0:f27ce43dee4f 7550 index++;
cparata 0:f27ce43dee4f 7551
cparata 0:f27ce43dee4f 7552 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]);
cparata 0:f27ce43dee4f 7553 }
cparata 0:f27ce43dee4f 7554 if (ret == 0) {
cparata 0:f27ce43dee4f 7555 index++;
cparata 0:f27ce43dee4f 7556 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]);
cparata 0:f27ce43dee4f 7557 }
cparata 0:f27ce43dee4f 7558 if (ret == 0) {
cparata 0:f27ce43dee4f 7559 index++;
cparata 0:f27ce43dee4f 7560
cparata 0:f27ce43dee4f 7561 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]);
cparata 0:f27ce43dee4f 7562 }
cparata 0:f27ce43dee4f 7563 if (ret == 0) {
cparata 0:f27ce43dee4f 7564 index++;
cparata 0:f27ce43dee4f 7565 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]);
cparata 0:f27ce43dee4f 7566 }
cparata 0:f27ce43dee4f 7567 if (ret == 0) {
cparata 0:f27ce43dee4f 7568 index++;
cparata 0:f27ce43dee4f 7569
cparata 0:f27ce43dee4f 7570 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]);
cparata 0:f27ce43dee4f 7571 }
cparata 0:f27ce43dee4f 7572 if (ret == 0) {
cparata 0:f27ce43dee4f 7573 index++;
cparata 0:f27ce43dee4f 7574 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]);
cparata 0:f27ce43dee4f 7575 }
cparata 0:f27ce43dee4f 7576 if (ret == 0) {
cparata 0:f27ce43dee4f 7577 index++;
cparata 0:f27ce43dee4f 7578
cparata 0:f27ce43dee4f 7579 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]);
cparata 0:f27ce43dee4f 7580 }
cparata 0:f27ce43dee4f 7581 if (ret == 0) {
cparata 0:f27ce43dee4f 7582 index++;
cparata 0:f27ce43dee4f 7583 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]);
cparata 0:f27ce43dee4f 7584 }
cparata 0:f27ce43dee4f 7585
cparata 0:f27ce43dee4f 7586 return ret;
cparata 0:f27ce43dee4f 7587 }
cparata 0:f27ce43dee4f 7588
cparata 0:f27ce43dee4f 7589 /**
cparata 0:f27ce43dee4f 7590 * @brief Magnetometer Z-axis coordinates
cparata 0:f27ce43dee4f 7591 * rotation (to be aligned to
cparata 0:f27ce43dee4f 7592 * accelerometer/gyroscope axes
cparata 0:f27ce43dee4f 7593 * orientation).[set]
cparata 0:f27ce43dee4f 7594 *
cparata 0:f27ce43dee4f 7595 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7596 * @param val change the values of mag_z_axis in reg MAG_CFG_A
cparata 0:f27ce43dee4f 7597 *
cparata 0:f27ce43dee4f 7598 */
cparata 0:f27ce43dee4f 7599 int32_t lsm6dsox_mag_z_orient_set(lsm6dsox_ctx_t *ctx, lsm6dsox_mag_z_axis_t val)
cparata 0:f27ce43dee4f 7600 {
cparata 0:f27ce43dee4f 7601 lsm6dsox_mag_cfg_a_t reg;
cparata 0:f27ce43dee4f 7602 int32_t ret;
cparata 0:f27ce43dee4f 7603
cparata 0:f27ce43dee4f 7604 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7605 if (ret == 0) {
cparata 0:f27ce43dee4f 7606 reg.mag_z_axis = (uint8_t) val;
cparata 0:f27ce43dee4f 7607 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7608 }
cparata 0:f27ce43dee4f 7609
cparata 0:f27ce43dee4f 7610 return ret;
cparata 0:f27ce43dee4f 7611 }
cparata 0:f27ce43dee4f 7612
cparata 0:f27ce43dee4f 7613 /**
cparata 0:f27ce43dee4f 7614 * @brief Magnetometer Z-axis coordinates
cparata 0:f27ce43dee4f 7615 * rotation (to be aligned to
cparata 0:f27ce43dee4f 7616 * accelerometer/gyroscope axes
cparata 0:f27ce43dee4f 7617 * orientation).[get]
cparata 0:f27ce43dee4f 7618 *
cparata 0:f27ce43dee4f 7619 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7620 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
cparata 0:f27ce43dee4f 7621 *
cparata 0:f27ce43dee4f 7622 */
cparata 0:f27ce43dee4f 7623 int32_t lsm6dsox_mag_z_orient_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 7624 lsm6dsox_mag_z_axis_t *val)
cparata 0:f27ce43dee4f 7625 {
cparata 0:f27ce43dee4f 7626 lsm6dsox_mag_cfg_a_t reg;
cparata 0:f27ce43dee4f 7627 int32_t ret;
cparata 0:f27ce43dee4f 7628 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7629 switch (reg.mag_z_axis) {
cparata 0:f27ce43dee4f 7630 case LSM6DSOX_Z_EQ_Y:
cparata 0:f27ce43dee4f 7631 *val = LSM6DSOX_Z_EQ_Y;
cparata 0:f27ce43dee4f 7632 break;
cparata 0:f27ce43dee4f 7633 case LSM6DSOX_Z_EQ_MIN_Y:
cparata 0:f27ce43dee4f 7634 *val = LSM6DSOX_Z_EQ_MIN_Y;
cparata 0:f27ce43dee4f 7635 break;
cparata 0:f27ce43dee4f 7636 case LSM6DSOX_Z_EQ_X:
cparata 0:f27ce43dee4f 7637 *val = LSM6DSOX_Z_EQ_X;
cparata 0:f27ce43dee4f 7638 break;
cparata 0:f27ce43dee4f 7639 case LSM6DSOX_Z_EQ_MIN_X:
cparata 0:f27ce43dee4f 7640 *val = LSM6DSOX_Z_EQ_MIN_X;
cparata 0:f27ce43dee4f 7641 break;
cparata 0:f27ce43dee4f 7642 case LSM6DSOX_Z_EQ_MIN_Z:
cparata 0:f27ce43dee4f 7643 *val = LSM6DSOX_Z_EQ_MIN_Z;
cparata 0:f27ce43dee4f 7644 break;
cparata 0:f27ce43dee4f 7645 case LSM6DSOX_Z_EQ_Z:
cparata 0:f27ce43dee4f 7646 *val = LSM6DSOX_Z_EQ_Z;
cparata 0:f27ce43dee4f 7647 break;
cparata 0:f27ce43dee4f 7648 default:
cparata 0:f27ce43dee4f 7649 *val = LSM6DSOX_Z_EQ_Y;
cparata 0:f27ce43dee4f 7650 break;
cparata 0:f27ce43dee4f 7651 }
cparata 0:f27ce43dee4f 7652 return ret;
cparata 0:f27ce43dee4f 7653 }
cparata 0:f27ce43dee4f 7654
cparata 0:f27ce43dee4f 7655 /**
cparata 0:f27ce43dee4f 7656 * @brief Magnetometer Y-axis coordinates
cparata 0:f27ce43dee4f 7657 * rotation (to be aligned to
cparata 0:f27ce43dee4f 7658 * accelerometer/gyroscope axes
cparata 0:f27ce43dee4f 7659 * orientation).[set]
cparata 0:f27ce43dee4f 7660 *
cparata 0:f27ce43dee4f 7661 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7662 * @param val change the values of mag_y_axis in reg MAG_CFG_A
cparata 0:f27ce43dee4f 7663 *
cparata 0:f27ce43dee4f 7664 */
cparata 0:f27ce43dee4f 7665 int32_t lsm6dsox_mag_y_orient_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 7666 lsm6dsox_mag_y_axis_t val)
cparata 0:f27ce43dee4f 7667 {
cparata 0:f27ce43dee4f 7668 lsm6dsox_mag_cfg_a_t reg;
cparata 0:f27ce43dee4f 7669 int32_t ret;
cparata 0:f27ce43dee4f 7670
cparata 0:f27ce43dee4f 7671 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7672 if (ret == 0) {
cparata 0:f27ce43dee4f 7673 reg.mag_y_axis = (uint8_t)val;
cparata 0:f27ce43dee4f 7674 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A,(uint8_t*) &reg);
cparata 0:f27ce43dee4f 7675 }
cparata 0:f27ce43dee4f 7676 return ret;
cparata 0:f27ce43dee4f 7677 }
cparata 0:f27ce43dee4f 7678
cparata 0:f27ce43dee4f 7679 /**
cparata 0:f27ce43dee4f 7680 * @brief Magnetometer Y-axis coordinates
cparata 0:f27ce43dee4f 7681 * rotation (to be aligned to
cparata 0:f27ce43dee4f 7682 * accelerometer/gyroscope axes
cparata 0:f27ce43dee4f 7683 * orientation).[get]
cparata 0:f27ce43dee4f 7684 *
cparata 0:f27ce43dee4f 7685 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7686 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
cparata 0:f27ce43dee4f 7687 *
cparata 0:f27ce43dee4f 7688 */
cparata 0:f27ce43dee4f 7689 int32_t lsm6dsox_mag_y_orient_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 7690 lsm6dsox_mag_y_axis_t *val)
cparata 0:f27ce43dee4f 7691 {
cparata 0:f27ce43dee4f 7692 lsm6dsox_mag_cfg_a_t reg;
cparata 0:f27ce43dee4f 7693 int32_t ret;
cparata 0:f27ce43dee4f 7694
cparata 0:f27ce43dee4f 7695 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7696 switch (reg.mag_y_axis) {
cparata 0:f27ce43dee4f 7697 case LSM6DSOX_Y_EQ_Y:
cparata 0:f27ce43dee4f 7698 *val = LSM6DSOX_Y_EQ_Y;
cparata 0:f27ce43dee4f 7699 break;
cparata 0:f27ce43dee4f 7700 case LSM6DSOX_Y_EQ_MIN_Y:
cparata 0:f27ce43dee4f 7701 *val = LSM6DSOX_Y_EQ_MIN_Y;
cparata 0:f27ce43dee4f 7702 break;
cparata 0:f27ce43dee4f 7703 case LSM6DSOX_Y_EQ_X:
cparata 0:f27ce43dee4f 7704 *val = LSM6DSOX_Y_EQ_X;
cparata 0:f27ce43dee4f 7705 break;
cparata 0:f27ce43dee4f 7706 case LSM6DSOX_Y_EQ_MIN_X:
cparata 0:f27ce43dee4f 7707 *val = LSM6DSOX_Y_EQ_MIN_X;
cparata 0:f27ce43dee4f 7708 break;
cparata 0:f27ce43dee4f 7709 case LSM6DSOX_Y_EQ_MIN_Z:
cparata 0:f27ce43dee4f 7710 *val = LSM6DSOX_Y_EQ_MIN_Z;
cparata 0:f27ce43dee4f 7711 break;
cparata 0:f27ce43dee4f 7712 case LSM6DSOX_Y_EQ_Z:
cparata 0:f27ce43dee4f 7713 *val = LSM6DSOX_Y_EQ_Z;
cparata 0:f27ce43dee4f 7714 break;
cparata 0:f27ce43dee4f 7715 default:
cparata 0:f27ce43dee4f 7716 *val = LSM6DSOX_Y_EQ_Y;
cparata 0:f27ce43dee4f 7717 break;
cparata 0:f27ce43dee4f 7718 }
cparata 0:f27ce43dee4f 7719 return ret;
cparata 0:f27ce43dee4f 7720 }
cparata 0:f27ce43dee4f 7721
cparata 0:f27ce43dee4f 7722 /**
cparata 0:f27ce43dee4f 7723 * @brief Magnetometer X-axis coordinates
cparata 0:f27ce43dee4f 7724 * rotation (to be aligned to
cparata 0:f27ce43dee4f 7725 * accelerometer/gyroscope axes
cparata 0:f27ce43dee4f 7726 * orientation).[set]
cparata 0:f27ce43dee4f 7727 *
cparata 0:f27ce43dee4f 7728 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7729 * @param val change the values of mag_x_axis in reg MAG_CFG_B
cparata 0:f27ce43dee4f 7730 *
cparata 0:f27ce43dee4f 7731 */
cparata 0:f27ce43dee4f 7732 int32_t lsm6dsox_mag_x_orient_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 7733 lsm6dsox_mag_x_axis_t val)
cparata 0:f27ce43dee4f 7734 {
cparata 0:f27ce43dee4f 7735 lsm6dsox_mag_cfg_b_t reg;
cparata 0:f27ce43dee4f 7736 int32_t ret;
cparata 0:f27ce43dee4f 7737
cparata 0:f27ce43dee4f 7738 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7739 if (ret == 0) {
cparata 0:f27ce43dee4f 7740 reg.mag_x_axis = (uint8_t)val;
cparata 0:f27ce43dee4f 7741 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7742 }
cparata 0:f27ce43dee4f 7743 return ret;
cparata 0:f27ce43dee4f 7744 }
cparata 0:f27ce43dee4f 7745
cparata 0:f27ce43dee4f 7746 /**
cparata 0:f27ce43dee4f 7747 * @brief Magnetometer X-axis coordinates
cparata 0:f27ce43dee4f 7748 * rotation (to be aligned to
cparata 0:f27ce43dee4f 7749 * accelerometer/gyroscope axes
cparata 0:f27ce43dee4f 7750 * orientation).[get]
cparata 0:f27ce43dee4f 7751 *
cparata 0:f27ce43dee4f 7752 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7753 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
cparata 0:f27ce43dee4f 7754 *
cparata 0:f27ce43dee4f 7755 */
cparata 0:f27ce43dee4f 7756 int32_t lsm6dsox_mag_x_orient_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 7757 lsm6dsox_mag_x_axis_t *val)
cparata 0:f27ce43dee4f 7758 {
cparata 0:f27ce43dee4f 7759 lsm6dsox_mag_cfg_b_t reg;
cparata 0:f27ce43dee4f 7760 int32_t ret;
cparata 0:f27ce43dee4f 7761
cparata 0:f27ce43dee4f 7762 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)&reg);
cparata 0:f27ce43dee4f 7763 switch (reg.mag_x_axis) {
cparata 0:f27ce43dee4f 7764 case LSM6DSOX_X_EQ_Y:
cparata 0:f27ce43dee4f 7765 *val = LSM6DSOX_X_EQ_Y;
cparata 0:f27ce43dee4f 7766 break;
cparata 0:f27ce43dee4f 7767 case LSM6DSOX_X_EQ_MIN_Y:
cparata 0:f27ce43dee4f 7768 *val = LSM6DSOX_X_EQ_MIN_Y;
cparata 0:f27ce43dee4f 7769 break;
cparata 0:f27ce43dee4f 7770 case LSM6DSOX_X_EQ_X:
cparata 0:f27ce43dee4f 7771 *val = LSM6DSOX_X_EQ_X;
cparata 0:f27ce43dee4f 7772 break;
cparata 0:f27ce43dee4f 7773 case LSM6DSOX_X_EQ_MIN_X:
cparata 0:f27ce43dee4f 7774 *val = LSM6DSOX_X_EQ_MIN_X;
cparata 0:f27ce43dee4f 7775 break;
cparata 0:f27ce43dee4f 7776 case LSM6DSOX_X_EQ_MIN_Z:
cparata 0:f27ce43dee4f 7777 *val = LSM6DSOX_X_EQ_MIN_Z;
cparata 0:f27ce43dee4f 7778 break;
cparata 0:f27ce43dee4f 7779 case LSM6DSOX_X_EQ_Z:
cparata 0:f27ce43dee4f 7780 *val = LSM6DSOX_X_EQ_Z;
cparata 0:f27ce43dee4f 7781 break;
cparata 0:f27ce43dee4f 7782 default:
cparata 0:f27ce43dee4f 7783 *val = LSM6DSOX_X_EQ_Y;
cparata 0:f27ce43dee4f 7784 break;
cparata 0:f27ce43dee4f 7785 }
cparata 0:f27ce43dee4f 7786 return ret;
cparata 0:f27ce43dee4f 7787 }
cparata 0:f27ce43dee4f 7788
cparata 0:f27ce43dee4f 7789 /**
cparata 0:f27ce43dee4f 7790 * @}
cparata 0:f27ce43dee4f 7791 *
cparata 0:f27ce43dee4f 7792 */
cparata 0:f27ce43dee4f 7793
cparata 0:f27ce43dee4f 7794 /**
cparata 0:f27ce43dee4f 7795 * @defgroup LSM6DSOX_significant_motion
cparata 0:f27ce43dee4f 7796 * @brief This section groups all the functions that manage the
cparata 0:f27ce43dee4f 7797 * state_machine.
cparata 0:f27ce43dee4f 7798 * @{
cparata 0:f27ce43dee4f 7799 *
cparata 0:f27ce43dee4f 7800 */
cparata 0:f27ce43dee4f 7801
cparata 0:f27ce43dee4f 7802 /**
cparata 0:f27ce43dee4f 7803 * @brief Interrupt status bit for FSM long counter
cparata 0:f27ce43dee4f 7804 * timeout interrupt event.[get]
cparata 0:f27ce43dee4f 7805 *
cparata 0:f27ce43dee4f 7806 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7807 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
cparata 0:f27ce43dee4f 7808 *
cparata 0:f27ce43dee4f 7809 */
cparata 0:f27ce43dee4f 7810 int32_t lsm6dsox_long_cnt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 7811 {
cparata 0:f27ce43dee4f 7812 lsm6dsox_emb_func_status_t reg;
cparata 0:f27ce43dee4f 7813 int32_t ret;
cparata 0:f27ce43dee4f 7814
cparata 0:f27ce43dee4f 7815 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7816 if (ret == 0) {
cparata 0:f27ce43dee4f 7817 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7818 }
cparata 0:f27ce43dee4f 7819 if (ret == 0) {
cparata 0:f27ce43dee4f 7820 *val = reg.is_fsm_lc;
cparata 0:f27ce43dee4f 7821 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7822 }
cparata 0:f27ce43dee4f 7823 return ret;
cparata 0:f27ce43dee4f 7824 }
cparata 0:f27ce43dee4f 7825
cparata 0:f27ce43dee4f 7826 /**
cparata 0:f27ce43dee4f 7827 * @brief Finite State Machine global enable.[set]
cparata 0:f27ce43dee4f 7828 *
cparata 0:f27ce43dee4f 7829 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7830 * @param val change the values of fsm_en in reg EMB_FUNC_EN_B
cparata 0:f27ce43dee4f 7831 *
cparata 0:f27ce43dee4f 7832 */
cparata 0:f27ce43dee4f 7833 int32_t lsm6dsox_emb_fsm_en_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 7834 {
cparata 0:f27ce43dee4f 7835 int32_t ret;
cparata 0:f27ce43dee4f 7836 lsm6dsox_emb_func_en_b_t reg;
cparata 0:f27ce43dee4f 7837
cparata 0:f27ce43dee4f 7838 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7839 if (ret == 0) {
cparata 0:f27ce43dee4f 7840 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7841 }
cparata 0:f27ce43dee4f 7842 if (ret == 0) {
cparata 0:f27ce43dee4f 7843 reg.fsm_en = val;
cparata 0:f27ce43dee4f 7844 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7845 }
cparata 0:f27ce43dee4f 7846 if (ret == 0) {
cparata 0:f27ce43dee4f 7847 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7848 }
cparata 0:f27ce43dee4f 7849 return ret;
cparata 0:f27ce43dee4f 7850 }
cparata 0:f27ce43dee4f 7851
cparata 0:f27ce43dee4f 7852 /**
cparata 0:f27ce43dee4f 7853 * @brief Finite State Machine global enable.[get]
cparata 0:f27ce43dee4f 7854 *
cparata 0:f27ce43dee4f 7855 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7856 * @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B
cparata 0:f27ce43dee4f 7857 *
cparata 0:f27ce43dee4f 7858 */
cparata 0:f27ce43dee4f 7859 int32_t lsm6dsox_emb_fsm_en_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 7860 {
cparata 0:f27ce43dee4f 7861 int32_t ret;
cparata 0:f27ce43dee4f 7862 lsm6dsox_emb_func_en_b_t reg;
cparata 0:f27ce43dee4f 7863
cparata 0:f27ce43dee4f 7864 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7865 if (ret == 0) {
cparata 0:f27ce43dee4f 7866 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7867 }
cparata 0:f27ce43dee4f 7868 if (ret == 0) {
cparata 0:f27ce43dee4f 7869 *val = reg.fsm_en;
cparata 0:f27ce43dee4f 7870 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7871 }
cparata 0:f27ce43dee4f 7872 if (ret == 0) {
cparata 0:f27ce43dee4f 7873 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7874 }
cparata 0:f27ce43dee4f 7875
cparata 0:f27ce43dee4f 7876 return ret;
cparata 0:f27ce43dee4f 7877 }
cparata 0:f27ce43dee4f 7878
cparata 0:f27ce43dee4f 7879 /**
cparata 0:f27ce43dee4f 7880 * @brief Finite State Machine enable.[set]
cparata 0:f27ce43dee4f 7881 *
cparata 0:f27ce43dee4f 7882 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7883 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata 0:f27ce43dee4f 7884 *
cparata 0:f27ce43dee4f 7885 */
cparata 0:f27ce43dee4f 7886 int32_t lsm6dsox_fsm_enable_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 7887 lsm6dsox_emb_fsm_enable_t *val)
cparata 0:f27ce43dee4f 7888 {
cparata 0:f27ce43dee4f 7889 int32_t ret;
cparata 0:f27ce43dee4f 7890 lsm6dsox_emb_func_en_b_t reg;
cparata 0:f27ce43dee4f 7891
cparata 0:f27ce43dee4f 7892
cparata 0:f27ce43dee4f 7893 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7894 if (ret == 0) {
cparata 0:f27ce43dee4f 7895 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_A,
cparata 0:f27ce43dee4f 7896 (uint8_t*)&val->fsm_enable_a, 1);
cparata 0:f27ce43dee4f 7897 }
cparata 0:f27ce43dee4f 7898 if (ret == 0) {
cparata 0:f27ce43dee4f 7899 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_B,
cparata 0:f27ce43dee4f 7900 (uint8_t*)&val->fsm_enable_b, 1);
cparata 0:f27ce43dee4f 7901 }
cparata 0:f27ce43dee4f 7902 if (ret == 0) {
cparata 0:f27ce43dee4f 7903 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
cparata 0:f27ce43dee4f 7904 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7905 }
cparata 0:f27ce43dee4f 7906 if (ret == 0) {
cparata 0:f27ce43dee4f 7907 if ( (val->fsm_enable_a.fsm1_en |
cparata 0:f27ce43dee4f 7908 val->fsm_enable_a.fsm2_en |
cparata 0:f27ce43dee4f 7909 val->fsm_enable_a.fsm3_en |
cparata 0:f27ce43dee4f 7910 val->fsm_enable_a.fsm4_en |
cparata 0:f27ce43dee4f 7911 val->fsm_enable_a.fsm5_en |
cparata 0:f27ce43dee4f 7912 val->fsm_enable_a.fsm6_en |
cparata 0:f27ce43dee4f 7913 val->fsm_enable_a.fsm7_en |
cparata 0:f27ce43dee4f 7914 val->fsm_enable_a.fsm8_en |
cparata 0:f27ce43dee4f 7915 val->fsm_enable_b.fsm9_en |
cparata 0:f27ce43dee4f 7916 val->fsm_enable_b.fsm10_en |
cparata 0:f27ce43dee4f 7917 val->fsm_enable_b.fsm11_en |
cparata 0:f27ce43dee4f 7918 val->fsm_enable_b.fsm12_en |
cparata 0:f27ce43dee4f 7919 val->fsm_enable_b.fsm13_en |
cparata 0:f27ce43dee4f 7920 val->fsm_enable_b.fsm14_en |
cparata 0:f27ce43dee4f 7921 val->fsm_enable_b.fsm15_en |
cparata 0:f27ce43dee4f 7922 val->fsm_enable_b.fsm16_en )
cparata 0:f27ce43dee4f 7923 != PROPERTY_DISABLE){
cparata 0:f27ce43dee4f 7924 reg.fsm_en = PROPERTY_ENABLE;
cparata 0:f27ce43dee4f 7925 }
cparata 0:f27ce43dee4f 7926 else{
cparata 0:f27ce43dee4f 7927 reg.fsm_en = PROPERTY_DISABLE;
cparata 0:f27ce43dee4f 7928 }
cparata 0:f27ce43dee4f 7929
cparata 0:f27ce43dee4f 7930 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 7931 }
cparata 0:f27ce43dee4f 7932 if (ret == 0) {
cparata 0:f27ce43dee4f 7933 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7934 }
cparata 0:f27ce43dee4f 7935
cparata 0:f27ce43dee4f 7936 return ret;
cparata 0:f27ce43dee4f 7937 }
cparata 0:f27ce43dee4f 7938
cparata 0:f27ce43dee4f 7939 /**
cparata 0:f27ce43dee4f 7940 * @brief Finite State Machine enable.[get]
cparata 0:f27ce43dee4f 7941 *
cparata 0:f27ce43dee4f 7942 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7943 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata 0:f27ce43dee4f 7944 *
cparata 0:f27ce43dee4f 7945 */
cparata 0:f27ce43dee4f 7946 int32_t lsm6dsox_fsm_enable_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 7947 lsm6dsox_emb_fsm_enable_t *val)
cparata 0:f27ce43dee4f 7948 {
cparata 0:f27ce43dee4f 7949 int32_t ret;
cparata 0:f27ce43dee4f 7950
cparata 0:f27ce43dee4f 7951 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7952 if (ret == 0) {
cparata 0:f27ce43dee4f 7953 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, (uint8_t*) val, 2);
cparata 0:f27ce43dee4f 7954 }
cparata 0:f27ce43dee4f 7955 if (ret == 0) {
cparata 0:f27ce43dee4f 7956 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7957 }
cparata 0:f27ce43dee4f 7958 return ret;
cparata 0:f27ce43dee4f 7959 }
cparata 0:f27ce43dee4f 7960
cparata 0:f27ce43dee4f 7961 /**
cparata 0:f27ce43dee4f 7962 * @brief FSM long counter status register. Long counter value is an
cparata 0:f27ce43dee4f 7963 * unsigned integer value (16-bit format).[set]
cparata 0:f27ce43dee4f 7964 *
cparata 0:f27ce43dee4f 7965 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7966 * @param buff buffer that contains data to write
cparata 0:f27ce43dee4f 7967 *
cparata 0:f27ce43dee4f 7968 */
cparata 0:f27ce43dee4f 7969 int32_t lsm6dsox_long_cnt_set(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7970 {
cparata 0:f27ce43dee4f 7971 int32_t ret;
cparata 0:f27ce43dee4f 7972
cparata 0:f27ce43dee4f 7973 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7974 if (ret == 0) {
cparata 0:f27ce43dee4f 7975 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2);
cparata 0:f27ce43dee4f 7976 }
cparata 0:f27ce43dee4f 7977 if (ret == 0) {
cparata 0:f27ce43dee4f 7978 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 7979 }
cparata 0:f27ce43dee4f 7980
cparata 0:f27ce43dee4f 7981 return ret;
cparata 0:f27ce43dee4f 7982 }
cparata 0:f27ce43dee4f 7983
cparata 0:f27ce43dee4f 7984 /**
cparata 0:f27ce43dee4f 7985 * @brief FSM long counter status register. Long counter value is an
cparata 0:f27ce43dee4f 7986 * unsigned integer value (16-bit format).[get]
cparata 0:f27ce43dee4f 7987 *
cparata 0:f27ce43dee4f 7988 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 7989 * @param buff buffer that stores data read
cparata 0:f27ce43dee4f 7990 *
cparata 0:f27ce43dee4f 7991 */
cparata 0:f27ce43dee4f 7992 int32_t lsm6dsox_long_cnt_get(lsm6dsox_ctx_t *ctx, uint8_t *buff)
cparata 0:f27ce43dee4f 7993 {
cparata 0:f27ce43dee4f 7994 int32_t ret;
cparata 0:f27ce43dee4f 7995
cparata 0:f27ce43dee4f 7996 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 7997 if (ret == 0) {
cparata 0:f27ce43dee4f 7998 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2);
cparata 0:f27ce43dee4f 7999 }
cparata 0:f27ce43dee4f 8000 if (ret == 0) {
cparata 0:f27ce43dee4f 8001 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8002 }
cparata 0:f27ce43dee4f 8003
cparata 0:f27ce43dee4f 8004 return ret;
cparata 0:f27ce43dee4f 8005 }
cparata 0:f27ce43dee4f 8006
cparata 0:f27ce43dee4f 8007 /**
cparata 0:f27ce43dee4f 8008 * @brief Clear FSM long counter value.[set]
cparata 0:f27ce43dee4f 8009 *
cparata 0:f27ce43dee4f 8010 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8011 * @param val change the values of fsm_lc_clr in
cparata 0:f27ce43dee4f 8012 * reg FSM_LONG_COUNTER_CLEAR
cparata 0:f27ce43dee4f 8013 *
cparata 0:f27ce43dee4f 8014 */
cparata 0:f27ce43dee4f 8015 int32_t lsm6dsox_long_clr_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val)
cparata 0:f27ce43dee4f 8016 {
cparata 0:f27ce43dee4f 8017 lsm6dsox_fsm_long_counter_clear_t reg;
cparata 0:f27ce43dee4f 8018 int32_t ret;
cparata 0:f27ce43dee4f 8019
cparata 0:f27ce43dee4f 8020 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8021 if (ret == 0) {
cparata 0:f27ce43dee4f 8022 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
cparata 0:f27ce43dee4f 8023 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8024 }
cparata 0:f27ce43dee4f 8025 if (ret == 0) {
cparata 0:f27ce43dee4f 8026 reg. fsm_lc_clr = (uint8_t)val;
cparata 0:f27ce43dee4f 8027 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
cparata 0:f27ce43dee4f 8028 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8029 }
cparata 0:f27ce43dee4f 8030 if (ret == 0) {
cparata 0:f27ce43dee4f 8031 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8032 }
cparata 0:f27ce43dee4f 8033 return ret;
cparata 0:f27ce43dee4f 8034 }
cparata 0:f27ce43dee4f 8035
cparata 0:f27ce43dee4f 8036 /**
cparata 0:f27ce43dee4f 8037 * @brief Clear FSM long counter value.[get]
cparata 0:f27ce43dee4f 8038 *
cparata 0:f27ce43dee4f 8039 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8040 * @param val Get the values of fsm_lc_clr in
cparata 0:f27ce43dee4f 8041 * reg FSM_LONG_COUNTER_CLEAR
cparata 0:f27ce43dee4f 8042 *
cparata 0:f27ce43dee4f 8043 */
cparata 0:f27ce43dee4f 8044 int32_t lsm6dsox_long_clr_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val)
cparata 0:f27ce43dee4f 8045 {
cparata 0:f27ce43dee4f 8046 lsm6dsox_fsm_long_counter_clear_t reg;
cparata 0:f27ce43dee4f 8047 int32_t ret;
cparata 0:f27ce43dee4f 8048
cparata 0:f27ce43dee4f 8049 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8050 if (ret == 0) {
cparata 0:f27ce43dee4f 8051 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
cparata 0:f27ce43dee4f 8052 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8053 }
cparata 0:f27ce43dee4f 8054 if (ret == 0) {
cparata 0:f27ce43dee4f 8055 switch (reg.fsm_lc_clr) {
cparata 0:f27ce43dee4f 8056 case LSM6DSOX_LC_NORMAL:
cparata 0:f27ce43dee4f 8057 *val = LSM6DSOX_LC_NORMAL;
cparata 0:f27ce43dee4f 8058 break;
cparata 0:f27ce43dee4f 8059 case LSM6DSOX_LC_CLEAR:
cparata 0:f27ce43dee4f 8060 *val = LSM6DSOX_LC_CLEAR;
cparata 0:f27ce43dee4f 8061 break;
cparata 0:f27ce43dee4f 8062 case LSM6DSOX_LC_CLEAR_DONE:
cparata 0:f27ce43dee4f 8063 *val = LSM6DSOX_LC_CLEAR_DONE;
cparata 0:f27ce43dee4f 8064 break;
cparata 0:f27ce43dee4f 8065 default:
cparata 0:f27ce43dee4f 8066 *val = LSM6DSOX_LC_NORMAL;
cparata 0:f27ce43dee4f 8067 break;
cparata 0:f27ce43dee4f 8068 }
cparata 0:f27ce43dee4f 8069 }
cparata 0:f27ce43dee4f 8070
cparata 0:f27ce43dee4f 8071 if (ret == 0) {
cparata 0:f27ce43dee4f 8072 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8073 }
cparata 0:f27ce43dee4f 8074
cparata 0:f27ce43dee4f 8075 return ret;
cparata 0:f27ce43dee4f 8076 }
cparata 0:f27ce43dee4f 8077
cparata 0:f27ce43dee4f 8078 /**
cparata 0:f27ce43dee4f 8079 * @brief FSM output registers[get]
cparata 0:f27ce43dee4f 8080 *
cparata 0:f27ce43dee4f 8081 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8082 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
cparata 0:f27ce43dee4f 8083 *
cparata 0:f27ce43dee4f 8084 */
cparata 0:f27ce43dee4f 8085 int32_t lsm6dsox_fsm_out_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_out_t *val)
cparata 0:f27ce43dee4f 8086 {
cparata 0:f27ce43dee4f 8087 int32_t ret;
cparata 0:f27ce43dee4f 8088
cparata 0:f27ce43dee4f 8089 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8090 if (ret == 0) {
cparata 0:f27ce43dee4f 8091 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_OUTS1, (uint8_t*)val, 16);
cparata 0:f27ce43dee4f 8092 }
cparata 0:f27ce43dee4f 8093 if (ret == 0) {
cparata 0:f27ce43dee4f 8094 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8095 }
cparata 0:f27ce43dee4f 8096
cparata 0:f27ce43dee4f 8097 return ret;
cparata 0:f27ce43dee4f 8098 }
cparata 0:f27ce43dee4f 8099
cparata 0:f27ce43dee4f 8100 /**
cparata 0:f27ce43dee4f 8101 * @brief Finite State Machine ODR configuration.[set]
cparata 0:f27ce43dee4f 8102 *
cparata 0:f27ce43dee4f 8103 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8104 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata 0:f27ce43dee4f 8105 *
cparata 0:f27ce43dee4f 8106 */
cparata 0:f27ce43dee4f 8107 int32_t lsm6dsox_fsm_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t val)
cparata 0:f27ce43dee4f 8108 {
cparata 0:f27ce43dee4f 8109 lsm6dsox_emb_func_odr_cfg_b_t reg;
cparata 0:f27ce43dee4f 8110 int32_t ret;
cparata 0:f27ce43dee4f 8111
cparata 0:f27ce43dee4f 8112 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8113 if (ret == 0) {
cparata 0:f27ce43dee4f 8114 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
cparata 0:f27ce43dee4f 8115 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8116 }
cparata 0:f27ce43dee4f 8117 if (ret == 0) {
cparata 0:f27ce43dee4f 8118 reg.not_used_01 = 3; /* set default values */
cparata 0:f27ce43dee4f 8119 reg.not_used_02 = 2; /* set default values */
cparata 0:f27ce43dee4f 8120 reg.fsm_odr = (uint8_t)val;
cparata 0:f27ce43dee4f 8121 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
cparata 0:f27ce43dee4f 8122 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8123 }
cparata 0:f27ce43dee4f 8124 if (ret == 0) {
cparata 0:f27ce43dee4f 8125 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8126 }
cparata 0:f27ce43dee4f 8127 return ret;
cparata 0:f27ce43dee4f 8128 }
cparata 0:f27ce43dee4f 8129
cparata 0:f27ce43dee4f 8130 /**
cparata 0:f27ce43dee4f 8131 * @brief Finite State Machine ODR configuration.[get]
cparata 0:f27ce43dee4f 8132 *
cparata 0:f27ce43dee4f 8133 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8134 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata 0:f27ce43dee4f 8135 *
cparata 0:f27ce43dee4f 8136 */
cparata 0:f27ce43dee4f 8137 int32_t lsm6dsox_fsm_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t *val)
cparata 0:f27ce43dee4f 8138 {
cparata 0:f27ce43dee4f 8139 lsm6dsox_emb_func_odr_cfg_b_t reg;
cparata 0:f27ce43dee4f 8140 int32_t ret;
cparata 0:f27ce43dee4f 8141
cparata 0:f27ce43dee4f 8142 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8143 if (ret == 0) {
cparata 0:f27ce43dee4f 8144 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
cparata 0:f27ce43dee4f 8145 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8146 }
cparata 0:f27ce43dee4f 8147 if (ret == 0) {
cparata 0:f27ce43dee4f 8148 switch (reg.fsm_odr) {
cparata 0:f27ce43dee4f 8149 case LSM6DSOX_ODR_FSM_12Hz5:
cparata 0:f27ce43dee4f 8150 *val = LSM6DSOX_ODR_FSM_12Hz5;
cparata 0:f27ce43dee4f 8151 break;
cparata 0:f27ce43dee4f 8152 case LSM6DSOX_ODR_FSM_26Hz:
cparata 0:f27ce43dee4f 8153 *val = LSM6DSOX_ODR_FSM_26Hz;
cparata 0:f27ce43dee4f 8154 break;
cparata 0:f27ce43dee4f 8155 case LSM6DSOX_ODR_FSM_52Hz:
cparata 0:f27ce43dee4f 8156 *val = LSM6DSOX_ODR_FSM_52Hz;
cparata 0:f27ce43dee4f 8157 break;
cparata 0:f27ce43dee4f 8158 case LSM6DSOX_ODR_FSM_104Hz:
cparata 0:f27ce43dee4f 8159 *val = LSM6DSOX_ODR_FSM_104Hz;
cparata 0:f27ce43dee4f 8160 break;
cparata 0:f27ce43dee4f 8161 default:
cparata 0:f27ce43dee4f 8162 *val = LSM6DSOX_ODR_FSM_12Hz5;
cparata 0:f27ce43dee4f 8163 break;
cparata 0:f27ce43dee4f 8164 }
cparata 0:f27ce43dee4f 8165 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8166 }
cparata 0:f27ce43dee4f 8167
cparata 0:f27ce43dee4f 8168 return ret;
cparata 0:f27ce43dee4f 8169 }
cparata 0:f27ce43dee4f 8170
cparata 0:f27ce43dee4f 8171 /**
cparata 0:f27ce43dee4f 8172 * @brief FSM initialization request.[set]
cparata 0:f27ce43dee4f 8173 *
cparata 0:f27ce43dee4f 8174 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8175 * @param val change the values of fsm_init in reg FSM_INIT
cparata 0:f27ce43dee4f 8176 *
cparata 0:f27ce43dee4f 8177 */
cparata 0:f27ce43dee4f 8178 int32_t lsm6dsox_fsm_init_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 8179 {
cparata 0:f27ce43dee4f 8180 lsm6dsox_emb_func_init_b_t reg;
cparata 0:f27ce43dee4f 8181 int32_t ret;
cparata 0:f27ce43dee4f 8182
cparata 0:f27ce43dee4f 8183 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8184 if (ret == 0) {
cparata 0:f27ce43dee4f 8185 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8186 }
cparata 0:f27ce43dee4f 8187 if (ret == 0) {
cparata 0:f27ce43dee4f 8188 reg.fsm_init = val;
cparata 0:f27ce43dee4f 8189 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8190 }
cparata 0:f27ce43dee4f 8191 if (ret == 0) {
cparata 0:f27ce43dee4f 8192 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8193 }
cparata 0:f27ce43dee4f 8194
cparata 0:f27ce43dee4f 8195 return ret;
cparata 0:f27ce43dee4f 8196 }
cparata 0:f27ce43dee4f 8197
cparata 0:f27ce43dee4f 8198 /**
cparata 0:f27ce43dee4f 8199 * @brief FSM initialization request.[get]
cparata 0:f27ce43dee4f 8200 *
cparata 0:f27ce43dee4f 8201 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8202 * @param val change the values of fsm_init in reg FSM_INIT
cparata 0:f27ce43dee4f 8203 *
cparata 0:f27ce43dee4f 8204 */
cparata 0:f27ce43dee4f 8205 int32_t lsm6dsox_fsm_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 8206 {
cparata 0:f27ce43dee4f 8207 lsm6dsox_emb_func_init_b_t reg;
cparata 0:f27ce43dee4f 8208 int32_t ret;
cparata 0:f27ce43dee4f 8209
cparata 0:f27ce43dee4f 8210 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8211 if (ret == 0) {
cparata 0:f27ce43dee4f 8212 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8213 }
cparata 0:f27ce43dee4f 8214 if (ret == 0) {
cparata 0:f27ce43dee4f 8215 *val = reg.fsm_init;
cparata 0:f27ce43dee4f 8216 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8217 }
cparata 0:f27ce43dee4f 8218 return ret;
cparata 0:f27ce43dee4f 8219 }
cparata 0:f27ce43dee4f 8220
cparata 0:f27ce43dee4f 8221 /**
cparata 0:f27ce43dee4f 8222 * @brief FSM long counter timeout register (r/w). The long counter
cparata 0:f27ce43dee4f 8223 * timeout value is an unsigned integer value (16-bit format).
cparata 0:f27ce43dee4f 8224 * When the long counter value reached this value,
cparata 0:f27ce43dee4f 8225 * the FSM generates an interrupt.[set]
cparata 0:f27ce43dee4f 8226 *
cparata 0:f27ce43dee4f 8227 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8228 * @param val the value of long counter
cparata 0:f27ce43dee4f 8229 *
cparata 0:f27ce43dee4f 8230 */
cparata 0:f27ce43dee4f 8231 int32_t lsm6dsox_long_cnt_int_value_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata 0:f27ce43dee4f 8232 {
cparata 0:f27ce43dee4f 8233 int32_t ret;
cparata 0:f27ce43dee4f 8234 uint8_t add_l;
cparata 0:f27ce43dee4f 8235 uint8_t add_h;
cparata 0:f27ce43dee4f 8236
cparata 0:f27ce43dee4f 8237 add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
cparata 0:f27ce43dee4f 8238 add_l = (uint8_t)( val & 0x00FFU );
cparata 0:f27ce43dee4f 8239
cparata 0:f27ce43dee4f 8240 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l);
cparata 0:f27ce43dee4f 8241 if (ret == 0) {
cparata 0:f27ce43dee4f 8242 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h);
cparata 0:f27ce43dee4f 8243 }
cparata 0:f27ce43dee4f 8244
cparata 0:f27ce43dee4f 8245 return ret;
cparata 0:f27ce43dee4f 8246 }
cparata 0:f27ce43dee4f 8247
cparata 0:f27ce43dee4f 8248 /**
cparata 0:f27ce43dee4f 8249 * @brief FSM long counter timeout register (r/w). The long counter
cparata 0:f27ce43dee4f 8250 * timeout value is an unsigned integer value (16-bit format).
cparata 0:f27ce43dee4f 8251 * When the long counter value reached this value,
cparata 0:f27ce43dee4f 8252 * the FSM generates an interrupt.[get]
cparata 0:f27ce43dee4f 8253 *
cparata 0:f27ce43dee4f 8254 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8255 * @param val buffer that stores the value of long counter
cparata 0:f27ce43dee4f 8256 *
cparata 0:f27ce43dee4f 8257 */
cparata 0:f27ce43dee4f 8258 int32_t lsm6dsox_long_cnt_int_value_get(lsm6dsox_ctx_t *ctx, uint16_t *val)
cparata 0:f27ce43dee4f 8259 {
cparata 0:f27ce43dee4f 8260 int32_t ret;
cparata 0:f27ce43dee4f 8261 uint8_t add_l;
cparata 0:f27ce43dee4f 8262 uint8_t add_h;
cparata 0:f27ce43dee4f 8263
cparata 0:f27ce43dee4f 8264 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l);
cparata 0:f27ce43dee4f 8265 if (ret == 0) {
cparata 0:f27ce43dee4f 8266 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h);
cparata 0:f27ce43dee4f 8267 *val = add_h;
cparata 0:f27ce43dee4f 8268 *val = *val << 8;
cparata 0:f27ce43dee4f 8269 *val += add_l;
cparata 0:f27ce43dee4f 8270 }
cparata 0:f27ce43dee4f 8271
cparata 0:f27ce43dee4f 8272 return ret;
cparata 0:f27ce43dee4f 8273 }
cparata 0:f27ce43dee4f 8274
cparata 0:f27ce43dee4f 8275 /**
cparata 0:f27ce43dee4f 8276 * @brief FSM number of programs register.[set]
cparata 0:f27ce43dee4f 8277 *
cparata 0:f27ce43dee4f 8278 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8279 * @param val value to write
cparata 0:f27ce43dee4f 8280 *
cparata 0:f27ce43dee4f 8281 */
cparata 0:f27ce43dee4f 8282 int32_t lsm6dsox_fsm_number_of_programs_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 8283 {
cparata 0:f27ce43dee4f 8284 int32_t ret;
cparata 0:f27ce43dee4f 8285
cparata 0:f27ce43dee4f 8286 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_PROGRAMS, &val);
cparata 0:f27ce43dee4f 8287
cparata 0:f27ce43dee4f 8288 return ret;
cparata 0:f27ce43dee4f 8289 }
cparata 0:f27ce43dee4f 8290
cparata 0:f27ce43dee4f 8291 /**
cparata 0:f27ce43dee4f 8292 * @brief FSM number of programs register.[get]
cparata 0:f27ce43dee4f 8293 *
cparata 0:f27ce43dee4f 8294 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8295 * @param val buffer that stores data read.
cparata 0:f27ce43dee4f 8296 *
cparata 0:f27ce43dee4f 8297 */
cparata 0:f27ce43dee4f 8298 int32_t lsm6dsox_fsm_number_of_programs_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 8299 {
cparata 0:f27ce43dee4f 8300 int32_t ret;
cparata 0:f27ce43dee4f 8301
cparata 0:f27ce43dee4f 8302 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_PROGRAMS, val);
cparata 0:f27ce43dee4f 8303
cparata 0:f27ce43dee4f 8304 return ret;
cparata 0:f27ce43dee4f 8305 }
cparata 0:f27ce43dee4f 8306
cparata 0:f27ce43dee4f 8307 /**
cparata 0:f27ce43dee4f 8308 * @brief FSM start address register (r/w).
cparata 0:f27ce43dee4f 8309 * First available address is 0x033C.[set]
cparata 0:f27ce43dee4f 8310 *
cparata 0:f27ce43dee4f 8311 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8312 * @param val the value of start address
cparata 0:f27ce43dee4f 8313 *
cparata 0:f27ce43dee4f 8314 */
cparata 0:f27ce43dee4f 8315 int32_t lsm6dsox_fsm_start_address_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata 0:f27ce43dee4f 8316 {
cparata 0:f27ce43dee4f 8317 int32_t ret;
cparata 0:f27ce43dee4f 8318 uint8_t add_l;
cparata 0:f27ce43dee4f 8319 uint8_t add_h;
cparata 0:f27ce43dee4f 8320
cparata 0:f27ce43dee4f 8321 add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
cparata 0:f27ce43dee4f 8322 add_l = (uint8_t)( val & 0x00FFU );
cparata 0:f27ce43dee4f 8323
cparata 0:f27ce43dee4f 8324 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l);
cparata 0:f27ce43dee4f 8325 if (ret == 0) {
cparata 0:f27ce43dee4f 8326 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h);
cparata 0:f27ce43dee4f 8327 }
cparata 0:f27ce43dee4f 8328 return ret;
cparata 0:f27ce43dee4f 8329 }
cparata 0:f27ce43dee4f 8330
cparata 0:f27ce43dee4f 8331 /**
cparata 0:f27ce43dee4f 8332 * @brief FSM start address register (r/w).
cparata 0:f27ce43dee4f 8333 * First available address is 0x033C.[get]
cparata 0:f27ce43dee4f 8334 *
cparata 0:f27ce43dee4f 8335 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8336 * @param val buffer the value of start address.
cparata 0:f27ce43dee4f 8337 *
cparata 0:f27ce43dee4f 8338 */
cparata 0:f27ce43dee4f 8339 int32_t lsm6dsox_fsm_start_address_get(lsm6dsox_ctx_t *ctx, uint16_t *val)
cparata 0:f27ce43dee4f 8340 {
cparata 0:f27ce43dee4f 8341 int32_t ret;
cparata 0:f27ce43dee4f 8342 uint8_t add_l;
cparata 0:f27ce43dee4f 8343 uint8_t add_h;
cparata 0:f27ce43dee4f 8344
cparata 0:f27ce43dee4f 8345 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l);
cparata 0:f27ce43dee4f 8346 if (ret == 0) {
cparata 0:f27ce43dee4f 8347 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h);
cparata 0:f27ce43dee4f 8348 *val = add_h;
cparata 0:f27ce43dee4f 8349 *val = *val << 8;
cparata 0:f27ce43dee4f 8350 *val += add_l;
cparata 0:f27ce43dee4f 8351 }
cparata 0:f27ce43dee4f 8352 return ret;
cparata 0:f27ce43dee4f 8353 }
cparata 0:f27ce43dee4f 8354
cparata 0:f27ce43dee4f 8355 /**
cparata 0:f27ce43dee4f 8356 * @}
cparata 0:f27ce43dee4f 8357 *
cparata 0:f27ce43dee4f 8358 */
cparata 0:f27ce43dee4f 8359
cparata 0:f27ce43dee4f 8360 /**
cparata 0:f27ce43dee4f 8361 * @addtogroup Machine Learning Core
cparata 0:f27ce43dee4f 8362 * @brief This section group all the functions concerning the
cparata 0:f27ce43dee4f 8363 * usage of Machine Learning Core
cparata 0:f27ce43dee4f 8364 * @{
cparata 0:f27ce43dee4f 8365 *
cparata 0:f27ce43dee4f 8366 */
cparata 0:f27ce43dee4f 8367
cparata 0:f27ce43dee4f 8368 /**
cparata 0:f27ce43dee4f 8369 * @brief Enable Machine Learning Core.[set]
cparata 0:f27ce43dee4f 8370 *
cparata 0:f27ce43dee4f 8371 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8372 * @param val change the values of mlc_en in
cparata 0:f27ce43dee4f 8373 * reg EMB_FUNC_EN_B and mlc_init
cparata 0:f27ce43dee4f 8374 * in EMB_FUNC_INIT_B
cparata 0:f27ce43dee4f 8375 *
cparata 0:f27ce43dee4f 8376 */
cparata 0:f27ce43dee4f 8377 int32_t lsm6dsox_mlc_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 8378 {
cparata 0:f27ce43dee4f 8379 lsm6dsox_emb_func_en_b_t reg;
cparata 0:f27ce43dee4f 8380 int32_t ret;
cparata 0:f27ce43dee4f 8381
cparata 0:f27ce43dee4f 8382 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8383 if (ret == 0) {
cparata 0:f27ce43dee4f 8384 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8385 }
cparata 0:f27ce43dee4f 8386 if (ret == 0) {
cparata 0:f27ce43dee4f 8387 reg.mlc_en = val;
cparata 0:f27ce43dee4f 8388 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8389 }
cparata 0:f27ce43dee4f 8390 if ((val != PROPERTY_DISABLE) && (ret == 0)){
cparata 0:f27ce43dee4f 8391 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
cparata 0:f27ce43dee4f 8392 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8393 if (ret == 0) {
cparata 0:f27ce43dee4f 8394 reg.mlc_en = val;
cparata 0:f27ce43dee4f 8395 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
cparata 0:f27ce43dee4f 8396 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8397 }
cparata 0:f27ce43dee4f 8398 }
cparata 0:f27ce43dee4f 8399 if (ret == 0) {
cparata 0:f27ce43dee4f 8400 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8401 }
cparata 0:f27ce43dee4f 8402 return ret;
cparata 0:f27ce43dee4f 8403 }
cparata 0:f27ce43dee4f 8404
cparata 0:f27ce43dee4f 8405 /**
cparata 0:f27ce43dee4f 8406 * @brief Enable Machine Learning Core.[get]
cparata 0:f27ce43dee4f 8407 *
cparata 0:f27ce43dee4f 8408 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8409 * @param val Get the values of mlc_en in
cparata 0:f27ce43dee4f 8410 * reg EMB_FUNC_EN_B
cparata 0:f27ce43dee4f 8411 *
cparata 0:f27ce43dee4f 8412 */
cparata 0:f27ce43dee4f 8413 int32_t lsm6dsox_mlc_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 8414 {
cparata 0:f27ce43dee4f 8415 lsm6dsox_emb_func_en_b_t reg;
cparata 0:f27ce43dee4f 8416 int32_t ret;
cparata 0:f27ce43dee4f 8417
cparata 0:f27ce43dee4f 8418 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8419 if (ret == 0) {
cparata 0:f27ce43dee4f 8420 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8421 }
cparata 0:f27ce43dee4f 8422 if (ret == 0) {
cparata 0:f27ce43dee4f 8423 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8424 *val = reg.mlc_en;
cparata 0:f27ce43dee4f 8425 }
cparata 0:f27ce43dee4f 8426 return ret;
cparata 0:f27ce43dee4f 8427 }
cparata 0:f27ce43dee4f 8428
cparata 0:f27ce43dee4f 8429 /**
cparata 0:f27ce43dee4f 8430 * @brief Machine Learning Core status register[get]
cparata 0:f27ce43dee4f 8431 *
cparata 0:f27ce43dee4f 8432 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8433 * @param val register MLC_STATUS_MAINPAGE
cparata 0:f27ce43dee4f 8434 *
cparata 0:f27ce43dee4f 8435 */
cparata 0:f27ce43dee4f 8436 int32_t lsm6dsox_mlc_status_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8437 lsm6dsox_mlc_status_mainpage_t *val)
cparata 0:f27ce43dee4f 8438 {
cparata 0:f27ce43dee4f 8439 return lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_STATUS_MAINPAGE,
cparata 0:f27ce43dee4f 8440 (uint8_t*) val, 1);
cparata 0:f27ce43dee4f 8441 }
cparata 0:f27ce43dee4f 8442
cparata 0:f27ce43dee4f 8443 /**
cparata 0:f27ce43dee4f 8444 * @brief Machine Learning Core data rate selection.[set]
cparata 0:f27ce43dee4f 8445 *
cparata 0:f27ce43dee4f 8446 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8447 * @param val get the values of mlc_odr in
cparata 0:f27ce43dee4f 8448 * reg EMB_FUNC_ODR_CFG_C
cparata 0:f27ce43dee4f 8449 *
cparata 0:f27ce43dee4f 8450 */
cparata 0:f27ce43dee4f 8451 int32_t lsm6dsox_mlc_data_rate_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8452 lsm6dsox_mlc_odr_t val)
cparata 0:f27ce43dee4f 8453 {
cparata 0:f27ce43dee4f 8454 lsm6dsox_emb_func_odr_cfg_c_t reg;
cparata 0:f27ce43dee4f 8455 int32_t ret;
cparata 0:f27ce43dee4f 8456
cparata 0:f27ce43dee4f 8457 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8458 if (ret == 0) {
cparata 0:f27ce43dee4f 8459 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
cparata 0:f27ce43dee4f 8460 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8461 }
cparata 0:f27ce43dee4f 8462 if (ret == 0) {
cparata 0:f27ce43dee4f 8463 reg.mlc_odr = (uint8_t)val;
cparata 0:f27ce43dee4f 8464 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8465 }
cparata 0:f27ce43dee4f 8466 if (ret == 0) {
cparata 0:f27ce43dee4f 8467 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8468 }
cparata 0:f27ce43dee4f 8469
cparata 0:f27ce43dee4f 8470 return ret;
cparata 0:f27ce43dee4f 8471 }
cparata 0:f27ce43dee4f 8472
cparata 0:f27ce43dee4f 8473 /**
cparata 0:f27ce43dee4f 8474 * @brief Machine Learning Core data rate selection.[get]
cparata 0:f27ce43dee4f 8475 *
cparata 0:f27ce43dee4f 8476 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8477 * @param val change the values of mlc_odr in
cparata 0:f27ce43dee4f 8478 * reg EMB_FUNC_ODR_CFG_C
cparata 0:f27ce43dee4f 8479 *
cparata 0:f27ce43dee4f 8480 */
cparata 0:f27ce43dee4f 8481 int32_t lsm6dsox_mlc_data_rate_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8482 lsm6dsox_mlc_odr_t *val)
cparata 0:f27ce43dee4f 8483 {
cparata 0:f27ce43dee4f 8484 lsm6dsox_emb_func_odr_cfg_c_t reg;
cparata 0:f27ce43dee4f 8485 int32_t ret;
cparata 0:f27ce43dee4f 8486
cparata 0:f27ce43dee4f 8487 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
cparata 0:f27ce43dee4f 8488 if (ret == 0) {
cparata 0:f27ce43dee4f 8489 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
cparata 0:f27ce43dee4f 8490 (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8491 }
cparata 0:f27ce43dee4f 8492 if (ret == 0) {
cparata 0:f27ce43dee4f 8493 switch (reg.mlc_odr) {
cparata 0:f27ce43dee4f 8494 case LSM6DSOX_ODR_PRGS_12Hz5:
cparata 0:f27ce43dee4f 8495 *val = LSM6DSOX_ODR_PRGS_12Hz5;
cparata 0:f27ce43dee4f 8496 break;
cparata 0:f27ce43dee4f 8497 case LSM6DSOX_ODR_PRGS_26Hz:
cparata 0:f27ce43dee4f 8498 *val = LSM6DSOX_ODR_PRGS_26Hz;
cparata 0:f27ce43dee4f 8499 break;
cparata 0:f27ce43dee4f 8500 case LSM6DSOX_ODR_PRGS_52Hz:
cparata 0:f27ce43dee4f 8501 *val = LSM6DSOX_ODR_PRGS_52Hz;
cparata 0:f27ce43dee4f 8502 break;
cparata 0:f27ce43dee4f 8503 case LSM6DSOX_ODR_PRGS_104Hz:
cparata 0:f27ce43dee4f 8504 *val = LSM6DSOX_ODR_PRGS_104Hz;
cparata 0:f27ce43dee4f 8505 break;
cparata 0:f27ce43dee4f 8506 default:
cparata 0:f27ce43dee4f 8507 *val = LSM6DSOX_ODR_PRGS_12Hz5;
cparata 0:f27ce43dee4f 8508 break;
cparata 0:f27ce43dee4f 8509 }
cparata 0:f27ce43dee4f 8510 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8511 }
cparata 0:f27ce43dee4f 8512 return ret;
cparata 0:f27ce43dee4f 8513 }
cparata 0:f27ce43dee4f 8514
cparata 0:f27ce43dee4f 8515 /**
cparata 0:f27ce43dee4f 8516 * @}
cparata 0:f27ce43dee4f 8517 *
cparata 0:f27ce43dee4f 8518 */
cparata 0:f27ce43dee4f 8519
cparata 0:f27ce43dee4f 8520 /**
cparata 0:f27ce43dee4f 8521 * @defgroup LSM6DSOX_Sensor_hub
cparata 0:f27ce43dee4f 8522 * @brief This section groups all the functions that manage the
cparata 0:f27ce43dee4f 8523 * sensor hub.
cparata 0:f27ce43dee4f 8524 * @{
cparata 0:f27ce43dee4f 8525 *
cparata 0:f27ce43dee4f 8526 */
cparata 0:f27ce43dee4f 8527
cparata 0:f27ce43dee4f 8528 /**
cparata 0:f27ce43dee4f 8529 * @brief Sensor hub output registers.[get]
cparata 0:f27ce43dee4f 8530 *
cparata 0:f27ce43dee4f 8531 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8532 * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
cparata 0:f27ce43dee4f 8533 *
cparata 0:f27ce43dee4f 8534 */
cparata 0:f27ce43dee4f 8535 int32_t lsm6dsox_sh_read_data_raw_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8536 lsm6dsox_emb_sh_read_t *val)
cparata 0:f27ce43dee4f 8537 {
cparata 0:f27ce43dee4f 8538 int32_t ret;
cparata 0:f27ce43dee4f 8539
cparata 0:f27ce43dee4f 8540 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8541 if (ret == 0) {
cparata 0:f27ce43dee4f 8542 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SENSOR_HUB_1, (uint8_t*) val, 18U);
cparata 0:f27ce43dee4f 8543 }
cparata 0:f27ce43dee4f 8544 if (ret == 0) {
cparata 0:f27ce43dee4f 8545 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8546 }
cparata 0:f27ce43dee4f 8547
cparata 0:f27ce43dee4f 8548 return ret;
cparata 0:f27ce43dee4f 8549 }
cparata 0:f27ce43dee4f 8550
cparata 0:f27ce43dee4f 8551 /**
cparata 0:f27ce43dee4f 8552 * @brief Number of external sensors to be read by the sensor hub.[set]
cparata 0:f27ce43dee4f 8553 *
cparata 0:f27ce43dee4f 8554 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8555 * @param val change the values of aux_sens_on in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8556 *
cparata 0:f27ce43dee4f 8557 */
cparata 0:f27ce43dee4f 8558 int32_t lsm6dsox_sh_slave_connected_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8559 lsm6dsox_aux_sens_on_t val)
cparata 0:f27ce43dee4f 8560 {
cparata 0:f27ce43dee4f 8561 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8562 int32_t ret;
cparata 0:f27ce43dee4f 8563
cparata 0:f27ce43dee4f 8564 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8565 if (ret == 0) {
cparata 0:f27ce43dee4f 8566 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8567 }
cparata 0:f27ce43dee4f 8568 if (ret == 0) {
cparata 0:f27ce43dee4f 8569 reg.aux_sens_on = (uint8_t)val;
cparata 0:f27ce43dee4f 8570 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8571 }
cparata 0:f27ce43dee4f 8572 if (ret == 0) {
cparata 0:f27ce43dee4f 8573 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8574 }
cparata 0:f27ce43dee4f 8575 return ret;
cparata 0:f27ce43dee4f 8576 }
cparata 0:f27ce43dee4f 8577
cparata 0:f27ce43dee4f 8578 /**
cparata 0:f27ce43dee4f 8579 * @brief Number of external sensors to be read by the sensor hub.[get]
cparata 0:f27ce43dee4f 8580 *
cparata 0:f27ce43dee4f 8581 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8582 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8583 *
cparata 0:f27ce43dee4f 8584 */
cparata 0:f27ce43dee4f 8585 int32_t lsm6dsox_sh_slave_connected_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8586 lsm6dsox_aux_sens_on_t *val)
cparata 0:f27ce43dee4f 8587 {
cparata 0:f27ce43dee4f 8588 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8589 int32_t ret;
cparata 0:f27ce43dee4f 8590
cparata 0:f27ce43dee4f 8591 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8592 if (ret == 0) {
cparata 0:f27ce43dee4f 8593 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8594 }
cparata 0:f27ce43dee4f 8595 if (ret == 0) {
cparata 0:f27ce43dee4f 8596 switch (reg.aux_sens_on) {
cparata 0:f27ce43dee4f 8597 case LSM6DSOX_SLV_0:
cparata 0:f27ce43dee4f 8598 *val = LSM6DSOX_SLV_0;
cparata 0:f27ce43dee4f 8599 break;
cparata 0:f27ce43dee4f 8600 case LSM6DSOX_SLV_0_1:
cparata 0:f27ce43dee4f 8601 *val = LSM6DSOX_SLV_0_1;
cparata 0:f27ce43dee4f 8602 break;
cparata 0:f27ce43dee4f 8603 case LSM6DSOX_SLV_0_1_2:
cparata 0:f27ce43dee4f 8604 *val = LSM6DSOX_SLV_0_1_2;
cparata 0:f27ce43dee4f 8605 break;
cparata 0:f27ce43dee4f 8606 case LSM6DSOX_SLV_0_1_2_3:
cparata 0:f27ce43dee4f 8607 *val = LSM6DSOX_SLV_0_1_2_3;
cparata 0:f27ce43dee4f 8608 break;
cparata 0:f27ce43dee4f 8609 default:
cparata 0:f27ce43dee4f 8610 *val = LSM6DSOX_SLV_0;
cparata 0:f27ce43dee4f 8611 break;
cparata 0:f27ce43dee4f 8612 }
cparata 0:f27ce43dee4f 8613 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8614 }
cparata 0:f27ce43dee4f 8615
cparata 0:f27ce43dee4f 8616 return ret;
cparata 0:f27ce43dee4f 8617 }
cparata 0:f27ce43dee4f 8618
cparata 0:f27ce43dee4f 8619 /**
cparata 0:f27ce43dee4f 8620 * @brief Sensor hub I2C master enable.[set]
cparata 0:f27ce43dee4f 8621 *
cparata 0:f27ce43dee4f 8622 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8623 * @param val change the values of master_on in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8624 *
cparata 0:f27ce43dee4f 8625 */
cparata 0:f27ce43dee4f 8626 int32_t lsm6dsox_sh_master_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 8627 {
cparata 0:f27ce43dee4f 8628 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8629 int32_t ret;
cparata 0:f27ce43dee4f 8630
cparata 0:f27ce43dee4f 8631 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8632 if (ret == 0) {
cparata 0:f27ce43dee4f 8633 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8634 }
cparata 0:f27ce43dee4f 8635 if (ret == 0) {
cparata 0:f27ce43dee4f 8636 reg.master_on = val;
cparata 0:f27ce43dee4f 8637 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8638 }
cparata 0:f27ce43dee4f 8639 if (ret == 0) {
cparata 0:f27ce43dee4f 8640 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8641 }
cparata 0:f27ce43dee4f 8642 return ret;
cparata 0:f27ce43dee4f 8643 }
cparata 0:f27ce43dee4f 8644
cparata 0:f27ce43dee4f 8645 /**
cparata 0:f27ce43dee4f 8646 * @brief Sensor hub I2C master enable.[get]
cparata 0:f27ce43dee4f 8647 *
cparata 0:f27ce43dee4f 8648 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8649 * @param val change the values of master_on in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8650 *
cparata 0:f27ce43dee4f 8651 */
cparata 0:f27ce43dee4f 8652 int32_t lsm6dsox_sh_master_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 8653 {
cparata 0:f27ce43dee4f 8654 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8655 int32_t ret;
cparata 0:f27ce43dee4f 8656
cparata 0:f27ce43dee4f 8657 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8658 if (ret == 0) {
cparata 0:f27ce43dee4f 8659 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8660 }
cparata 0:f27ce43dee4f 8661 if (ret == 0) {
cparata 0:f27ce43dee4f 8662 *val = reg.master_on;
cparata 0:f27ce43dee4f 8663 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8664 }
cparata 0:f27ce43dee4f 8665
cparata 0:f27ce43dee4f 8666 return ret;
cparata 0:f27ce43dee4f 8667 }
cparata 0:f27ce43dee4f 8668
cparata 0:f27ce43dee4f 8669 /**
cparata 0:f27ce43dee4f 8670 * @brief Master I2C pull-up enable.[set]
cparata 0:f27ce43dee4f 8671 *
cparata 0:f27ce43dee4f 8672 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8673 * @param val change the values of shub_pu_en in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8674 *
cparata 0:f27ce43dee4f 8675 */
cparata 0:f27ce43dee4f 8676 int32_t lsm6dsox_sh_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_pu_en_t val)
cparata 0:f27ce43dee4f 8677 {
cparata 0:f27ce43dee4f 8678 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8679 int32_t ret;
cparata 0:f27ce43dee4f 8680
cparata 0:f27ce43dee4f 8681 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8682 if (ret == 0) {
cparata 0:f27ce43dee4f 8683 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8684 }
cparata 0:f27ce43dee4f 8685 if (ret == 0) {
cparata 0:f27ce43dee4f 8686 reg.shub_pu_en = (uint8_t)val;
cparata 0:f27ce43dee4f 8687 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8688 }
cparata 0:f27ce43dee4f 8689 if (ret == 0) {
cparata 0:f27ce43dee4f 8690 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8691 }
cparata 0:f27ce43dee4f 8692
cparata 0:f27ce43dee4f 8693 return ret;
cparata 0:f27ce43dee4f 8694 }
cparata 0:f27ce43dee4f 8695
cparata 0:f27ce43dee4f 8696 /**
cparata 0:f27ce43dee4f 8697 * @brief Master I2C pull-up enable.[get]
cparata 0:f27ce43dee4f 8698 *
cparata 0:f27ce43dee4f 8699 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8700 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8701 *
cparata 0:f27ce43dee4f 8702 */
cparata 0:f27ce43dee4f 8703 int32_t lsm6dsox_sh_pin_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8704 lsm6dsox_shub_pu_en_t *val)
cparata 0:f27ce43dee4f 8705 {
cparata 0:f27ce43dee4f 8706 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8707 int32_t ret;
cparata 0:f27ce43dee4f 8708
cparata 0:f27ce43dee4f 8709 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8710 if (ret == 0) {
cparata 0:f27ce43dee4f 8711 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8712 }
cparata 0:f27ce43dee4f 8713 if (ret == 0) {
cparata 0:f27ce43dee4f 8714 switch (reg.shub_pu_en) {
cparata 0:f27ce43dee4f 8715 case LSM6DSOX_EXT_PULL_UP:
cparata 0:f27ce43dee4f 8716 *val = LSM6DSOX_EXT_PULL_UP;
cparata 0:f27ce43dee4f 8717 break;
cparata 0:f27ce43dee4f 8718 case LSM6DSOX_INTERNAL_PULL_UP:
cparata 0:f27ce43dee4f 8719 *val = LSM6DSOX_INTERNAL_PULL_UP;
cparata 0:f27ce43dee4f 8720 break;
cparata 0:f27ce43dee4f 8721 default:
cparata 0:f27ce43dee4f 8722 *val = LSM6DSOX_EXT_PULL_UP;
cparata 0:f27ce43dee4f 8723 break;
cparata 0:f27ce43dee4f 8724 }
cparata 0:f27ce43dee4f 8725 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8726 }
cparata 0:f27ce43dee4f 8727
cparata 0:f27ce43dee4f 8728 return ret;
cparata 0:f27ce43dee4f 8729 }
cparata 0:f27ce43dee4f 8730
cparata 0:f27ce43dee4f 8731 /**
cparata 0:f27ce43dee4f 8732 * @brief I2C interface pass-through.[set]
cparata 0:f27ce43dee4f 8733 *
cparata 0:f27ce43dee4f 8734 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8735 * @param val change the values of pass_through_mode in
cparata 0:f27ce43dee4f 8736 * reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8737 *
cparata 0:f27ce43dee4f 8738 */
cparata 0:f27ce43dee4f 8739 int32_t lsm6dsox_sh_pass_through_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 8740 {
cparata 0:f27ce43dee4f 8741 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8742 int32_t ret;
cparata 0:f27ce43dee4f 8743
cparata 0:f27ce43dee4f 8744 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8745 if (ret == 0) {
cparata 0:f27ce43dee4f 8746 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8747 }
cparata 0:f27ce43dee4f 8748 if (ret == 0) {
cparata 0:f27ce43dee4f 8749 reg.pass_through_mode = val;
cparata 0:f27ce43dee4f 8750 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8751 }
cparata 0:f27ce43dee4f 8752 if (ret == 0) {
cparata 0:f27ce43dee4f 8753 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8754 }
cparata 0:f27ce43dee4f 8755
cparata 0:f27ce43dee4f 8756 return ret;
cparata 0:f27ce43dee4f 8757 }
cparata 0:f27ce43dee4f 8758
cparata 0:f27ce43dee4f 8759 /**
cparata 0:f27ce43dee4f 8760 * @brief I2C interface pass-through.[get]
cparata 0:f27ce43dee4f 8761 *
cparata 0:f27ce43dee4f 8762 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8763 * @param val change the values of pass_through_mode in
cparata 0:f27ce43dee4f 8764 * reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8765 *
cparata 0:f27ce43dee4f 8766 */
cparata 0:f27ce43dee4f 8767 int32_t lsm6dsox_sh_pass_through_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 8768 {
cparata 0:f27ce43dee4f 8769 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8770 int32_t ret;
cparata 0:f27ce43dee4f 8771
cparata 0:f27ce43dee4f 8772 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8773 if (ret == 0) {
cparata 0:f27ce43dee4f 8774 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8775 }
cparata 0:f27ce43dee4f 8776 if (ret == 0) {
cparata 0:f27ce43dee4f 8777 *val = reg.pass_through_mode;
cparata 0:f27ce43dee4f 8778 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8779 }
cparata 0:f27ce43dee4f 8780
cparata 0:f27ce43dee4f 8781 return ret;
cparata 0:f27ce43dee4f 8782 }
cparata 0:f27ce43dee4f 8783
cparata 0:f27ce43dee4f 8784 /**
cparata 0:f27ce43dee4f 8785 * @brief Sensor hub trigger signal selection.[set]
cparata 0:f27ce43dee4f 8786 *
cparata 0:f27ce43dee4f 8787 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8788 * @param val change the values of start_config in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8789 *
cparata 0:f27ce43dee4f 8790 */
cparata 0:f27ce43dee4f 8791 int32_t lsm6dsox_sh_syncro_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8792 lsm6dsox_start_config_t val)
cparata 0:f27ce43dee4f 8793 {
cparata 0:f27ce43dee4f 8794 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8795 int32_t ret;
cparata 0:f27ce43dee4f 8796
cparata 0:f27ce43dee4f 8797 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8798 if (ret == 0) {
cparata 0:f27ce43dee4f 8799 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8800 }
cparata 0:f27ce43dee4f 8801 if (ret == 0) {
cparata 0:f27ce43dee4f 8802 reg.start_config = (uint8_t)val;
cparata 0:f27ce43dee4f 8803 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8804 }
cparata 0:f27ce43dee4f 8805 if (ret == 0) {
cparata 0:f27ce43dee4f 8806 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8807 }
cparata 0:f27ce43dee4f 8808
cparata 0:f27ce43dee4f 8809 return ret;
cparata 0:f27ce43dee4f 8810 }
cparata 0:f27ce43dee4f 8811
cparata 0:f27ce43dee4f 8812 /**
cparata 0:f27ce43dee4f 8813 * @brief Sensor hub trigger signal selection.[get]
cparata 0:f27ce43dee4f 8814 *
cparata 0:f27ce43dee4f 8815 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8816 * @param val Get the values of start_config in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8817 *
cparata 0:f27ce43dee4f 8818 */
cparata 0:f27ce43dee4f 8819 int32_t lsm6dsox_sh_syncro_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8820 lsm6dsox_start_config_t *val)
cparata 0:f27ce43dee4f 8821 {
cparata 0:f27ce43dee4f 8822 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8823 int32_t ret;
cparata 0:f27ce43dee4f 8824
cparata 0:f27ce43dee4f 8825 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8826 if (ret == 0) {
cparata 0:f27ce43dee4f 8827 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8828 }
cparata 0:f27ce43dee4f 8829 if (ret == 0) {
cparata 0:f27ce43dee4f 8830 switch (reg.start_config) {
cparata 0:f27ce43dee4f 8831 case LSM6DSOX_EXT_ON_INT2_PIN:
cparata 0:f27ce43dee4f 8832 *val = LSM6DSOX_EXT_ON_INT2_PIN;
cparata 0:f27ce43dee4f 8833 break;
cparata 0:f27ce43dee4f 8834 case LSM6DSOX_XL_GY_DRDY:
cparata 0:f27ce43dee4f 8835 *val = LSM6DSOX_XL_GY_DRDY;
cparata 0:f27ce43dee4f 8836 break;
cparata 0:f27ce43dee4f 8837 default:
cparata 0:f27ce43dee4f 8838 *val = LSM6DSOX_EXT_ON_INT2_PIN;
cparata 0:f27ce43dee4f 8839 break;
cparata 0:f27ce43dee4f 8840 }
cparata 0:f27ce43dee4f 8841 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8842 }
cparata 0:f27ce43dee4f 8843 return ret;
cparata 0:f27ce43dee4f 8844 }
cparata 0:f27ce43dee4f 8845
cparata 0:f27ce43dee4f 8846 /**
cparata 0:f27ce43dee4f 8847 * @brief Slave 0 write operation is performed only at the first
cparata 0:f27ce43dee4f 8848 * sensor hub cycle.[set]
cparata 0:f27ce43dee4f 8849 *
cparata 0:f27ce43dee4f 8850 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8851 * @param val change the values of write_once in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8852 *
cparata 0:f27ce43dee4f 8853 */
cparata 0:f27ce43dee4f 8854 int32_t lsm6dsox_sh_write_mode_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8855 lsm6dsox_write_once_t val)
cparata 0:f27ce43dee4f 8856 {
cparata 0:f27ce43dee4f 8857 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8858 int32_t ret;
cparata 0:f27ce43dee4f 8859
cparata 0:f27ce43dee4f 8860 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8861 if (ret == 0) {
cparata 0:f27ce43dee4f 8862 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8863 }
cparata 0:f27ce43dee4f 8864 if (ret == 0) {
cparata 0:f27ce43dee4f 8865 reg.write_once = (uint8_t)val;
cparata 0:f27ce43dee4f 8866 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8867 }
cparata 0:f27ce43dee4f 8868 if (ret == 0) {
cparata 0:f27ce43dee4f 8869 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8870 }
cparata 0:f27ce43dee4f 8871
cparata 0:f27ce43dee4f 8872 return ret;
cparata 0:f27ce43dee4f 8873 }
cparata 0:f27ce43dee4f 8874
cparata 0:f27ce43dee4f 8875 /**
cparata 0:f27ce43dee4f 8876 * @brief Slave 0 write operation is performed only at the first sensor
cparata 0:f27ce43dee4f 8877 * hub cycle.[get]
cparata 0:f27ce43dee4f 8878 *
cparata 0:f27ce43dee4f 8879 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8880 * @param val Get the values of write_once in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8881 *
cparata 0:f27ce43dee4f 8882 */
cparata 0:f27ce43dee4f 8883 int32_t lsm6dsox_sh_write_mode_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8884 lsm6dsox_write_once_t *val)
cparata 0:f27ce43dee4f 8885 {
cparata 0:f27ce43dee4f 8886 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8887 int32_t ret;
cparata 0:f27ce43dee4f 8888
cparata 0:f27ce43dee4f 8889 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8890 if (ret == 0) {
cparata 0:f27ce43dee4f 8891 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8892 }
cparata 0:f27ce43dee4f 8893 if (ret == 0) {
cparata 0:f27ce43dee4f 8894 switch (reg.write_once) {
cparata 0:f27ce43dee4f 8895 case LSM6DSOX_EACH_SH_CYCLE:
cparata 0:f27ce43dee4f 8896 *val = LSM6DSOX_EACH_SH_CYCLE;
cparata 0:f27ce43dee4f 8897 break;
cparata 0:f27ce43dee4f 8898 case LSM6DSOX_ONLY_FIRST_CYCLE:
cparata 0:f27ce43dee4f 8899 *val = LSM6DSOX_ONLY_FIRST_CYCLE;
cparata 0:f27ce43dee4f 8900 break;
cparata 0:f27ce43dee4f 8901 default:
cparata 0:f27ce43dee4f 8902 *val = LSM6DSOX_EACH_SH_CYCLE;
cparata 0:f27ce43dee4f 8903 break;
cparata 0:f27ce43dee4f 8904 }
cparata 0:f27ce43dee4f 8905 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8906 }
cparata 0:f27ce43dee4f 8907
cparata 0:f27ce43dee4f 8908 return ret;
cparata 0:f27ce43dee4f 8909 }
cparata 0:f27ce43dee4f 8910
cparata 0:f27ce43dee4f 8911 /**
cparata 0:f27ce43dee4f 8912 * @brief Reset Master logic and output registers.[set]
cparata 0:f27ce43dee4f 8913 *
cparata 0:f27ce43dee4f 8914 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8915 *
cparata 0:f27ce43dee4f 8916 */
cparata 0:f27ce43dee4f 8917 int32_t lsm6dsox_sh_reset_set(lsm6dsox_ctx_t *ctx)
cparata 0:f27ce43dee4f 8918 {
cparata 0:f27ce43dee4f 8919 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8920 int32_t ret;
cparata 0:f27ce43dee4f 8921
cparata 0:f27ce43dee4f 8922 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8923 if (ret == 0) {
cparata 0:f27ce43dee4f 8924 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8925 }
cparata 0:f27ce43dee4f 8926 if (ret == 0) {
cparata 0:f27ce43dee4f 8927 reg.rst_master_regs = PROPERTY_ENABLE;
cparata 0:f27ce43dee4f 8928 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8929 }
cparata 0:f27ce43dee4f 8930 if (ret == 0) {
cparata 0:f27ce43dee4f 8931 reg.rst_master_regs = PROPERTY_DISABLE;
cparata 0:f27ce43dee4f 8932 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8933 }
cparata 0:f27ce43dee4f 8934 if (ret == 0) {
cparata 0:f27ce43dee4f 8935 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8936 }
cparata 0:f27ce43dee4f 8937
cparata 0:f27ce43dee4f 8938 return ret;
cparata 0:f27ce43dee4f 8939 }
cparata 0:f27ce43dee4f 8940
cparata 0:f27ce43dee4f 8941 /**
cparata 0:f27ce43dee4f 8942 * @brief Reset Master logic and output registers.[get]
cparata 0:f27ce43dee4f 8943 *
cparata 0:f27ce43dee4f 8944 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8945 * @param val change the values of rst_master_regs in reg MASTER_CONFIG
cparata 0:f27ce43dee4f 8946 *
cparata 0:f27ce43dee4f 8947 */
cparata 0:f27ce43dee4f 8948 int32_t lsm6dsox_sh_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 8949 {
cparata 0:f27ce43dee4f 8950 lsm6dsox_master_config_t reg;
cparata 0:f27ce43dee4f 8951 int32_t ret;
cparata 0:f27ce43dee4f 8952
cparata 0:f27ce43dee4f 8953 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8954 if (ret == 0) {
cparata 0:f27ce43dee4f 8955 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8956 }
cparata 0:f27ce43dee4f 8957 if (ret == 0) {
cparata 0:f27ce43dee4f 8958 *val = reg.rst_master_regs;
cparata 0:f27ce43dee4f 8959 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8960 }
cparata 0:f27ce43dee4f 8961 return ret;
cparata 0:f27ce43dee4f 8962 }
cparata 0:f27ce43dee4f 8963
cparata 0:f27ce43dee4f 8964 /**
cparata 0:f27ce43dee4f 8965 * @brief Rate at which the master communicates.[set]
cparata 0:f27ce43dee4f 8966 *
cparata 0:f27ce43dee4f 8967 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8968 * @param val change the values of shub_odr in reg slv1_CONFIG
cparata 0:f27ce43dee4f 8969 *
cparata 0:f27ce43dee4f 8970 */
cparata 0:f27ce43dee4f 8971 int32_t lsm6dsox_sh_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_odr_t val)
cparata 0:f27ce43dee4f 8972 {
cparata 0:f27ce43dee4f 8973 lsm6dsox_slv0_config_t reg;
cparata 0:f27ce43dee4f 8974 int32_t ret;
cparata 0:f27ce43dee4f 8975
cparata 0:f27ce43dee4f 8976 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 8977 if (ret == 0) {
cparata 0:f27ce43dee4f 8978 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8979 }
cparata 0:f27ce43dee4f 8980 if (ret == 0) {
cparata 0:f27ce43dee4f 8981 reg.shub_odr = (uint8_t)val;
cparata 0:f27ce43dee4f 8982 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 8983 }
cparata 0:f27ce43dee4f 8984 if (ret == 0) {
cparata 0:f27ce43dee4f 8985 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 8986 }
cparata 0:f27ce43dee4f 8987
cparata 0:f27ce43dee4f 8988 return ret;
cparata 0:f27ce43dee4f 8989 }
cparata 0:f27ce43dee4f 8990
cparata 0:f27ce43dee4f 8991 /**
cparata 0:f27ce43dee4f 8992 * @brief Rate at which the master communicates.[get]
cparata 0:f27ce43dee4f 8993 *
cparata 0:f27ce43dee4f 8994 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 8995 * @param val Get the values of shub_odr in reg slv1_CONFIG
cparata 0:f27ce43dee4f 8996 *
cparata 0:f27ce43dee4f 8997 */
cparata 0:f27ce43dee4f 8998 int32_t lsm6dsox_sh_data_rate_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 8999 lsm6dsox_shub_odr_t *val)
cparata 0:f27ce43dee4f 9000 {
cparata 0:f27ce43dee4f 9001 lsm6dsox_slv0_config_t reg;
cparata 0:f27ce43dee4f 9002 int32_t ret;
cparata 0:f27ce43dee4f 9003
cparata 0:f27ce43dee4f 9004 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 9005 if (ret == 0) {
cparata 0:f27ce43dee4f 9006 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9007 }
cparata 0:f27ce43dee4f 9008 if (ret == 0) {
cparata 0:f27ce43dee4f 9009 switch (reg.shub_odr) {
cparata 0:f27ce43dee4f 9010 case LSM6DSOX_SH_ODR_104Hz:
cparata 0:f27ce43dee4f 9011 *val = LSM6DSOX_SH_ODR_104Hz;
cparata 0:f27ce43dee4f 9012 break;
cparata 0:f27ce43dee4f 9013 case LSM6DSOX_SH_ODR_52Hz:
cparata 0:f27ce43dee4f 9014 *val = LSM6DSOX_SH_ODR_52Hz;
cparata 0:f27ce43dee4f 9015 break;
cparata 0:f27ce43dee4f 9016 case LSM6DSOX_SH_ODR_26Hz:
cparata 0:f27ce43dee4f 9017 *val = LSM6DSOX_SH_ODR_26Hz;
cparata 0:f27ce43dee4f 9018 break;
cparata 0:f27ce43dee4f 9019 case LSM6DSOX_SH_ODR_13Hz:
cparata 0:f27ce43dee4f 9020 *val = LSM6DSOX_SH_ODR_13Hz;
cparata 0:f27ce43dee4f 9021 break;
cparata 0:f27ce43dee4f 9022 default:
cparata 0:f27ce43dee4f 9023 *val = LSM6DSOX_SH_ODR_104Hz;
cparata 0:f27ce43dee4f 9024 break;
cparata 0:f27ce43dee4f 9025 }
cparata 0:f27ce43dee4f 9026 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 9027 }
cparata 0:f27ce43dee4f 9028
cparata 0:f27ce43dee4f 9029 return ret;
cparata 0:f27ce43dee4f 9030 }
cparata 0:f27ce43dee4f 9031
cparata 0:f27ce43dee4f 9032 /**
cparata 0:f27ce43dee4f 9033 * @brief Configure slave 0 for perform a write.[set]
cparata 0:f27ce43dee4f 9034 *
cparata 0:f27ce43dee4f 9035 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 9036 * @param val a structure that contain
cparata 0:f27ce43dee4f 9037 * - uint8_t slv1_add; 8 bit i2c device address
cparata 0:f27ce43dee4f 9038 * - uint8_t slv1_subadd; 8 bit register device address
cparata 0:f27ce43dee4f 9039 * - uint8_t slv1_data; 8 bit data to write
cparata 0:f27ce43dee4f 9040 *
cparata 0:f27ce43dee4f 9041 */
cparata 0:f27ce43dee4f 9042 int32_t lsm6dsox_sh_cfg_write(lsm6dsox_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val)
cparata 0:f27ce43dee4f 9043 {
cparata 0:f27ce43dee4f 9044 lsm6dsox_slv0_add_t reg;
cparata 0:f27ce43dee4f 9045 int32_t ret;
cparata 0:f27ce43dee4f 9046
cparata 0:f27ce43dee4f 9047 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 9048 if (ret == 0) {
cparata 0:f27ce43dee4f 9049 reg.slave0 = val->slv0_add;
cparata 0:f27ce43dee4f 9050 reg.rw_0 = 0;
cparata 0:f27ce43dee4f 9051 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9052 }
cparata 0:f27ce43dee4f 9053 if (ret == 0) {
cparata 0:f27ce43dee4f 9054 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD,
cparata 0:f27ce43dee4f 9055 &(val->slv0_subadd), 1);
cparata 0:f27ce43dee4f 9056 }
cparata 0:f27ce43dee4f 9057 if (ret == 0) {
cparata 0:f27ce43dee4f 9058 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_DATAWRITE_SLV0,
cparata 0:f27ce43dee4f 9059 &(val->slv0_data), 1);
cparata 0:f27ce43dee4f 9060 }
cparata 0:f27ce43dee4f 9061 if (ret == 0) {
cparata 0:f27ce43dee4f 9062 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 9063 }
cparata 0:f27ce43dee4f 9064 return ret;
cparata 0:f27ce43dee4f 9065 }
cparata 0:f27ce43dee4f 9066
cparata 0:f27ce43dee4f 9067 /**
cparata 0:f27ce43dee4f 9068 * @brief Configure slave 0 for perform a read.[set]
cparata 0:f27ce43dee4f 9069 *
cparata 0:f27ce43dee4f 9070 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 9071 * @param val Structure that contain
cparata 0:f27ce43dee4f 9072 * - uint8_t slv1_add; 8 bit i2c device address
cparata 0:f27ce43dee4f 9073 * - uint8_t slv1_subadd; 8 bit register device address
cparata 0:f27ce43dee4f 9074 * - uint8_t slv1_len; num of bit to read
cparata 0:f27ce43dee4f 9075 *
cparata 0:f27ce43dee4f 9076 */
cparata 0:f27ce43dee4f 9077 int32_t lsm6dsox_sh_slv0_cfg_read(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 9078 lsm6dsox_sh_cfg_read_t *val)
cparata 0:f27ce43dee4f 9079 {
cparata 0:f27ce43dee4f 9080 lsm6dsox_slv0_add_t slv0_add;
cparata 0:f27ce43dee4f 9081 lsm6dsox_slv0_config_t slv0_config;
cparata 0:f27ce43dee4f 9082 int32_t ret;
cparata 0:f27ce43dee4f 9083
cparata 0:f27ce43dee4f 9084 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 9085 if (ret == 0) {
cparata 0:f27ce43dee4f 9086 slv0_add.slave0 = val->slv_add;
cparata 0:f27ce43dee4f 9087 slv0_add.rw_0 = 1;
cparata 0:f27ce43dee4f 9088 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)&slv0_add, 1);
cparata 0:f27ce43dee4f 9089 }
cparata 0:f27ce43dee4f 9090 if (ret == 0) {
cparata 0:f27ce43dee4f 9091 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD,
cparata 0:f27ce43dee4f 9092 &(val->slv_subadd), 1);
cparata 0:f27ce43dee4f 9093 }
cparata 0:f27ce43dee4f 9094 if (ret == 0) {
cparata 0:f27ce43dee4f 9095 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG,
cparata 0:f27ce43dee4f 9096 (uint8_t*)&slv0_config, 1);
cparata 0:f27ce43dee4f 9097 }
cparata 0:f27ce43dee4f 9098 if (ret == 0) {
cparata 0:f27ce43dee4f 9099 slv0_config.slave0_numop = val->slv_len;
cparata 0:f27ce43dee4f 9100 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG,
cparata 0:f27ce43dee4f 9101 (uint8_t*)&slv0_config, 1);
cparata 0:f27ce43dee4f 9102 }
cparata 0:f27ce43dee4f 9103 if (ret == 0) {
cparata 0:f27ce43dee4f 9104 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 9105 }
cparata 0:f27ce43dee4f 9106
cparata 0:f27ce43dee4f 9107 return ret;
cparata 0:f27ce43dee4f 9108 }
cparata 0:f27ce43dee4f 9109
cparata 0:f27ce43dee4f 9110 /**
cparata 0:f27ce43dee4f 9111 * @brief Configure slave 0 for perform a write/read.[set]
cparata 0:f27ce43dee4f 9112 *
cparata 0:f27ce43dee4f 9113 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 9114 * @param val Structure that contain
cparata 0:f27ce43dee4f 9115 * - uint8_t slv1_add; 8 bit i2c device address
cparata 0:f27ce43dee4f 9116 * - uint8_t slv1_subadd; 8 bit register device address
cparata 0:f27ce43dee4f 9117 * - uint8_t slv1_len; num of bit to read
cparata 0:f27ce43dee4f 9118 *
cparata 0:f27ce43dee4f 9119 */
cparata 0:f27ce43dee4f 9120 int32_t lsm6dsox_sh_slv1_cfg_read(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 9121 lsm6dsox_sh_cfg_read_t *val)
cparata 0:f27ce43dee4f 9122 {
cparata 0:f27ce43dee4f 9123 lsm6dsox_slv1_add_t slv1_add;
cparata 0:f27ce43dee4f 9124 lsm6dsox_slv1_config_t slv1_config;
cparata 0:f27ce43dee4f 9125 int32_t ret;
cparata 0:f27ce43dee4f 9126
cparata 0:f27ce43dee4f 9127 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 9128 if (ret == 0) {
cparata 0:f27ce43dee4f 9129 slv1_add.slave1_add = val->slv_add;
cparata 0:f27ce43dee4f 9130 slv1_add.r_1 = 1;
cparata 0:f27ce43dee4f 9131 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_ADD, (uint8_t*)&slv1_add, 1);
cparata 0:f27ce43dee4f 9132 }
cparata 0:f27ce43dee4f 9133 if (ret == 0) {
cparata 0:f27ce43dee4f 9134 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_SUBADD,
cparata 0:f27ce43dee4f 9135 &(val->slv_subadd), 1);
cparata 0:f27ce43dee4f 9136 }
cparata 0:f27ce43dee4f 9137 if (ret == 0) {
cparata 0:f27ce43dee4f 9138 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG,
cparata 0:f27ce43dee4f 9139 (uint8_t*)&slv1_config, 1);
cparata 0:f27ce43dee4f 9140 }
cparata 0:f27ce43dee4f 9141 if (ret == 0) {
cparata 0:f27ce43dee4f 9142 slv1_config.slave1_numop = val->slv_len;
cparata 0:f27ce43dee4f 9143 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG,
cparata 0:f27ce43dee4f 9144 (uint8_t*)&slv1_config, 1);
cparata 0:f27ce43dee4f 9145 }
cparata 0:f27ce43dee4f 9146 if (ret == 0) {
cparata 0:f27ce43dee4f 9147 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 9148 }
cparata 0:f27ce43dee4f 9149
cparata 0:f27ce43dee4f 9150 return ret;
cparata 0:f27ce43dee4f 9151 }
cparata 0:f27ce43dee4f 9152
cparata 0:f27ce43dee4f 9153 /**
cparata 0:f27ce43dee4f 9154 * @brief Configure slave 0 for perform a write/read.[set]
cparata 0:f27ce43dee4f 9155 *
cparata 0:f27ce43dee4f 9156 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 9157 * @param val Structure that contain
cparata 0:f27ce43dee4f 9158 * - uint8_t slv2_add; 8 bit i2c device address
cparata 0:f27ce43dee4f 9159 * - uint8_t slv2_subadd; 8 bit register device address
cparata 0:f27ce43dee4f 9160 * - uint8_t slv2_len; num of bit to read
cparata 0:f27ce43dee4f 9161 *
cparata 0:f27ce43dee4f 9162 */
cparata 0:f27ce43dee4f 9163 int32_t lsm6dsox_sh_slv2_cfg_read(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 9164 lsm6dsox_sh_cfg_read_t *val)
cparata 0:f27ce43dee4f 9165 {
cparata 0:f27ce43dee4f 9166 lsm6dsox_slv2_add_t slv2_add;
cparata 0:f27ce43dee4f 9167 lsm6dsox_slv2_config_t slv2_config;
cparata 0:f27ce43dee4f 9168 int32_t ret;
cparata 0:f27ce43dee4f 9169
cparata 0:f27ce43dee4f 9170 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 9171 if (ret == 0) {
cparata 0:f27ce43dee4f 9172 slv2_add.slave2_add = val->slv_add;
cparata 0:f27ce43dee4f 9173 slv2_add.r_2 = 1;
cparata 0:f27ce43dee4f 9174 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_ADD, (uint8_t*)&slv2_add, 1);
cparata 0:f27ce43dee4f 9175 }
cparata 0:f27ce43dee4f 9176 if (ret == 0) {
cparata 0:f27ce43dee4f 9177 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_SUBADD,
cparata 0:f27ce43dee4f 9178 &(val->slv_subadd), 1);
cparata 0:f27ce43dee4f 9179 }
cparata 0:f27ce43dee4f 9180 if (ret == 0) {
cparata 0:f27ce43dee4f 9181 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG,
cparata 0:f27ce43dee4f 9182 (uint8_t*)&slv2_config, 1);
cparata 0:f27ce43dee4f 9183 }
cparata 0:f27ce43dee4f 9184 if (ret == 0) {
cparata 0:f27ce43dee4f 9185 slv2_config.slave2_numop = val->slv_len;
cparata 0:f27ce43dee4f 9186 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG,
cparata 0:f27ce43dee4f 9187 (uint8_t*)&slv2_config, 1);
cparata 0:f27ce43dee4f 9188 }
cparata 0:f27ce43dee4f 9189 if (ret == 0) {
cparata 0:f27ce43dee4f 9190 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 9191 }
cparata 0:f27ce43dee4f 9192 return ret;
cparata 0:f27ce43dee4f 9193 }
cparata 0:f27ce43dee4f 9194
cparata 0:f27ce43dee4f 9195 /**
cparata 0:f27ce43dee4f 9196 * @brief Configure slave 0 for perform a write/read.[set]
cparata 0:f27ce43dee4f 9197 *
cparata 0:f27ce43dee4f 9198 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 9199 * @param val Structure that contain
cparata 0:f27ce43dee4f 9200 * - uint8_t slv3_add; 8 bit i2c device address
cparata 0:f27ce43dee4f 9201 * - uint8_t slv3_subadd; 8 bit register device address
cparata 0:f27ce43dee4f 9202 * - uint8_t slv3_len; num of bit to read
cparata 0:f27ce43dee4f 9203 *
cparata 0:f27ce43dee4f 9204 */
cparata 0:f27ce43dee4f 9205 int32_t lsm6dsox_sh_slv3_cfg_read(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 9206 lsm6dsox_sh_cfg_read_t *val)
cparata 0:f27ce43dee4f 9207 {
cparata 0:f27ce43dee4f 9208 lsm6dsox_slv3_add_t slv3_add;
cparata 0:f27ce43dee4f 9209 lsm6dsox_slv3_config_t slv3_config;
cparata 0:f27ce43dee4f 9210 int32_t ret;
cparata 0:f27ce43dee4f 9211
cparata 0:f27ce43dee4f 9212 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 9213 if (ret == 0) {
cparata 0:f27ce43dee4f 9214 slv3_add.slave3_add = val->slv_add;
cparata 0:f27ce43dee4f 9215 slv3_add.r_3 = 1;
cparata 0:f27ce43dee4f 9216 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_ADD, (uint8_t*)&slv3_add, 1);
cparata 0:f27ce43dee4f 9217 }
cparata 0:f27ce43dee4f 9218 if (ret == 0) {
cparata 0:f27ce43dee4f 9219 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_SUBADD,
cparata 0:f27ce43dee4f 9220 &(val->slv_subadd), 1);
cparata 0:f27ce43dee4f 9221 }
cparata 0:f27ce43dee4f 9222 if (ret == 0) {
cparata 0:f27ce43dee4f 9223 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG,
cparata 0:f27ce43dee4f 9224 (uint8_t*)&slv3_config, 1);
cparata 0:f27ce43dee4f 9225 }
cparata 0:f27ce43dee4f 9226 if (ret == 0) {
cparata 0:f27ce43dee4f 9227 slv3_config.slave3_numop = val->slv_len;
cparata 0:f27ce43dee4f 9228 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG,
cparata 0:f27ce43dee4f 9229 (uint8_t*)&slv3_config, 1);
cparata 0:f27ce43dee4f 9230 }
cparata 0:f27ce43dee4f 9231 if (ret == 0) {
cparata 0:f27ce43dee4f 9232 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 9233 }
cparata 0:f27ce43dee4f 9234 return ret;
cparata 0:f27ce43dee4f 9235 }
cparata 0:f27ce43dee4f 9236
cparata 0:f27ce43dee4f 9237 /**
cparata 0:f27ce43dee4f 9238 * @brief Sensor hub source register.[get]
cparata 0:f27ce43dee4f 9239 *
cparata 0:f27ce43dee4f 9240 * @param ctx read / write interface definitions
cparata 0:f27ce43dee4f 9241 * @param val union of registers from STATUS_MASTER to
cparata 0:f27ce43dee4f 9242 *
cparata 0:f27ce43dee4f 9243 */
cparata 0:f27ce43dee4f 9244 int32_t lsm6dsox_sh_status_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 9245 lsm6dsox_status_master_t *val)
cparata 0:f27ce43dee4f 9246 {
cparata 0:f27ce43dee4f 9247 int32_t ret;
cparata 0:f27ce43dee4f 9248
cparata 0:f27ce43dee4f 9249 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
cparata 0:f27ce43dee4f 9250 if (ret == 0) {
cparata 0:f27ce43dee4f 9251 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_MASTER, (uint8_t*) val, 1);
cparata 0:f27ce43dee4f 9252 }
cparata 0:f27ce43dee4f 9253 if (ret == 0) {
cparata 0:f27ce43dee4f 9254 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
cparata 0:f27ce43dee4f 9255 }
cparata 0:f27ce43dee4f 9256
cparata 0:f27ce43dee4f 9257 return ret;
cparata 0:f27ce43dee4f 9258 }
cparata 0:f27ce43dee4f 9259
cparata 0:f27ce43dee4f 9260 /**
cparata 0:f27ce43dee4f 9261 * @}
cparata 0:f27ce43dee4f 9262 *
cparata 0:f27ce43dee4f 9263 */
cparata 0:f27ce43dee4f 9264
cparata 0:f27ce43dee4f 9265 /**
cparata 0:f27ce43dee4f 9266 * @addtogroup Sensors for Smart Mobile Devices
cparata 0:f27ce43dee4f 9267 * @brief This section groups all the functions that manage the
cparata 0:f27ce43dee4f 9268 * Sensors for Smart Mobile Devices.
cparata 0:f27ce43dee4f 9269 * @{
cparata 0:f27ce43dee4f 9270 *
cparata 0:f27ce43dee4f 9271 */
cparata 0:f27ce43dee4f 9272
cparata 0:f27ce43dee4f 9273 /**
cparata 0:f27ce43dee4f 9274 * @brief s4s_tph_res: [set] Sensor synchronization time frame resolution
cparata 0:f27ce43dee4f 9275 *
cparata 0:f27ce43dee4f 9276 * @param *ctx read / write interface definitions
cparata 0:f27ce43dee4f 9277 * @param val change the values of tph_h_sel in LSM6DSOX_S4S_TPH_L
cparata 0:f27ce43dee4f 9278 *
cparata 0:f27ce43dee4f 9279 */
cparata 0:f27ce43dee4f 9280 int32_t lsm6dsox_s4s_tph_res_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 9281 lsm6dsox_s4s_tph_res_t val)
cparata 0:f27ce43dee4f 9282 {
cparata 0:f27ce43dee4f 9283 lsm6dsox_s4s_tph_l_t reg;
cparata 0:f27ce43dee4f 9284 int32_t ret;
cparata 0:f27ce43dee4f 9285
cparata 0:f27ce43dee4f 9286 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9287 if (ret == 0) {
cparata 0:f27ce43dee4f 9288 reg.tph_h_sel = (uint8_t)val;
cparata 0:f27ce43dee4f 9289 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9290 }
cparata 0:f27ce43dee4f 9291 return ret;
cparata 0:f27ce43dee4f 9292 }
cparata 0:f27ce43dee4f 9293
cparata 0:f27ce43dee4f 9294 /**
cparata 0:f27ce43dee4f 9295 * @brief s4s_tph_res: [get] Sensor synchronization time frame resolution
cparata 0:f27ce43dee4f 9296 *
cparata 0:f27ce43dee4f 9297 * @param *ctx read / write interface definitions
cparata 0:f27ce43dee4f 9298 * @param val get the values of tph_h_sel in LSM6DSOX_S4S_TPH_L
cparata 0:f27ce43dee4f 9299 *
cparata 0:f27ce43dee4f 9300 */
cparata 0:f27ce43dee4f 9301 int32_t lsm6dsox_s4s_tph_res_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 9302 lsm6dsox_s4s_tph_res_t *val)
cparata 0:f27ce43dee4f 9303 {
cparata 0:f27ce43dee4f 9304 lsm6dsox_s4s_tph_l_t reg;
cparata 0:f27ce43dee4f 9305 int32_t ret;
cparata 0:f27ce43dee4f 9306
cparata 0:f27ce43dee4f 9307 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9308 switch (reg.tph_h_sel) {
cparata 0:f27ce43dee4f 9309 case LSM6DSOX_S4S_TPH_7bit:
cparata 0:f27ce43dee4f 9310 *val = LSM6DSOX_S4S_TPH_7bit;
cparata 0:f27ce43dee4f 9311 break;
cparata 0:f27ce43dee4f 9312 case LSM6DSOX_S4S_TPH_15bit:
cparata 0:f27ce43dee4f 9313 *val = LSM6DSOX_S4S_TPH_15bit;
cparata 0:f27ce43dee4f 9314 break;
cparata 0:f27ce43dee4f 9315 default:
cparata 0:f27ce43dee4f 9316 *val = LSM6DSOX_S4S_TPH_7bit;
cparata 0:f27ce43dee4f 9317 break;
cparata 0:f27ce43dee4f 9318 }
cparata 0:f27ce43dee4f 9319
cparata 0:f27ce43dee4f 9320 return ret;
cparata 0:f27ce43dee4f 9321 }
cparata 0:f27ce43dee4f 9322
cparata 0:f27ce43dee4f 9323 /**
cparata 0:f27ce43dee4f 9324 * @brief s4s_tph_val: [set] Sensor synchronization time frame
cparata 0:f27ce43dee4f 9325 *
cparata 0:f27ce43dee4f 9326 * @param *ctx read / write interface definitions
cparata 0:f27ce43dee4f 9327 * @param val change the values of tph_l in S4S_TPH_L and
cparata 0:f27ce43dee4f 9328 * tph_h in S4S_TPH_H
cparata 0:f27ce43dee4f 9329 *
cparata 0:f27ce43dee4f 9330 */
cparata 0:f27ce43dee4f 9331 int32_t lsm6dsox_s4s_tph_val_set(lsm6dsox_ctx_t *ctx, uint16_t val)
cparata 0:f27ce43dee4f 9332 {
cparata 0:f27ce43dee4f 9333 lsm6dsox_s4s_tph_l_t s4s_tph_l;
cparata 0:f27ce43dee4f 9334 lsm6dsox_s4s_tph_h_t s4s_tph_h;
cparata 0:f27ce43dee4f 9335 int32_t ret;
cparata 0:f27ce43dee4f 9336
cparata 0:f27ce43dee4f 9337 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
cparata 0:f27ce43dee4f 9338 if (ret == 0) {
cparata 0:f27ce43dee4f 9339 s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
cparata 0:f27ce43dee4f 9340 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
cparata 0:f27ce43dee4f 9341 }
cparata 0:f27ce43dee4f 9342 if (ret == 0) {
cparata 0:f27ce43dee4f 9343 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1);
cparata 0:f27ce43dee4f 9344 s4s_tph_h.tph_h = (uint8_t)(val & 0x7F80U) >> 7;
cparata 0:f27ce43dee4f 9345 }
cparata 0:f27ce43dee4f 9346 if (ret == 0) {
cparata 0:f27ce43dee4f 9347 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1);
cparata 0:f27ce43dee4f 9348 }
cparata 0:f27ce43dee4f 9349 return ret;
cparata 0:f27ce43dee4f 9350 }
cparata 0:f27ce43dee4f 9351
cparata 0:f27ce43dee4f 9352 /**
cparata 0:f27ce43dee4f 9353 * @brief s4s_tph_val: [get] Sensor synchronization time frame.
cparata 0:f27ce43dee4f 9354 *
cparata 0:f27ce43dee4f 9355 * @param *ctx read / write interface definitions
cparata 0:f27ce43dee4f 9356 * @param val get the values of tph_l in S4S_TPH_L and
cparata 0:f27ce43dee4f 9357 * tph_h in S4S_TPH_H
cparata 0:f27ce43dee4f 9358 *
cparata 0:f27ce43dee4f 9359 */
cparata 0:f27ce43dee4f 9360 int32_t lsm6dsox_s4s_tph_val_get(lsm6dsox_ctx_t *ctx, uint16_t *val)
cparata 0:f27ce43dee4f 9361 {
cparata 0:f27ce43dee4f 9362 lsm6dsox_s4s_tph_l_t s4s_tph_l;
cparata 0:f27ce43dee4f 9363 lsm6dsox_s4s_tph_h_t s4s_tph_h;
cparata 0:f27ce43dee4f 9364 int32_t ret;
cparata 0:f27ce43dee4f 9365
cparata 0:f27ce43dee4f 9366 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1);
cparata 0:f27ce43dee4f 9367 if (ret == 0) {
cparata 0:f27ce43dee4f 9368 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1);
cparata 0:f27ce43dee4f 9369 *val = s4s_tph_h.tph_h;
cparata 0:f27ce43dee4f 9370 *val = *val << 7;
cparata 0:f27ce43dee4f 9371 *val += s4s_tph_l.tph_l;
cparata 0:f27ce43dee4f 9372 }
cparata 0:f27ce43dee4f 9373 return ret;
cparata 0:f27ce43dee4f 9374 }
cparata 0:f27ce43dee4f 9375
cparata 0:f27ce43dee4f 9376 /**
cparata 0:f27ce43dee4f 9377 * @brief s4s_res_ratio: [set]Sensor synchronization resolution
cparata 0:f27ce43dee4f 9378 * ratio register.
cparata 0:f27ce43dee4f 9379 *
cparata 0:f27ce43dee4f 9380 * @param *ctx read / write interface definitions.
cparata 0:f27ce43dee4f 9381 * @param val change the values of rr in S4S_RR.
cparata 0:f27ce43dee4f 9382 *
cparata 0:f27ce43dee4f 9383 */
cparata 0:f27ce43dee4f 9384 int32_t lsm6dsox_s4s_res_ratio_set(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 9385 lsm6dsox_s4s_res_ratio_t val)
cparata 0:f27ce43dee4f 9386 {
cparata 0:f27ce43dee4f 9387 lsm6dsox_s4s_rr_t reg;
cparata 0:f27ce43dee4f 9388 int32_t ret;
cparata 0:f27ce43dee4f 9389
cparata 0:f27ce43dee4f 9390 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9391 if (ret == 0) {
cparata 0:f27ce43dee4f 9392 reg.rr = (uint8_t)val;
cparata 0:f27ce43dee4f 9393 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9394 }
cparata 0:f27ce43dee4f 9395 return ret;
cparata 0:f27ce43dee4f 9396 }
cparata 0:f27ce43dee4f 9397
cparata 0:f27ce43dee4f 9398 /**
cparata 0:f27ce43dee4f 9399 * @brief s4s_res_ratio: [get]Sensor synchronization resolution
cparata 0:f27ce43dee4f 9400 * ratio register.
cparata 0:f27ce43dee4f 9401 *
cparata 0:f27ce43dee4f 9402 * @param *ctx read / write interface definitions
cparata 0:f27ce43dee4f 9403 * @param val get the values of rr in S4S_RR
cparata 0:f27ce43dee4f 9404 *
cparata 0:f27ce43dee4f 9405 */
cparata 0:f27ce43dee4f 9406 int32_t lsm6dsox_s4s_res_ratio_get(lsm6dsox_ctx_t *ctx,
cparata 0:f27ce43dee4f 9407 lsm6dsox_s4s_res_ratio_t *val)
cparata 0:f27ce43dee4f 9408 {
cparata 0:f27ce43dee4f 9409 lsm6dsox_s4s_rr_t reg;
cparata 0:f27ce43dee4f 9410 int32_t ret;
cparata 0:f27ce43dee4f 9411
cparata 0:f27ce43dee4f 9412 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9413 switch (reg.rr) {
cparata 0:f27ce43dee4f 9414 case LSM6DSOX_S4S_DT_RES_11:
cparata 0:f27ce43dee4f 9415 *val = LSM6DSOX_S4S_DT_RES_11;
cparata 0:f27ce43dee4f 9416 break;
cparata 0:f27ce43dee4f 9417 case LSM6DSOX_S4S_DT_RES_12:
cparata 0:f27ce43dee4f 9418 *val = LSM6DSOX_S4S_DT_RES_12;
cparata 0:f27ce43dee4f 9419 break;
cparata 0:f27ce43dee4f 9420 case LSM6DSOX_S4S_DT_RES_13:
cparata 0:f27ce43dee4f 9421 *val = LSM6DSOX_S4S_DT_RES_13;
cparata 0:f27ce43dee4f 9422 break;
cparata 0:f27ce43dee4f 9423 case LSM6DSOX_S4S_DT_RES_14:
cparata 0:f27ce43dee4f 9424 *val = LSM6DSOX_S4S_DT_RES_14;
cparata 0:f27ce43dee4f 9425 break;
cparata 0:f27ce43dee4f 9426 default:
cparata 0:f27ce43dee4f 9427 *val = LSM6DSOX_S4S_DT_RES_11;
cparata 0:f27ce43dee4f 9428 break;
cparata 0:f27ce43dee4f 9429 }
cparata 0:f27ce43dee4f 9430 return ret;
cparata 0:f27ce43dee4f 9431 }
cparata 0:f27ce43dee4f 9432
cparata 0:f27ce43dee4f 9433 /**
cparata 0:f27ce43dee4f 9434 * @brief s4s_command: [set] s4s master command.
cparata 0:f27ce43dee4f 9435 *
cparata 0:f27ce43dee4f 9436 * @param *ctx read / write interface definitions.
cparata 0:f27ce43dee4f 9437 * @param val change the values of S4S_ST_CMD_CODE.
cparata 0:f27ce43dee4f 9438 *
cparata 0:f27ce43dee4f 9439 */
cparata 0:f27ce43dee4f 9440 int32_t lsm6dsox_s4s_command_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 9441 {
cparata 0:f27ce43dee4f 9442 lsm6dsox_s4s_st_cmd_code_t reg;
cparata 0:f27ce43dee4f 9443 int32_t ret;
cparata 0:f27ce43dee4f 9444
cparata 0:f27ce43dee4f 9445 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9446
cparata 0:f27ce43dee4f 9447 if (ret == 0) {
cparata 0:f27ce43dee4f 9448 reg.s4s_st_cmd_code = val;
cparata 0:f27ce43dee4f 9449 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9450 }
cparata 0:f27ce43dee4f 9451 return ret;
cparata 0:f27ce43dee4f 9452 }
cparata 0:f27ce43dee4f 9453
cparata 0:f27ce43dee4f 9454 /**
cparata 0:f27ce43dee4f 9455 * @brief s4s_command: [get] s4s master command.
cparata 0:f27ce43dee4f 9456 *
cparata 0:f27ce43dee4f 9457 * @param *ctx read / write interface definitions.
cparata 0:f27ce43dee4f 9458 * @param val get the values of S4S_ST_CMD_CODE.
cparata 0:f27ce43dee4f 9459 *
cparata 0:f27ce43dee4f 9460 */
cparata 0:f27ce43dee4f 9461 int32_t lsm6dsox_s4s_command_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 9462 {
cparata 0:f27ce43dee4f 9463 lsm6dsox_s4s_st_cmd_code_t reg;
cparata 0:f27ce43dee4f 9464 int32_t ret;
cparata 0:f27ce43dee4f 9465
cparata 0:f27ce43dee4f 9466 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9467 *val = reg.s4s_st_cmd_code;
cparata 0:f27ce43dee4f 9468
cparata 0:f27ce43dee4f 9469 return ret;
cparata 0:f27ce43dee4f 9470 }
cparata 0:f27ce43dee4f 9471
cparata 0:f27ce43dee4f 9472 /**
cparata 0:f27ce43dee4f 9473 * @brief s4s_dt: [set] S4S DT register.
cparata 0:f27ce43dee4f 9474 *
cparata 0:f27ce43dee4f 9475 * @param *ctx read / write interface definitions.
cparata 0:f27ce43dee4f 9476 * @param val change the values of S4S_DT_REG.
cparata 0:f27ce43dee4f 9477 *
cparata 0:f27ce43dee4f 9478 */
cparata 0:f27ce43dee4f 9479 int32_t lsm6dsox_s4s_dt_set(lsm6dsox_ctx_t *ctx, uint8_t val)
cparata 0:f27ce43dee4f 9480 {
cparata 0:f27ce43dee4f 9481 lsm6dsox_s4s_dt_reg_t reg;
cparata 0:f27ce43dee4f 9482 int32_t ret;
cparata 0:f27ce43dee4f 9483
cparata 0:f27ce43dee4f 9484 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9485 if (ret == 0) {
cparata 0:f27ce43dee4f 9486 reg.dt = val;
cparata 0:f27ce43dee4f 9487 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9488 }
cparata 0:f27ce43dee4f 9489 return ret;
cparata 0:f27ce43dee4f 9490 }
cparata 0:f27ce43dee4f 9491
cparata 0:f27ce43dee4f 9492 /**
cparata 0:f27ce43dee4f 9493 * @brief s4s_dt: [get] S4S DT register.
cparata 0:f27ce43dee4f 9494 *
cparata 0:f27ce43dee4f 9495 * @param *ctx read / write interface definitions.
cparata 0:f27ce43dee4f 9496 * @param val get the values of S4S_DT_REG.
cparata 0:f27ce43dee4f 9497 *
cparata 0:f27ce43dee4f 9498 */
cparata 0:f27ce43dee4f 9499 int32_t lsm6dsox_s4s_dt_get(lsm6dsox_ctx_t *ctx, uint8_t *val)
cparata 0:f27ce43dee4f 9500 {
cparata 0:f27ce43dee4f 9501 lsm6dsox_s4s_dt_reg_t reg;
cparata 0:f27ce43dee4f 9502 int32_t ret;
cparata 0:f27ce43dee4f 9503
cparata 0:f27ce43dee4f 9504 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)&reg, 1);
cparata 0:f27ce43dee4f 9505 *val = reg.dt;
cparata 0:f27ce43dee4f 9506
cparata 0:f27ce43dee4f 9507 return ret;
cparata 0:f27ce43dee4f 9508 }
cparata 0:f27ce43dee4f 9509
cparata 0:f27ce43dee4f 9510 /**
cparata 0:f27ce43dee4f 9511 * @}
cparata 0:f27ce43dee4f 9512 *
cparata 0:f27ce43dee4f 9513 */
cparata 0:f27ce43dee4f 9514
cparata 0:f27ce43dee4f 9515 /**
cparata 0:f27ce43dee4f 9516 * @}
cparata 0:f27ce43dee4f 9517 *
cparata 0:f27ce43dee4f 9518 */
cparata 0:f27ce43dee4f 9519
cparata 0:f27ce43dee4f 9520 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/