LSM6DSO - iNEMO inertial module: 3D accelerometer and 3D gy…

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iNEMO inertial module: 3D accelerometer and 3D gyroscope.

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3

lsm6dso_reg.c@4:77faf76e3cd8, 2020-10-29 (annotated)

Committer:: cparata
Date:: Thu Oct 29 12:50:52 2020 +0000
Revision:: 4:77faf76e3cd8
Parent:: 3:4274d9103f1d
Child:: 6:4774b86385e5

Update PID and add low power modes

Who changed what in which revision?

User	Revision	Line number	New contents of line
cparata	0:6d69e896ce38	1	/*
cparata	4:77faf76e3cd8	2	******************************************************************************
cparata	4:77faf76e3cd8	3	* @file lsm6dso_reg.c
cparata	4:77faf76e3cd8	4	* @author Sensors Software Solution Team
cparata	4:77faf76e3cd8	5	* @brief LSM6DSO driver file
cparata	4:77faf76e3cd8	6	******************************************************************************
cparata	4:77faf76e3cd8	7	* @attention
cparata	4:77faf76e3cd8	8	*
cparata	4:77faf76e3cd8	9	* <h2><center>© Copyright (c) 2019 STMicroelectronics.
cparata	4:77faf76e3cd8	10	* All rights reserved.</center></h2>
cparata	4:77faf76e3cd8	11	*
cparata	4:77faf76e3cd8	12	* This software component is licensed by ST under BSD 3-Clause license,
cparata	4:77faf76e3cd8	13	* the "License"; You may not use this file except in compliance with the
cparata	4:77faf76e3cd8	14	* License. You may obtain a copy of the License at:
cparata	4:77faf76e3cd8	15	* opensource.org/licenses/BSD-3-Clause
cparata	4:77faf76e3cd8	16	*
cparata	4:77faf76e3cd8	17	******************************************************************************
cparata	4:77faf76e3cd8	18	*/
cparata	0:6d69e896ce38	19
cparata	0:6d69e896ce38	20	#include "lsm6dso_reg.h"
cparata	0:6d69e896ce38	21
cparata	0:6d69e896ce38	22	/**
cparata	0:6d69e896ce38	23	* @defgroup LSM6DSO
cparata	0:6d69e896ce38	24	* @brief This file provides a set of functions needed to drive the
cparata	0:6d69e896ce38	25	* lsm6dso enhanced inertial module.
cparata	0:6d69e896ce38	26	* @{
cparata	0:6d69e896ce38	27	*
cparata	0:6d69e896ce38	28	*/
cparata	0:6d69e896ce38	29
cparata	0:6d69e896ce38	30	/**
cparata	0:6d69e896ce38	31	* @defgroup LSM6DSO_Interfaces_Functions
cparata	0:6d69e896ce38	32	* @brief This section provide a set of functions used to read and
cparata	0:6d69e896ce38	33	* write a generic register of the device.
cparata	0:6d69e896ce38	34	* MANDATORY: return 0 -> no Error.
cparata	0:6d69e896ce38	35	* @{
cparata	0:6d69e896ce38	36	*
cparata	0:6d69e896ce38	37	*/
cparata	0:6d69e896ce38	38
cparata	0:6d69e896ce38	39	/**
cparata	0:6d69e896ce38	40	* @brief Read generic device register
cparata	0:6d69e896ce38	41	*
cparata	0:6d69e896ce38	42	* @param ctx read / write interface definitions(ptr)
cparata	0:6d69e896ce38	43	* @param reg register to read
cparata	0:6d69e896ce38	44	* @param data pointer to buffer that store the data read(ptr)
cparata	0:6d69e896ce38	45	* @param len number of consecutive register to read
cparata	0:6d69e896ce38	46	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:6d69e896ce38	47	*
cparata	0:6d69e896ce38	48	*/
cparata	4:77faf76e3cd8	49	int32_t lsm6dso_read_reg(lsm6dso_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:6d69e896ce38	50	uint16_t len)
cparata	0:6d69e896ce38	51	{
cparata	4:77faf76e3cd8	52	int32_t ret;
cparata	4:77faf76e3cd8	53	ret = ctx->read_reg(ctx->handle, reg, data, len);
cparata	4:77faf76e3cd8	54	return ret;
cparata	0:6d69e896ce38	55	}
cparata	0:6d69e896ce38	56
cparata	0:6d69e896ce38	57	/**
cparata	0:6d69e896ce38	58	* @brief Write generic device register
cparata	0:6d69e896ce38	59	*
cparata	0:6d69e896ce38	60	* @param ctx read / write interface definitions(ptr)
cparata	0:6d69e896ce38	61	* @param reg register to write
cparata	0:6d69e896ce38	62	* @param data pointer to data to write in register reg(ptr)
cparata	0:6d69e896ce38	63	* @param len number of consecutive register to write
cparata	0:6d69e896ce38	64	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:6d69e896ce38	65	*
cparata	0:6d69e896ce38	66	*/
cparata	4:77faf76e3cd8	67	int32_t lsm6dso_write_reg(lsm6dso_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:6d69e896ce38	68	uint16_t len)
cparata	0:6d69e896ce38	69	{
cparata	4:77faf76e3cd8	70	int32_t ret;
cparata	4:77faf76e3cd8	71	ret = ctx->write_reg(ctx->handle, reg, data, len);
cparata	4:77faf76e3cd8	72	return ret;
cparata	0:6d69e896ce38	73	}
cparata	0:6d69e896ce38	74
cparata	0:6d69e896ce38	75	/**
cparata	0:6d69e896ce38	76	* @}
cparata	0:6d69e896ce38	77	*
cparata	0:6d69e896ce38	78	*/
cparata	0:6d69e896ce38	79
cparata	0:6d69e896ce38	80	/**
cparata	4:77faf76e3cd8	81	* @defgroup LSM6DSOX_Private_functions
cparata	4:77faf76e3cd8	82	* @brief Section collect all the utility functions needed by APIs.
cparata	4:77faf76e3cd8	83	* @{
cparata	4:77faf76e3cd8	84	*
cparata	4:77faf76e3cd8	85	*/
cparata	4:77faf76e3cd8	86
cparata	4:77faf76e3cd8	87	static void bytecpy(uint8_t target, uint8_t source)
cparata	4:77faf76e3cd8	88	{
cparata	4:77faf76e3cd8	89	if ( (target != NULL) && (source != NULL) ) {
cparata	4:77faf76e3cd8	90	target = source;
cparata	4:77faf76e3cd8	91	}
cparata	4:77faf76e3cd8	92	}
cparata	4:77faf76e3cd8	93
cparata	4:77faf76e3cd8	94	/**
cparata	0:6d69e896ce38	95	* @defgroup LSM6DSO_Sensitivity
cparata	0:6d69e896ce38	96	* @brief These functions convert raw-data into engineering units.
cparata	0:6d69e896ce38	97	* @{
cparata	0:6d69e896ce38	98	*
cparata	0:6d69e896ce38	99	*/
cparata	2:4d14e9edf37e	100	float_t lsm6dso_from_fs2_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	101	{
cparata	4:77faf76e3cd8	102	return ((float_t)lsb) * 0.061f;
cparata	2:4d14e9edf37e	103	}
cparata	2:4d14e9edf37e	104
cparata	2:4d14e9edf37e	105	float_t lsm6dso_from_fs4_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	106	{
cparata	4:77faf76e3cd8	107	return ((float_t)lsb) * 0.122f;
cparata	2:4d14e9edf37e	108	}
cparata	2:4d14e9edf37e	109
cparata	2:4d14e9edf37e	110	float_t lsm6dso_from_fs8_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	111	{
cparata	4:77faf76e3cd8	112	return ((float_t)lsb) * 0.244f;
cparata	2:4d14e9edf37e	113	}
cparata	2:4d14e9edf37e	114
cparata	2:4d14e9edf37e	115	float_t lsm6dso_from_fs16_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	116	{
cparata	4:77faf76e3cd8	117	return ((float_t)lsb) *0.488f;
cparata	2:4d14e9edf37e	118	}
cparata	2:4d14e9edf37e	119
cparata	2:4d14e9edf37e	120	float_t lsm6dso_from_fs125_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	121	{
cparata	4:77faf76e3cd8	122	return ((float_t)lsb) *4.375f;
cparata	2:4d14e9edf37e	123	}
cparata	2:4d14e9edf37e	124
cparata	2:4d14e9edf37e	125	float_t lsm6dso_from_fs500_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	126	{
cparata	4:77faf76e3cd8	127	return ((float_t)lsb) *17.50f;
cparata	2:4d14e9edf37e	128	}
cparata	2:4d14e9edf37e	129
cparata	2:4d14e9edf37e	130	float_t lsm6dso_from_fs250_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	131	{
cparata	4:77faf76e3cd8	132	return ((float_t)lsb) *8.750f;
cparata	2:4d14e9edf37e	133	}
cparata	2:4d14e9edf37e	134
cparata	2:4d14e9edf37e	135	float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	136	{
cparata	4:77faf76e3cd8	137	return ((float_t)lsb) *35.0f;
cparata	2:4d14e9edf37e	138	}
cparata	2:4d14e9edf37e	139
cparata	2:4d14e9edf37e	140	float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	141	{
cparata	4:77faf76e3cd8	142	return ((float_t)lsb) *70.0f;
cparata	2:4d14e9edf37e	143	}
cparata	2:4d14e9edf37e	144
cparata	2:4d14e9edf37e	145	float_t lsm6dso_from_lsb_to_celsius(int16_t lsb)
cparata	2:4d14e9edf37e	146	{
cparata	4:77faf76e3cd8	147	return (((float_t)lsb / 256.0f) + 25.0f);
cparata	2:4d14e9edf37e	148	}
cparata	2:4d14e9edf37e	149
cparata	2:4d14e9edf37e	150	float_t lsm6dso_from_lsb_to_nsec(int16_t lsb)
cparata	2:4d14e9edf37e	151	{
cparata	4:77faf76e3cd8	152	return ((float_t)lsb * 25000.0f);
cparata	0:6d69e896ce38	153	}
cparata	0:6d69e896ce38	154
cparata	0:6d69e896ce38	155	/**
cparata	0:6d69e896ce38	156	* @}
cparata	0:6d69e896ce38	157	*
cparata	0:6d69e896ce38	158	*/
cparata	0:6d69e896ce38	159
cparata	0:6d69e896ce38	160	/**
cparata	0:6d69e896ce38	161	* @defgroup LSM6DSO_Data_Generation
cparata	0:6d69e896ce38	162	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	163	* data generation.
cparata	0:6d69e896ce38	164	*
cparata	0:6d69e896ce38	165	*/
cparata	0:6d69e896ce38	166
cparata	0:6d69e896ce38	167	/**
cparata	0:6d69e896ce38	168	* @brief Accelerometer full-scale selection.[set]
cparata	0:6d69e896ce38	169	*
cparata	0:6d69e896ce38	170	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	171	* @param val change the values of fs_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	172	*
cparata	0:6d69e896ce38	173	*/
cparata	0:6d69e896ce38	174	int32_t lsm6dso_xl_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	175	lsm6dso_fs_xl_t val)
cparata	0:6d69e896ce38	176	{
cparata	4:77faf76e3cd8	177	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	178	int32_t ret;
cparata	4:77faf76e3cd8	179
cparata	4:77faf76e3cd8	180	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	181	if (ret == 0) {
cparata	4:77faf76e3cd8	182	reg.fs_xl = (uint8_t) val;
cparata	4:77faf76e3cd8	183	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	184	}
cparata	4:77faf76e3cd8	185	return ret;
cparata	0:6d69e896ce38	186	}
cparata	0:6d69e896ce38	187
cparata	0:6d69e896ce38	188	/**
cparata	0:6d69e896ce38	189	* @brief Accelerometer full-scale selection.[get]
cparata	0:6d69e896ce38	190	*
cparata	0:6d69e896ce38	191	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	192	* @param val Get the values of fs_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	193	*
cparata	0:6d69e896ce38	194	*/
cparata	0:6d69e896ce38	195	int32_t lsm6dso_xl_full_scale_get(lsm6dso_ctx_t ctx, lsm6dso_fs_xl_t val)
cparata	0:6d69e896ce38	196	{
cparata	4:77faf76e3cd8	197	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	198	int32_t ret;
cparata	4:77faf76e3cd8	199
cparata	4:77faf76e3cd8	200	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	201	switch (reg.fs_xl) {
cparata	4:77faf76e3cd8	202	case LSM6DSO_2g:
cparata	4:77faf76e3cd8	203	*val = LSM6DSO_2g;
cparata	4:77faf76e3cd8	204	break;
cparata	4:77faf76e3cd8	205	case LSM6DSO_16g:
cparata	4:77faf76e3cd8	206	*val = LSM6DSO_16g;
cparata	4:77faf76e3cd8	207	break;
cparata	4:77faf76e3cd8	208	case LSM6DSO_4g:
cparata	4:77faf76e3cd8	209	*val = LSM6DSO_4g;
cparata	4:77faf76e3cd8	210	break;
cparata	4:77faf76e3cd8	211	case LSM6DSO_8g:
cparata	4:77faf76e3cd8	212	*val = LSM6DSO_8g;
cparata	4:77faf76e3cd8	213	break;
cparata	4:77faf76e3cd8	214	default:
cparata	4:77faf76e3cd8	215	*val = LSM6DSO_2g;
cparata	4:77faf76e3cd8	216	break;
cparata	4:77faf76e3cd8	217	}
cparata	4:77faf76e3cd8	218
cparata	4:77faf76e3cd8	219	return ret;
cparata	0:6d69e896ce38	220	}
cparata	0:6d69e896ce38	221
cparata	0:6d69e896ce38	222	/**
cparata	0:6d69e896ce38	223	* @brief Accelerometer UI data rate selection.[set]
cparata	0:6d69e896ce38	224	*
cparata	0:6d69e896ce38	225	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	226	* @param val change the values of odr_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	227	*
cparata	0:6d69e896ce38	228	*/
cparata	0:6d69e896ce38	229	int32_t lsm6dso_xl_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t val)
cparata	0:6d69e896ce38	230	{
cparata	4:77faf76e3cd8	231	lsm6dso_odr_xl_t odr_xl = val;
cparata	4:77faf76e3cd8	232	lsm6dso_emb_fsm_enable_t fsm_enable;
cparata	4:77faf76e3cd8	233	lsm6dso_fsm_odr_t fsm_odr;
cparata	4:77faf76e3cd8	234	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	235	int32_t ret;
cparata	4:77faf76e3cd8	236
cparata	4:77faf76e3cd8	237	/* Check the Finite State Machine data rate constraints */
cparata	4:77faf76e3cd8	238	ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
cparata	4:77faf76e3cd8	239	if (ret == 0) {
cparata	4:77faf76e3cd8	240	if ( (fsm_enable.fsm_enable_a.fsm1_en \|
cparata	4:77faf76e3cd8	241	fsm_enable.fsm_enable_a.fsm2_en \|
cparata	4:77faf76e3cd8	242	fsm_enable.fsm_enable_a.fsm3_en \|
cparata	4:77faf76e3cd8	243	fsm_enable.fsm_enable_a.fsm4_en \|
cparata	4:77faf76e3cd8	244	fsm_enable.fsm_enable_a.fsm5_en \|
cparata	4:77faf76e3cd8	245	fsm_enable.fsm_enable_a.fsm6_en \|
cparata	4:77faf76e3cd8	246	fsm_enable.fsm_enable_a.fsm7_en \|
cparata	4:77faf76e3cd8	247	fsm_enable.fsm_enable_a.fsm8_en \|
cparata	4:77faf76e3cd8	248	fsm_enable.fsm_enable_b.fsm9_en \|
cparata	4:77faf76e3cd8	249	fsm_enable.fsm_enable_b.fsm10_en \|
cparata	4:77faf76e3cd8	250	fsm_enable.fsm_enable_b.fsm11_en \|
cparata	4:77faf76e3cd8	251	fsm_enable.fsm_enable_b.fsm12_en \|
cparata	4:77faf76e3cd8	252	fsm_enable.fsm_enable_b.fsm13_en \|
cparata	4:77faf76e3cd8	253	fsm_enable.fsm_enable_b.fsm14_en \|
cparata	4:77faf76e3cd8	254	fsm_enable.fsm_enable_b.fsm15_en \|
cparata	4:77faf76e3cd8	255	fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
cparata	4:77faf76e3cd8	256
cparata	4:77faf76e3cd8	257	ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
cparata	4:77faf76e3cd8	258	if (ret == 0) {
cparata	4:77faf76e3cd8	259	switch (fsm_odr) {
cparata	4:77faf76e3cd8	260	case LSM6DSO_ODR_FSM_12Hz5:
cparata	4:77faf76e3cd8	261
cparata	4:77faf76e3cd8	262	if (val == LSM6DSO_XL_ODR_OFF){
cparata	4:77faf76e3cd8	263	odr_xl = LSM6DSO_XL_ODR_12Hz5;
cparata	4:77faf76e3cd8	264
cparata	4:77faf76e3cd8	265	} else {
cparata	4:77faf76e3cd8	266	odr_xl = val;
cparata	4:77faf76e3cd8	267	}
cparata	4:77faf76e3cd8	268	break;
cparata	4:77faf76e3cd8	269	case LSM6DSO_ODR_FSM_26Hz:
cparata	4:77faf76e3cd8	270
cparata	4:77faf76e3cd8	271	if (val == LSM6DSO_XL_ODR_OFF){
cparata	4:77faf76e3cd8	272	odr_xl = LSM6DSO_XL_ODR_26Hz;
cparata	4:77faf76e3cd8	273
cparata	4:77faf76e3cd8	274	} else if (val == LSM6DSO_XL_ODR_12Hz5){
cparata	4:77faf76e3cd8	275	odr_xl = LSM6DSO_XL_ODR_26Hz;
cparata	4:77faf76e3cd8	276
cparata	4:77faf76e3cd8	277	} else {
cparata	4:77faf76e3cd8	278	odr_xl = val;
cparata	4:77faf76e3cd8	279	}
cparata	4:77faf76e3cd8	280	break;
cparata	4:77faf76e3cd8	281	case LSM6DSO_ODR_FSM_52Hz:
cparata	4:77faf76e3cd8	282
cparata	4:77faf76e3cd8	283	if (val == LSM6DSO_XL_ODR_OFF){
cparata	4:77faf76e3cd8	284	odr_xl = LSM6DSO_XL_ODR_52Hz;
cparata	4:77faf76e3cd8	285
cparata	4:77faf76e3cd8	286	} else if (val == LSM6DSO_XL_ODR_12Hz5){
cparata	4:77faf76e3cd8	287	odr_xl = LSM6DSO_XL_ODR_52Hz;
cparata	4:77faf76e3cd8	288
cparata	4:77faf76e3cd8	289	} else if (val == LSM6DSO_XL_ODR_26Hz){
cparata	4:77faf76e3cd8	290	odr_xl = LSM6DSO_XL_ODR_52Hz;
cparata	4:77faf76e3cd8	291
cparata	4:77faf76e3cd8	292	} else {
cparata	4:77faf76e3cd8	293	odr_xl = val;
cparata	4:77faf76e3cd8	294	}
cparata	4:77faf76e3cd8	295	break;
cparata	4:77faf76e3cd8	296	case LSM6DSO_ODR_FSM_104Hz:
cparata	4:77faf76e3cd8	297
cparata	4:77faf76e3cd8	298	if (val == LSM6DSO_XL_ODR_OFF){
cparata	4:77faf76e3cd8	299	odr_xl = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	300
cparata	4:77faf76e3cd8	301	} else if (val == LSM6DSO_XL_ODR_12Hz5){
cparata	4:77faf76e3cd8	302	odr_xl = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	303
cparata	4:77faf76e3cd8	304	} else if (val == LSM6DSO_XL_ODR_26Hz){
cparata	4:77faf76e3cd8	305	odr_xl = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	306
cparata	4:77faf76e3cd8	307	} else if (val == LSM6DSO_XL_ODR_52Hz){
cparata	4:77faf76e3cd8	308	odr_xl = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	309
cparata	4:77faf76e3cd8	310	} else {
cparata	4:77faf76e3cd8	311	odr_xl = val;
cparata	4:77faf76e3cd8	312	}
cparata	4:77faf76e3cd8	313	break;
cparata	4:77faf76e3cd8	314	default:
cparata	4:77faf76e3cd8	315	odr_xl = val;
cparata	4:77faf76e3cd8	316	break;
cparata	4:77faf76e3cd8	317	}
cparata	4:77faf76e3cd8	318	}
cparata	3:4274d9103f1d	319	}
cparata	4:77faf76e3cd8	320	}
cparata	4:77faf76e3cd8	321	if (ret == 0) {
cparata	4:77faf76e3cd8	322	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	323	}
cparata	4:77faf76e3cd8	324	if (ret == 0) {
cparata	4:77faf76e3cd8	325	reg.odr_xl = (uint8_t) odr_xl;
cparata	4:77faf76e3cd8	326	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	327	}
cparata	4:77faf76e3cd8	328	return ret;
cparata	0:6d69e896ce38	329	}
cparata	0:6d69e896ce38	330
cparata	0:6d69e896ce38	331	/**
cparata	0:6d69e896ce38	332	* @brief Accelerometer UI data rate selection.[get]
cparata	0:6d69e896ce38	333	*
cparata	0:6d69e896ce38	334	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	335	* @param val Get the values of odr_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	336	*
cparata	0:6d69e896ce38	337	*/
cparata	0:6d69e896ce38	338	int32_t lsm6dso_xl_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_odr_xl_t val)
cparata	0:6d69e896ce38	339	{
cparata	4:77faf76e3cd8	340	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	341	int32_t ret;
cparata	4:77faf76e3cd8	342
cparata	4:77faf76e3cd8	343	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	344
cparata	4:77faf76e3cd8	345	switch (reg.odr_xl) {
cparata	4:77faf76e3cd8	346	case LSM6DSO_XL_ODR_OFF:
cparata	4:77faf76e3cd8	347	*val = LSM6DSO_XL_ODR_OFF;
cparata	4:77faf76e3cd8	348	break;
cparata	4:77faf76e3cd8	349	case LSM6DSO_XL_ODR_12Hz5:
cparata	4:77faf76e3cd8	350	*val = LSM6DSO_XL_ODR_12Hz5;
cparata	4:77faf76e3cd8	351	break;
cparata	4:77faf76e3cd8	352	case LSM6DSO_XL_ODR_26Hz:
cparata	4:77faf76e3cd8	353	*val = LSM6DSO_XL_ODR_26Hz;
cparata	4:77faf76e3cd8	354	break;
cparata	4:77faf76e3cd8	355	case LSM6DSO_XL_ODR_52Hz:
cparata	4:77faf76e3cd8	356	*val = LSM6DSO_XL_ODR_52Hz;
cparata	4:77faf76e3cd8	357	break;
cparata	4:77faf76e3cd8	358	case LSM6DSO_XL_ODR_104Hz:
cparata	4:77faf76e3cd8	359	*val = LSM6DSO_XL_ODR_104Hz;
cparata	4:77faf76e3cd8	360	break;
cparata	4:77faf76e3cd8	361	case LSM6DSO_XL_ODR_208Hz:
cparata	4:77faf76e3cd8	362	*val = LSM6DSO_XL_ODR_208Hz;
cparata	4:77faf76e3cd8	363	break;
cparata	4:77faf76e3cd8	364	case LSM6DSO_XL_ODR_417Hz:
cparata	4:77faf76e3cd8	365	*val = LSM6DSO_XL_ODR_417Hz;
cparata	4:77faf76e3cd8	366	break;
cparata	4:77faf76e3cd8	367	case LSM6DSO_XL_ODR_833Hz:
cparata	4:77faf76e3cd8	368	*val = LSM6DSO_XL_ODR_833Hz;
cparata	4:77faf76e3cd8	369	break;
cparata	4:77faf76e3cd8	370	case LSM6DSO_XL_ODR_1667Hz:
cparata	4:77faf76e3cd8	371	*val = LSM6DSO_XL_ODR_1667Hz;
cparata	4:77faf76e3cd8	372	break;
cparata	4:77faf76e3cd8	373	case LSM6DSO_XL_ODR_3333Hz:
cparata	4:77faf76e3cd8	374	*val = LSM6DSO_XL_ODR_3333Hz;
cparata	4:77faf76e3cd8	375	break;
cparata	4:77faf76e3cd8	376	case LSM6DSO_XL_ODR_6667Hz:
cparata	4:77faf76e3cd8	377	*val = LSM6DSO_XL_ODR_6667Hz;
cparata	4:77faf76e3cd8	378	break;
cparata	4:77faf76e3cd8	379	case LSM6DSO_XL_ODR_1Hz6:
cparata	4:77faf76e3cd8	380	*val = LSM6DSO_XL_ODR_1Hz6;
cparata	4:77faf76e3cd8	381	break;
cparata	4:77faf76e3cd8	382	default:
cparata	4:77faf76e3cd8	383	*val = LSM6DSO_XL_ODR_OFF;
cparata	4:77faf76e3cd8	384	break;
cparata	4:77faf76e3cd8	385	}
cparata	4:77faf76e3cd8	386	return ret;
cparata	0:6d69e896ce38	387	}
cparata	0:6d69e896ce38	388
cparata	0:6d69e896ce38	389	/**
cparata	0:6d69e896ce38	390	* @brief Gyroscope UI chain full-scale selection.[set]
cparata	0:6d69e896ce38	391	*
cparata	0:6d69e896ce38	392	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	393	* @param val change the values of fs_g in reg CTRL2_G
cparata	0:6d69e896ce38	394	*
cparata	0:6d69e896ce38	395	*/
cparata	0:6d69e896ce38	396	int32_t lsm6dso_gy_full_scale_set(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t val)
cparata	0:6d69e896ce38	397	{
cparata	4:77faf76e3cd8	398	lsm6dso_ctrl2_g_t reg;
cparata	4:77faf76e3cd8	399	int32_t ret;
cparata	4:77faf76e3cd8	400
cparata	4:77faf76e3cd8	401	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	402	if (ret == 0) {
cparata	4:77faf76e3cd8	403	reg.fs_g = (uint8_t) val;
cparata	4:77faf76e3cd8	404	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	405	}
cparata	4:77faf76e3cd8	406
cparata	4:77faf76e3cd8	407	return ret;
cparata	0:6d69e896ce38	408	}
cparata	0:6d69e896ce38	409
cparata	0:6d69e896ce38	410	/**
cparata	0:6d69e896ce38	411	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:6d69e896ce38	412	*
cparata	0:6d69e896ce38	413	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	414	* @param val Get the values of fs_g in reg CTRL2_G
cparata	0:6d69e896ce38	415	*
cparata	0:6d69e896ce38	416	*/
cparata	0:6d69e896ce38	417	int32_t lsm6dso_gy_full_scale_get(lsm6dso_ctx_t ctx, lsm6dso_fs_g_t val)
cparata	0:6d69e896ce38	418	{
cparata	4:77faf76e3cd8	419	lsm6dso_ctrl2_g_t reg;
cparata	4:77faf76e3cd8	420	int32_t ret;
cparata	4:77faf76e3cd8	421
cparata	4:77faf76e3cd8	422	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	423	switch (reg.fs_g) {
cparata	4:77faf76e3cd8	424	case LSM6DSO_250dps:
cparata	4:77faf76e3cd8	425	*val = LSM6DSO_250dps;
cparata	4:77faf76e3cd8	426	break;
cparata	4:77faf76e3cd8	427	case LSM6DSO_125dps:
cparata	4:77faf76e3cd8	428	*val = LSM6DSO_125dps;
cparata	4:77faf76e3cd8	429	break;
cparata	4:77faf76e3cd8	430	case LSM6DSO_500dps:
cparata	4:77faf76e3cd8	431	*val = LSM6DSO_500dps;
cparata	4:77faf76e3cd8	432	break;
cparata	4:77faf76e3cd8	433	case LSM6DSO_1000dps:
cparata	4:77faf76e3cd8	434	*val = LSM6DSO_1000dps;
cparata	4:77faf76e3cd8	435	break;
cparata	4:77faf76e3cd8	436	case LSM6DSO_2000dps:
cparata	4:77faf76e3cd8	437	*val = LSM6DSO_2000dps;
cparata	4:77faf76e3cd8	438	break;
cparata	4:77faf76e3cd8	439	default:
cparata	4:77faf76e3cd8	440	*val = LSM6DSO_250dps;
cparata	4:77faf76e3cd8	441	break;
cparata	4:77faf76e3cd8	442	}
cparata	4:77faf76e3cd8	443
cparata	4:77faf76e3cd8	444	return ret;
cparata	0:6d69e896ce38	445	}
cparata	0:6d69e896ce38	446
cparata	0:6d69e896ce38	447	/**
cparata	0:6d69e896ce38	448	* @brief Gyroscope UI data rate selection.[set]
cparata	0:6d69e896ce38	449	*
cparata	0:6d69e896ce38	450	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	451	* @param val change the values of odr_g in reg CTRL2_G
cparata	0:6d69e896ce38	452	*
cparata	0:6d69e896ce38	453	*/
cparata	0:6d69e896ce38	454	int32_t lsm6dso_gy_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t val)
cparata	0:6d69e896ce38	455	{
cparata	4:77faf76e3cd8	456	lsm6dso_odr_g_t odr_gy = val;
cparata	4:77faf76e3cd8	457	lsm6dso_emb_fsm_enable_t fsm_enable;
cparata	4:77faf76e3cd8	458	lsm6dso_fsm_odr_t fsm_odr;
cparata	4:77faf76e3cd8	459	lsm6dso_ctrl2_g_t reg;
cparata	4:77faf76e3cd8	460	int32_t ret;
cparata	4:77faf76e3cd8	461
cparata	4:77faf76e3cd8	462	/* Check the Finite State Machine data rate constraints */
cparata	4:77faf76e3cd8	463	ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
cparata	4:77faf76e3cd8	464	if (ret == 0) {
cparata	4:77faf76e3cd8	465	if ( (fsm_enable.fsm_enable_a.fsm1_en \|
cparata	4:77faf76e3cd8	466	fsm_enable.fsm_enable_a.fsm2_en \|
cparata	4:77faf76e3cd8	467	fsm_enable.fsm_enable_a.fsm3_en \|
cparata	4:77faf76e3cd8	468	fsm_enable.fsm_enable_a.fsm4_en \|
cparata	4:77faf76e3cd8	469	fsm_enable.fsm_enable_a.fsm5_en \|
cparata	4:77faf76e3cd8	470	fsm_enable.fsm_enable_a.fsm6_en \|
cparata	4:77faf76e3cd8	471	fsm_enable.fsm_enable_a.fsm7_en \|
cparata	4:77faf76e3cd8	472	fsm_enable.fsm_enable_a.fsm8_en \|
cparata	4:77faf76e3cd8	473	fsm_enable.fsm_enable_b.fsm9_en \|
cparata	4:77faf76e3cd8	474	fsm_enable.fsm_enable_b.fsm10_en \|
cparata	4:77faf76e3cd8	475	fsm_enable.fsm_enable_b.fsm11_en \|
cparata	4:77faf76e3cd8	476	fsm_enable.fsm_enable_b.fsm12_en \|
cparata	4:77faf76e3cd8	477	fsm_enable.fsm_enable_b.fsm13_en \|
cparata	4:77faf76e3cd8	478	fsm_enable.fsm_enable_b.fsm14_en \|
cparata	4:77faf76e3cd8	479	fsm_enable.fsm_enable_b.fsm15_en \|
cparata	4:77faf76e3cd8	480	fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){
cparata	4:77faf76e3cd8	481
cparata	4:77faf76e3cd8	482	ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
cparata	4:77faf76e3cd8	483	if (ret == 0) {
cparata	4:77faf76e3cd8	484	switch (fsm_odr) {
cparata	4:77faf76e3cd8	485	case LSM6DSO_ODR_FSM_12Hz5:
cparata	4:77faf76e3cd8	486
cparata	4:77faf76e3cd8	487	if (val == LSM6DSO_GY_ODR_OFF){
cparata	4:77faf76e3cd8	488	odr_gy = LSM6DSO_GY_ODR_12Hz5;
cparata	4:77faf76e3cd8	489
cparata	4:77faf76e3cd8	490	} else {
cparata	4:77faf76e3cd8	491	odr_gy = val;
cparata	4:77faf76e3cd8	492	}
cparata	4:77faf76e3cd8	493	break;
cparata	4:77faf76e3cd8	494	case LSM6DSO_ODR_FSM_26Hz:
cparata	4:77faf76e3cd8	495
cparata	4:77faf76e3cd8	496	if (val == LSM6DSO_GY_ODR_OFF){
cparata	4:77faf76e3cd8	497	odr_gy = LSM6DSO_GY_ODR_26Hz;
cparata	4:77faf76e3cd8	498
cparata	4:77faf76e3cd8	499	} else if (val == LSM6DSO_GY_ODR_12Hz5){
cparata	4:77faf76e3cd8	500	odr_gy = LSM6DSO_GY_ODR_26Hz;
cparata	4:77faf76e3cd8	501
cparata	4:77faf76e3cd8	502	} else {
cparata	4:77faf76e3cd8	503	odr_gy = val;
cparata	4:77faf76e3cd8	504	}
cparata	4:77faf76e3cd8	505	break;
cparata	4:77faf76e3cd8	506	case LSM6DSO_ODR_FSM_52Hz:
cparata	4:77faf76e3cd8	507
cparata	4:77faf76e3cd8	508	if (val == LSM6DSO_GY_ODR_OFF){
cparata	4:77faf76e3cd8	509	odr_gy = LSM6DSO_GY_ODR_52Hz;
cparata	4:77faf76e3cd8	510
cparata	4:77faf76e3cd8	511	} else if (val == LSM6DSO_GY_ODR_12Hz5){
cparata	4:77faf76e3cd8	512	odr_gy = LSM6DSO_GY_ODR_52Hz;
cparata	4:77faf76e3cd8	513
cparata	4:77faf76e3cd8	514	} else if (val == LSM6DSO_GY_ODR_26Hz){
cparata	4:77faf76e3cd8	515	odr_gy = LSM6DSO_GY_ODR_52Hz;
cparata	4:77faf76e3cd8	516
cparata	4:77faf76e3cd8	517	} else {
cparata	4:77faf76e3cd8	518	odr_gy = val;
cparata	4:77faf76e3cd8	519	}
cparata	4:77faf76e3cd8	520	break;
cparata	4:77faf76e3cd8	521	case LSM6DSO_ODR_FSM_104Hz:
cparata	4:77faf76e3cd8	522
cparata	4:77faf76e3cd8	523	if (val == LSM6DSO_GY_ODR_OFF){
cparata	4:77faf76e3cd8	524	odr_gy = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	525
cparata	4:77faf76e3cd8	526	} else if (val == LSM6DSO_GY_ODR_12Hz5){
cparata	4:77faf76e3cd8	527	odr_gy = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	528
cparata	4:77faf76e3cd8	529	} else if (val == LSM6DSO_GY_ODR_26Hz){
cparata	4:77faf76e3cd8	530	odr_gy = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	531
cparata	4:77faf76e3cd8	532	} else if (val == LSM6DSO_GY_ODR_52Hz){
cparata	4:77faf76e3cd8	533	odr_gy = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	534
cparata	4:77faf76e3cd8	535	} else {
cparata	4:77faf76e3cd8	536	odr_gy = val;
cparata	4:77faf76e3cd8	537	}
cparata	4:77faf76e3cd8	538	break;
cparata	4:77faf76e3cd8	539	default:
cparata	4:77faf76e3cd8	540	odr_gy = val;
cparata	4:77faf76e3cd8	541	break;
cparata	4:77faf76e3cd8	542	}
cparata	4:77faf76e3cd8	543	}
cparata	3:4274d9103f1d	544	}
cparata	4:77faf76e3cd8	545	}
cparata	4:77faf76e3cd8	546
cparata	4:77faf76e3cd8	547	if (ret == 0) {
cparata	4:77faf76e3cd8	548	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	549	}
cparata	4:77faf76e3cd8	550	if (ret == 0) {
cparata	4:77faf76e3cd8	551	reg.odr_g = (uint8_t) odr_gy;
cparata	4:77faf76e3cd8	552	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	553	}
cparata	4:77faf76e3cd8	554
cparata	4:77faf76e3cd8	555	return ret;
cparata	0:6d69e896ce38	556	}
cparata	0:6d69e896ce38	557
cparata	0:6d69e896ce38	558	/**
cparata	0:6d69e896ce38	559	* @brief Gyroscope UI data rate selection.[get]
cparata	0:6d69e896ce38	560	*
cparata	0:6d69e896ce38	561	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	562	* @param val Get the values of odr_g in reg CTRL2_G
cparata	0:6d69e896ce38	563	*
cparata	0:6d69e896ce38	564	*/
cparata	0:6d69e896ce38	565	int32_t lsm6dso_gy_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_odr_g_t val)
cparata	0:6d69e896ce38	566	{
cparata	4:77faf76e3cd8	567	lsm6dso_ctrl2_g_t reg;
cparata	4:77faf76e3cd8	568	int32_t ret;
cparata	4:77faf76e3cd8	569
cparata	4:77faf76e3cd8	570	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	571	switch (reg.odr_g) {
cparata	4:77faf76e3cd8	572	case LSM6DSO_GY_ODR_OFF:
cparata	4:77faf76e3cd8	573	*val = LSM6DSO_GY_ODR_OFF;
cparata	4:77faf76e3cd8	574	break;
cparata	4:77faf76e3cd8	575	case LSM6DSO_GY_ODR_12Hz5:
cparata	4:77faf76e3cd8	576	*val = LSM6DSO_GY_ODR_12Hz5;
cparata	4:77faf76e3cd8	577	break;
cparata	4:77faf76e3cd8	578	case LSM6DSO_GY_ODR_26Hz:
cparata	4:77faf76e3cd8	579	*val = LSM6DSO_GY_ODR_26Hz;
cparata	4:77faf76e3cd8	580	break;
cparata	4:77faf76e3cd8	581	case LSM6DSO_GY_ODR_52Hz:
cparata	4:77faf76e3cd8	582	*val = LSM6DSO_GY_ODR_52Hz;
cparata	4:77faf76e3cd8	583	break;
cparata	4:77faf76e3cd8	584	case LSM6DSO_GY_ODR_104Hz:
cparata	4:77faf76e3cd8	585	*val = LSM6DSO_GY_ODR_104Hz;
cparata	4:77faf76e3cd8	586	break;
cparata	4:77faf76e3cd8	587	case LSM6DSO_GY_ODR_208Hz:
cparata	4:77faf76e3cd8	588	*val = LSM6DSO_GY_ODR_208Hz;
cparata	4:77faf76e3cd8	589	break;
cparata	4:77faf76e3cd8	590	case LSM6DSO_GY_ODR_417Hz:
cparata	4:77faf76e3cd8	591	*val = LSM6DSO_GY_ODR_417Hz;
cparata	4:77faf76e3cd8	592	break;
cparata	4:77faf76e3cd8	593	case LSM6DSO_GY_ODR_833Hz:
cparata	4:77faf76e3cd8	594	*val = LSM6DSO_GY_ODR_833Hz;
cparata	4:77faf76e3cd8	595	break;
cparata	4:77faf76e3cd8	596	case LSM6DSO_GY_ODR_1667Hz:
cparata	4:77faf76e3cd8	597	*val = LSM6DSO_GY_ODR_1667Hz;
cparata	4:77faf76e3cd8	598	break;
cparata	4:77faf76e3cd8	599	case LSM6DSO_GY_ODR_3333Hz:
cparata	4:77faf76e3cd8	600	*val = LSM6DSO_GY_ODR_3333Hz;
cparata	4:77faf76e3cd8	601	break;
cparata	4:77faf76e3cd8	602	case LSM6DSO_GY_ODR_6667Hz:
cparata	4:77faf76e3cd8	603	*val = LSM6DSO_GY_ODR_6667Hz;
cparata	4:77faf76e3cd8	604	break;
cparata	4:77faf76e3cd8	605	default:
cparata	4:77faf76e3cd8	606	*val = LSM6DSO_GY_ODR_OFF;
cparata	4:77faf76e3cd8	607	break;
cparata	4:77faf76e3cd8	608	}
cparata	4:77faf76e3cd8	609	return ret;
cparata	0:6d69e896ce38	610	}
cparata	0:6d69e896ce38	611
cparata	0:6d69e896ce38	612	/**
cparata	0:6d69e896ce38	613	* @brief Block data update.[set]
cparata	0:6d69e896ce38	614	*
cparata	0:6d69e896ce38	615	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	616	* @param val change the values of bdu in reg CTRL3_C
cparata	0:6d69e896ce38	617	*
cparata	0:6d69e896ce38	618	*/
cparata	0:6d69e896ce38	619	int32_t lsm6dso_block_data_update_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	620	{
cparata	4:77faf76e3cd8	621	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	622	int32_t ret;
cparata	4:77faf76e3cd8	623
cparata	4:77faf76e3cd8	624	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	625	if (ret == 0) {
cparata	4:77faf76e3cd8	626	reg.bdu = val;
cparata	4:77faf76e3cd8	627	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	628	}
cparata	4:77faf76e3cd8	629	return ret;
cparata	0:6d69e896ce38	630	}
cparata	0:6d69e896ce38	631
cparata	0:6d69e896ce38	632	/**
cparata	0:6d69e896ce38	633	* @brief Block data update.[get]
cparata	0:6d69e896ce38	634	*
cparata	0:6d69e896ce38	635	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	636	* @param val change the values of bdu in reg CTRL3_C
cparata	0:6d69e896ce38	637	*
cparata	0:6d69e896ce38	638	*/
cparata	0:6d69e896ce38	639	int32_t lsm6dso_block_data_update_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	640	{
cparata	4:77faf76e3cd8	641	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	642	int32_t ret;
cparata	4:77faf76e3cd8	643
cparata	4:77faf76e3cd8	644	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	645	*val = reg.bdu;
cparata	4:77faf76e3cd8	646
cparata	4:77faf76e3cd8	647	return ret;
cparata	0:6d69e896ce38	648	}
cparata	0:6d69e896ce38	649
cparata	0:6d69e896ce38	650	/**
cparata	0:6d69e896ce38	651	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:6d69e896ce38	652	* Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
cparata	0:6d69e896ce38	653	*
cparata	0:6d69e896ce38	654	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	655	* @param val change the values of usr_off_w in reg CTRL6_C
cparata	0:6d69e896ce38	656	*
cparata	0:6d69e896ce38	657	*/
cparata	0:6d69e896ce38	658	int32_t lsm6dso_xl_offset_weight_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	659	lsm6dso_usr_off_w_t val)
cparata	0:6d69e896ce38	660	{
cparata	4:77faf76e3cd8	661	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	662	int32_t ret;
cparata	4:77faf76e3cd8	663
cparata	4:77faf76e3cd8	664	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	665	if (ret == 0) {
cparata	4:77faf76e3cd8	666	reg.usr_off_w = (uint8_t)val;
cparata	4:77faf76e3cd8	667	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	668	}
cparata	4:77faf76e3cd8	669	return ret;
cparata	0:6d69e896ce38	670	}
cparata	0:6d69e896ce38	671
cparata	0:6d69e896ce38	672	/**
cparata	0:6d69e896ce38	673	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:6d69e896ce38	674	* Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
cparata	0:6d69e896ce38	675	*
cparata	0:6d69e896ce38	676	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	677	* @param val Get the values of usr_off_w in reg CTRL6_C
cparata	0:6d69e896ce38	678	*
cparata	0:6d69e896ce38	679	*/
cparata	0:6d69e896ce38	680	int32_t lsm6dso_xl_offset_weight_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	681	lsm6dso_usr_off_w_t *val)
cparata	0:6d69e896ce38	682	{
cparata	4:77faf76e3cd8	683	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	684	int32_t ret;
cparata	4:77faf76e3cd8	685
cparata	4:77faf76e3cd8	686	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	687
cparata	4:77faf76e3cd8	688	switch (reg.usr_off_w) {
cparata	4:77faf76e3cd8	689	case LSM6DSO_LSb_1mg:
cparata	4:77faf76e3cd8	690	*val = LSM6DSO_LSb_1mg;
cparata	4:77faf76e3cd8	691	break;
cparata	4:77faf76e3cd8	692	case LSM6DSO_LSb_16mg:
cparata	4:77faf76e3cd8	693	*val = LSM6DSO_LSb_16mg;
cparata	4:77faf76e3cd8	694	break;
cparata	4:77faf76e3cd8	695	default:
cparata	4:77faf76e3cd8	696	*val = LSM6DSO_LSb_1mg;
cparata	4:77faf76e3cd8	697	break;
cparata	4:77faf76e3cd8	698	}
cparata	4:77faf76e3cd8	699	return ret;
cparata	0:6d69e896ce38	700	}
cparata	0:6d69e896ce38	701
cparata	0:6d69e896ce38	702	/**
cparata	0:6d69e896ce38	703	* @brief Accelerometer power mode.[set]
cparata	0:6d69e896ce38	704	*
cparata	0:6d69e896ce38	705	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	706	* @param val change the values of xl_hm_mode in
cparata	0:6d69e896ce38	707	* reg CTRL6_C
cparata	0:6d69e896ce38	708	*
cparata	0:6d69e896ce38	709	*/
cparata	0:6d69e896ce38	710	int32_t lsm6dso_xl_power_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	711	lsm6dso_xl_hm_mode_t val)
cparata	0:6d69e896ce38	712	{
cparata	4:77faf76e3cd8	713	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	4:77faf76e3cd8	714	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	4:77faf76e3cd8	715	int32_t ret;
cparata	4:77faf76e3cd8	716
cparata	4:77faf76e3cd8	717	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	4:77faf76e3cd8	718	if (ret == 0) {
cparata	4:77faf76e3cd8	719	ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
cparata	4:77faf76e3cd8	720	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	4:77faf76e3cd8	721	}
cparata	4:77faf76e3cd8	722	if (ret == 0) {
cparata	4:77faf76e3cd8	723	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	4:77faf76e3cd8	724	}
cparata	4:77faf76e3cd8	725	if (ret == 0) {
cparata	4:77faf76e3cd8	726	ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	727	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	4:77faf76e3cd8	728	}
cparata	4:77faf76e3cd8	729	return ret;
cparata	0:6d69e896ce38	730	}
cparata	0:6d69e896ce38	731
cparata	0:6d69e896ce38	732	/**
cparata	0:6d69e896ce38	733	* @brief Accelerometer power mode.[get]
cparata	0:6d69e896ce38	734	*
cparata	0:6d69e896ce38	735	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	736	* @param val Get the values of xl_hm_mode in reg CTRL6_C
cparata	0:6d69e896ce38	737	*
cparata	0:6d69e896ce38	738	*/
cparata	0:6d69e896ce38	739	int32_t lsm6dso_xl_power_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	740	lsm6dso_xl_hm_mode_t *val)
cparata	0:6d69e896ce38	741	{
cparata	4:77faf76e3cd8	742	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	4:77faf76e3cd8	743	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	4:77faf76e3cd8	744	int32_t ret;
cparata	4:77faf76e3cd8	745
cparata	4:77faf76e3cd8	746	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	4:77faf76e3cd8	747	if (ret == 0) {
cparata	4:77faf76e3cd8	748	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	4:77faf76e3cd8	749	switch ( (ctrl5_c.xl_ulp_en << 1) \| ctrl6_c.xl_hm_mode) {
cparata	4:77faf76e3cd8	750	case LSM6DSO_HIGH_PERFORMANCE_MD:
cparata	4:77faf76e3cd8	751	*val = LSM6DSO_HIGH_PERFORMANCE_MD;
cparata	4:77faf76e3cd8	752	break;
cparata	4:77faf76e3cd8	753	case LSM6DSO_LOW_NORMAL_POWER_MD:
cparata	4:77faf76e3cd8	754	*val = LSM6DSO_LOW_NORMAL_POWER_MD;
cparata	4:77faf76e3cd8	755	break;
cparata	4:77faf76e3cd8	756	case LSM6DSO_ULTRA_LOW_POWER_MD:
cparata	4:77faf76e3cd8	757	*val = LSM6DSO_ULTRA_LOW_POWER_MD;
cparata	4:77faf76e3cd8	758	break;
cparata	4:77faf76e3cd8	759	default:
cparata	4:77faf76e3cd8	760	*val = LSM6DSO_HIGH_PERFORMANCE_MD;
cparata	4:77faf76e3cd8	761	break;
cparata	3:4274d9103f1d	762	}
cparata	4:77faf76e3cd8	763	}
cparata	4:77faf76e3cd8	764	return ret;
cparata	0:6d69e896ce38	765	}
cparata	0:6d69e896ce38	766
cparata	0:6d69e896ce38	767	/**
cparata	0:6d69e896ce38	768	* @brief Operating mode for gyroscope.[set]
cparata	0:6d69e896ce38	769	*
cparata	0:6d69e896ce38	770	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	771	* @param val change the values of g_hm_mode in reg CTRL7_G
cparata	0:6d69e896ce38	772	*
cparata	0:6d69e896ce38	773	*/
cparata	0:6d69e896ce38	774	int32_t lsm6dso_gy_power_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	775	lsm6dso_g_hm_mode_t val)
cparata	0:6d69e896ce38	776	{
cparata	4:77faf76e3cd8	777	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	778	int32_t ret;
cparata	4:77faf76e3cd8	779
cparata	4:77faf76e3cd8	780	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	781	if (ret == 0) {
cparata	4:77faf76e3cd8	782	reg.g_hm_mode = (uint8_t)val;
cparata	4:77faf76e3cd8	783	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	784	}
cparata	4:77faf76e3cd8	785	return ret;
cparata	0:6d69e896ce38	786	}
cparata	0:6d69e896ce38	787
cparata	0:6d69e896ce38	788	/**
cparata	0:6d69e896ce38	789	* @brief Operating mode for gyroscope.[get]
cparata	0:6d69e896ce38	790	*
cparata	0:6d69e896ce38	791	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	792	* @param val Get the values of g_hm_mode in reg CTRL7_G
cparata	0:6d69e896ce38	793	*
cparata	0:6d69e896ce38	794	*/
cparata	0:6d69e896ce38	795	int32_t lsm6dso_gy_power_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	796	lsm6dso_g_hm_mode_t *val)
cparata	0:6d69e896ce38	797	{
cparata	4:77faf76e3cd8	798	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	799	int32_t ret;
cparata	4:77faf76e3cd8	800
cparata	4:77faf76e3cd8	801	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	802	switch (reg.g_hm_mode) {
cparata	4:77faf76e3cd8	803	case LSM6DSO_GY_HIGH_PERFORMANCE:
cparata	4:77faf76e3cd8	804	*val = LSM6DSO_GY_HIGH_PERFORMANCE;
cparata	4:77faf76e3cd8	805	break;
cparata	4:77faf76e3cd8	806	case LSM6DSO_GY_NORMAL:
cparata	4:77faf76e3cd8	807	*val = LSM6DSO_GY_NORMAL;
cparata	4:77faf76e3cd8	808	break;
cparata	4:77faf76e3cd8	809	default:
cparata	4:77faf76e3cd8	810	*val = LSM6DSO_GY_HIGH_PERFORMANCE;
cparata	4:77faf76e3cd8	811	break;
cparata	4:77faf76e3cd8	812	}
cparata	4:77faf76e3cd8	813	return ret;
cparata	0:6d69e896ce38	814	}
cparata	0:6d69e896ce38	815
cparata	0:6d69e896ce38	816	/**
cparata	0:6d69e896ce38	817	* @brief The STATUS_REG register is read by the primary interface.[get]
cparata	0:6d69e896ce38	818	*
cparata	0:6d69e896ce38	819	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	820	* @param val register STATUS_REG
cparata	0:6d69e896ce38	821	*
cparata	0:6d69e896ce38	822	*/
cparata	0:6d69e896ce38	823	int32_t lsm6dso_status_reg_get(lsm6dso_ctx_t ctx, lsm6dso_status_reg_t val)
cparata	0:6d69e896ce38	824	{
cparata	4:77faf76e3cd8	825	int32_t ret;
cparata	4:77faf76e3cd8	826	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*) val, 1);
cparata	4:77faf76e3cd8	827	return ret;
cparata	0:6d69e896ce38	828	}
cparata	0:6d69e896ce38	829
cparata	0:6d69e896ce38	830	/**
cparata	0:6d69e896ce38	831	* @brief Accelerometer new data available.[get]
cparata	0:6d69e896ce38	832	*
cparata	0:6d69e896ce38	833	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	834	* @param val change the values of xlda in reg STATUS_REG
cparata	0:6d69e896ce38	835	*
cparata	0:6d69e896ce38	836	*/
cparata	0:6d69e896ce38	837	int32_t lsm6dso_xl_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	838	{
cparata	4:77faf76e3cd8	839	lsm6dso_status_reg_t reg;
cparata	4:77faf76e3cd8	840	int32_t ret;
cparata	4:77faf76e3cd8	841
cparata	4:77faf76e3cd8	842	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	843	*val = reg.xlda;
cparata	4:77faf76e3cd8	844
cparata	4:77faf76e3cd8	845	return ret;
cparata	0:6d69e896ce38	846	}
cparata	0:6d69e896ce38	847
cparata	0:6d69e896ce38	848	/**
cparata	0:6d69e896ce38	849	* @brief Gyroscope new data available.[get]
cparata	0:6d69e896ce38	850	*
cparata	0:6d69e896ce38	851	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	852	* @param val change the values of gda in reg STATUS_REG
cparata	0:6d69e896ce38	853	*
cparata	0:6d69e896ce38	854	*/
cparata	0:6d69e896ce38	855	int32_t lsm6dso_gy_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	856	{
cparata	4:77faf76e3cd8	857	lsm6dso_status_reg_t reg;
cparata	4:77faf76e3cd8	858	int32_t ret;
cparata	4:77faf76e3cd8	859
cparata	4:77faf76e3cd8	860	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	861	*val = reg.gda;
cparata	4:77faf76e3cd8	862
cparata	4:77faf76e3cd8	863	return ret;
cparata	0:6d69e896ce38	864	}
cparata	0:6d69e896ce38	865
cparata	0:6d69e896ce38	866	/**
cparata	0:6d69e896ce38	867	* @brief Temperature new data available.[get]
cparata	0:6d69e896ce38	868	*
cparata	0:6d69e896ce38	869	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	870	* @param val change the values of tda in reg STATUS_REG
cparata	0:6d69e896ce38	871	*
cparata	0:6d69e896ce38	872	*/
cparata	0:6d69e896ce38	873	int32_t lsm6dso_temp_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	874	{
cparata	4:77faf76e3cd8	875	lsm6dso_status_reg_t reg;
cparata	4:77faf76e3cd8	876	int32_t ret;
cparata	4:77faf76e3cd8	877
cparata	4:77faf76e3cd8	878	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	879	*val = reg.tda;
cparata	4:77faf76e3cd8	880
cparata	4:77faf76e3cd8	881	return ret;
cparata	0:6d69e896ce38	882	}
cparata	0:6d69e896ce38	883
cparata	0:6d69e896ce38	884	/**
cparata	0:6d69e896ce38	885	* @brief Accelerometer X-axis user offset correction expressed in
cparata	0:6d69e896ce38	886	* two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	887	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	888	*
cparata	0:6d69e896ce38	889	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	890	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	891	*
cparata	0:6d69e896ce38	892	*/
cparata	0:6d69e896ce38	893	int32_t lsm6dso_xl_usr_offset_x_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	894	{
cparata	4:77faf76e3cd8	895	int32_t ret;
cparata	4:77faf76e3cd8	896	ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	897	return ret;
cparata	0:6d69e896ce38	898	}
cparata	0:6d69e896ce38	899
cparata	0:6d69e896ce38	900	/**
cparata	0:6d69e896ce38	901	* @brief Accelerometer X-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	902	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	903	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	904	*
cparata	0:6d69e896ce38	905	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	906	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	907	*
cparata	0:6d69e896ce38	908	*/
cparata	0:6d69e896ce38	909	int32_t lsm6dso_xl_usr_offset_x_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	910	{
cparata	4:77faf76e3cd8	911	int32_t ret;
cparata	4:77faf76e3cd8	912	ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	913	return ret;
cparata	0:6d69e896ce38	914	}
cparata	0:6d69e896ce38	915
cparata	0:6d69e896ce38	916	/**
cparata	0:6d69e896ce38	917	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	918	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	919	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	920	*
cparata	0:6d69e896ce38	921	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	922	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	923	*
cparata	0:6d69e896ce38	924	*/
cparata	0:6d69e896ce38	925	int32_t lsm6dso_xl_usr_offset_y_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	926	{
cparata	4:77faf76e3cd8	927	int32_t ret;
cparata	4:77faf76e3cd8	928	ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	929	return ret;
cparata	0:6d69e896ce38	930	}
cparata	0:6d69e896ce38	931
cparata	0:6d69e896ce38	932	/**
cparata	0:6d69e896ce38	933	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	934	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	935	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	936	*
cparata	0:6d69e896ce38	937	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	938	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	939	*
cparata	0:6d69e896ce38	940	*/
cparata	0:6d69e896ce38	941	int32_t lsm6dso_xl_usr_offset_y_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	942	{
cparata	4:77faf76e3cd8	943	int32_t ret;
cparata	4:77faf76e3cd8	944	ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	945	return ret;
cparata	0:6d69e896ce38	946	}
cparata	0:6d69e896ce38	947
cparata	0:6d69e896ce38	948	/**
cparata	0:6d69e896ce38	949	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	950	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	951	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	952	*
cparata	0:6d69e896ce38	953	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	954	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	955	*
cparata	0:6d69e896ce38	956	*/
cparata	0:6d69e896ce38	957	int32_t lsm6dso_xl_usr_offset_z_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	958	{
cparata	4:77faf76e3cd8	959	int32_t ret;
cparata	4:77faf76e3cd8	960	ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	961	return ret;
cparata	0:6d69e896ce38	962	}
cparata	0:6d69e896ce38	963
cparata	0:6d69e896ce38	964	/**
cparata	0:6d69e896ce38	965	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	966	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	967	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	968	*
cparata	0:6d69e896ce38	969	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	970	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	971	*
cparata	0:6d69e896ce38	972	*/
cparata	0:6d69e896ce38	973	int32_t lsm6dso_xl_usr_offset_z_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	974	{
cparata	4:77faf76e3cd8	975	int32_t ret;
cparata	4:77faf76e3cd8	976	ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
cparata	4:77faf76e3cd8	977	return ret;
cparata	0:6d69e896ce38	978	}
cparata	0:6d69e896ce38	979
cparata	0:6d69e896ce38	980	/**
cparata	0:6d69e896ce38	981	* @brief Enables user offset on out.[set]
cparata	0:6d69e896ce38	982	*
cparata	0:6d69e896ce38	983	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	984	* @param val change the values of usr_off_on_out in reg CTRL7_G
cparata	0:6d69e896ce38	985	*
cparata	0:6d69e896ce38	986	*/
cparata	0:6d69e896ce38	987	int32_t lsm6dso_xl_usr_offset_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	988	{
cparata	4:77faf76e3cd8	989	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	990	int32_t ret;
cparata	4:77faf76e3cd8	991
cparata	4:77faf76e3cd8	992	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	993	if (ret == 0) {
cparata	4:77faf76e3cd8	994	reg.usr_off_on_out = val;
cparata	4:77faf76e3cd8	995	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	996	}
cparata	4:77faf76e3cd8	997	return ret;
cparata	0:6d69e896ce38	998	}
cparata	0:6d69e896ce38	999
cparata	0:6d69e896ce38	1000	/**
cparata	0:6d69e896ce38	1001	* @brief User offset on out flag.[get]
cparata	0:6d69e896ce38	1002	*
cparata	0:6d69e896ce38	1003	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1004	* @param val values of usr_off_on_out in reg CTRL7_G
cparata	0:6d69e896ce38	1005	*
cparata	0:6d69e896ce38	1006	*/
cparata	0:6d69e896ce38	1007	int32_t lsm6dso_xl_usr_offset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1008	{
cparata	4:77faf76e3cd8	1009	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	1010	int32_t ret;
cparata	4:77faf76e3cd8	1011
cparata	4:77faf76e3cd8	1012	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1013	*val = reg.usr_off_on_out;
cparata	4:77faf76e3cd8	1014
cparata	4:77faf76e3cd8	1015	return ret;
cparata	0:6d69e896ce38	1016	}
cparata	0:6d69e896ce38	1017
cparata	0:6d69e896ce38	1018	/**
cparata	0:6d69e896ce38	1019	* @}
cparata	0:6d69e896ce38	1020	*
cparata	0:6d69e896ce38	1021	*/
cparata	0:6d69e896ce38	1022
cparata	0:6d69e896ce38	1023	/**
cparata	0:6d69e896ce38	1024	* @defgroup LSM6DSO_Timestamp
cparata	0:6d69e896ce38	1025	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	1026	* timestamp generation.
cparata	0:6d69e896ce38	1027	* @{
cparata	0:6d69e896ce38	1028	*
cparata	4:77faf76e3cd8	1029	*/
cparata	4:77faf76e3cd8	1030
cparata	4:77faf76e3cd8	1031	/**
cparata	4:77faf76e3cd8	1032	* @brief Reset timestamp counter.[set]
cparata	4:77faf76e3cd8	1033	*
cparata	4:77faf76e3cd8	1034	* @param ctx Read / write interface definitions.(ptr)
cparata	4:77faf76e3cd8	1035	* @retval Interface status (MANDATORY: return 0 -> no Error).
cparata	4:77faf76e3cd8	1036	*
cparata	4:77faf76e3cd8	1037	*/
cparata	4:77faf76e3cd8	1038	int32_t lsm6dso_timestamp_rst(lsm6dso_ctx_t *ctx)
cparata	4:77faf76e3cd8	1039	{
cparata	4:77faf76e3cd8	1040	uint8_t rst_val = 0xAA;
cparata	4:77faf76e3cd8	1041
cparata	4:77faf76e3cd8	1042	return lsm6dso_write_reg(ctx, LSM6DSO_TIMESTAMP2, &rst_val, 1);
cparata	4:77faf76e3cd8	1043	}
cparata	0:6d69e896ce38	1044
cparata	0:6d69e896ce38	1045	/**
cparata	0:6d69e896ce38	1046	* @brief Enables timestamp counter.[set]
cparata	0:6d69e896ce38	1047	*
cparata	0:6d69e896ce38	1048	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1049	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:6d69e896ce38	1050	*
cparata	0:6d69e896ce38	1051	*/
cparata	0:6d69e896ce38	1052	int32_t lsm6dso_timestamp_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1053	{
cparata	4:77faf76e3cd8	1054	lsm6dso_ctrl10_c_t reg;
cparata	4:77faf76e3cd8	1055	int32_t ret;
cparata	4:77faf76e3cd8	1056
cparata	4:77faf76e3cd8	1057	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1058	if (ret == 0) {
cparata	4:77faf76e3cd8	1059	reg.timestamp_en = val;
cparata	4:77faf76e3cd8	1060	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1061	}
cparata	4:77faf76e3cd8	1062	return ret;
cparata	0:6d69e896ce38	1063	}
cparata	0:6d69e896ce38	1064
cparata	0:6d69e896ce38	1065	/**
cparata	0:6d69e896ce38	1066	* @brief Enables timestamp counter.[get]
cparata	0:6d69e896ce38	1067	*
cparata	0:6d69e896ce38	1068	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1069	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:6d69e896ce38	1070	*
cparata	0:6d69e896ce38	1071	*/
cparata	0:6d69e896ce38	1072	int32_t lsm6dso_timestamp_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1073	{
cparata	4:77faf76e3cd8	1074	lsm6dso_ctrl10_c_t reg;
cparata	4:77faf76e3cd8	1075	int32_t ret;
cparata	4:77faf76e3cd8	1076
cparata	4:77faf76e3cd8	1077	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1078	*val = reg.timestamp_en;
cparata	4:77faf76e3cd8	1079
cparata	4:77faf76e3cd8	1080	return ret;
cparata	0:6d69e896ce38	1081	}
cparata	0:6d69e896ce38	1082
cparata	0:6d69e896ce38	1083	/**
cparata	0:6d69e896ce38	1084	* @brief Timestamp first data output register (r).
cparata	0:6d69e896ce38	1085	* The value is expressed as a 32-bit word and the bit
cparata	0:6d69e896ce38	1086	* resolution is 25 μs.[get]
cparata	0:6d69e896ce38	1087	*
cparata	0:6d69e896ce38	1088	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1089	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1090	*
cparata	0:6d69e896ce38	1091	*/
cparata	0:6d69e896ce38	1092	int32_t lsm6dso_timestamp_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1093	{
cparata	4:77faf76e3cd8	1094	int32_t ret;
cparata	4:77faf76e3cd8	1095	ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4);
cparata	4:77faf76e3cd8	1096	return ret;
cparata	0:6d69e896ce38	1097	}
cparata	0:6d69e896ce38	1098
cparata	0:6d69e896ce38	1099	/**
cparata	0:6d69e896ce38	1100	* @}
cparata	0:6d69e896ce38	1101	*
cparata	0:6d69e896ce38	1102	*/
cparata	0:6d69e896ce38	1103
cparata	0:6d69e896ce38	1104	/**
cparata	0:6d69e896ce38	1105	* @defgroup LSM6DSO_Data output
cparata	0:6d69e896ce38	1106	* @brief This section groups all the data output functions.
cparata	0:6d69e896ce38	1107	* @{
cparata	0:6d69e896ce38	1108	*
cparata	0:6d69e896ce38	1109	*/
cparata	0:6d69e896ce38	1110
cparata	0:6d69e896ce38	1111	/**
cparata	0:6d69e896ce38	1112	* @brief Circular burst-mode (rounding) read of the output
cparata	0:6d69e896ce38	1113	* registers.[set]
cparata	0:6d69e896ce38	1114	*
cparata	0:6d69e896ce38	1115	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1116	* @param val change the values of rounding in reg CTRL5_C
cparata	0:6d69e896ce38	1117	*
cparata	0:6d69e896ce38	1118	*/
cparata	0:6d69e896ce38	1119	int32_t lsm6dso_rounding_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1120	lsm6dso_rounding_t val)
cparata	0:6d69e896ce38	1121	{
cparata	4:77faf76e3cd8	1122	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1123	int32_t ret;
cparata	4:77faf76e3cd8	1124
cparata	4:77faf76e3cd8	1125	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1126	if (ret == 0) {
cparata	4:77faf76e3cd8	1127	reg.rounding = (uint8_t)val;
cparata	4:77faf76e3cd8	1128	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1129	}
cparata	4:77faf76e3cd8	1130	return ret;
cparata	0:6d69e896ce38	1131	}
cparata	0:6d69e896ce38	1132
cparata	0:6d69e896ce38	1133	/**
cparata	0:6d69e896ce38	1134	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:6d69e896ce38	1135	*
cparata	0:6d69e896ce38	1136	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1137	* @param val Get the values of rounding in reg CTRL5_C
cparata	0:6d69e896ce38	1138	*
cparata	0:6d69e896ce38	1139	*/
cparata	0:6d69e896ce38	1140	int32_t lsm6dso_rounding_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1141	lsm6dso_rounding_t *val)
cparata	0:6d69e896ce38	1142	{
cparata	4:77faf76e3cd8	1143	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1144	int32_t ret;
cparata	4:77faf76e3cd8	1145
cparata	4:77faf76e3cd8	1146	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1147	switch (reg.rounding) {
cparata	4:77faf76e3cd8	1148	case LSM6DSO_NO_ROUND:
cparata	4:77faf76e3cd8	1149	*val = LSM6DSO_NO_ROUND;
cparata	4:77faf76e3cd8	1150	break;
cparata	4:77faf76e3cd8	1151	case LSM6DSO_ROUND_XL:
cparata	4:77faf76e3cd8	1152	*val = LSM6DSO_ROUND_XL;
cparata	4:77faf76e3cd8	1153	break;
cparata	4:77faf76e3cd8	1154	case LSM6DSO_ROUND_GY:
cparata	4:77faf76e3cd8	1155	*val = LSM6DSO_ROUND_GY;
cparata	4:77faf76e3cd8	1156	break;
cparata	4:77faf76e3cd8	1157	case LSM6DSO_ROUND_GY_XL:
cparata	4:77faf76e3cd8	1158	*val = LSM6DSO_ROUND_GY_XL;
cparata	4:77faf76e3cd8	1159	break;
cparata	4:77faf76e3cd8	1160	default:
cparata	4:77faf76e3cd8	1161	*val = LSM6DSO_NO_ROUND;
cparata	4:77faf76e3cd8	1162	break;
cparata	4:77faf76e3cd8	1163	}
cparata	4:77faf76e3cd8	1164	return ret;
cparata	0:6d69e896ce38	1165	}
cparata	0:6d69e896ce38	1166
cparata	0:6d69e896ce38	1167	/**
cparata	0:6d69e896ce38	1168	* @brief Temperature data output register (r).
cparata	0:6d69e896ce38	1169	* L and H registers together express a 16-bit word in two’s
cparata	0:6d69e896ce38	1170	* complement.[get]
cparata	0:6d69e896ce38	1171	*
cparata	0:6d69e896ce38	1172	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1173	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1174	*
cparata	0:6d69e896ce38	1175	*/
cparata	0:6d69e896ce38	1176	int32_t lsm6dso_temperature_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1177	{
cparata	4:77faf76e3cd8	1178	int32_t ret;
cparata	4:77faf76e3cd8	1179	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2);
cparata	4:77faf76e3cd8	1180	return ret;
cparata	0:6d69e896ce38	1181	}
cparata	0:6d69e896ce38	1182
cparata	0:6d69e896ce38	1183	/**
cparata	0:6d69e896ce38	1184	* @brief Angular rate sensor. The value is expressed as a 16-bit
cparata	0:6d69e896ce38	1185	* word in two’s complement.[get]
cparata	0:6d69e896ce38	1186	*
cparata	0:6d69e896ce38	1187	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1188	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1189	*
cparata	0:6d69e896ce38	1190	*/
cparata	0:6d69e896ce38	1191	int32_t lsm6dso_angular_rate_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1192	{
cparata	4:77faf76e3cd8	1193	int32_t ret;
cparata	4:77faf76e3cd8	1194	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6);
cparata	4:77faf76e3cd8	1195	return ret;
cparata	0:6d69e896ce38	1196	}
cparata	0:6d69e896ce38	1197
cparata	0:6d69e896ce38	1198	/**
cparata	0:6d69e896ce38	1199	* @brief Linear acceleration output register.
cparata	0:6d69e896ce38	1200	* The value is expressed as a 16-bit word in two’s complement.[get]
cparata	0:6d69e896ce38	1201	*
cparata	0:6d69e896ce38	1202	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1203	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1204	*
cparata	0:6d69e896ce38	1205	*/
cparata	0:6d69e896ce38	1206	int32_t lsm6dso_acceleration_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1207	{
cparata	4:77faf76e3cd8	1208	int32_t ret;
cparata	4:77faf76e3cd8	1209	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6);
cparata	4:77faf76e3cd8	1210	return ret;
cparata	0:6d69e896ce38	1211	}
cparata	0:6d69e896ce38	1212
cparata	0:6d69e896ce38	1213	/**
cparata	0:6d69e896ce38	1214	* @brief FIFO data output [get]
cparata	0:6d69e896ce38	1215	*
cparata	0:6d69e896ce38	1216	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1217	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1218	*
cparata	0:6d69e896ce38	1219	*/
cparata	0:6d69e896ce38	1220	int32_t lsm6dso_fifo_out_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1221	{
cparata	4:77faf76e3cd8	1222	int32_t ret;
cparata	4:77faf76e3cd8	1223	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6);
cparata	4:77faf76e3cd8	1224	return ret;
cparata	0:6d69e896ce38	1225	}
cparata	0:6d69e896ce38	1226
cparata	0:6d69e896ce38	1227	/**
cparata	0:6d69e896ce38	1228	* @brief Step counter output register.[get]
cparata	0:6d69e896ce38	1229	*
cparata	0:6d69e896ce38	1230	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1231	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1232	*
cparata	0:6d69e896ce38	1233	*/
cparata	0:6d69e896ce38	1234	int32_t lsm6dso_number_of_steps_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1235	{
cparata	4:77faf76e3cd8	1236	int32_t ret;
cparata	4:77faf76e3cd8	1237
cparata	4:77faf76e3cd8	1238	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1239	if (ret == 0) {
cparata	4:77faf76e3cd8	1240	ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2);
cparata	4:77faf76e3cd8	1241	}
cparata	4:77faf76e3cd8	1242	if (ret == 0) {
cparata	4:77faf76e3cd8	1243	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1244	}
cparata	4:77faf76e3cd8	1245	return ret;
cparata	0:6d69e896ce38	1246	}
cparata	0:6d69e896ce38	1247
cparata	0:6d69e896ce38	1248	/**
cparata	0:6d69e896ce38	1249	* @brief Reset step counter register.[get]
cparata	0:6d69e896ce38	1250	*
cparata	0:6d69e896ce38	1251	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1252	*
cparata	0:6d69e896ce38	1253	*/
cparata	0:6d69e896ce38	1254	int32_t lsm6dso_steps_reset(lsm6dso_ctx_t *ctx)
cparata	0:6d69e896ce38	1255	{
cparata	4:77faf76e3cd8	1256	lsm6dso_emb_func_src_t reg;
cparata	4:77faf76e3cd8	1257	int32_t ret;
cparata	4:77faf76e3cd8	1258
cparata	4:77faf76e3cd8	1259	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1260	if (ret == 0) {
cparata	4:77faf76e3cd8	1261	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1262	}
cparata	4:77faf76e3cd8	1263	if (ret == 0) {
cparata	4:77faf76e3cd8	1264	reg.pedo_rst_step = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	1265	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1266	}
cparata	4:77faf76e3cd8	1267	if (ret == 0) {
cparata	4:77faf76e3cd8	1268	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1269	}
cparata	4:77faf76e3cd8	1270	return ret;
cparata	0:6d69e896ce38	1271	}
cparata	0:6d69e896ce38	1272
cparata	0:6d69e896ce38	1273	/**
cparata	0:6d69e896ce38	1274	* @}
cparata	0:6d69e896ce38	1275	*
cparata	0:6d69e896ce38	1276	*/
cparata	0:6d69e896ce38	1277
cparata	0:6d69e896ce38	1278	/**
cparata	0:6d69e896ce38	1279	* @defgroup LSM6DSO_common
cparata	0:6d69e896ce38	1280	* @brief This section groups common usefull functions.
cparata	0:6d69e896ce38	1281	* @{
cparata	0:6d69e896ce38	1282	*
cparata	0:6d69e896ce38	1283	*/
cparata	0:6d69e896ce38	1284
cparata	0:6d69e896ce38	1285	/**
cparata	0:6d69e896ce38	1286	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:6d69e896ce38	1287	* with respect to the typical.
cparata	0:6d69e896ce38	1288	* Step: 0.15%. 8-bit format, 2's complement.[set]
cparata	0:6d69e896ce38	1289	*
cparata	0:6d69e896ce38	1290	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1291	* @param val change the values of freq_fine in reg
cparata	0:6d69e896ce38	1292	* INTERNAL_FREQ_FINE
cparata	0:6d69e896ce38	1293	*
cparata	0:6d69e896ce38	1294	*/
cparata	0:6d69e896ce38	1295	int32_t lsm6dso_odr_cal_reg_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1296	{
cparata	4:77faf76e3cd8	1297	lsm6dso_internal_freq_fine_t reg;
cparata	4:77faf76e3cd8	1298	int32_t ret;
cparata	4:77faf76e3cd8	1299
cparata	4:77faf76e3cd8	1300	ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1301	if (ret == 0) {
cparata	4:77faf76e3cd8	1302	reg.freq_fine = val;
cparata	4:77faf76e3cd8	1303	ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
cparata	4:77faf76e3cd8	1304	(uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1305	}
cparata	4:77faf76e3cd8	1306	return ret;
cparata	0:6d69e896ce38	1307	}
cparata	0:6d69e896ce38	1308
cparata	0:6d69e896ce38	1309	/**
cparata	0:6d69e896ce38	1310	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:6d69e896ce38	1311	* with respect to the typical.
cparata	0:6d69e896ce38	1312	* Step: 0.15%. 8-bit format, 2's complement.[get]
cparata	0:6d69e896ce38	1313	*
cparata	0:6d69e896ce38	1314	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1315	* @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
cparata	0:6d69e896ce38	1316	*
cparata	0:6d69e896ce38	1317	*/
cparata	0:6d69e896ce38	1318	int32_t lsm6dso_odr_cal_reg_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1319	{
cparata	4:77faf76e3cd8	1320	lsm6dso_internal_freq_fine_t reg;
cparata	4:77faf76e3cd8	1321	int32_t ret;
cparata	4:77faf76e3cd8	1322
cparata	4:77faf76e3cd8	1323	ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1324	*val = reg.freq_fine;
cparata	4:77faf76e3cd8	1325
cparata	4:77faf76e3cd8	1326	return ret;
cparata	0:6d69e896ce38	1327	}
cparata	0:6d69e896ce38	1328
cparata	0:6d69e896ce38	1329
cparata	0:6d69e896ce38	1330	/**
cparata	0:6d69e896ce38	1331	* @brief Enable access to the embedded functions/sensor
cparata	0:6d69e896ce38	1332	* hub configuration registers.[set]
cparata	0:6d69e896ce38	1333	*
cparata	0:6d69e896ce38	1334	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1335	* @param val change the values of reg_access in
cparata	0:6d69e896ce38	1336	* reg FUNC_CFG_ACCESS
cparata	0:6d69e896ce38	1337	*
cparata	0:6d69e896ce38	1338	*/
cparata	0:6d69e896ce38	1339	int32_t lsm6dso_mem_bank_set(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t val)
cparata	0:6d69e896ce38	1340	{
cparata	4:77faf76e3cd8	1341	lsm6dso_func_cfg_access_t reg;
cparata	4:77faf76e3cd8	1342	int32_t ret;
cparata	4:77faf76e3cd8	1343
cparata	4:77faf76e3cd8	1344	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1345	if (ret == 0) {
cparata	4:77faf76e3cd8	1346	reg.reg_access = (uint8_t)val;
cparata	4:77faf76e3cd8	1347	ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1348	}
cparata	4:77faf76e3cd8	1349	return ret;
cparata	0:6d69e896ce38	1350	}
cparata	0:6d69e896ce38	1351
cparata	0:6d69e896ce38	1352	/**
cparata	0:6d69e896ce38	1353	* @brief Enable access to the embedded functions/sensor
cparata	0:6d69e896ce38	1354	* hub configuration registers.[get]
cparata	0:6d69e896ce38	1355	*
cparata	0:6d69e896ce38	1356	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1357	* @param val Get the values of reg_access in
cparata	0:6d69e896ce38	1358	* reg FUNC_CFG_ACCESS
cparata	0:6d69e896ce38	1359	*
cparata	0:6d69e896ce38	1360	*/
cparata	0:6d69e896ce38	1361	int32_t lsm6dso_mem_bank_get(lsm6dso_ctx_t ctx, lsm6dso_reg_access_t val)
cparata	0:6d69e896ce38	1362	{
cparata	4:77faf76e3cd8	1363	lsm6dso_func_cfg_access_t reg;
cparata	4:77faf76e3cd8	1364	int32_t ret;
cparata	4:77faf76e3cd8	1365
cparata	4:77faf76e3cd8	1366	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1367	switch (reg.reg_access) {
cparata	4:77faf76e3cd8	1368	case LSM6DSO_USER_BANK:
cparata	4:77faf76e3cd8	1369	*val = LSM6DSO_USER_BANK;
cparata	4:77faf76e3cd8	1370	break;
cparata	4:77faf76e3cd8	1371	case LSM6DSO_SENSOR_HUB_BANK:
cparata	4:77faf76e3cd8	1372	*val = LSM6DSO_SENSOR_HUB_BANK;
cparata	4:77faf76e3cd8	1373	break;
cparata	4:77faf76e3cd8	1374	case LSM6DSO_EMBEDDED_FUNC_BANK:
cparata	4:77faf76e3cd8	1375	*val = LSM6DSO_EMBEDDED_FUNC_BANK;
cparata	4:77faf76e3cd8	1376	break;
cparata	4:77faf76e3cd8	1377	default:
cparata	4:77faf76e3cd8	1378	*val = LSM6DSO_USER_BANK;
cparata	4:77faf76e3cd8	1379	break;
cparata	4:77faf76e3cd8	1380	}
cparata	4:77faf76e3cd8	1381	return ret;
cparata	0:6d69e896ce38	1382	}
cparata	0:6d69e896ce38	1383
cparata	0:6d69e896ce38	1384	/**
cparata	0:6d69e896ce38	1385	* @brief Write a line(byte) in a page.[set]
cparata	0:6d69e896ce38	1386	*
cparata	0:6d69e896ce38	1387	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1388	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1389	* @param val value to write
cparata	0:6d69e896ce38	1390	*
cparata	0:6d69e896ce38	1391	*/
cparata	0:6d69e896ce38	1392	int32_t lsm6dso_ln_pg_write_byte(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1393	uint8_t *val)
cparata	0:6d69e896ce38	1394	{
cparata	4:77faf76e3cd8	1395	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	1396	lsm6dso_page_sel_t page_sel;
cparata	4:77faf76e3cd8	1397	lsm6dso_page_address_t page_address;
cparata	4:77faf76e3cd8	1398	int32_t ret;
cparata	4:77faf76e3cd8	1399
cparata	4:77faf76e3cd8	1400	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1401
cparata	4:77faf76e3cd8	1402	if (ret == 0) {
cparata	4:77faf76e3cd8	1403	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1404	}
cparata	4:77faf76e3cd8	1405	if (ret == 0) {
cparata	4:77faf76e3cd8	1406	page_rw.page_rw = 0x02; /* page_write enable */
cparata	4:77faf76e3cd8	1407	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1408	}
cparata	4:77faf76e3cd8	1409	if (ret == 0) {
cparata	4:77faf76e3cd8	1410	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1411	}
cparata	4:77faf76e3cd8	1412
cparata	4:77faf76e3cd8	1413	if (ret == 0) {
cparata	4:77faf76e3cd8	1414	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	4:77faf76e3cd8	1415	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1416	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1417	}
cparata	4:77faf76e3cd8	1418	if (ret == 0) {
cparata	4:77faf76e3cd8	1419	page_address.page_addr = (uint8_t)address & 0xFFU;
cparata	4:77faf76e3cd8	1420	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	4:77faf76e3cd8	1421	(uint8_t*)&page_address, 1);
cparata	4:77faf76e3cd8	1422	}
cparata	4:77faf76e3cd8	1423	if (ret == 0) {
cparata	4:77faf76e3cd8	1424	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
cparata	4:77faf76e3cd8	1425	}
cparata	4:77faf76e3cd8	1426	if (ret == 0) {
cparata	4:77faf76e3cd8	1427	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1428	}
cparata	4:77faf76e3cd8	1429	if (ret == 0) {
cparata	4:77faf76e3cd8	1430	page_rw.page_rw = 0x00; /* page_write disable */
cparata	4:77faf76e3cd8	1431	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1432	}
cparata	4:77faf76e3cd8	1433	if (ret == 0) {
cparata	4:77faf76e3cd8	1434
cparata	4:77faf76e3cd8	1435	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1436	}
cparata	4:77faf76e3cd8	1437	return ret;
cparata	0:6d69e896ce38	1438	}
cparata	0:6d69e896ce38	1439
cparata	0:6d69e896ce38	1440	/**
cparata	0:6d69e896ce38	1441	* @brief Write buffer in a page.[set]
cparata	0:6d69e896ce38	1442	*
cparata	0:6d69e896ce38	1443	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1444	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1445	* @param uint8_t *buf: buffer to write
cparata	0:6d69e896ce38	1446	* @param uint8_t len: buffer len
cparata	0:6d69e896ce38	1447	*
cparata	0:6d69e896ce38	1448	*/
cparata	0:6d69e896ce38	1449	int32_t lsm6dso_ln_pg_write(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1450	uint8_t *buf, uint8_t len)
cparata	0:6d69e896ce38	1451	{
cparata	4:77faf76e3cd8	1452	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	1453	lsm6dso_page_sel_t page_sel;
cparata	4:77faf76e3cd8	1454	lsm6dso_page_address_t page_address;
cparata	4:77faf76e3cd8	1455	uint16_t addr_pointed;
cparata	4:77faf76e3cd8	1456	int32_t ret;
cparata	4:77faf76e3cd8	1457	uint8_t i ;
cparata	4:77faf76e3cd8	1458
cparata	4:77faf76e3cd8	1459	addr_pointed = address;
cparata	4:77faf76e3cd8	1460
cparata	4:77faf76e3cd8	1461	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1462	if (ret == 0) {
cparata	4:77faf76e3cd8	1463
cparata	4:77faf76e3cd8	1464	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1465	}
cparata	4:77faf76e3cd8	1466	if (ret == 0) {
cparata	4:77faf76e3cd8	1467	page_rw.page_rw = 0x02; /* page_write enable*/
cparata	4:77faf76e3cd8	1468	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1469	}
cparata	4:77faf76e3cd8	1470	if (ret == 0) {
cparata	4:77faf76e3cd8	1471	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1472	}
cparata	4:77faf76e3cd8	1473	if (ret == 0) {
cparata	4:77faf76e3cd8	1474	page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
cparata	4:77faf76e3cd8	1475	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1476	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1477	}
cparata	4:77faf76e3cd8	1478	if (ret == 0) {
cparata	4:77faf76e3cd8	1479	page_address.page_addr = (uint8_t)(addr_pointed & 0x00FFU);
cparata	4:77faf76e3cd8	1480	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	4:77faf76e3cd8	1481	(uint8_t*)&page_address, 1);
cparata	4:77faf76e3cd8	1482	}
cparata	4:77faf76e3cd8	1483
cparata	4:77faf76e3cd8	1484	if (ret == 0) {
cparata	4:77faf76e3cd8	1485	for (i = 0; ( (i < len) && (ret == 0) ); i++) {
cparata	4:77faf76e3cd8	1486	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1);
cparata	4:77faf76e3cd8	1487	addr_pointed++;
cparata	4:77faf76e3cd8	1488	/* Check if page wrap */
cparata	4:77faf76e3cd8	1489	if ( ( (addr_pointed % 0x0100U) == 0x00U ) && (ret == 0) ) {
cparata	4:77faf76e3cd8	1490	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*)&page_sel, 1);
cparata	4:77faf76e3cd8	1491	if (ret == 0) {
cparata	4:77faf76e3cd8	1492	page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
cparata	4:77faf76e3cd8	1493	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1494	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL,
cparata	4:77faf76e3cd8	1495	(uint8_t*)&page_sel, 1);
cparata	4:77faf76e3cd8	1496	}
cparata	4:77faf76e3cd8	1497	}
cparata	3:4274d9103f1d	1498	}
cparata	4:77faf76e3cd8	1499	page_sel.page_sel = 0;
cparata	4:77faf76e3cd8	1500	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1501	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1502	}
cparata	4:77faf76e3cd8	1503	if (ret == 0) {
cparata	4:77faf76e3cd8	1504	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1505	}
cparata	4:77faf76e3cd8	1506	if (ret == 0) {
cparata	4:77faf76e3cd8	1507	page_rw.page_rw = 0x00; /* page_write disable */
cparata	4:77faf76e3cd8	1508	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1509	}
cparata	4:77faf76e3cd8	1510	if (ret == 0) {
cparata	4:77faf76e3cd8	1511	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1512	}
cparata	4:77faf76e3cd8	1513	return ret;
cparata	0:6d69e896ce38	1514	}
cparata	0:6d69e896ce38	1515
cparata	0:6d69e896ce38	1516	/**
cparata	0:6d69e896ce38	1517	* @brief Read a line(byte) in a page.[get]
cparata	0:6d69e896ce38	1518	*
cparata	0:6d69e896ce38	1519	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1520	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1521	* @param val read value
cparata	0:6d69e896ce38	1522	*
cparata	0:6d69e896ce38	1523	*/
cparata	0:6d69e896ce38	1524	int32_t lsm6dso_ln_pg_read_byte(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1525	uint8_t *val)
cparata	0:6d69e896ce38	1526	{
cparata	4:77faf76e3cd8	1527	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	1528	lsm6dso_page_sel_t page_sel;
cparata	4:77faf76e3cd8	1529	lsm6dso_page_address_t page_address;
cparata	4:77faf76e3cd8	1530	int32_t ret;
cparata	4:77faf76e3cd8	1531
cparata	4:77faf76e3cd8	1532	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	1533	if (ret == 0) {
cparata	4:77faf76e3cd8	1534
cparata	4:77faf76e3cd8	1535	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1536	}
cparata	4:77faf76e3cd8	1537	if (ret == 0) {
cparata	4:77faf76e3cd8	1538	page_rw.page_rw = 0x01; /* page_read enable*/
cparata	4:77faf76e3cd8	1539	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1540	}
cparata	4:77faf76e3cd8	1541	if (ret == 0) {
cparata	4:77faf76e3cd8	1542
cparata	4:77faf76e3cd8	1543	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1544	}
cparata	4:77faf76e3cd8	1545	if (ret == 0) {
cparata	4:77faf76e3cd8	1546	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	4:77faf76e3cd8	1547	page_sel.not_used_01 = 1;
cparata	4:77faf76e3cd8	1548	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	4:77faf76e3cd8	1549	}
cparata	4:77faf76e3cd8	1550	if (ret == 0) {
cparata	4:77faf76e3cd8	1551	page_address.page_addr = (uint8_t)address & 0x00FFU;
cparata	4:77faf76e3cd8	1552	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	4:77faf76e3cd8	1553	(uint8_t*)&page_address, 1);
cparata	4:77faf76e3cd8	1554	}
cparata	4:77faf76e3cd8	1555	if (ret == 0) {
cparata	4:77faf76e3cd8	1556
cparata	4:77faf76e3cd8	1557	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
cparata	4:77faf76e3cd8	1558	}
cparata	4:77faf76e3cd8	1559	if (ret == 0) {
cparata	4:77faf76e3cd8	1560	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1561	}
cparata	4:77faf76e3cd8	1562	if (ret == 0) {
cparata	4:77faf76e3cd8	1563	page_rw.page_rw = 0x00; /* page_read disable */
cparata	4:77faf76e3cd8	1564	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	1565	}
cparata	4:77faf76e3cd8	1566	if (ret == 0) {
cparata	4:77faf76e3cd8	1567	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	1568	}
cparata	4:77faf76e3cd8	1569
cparata	4:77faf76e3cd8	1570	return ret;
cparata	0:6d69e896ce38	1571	}
cparata	0:6d69e896ce38	1572
cparata	0:6d69e896ce38	1573	/**
cparata	0:6d69e896ce38	1574	* @brief Data-ready pulsed / letched mode.[set]
cparata	0:6d69e896ce38	1575	*
cparata	0:6d69e896ce38	1576	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1577	* @param val change the values of
cparata	0:6d69e896ce38	1578	* dataready_pulsed in
cparata	0:6d69e896ce38	1579	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	1580	*
cparata	0:6d69e896ce38	1581	*/
cparata	0:6d69e896ce38	1582	int32_t lsm6dso_data_ready_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1583	lsm6dso_dataready_pulsed_t val)
cparata	0:6d69e896ce38	1584	{
cparata	4:77faf76e3cd8	1585	lsm6dso_counter_bdr_reg1_t reg;
cparata	4:77faf76e3cd8	1586	int32_t ret;
cparata	4:77faf76e3cd8	1587
cparata	4:77faf76e3cd8	1588	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1589	if (ret == 0) {
cparata	4:77faf76e3cd8	1590	reg.dataready_pulsed = (uint8_t)val;
cparata	4:77faf76e3cd8	1591	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1592	}
cparata	4:77faf76e3cd8	1593	return ret;
cparata	0:6d69e896ce38	1594	}
cparata	0:6d69e896ce38	1595
cparata	0:6d69e896ce38	1596	/**
cparata	0:6d69e896ce38	1597	* @brief Data-ready pulsed / letched mode.[get]
cparata	0:6d69e896ce38	1598	*
cparata	0:6d69e896ce38	1599	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1600	* @param val Get the values of
cparata	0:6d69e896ce38	1601	* dataready_pulsed in
cparata	0:6d69e896ce38	1602	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	1603	*
cparata	0:6d69e896ce38	1604	*/
cparata	0:6d69e896ce38	1605	int32_t lsm6dso_data_ready_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1606	lsm6dso_dataready_pulsed_t *val)
cparata	0:6d69e896ce38	1607	{
cparata	4:77faf76e3cd8	1608	lsm6dso_counter_bdr_reg1_t reg;
cparata	4:77faf76e3cd8	1609	int32_t ret;
cparata	4:77faf76e3cd8	1610
cparata	4:77faf76e3cd8	1611	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1612	switch (reg.dataready_pulsed) {
cparata	4:77faf76e3cd8	1613	case LSM6DSO_DRDY_LATCHED:
cparata	4:77faf76e3cd8	1614	*val = LSM6DSO_DRDY_LATCHED;
cparata	4:77faf76e3cd8	1615	break;
cparata	4:77faf76e3cd8	1616	case LSM6DSO_DRDY_PULSED:
cparata	4:77faf76e3cd8	1617	*val = LSM6DSO_DRDY_PULSED;
cparata	4:77faf76e3cd8	1618	break;
cparata	4:77faf76e3cd8	1619	default:
cparata	4:77faf76e3cd8	1620	*val = LSM6DSO_DRDY_LATCHED;
cparata	4:77faf76e3cd8	1621	break;
cparata	4:77faf76e3cd8	1622	}
cparata	4:77faf76e3cd8	1623	return ret;
cparata	0:6d69e896ce38	1624	}
cparata	0:6d69e896ce38	1625
cparata	0:6d69e896ce38	1626	/**
cparata	0:6d69e896ce38	1627	* @brief Device "Who am I".[get]
cparata	0:6d69e896ce38	1628	*
cparata	0:6d69e896ce38	1629	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1630	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1631	*
cparata	0:6d69e896ce38	1632	*/
cparata	0:6d69e896ce38	1633	int32_t lsm6dso_device_id_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1634	{
cparata	4:77faf76e3cd8	1635	int32_t ret;
cparata	4:77faf76e3cd8	1636	ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1);
cparata	4:77faf76e3cd8	1637	return ret;
cparata	0:6d69e896ce38	1638	}
cparata	0:6d69e896ce38	1639
cparata	0:6d69e896ce38	1640	/**
cparata	0:6d69e896ce38	1641	* @brief Software reset. Restore the default values
cparata	0:6d69e896ce38	1642	* in user registers[set]
cparata	0:6d69e896ce38	1643	*
cparata	0:6d69e896ce38	1644	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1645	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:6d69e896ce38	1646	*
cparata	0:6d69e896ce38	1647	*/
cparata	0:6d69e896ce38	1648	int32_t lsm6dso_reset_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1649	{
cparata	4:77faf76e3cd8	1650	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1651	int32_t ret;
cparata	4:77faf76e3cd8	1652
cparata	4:77faf76e3cd8	1653	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1654	if (ret == 0) {
cparata	4:77faf76e3cd8	1655	reg.sw_reset = val;
cparata	4:77faf76e3cd8	1656	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1657	}
cparata	4:77faf76e3cd8	1658
cparata	4:77faf76e3cd8	1659	return ret;
cparata	0:6d69e896ce38	1660	}
cparata	0:6d69e896ce38	1661
cparata	0:6d69e896ce38	1662	/**
cparata	0:6d69e896ce38	1663	* @brief Software reset. Restore the default values in user registers.[get]
cparata	0:6d69e896ce38	1664	*
cparata	0:6d69e896ce38	1665	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1666	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:6d69e896ce38	1667	*
cparata	0:6d69e896ce38	1668	*/
cparata	0:6d69e896ce38	1669	int32_t lsm6dso_reset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1670	{
cparata	4:77faf76e3cd8	1671	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1672	int32_t ret;
cparata	4:77faf76e3cd8	1673
cparata	4:77faf76e3cd8	1674	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1675	*val = reg.sw_reset;
cparata	4:77faf76e3cd8	1676
cparata	4:77faf76e3cd8	1677	return ret;
cparata	0:6d69e896ce38	1678	}
cparata	0:6d69e896ce38	1679
cparata	0:6d69e896ce38	1680	/**
cparata	0:6d69e896ce38	1681	* @brief Register address automatically incremented during a multiple byte
cparata	0:6d69e896ce38	1682	* access with a serial interface.[set]
cparata	0:6d69e896ce38	1683	*
cparata	0:6d69e896ce38	1684	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1685	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:6d69e896ce38	1686	*
cparata	0:6d69e896ce38	1687	*/
cparata	0:6d69e896ce38	1688	int32_t lsm6dso_auto_increment_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1689	{
cparata	4:77faf76e3cd8	1690	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1691	int32_t ret;
cparata	4:77faf76e3cd8	1692
cparata	4:77faf76e3cd8	1693	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1694	if (ret == 0) {
cparata	4:77faf76e3cd8	1695	reg.if_inc = val;
cparata	4:77faf76e3cd8	1696	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1697	}
cparata	4:77faf76e3cd8	1698	return ret;
cparata	0:6d69e896ce38	1699	}
cparata	0:6d69e896ce38	1700
cparata	0:6d69e896ce38	1701	/**
cparata	0:6d69e896ce38	1702	* @brief Register address automatically incremented during a multiple byte
cparata	0:6d69e896ce38	1703	* access with a serial interface.[get]
cparata	0:6d69e896ce38	1704	*
cparata	0:6d69e896ce38	1705	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1706	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:6d69e896ce38	1707	*
cparata	0:6d69e896ce38	1708	*/
cparata	0:6d69e896ce38	1709	int32_t lsm6dso_auto_increment_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1710	{
cparata	4:77faf76e3cd8	1711	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1712	int32_t ret;
cparata	4:77faf76e3cd8	1713
cparata	4:77faf76e3cd8	1714	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1715	*val = reg.if_inc;
cparata	4:77faf76e3cd8	1716
cparata	4:77faf76e3cd8	1717	return ret;
cparata	0:6d69e896ce38	1718	}
cparata	0:6d69e896ce38	1719
cparata	0:6d69e896ce38	1720	/**
cparata	0:6d69e896ce38	1721	* @brief Reboot memory content. Reload the calibration parameters.[set]
cparata	0:6d69e896ce38	1722	*
cparata	0:6d69e896ce38	1723	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1724	* @param val change the values of boot in reg CTRL3_C
cparata	0:6d69e896ce38	1725	*
cparata	0:6d69e896ce38	1726	*/
cparata	0:6d69e896ce38	1727	int32_t lsm6dso_boot_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1728	{
cparata	4:77faf76e3cd8	1729	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1730	int32_t ret;
cparata	4:77faf76e3cd8	1731
cparata	4:77faf76e3cd8	1732	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1733	if (ret == 0) {
cparata	4:77faf76e3cd8	1734	reg.boot = val;
cparata	4:77faf76e3cd8	1735	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1736	}
cparata	4:77faf76e3cd8	1737	return ret;
cparata	0:6d69e896ce38	1738	}
cparata	0:6d69e896ce38	1739
cparata	0:6d69e896ce38	1740	/**
cparata	0:6d69e896ce38	1741	* @brief Reboot memory content. Reload the calibration parameters.[get]
cparata	0:6d69e896ce38	1742	*
cparata	0:6d69e896ce38	1743	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1744	* @param val change the values of boot in reg CTRL3_C
cparata	0:6d69e896ce38	1745	*
cparata	0:6d69e896ce38	1746	*/
cparata	0:6d69e896ce38	1747	int32_t lsm6dso_boot_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1748	{
cparata	4:77faf76e3cd8	1749	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	1750	int32_t ret;
cparata	4:77faf76e3cd8	1751
cparata	4:77faf76e3cd8	1752	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1753	*val = reg.boot;
cparata	4:77faf76e3cd8	1754
cparata	4:77faf76e3cd8	1755	return ret;
cparata	0:6d69e896ce38	1756	}
cparata	0:6d69e896ce38	1757
cparata	0:6d69e896ce38	1758	/**
cparata	0:6d69e896ce38	1759	* @brief Linear acceleration sensor self-test enable.[set]
cparata	0:6d69e896ce38	1760	*
cparata	0:6d69e896ce38	1761	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1762	* @param val change the values of st_xl in reg CTRL5_C
cparata	0:6d69e896ce38	1763	*
cparata	0:6d69e896ce38	1764	*/
cparata	0:6d69e896ce38	1765	int32_t lsm6dso_xl_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t val)
cparata	0:6d69e896ce38	1766	{
cparata	4:77faf76e3cd8	1767	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1768	int32_t ret;
cparata	4:77faf76e3cd8	1769
cparata	4:77faf76e3cd8	1770	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1771	if (ret == 0) {
cparata	4:77faf76e3cd8	1772	reg.st_xl = (uint8_t)val;
cparata	4:77faf76e3cd8	1773	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1774	}
cparata	4:77faf76e3cd8	1775	return ret;
cparata	0:6d69e896ce38	1776	}
cparata	0:6d69e896ce38	1777
cparata	0:6d69e896ce38	1778	/**
cparata	0:6d69e896ce38	1779	* @brief Linear acceleration sensor self-test enable.[get]
cparata	0:6d69e896ce38	1780	*
cparata	0:6d69e896ce38	1781	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1782	* @param val Get the values of st_xl in reg CTRL5_C
cparata	0:6d69e896ce38	1783	*
cparata	0:6d69e896ce38	1784	*/
cparata	0:6d69e896ce38	1785	int32_t lsm6dso_xl_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_xl_t val)
cparata	0:6d69e896ce38	1786	{
cparata	4:77faf76e3cd8	1787	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1788	int32_t ret;
cparata	4:77faf76e3cd8	1789
cparata	4:77faf76e3cd8	1790	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1791	switch (reg.st_xl) {
cparata	4:77faf76e3cd8	1792	case LSM6DSO_XL_ST_DISABLE:
cparata	4:77faf76e3cd8	1793	*val = LSM6DSO_XL_ST_DISABLE;
cparata	4:77faf76e3cd8	1794	break;
cparata	4:77faf76e3cd8	1795	case LSM6DSO_XL_ST_POSITIVE:
cparata	4:77faf76e3cd8	1796	*val = LSM6DSO_XL_ST_POSITIVE;
cparata	4:77faf76e3cd8	1797	break;
cparata	4:77faf76e3cd8	1798	case LSM6DSO_XL_ST_NEGATIVE:
cparata	4:77faf76e3cd8	1799	*val = LSM6DSO_XL_ST_NEGATIVE;
cparata	4:77faf76e3cd8	1800	break;
cparata	4:77faf76e3cd8	1801	default:
cparata	4:77faf76e3cd8	1802	*val = LSM6DSO_XL_ST_DISABLE;
cparata	4:77faf76e3cd8	1803	break;
cparata	4:77faf76e3cd8	1804	}
cparata	4:77faf76e3cd8	1805	return ret;
cparata	0:6d69e896ce38	1806	}
cparata	0:6d69e896ce38	1807
cparata	0:6d69e896ce38	1808	/**
cparata	0:6d69e896ce38	1809	* @brief Angular rate sensor self-test enable.[set]
cparata	0:6d69e896ce38	1810	*
cparata	0:6d69e896ce38	1811	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1812	* @param val change the values of st_g in reg CTRL5_C
cparata	0:6d69e896ce38	1813	*
cparata	0:6d69e896ce38	1814	*/
cparata	0:6d69e896ce38	1815	int32_t lsm6dso_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t val)
cparata	0:6d69e896ce38	1816	{
cparata	4:77faf76e3cd8	1817	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1818	int32_t ret;
cparata	4:77faf76e3cd8	1819
cparata	4:77faf76e3cd8	1820	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1821	if (ret == 0) {
cparata	4:77faf76e3cd8	1822	reg.st_g = (uint8_t)val;
cparata	4:77faf76e3cd8	1823	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1824	}
cparata	4:77faf76e3cd8	1825	return ret;
cparata	0:6d69e896ce38	1826	}
cparata	0:6d69e896ce38	1827
cparata	0:6d69e896ce38	1828	/**
cparata	0:6d69e896ce38	1829	* @brief Angular rate sensor self-test enable.[get]
cparata	0:6d69e896ce38	1830	*
cparata	0:6d69e896ce38	1831	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1832	* @param val Get the values of st_g in reg CTRL5_C
cparata	0:6d69e896ce38	1833	*
cparata	0:6d69e896ce38	1834	*/
cparata	0:6d69e896ce38	1835	int32_t lsm6dso_gy_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_g_t val)
cparata	0:6d69e896ce38	1836	{
cparata	4:77faf76e3cd8	1837	lsm6dso_ctrl5_c_t reg;
cparata	4:77faf76e3cd8	1838	int32_t ret;
cparata	4:77faf76e3cd8	1839
cparata	4:77faf76e3cd8	1840	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1841	switch (reg.st_g) {
cparata	4:77faf76e3cd8	1842	case LSM6DSO_GY_ST_DISABLE:
cparata	4:77faf76e3cd8	1843	*val = LSM6DSO_GY_ST_DISABLE;
cparata	4:77faf76e3cd8	1844	break;
cparata	4:77faf76e3cd8	1845	case LSM6DSO_GY_ST_POSITIVE:
cparata	4:77faf76e3cd8	1846	*val = LSM6DSO_GY_ST_POSITIVE;
cparata	4:77faf76e3cd8	1847	break;
cparata	4:77faf76e3cd8	1848	case LSM6DSO_GY_ST_NEGATIVE:
cparata	4:77faf76e3cd8	1849	*val = LSM6DSO_GY_ST_NEGATIVE;
cparata	4:77faf76e3cd8	1850	break;
cparata	4:77faf76e3cd8	1851	default:
cparata	4:77faf76e3cd8	1852	*val = LSM6DSO_GY_ST_DISABLE;
cparata	4:77faf76e3cd8	1853	break;
cparata	4:77faf76e3cd8	1854	}
cparata	4:77faf76e3cd8	1855	return ret;
cparata	0:6d69e896ce38	1856	}
cparata	0:6d69e896ce38	1857
cparata	0:6d69e896ce38	1858	/**
cparata	0:6d69e896ce38	1859	* @}
cparata	0:6d69e896ce38	1860	*
cparata	0:6d69e896ce38	1861	*/
cparata	0:6d69e896ce38	1862
cparata	0:6d69e896ce38	1863	/**
cparata	0:6d69e896ce38	1864	* @defgroup LSM6DSO_filters
cparata	0:6d69e896ce38	1865	* @brief This section group all the functions concerning the
cparata	0:6d69e896ce38	1866	* filters configuration
cparata	0:6d69e896ce38	1867	* @{
cparata	0:6d69e896ce38	1868	*
cparata	0:6d69e896ce38	1869	*/
cparata	0:6d69e896ce38	1870
cparata	0:6d69e896ce38	1871	/**
cparata	0:6d69e896ce38	1872	* @brief Accelerometer output from LPF2 filtering stage selection.[set]
cparata	0:6d69e896ce38	1873	*
cparata	0:6d69e896ce38	1874	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1875	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:6d69e896ce38	1876	*
cparata	0:6d69e896ce38	1877	*/
cparata	0:6d69e896ce38	1878	int32_t lsm6dso_xl_filter_lp2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1879	{
cparata	4:77faf76e3cd8	1880	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	1881	int32_t ret;
cparata	4:77faf76e3cd8	1882
cparata	4:77faf76e3cd8	1883	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1884	if (ret == 0) {
cparata	4:77faf76e3cd8	1885	reg.lpf2_xl_en = val;
cparata	4:77faf76e3cd8	1886	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1887	}
cparata	4:77faf76e3cd8	1888	return ret;
cparata	0:6d69e896ce38	1889	}
cparata	0:6d69e896ce38	1890
cparata	0:6d69e896ce38	1891	/**
cparata	0:6d69e896ce38	1892	* @brief Accelerometer output from LPF2 filtering stage selection.[get]
cparata	0:6d69e896ce38	1893	*
cparata	0:6d69e896ce38	1894	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1895	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:6d69e896ce38	1896	*
cparata	0:6d69e896ce38	1897	*/
cparata	0:6d69e896ce38	1898	int32_t lsm6dso_xl_filter_lp2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1899	{
cparata	4:77faf76e3cd8	1900	lsm6dso_ctrl1_xl_t reg;
cparata	4:77faf76e3cd8	1901	int32_t ret;
cparata	4:77faf76e3cd8	1902
cparata	4:77faf76e3cd8	1903	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1904	*val = reg.lpf2_xl_en;
cparata	4:77faf76e3cd8	1905
cparata	4:77faf76e3cd8	1906	return ret;
cparata	0:6d69e896ce38	1907	}
cparata	0:6d69e896ce38	1908
cparata	0:6d69e896ce38	1909	/**
cparata	0:6d69e896ce38	1910	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:6d69e896ce38	1911	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:6d69e896ce38	1912	* in CTRL6_C (15h).[set]
cparata	0:6d69e896ce38	1913	*
cparata	0:6d69e896ce38	1914	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1915	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:6d69e896ce38	1916	*
cparata	0:6d69e896ce38	1917	*/
cparata	0:6d69e896ce38	1918	int32_t lsm6dso_gy_filter_lp1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1919	{
cparata	4:77faf76e3cd8	1920	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	1921	int32_t ret;
cparata	4:77faf76e3cd8	1922
cparata	4:77faf76e3cd8	1923	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1924	if (ret == 0) {
cparata	4:77faf76e3cd8	1925	reg.lpf1_sel_g = val;
cparata	4:77faf76e3cd8	1926	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1927	}
cparata	4:77faf76e3cd8	1928	return ret;
cparata	0:6d69e896ce38	1929	}
cparata	0:6d69e896ce38	1930
cparata	0:6d69e896ce38	1931	/**
cparata	0:6d69e896ce38	1932	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:6d69e896ce38	1933	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:6d69e896ce38	1934	* in CTRL6_C (15h).[get]
cparata	0:6d69e896ce38	1935	*
cparata	0:6d69e896ce38	1936	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1937	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:6d69e896ce38	1938	*
cparata	0:6d69e896ce38	1939	*/
cparata	0:6d69e896ce38	1940	int32_t lsm6dso_gy_filter_lp1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1941	{
cparata	4:77faf76e3cd8	1942	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	1943	int32_t ret;
cparata	4:77faf76e3cd8	1944
cparata	4:77faf76e3cd8	1945	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1946	*val = reg.lpf1_sel_g;
cparata	4:77faf76e3cd8	1947
cparata	4:77faf76e3cd8	1948	return ret;
cparata	0:6d69e896ce38	1949	}
cparata	0:6d69e896ce38	1950
cparata	0:6d69e896ce38	1951	/**
cparata	0:6d69e896ce38	1952	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:6d69e896ce38	1953	* (XL and Gyro independently masked).[set]
cparata	0:6d69e896ce38	1954	*
cparata	0:6d69e896ce38	1955	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1956	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:6d69e896ce38	1957	*
cparata	0:6d69e896ce38	1958	*/
cparata	0:6d69e896ce38	1959	int32_t lsm6dso_filter_settling_mask_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1960	{
cparata	4:77faf76e3cd8	1961	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	1962	int32_t ret;
cparata	4:77faf76e3cd8	1963
cparata	4:77faf76e3cd8	1964	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1965	if (ret == 0) {
cparata	4:77faf76e3cd8	1966	reg.drdy_mask = val;
cparata	4:77faf76e3cd8	1967	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1968	}
cparata	4:77faf76e3cd8	1969	return ret;
cparata	0:6d69e896ce38	1970	}
cparata	0:6d69e896ce38	1971
cparata	0:6d69e896ce38	1972	/**
cparata	0:6d69e896ce38	1973	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:6d69e896ce38	1974	* (XL and Gyro independently masked).[get]
cparata	0:6d69e896ce38	1975	*
cparata	0:6d69e896ce38	1976	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1977	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:6d69e896ce38	1978	*
cparata	0:6d69e896ce38	1979	*/
cparata	0:6d69e896ce38	1980	int32_t lsm6dso_filter_settling_mask_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1981	{
cparata	4:77faf76e3cd8	1982	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	1983	int32_t ret;
cparata	4:77faf76e3cd8	1984
cparata	4:77faf76e3cd8	1985	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	1986	*val = reg.drdy_mask;
cparata	4:77faf76e3cd8	1987
cparata	4:77faf76e3cd8	1988	return ret;
cparata	0:6d69e896ce38	1989	}
cparata	0:6d69e896ce38	1990
cparata	0:6d69e896ce38	1991	/**
cparata	0:6d69e896ce38	1992	* @brief Gyroscope lp1 bandwidth.[set]
cparata	0:6d69e896ce38	1993	*
cparata	0:6d69e896ce38	1994	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1995	* @param val change the values of ftype in reg CTRL6_C
cparata	0:6d69e896ce38	1996	*
cparata	0:6d69e896ce38	1997	*/
cparata	0:6d69e896ce38	1998	int32_t lsm6dso_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, lsm6dso_ftype_t val)
cparata	0:6d69e896ce38	1999	{
cparata	4:77faf76e3cd8	2000	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	2001	int32_t ret;
cparata	4:77faf76e3cd8	2002
cparata	4:77faf76e3cd8	2003	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2004	if (ret == 0) {
cparata	4:77faf76e3cd8	2005	reg.ftype = (uint8_t)val;
cparata	4:77faf76e3cd8	2006	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2007	}
cparata	4:77faf76e3cd8	2008	return ret;
cparata	0:6d69e896ce38	2009	}
cparata	0:6d69e896ce38	2010
cparata	0:6d69e896ce38	2011	/**
cparata	0:6d69e896ce38	2012	* @brief Gyroscope lp1 bandwidth.[get]
cparata	0:6d69e896ce38	2013	*
cparata	0:6d69e896ce38	2014	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2015	* @param val Get the values of ftype in reg CTRL6_C
cparata	0:6d69e896ce38	2016	*
cparata	0:6d69e896ce38	2017	*/
cparata	0:6d69e896ce38	2018	int32_t lsm6dso_gy_lp1_bandwidth_get(lsm6dso_ctx_t ctx, lsm6dso_ftype_t val)
cparata	0:6d69e896ce38	2019	{
cparata	4:77faf76e3cd8	2020	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	2021	int32_t ret;
cparata	4:77faf76e3cd8	2022
cparata	4:77faf76e3cd8	2023	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2024	switch (reg.ftype) {
cparata	4:77faf76e3cd8	2025	case LSM6DSO_ULTRA_LIGHT:
cparata	4:77faf76e3cd8	2026	*val = LSM6DSO_ULTRA_LIGHT;
cparata	4:77faf76e3cd8	2027	break;
cparata	4:77faf76e3cd8	2028	case LSM6DSO_VERY_LIGHT:
cparata	4:77faf76e3cd8	2029	*val = LSM6DSO_VERY_LIGHT;
cparata	4:77faf76e3cd8	2030	break;
cparata	4:77faf76e3cd8	2031	case LSM6DSO_LIGHT:
cparata	4:77faf76e3cd8	2032	*val = LSM6DSO_LIGHT;
cparata	4:77faf76e3cd8	2033	break;
cparata	4:77faf76e3cd8	2034	case LSM6DSO_MEDIUM:
cparata	4:77faf76e3cd8	2035	*val = LSM6DSO_MEDIUM;
cparata	4:77faf76e3cd8	2036	break;
cparata	4:77faf76e3cd8	2037	case LSM6DSO_STRONG:
cparata	4:77faf76e3cd8	2038	*val = LSM6DSO_STRONG;
cparata	4:77faf76e3cd8	2039	break;
cparata	4:77faf76e3cd8	2040	case LSM6DSO_VERY_STRONG:
cparata	4:77faf76e3cd8	2041	*val = LSM6DSO_VERY_STRONG;
cparata	4:77faf76e3cd8	2042	break;
cparata	4:77faf76e3cd8	2043	case LSM6DSO_AGGRESSIVE:
cparata	4:77faf76e3cd8	2044	*val = LSM6DSO_AGGRESSIVE;
cparata	4:77faf76e3cd8	2045	break;
cparata	4:77faf76e3cd8	2046	case LSM6DSO_XTREME:
cparata	4:77faf76e3cd8	2047	*val = LSM6DSO_XTREME;
cparata	4:77faf76e3cd8	2048	break;
cparata	4:77faf76e3cd8	2049	default:
cparata	4:77faf76e3cd8	2050	*val = LSM6DSO_ULTRA_LIGHT;
cparata	4:77faf76e3cd8	2051	break;
cparata	4:77faf76e3cd8	2052	}
cparata	4:77faf76e3cd8	2053	return ret;
cparata	0:6d69e896ce38	2054	}
cparata	0:6d69e896ce38	2055
cparata	0:6d69e896ce38	2056	/**
cparata	0:6d69e896ce38	2057	* @brief Low pass filter 2 on 6D function selection.[set]
cparata	0:6d69e896ce38	2058	*
cparata	0:6d69e896ce38	2059	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2060	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:6d69e896ce38	2061	*
cparata	0:6d69e896ce38	2062	*/
cparata	0:6d69e896ce38	2063	int32_t lsm6dso_xl_lp2_on_6d_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2064	{
cparata	4:77faf76e3cd8	2065	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2066	int32_t ret;
cparata	4:77faf76e3cd8	2067
cparata	4:77faf76e3cd8	2068	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2069	if (ret == 0) {
cparata	4:77faf76e3cd8	2070	reg.low_pass_on_6d = val;
cparata	4:77faf76e3cd8	2071	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2072	}
cparata	4:77faf76e3cd8	2073	return ret;
cparata	0:6d69e896ce38	2074	}
cparata	0:6d69e896ce38	2075
cparata	0:6d69e896ce38	2076	/**
cparata	0:6d69e896ce38	2077	* @brief Low pass filter 2 on 6D function selection.[get]
cparata	0:6d69e896ce38	2078	*
cparata	0:6d69e896ce38	2079	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2080	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:6d69e896ce38	2081	*
cparata	0:6d69e896ce38	2082	*/
cparata	0:6d69e896ce38	2083	int32_t lsm6dso_xl_lp2_on_6d_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2084	{
cparata	4:77faf76e3cd8	2085	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2086	int32_t ret;
cparata	4:77faf76e3cd8	2087
cparata	4:77faf76e3cd8	2088	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2089	*val = reg.low_pass_on_6d;
cparata	4:77faf76e3cd8	2090
cparata	4:77faf76e3cd8	2091	return ret;
cparata	0:6d69e896ce38	2092	}
cparata	0:6d69e896ce38	2093
cparata	0:6d69e896ce38	2094	/**
cparata	0:6d69e896ce38	2095	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:6d69e896ce38	2096	* on output.[set]
cparata	0:6d69e896ce38	2097	*
cparata	0:6d69e896ce38	2098	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2099	* @param val change the values of hp_slope_xl_en
cparata	0:6d69e896ce38	2100	* in reg CTRL8_XL
cparata	0:6d69e896ce38	2101	*
cparata	0:6d69e896ce38	2102	*/
cparata	0:6d69e896ce38	2103	int32_t lsm6dso_xl_hp_path_on_out_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2104	lsm6dso_hp_slope_xl_en_t val)
cparata	0:6d69e896ce38	2105	{
cparata	4:77faf76e3cd8	2106	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2107	int32_t ret;
cparata	4:77faf76e3cd8	2108
cparata	4:77faf76e3cd8	2109	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2110	if (ret == 0) {
cparata	4:77faf76e3cd8	2111	reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
cparata	4:77faf76e3cd8	2112	reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
cparata	4:77faf76e3cd8	2113	reg.hpcf_xl = (uint8_t)val & 0x07U;
cparata	4:77faf76e3cd8	2114	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2115	}
cparata	4:77faf76e3cd8	2116	return ret;
cparata	0:6d69e896ce38	2117	}
cparata	0:6d69e896ce38	2118
cparata	0:6d69e896ce38	2119	/**
cparata	0:6d69e896ce38	2120	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:6d69e896ce38	2121	* on output.[get]
cparata	0:6d69e896ce38	2122	*
cparata	0:6d69e896ce38	2123	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2124	* @param val Get the values of hp_slope_xl_en
cparata	0:6d69e896ce38	2125	* in reg CTRL8_XL
cparata	0:6d69e896ce38	2126	*
cparata	0:6d69e896ce38	2127	*/
cparata	0:6d69e896ce38	2128	int32_t lsm6dso_xl_hp_path_on_out_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2129	lsm6dso_hp_slope_xl_en_t *val)
cparata	0:6d69e896ce38	2130	{
cparata	4:77faf76e3cd8	2131	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2132	int32_t ret;
cparata	4:77faf76e3cd8	2133
cparata	4:77faf76e3cd8	2134	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2135	switch ((reg.hp_ref_mode_xl << 5) \| (reg.hp_slope_xl_en << 4) \|
cparata	4:77faf76e3cd8	2136	reg.hpcf_xl) {
cparata	4:77faf76e3cd8	2137	case LSM6DSO_HP_PATH_DISABLE_ON_OUT:
cparata	4:77faf76e3cd8	2138	*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
cparata	4:77faf76e3cd8	2139	break;
cparata	4:77faf76e3cd8	2140	case LSM6DSO_SLOPE_ODR_DIV_4:
cparata	4:77faf76e3cd8	2141	*val = LSM6DSO_SLOPE_ODR_DIV_4;
cparata	4:77faf76e3cd8	2142	break;
cparata	4:77faf76e3cd8	2143	case LSM6DSO_HP_ODR_DIV_10:
cparata	4:77faf76e3cd8	2144	*val = LSM6DSO_HP_ODR_DIV_10;
cparata	4:77faf76e3cd8	2145	break;
cparata	4:77faf76e3cd8	2146	case LSM6DSO_HP_ODR_DIV_20:
cparata	4:77faf76e3cd8	2147	*val = LSM6DSO_HP_ODR_DIV_20;
cparata	4:77faf76e3cd8	2148	break;
cparata	4:77faf76e3cd8	2149	case LSM6DSO_HP_ODR_DIV_45:
cparata	4:77faf76e3cd8	2150	*val = LSM6DSO_HP_ODR_DIV_45;
cparata	4:77faf76e3cd8	2151	break;
cparata	4:77faf76e3cd8	2152	case LSM6DSO_HP_ODR_DIV_100:
cparata	4:77faf76e3cd8	2153	*val = LSM6DSO_HP_ODR_DIV_100;
cparata	4:77faf76e3cd8	2154	break;
cparata	4:77faf76e3cd8	2155	case LSM6DSO_HP_ODR_DIV_200:
cparata	4:77faf76e3cd8	2156	*val = LSM6DSO_HP_ODR_DIV_200;
cparata	4:77faf76e3cd8	2157	break;
cparata	4:77faf76e3cd8	2158	case LSM6DSO_HP_ODR_DIV_400:
cparata	4:77faf76e3cd8	2159	*val = LSM6DSO_HP_ODR_DIV_400;
cparata	4:77faf76e3cd8	2160	break;
cparata	4:77faf76e3cd8	2161	case LSM6DSO_HP_ODR_DIV_800:
cparata	4:77faf76e3cd8	2162	*val = LSM6DSO_HP_ODR_DIV_800;
cparata	4:77faf76e3cd8	2163	break;
cparata	4:77faf76e3cd8	2164	case LSM6DSO_HP_REF_MD_ODR_DIV_10:
cparata	4:77faf76e3cd8	2165	*val = LSM6DSO_HP_REF_MD_ODR_DIV_10;
cparata	4:77faf76e3cd8	2166	break;
cparata	4:77faf76e3cd8	2167	case LSM6DSO_HP_REF_MD_ODR_DIV_20:
cparata	4:77faf76e3cd8	2168	*val = LSM6DSO_HP_REF_MD_ODR_DIV_20;
cparata	4:77faf76e3cd8	2169	break;
cparata	4:77faf76e3cd8	2170	case LSM6DSO_HP_REF_MD_ODR_DIV_45:
cparata	4:77faf76e3cd8	2171	*val = LSM6DSO_HP_REF_MD_ODR_DIV_45;
cparata	4:77faf76e3cd8	2172	break;
cparata	4:77faf76e3cd8	2173	case LSM6DSO_HP_REF_MD_ODR_DIV_100:
cparata	4:77faf76e3cd8	2174	*val = LSM6DSO_HP_REF_MD_ODR_DIV_100;
cparata	4:77faf76e3cd8	2175	break;
cparata	4:77faf76e3cd8	2176	case LSM6DSO_HP_REF_MD_ODR_DIV_200:
cparata	4:77faf76e3cd8	2177	*val = LSM6DSO_HP_REF_MD_ODR_DIV_200;
cparata	4:77faf76e3cd8	2178	break;
cparata	4:77faf76e3cd8	2179	case LSM6DSO_HP_REF_MD_ODR_DIV_400:
cparata	4:77faf76e3cd8	2180	*val = LSM6DSO_HP_REF_MD_ODR_DIV_400;
cparata	4:77faf76e3cd8	2181	break;
cparata	4:77faf76e3cd8	2182	case LSM6DSO_HP_REF_MD_ODR_DIV_800:
cparata	4:77faf76e3cd8	2183	*val = LSM6DSO_HP_REF_MD_ODR_DIV_800;
cparata	4:77faf76e3cd8	2184	break;
cparata	4:77faf76e3cd8	2185	case LSM6DSO_LP_ODR_DIV_10:
cparata	4:77faf76e3cd8	2186	*val = LSM6DSO_LP_ODR_DIV_10;
cparata	4:77faf76e3cd8	2187	break;
cparata	4:77faf76e3cd8	2188	case LSM6DSO_LP_ODR_DIV_20:
cparata	4:77faf76e3cd8	2189	*val = LSM6DSO_LP_ODR_DIV_20;
cparata	4:77faf76e3cd8	2190	break;
cparata	4:77faf76e3cd8	2191	case LSM6DSO_LP_ODR_DIV_45:
cparata	4:77faf76e3cd8	2192	*val = LSM6DSO_LP_ODR_DIV_45;
cparata	4:77faf76e3cd8	2193	break;
cparata	4:77faf76e3cd8	2194	case LSM6DSO_LP_ODR_DIV_100:
cparata	4:77faf76e3cd8	2195	*val = LSM6DSO_LP_ODR_DIV_100;
cparata	4:77faf76e3cd8	2196	break;
cparata	4:77faf76e3cd8	2197	case LSM6DSO_LP_ODR_DIV_200:
cparata	4:77faf76e3cd8	2198	*val = LSM6DSO_LP_ODR_DIV_200;
cparata	4:77faf76e3cd8	2199	break;
cparata	4:77faf76e3cd8	2200	case LSM6DSO_LP_ODR_DIV_400:
cparata	4:77faf76e3cd8	2201	*val = LSM6DSO_LP_ODR_DIV_400;
cparata	4:77faf76e3cd8	2202	break;
cparata	4:77faf76e3cd8	2203	case LSM6DSO_LP_ODR_DIV_800:
cparata	4:77faf76e3cd8	2204	*val = LSM6DSO_LP_ODR_DIV_800;
cparata	4:77faf76e3cd8	2205	break;
cparata	4:77faf76e3cd8	2206	default:
cparata	4:77faf76e3cd8	2207	*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
cparata	4:77faf76e3cd8	2208	break;
cparata	4:77faf76e3cd8	2209	}
cparata	4:77faf76e3cd8	2210
cparata	4:77faf76e3cd8	2211	return ret;
cparata	0:6d69e896ce38	2212	}
cparata	0:6d69e896ce38	2213
cparata	0:6d69e896ce38	2214	/**
cparata	0:6d69e896ce38	2215	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:6d69e896ce38	2216	* The filter sets the second samples after writing this bit.
cparata	0:6d69e896ce38	2217	* Active only during device exit from power-down mode.[set]
cparata	0:6d69e896ce38	2218	*
cparata	0:6d69e896ce38	2219	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2220	* @param val change the values of fastsettl_mode_xl in
cparata	0:6d69e896ce38	2221	* reg CTRL8_XL
cparata	0:6d69e896ce38	2222	*
cparata	0:6d69e896ce38	2223	*/
cparata	0:6d69e896ce38	2224	int32_t lsm6dso_xl_fast_settling_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2225	{
cparata	4:77faf76e3cd8	2226	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2227	int32_t ret;
cparata	4:77faf76e3cd8	2228
cparata	4:77faf76e3cd8	2229	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2230	if (ret == 0) {
cparata	4:77faf76e3cd8	2231	reg.fastsettl_mode_xl = val;
cparata	4:77faf76e3cd8	2232	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2233	}
cparata	4:77faf76e3cd8	2234	return ret;
cparata	0:6d69e896ce38	2235	}
cparata	0:6d69e896ce38	2236
cparata	0:6d69e896ce38	2237	/**
cparata	0:6d69e896ce38	2238	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:6d69e896ce38	2239	* The filter sets the second samples after writing this bit.
cparata	0:6d69e896ce38	2240	* Active only during device exit from power-down mode.[get]
cparata	0:6d69e896ce38	2241	*
cparata	0:6d69e896ce38	2242	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2243	* @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
cparata	0:6d69e896ce38	2244	*
cparata	0:6d69e896ce38	2245	*/
cparata	0:6d69e896ce38	2246	int32_t lsm6dso_xl_fast_settling_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2247	{
cparata	4:77faf76e3cd8	2248	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2249	int32_t ret;
cparata	4:77faf76e3cd8	2250
cparata	4:77faf76e3cd8	2251	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2252	*val = reg.fastsettl_mode_xl;
cparata	4:77faf76e3cd8	2253
cparata	4:77faf76e3cd8	2254	return ret;
cparata	0:6d69e896ce38	2255	}
cparata	0:6d69e896ce38	2256
cparata	0:6d69e896ce38	2257	/**
cparata	0:6d69e896ce38	2258	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:6d69e896ce38	2259	* functions.[set]
cparata	0:6d69e896ce38	2260	*
cparata	0:6d69e896ce38	2261	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2262	* @param val change the values of slope_fds in reg TAP_CFG0
cparata	0:6d69e896ce38	2263	*
cparata	0:6d69e896ce38	2264	*/
cparata	0:6d69e896ce38	2265	int32_t lsm6dso_xl_hp_path_internal_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2266	lsm6dso_slope_fds_t val)
cparata	0:6d69e896ce38	2267	{
cparata	4:77faf76e3cd8	2268	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	2269	int32_t ret;
cparata	4:77faf76e3cd8	2270
cparata	4:77faf76e3cd8	2271	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2272	if (ret == 0) {
cparata	4:77faf76e3cd8	2273	reg.slope_fds = (uint8_t)val;
cparata	4:77faf76e3cd8	2274	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2275	}
cparata	4:77faf76e3cd8	2276	return ret;
cparata	0:6d69e896ce38	2277	}
cparata	0:6d69e896ce38	2278
cparata	0:6d69e896ce38	2279	/**
cparata	0:6d69e896ce38	2280	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:6d69e896ce38	2281	* functions.[get]
cparata	0:6d69e896ce38	2282	*
cparata	0:6d69e896ce38	2283	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2284	* @param val Get the values of slope_fds in reg TAP_CFG0
cparata	0:6d69e896ce38	2285	*
cparata	0:6d69e896ce38	2286	*/
cparata	0:6d69e896ce38	2287	int32_t lsm6dso_xl_hp_path_internal_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2288	lsm6dso_slope_fds_t *val)
cparata	0:6d69e896ce38	2289	{
cparata	4:77faf76e3cd8	2290	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	2291	int32_t ret;
cparata	4:77faf76e3cd8	2292
cparata	4:77faf76e3cd8	2293	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2294	switch (reg.slope_fds) {
cparata	4:77faf76e3cd8	2295	case LSM6DSO_USE_SLOPE:
cparata	4:77faf76e3cd8	2296	*val = LSM6DSO_USE_SLOPE;
cparata	4:77faf76e3cd8	2297	break;
cparata	4:77faf76e3cd8	2298	case LSM6DSO_USE_HPF:
cparata	4:77faf76e3cd8	2299	*val = LSM6DSO_USE_HPF;
cparata	4:77faf76e3cd8	2300	break;
cparata	4:77faf76e3cd8	2301	default:
cparata	4:77faf76e3cd8	2302	*val = LSM6DSO_USE_SLOPE;
cparata	4:77faf76e3cd8	2303	break;
cparata	4:77faf76e3cd8	2304	}
cparata	4:77faf76e3cd8	2305	return ret;
cparata	0:6d69e896ce38	2306	}
cparata	0:6d69e896ce38	2307
cparata	0:6d69e896ce38	2308	/**
cparata	0:6d69e896ce38	2309	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:6d69e896ce38	2310	* enabled only if the gyro is in HP mode.[set]
cparata	0:6d69e896ce38	2311	*
cparata	0:6d69e896ce38	2312	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2313	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:6d69e896ce38	2314	* in reg CTRL7_G
cparata	0:6d69e896ce38	2315	*
cparata	0:6d69e896ce38	2316	*/
cparata	0:6d69e896ce38	2317	int32_t lsm6dso_gy_hp_path_internal_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2318	lsm6dso_hpm_g_t val)
cparata	0:6d69e896ce38	2319	{
cparata	4:77faf76e3cd8	2320	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	2321	int32_t ret;
cparata	4:77faf76e3cd8	2322
cparata	4:77faf76e3cd8	2323	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2324	if (ret == 0) {
cparata	4:77faf76e3cd8	2325	reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
cparata	4:77faf76e3cd8	2326	reg.hpm_g = (uint8_t)val & 0x03U;
cparata	4:77faf76e3cd8	2327	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2328	}
cparata	4:77faf76e3cd8	2329	return ret;
cparata	0:6d69e896ce38	2330	}
cparata	0:6d69e896ce38	2331
cparata	0:6d69e896ce38	2332	/**
cparata	0:6d69e896ce38	2333	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:6d69e896ce38	2334	* enabled only if the gyro is in HP mode.[get]
cparata	0:6d69e896ce38	2335	*
cparata	0:6d69e896ce38	2336	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2337	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:6d69e896ce38	2338	* in reg CTRL7_G
cparata	0:6d69e896ce38	2339	*
cparata	0:6d69e896ce38	2340	*/
cparata	0:6d69e896ce38	2341	int32_t lsm6dso_gy_hp_path_internal_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2342	lsm6dso_hpm_g_t *val)
cparata	0:6d69e896ce38	2343	{
cparata	4:77faf76e3cd8	2344	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	2345	int32_t ret;
cparata	4:77faf76e3cd8	2346
cparata	4:77faf76e3cd8	2347	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2348	switch ((reg.hp_en_g << 7) + reg.hpm_g) {
cparata	4:77faf76e3cd8	2349	case LSM6DSO_HP_FILTER_NONE:
cparata	4:77faf76e3cd8	2350	*val = LSM6DSO_HP_FILTER_NONE;
cparata	4:77faf76e3cd8	2351	break;
cparata	4:77faf76e3cd8	2352	case LSM6DSO_HP_FILTER_16mHz:
cparata	4:77faf76e3cd8	2353	*val = LSM6DSO_HP_FILTER_16mHz;
cparata	4:77faf76e3cd8	2354	break;
cparata	4:77faf76e3cd8	2355	case LSM6DSO_HP_FILTER_65mHz:
cparata	4:77faf76e3cd8	2356	*val = LSM6DSO_HP_FILTER_65mHz;
cparata	4:77faf76e3cd8	2357	break;
cparata	4:77faf76e3cd8	2358	case LSM6DSO_HP_FILTER_260mHz:
cparata	4:77faf76e3cd8	2359	*val = LSM6DSO_HP_FILTER_260mHz;
cparata	4:77faf76e3cd8	2360	break;
cparata	4:77faf76e3cd8	2361	case LSM6DSO_HP_FILTER_1Hz04:
cparata	4:77faf76e3cd8	2362	*val = LSM6DSO_HP_FILTER_1Hz04;
cparata	4:77faf76e3cd8	2363	break;
cparata	4:77faf76e3cd8	2364	default:
cparata	4:77faf76e3cd8	2365	*val = LSM6DSO_HP_FILTER_NONE;
cparata	4:77faf76e3cd8	2366	break;
cparata	4:77faf76e3cd8	2367	}
cparata	4:77faf76e3cd8	2368	return ret;
cparata	0:6d69e896ce38	2369	}
cparata	0:6d69e896ce38	2370
cparata	0:6d69e896ce38	2371	/**
cparata	0:6d69e896ce38	2372	* @}
cparata	0:6d69e896ce38	2373	*
cparata	0:6d69e896ce38	2374	*/
cparata	0:6d69e896ce38	2375
cparata	0:6d69e896ce38	2376	/**
cparata	0:6d69e896ce38	2377	* @defgroup LSM6DSO_ Auxiliary_interface
cparata	0:6d69e896ce38	2378	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	2379	* auxiliary interface.
cparata	0:6d69e896ce38	2380	* @{
cparata	0:6d69e896ce38	2381	*
cparata	0:6d69e896ce38	2382	*/
cparata	0:6d69e896ce38	2383
cparata	0:6d69e896ce38	2384	/**
cparata	0:6d69e896ce38	2385	* @brief aOn auxiliary interface connect/disconnect SDO and OCS
cparata	0:6d69e896ce38	2386	* internal pull-up.[set]
cparata	0:6d69e896ce38	2387	*
cparata	0:6d69e896ce38	2388	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2389	* @param val change the values of ois_pu_dis in
cparata	0:6d69e896ce38	2390	* reg PIN_CTRL
cparata	0:6d69e896ce38	2391	*
cparata	0:6d69e896ce38	2392	*/
cparata	0:6d69e896ce38	2393	int32_t lsm6dso_aux_sdo_ocs_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2394	lsm6dso_ois_pu_dis_t val)
cparata	0:6d69e896ce38	2395	{
cparata	4:77faf76e3cd8	2396	lsm6dso_pin_ctrl_t reg;
cparata	4:77faf76e3cd8	2397	int32_t ret;
cparata	4:77faf76e3cd8	2398
cparata	4:77faf76e3cd8	2399	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2400	if (ret == 0) {
cparata	4:77faf76e3cd8	2401	reg.ois_pu_dis = (uint8_t)val;
cparata	4:77faf76e3cd8	2402	ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2403	}
cparata	4:77faf76e3cd8	2404	return ret;
cparata	0:6d69e896ce38	2405	}
cparata	0:6d69e896ce38	2406
cparata	0:6d69e896ce38	2407	/**
cparata	0:6d69e896ce38	2408	* @brief On auxiliary interface connect/disconnect SDO and OCS
cparata	0:6d69e896ce38	2409	* internal pull-up.[get]
cparata	0:6d69e896ce38	2410	*
cparata	0:6d69e896ce38	2411	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2412	* @param val Get the values of ois_pu_dis in reg PIN_CTRL
cparata	0:6d69e896ce38	2413	*
cparata	0:6d69e896ce38	2414	*/
cparata	0:6d69e896ce38	2415	int32_t lsm6dso_aux_sdo_ocs_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2416	lsm6dso_ois_pu_dis_t *val)
cparata	0:6d69e896ce38	2417	{
cparata	4:77faf76e3cd8	2418	lsm6dso_pin_ctrl_t reg;
cparata	4:77faf76e3cd8	2419	int32_t ret;
cparata	4:77faf76e3cd8	2420
cparata	4:77faf76e3cd8	2421	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2422	switch (reg.ois_pu_dis) {
cparata	4:77faf76e3cd8	2423	case LSM6DSO_AUX_PULL_UP_DISC:
cparata	4:77faf76e3cd8	2424	*val = LSM6DSO_AUX_PULL_UP_DISC;
cparata	4:77faf76e3cd8	2425	break;
cparata	4:77faf76e3cd8	2426	case LSM6DSO_AUX_PULL_UP_CONNECT:
cparata	4:77faf76e3cd8	2427	*val = LSM6DSO_AUX_PULL_UP_CONNECT;
cparata	4:77faf76e3cd8	2428	break;
cparata	4:77faf76e3cd8	2429	default:
cparata	4:77faf76e3cd8	2430	*val = LSM6DSO_AUX_PULL_UP_DISC;
cparata	4:77faf76e3cd8	2431	break;
cparata	4:77faf76e3cd8	2432	}
cparata	4:77faf76e3cd8	2433	return ret;
cparata	0:6d69e896ce38	2434	}
cparata	0:6d69e896ce38	2435
cparata	0:6d69e896ce38	2436	/**
cparata	0:6d69e896ce38	2437	* @brief OIS chain on aux interface power on mode.[set]
cparata	0:6d69e896ce38	2438	*
cparata	0:6d69e896ce38	2439	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2440	* @param val change the values of ois_on in reg CTRL7_G
cparata	0:6d69e896ce38	2441	*
cparata	0:6d69e896ce38	2442	*/
cparata	0:6d69e896ce38	2443	int32_t lsm6dso_aux_pw_on_ctrl_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t val)
cparata	0:6d69e896ce38	2444	{
cparata	4:77faf76e3cd8	2445	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	2446	int32_t ret;
cparata	4:77faf76e3cd8	2447
cparata	4:77faf76e3cd8	2448	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2449	if (ret == 0) {
cparata	4:77faf76e3cd8	2450	reg.ois_on_en = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	2451	reg.ois_on = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	2452	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2453	}
cparata	4:77faf76e3cd8	2454	return ret;
cparata	0:6d69e896ce38	2455	}
cparata	0:6d69e896ce38	2456
cparata	0:6d69e896ce38	2457	/**
cparata	0:6d69e896ce38	2458	* @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode
cparata	0:6d69e896ce38	2459	*
cparata	0:6d69e896ce38	2460	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2461	* @param val Get the values of ois_on in reg CTRL7_G
cparata	0:6d69e896ce38	2462	*
cparata	0:6d69e896ce38	2463	*/
cparata	0:6d69e896ce38	2464	int32_t lsm6dso_aux_pw_on_ctrl_get(lsm6dso_ctx_t ctx, lsm6dso_ois_on_t val)
cparata	0:6d69e896ce38	2465	{
cparata	4:77faf76e3cd8	2466	lsm6dso_ctrl7_g_t reg;
cparata	4:77faf76e3cd8	2467	int32_t ret;
cparata	4:77faf76e3cd8	2468
cparata	4:77faf76e3cd8	2469	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2470	switch (reg.ois_on) {
cparata	4:77faf76e3cd8	2471	case LSM6DSO_AUX_ON:
cparata	4:77faf76e3cd8	2472	*val = LSM6DSO_AUX_ON;
cparata	4:77faf76e3cd8	2473	break;
cparata	4:77faf76e3cd8	2474	case LSM6DSO_AUX_ON_BY_AUX_INTERFACE:
cparata	4:77faf76e3cd8	2475	*val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE;
cparata	4:77faf76e3cd8	2476	break;
cparata	4:77faf76e3cd8	2477	default:
cparata	4:77faf76e3cd8	2478	*val = LSM6DSO_AUX_ON;
cparata	4:77faf76e3cd8	2479	break;
cparata	4:77faf76e3cd8	2480	}
cparata	4:77faf76e3cd8	2481
cparata	4:77faf76e3cd8	2482	return ret;
cparata	0:6d69e896ce38	2483	}
cparata	0:6d69e896ce38	2484
cparata	0:6d69e896ce38	2485	/**
cparata	0:6d69e896ce38	2486	* @brief Accelerometer full-scale management between UI chain and
cparata	0:6d69e896ce38	2487	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:6d69e896ce38	2488	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:6d69e896ce38	2489	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:6d69e896ce38	2490	* Full scales are independent between the UI/OIS chain
cparata	0:6d69e896ce38	2491	* but both bound to 8 g.[set]
cparata	0:6d69e896ce38	2492	*
cparata	0:6d69e896ce38	2493	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2494	* @param val change the values of xl_fs_mode in
cparata	0:6d69e896ce38	2495	* reg CTRL8_XL
cparata	0:6d69e896ce38	2496	*
cparata	0:6d69e896ce38	2497	*/
cparata	0:6d69e896ce38	2498	int32_t lsm6dso_aux_xl_fs_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2499	lsm6dso_xl_fs_mode_t val)
cparata	0:6d69e896ce38	2500	{
cparata	4:77faf76e3cd8	2501	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2502	int32_t ret;
cparata	4:77faf76e3cd8	2503
cparata	4:77faf76e3cd8	2504	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2505	if (ret == 0) {
cparata	4:77faf76e3cd8	2506	reg.xl_fs_mode = (uint8_t)val;
cparata	4:77faf76e3cd8	2507	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2508	}
cparata	4:77faf76e3cd8	2509	return ret;
cparata	0:6d69e896ce38	2510	}
cparata	0:6d69e896ce38	2511
cparata	0:6d69e896ce38	2512	/**
cparata	0:6d69e896ce38	2513	* @brief Accelerometer full-scale management between UI chain and
cparata	0:6d69e896ce38	2514	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:6d69e896ce38	2515	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:6d69e896ce38	2516	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:6d69e896ce38	2517	* Full scales are independent between the UI/OIS chain
cparata	0:6d69e896ce38	2518	* but both bound to 8 g.[get]
cparata	0:6d69e896ce38	2519	*
cparata	0:6d69e896ce38	2520	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2521	* @param val Get the values of xl_fs_mode in reg CTRL8_XL
cparata	0:6d69e896ce38	2522	*
cparata	0:6d69e896ce38	2523	*/
cparata	0:6d69e896ce38	2524	int32_t lsm6dso_aux_xl_fs_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2525	lsm6dso_xl_fs_mode_t *val)
cparata	0:6d69e896ce38	2526	{
cparata	4:77faf76e3cd8	2527	lsm6dso_ctrl8_xl_t reg;
cparata	4:77faf76e3cd8	2528	int32_t ret;
cparata	4:77faf76e3cd8	2529
cparata	4:77faf76e3cd8	2530	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2531	switch (reg.xl_fs_mode) {
cparata	4:77faf76e3cd8	2532	case LSM6DSO_USE_SAME_XL_FS:
cparata	4:77faf76e3cd8	2533	*val = LSM6DSO_USE_SAME_XL_FS;
cparata	4:77faf76e3cd8	2534	break;
cparata	4:77faf76e3cd8	2535	case LSM6DSO_USE_DIFFERENT_XL_FS:
cparata	4:77faf76e3cd8	2536	*val = LSM6DSO_USE_DIFFERENT_XL_FS;
cparata	4:77faf76e3cd8	2537	break;
cparata	4:77faf76e3cd8	2538	default:
cparata	4:77faf76e3cd8	2539	*val = LSM6DSO_USE_SAME_XL_FS;
cparata	4:77faf76e3cd8	2540	break;
cparata	4:77faf76e3cd8	2541	}
cparata	4:77faf76e3cd8	2542
cparata	4:77faf76e3cd8	2543	return ret;
cparata	0:6d69e896ce38	2544	}
cparata	0:6d69e896ce38	2545
cparata	0:6d69e896ce38	2546	/**
cparata	0:6d69e896ce38	2547	* @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
cparata	0:6d69e896ce38	2548	*
cparata	0:6d69e896ce38	2549	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2550	* @param lsm6dso_status_spiaux_t: registers STATUS_SPIAUX
cparata	0:6d69e896ce38	2551	*
cparata	0:6d69e896ce38	2552	*/
cparata	0:6d69e896ce38	2553	int32_t lsm6dso_aux_status_reg_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2554	lsm6dso_status_spiaux_t *val)
cparata	0:6d69e896ce38	2555	{
cparata	4:77faf76e3cd8	2556	int32_t ret;
cparata	4:77faf76e3cd8	2557	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*) val, 1);
cparata	4:77faf76e3cd8	2558	return ret;
cparata	0:6d69e896ce38	2559	}
cparata	0:6d69e896ce38	2560
cparata	0:6d69e896ce38	2561	/**
cparata	0:6d69e896ce38	2562	* @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available
cparata	0:6d69e896ce38	2563	*
cparata	0:6d69e896ce38	2564	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2565	* @param val change the values of xlda in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2566	*
cparata	0:6d69e896ce38	2567	*/
cparata	0:6d69e896ce38	2568	int32_t lsm6dso_aux_xl_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2569	{
cparata	4:77faf76e3cd8	2570	lsm6dso_status_spiaux_t reg;
cparata	4:77faf76e3cd8	2571	int32_t ret;
cparata	4:77faf76e3cd8	2572
cparata	4:77faf76e3cd8	2573	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2574	*val = reg.xlda;
cparata	4:77faf76e3cd8	2575
cparata	4:77faf76e3cd8	2576	return ret;
cparata	0:6d69e896ce38	2577	}
cparata	0:6d69e896ce38	2578
cparata	0:6d69e896ce38	2579	/**
cparata	0:6d69e896ce38	2580	* @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available.
cparata	0:6d69e896ce38	2581	*
cparata	0:6d69e896ce38	2582	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2583	* @param val change the values of gda in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2584	*
cparata	0:6d69e896ce38	2585	*/
cparata	0:6d69e896ce38	2586	int32_t lsm6dso_aux_gy_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2587	{
cparata	4:77faf76e3cd8	2588	lsm6dso_status_spiaux_t reg;
cparata	4:77faf76e3cd8	2589	int32_t ret;
cparata	4:77faf76e3cd8	2590
cparata	4:77faf76e3cd8	2591	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2592	*val = reg.gda;
cparata	4:77faf76e3cd8	2593
cparata	4:77faf76e3cd8	2594	return ret;
cparata	0:6d69e896ce38	2595	}
cparata	0:6d69e896ce38	2596
cparata	0:6d69e896ce38	2597	/**
cparata	0:6d69e896ce38	2598	* @brief High when the gyroscope output is in the settling phase.[get]
cparata	0:6d69e896ce38	2599	*
cparata	0:6d69e896ce38	2600	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2601	* @param val change the values of gyro_settling in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2602	*
cparata	0:6d69e896ce38	2603	*/
cparata	0:6d69e896ce38	2604	int32_t lsm6dso_aux_gy_flag_settling_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2605	{
cparata	4:77faf76e3cd8	2606	lsm6dso_status_spiaux_t reg;
cparata	4:77faf76e3cd8	2607	int32_t ret;
cparata	4:77faf76e3cd8	2608
cparata	4:77faf76e3cd8	2609	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2610	*val = reg.gyro_settling;
cparata	4:77faf76e3cd8	2611
cparata	4:77faf76e3cd8	2612	return ret;
cparata	0:6d69e896ce38	2613	}
cparata	0:6d69e896ce38	2614
cparata	0:6d69e896ce38	2615	/**
cparata	0:6d69e896ce38	2616	* @brief Selects accelerometer self-test. Effective only if XL OIS
cparata	0:6d69e896ce38	2617	* chain is enabled.[set]
cparata	0:6d69e896ce38	2618	*
cparata	0:6d69e896ce38	2619	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2620	* @param val change the values of st_xl_ois in reg INT_OIS
cparata	0:6d69e896ce38	2621	*
cparata	0:6d69e896ce38	2622	*/
cparata	0:6d69e896ce38	2623	int32_t lsm6dso_aux_xl_self_test_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2624	lsm6dso_st_xl_ois_t val)
cparata	0:6d69e896ce38	2625	{
cparata	4:77faf76e3cd8	2626	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2627	int32_t ret;
cparata	4:77faf76e3cd8	2628
cparata	4:77faf76e3cd8	2629	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2630	if (ret == 0) {
cparata	4:77faf76e3cd8	2631	reg.st_xl_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	2632	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2633	}
cparata	4:77faf76e3cd8	2634	return ret;
cparata	0:6d69e896ce38	2635	}
cparata	0:6d69e896ce38	2636
cparata	0:6d69e896ce38	2637	/**
cparata	0:6d69e896ce38	2638	* @brief Selects accelerometer self-test. Effective only if XL OIS
cparata	0:6d69e896ce38	2639	* chain is enabled.[get]
cparata	0:6d69e896ce38	2640	*
cparata	0:6d69e896ce38	2641	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2642	* @param val Get the values of st_xl_ois in reg INT_OIS
cparata	0:6d69e896ce38	2643	*
cparata	0:6d69e896ce38	2644	*/
cparata	0:6d69e896ce38	2645	int32_t lsm6dso_aux_xl_self_test_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2646	lsm6dso_st_xl_ois_t *val)
cparata	0:6d69e896ce38	2647	{
cparata	4:77faf76e3cd8	2648	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2649	int32_t ret;
cparata	4:77faf76e3cd8	2650
cparata	4:77faf76e3cd8	2651	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2652	switch (reg.st_xl_ois) {
cparata	4:77faf76e3cd8	2653	case LSM6DSO_AUX_XL_DISABLE:
cparata	4:77faf76e3cd8	2654	*val = LSM6DSO_AUX_XL_DISABLE;
cparata	4:77faf76e3cd8	2655	break;
cparata	4:77faf76e3cd8	2656	case LSM6DSO_AUX_XL_POS:
cparata	4:77faf76e3cd8	2657	*val = LSM6DSO_AUX_XL_POS;
cparata	4:77faf76e3cd8	2658	break;
cparata	4:77faf76e3cd8	2659	case LSM6DSO_AUX_XL_NEG:
cparata	4:77faf76e3cd8	2660	*val = LSM6DSO_AUX_XL_NEG;
cparata	4:77faf76e3cd8	2661	break;
cparata	4:77faf76e3cd8	2662	default:
cparata	4:77faf76e3cd8	2663	*val = LSM6DSO_AUX_XL_DISABLE;
cparata	4:77faf76e3cd8	2664	break;
cparata	4:77faf76e3cd8	2665	}
cparata	4:77faf76e3cd8	2666	return ret;
cparata	0:6d69e896ce38	2667	}
cparata	0:6d69e896ce38	2668
cparata	0:6d69e896ce38	2669	/**
cparata	0:6d69e896ce38	2670	* @brief Indicates polarity of DEN signal on OIS chain.[set]
cparata	0:6d69e896ce38	2671	*
cparata	0:6d69e896ce38	2672	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2673	* @param val change the values of den_lh_ois in
cparata	0:6d69e896ce38	2674	* reg INT_OIS
cparata	0:6d69e896ce38	2675	*
cparata	0:6d69e896ce38	2676	*/
cparata	0:6d69e896ce38	2677	int32_t lsm6dso_aux_den_polarity_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2678	lsm6dso_den_lh_ois_t val)
cparata	0:6d69e896ce38	2679	{
cparata	4:77faf76e3cd8	2680	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2681	int32_t ret;
cparata	4:77faf76e3cd8	2682
cparata	4:77faf76e3cd8	2683	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2684	if (ret == 0) {
cparata	4:77faf76e3cd8	2685	reg.den_lh_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	2686	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2687	}
cparata	4:77faf76e3cd8	2688	return ret;
cparata	0:6d69e896ce38	2689	}
cparata	0:6d69e896ce38	2690
cparata	0:6d69e896ce38	2691	/**
cparata	0:6d69e896ce38	2692	* @brief Indicates polarity of DEN signal on OIS chain.[get]
cparata	0:6d69e896ce38	2693	*
cparata	0:6d69e896ce38	2694	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2695	* @param val Get the values of den_lh_ois in reg INT_OIS
cparata	0:6d69e896ce38	2696	*
cparata	0:6d69e896ce38	2697	*/
cparata	0:6d69e896ce38	2698	int32_t lsm6dso_aux_den_polarity_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2699	lsm6dso_den_lh_ois_t *val)
cparata	0:6d69e896ce38	2700	{
cparata	4:77faf76e3cd8	2701	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2702	int32_t ret;
cparata	4:77faf76e3cd8	2703
cparata	4:77faf76e3cd8	2704	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2705	switch (reg.den_lh_ois) {
cparata	4:77faf76e3cd8	2706	case LSM6DSO_AUX_DEN_ACTIVE_LOW:
cparata	4:77faf76e3cd8	2707	*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
cparata	4:77faf76e3cd8	2708	break;
cparata	4:77faf76e3cd8	2709	case LSM6DSO_AUX_DEN_ACTIVE_HIGH:
cparata	4:77faf76e3cd8	2710	*val = LSM6DSO_AUX_DEN_ACTIVE_HIGH;
cparata	4:77faf76e3cd8	2711	break;
cparata	4:77faf76e3cd8	2712	default:
cparata	4:77faf76e3cd8	2713	*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
cparata	4:77faf76e3cd8	2714	break;
cparata	4:77faf76e3cd8	2715	}
cparata	4:77faf76e3cd8	2716	return ret;
cparata	0:6d69e896ce38	2717	}
cparata	0:6d69e896ce38	2718
cparata	0:6d69e896ce38	2719	/**
cparata	0:6d69e896ce38	2720	* @brief Configure DEN mode on the OIS chain.[set]
cparata	0:6d69e896ce38	2721	*
cparata	0:6d69e896ce38	2722	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2723	* @param val change the values of lvl2_ois in reg INT_OIS
cparata	0:6d69e896ce38	2724	*
cparata	0:6d69e896ce38	2725	*/
cparata	0:6d69e896ce38	2726	int32_t lsm6dso_aux_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t val)
cparata	0:6d69e896ce38	2727	{
cparata	4:77faf76e3cd8	2728	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	4:77faf76e3cd8	2729	lsm6dso_int_ois_t int_ois;
cparata	4:77faf76e3cd8	2730	int32_t ret;
cparata	4:77faf76e3cd8	2731
cparata	4:77faf76e3cd8	2732	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	4:77faf76e3cd8	2733	if (ret == 0) {
cparata	4:77faf76e3cd8	2734	int_ois.lvl2_ois = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	2735	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	4:77faf76e3cd8	2736	}
cparata	4:77faf76e3cd8	2737	if (ret == 0) {
cparata	4:77faf76e3cd8	2738	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	4:77faf76e3cd8	2739	}
cparata	4:77faf76e3cd8	2740	if (ret == 0) {
cparata	4:77faf76e3cd8	2741	ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
cparata	4:77faf76e3cd8	2742	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	4:77faf76e3cd8	2743	}
cparata	4:77faf76e3cd8	2744	return ret;
cparata	0:6d69e896ce38	2745	}
cparata	0:6d69e896ce38	2746
cparata	0:6d69e896ce38	2747	/**
cparata	0:6d69e896ce38	2748	* @brief Configure DEN mode on the OIS chain.[get]
cparata	0:6d69e896ce38	2749	*
cparata	0:6d69e896ce38	2750	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2751	* @param val Get the values of lvl2_ois in reg INT_OIS
cparata	0:6d69e896ce38	2752	*
cparata	0:6d69e896ce38	2753	*/
cparata	0:6d69e896ce38	2754	int32_t lsm6dso_aux_den_mode_get(lsm6dso_ctx_t ctx, lsm6dso_lvl2_ois_t val)
cparata	0:6d69e896ce38	2755	{
cparata	4:77faf76e3cd8	2756	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	4:77faf76e3cd8	2757	lsm6dso_int_ois_t int_ois;
cparata	4:77faf76e3cd8	2758	int32_t ret;
cparata	4:77faf76e3cd8	2759
cparata	4:77faf76e3cd8	2760	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	4:77faf76e3cd8	2761	if (ret == 0) {
cparata	4:77faf76e3cd8	2762	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	4:77faf76e3cd8	2763	switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) {
cparata	4:77faf76e3cd8	2764	case LSM6DSO_AUX_DEN_DISABLE:
cparata	4:77faf76e3cd8	2765	*val = LSM6DSO_AUX_DEN_DISABLE;
cparata	4:77faf76e3cd8	2766	break;
cparata	4:77faf76e3cd8	2767	case LSM6DSO_AUX_DEN_LEVEL_LATCH:
cparata	4:77faf76e3cd8	2768	*val = LSM6DSO_AUX_DEN_LEVEL_LATCH;
cparata	4:77faf76e3cd8	2769	break;
cparata	4:77faf76e3cd8	2770	case LSM6DSO_AUX_DEN_LEVEL_TRIG:
cparata	4:77faf76e3cd8	2771	*val = LSM6DSO_AUX_DEN_LEVEL_TRIG;
cparata	4:77faf76e3cd8	2772	break;
cparata	4:77faf76e3cd8	2773	default:
cparata	4:77faf76e3cd8	2774	*val = LSM6DSO_AUX_DEN_DISABLE;
cparata	4:77faf76e3cd8	2775	break;
cparata	3:4274d9103f1d	2776	}
cparata	4:77faf76e3cd8	2777	}
cparata	4:77faf76e3cd8	2778	return ret;
cparata	0:6d69e896ce38	2779	}
cparata	0:6d69e896ce38	2780
cparata	0:6d69e896ce38	2781	/**
cparata	0:6d69e896ce38	2782	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:6d69e896ce38	2783	* This setting has priority over all other INT2 settings.[set]
cparata	0:6d69e896ce38	2784	*
cparata	0:6d69e896ce38	2785	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2786	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:6d69e896ce38	2787	*
cparata	0:6d69e896ce38	2788	*/
cparata	0:6d69e896ce38	2789	int32_t lsm6dso_aux_drdy_on_int2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2790	{
cparata	4:77faf76e3cd8	2791	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2792	int32_t ret;
cparata	4:77faf76e3cd8	2793
cparata	4:77faf76e3cd8	2794	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2795	if (ret == 0) {
cparata	4:77faf76e3cd8	2796	reg.int2_drdy_ois = val;
cparata	4:77faf76e3cd8	2797	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2798	}
cparata	4:77faf76e3cd8	2799	return ret;
cparata	0:6d69e896ce38	2800	}
cparata	0:6d69e896ce38	2801
cparata	0:6d69e896ce38	2802	/**
cparata	0:6d69e896ce38	2803	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:6d69e896ce38	2804	* This setting has priority over all other INT2 settings.[get]
cparata	0:6d69e896ce38	2805	*
cparata	0:6d69e896ce38	2806	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2807	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:6d69e896ce38	2808	*
cparata	0:6d69e896ce38	2809	*/
cparata	0:6d69e896ce38	2810	int32_t lsm6dso_aux_drdy_on_int2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2811	{
cparata	4:77faf76e3cd8	2812	lsm6dso_int_ois_t reg;
cparata	4:77faf76e3cd8	2813	int32_t ret;
cparata	4:77faf76e3cd8	2814
cparata	4:77faf76e3cd8	2815	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2816	*val = reg.int2_drdy_ois;
cparata	4:77faf76e3cd8	2817
cparata	4:77faf76e3cd8	2818	return ret;
cparata	0:6d69e896ce38	2819	}
cparata	0:6d69e896ce38	2820
cparata	0:6d69e896ce38	2821	/**
cparata	0:6d69e896ce38	2822	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:6d69e896ce38	2823	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:6d69e896ce38	2824	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:6d69e896ce38	2825	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:6d69e896ce38	2826	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:6d69e896ce38	2827	* LPF1 is dedicated to this chain.[set]
cparata	0:6d69e896ce38	2828	*
cparata	0:6d69e896ce38	2829	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2830	* @param val change the values of ois_en_spi2 in
cparata	0:6d69e896ce38	2831	* reg CTRL1_OIS
cparata	0:6d69e896ce38	2832	*
cparata	0:6d69e896ce38	2833	*/
cparata	0:6d69e896ce38	2834	int32_t lsm6dso_aux_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t val)
cparata	0:6d69e896ce38	2835	{
cparata	4:77faf76e3cd8	2836	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2837	int32_t ret;
cparata	4:77faf76e3cd8	2838
cparata	4:77faf76e3cd8	2839	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2840	if (ret == 0) {
cparata	4:77faf76e3cd8	2841	reg.ois_en_spi2 = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	2842	reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
cparata	4:77faf76e3cd8	2843	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2844	}
cparata	4:77faf76e3cd8	2845	return ret;
cparata	0:6d69e896ce38	2846	}
cparata	0:6d69e896ce38	2847
cparata	0:6d69e896ce38	2848	/**
cparata	0:6d69e896ce38	2849	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:6d69e896ce38	2850	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:6d69e896ce38	2851	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:6d69e896ce38	2852	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:6d69e896ce38	2853	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:6d69e896ce38	2854	* LPF1 is dedicated to this chain.[get]
cparata	0:6d69e896ce38	2855	*
cparata	0:6d69e896ce38	2856	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2857	* @param val Get the values of ois_en_spi2 in
cparata	0:6d69e896ce38	2858	* reg CTRL1_OIS
cparata	0:6d69e896ce38	2859	*
cparata	0:6d69e896ce38	2860	*/
cparata	0:6d69e896ce38	2861	int32_t lsm6dso_aux_mode_get(lsm6dso_ctx_t ctx, lsm6dso_ois_en_spi2_t val)
cparata	0:6d69e896ce38	2862	{
cparata	4:77faf76e3cd8	2863	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2864	int32_t ret;
cparata	4:77faf76e3cd8	2865
cparata	4:77faf76e3cd8	2866	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2867	switch ((reg.mode4_en << 1) \| reg.ois_en_spi2) {
cparata	4:77faf76e3cd8	2868	case LSM6DSO_AUX_DISABLE:
cparata	4:77faf76e3cd8	2869	*val = LSM6DSO_AUX_DISABLE;
cparata	4:77faf76e3cd8	2870	break;
cparata	4:77faf76e3cd8	2871	case LSM6DSO_MODE_3_GY:
cparata	4:77faf76e3cd8	2872	*val = LSM6DSO_MODE_3_GY;
cparata	4:77faf76e3cd8	2873	break;
cparata	4:77faf76e3cd8	2874	case LSM6DSO_MODE_4_GY_XL:
cparata	4:77faf76e3cd8	2875	*val = LSM6DSO_MODE_4_GY_XL;
cparata	4:77faf76e3cd8	2876	break;
cparata	4:77faf76e3cd8	2877	default:
cparata	4:77faf76e3cd8	2878	*val = LSM6DSO_AUX_DISABLE;
cparata	4:77faf76e3cd8	2879	break;
cparata	4:77faf76e3cd8	2880	}
cparata	4:77faf76e3cd8	2881	return ret;
cparata	0:6d69e896ce38	2882	}
cparata	0:6d69e896ce38	2883
cparata	0:6d69e896ce38	2884	/**
cparata	0:6d69e896ce38	2885	* @brief Selects gyroscope OIS chain full-scale.[set]
cparata	0:6d69e896ce38	2886	*
cparata	0:6d69e896ce38	2887	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2888	* @param val change the values of fs_g_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2889	*
cparata	0:6d69e896ce38	2890	*/
cparata	0:6d69e896ce38	2891	int32_t lsm6dso_aux_gy_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2892	lsm6dso_fs_g_ois_t val)
cparata	0:6d69e896ce38	2893	{
cparata	4:77faf76e3cd8	2894	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2895	int32_t ret;
cparata	4:77faf76e3cd8	2896
cparata	4:77faf76e3cd8	2897	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2898	if (ret == 0) {
cparata	4:77faf76e3cd8	2899	reg.fs_g_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	2900	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2901	}
cparata	4:77faf76e3cd8	2902	return ret;
cparata	0:6d69e896ce38	2903	}
cparata	0:6d69e896ce38	2904
cparata	0:6d69e896ce38	2905	/**
cparata	0:6d69e896ce38	2906	* @brief Selects gyroscope OIS chain full-scale.[get]
cparata	0:6d69e896ce38	2907	*
cparata	0:6d69e896ce38	2908	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2909	* @param val Get the values of fs_g_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2910	*
cparata	0:6d69e896ce38	2911	*/
cparata	0:6d69e896ce38	2912	int32_t lsm6dso_aux_gy_full_scale_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2913	lsm6dso_fs_g_ois_t *val)
cparata	0:6d69e896ce38	2914	{
cparata	4:77faf76e3cd8	2915	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2916	int32_t ret;
cparata	4:77faf76e3cd8	2917
cparata	4:77faf76e3cd8	2918	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2919	switch (reg.fs_g_ois) {
cparata	4:77faf76e3cd8	2920	case LSM6DSO_250dps_AUX:
cparata	4:77faf76e3cd8	2921	*val = LSM6DSO_250dps_AUX;
cparata	4:77faf76e3cd8	2922	break;
cparata	4:77faf76e3cd8	2923	case LSM6DSO_125dps_AUX:
cparata	4:77faf76e3cd8	2924	*val = LSM6DSO_125dps_AUX;
cparata	4:77faf76e3cd8	2925	break;
cparata	4:77faf76e3cd8	2926	case LSM6DSO_500dps_AUX:
cparata	4:77faf76e3cd8	2927	*val = LSM6DSO_500dps_AUX;
cparata	4:77faf76e3cd8	2928	break;
cparata	4:77faf76e3cd8	2929	case LSM6DSO_1000dps_AUX:
cparata	4:77faf76e3cd8	2930	*val = LSM6DSO_1000dps_AUX;
cparata	4:77faf76e3cd8	2931	break;
cparata	4:77faf76e3cd8	2932	case LSM6DSO_2000dps_AUX:
cparata	4:77faf76e3cd8	2933	*val = LSM6DSO_2000dps_AUX;
cparata	4:77faf76e3cd8	2934	break;
cparata	4:77faf76e3cd8	2935	default:
cparata	4:77faf76e3cd8	2936	*val = LSM6DSO_250dps_AUX;
cparata	4:77faf76e3cd8	2937	break;
cparata	4:77faf76e3cd8	2938	}
cparata	4:77faf76e3cd8	2939	return ret;
cparata	0:6d69e896ce38	2940	}
cparata	0:6d69e896ce38	2941
cparata	0:6d69e896ce38	2942	/**
cparata	0:6d69e896ce38	2943	* @brief SPI2 3- or 4-wire interface.[set]
cparata	0:6d69e896ce38	2944	*
cparata	0:6d69e896ce38	2945	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2946	* @param val change the values of sim_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2947	*
cparata	0:6d69e896ce38	2948	*/
cparata	0:6d69e896ce38	2949	int32_t lsm6dso_aux_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t val)
cparata	0:6d69e896ce38	2950	{
cparata	4:77faf76e3cd8	2951	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2952	int32_t ret;
cparata	4:77faf76e3cd8	2953
cparata	4:77faf76e3cd8	2954	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2955	if (ret == 0) {
cparata	4:77faf76e3cd8	2956	reg.sim_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	2957	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2958	}
cparata	4:77faf76e3cd8	2959	return ret;
cparata	0:6d69e896ce38	2960	}
cparata	0:6d69e896ce38	2961
cparata	0:6d69e896ce38	2962	/**
cparata	0:6d69e896ce38	2963	* @brief SPI2 3- or 4-wire interface.[get]
cparata	0:6d69e896ce38	2964	*
cparata	0:6d69e896ce38	2965	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2966	* @param val Get the values of sim_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2967	*
cparata	0:6d69e896ce38	2968	*/
cparata	0:6d69e896ce38	2969	int32_t lsm6dso_aux_spi_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sim_ois_t val)
cparata	0:6d69e896ce38	2970	{
cparata	4:77faf76e3cd8	2971	lsm6dso_ctrl1_ois_t reg;
cparata	4:77faf76e3cd8	2972	int32_t ret;
cparata	4:77faf76e3cd8	2973
cparata	4:77faf76e3cd8	2974	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	2975	switch (reg.sim_ois) {
cparata	4:77faf76e3cd8	2976	case LSM6DSO_AUX_SPI_4_WIRE:
cparata	4:77faf76e3cd8	2977	*val = LSM6DSO_AUX_SPI_4_WIRE;
cparata	4:77faf76e3cd8	2978	break;
cparata	4:77faf76e3cd8	2979	case LSM6DSO_AUX_SPI_3_WIRE:
cparata	4:77faf76e3cd8	2980	*val = LSM6DSO_AUX_SPI_3_WIRE;
cparata	4:77faf76e3cd8	2981	break;
cparata	4:77faf76e3cd8	2982	default:
cparata	4:77faf76e3cd8	2983	*val = LSM6DSO_AUX_SPI_4_WIRE;
cparata	4:77faf76e3cd8	2984	break;
cparata	4:77faf76e3cd8	2985	}
cparata	4:77faf76e3cd8	2986	return ret;
cparata	0:6d69e896ce38	2987	}
cparata	0:6d69e896ce38	2988
cparata	0:6d69e896ce38	2989	/**
cparata	0:6d69e896ce38	2990	* @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
cparata	0:6d69e896ce38	2991	*
cparata	0:6d69e896ce38	2992	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2993	* @param val change the values of ftype_ois in
cparata	0:6d69e896ce38	2994	* reg CTRL2_OIS
cparata	0:6d69e896ce38	2995	*
cparata	0:6d69e896ce38	2996	*/
cparata	0:6d69e896ce38	2997	int32_t lsm6dso_aux_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2998	lsm6dso_ftype_ois_t val)
cparata	0:6d69e896ce38	2999	{
cparata	4:77faf76e3cd8	3000	lsm6dso_ctrl2_ois_t reg;
cparata	4:77faf76e3cd8	3001	int32_t ret;
cparata	4:77faf76e3cd8	3002
cparata	4:77faf76e3cd8	3003	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3004	if (ret == 0) {
cparata	4:77faf76e3cd8	3005	reg.ftype_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	3006	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3007	}
cparata	4:77faf76e3cd8	3008	return ret;
cparata	0:6d69e896ce38	3009	}
cparata	0:6d69e896ce38	3010
cparata	0:6d69e896ce38	3011	/**
cparata	0:6d69e896ce38	3012	* @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
cparata	0:6d69e896ce38	3013	*
cparata	0:6d69e896ce38	3014	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3015	* @param val Get the values of ftype_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	3016	*
cparata	0:6d69e896ce38	3017	*/
cparata	0:6d69e896ce38	3018	int32_t lsm6dso_aux_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3019	lsm6dso_ftype_ois_t *val)
cparata	0:6d69e896ce38	3020	{
cparata	4:77faf76e3cd8	3021	lsm6dso_ctrl2_ois_t reg;
cparata	4:77faf76e3cd8	3022	int32_t ret;
cparata	4:77faf76e3cd8	3023
cparata	4:77faf76e3cd8	3024	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3025	switch (reg.ftype_ois) {
cparata	4:77faf76e3cd8	3026	case LSM6DSO_351Hz39:
cparata	4:77faf76e3cd8	3027	*val = LSM6DSO_351Hz39;
cparata	4:77faf76e3cd8	3028	break;
cparata	4:77faf76e3cd8	3029	case LSM6DSO_236Hz63:
cparata	4:77faf76e3cd8	3030	*val = LSM6DSO_236Hz63;
cparata	4:77faf76e3cd8	3031	break;
cparata	4:77faf76e3cd8	3032	case LSM6DSO_172Hz70:
cparata	4:77faf76e3cd8	3033	*val = LSM6DSO_172Hz70;
cparata	4:77faf76e3cd8	3034	break;
cparata	4:77faf76e3cd8	3035	case LSM6DSO_937Hz91:
cparata	4:77faf76e3cd8	3036	*val = LSM6DSO_937Hz91;
cparata	4:77faf76e3cd8	3037	break;
cparata	4:77faf76e3cd8	3038	default:
cparata	4:77faf76e3cd8	3039	*val = LSM6DSO_351Hz39;
cparata	4:77faf76e3cd8	3040	break;
cparata	4:77faf76e3cd8	3041	}
cparata	4:77faf76e3cd8	3042	return ret;
cparata	0:6d69e896ce38	3043	}
cparata	0:6d69e896ce38	3044
cparata	0:6d69e896ce38	3045	/**
cparata	0:6d69e896ce38	3046	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
cparata	0:6d69e896ce38	3047	*
cparata	0:6d69e896ce38	3048	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3049	* @param val change the values of hpm_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	3050	*
cparata	0:6d69e896ce38	3051	*/
cparata	0:6d69e896ce38	3052	int32_t lsm6dso_aux_gy_hp_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3053	lsm6dso_hpm_ois_t val)
cparata	0:6d69e896ce38	3054	{
cparata	4:77faf76e3cd8	3055	lsm6dso_ctrl2_ois_t reg;
cparata	4:77faf76e3cd8	3056	int32_t ret;
cparata	4:77faf76e3cd8	3057
cparata	4:77faf76e3cd8	3058	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3059	if (ret == 0) {
cparata	4:77faf76e3cd8	3060	reg.hpm_ois = (uint8_t)val & 0x03U;
cparata	4:77faf76e3cd8	3061	reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
cparata	4:77faf76e3cd8	3062	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3063	}
cparata	4:77faf76e3cd8	3064	return ret;
cparata	0:6d69e896ce38	3065	}
cparata	0:6d69e896ce38	3066
cparata	0:6d69e896ce38	3067	/**
cparata	0:6d69e896ce38	3068	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
cparata	0:6d69e896ce38	3069	*
cparata	0:6d69e896ce38	3070	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3071	* @param val Get the values of hpm_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	3072	*
cparata	0:6d69e896ce38	3073	*/
cparata	0:6d69e896ce38	3074	int32_t lsm6dso_aux_gy_hp_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3075	lsm6dso_hpm_ois_t *val)
cparata	0:6d69e896ce38	3076	{
cparata	4:77faf76e3cd8	3077	lsm6dso_ctrl2_ois_t reg;
cparata	4:77faf76e3cd8	3078	int32_t ret;
cparata	4:77faf76e3cd8	3079
cparata	4:77faf76e3cd8	3080	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3081	switch ((reg.hp_en_ois << 4) \| reg.hpm_ois) {
cparata	4:77faf76e3cd8	3082	case LSM6DSO_AUX_HP_DISABLE:
cparata	4:77faf76e3cd8	3083	*val = LSM6DSO_AUX_HP_DISABLE;
cparata	4:77faf76e3cd8	3084	break;
cparata	4:77faf76e3cd8	3085	case LSM6DSO_AUX_HP_Hz016:
cparata	4:77faf76e3cd8	3086	*val = LSM6DSO_AUX_HP_Hz016;
cparata	4:77faf76e3cd8	3087	break;
cparata	4:77faf76e3cd8	3088	case LSM6DSO_AUX_HP_Hz065:
cparata	4:77faf76e3cd8	3089	*val = LSM6DSO_AUX_HP_Hz065;
cparata	4:77faf76e3cd8	3090	break;
cparata	4:77faf76e3cd8	3091	case LSM6DSO_AUX_HP_Hz260:
cparata	4:77faf76e3cd8	3092	*val = LSM6DSO_AUX_HP_Hz260;
cparata	4:77faf76e3cd8	3093	break;
cparata	4:77faf76e3cd8	3094	case LSM6DSO_AUX_HP_1Hz040:
cparata	4:77faf76e3cd8	3095	*val = LSM6DSO_AUX_HP_1Hz040;
cparata	4:77faf76e3cd8	3096	break;
cparata	4:77faf76e3cd8	3097	default:
cparata	4:77faf76e3cd8	3098	*val = LSM6DSO_AUX_HP_DISABLE;
cparata	4:77faf76e3cd8	3099	break;
cparata	4:77faf76e3cd8	3100	}
cparata	4:77faf76e3cd8	3101	return ret;
cparata	0:6d69e896ce38	3102	}
cparata	0:6d69e896ce38	3103
cparata	0:6d69e896ce38	3104	/**
cparata	0:6d69e896ce38	3105	* @brief Enable / Disables OIS chain clamp.
cparata	0:6d69e896ce38	3106	* Enable: All OIS chain outputs = 8000h
cparata	0:6d69e896ce38	3107	* during self-test; Disable: OIS chain self-test
cparata	0:6d69e896ce38	3108	* outputs dependent from the aux gyro full
cparata	0:6d69e896ce38	3109	* scale selected.[set]
cparata	0:6d69e896ce38	3110	*
cparata	0:6d69e896ce38	3111	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3112	* @param val change the values of st_ois_clampdis in
cparata	0:6d69e896ce38	3113	* reg CTRL3_OIS
cparata	0:6d69e896ce38	3114	*
cparata	0:6d69e896ce38	3115	*/
cparata	0:6d69e896ce38	3116	int32_t lsm6dso_aux_gy_clamp_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3117	lsm6dso_st_ois_clampdis_t val)
cparata	0:6d69e896ce38	3118	{
cparata	4:77faf76e3cd8	3119	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3120	int32_t ret;
cparata	4:77faf76e3cd8	3121
cparata	4:77faf76e3cd8	3122	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3123	if (ret == 0) {
cparata	4:77faf76e3cd8	3124	reg.st_ois_clampdis = (uint8_t)val;
cparata	4:77faf76e3cd8	3125	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3126	}
cparata	4:77faf76e3cd8	3127	return ret;
cparata	0:6d69e896ce38	3128	}
cparata	0:6d69e896ce38	3129
cparata	0:6d69e896ce38	3130	/**
cparata	0:6d69e896ce38	3131	* @brief Enable / Disables OIS chain clamp.
cparata	0:6d69e896ce38	3132	* Enable: All OIS chain outputs = 8000h
cparata	0:6d69e896ce38	3133	* during self-test; Disable: OIS chain self-test
cparata	0:6d69e896ce38	3134	* outputs dependent from the aux gyro full
cparata	0:6d69e896ce38	3135	* scale selected.[set]
cparata	0:6d69e896ce38	3136	*
cparata	0:6d69e896ce38	3137	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3138	* @param val Get the values of st_ois_clampdis in
cparata	0:6d69e896ce38	3139	* reg CTRL3_OIS
cparata	0:6d69e896ce38	3140	*
cparata	0:6d69e896ce38	3141	*/
cparata	0:6d69e896ce38	3142	int32_t lsm6dso_aux_gy_clamp_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3143	lsm6dso_st_ois_clampdis_t *val)
cparata	0:6d69e896ce38	3144	{
cparata	4:77faf76e3cd8	3145	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3146	int32_t ret;
cparata	4:77faf76e3cd8	3147
cparata	4:77faf76e3cd8	3148	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3149	switch (reg.st_ois_clampdis) {
cparata	4:77faf76e3cd8	3150	case LSM6DSO_ENABLE_CLAMP:
cparata	4:77faf76e3cd8	3151	*val = LSM6DSO_ENABLE_CLAMP;
cparata	4:77faf76e3cd8	3152	break;
cparata	4:77faf76e3cd8	3153	case LSM6DSO_DISABLE_CLAMP:
cparata	4:77faf76e3cd8	3154	*val = LSM6DSO_DISABLE_CLAMP;
cparata	4:77faf76e3cd8	3155	break;
cparata	4:77faf76e3cd8	3156	default:
cparata	4:77faf76e3cd8	3157	*val = LSM6DSO_ENABLE_CLAMP;
cparata	4:77faf76e3cd8	3158	break;
cparata	4:77faf76e3cd8	3159	}
cparata	4:77faf76e3cd8	3160	return ret;
cparata	0:6d69e896ce38	3161	}
cparata	0:6d69e896ce38	3162
cparata	0:6d69e896ce38	3163	/**
cparata	0:6d69e896ce38	3164	* @brief Selects gyroscope OIS chain self-test.[set]
cparata	0:6d69e896ce38	3165	*
cparata	0:6d69e896ce38	3166	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3167	* @param val change the values of st_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3168	*
cparata	0:6d69e896ce38	3169	*/
cparata	0:6d69e896ce38	3170	int32_t lsm6dso_aux_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_ois_t val)
cparata	0:6d69e896ce38	3171	{
cparata	4:77faf76e3cd8	3172	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3173	int32_t ret;
cparata	4:77faf76e3cd8	3174
cparata	4:77faf76e3cd8	3175	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3176	if (ret == 0) {
cparata	4:77faf76e3cd8	3177	reg.st_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	3178	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3179	}
cparata	4:77faf76e3cd8	3180	return ret;
cparata	0:6d69e896ce38	3181	}
cparata	0:6d69e896ce38	3182
cparata	0:6d69e896ce38	3183	/**
cparata	0:6d69e896ce38	3184	* @brief Selects gyroscope OIS chain self-test.[get]
cparata	0:6d69e896ce38	3185	*
cparata	0:6d69e896ce38	3186	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3187	* @param val Get the values of st_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3188	*
cparata	0:6d69e896ce38	3189	*/
cparata	0:6d69e896ce38	3190	int32_t lsm6dso_aux_gy_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_ois_t val)
cparata	0:6d69e896ce38	3191	{
cparata	4:77faf76e3cd8	3192	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3193	int32_t ret;
cparata	4:77faf76e3cd8	3194
cparata	4:77faf76e3cd8	3195	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3196	switch (reg.st_ois) {
cparata	4:77faf76e3cd8	3197	case LSM6DSO_AUX_GY_DISABLE:
cparata	4:77faf76e3cd8	3198	*val = LSM6DSO_AUX_GY_DISABLE;
cparata	4:77faf76e3cd8	3199	break;
cparata	4:77faf76e3cd8	3200	case LSM6DSO_AUX_GY_POS:
cparata	4:77faf76e3cd8	3201	*val = LSM6DSO_AUX_GY_POS;
cparata	4:77faf76e3cd8	3202	break;
cparata	4:77faf76e3cd8	3203	case LSM6DSO_AUX_GY_NEG:
cparata	4:77faf76e3cd8	3204	*val = LSM6DSO_AUX_GY_NEG;
cparata	4:77faf76e3cd8	3205	break;
cparata	4:77faf76e3cd8	3206	default:
cparata	4:77faf76e3cd8	3207	*val = LSM6DSO_AUX_GY_DISABLE;
cparata	4:77faf76e3cd8	3208	break;
cparata	4:77faf76e3cd8	3209	}
cparata	4:77faf76e3cd8	3210	return ret;
cparata	0:6d69e896ce38	3211	}
cparata	0:6d69e896ce38	3212
cparata	0:6d69e896ce38	3213	/**
cparata	0:6d69e896ce38	3214	* @brief Selects accelerometer OIS channel bandwidth.[set]
cparata	0:6d69e896ce38	3215	*
cparata	0:6d69e896ce38	3216	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3217	* @param val change the values of
cparata	0:6d69e896ce38	3218	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3219	*
cparata	0:6d69e896ce38	3220	*/
cparata	0:6d69e896ce38	3221	int32_t lsm6dso_aux_xl_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3222	lsm6dso_filter_xl_conf_ois_t val)
cparata	0:6d69e896ce38	3223	{
cparata	4:77faf76e3cd8	3224	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3225	int32_t ret;
cparata	4:77faf76e3cd8	3226
cparata	4:77faf76e3cd8	3227	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3228	if (ret == 0) {
cparata	4:77faf76e3cd8	3229	reg.filter_xl_conf_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	3230	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3231	}
cparata	4:77faf76e3cd8	3232	return ret;
cparata	0:6d69e896ce38	3233	}
cparata	0:6d69e896ce38	3234
cparata	0:6d69e896ce38	3235	/**
cparata	0:6d69e896ce38	3236	* @brief Selects accelerometer OIS channel bandwidth.[get]
cparata	0:6d69e896ce38	3237	*
cparata	0:6d69e896ce38	3238	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3239	* @param val Get the values of
cparata	0:6d69e896ce38	3240	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3241	*
cparata	0:6d69e896ce38	3242	*/
cparata	0:6d69e896ce38	3243	int32_t lsm6dso_aux_xl_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3244	lsm6dso_filter_xl_conf_ois_t *val)
cparata	0:6d69e896ce38	3245	{
cparata	4:77faf76e3cd8	3246	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3247	int32_t ret;
cparata	4:77faf76e3cd8	3248
cparata	4:77faf76e3cd8	3249	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3250
cparata	4:77faf76e3cd8	3251	switch (reg.filter_xl_conf_ois) {
cparata	4:77faf76e3cd8	3252	case LSM6DSO_289Hz:
cparata	4:77faf76e3cd8	3253	*val = LSM6DSO_289Hz;
cparata	4:77faf76e3cd8	3254	break;
cparata	4:77faf76e3cd8	3255	case LSM6DSO_258Hz:
cparata	4:77faf76e3cd8	3256	*val = LSM6DSO_258Hz;
cparata	4:77faf76e3cd8	3257	break;
cparata	4:77faf76e3cd8	3258	case LSM6DSO_120Hz:
cparata	4:77faf76e3cd8	3259	*val = LSM6DSO_120Hz;
cparata	4:77faf76e3cd8	3260	break;
cparata	4:77faf76e3cd8	3261	case LSM6DSO_65Hz2:
cparata	4:77faf76e3cd8	3262	*val = LSM6DSO_65Hz2;
cparata	4:77faf76e3cd8	3263	break;
cparata	4:77faf76e3cd8	3264	case LSM6DSO_33Hz2:
cparata	4:77faf76e3cd8	3265	*val = LSM6DSO_33Hz2;
cparata	4:77faf76e3cd8	3266	break;
cparata	4:77faf76e3cd8	3267	case LSM6DSO_16Hz6:
cparata	4:77faf76e3cd8	3268	*val = LSM6DSO_16Hz6;
cparata	4:77faf76e3cd8	3269	break;
cparata	4:77faf76e3cd8	3270	case LSM6DSO_8Hz30:
cparata	4:77faf76e3cd8	3271	*val = LSM6DSO_8Hz30;
cparata	4:77faf76e3cd8	3272	break;
cparata	4:77faf76e3cd8	3273	case LSM6DSO_4Hz15:
cparata	4:77faf76e3cd8	3274	*val = LSM6DSO_4Hz15;
cparata	4:77faf76e3cd8	3275	break;
cparata	4:77faf76e3cd8	3276	default:
cparata	4:77faf76e3cd8	3277	*val = LSM6DSO_289Hz;
cparata	4:77faf76e3cd8	3278	break;
cparata	4:77faf76e3cd8	3279	}
cparata	4:77faf76e3cd8	3280	return ret;
cparata	0:6d69e896ce38	3281	}
cparata	0:6d69e896ce38	3282
cparata	0:6d69e896ce38	3283	/**
cparata	0:6d69e896ce38	3284	* @brief Selects accelerometer OIS channel full-scale.[set]
cparata	0:6d69e896ce38	3285	*
cparata	0:6d69e896ce38	3286	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3287	* @param val change the values of fs_xl_ois in
cparata	0:6d69e896ce38	3288	* reg CTRL3_OIS
cparata	0:6d69e896ce38	3289	*
cparata	0:6d69e896ce38	3290	*/
cparata	0:6d69e896ce38	3291	int32_t lsm6dso_aux_xl_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3292	lsm6dso_fs_xl_ois_t val)
cparata	0:6d69e896ce38	3293	{
cparata	4:77faf76e3cd8	3294	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3295	int32_t ret;
cparata	4:77faf76e3cd8	3296
cparata	4:77faf76e3cd8	3297	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3298	if (ret == 0) {
cparata	4:77faf76e3cd8	3299	reg.fs_xl_ois = (uint8_t)val;
cparata	4:77faf76e3cd8	3300	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3301	}
cparata	4:77faf76e3cd8	3302	return ret;
cparata	0:6d69e896ce38	3303	}
cparata	0:6d69e896ce38	3304
cparata	0:6d69e896ce38	3305	/**
cparata	0:6d69e896ce38	3306	* @brief Selects accelerometer OIS channel full-scale.[get]
cparata	0:6d69e896ce38	3307	*
cparata	0:6d69e896ce38	3308	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3309	* @param val Get the values of fs_xl_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3310	*
cparata	0:6d69e896ce38	3311	*/
cparata	0:6d69e896ce38	3312	int32_t lsm6dso_aux_xl_full_scale_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3313	lsm6dso_fs_xl_ois_t *val)
cparata	0:6d69e896ce38	3314	{
cparata	4:77faf76e3cd8	3315	lsm6dso_ctrl3_ois_t reg;
cparata	4:77faf76e3cd8	3316	int32_t ret;
cparata	4:77faf76e3cd8	3317
cparata	4:77faf76e3cd8	3318	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3319	switch (reg.fs_xl_ois) {
cparata	4:77faf76e3cd8	3320	case LSM6DSO_AUX_2g:
cparata	4:77faf76e3cd8	3321	*val = LSM6DSO_AUX_2g;
cparata	4:77faf76e3cd8	3322	break;
cparata	4:77faf76e3cd8	3323	case LSM6DSO_AUX_16g:
cparata	4:77faf76e3cd8	3324	*val = LSM6DSO_AUX_16g;
cparata	4:77faf76e3cd8	3325	break;
cparata	4:77faf76e3cd8	3326	case LSM6DSO_AUX_4g:
cparata	4:77faf76e3cd8	3327	*val = LSM6DSO_AUX_4g;
cparata	4:77faf76e3cd8	3328	break;
cparata	4:77faf76e3cd8	3329	case LSM6DSO_AUX_8g:
cparata	4:77faf76e3cd8	3330	*val = LSM6DSO_AUX_8g;
cparata	4:77faf76e3cd8	3331	break;
cparata	4:77faf76e3cd8	3332	default:
cparata	4:77faf76e3cd8	3333	*val = LSM6DSO_AUX_2g;
cparata	4:77faf76e3cd8	3334	break;
cparata	4:77faf76e3cd8	3335	}
cparata	4:77faf76e3cd8	3336	return ret;
cparata	0:6d69e896ce38	3337	}
cparata	0:6d69e896ce38	3338
cparata	0:6d69e896ce38	3339	/**
cparata	0:6d69e896ce38	3340	* @}
cparata	0:6d69e896ce38	3341	*
cparata	0:6d69e896ce38	3342	*/
cparata	0:6d69e896ce38	3343
cparata	0:6d69e896ce38	3344	/**
cparata	0:6d69e896ce38	3345	* @defgroup LSM6DSO_ main_serial_interface
cparata	0:6d69e896ce38	3346	* @brief This section groups all the functions concerning main
cparata	0:6d69e896ce38	3347	* serial interface management (not auxiliary)
cparata	0:6d69e896ce38	3348	* @{
cparata	0:6d69e896ce38	3349	*
cparata	0:6d69e896ce38	3350	*/
cparata	0:6d69e896ce38	3351
cparata	0:6d69e896ce38	3352	/**
cparata	0:6d69e896ce38	3353	* @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
cparata	0:6d69e896ce38	3354	*
cparata	0:6d69e896ce38	3355	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3356	* @param val change the values of sdo_pu_en in
cparata	0:6d69e896ce38	3357	* reg PIN_CTRL
cparata	0:6d69e896ce38	3358	*
cparata	0:6d69e896ce38	3359	*/
cparata	0:6d69e896ce38	3360	int32_t lsm6dso_sdo_sa0_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sdo_pu_en_t val)
cparata	0:6d69e896ce38	3361	{
cparata	4:77faf76e3cd8	3362	lsm6dso_pin_ctrl_t reg;
cparata	4:77faf76e3cd8	3363	int32_t ret;
cparata	4:77faf76e3cd8	3364
cparata	4:77faf76e3cd8	3365	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3366	if (ret == 0) {
cparata	4:77faf76e3cd8	3367	reg.sdo_pu_en = (uint8_t)val;
cparata	4:77faf76e3cd8	3368	ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3369	}
cparata	4:77faf76e3cd8	3370	return ret;
cparata	0:6d69e896ce38	3371	}
cparata	0:6d69e896ce38	3372
cparata	0:6d69e896ce38	3373	/**
cparata	0:6d69e896ce38	3374	* @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
cparata	0:6d69e896ce38	3375	*
cparata	0:6d69e896ce38	3376	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3377	* @param val Get the values of sdo_pu_en in reg PIN_CTRL
cparata	0:6d69e896ce38	3378	*
cparata	0:6d69e896ce38	3379	*/
cparata	0:6d69e896ce38	3380	int32_t lsm6dso_sdo_sa0_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sdo_pu_en_t val)
cparata	0:6d69e896ce38	3381	{
cparata	4:77faf76e3cd8	3382	lsm6dso_pin_ctrl_t reg;
cparata	4:77faf76e3cd8	3383	int32_t ret;
cparata	4:77faf76e3cd8	3384
cparata	4:77faf76e3cd8	3385	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3386	switch (reg.sdo_pu_en) {
cparata	4:77faf76e3cd8	3387	case LSM6DSO_PULL_UP_DISC:
cparata	4:77faf76e3cd8	3388	*val = LSM6DSO_PULL_UP_DISC;
cparata	4:77faf76e3cd8	3389	break;
cparata	4:77faf76e3cd8	3390	case LSM6DSO_PULL_UP_CONNECT:
cparata	4:77faf76e3cd8	3391	*val = LSM6DSO_PULL_UP_CONNECT;
cparata	4:77faf76e3cd8	3392	break;
cparata	4:77faf76e3cd8	3393	default:
cparata	4:77faf76e3cd8	3394	*val = LSM6DSO_PULL_UP_DISC;
cparata	4:77faf76e3cd8	3395	break;
cparata	4:77faf76e3cd8	3396	}
cparata	4:77faf76e3cd8	3397	return ret;
cparata	0:6d69e896ce38	3398	}
cparata	0:6d69e896ce38	3399
cparata	0:6d69e896ce38	3400	/**
cparata	0:6d69e896ce38	3401	* @brief SPI Serial Interface Mode selection.[set]
cparata	0:6d69e896ce38	3402	*
cparata	0:6d69e896ce38	3403	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3404	* @param val change the values of sim in reg CTRL3_C
cparata	0:6d69e896ce38	3405	*
cparata	0:6d69e896ce38	3406	*/
cparata	0:6d69e896ce38	3407	int32_t lsm6dso_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_t val)
cparata	0:6d69e896ce38	3408	{
cparata	4:77faf76e3cd8	3409	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	3410	int32_t ret;
cparata	4:77faf76e3cd8	3411
cparata	4:77faf76e3cd8	3412	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3413	if (ret == 0) {
cparata	4:77faf76e3cd8	3414	reg.sim = (uint8_t)val;
cparata	4:77faf76e3cd8	3415	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3416	}
cparata	4:77faf76e3cd8	3417	return ret;
cparata	0:6d69e896ce38	3418	}
cparata	0:6d69e896ce38	3419
cparata	0:6d69e896ce38	3420	/**
cparata	0:6d69e896ce38	3421	* @brief SPI Serial Interface Mode selection.[get]
cparata	0:6d69e896ce38	3422	*
cparata	0:6d69e896ce38	3423	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3424	* @param val Get the values of sim in reg CTRL3_C
cparata	0:6d69e896ce38	3425	*
cparata	0:6d69e896ce38	3426	*/
cparata	0:6d69e896ce38	3427	int32_t lsm6dso_spi_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sim_t val)
cparata	0:6d69e896ce38	3428	{
cparata	4:77faf76e3cd8	3429	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	3430	int32_t ret;
cparata	4:77faf76e3cd8	3431
cparata	4:77faf76e3cd8	3432	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3433	switch (reg.sim) {
cparata	4:77faf76e3cd8	3434	case LSM6DSO_SPI_4_WIRE:
cparata	4:77faf76e3cd8	3435	*val = LSM6DSO_SPI_4_WIRE;
cparata	4:77faf76e3cd8	3436	break;
cparata	4:77faf76e3cd8	3437	case LSM6DSO_SPI_3_WIRE:
cparata	4:77faf76e3cd8	3438	*val = LSM6DSO_SPI_3_WIRE;
cparata	4:77faf76e3cd8	3439	break;
cparata	4:77faf76e3cd8	3440	default:
cparata	4:77faf76e3cd8	3441	*val = LSM6DSO_SPI_4_WIRE;
cparata	4:77faf76e3cd8	3442	break;
cparata	4:77faf76e3cd8	3443	}
cparata	4:77faf76e3cd8	3444	return ret;
cparata	0:6d69e896ce38	3445	}
cparata	0:6d69e896ce38	3446
cparata	0:6d69e896ce38	3447	/**
cparata	0:6d69e896ce38	3448	* @brief Disable / Enable I2C interface.[set]
cparata	0:6d69e896ce38	3449	*
cparata	0:6d69e896ce38	3450	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3451	* @param val change the values of i2c_disable in
cparata	0:6d69e896ce38	3452	* reg CTRL4_C
cparata	0:6d69e896ce38	3453	*
cparata	0:6d69e896ce38	3454	*/
cparata	0:6d69e896ce38	3455	int32_t lsm6dso_i2c_interface_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3456	lsm6dso_i2c_disable_t val)
cparata	0:6d69e896ce38	3457	{
cparata	4:77faf76e3cd8	3458	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	3459	int32_t ret;
cparata	4:77faf76e3cd8	3460
cparata	4:77faf76e3cd8	3461	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3462	if (ret == 0) {
cparata	4:77faf76e3cd8	3463	reg.i2c_disable = (uint8_t)val;
cparata	4:77faf76e3cd8	3464	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3465	}
cparata	4:77faf76e3cd8	3466	return ret;
cparata	0:6d69e896ce38	3467	}
cparata	0:6d69e896ce38	3468
cparata	0:6d69e896ce38	3469	/**
cparata	0:6d69e896ce38	3470	* @brief Disable / Enable I2C interface.[get]
cparata	0:6d69e896ce38	3471	*
cparata	0:6d69e896ce38	3472	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3473	* @param val Get the values of i2c_disable in
cparata	0:6d69e896ce38	3474	* reg CTRL4_C
cparata	0:6d69e896ce38	3475	*
cparata	0:6d69e896ce38	3476	*/
cparata	0:6d69e896ce38	3477	int32_t lsm6dso_i2c_interface_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3478	lsm6dso_i2c_disable_t *val)
cparata	0:6d69e896ce38	3479	{
cparata	4:77faf76e3cd8	3480	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	3481	int32_t ret;
cparata	4:77faf76e3cd8	3482
cparata	4:77faf76e3cd8	3483	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3484	switch (reg.i2c_disable) {
cparata	4:77faf76e3cd8	3485	case LSM6DSO_I2C_ENABLE:
cparata	4:77faf76e3cd8	3486	*val = LSM6DSO_I2C_ENABLE;
cparata	4:77faf76e3cd8	3487	break;
cparata	4:77faf76e3cd8	3488	case LSM6DSO_I2C_DISABLE:
cparata	4:77faf76e3cd8	3489	*val = LSM6DSO_I2C_DISABLE;
cparata	4:77faf76e3cd8	3490	break;
cparata	4:77faf76e3cd8	3491	default:
cparata	4:77faf76e3cd8	3492	*val = LSM6DSO_I2C_ENABLE;
cparata	4:77faf76e3cd8	3493	break;
cparata	4:77faf76e3cd8	3494	}
cparata	4:77faf76e3cd8	3495	return ret;
cparata	0:6d69e896ce38	3496	}
cparata	0:6d69e896ce38	3497
cparata	0:6d69e896ce38	3498	/**
cparata	0:6d69e896ce38	3499	* @brief I3C Enable/Disable communication protocol[.set]
cparata	0:6d69e896ce38	3500	*
cparata	0:6d69e896ce38	3501	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3502	* @param val change the values of i3c_disable
cparata	0:6d69e896ce38	3503	* in reg CTRL9_XL
cparata	0:6d69e896ce38	3504	*
cparata	0:6d69e896ce38	3505	*/
cparata	0:6d69e896ce38	3506	int32_t lsm6dso_i3c_disable_set(lsm6dso_ctx_t *ctx, lsm6dso_i3c_disable_t val)
cparata	0:6d69e896ce38	3507	{
cparata	4:77faf76e3cd8	3508	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	4:77faf76e3cd8	3509	lsm6dso_ctrl9_xl_t ctrl9_xl;
cparata	4:77faf76e3cd8	3510	int32_t ret;
cparata	4:77faf76e3cd8	3511
cparata	4:77faf76e3cd8	3512	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata	4:77faf76e3cd8	3513	if (ret == 0) {
cparata	4:77faf76e3cd8	3514	ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
cparata	4:77faf76e3cd8	3515	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata	4:77faf76e3cd8	3516	}
cparata	4:77faf76e3cd8	3517	if (ret == 0) {
cparata	4:77faf76e3cd8	3518
cparata	4:77faf76e3cd8	3519	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	4:77faf76e3cd8	3520	(uint8_t*)&i3c_bus_avb, 1);
cparata	4:77faf76e3cd8	3521	}
cparata	4:77faf76e3cd8	3522	if (ret == 0) {
cparata	4:77faf76e3cd8	3523	i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
cparata	4:77faf76e3cd8	3524	ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	4:77faf76e3cd8	3525	(uint8_t*)&i3c_bus_avb, 1);
cparata	4:77faf76e3cd8	3526	}
cparata	4:77faf76e3cd8	3527
cparata	4:77faf76e3cd8	3528	return ret;
cparata	0:6d69e896ce38	3529	}
cparata	0:6d69e896ce38	3530
cparata	0:6d69e896ce38	3531	/**
cparata	0:6d69e896ce38	3532	* @brief I3C Enable/Disable communication protocol.[get]
cparata	0:6d69e896ce38	3533	*
cparata	0:6d69e896ce38	3534	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3535	* @param val change the values of i3c_disable in
cparata	0:6d69e896ce38	3536	* reg CTRL9_XL
cparata	0:6d69e896ce38	3537	*
cparata	0:6d69e896ce38	3538	*/
cparata	0:6d69e896ce38	3539	int32_t lsm6dso_i3c_disable_get(lsm6dso_ctx_t ctx, lsm6dso_i3c_disable_t val)
cparata	0:6d69e896ce38	3540	{
cparata	4:77faf76e3cd8	3541	lsm6dso_ctrl9_xl_t ctrl9_xl;
cparata	4:77faf76e3cd8	3542	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	4:77faf76e3cd8	3543	int32_t ret;
cparata	4:77faf76e3cd8	3544
cparata	4:77faf76e3cd8	3545	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata	4:77faf76e3cd8	3546	if (ret == 0) {
cparata	4:77faf76e3cd8	3547	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	4:77faf76e3cd8	3548	(uint8_t*)&i3c_bus_avb, 1);
cparata	4:77faf76e3cd8	3549
cparata	4:77faf76e3cd8	3550	switch ((ctrl9_xl.i3c_disable << 7) \| i3c_bus_avb.i3c_bus_avb_sel) {
cparata	4:77faf76e3cd8	3551	case LSM6DSO_I3C_DISABLE:
cparata	4:77faf76e3cd8	3552	*val = LSM6DSO_I3C_DISABLE;
cparata	4:77faf76e3cd8	3553	break;
cparata	4:77faf76e3cd8	3554	case LSM6DSO_I3C_ENABLE_T_50us:
cparata	4:77faf76e3cd8	3555	*val = LSM6DSO_I3C_ENABLE_T_50us;
cparata	4:77faf76e3cd8	3556	break;
cparata	4:77faf76e3cd8	3557	case LSM6DSO_I3C_ENABLE_T_2us:
cparata	4:77faf76e3cd8	3558	*val = LSM6DSO_I3C_ENABLE_T_2us;
cparata	4:77faf76e3cd8	3559	break;
cparata	4:77faf76e3cd8	3560	case LSM6DSO_I3C_ENABLE_T_1ms:
cparata	4:77faf76e3cd8	3561	*val = LSM6DSO_I3C_ENABLE_T_1ms;
cparata	4:77faf76e3cd8	3562	break;
cparata	4:77faf76e3cd8	3563	case LSM6DSO_I3C_ENABLE_T_25ms:
cparata	4:77faf76e3cd8	3564	*val = LSM6DSO_I3C_ENABLE_T_25ms;
cparata	4:77faf76e3cd8	3565	break;
cparata	4:77faf76e3cd8	3566	default:
cparata	4:77faf76e3cd8	3567	*val = LSM6DSO_I3C_DISABLE;
cparata	4:77faf76e3cd8	3568	break;
cparata	3:4274d9103f1d	3569	}
cparata	4:77faf76e3cd8	3570	}
cparata	4:77faf76e3cd8	3571	return ret;
cparata	0:6d69e896ce38	3572	}
cparata	0:6d69e896ce38	3573
cparata	0:6d69e896ce38	3574	/**
cparata	0:6d69e896ce38	3575	* @}
cparata	0:6d69e896ce38	3576	*
cparata	0:6d69e896ce38	3577	*/
cparata	0:6d69e896ce38	3578
cparata	0:6d69e896ce38	3579	/**
cparata	0:6d69e896ce38	3580	* @defgroup LSM6DSO_interrupt_pins
cparata	0:6d69e896ce38	3581	* @brief This section groups all the functions that manage interrup pins
cparata	0:6d69e896ce38	3582	* @{
cparata	0:6d69e896ce38	3583	*
cparata	0:6d69e896ce38	3584	*/
cparata	0:6d69e896ce38	3585
cparata	0:6d69e896ce38	3586	/**
cparata	0:6d69e896ce38	3587	* @brief Connect/Disconnect INT1 internal pull-down.[set]
cparata	0:6d69e896ce38	3588	*
cparata	0:6d69e896ce38	3589	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3590	* @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB
cparata	0:6d69e896ce38	3591	*
cparata	0:6d69e896ce38	3592	*/
cparata	0:6d69e896ce38	3593	int32_t lsm6dso_int1_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_int1_pd_en_t val)
cparata	0:6d69e896ce38	3594	{
cparata	4:77faf76e3cd8	3595	lsm6dso_i3c_bus_avb_t reg;
cparata	4:77faf76e3cd8	3596	int32_t ret;
cparata	4:77faf76e3cd8	3597
cparata	4:77faf76e3cd8	3598	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3599	if (ret == 0) {
cparata	4:77faf76e3cd8	3600	reg.pd_dis_int1 = (uint8_t)val;
cparata	4:77faf76e3cd8	3601	ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3602	}
cparata	4:77faf76e3cd8	3603	return ret;
cparata	0:6d69e896ce38	3604	}
cparata	0:6d69e896ce38	3605
cparata	0:6d69e896ce38	3606	/**
cparata	0:6d69e896ce38	3607	* @brief Connect/Disconnect INT1 internal pull-down.[get]
cparata	0:6d69e896ce38	3608	*
cparata	0:6d69e896ce38	3609	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3610	* @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
cparata	0:6d69e896ce38	3611	*
cparata	0:6d69e896ce38	3612	*/
cparata	0:6d69e896ce38	3613	int32_t lsm6dso_int1_mode_get(lsm6dso_ctx_t ctx, lsm6dso_int1_pd_en_t val)
cparata	0:6d69e896ce38	3614	{
cparata	4:77faf76e3cd8	3615	lsm6dso_i3c_bus_avb_t reg;
cparata	4:77faf76e3cd8	3616	int32_t ret;
cparata	4:77faf76e3cd8	3617
cparata	4:77faf76e3cd8	3618	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3619	switch (reg.pd_dis_int1) {
cparata	4:77faf76e3cd8	3620	case LSM6DSO_PULL_DOWN_DISC:
cparata	4:77faf76e3cd8	3621	*val = LSM6DSO_PULL_DOWN_DISC;
cparata	4:77faf76e3cd8	3622	break;
cparata	4:77faf76e3cd8	3623	case LSM6DSO_PULL_DOWN_CONNECT:
cparata	4:77faf76e3cd8	3624	*val = LSM6DSO_PULL_DOWN_CONNECT;
cparata	4:77faf76e3cd8	3625	break;
cparata	4:77faf76e3cd8	3626	default:
cparata	4:77faf76e3cd8	3627	*val = LSM6DSO_PULL_DOWN_DISC;
cparata	4:77faf76e3cd8	3628	break;
cparata	4:77faf76e3cd8	3629	}
cparata	4:77faf76e3cd8	3630	return ret;
cparata	0:6d69e896ce38	3631	}
cparata	0:6d69e896ce38	3632
cparata	0:6d69e896ce38	3633	/**
cparata	0:6d69e896ce38	3634	* @brief Push-pull/open drain selection on interrupt pads.[set]
cparata	0:6d69e896ce38	3635	*
cparata	0:6d69e896ce38	3636	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3637	* @param val change the values of pp_od in reg CTRL3_C
cparata	0:6d69e896ce38	3638	*
cparata	0:6d69e896ce38	3639	*/
cparata	0:6d69e896ce38	3640	int32_t lsm6dso_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_pp_od_t val)
cparata	0:6d69e896ce38	3641	{
cparata	4:77faf76e3cd8	3642	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	3643	int32_t ret;
cparata	4:77faf76e3cd8	3644
cparata	4:77faf76e3cd8	3645	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3646	if (ret == 0) {
cparata	4:77faf76e3cd8	3647	reg.pp_od = (uint8_t)val;
cparata	4:77faf76e3cd8	3648	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3649	}
cparata	4:77faf76e3cd8	3650	return ret;
cparata	0:6d69e896ce38	3651	}
cparata	0:6d69e896ce38	3652
cparata	0:6d69e896ce38	3653	/**
cparata	0:6d69e896ce38	3654	* @brief Push-pull/open drain selection on interrupt pads.[get]
cparata	0:6d69e896ce38	3655	*
cparata	0:6d69e896ce38	3656	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3657	* @param val Get the values of pp_od in reg CTRL3_C
cparata	0:6d69e896ce38	3658	*
cparata	0:6d69e896ce38	3659	*/
cparata	0:6d69e896ce38	3660	int32_t lsm6dso_pin_mode_get(lsm6dso_ctx_t ctx, lsm6dso_pp_od_t val)
cparata	0:6d69e896ce38	3661	{
cparata	4:77faf76e3cd8	3662	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	3663	int32_t ret;
cparata	4:77faf76e3cd8	3664
cparata	4:77faf76e3cd8	3665	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3666
cparata	4:77faf76e3cd8	3667	switch (reg.pp_od) {
cparata	4:77faf76e3cd8	3668	case LSM6DSO_PUSH_PULL:
cparata	4:77faf76e3cd8	3669	*val = LSM6DSO_PUSH_PULL;
cparata	4:77faf76e3cd8	3670	break;
cparata	4:77faf76e3cd8	3671	case LSM6DSO_OPEN_DRAIN:
cparata	4:77faf76e3cd8	3672	*val = LSM6DSO_OPEN_DRAIN;
cparata	4:77faf76e3cd8	3673	break;
cparata	4:77faf76e3cd8	3674	default:
cparata	4:77faf76e3cd8	3675	*val = LSM6DSO_PUSH_PULL;
cparata	4:77faf76e3cd8	3676	break;
cparata	4:77faf76e3cd8	3677	}
cparata	4:77faf76e3cd8	3678	return ret;
cparata	0:6d69e896ce38	3679	}
cparata	0:6d69e896ce38	3680
cparata	0:6d69e896ce38	3681	/**
cparata	0:6d69e896ce38	3682	* @brief Interrupt active-high/low.[set]
cparata	0:6d69e896ce38	3683	*
cparata	0:6d69e896ce38	3684	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3685	* @param val change the values of h_lactive in reg CTRL3_C
cparata	0:6d69e896ce38	3686	*
cparata	0:6d69e896ce38	3687	*/
cparata	0:6d69e896ce38	3688	int32_t lsm6dso_pin_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_h_lactive_t val)
cparata	0:6d69e896ce38	3689	{
cparata	4:77faf76e3cd8	3690	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	3691	int32_t ret;
cparata	4:77faf76e3cd8	3692
cparata	4:77faf76e3cd8	3693	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3694	if (ret == 0) {
cparata	4:77faf76e3cd8	3695	reg.h_lactive = (uint8_t)val;
cparata	4:77faf76e3cd8	3696	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3697	}
cparata	4:77faf76e3cd8	3698
cparata	4:77faf76e3cd8	3699	return ret;
cparata	0:6d69e896ce38	3700	}
cparata	0:6d69e896ce38	3701
cparata	0:6d69e896ce38	3702	/**
cparata	0:6d69e896ce38	3703	* @brief Interrupt active-high/low.[get]
cparata	0:6d69e896ce38	3704	*
cparata	0:6d69e896ce38	3705	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3706	* @param val Get the values of h_lactive in reg CTRL3_C
cparata	0:6d69e896ce38	3707	*
cparata	0:6d69e896ce38	3708	*/
cparata	0:6d69e896ce38	3709	int32_t lsm6dso_pin_polarity_get(lsm6dso_ctx_t ctx, lsm6dso_h_lactive_t val)
cparata	0:6d69e896ce38	3710	{
cparata	4:77faf76e3cd8	3711	lsm6dso_ctrl3_c_t reg;
cparata	4:77faf76e3cd8	3712	int32_t ret;
cparata	4:77faf76e3cd8	3713
cparata	4:77faf76e3cd8	3714	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3715
cparata	4:77faf76e3cd8	3716	switch (reg.h_lactive) {
cparata	4:77faf76e3cd8	3717	case LSM6DSO_ACTIVE_HIGH:
cparata	4:77faf76e3cd8	3718	*val = LSM6DSO_ACTIVE_HIGH;
cparata	4:77faf76e3cd8	3719	break;
cparata	4:77faf76e3cd8	3720	case LSM6DSO_ACTIVE_LOW:
cparata	4:77faf76e3cd8	3721	*val = LSM6DSO_ACTIVE_LOW;
cparata	4:77faf76e3cd8	3722	break;
cparata	4:77faf76e3cd8	3723	default:
cparata	4:77faf76e3cd8	3724	*val = LSM6DSO_ACTIVE_HIGH;
cparata	4:77faf76e3cd8	3725	break;
cparata	4:77faf76e3cd8	3726	}
cparata	4:77faf76e3cd8	3727	return ret;
cparata	0:6d69e896ce38	3728	}
cparata	0:6d69e896ce38	3729
cparata	0:6d69e896ce38	3730	/**
cparata	0:6d69e896ce38	3731	* @brief All interrupt signals become available on INT1 pin.[set]
cparata	0:6d69e896ce38	3732	*
cparata	0:6d69e896ce38	3733	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3734	* @param val change the values of int2_on_int1 in reg CTRL4_C
cparata	0:6d69e896ce38	3735	*
cparata	0:6d69e896ce38	3736	*/
cparata	0:6d69e896ce38	3737	int32_t lsm6dso_all_on_int1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	3738	{
cparata	4:77faf76e3cd8	3739	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	3740	int32_t ret;
cparata	4:77faf76e3cd8	3741
cparata	4:77faf76e3cd8	3742	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3743	if (ret == 0) {
cparata	4:77faf76e3cd8	3744	reg.int2_on_int1 = val;
cparata	4:77faf76e3cd8	3745	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3746	}
cparata	4:77faf76e3cd8	3747
cparata	4:77faf76e3cd8	3748	return ret;
cparata	0:6d69e896ce38	3749	}
cparata	0:6d69e896ce38	3750
cparata	0:6d69e896ce38	3751	/**
cparata	0:6d69e896ce38	3752	* @brief All interrupt signals become available on INT1 pin.[get]
cparata	0:6d69e896ce38	3753	*
cparata	0:6d69e896ce38	3754	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3755	* @param val change the values of int2_on_int1 in reg CTRL4_C
cparata	0:6d69e896ce38	3756	*
cparata	0:6d69e896ce38	3757	*/
cparata	0:6d69e896ce38	3758	int32_t lsm6dso_all_on_int1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	3759	{
cparata	4:77faf76e3cd8	3760	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	3761	int32_t ret;
cparata	4:77faf76e3cd8	3762
cparata	4:77faf76e3cd8	3763	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3764	*val = reg.int2_on_int1;
cparata	4:77faf76e3cd8	3765
cparata	4:77faf76e3cd8	3766	return ret;
cparata	0:6d69e896ce38	3767	}
cparata	0:6d69e896ce38	3768
cparata	0:6d69e896ce38	3769	/**
cparata	0:6d69e896ce38	3770	* @brief Interrupt notification mode.[set]
cparata	0:6d69e896ce38	3771	*
cparata	0:6d69e896ce38	3772	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3773	* @param val change the values of lir in reg TAP_CFG0
cparata	0:6d69e896ce38	3774	*
cparata	0:6d69e896ce38	3775	*/
cparata	0:6d69e896ce38	3776	int32_t lsm6dso_int_notification_set(lsm6dso_ctx_t *ctx, lsm6dso_lir_t val)
cparata	0:6d69e896ce38	3777	{
cparata	4:77faf76e3cd8	3778	lsm6dso_tap_cfg0_t tap_cfg0;
cparata	4:77faf76e3cd8	3779	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	3780	int32_t ret;
cparata	4:77faf76e3cd8	3781
cparata	4:77faf76e3cd8	3782	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	4:77faf76e3cd8	3783	if (ret == 0) {
cparata	4:77faf76e3cd8	3784	tap_cfg0.lir = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	3785	tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
cparata	4:77faf76e3cd8	3786	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	4:77faf76e3cd8	3787	}
cparata	4:77faf76e3cd8	3788	if (ret == 0) {
cparata	4:77faf76e3cd8	3789
cparata	4:77faf76e3cd8	3790	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	3791	}
cparata	4:77faf76e3cd8	3792	if (ret == 0) {
cparata	4:77faf76e3cd8	3793	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	3794	}
cparata	4:77faf76e3cd8	3795	if (ret == 0) {
cparata	4:77faf76e3cd8	3796	page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
cparata	4:77faf76e3cd8	3797	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	3798	}
cparata	4:77faf76e3cd8	3799	if (ret == 0) {
cparata	4:77faf76e3cd8	3800	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	3801	}
cparata	4:77faf76e3cd8	3802
cparata	4:77faf76e3cd8	3803	return ret;
cparata	0:6d69e896ce38	3804	}
cparata	0:6d69e896ce38	3805
cparata	0:6d69e896ce38	3806	/**
cparata	0:6d69e896ce38	3807	* @brief Interrupt notification mode.[get]
cparata	0:6d69e896ce38	3808	*
cparata	0:6d69e896ce38	3809	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3810	* @param val Get the values of lir in reg TAP_CFG0
cparata	0:6d69e896ce38	3811	*
cparata	0:6d69e896ce38	3812	*/
cparata	0:6d69e896ce38	3813	int32_t lsm6dso_int_notification_get(lsm6dso_ctx_t ctx, lsm6dso_lir_t val)
cparata	0:6d69e896ce38	3814	{
cparata	4:77faf76e3cd8	3815	lsm6dso_tap_cfg0_t tap_cfg0;
cparata	4:77faf76e3cd8	3816	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	3817	int32_t ret;
cparata	4:77faf76e3cd8	3818
cparata	4:77faf76e3cd8	3819
cparata	4:77faf76e3cd8	3820	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	4:77faf76e3cd8	3821	if (ret == 0) {
cparata	4:77faf76e3cd8	3822
cparata	4:77faf76e3cd8	3823	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	3824	}
cparata	4:77faf76e3cd8	3825	if (ret == 0) {
cparata	4:77faf76e3cd8	3826	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	3827	}
cparata	4:77faf76e3cd8	3828	if (ret == 0) {
cparata	4:77faf76e3cd8	3829	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	3830	}
cparata	4:77faf76e3cd8	3831	if (ret == 0) {
cparata	4:77faf76e3cd8	3832	switch ((page_rw.emb_func_lir << 1) \| tap_cfg0.lir) {
cparata	4:77faf76e3cd8	3833	case LSM6DSO_ALL_INT_PULSED:
cparata	4:77faf76e3cd8	3834	*val = LSM6DSO_ALL_INT_PULSED;
cparata	4:77faf76e3cd8	3835	break;
cparata	4:77faf76e3cd8	3836	case LSM6DSO_BASE_LATCHED_EMB_PULSED:
cparata	4:77faf76e3cd8	3837	*val = LSM6DSO_BASE_LATCHED_EMB_PULSED;
cparata	4:77faf76e3cd8	3838	break;
cparata	4:77faf76e3cd8	3839	case LSM6DSO_BASE_PULSED_EMB_LATCHED:
cparata	4:77faf76e3cd8	3840	*val = LSM6DSO_BASE_PULSED_EMB_LATCHED;
cparata	4:77faf76e3cd8	3841	break;
cparata	4:77faf76e3cd8	3842	case LSM6DSO_ALL_INT_LATCHED:
cparata	4:77faf76e3cd8	3843	*val = LSM6DSO_ALL_INT_LATCHED;
cparata	4:77faf76e3cd8	3844	break;
cparata	4:77faf76e3cd8	3845	default:
cparata	4:77faf76e3cd8	3846	*val = LSM6DSO_ALL_INT_PULSED;
cparata	4:77faf76e3cd8	3847	break;
cparata	3:4274d9103f1d	3848	}
cparata	4:77faf76e3cd8	3849	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	3850	}
cparata	4:77faf76e3cd8	3851	if (ret == 0) {
cparata	4:77faf76e3cd8	3852	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	3853	}
cparata	4:77faf76e3cd8	3854	if (ret == 0) {
cparata	4:77faf76e3cd8	3855	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	3856	}
cparata	4:77faf76e3cd8	3857
cparata	4:77faf76e3cd8	3858	return ret;
cparata	0:6d69e896ce38	3859	}
cparata	0:6d69e896ce38	3860
cparata	0:6d69e896ce38	3861	/**
cparata	0:6d69e896ce38	3862	* @}
cparata	0:6d69e896ce38	3863	*
cparata	0:6d69e896ce38	3864	*/
cparata	0:6d69e896ce38	3865
cparata	0:6d69e896ce38	3866	/**
cparata	0:6d69e896ce38	3867	* @defgroup LSM6DSO_Wake_Up_event
cparata	0:6d69e896ce38	3868	* @brief This section groups all the functions that manage the Wake Up
cparata	0:6d69e896ce38	3869	* event generation.
cparata	0:6d69e896ce38	3870	* @{
cparata	0:6d69e896ce38	3871	*
cparata	0:6d69e896ce38	3872	*/
cparata	0:6d69e896ce38	3873
cparata	0:6d69e896ce38	3874	/**
cparata	0:6d69e896ce38	3875	* @brief Weight of 1 LSB of wakeup threshold.[set]
cparata	0:6d69e896ce38	3876	* 0: 1 LSB =FS_XL / 64
cparata	0:6d69e896ce38	3877	* 1: 1 LSB = FS_XL / 256
cparata	0:6d69e896ce38	3878	*
cparata	0:6d69e896ce38	3879	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3880	* @param val change the values of wake_ths_w in
cparata	0:6d69e896ce38	3881	* reg WAKE_UP_DUR
cparata	0:6d69e896ce38	3882	*
cparata	0:6d69e896ce38	3883	*/
cparata	0:6d69e896ce38	3884	int32_t lsm6dso_wkup_ths_weight_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3885	lsm6dso_wake_ths_w_t val)
cparata	0:6d69e896ce38	3886	{
cparata	4:77faf76e3cd8	3887	lsm6dso_wake_up_dur_t reg;
cparata	4:77faf76e3cd8	3888	int32_t ret;
cparata	4:77faf76e3cd8	3889
cparata	4:77faf76e3cd8	3890	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3891	if (ret == 0) {
cparata	4:77faf76e3cd8	3892	reg.wake_ths_w = (uint8_t)val;
cparata	4:77faf76e3cd8	3893	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3894	}
cparata	4:77faf76e3cd8	3895	return ret;
cparata	0:6d69e896ce38	3896	}
cparata	0:6d69e896ce38	3897
cparata	0:6d69e896ce38	3898	/**
cparata	0:6d69e896ce38	3899	* @brief Weight of 1 LSB of wakeup threshold.[get]
cparata	0:6d69e896ce38	3900	* 0: 1 LSB =FS_XL / 64
cparata	0:6d69e896ce38	3901	* 1: 1 LSB = FS_XL / 256
cparata	0:6d69e896ce38	3902	*
cparata	0:6d69e896ce38	3903	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3904	* @param val Get the values of wake_ths_w in
cparata	0:6d69e896ce38	3905	* reg WAKE_UP_DUR
cparata	0:6d69e896ce38	3906	*
cparata	0:6d69e896ce38	3907	*/
cparata	0:6d69e896ce38	3908	int32_t lsm6dso_wkup_ths_weight_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3909	lsm6dso_wake_ths_w_t *val)
cparata	0:6d69e896ce38	3910	{
cparata	4:77faf76e3cd8	3911	lsm6dso_wake_up_dur_t reg;
cparata	4:77faf76e3cd8	3912	int32_t ret;
cparata	4:77faf76e3cd8	3913
cparata	4:77faf76e3cd8	3914	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3915
cparata	4:77faf76e3cd8	3916	switch (reg.wake_ths_w) {
cparata	4:77faf76e3cd8	3917	case LSM6DSO_LSb_FS_DIV_64:
cparata	4:77faf76e3cd8	3918	*val = LSM6DSO_LSb_FS_DIV_64;
cparata	4:77faf76e3cd8	3919	break;
cparata	4:77faf76e3cd8	3920	case LSM6DSO_LSb_FS_DIV_256:
cparata	4:77faf76e3cd8	3921	*val = LSM6DSO_LSb_FS_DIV_256;
cparata	4:77faf76e3cd8	3922	break;
cparata	4:77faf76e3cd8	3923	default:
cparata	4:77faf76e3cd8	3924	*val = LSM6DSO_LSb_FS_DIV_64;
cparata	4:77faf76e3cd8	3925	break;
cparata	4:77faf76e3cd8	3926	}
cparata	4:77faf76e3cd8	3927	return ret;
cparata	0:6d69e896ce38	3928	}
cparata	0:6d69e896ce38	3929
cparata	0:6d69e896ce38	3930	/**
cparata	0:6d69e896ce38	3931	* @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata	0:6d69e896ce38	3932	* WAKE_UP_DUR.[set]
cparata	0:6d69e896ce38	3933	*
cparata	0:6d69e896ce38	3934	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3935	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:6d69e896ce38	3936	*
cparata	0:6d69e896ce38	3937	*/
cparata	0:6d69e896ce38	3938	int32_t lsm6dso_wkup_threshold_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	3939	{
cparata	4:77faf76e3cd8	3940	lsm6dso_wake_up_ths_t reg;
cparata	4:77faf76e3cd8	3941	int32_t ret;
cparata	4:77faf76e3cd8	3942
cparata	4:77faf76e3cd8	3943	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3944	if (ret == 0) {
cparata	4:77faf76e3cd8	3945	reg.wk_ths = val;
cparata	4:77faf76e3cd8	3946	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3947	}
cparata	4:77faf76e3cd8	3948	return ret;
cparata	0:6d69e896ce38	3949	}
cparata	0:6d69e896ce38	3950
cparata	0:6d69e896ce38	3951	/**
cparata	0:6d69e896ce38	3952	* @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata	0:6d69e896ce38	3953	* WAKE_UP_DUR.[get]
cparata	0:6d69e896ce38	3954	*
cparata	0:6d69e896ce38	3955	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3956	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:6d69e896ce38	3957	*
cparata	0:6d69e896ce38	3958	*/
cparata	0:6d69e896ce38	3959	int32_t lsm6dso_wkup_threshold_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	3960	{
cparata	4:77faf76e3cd8	3961	lsm6dso_wake_up_ths_t reg;
cparata	4:77faf76e3cd8	3962	int32_t ret;
cparata	4:77faf76e3cd8	3963
cparata	4:77faf76e3cd8	3964	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3965	*val = reg.wk_ths;
cparata	4:77faf76e3cd8	3966
cparata	4:77faf76e3cd8	3967	return ret;
cparata	0:6d69e896ce38	3968	}
cparata	0:6d69e896ce38	3969
cparata	0:6d69e896ce38	3970	/**
cparata	0:6d69e896ce38	3971	* @brief Wake up duration event.[set]
cparata	0:6d69e896ce38	3972	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	3973	*
cparata	0:6d69e896ce38	3974	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3975	* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata	0:6d69e896ce38	3976	*
cparata	0:6d69e896ce38	3977	*/
cparata	0:6d69e896ce38	3978	int32_t lsm6dso_xl_usr_offset_on_wkup_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	3979	{
cparata	4:77faf76e3cd8	3980	lsm6dso_wake_up_ths_t reg;
cparata	4:77faf76e3cd8	3981	int32_t ret;
cparata	4:77faf76e3cd8	3982
cparata	4:77faf76e3cd8	3983	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3984	if (ret == 0) {
cparata	4:77faf76e3cd8	3985	reg.usr_off_on_wu = val;
cparata	4:77faf76e3cd8	3986	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	3987	}
cparata	4:77faf76e3cd8	3988	return ret;
cparata	0:6d69e896ce38	3989	}
cparata	0:6d69e896ce38	3990
cparata	0:6d69e896ce38	3991	/**
cparata	0:6d69e896ce38	3992	* @brief Wake up duration event.[get]
cparata	0:6d69e896ce38	3993	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	3994	*
cparata	0:6d69e896ce38	3995	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3996	* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata	0:6d69e896ce38	3997	*
cparata	0:6d69e896ce38	3998	*/
cparata	0:6d69e896ce38	3999	int32_t lsm6dso_xl_usr_offset_on_wkup_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4000	{
cparata	4:77faf76e3cd8	4001	lsm6dso_wake_up_ths_t reg;
cparata	4:77faf76e3cd8	4002	int32_t ret;
cparata	4:77faf76e3cd8	4003
cparata	4:77faf76e3cd8	4004	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4005	*val = reg.usr_off_on_wu;
cparata	4:77faf76e3cd8	4006
cparata	4:77faf76e3cd8	4007	return ret;
cparata	0:6d69e896ce38	4008	}
cparata	0:6d69e896ce38	4009
cparata	0:6d69e896ce38	4010	/**
cparata	0:6d69e896ce38	4011	* @brief Wake up duration event.[set]
cparata	0:6d69e896ce38	4012	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4013	*
cparata	0:6d69e896ce38	4014	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4015	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4016	*
cparata	0:6d69e896ce38	4017	*/
cparata	0:6d69e896ce38	4018	int32_t lsm6dso_wkup_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4019	{
cparata	4:77faf76e3cd8	4020	lsm6dso_wake_up_dur_t reg;
cparata	4:77faf76e3cd8	4021	int32_t ret;
cparata	4:77faf76e3cd8	4022
cparata	4:77faf76e3cd8	4023	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4024	if (ret == 0) {
cparata	4:77faf76e3cd8	4025	reg.wake_dur = val;
cparata	4:77faf76e3cd8	4026	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4027	}
cparata	4:77faf76e3cd8	4028	return ret;
cparata	0:6d69e896ce38	4029	}
cparata	0:6d69e896ce38	4030
cparata	0:6d69e896ce38	4031	/**
cparata	0:6d69e896ce38	4032	* @brief Wake up duration event.[get]
cparata	0:6d69e896ce38	4033	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4034	*
cparata	0:6d69e896ce38	4035	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4036	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4037	*
cparata	0:6d69e896ce38	4038	*/
cparata	0:6d69e896ce38	4039	int32_t lsm6dso_wkup_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4040	{
cparata	4:77faf76e3cd8	4041	lsm6dso_wake_up_dur_t reg;
cparata	4:77faf76e3cd8	4042	int32_t ret;
cparata	4:77faf76e3cd8	4043
cparata	4:77faf76e3cd8	4044	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4045	*val = reg.wake_dur;
cparata	4:77faf76e3cd8	4046
cparata	4:77faf76e3cd8	4047	return ret;
cparata	0:6d69e896ce38	4048	}
cparata	0:6d69e896ce38	4049
cparata	0:6d69e896ce38	4050	/**
cparata	0:6d69e896ce38	4051	* @}
cparata	0:6d69e896ce38	4052	*
cparata	0:6d69e896ce38	4053	*/
cparata	0:6d69e896ce38	4054
cparata	0:6d69e896ce38	4055	/**
cparata	0:6d69e896ce38	4056	* @defgroup LSM6DSO_ Activity/Inactivity_detection
cparata	0:6d69e896ce38	4057	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	4058	* activity/inactivity detection.
cparata	0:6d69e896ce38	4059	* @{
cparata	0:6d69e896ce38	4060	*
cparata	0:6d69e896ce38	4061	*/
cparata	0:6d69e896ce38	4062
cparata	0:6d69e896ce38	4063	/**
cparata	0:6d69e896ce38	4064	* @brief Enables gyroscope Sleep mode.[set]
cparata	0:6d69e896ce38	4065	*
cparata	0:6d69e896ce38	4066	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4067	* @param val change the values of sleep_g in reg CTRL4_C
cparata	0:6d69e896ce38	4068	*
cparata	0:6d69e896ce38	4069	*/
cparata	0:6d69e896ce38	4070	int32_t lsm6dso_gy_sleep_mode_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4071	{
cparata	4:77faf76e3cd8	4072	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	4073	int32_t ret;
cparata	4:77faf76e3cd8	4074
cparata	4:77faf76e3cd8	4075	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4076	if (ret == 0) {
cparata	4:77faf76e3cd8	4077	reg.sleep_g = val;
cparata	4:77faf76e3cd8	4078	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4079	}
cparata	4:77faf76e3cd8	4080	return ret;
cparata	0:6d69e896ce38	4081	}
cparata	0:6d69e896ce38	4082
cparata	0:6d69e896ce38	4083	/**
cparata	0:6d69e896ce38	4084	* @brief Enables gyroscope Sleep mode.[get]
cparata	0:6d69e896ce38	4085	*
cparata	0:6d69e896ce38	4086	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4087	* @param val change the values of sleep_g in reg CTRL4_C
cparata	0:6d69e896ce38	4088	*
cparata	0:6d69e896ce38	4089	*/
cparata	0:6d69e896ce38	4090	int32_t lsm6dso_gy_sleep_mode_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4091	{
cparata	4:77faf76e3cd8	4092	lsm6dso_ctrl4_c_t reg;
cparata	4:77faf76e3cd8	4093	int32_t ret;
cparata	4:77faf76e3cd8	4094
cparata	4:77faf76e3cd8	4095	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4096	*val = reg.sleep_g;
cparata	4:77faf76e3cd8	4097
cparata	4:77faf76e3cd8	4098	return ret;
cparata	0:6d69e896ce38	4099	}
cparata	0:6d69e896ce38	4100
cparata	0:6d69e896ce38	4101	/**
cparata	0:6d69e896ce38	4102	* @brief Drives the sleep status instead of
cparata	0:6d69e896ce38	4103	* sleep change on INT pins
cparata	0:6d69e896ce38	4104	* (only if INT1_SLEEP_CHANGE or
cparata	0:6d69e896ce38	4105	* INT2_SLEEP_CHANGE bits are enabled).[set]
cparata	0:6d69e896ce38	4106	*
cparata	0:6d69e896ce38	4107	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4108	* @param val change the values of sleep_status_on_int in reg TAP_CFG0
cparata	0:6d69e896ce38	4109	*
cparata	0:6d69e896ce38	4110	*/
cparata	0:6d69e896ce38	4111	int32_t lsm6dso_act_pin_notification_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4112	lsm6dso_sleep_status_on_int_t val)
cparata	0:6d69e896ce38	4113	{
cparata	4:77faf76e3cd8	4114	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	4115	int32_t ret;
cparata	4:77faf76e3cd8	4116
cparata	4:77faf76e3cd8	4117	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4118	if (ret == 0) {
cparata	4:77faf76e3cd8	4119	reg.sleep_status_on_int = (uint8_t)val;
cparata	4:77faf76e3cd8	4120	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4121	}
cparata	4:77faf76e3cd8	4122	return ret;
cparata	0:6d69e896ce38	4123	}
cparata	0:6d69e896ce38	4124
cparata	0:6d69e896ce38	4125	/**
cparata	0:6d69e896ce38	4126	* @brief Drives the sleep status instead of
cparata	0:6d69e896ce38	4127	* sleep change on INT pins (only if
cparata	0:6d69e896ce38	4128	* INT1_SLEEP_CHANGE or
cparata	0:6d69e896ce38	4129	* INT2_SLEEP_CHANGE bits are enabled).[get]
cparata	0:6d69e896ce38	4130	*
cparata	0:6d69e896ce38	4131	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4132	* @param val Get the values of sleep_status_on_int in reg TAP_CFG0
cparata	0:6d69e896ce38	4133	*
cparata	0:6d69e896ce38	4134	*/
cparata	0:6d69e896ce38	4135	int32_t lsm6dso_act_pin_notification_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4136	lsm6dso_sleep_status_on_int_t *val)
cparata	0:6d69e896ce38	4137	{
cparata	4:77faf76e3cd8	4138	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	4139	int32_t ret;
cparata	4:77faf76e3cd8	4140
cparata	4:77faf76e3cd8	4141	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4142	switch (reg.sleep_status_on_int) {
cparata	4:77faf76e3cd8	4143	case LSM6DSO_DRIVE_SLEEP_CHG_EVENT:
cparata	4:77faf76e3cd8	4144	*val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
cparata	4:77faf76e3cd8	4145	break;
cparata	4:77faf76e3cd8	4146	case LSM6DSO_DRIVE_SLEEP_STATUS:
cparata	4:77faf76e3cd8	4147	*val = LSM6DSO_DRIVE_SLEEP_STATUS;
cparata	4:77faf76e3cd8	4148	break;
cparata	4:77faf76e3cd8	4149	default:
cparata	4:77faf76e3cd8	4150	*val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
cparata	4:77faf76e3cd8	4151	break;
cparata	4:77faf76e3cd8	4152	}
cparata	4:77faf76e3cd8	4153	return ret;
cparata	0:6d69e896ce38	4154	}
cparata	0:6d69e896ce38	4155
cparata	0:6d69e896ce38	4156	/**
cparata	0:6d69e896ce38	4157	* @brief Enable inactivity function.[set]
cparata	0:6d69e896ce38	4158	*
cparata	0:6d69e896ce38	4159	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4160	* @param val change the values of inact_en in reg TAP_CFG2
cparata	0:6d69e896ce38	4161	*
cparata	0:6d69e896ce38	4162	*/
cparata	0:6d69e896ce38	4163	int32_t lsm6dso_act_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_inact_en_t val)
cparata	0:6d69e896ce38	4164	{
cparata	4:77faf76e3cd8	4165	lsm6dso_tap_cfg2_t reg;
cparata	4:77faf76e3cd8	4166	int32_t ret;
cparata	4:77faf76e3cd8	4167
cparata	4:77faf76e3cd8	4168	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4169	if (ret == 0) {
cparata	4:77faf76e3cd8	4170	reg.inact_en = (uint8_t)val;
cparata	4:77faf76e3cd8	4171	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4172	}
cparata	4:77faf76e3cd8	4173	return ret;
cparata	0:6d69e896ce38	4174	}
cparata	0:6d69e896ce38	4175
cparata	0:6d69e896ce38	4176	/**
cparata	0:6d69e896ce38	4177	* @brief Enable inactivity function.[get]
cparata	0:6d69e896ce38	4178	*
cparata	0:6d69e896ce38	4179	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4180	* @param val Get the values of inact_en in reg TAP_CFG2
cparata	0:6d69e896ce38	4181	*
cparata	0:6d69e896ce38	4182	*/
cparata	0:6d69e896ce38	4183	int32_t lsm6dso_act_mode_get(lsm6dso_ctx_t ctx, lsm6dso_inact_en_t val)
cparata	0:6d69e896ce38	4184	{
cparata	4:77faf76e3cd8	4185	lsm6dso_tap_cfg2_t reg;
cparata	4:77faf76e3cd8	4186	int32_t ret;
cparata	4:77faf76e3cd8	4187
cparata	4:77faf76e3cd8	4188	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4189	switch (reg.inact_en) {
cparata	4:77faf76e3cd8	4190	case LSM6DSO_XL_AND_GY_NOT_AFFECTED:
cparata	4:77faf76e3cd8	4191	*val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
cparata	4:77faf76e3cd8	4192	break;
cparata	4:77faf76e3cd8	4193	case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED:
cparata	4:77faf76e3cd8	4194	*val = LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED;
cparata	4:77faf76e3cd8	4195	break;
cparata	4:77faf76e3cd8	4196	case LSM6DSO_XL_12Hz5_GY_SLEEP:
cparata	4:77faf76e3cd8	4197	*val = LSM6DSO_XL_12Hz5_GY_SLEEP;
cparata	4:77faf76e3cd8	4198	break;
cparata	4:77faf76e3cd8	4199	case LSM6DSO_XL_12Hz5_GY_PD:
cparata	4:77faf76e3cd8	4200	*val = LSM6DSO_XL_12Hz5_GY_PD;
cparata	4:77faf76e3cd8	4201	break;
cparata	4:77faf76e3cd8	4202	default:
cparata	4:77faf76e3cd8	4203	*val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
cparata	4:77faf76e3cd8	4204	break;
cparata	4:77faf76e3cd8	4205	}
cparata	4:77faf76e3cd8	4206	return ret;
cparata	0:6d69e896ce38	4207	}
cparata	0:6d69e896ce38	4208
cparata	0:6d69e896ce38	4209	/**
cparata	0:6d69e896ce38	4210	* @brief Duration to go in sleep mode.[set]
cparata	0:6d69e896ce38	4211	* 1 LSb = 512 / ODR
cparata	0:6d69e896ce38	4212	*
cparata	0:6d69e896ce38	4213	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4214	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4215	*
cparata	0:6d69e896ce38	4216	*/
cparata	0:6d69e896ce38	4217	int32_t lsm6dso_act_sleep_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4218	{
cparata	4:77faf76e3cd8	4219	lsm6dso_wake_up_dur_t reg;
cparata	4:77faf76e3cd8	4220	int32_t ret;
cparata	4:77faf76e3cd8	4221
cparata	4:77faf76e3cd8	4222	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4223	if (ret == 0) {
cparata	4:77faf76e3cd8	4224	reg.sleep_dur = val;
cparata	4:77faf76e3cd8	4225	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4226	}
cparata	4:77faf76e3cd8	4227	return ret;
cparata	0:6d69e896ce38	4228	}
cparata	0:6d69e896ce38	4229
cparata	0:6d69e896ce38	4230	/**
cparata	0:6d69e896ce38	4231	* @brief Duration to go in sleep mode.[get]
cparata	0:6d69e896ce38	4232	* 1 LSb = 512 / ODR
cparata	0:6d69e896ce38	4233	*
cparata	0:6d69e896ce38	4234	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4235	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4236	*
cparata	0:6d69e896ce38	4237	*/
cparata	0:6d69e896ce38	4238	int32_t lsm6dso_act_sleep_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4239	{
cparata	4:77faf76e3cd8	4240	lsm6dso_wake_up_dur_t reg;
cparata	4:77faf76e3cd8	4241	int32_t ret;
cparata	4:77faf76e3cd8	4242
cparata	4:77faf76e3cd8	4243	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4244	*val = reg.sleep_dur;
cparata	4:77faf76e3cd8	4245
cparata	4:77faf76e3cd8	4246	return ret;
cparata	0:6d69e896ce38	4247	}
cparata	0:6d69e896ce38	4248
cparata	0:6d69e896ce38	4249	/**
cparata	0:6d69e896ce38	4250	* @}
cparata	0:6d69e896ce38	4251	*
cparata	0:6d69e896ce38	4252	*/
cparata	0:6d69e896ce38	4253
cparata	0:6d69e896ce38	4254	/**
cparata	0:6d69e896ce38	4255	* @defgroup LSM6DSO_tap_generator
cparata	0:6d69e896ce38	4256	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	4257	* tap and double tap event generation.
cparata	0:6d69e896ce38	4258	* @{
cparata	0:6d69e896ce38	4259	*
cparata	0:6d69e896ce38	4260	*/
cparata	0:6d69e896ce38	4261
cparata	0:6d69e896ce38	4262	/**
cparata	0:6d69e896ce38	4263	* @brief Enable Z direction in tap recognition.[set]
cparata	0:6d69e896ce38	4264	*
cparata	0:6d69e896ce38	4265	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4266	* @param val change the values of tap_z_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4267	*
cparata	0:6d69e896ce38	4268	*/
cparata	0:6d69e896ce38	4269	int32_t lsm6dso_tap_detection_on_z_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4270	{
cparata	4:77faf76e3cd8	4271	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	4272	int32_t ret;
cparata	4:77faf76e3cd8	4273
cparata	4:77faf76e3cd8	4274	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4275	if (ret == 0) {
cparata	4:77faf76e3cd8	4276	reg.tap_z_en = val;
cparata	4:77faf76e3cd8	4277	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4278	}
cparata	4:77faf76e3cd8	4279	return ret;
cparata	0:6d69e896ce38	4280	}
cparata	0:6d69e896ce38	4281
cparata	0:6d69e896ce38	4282	/**
cparata	0:6d69e896ce38	4283	* @brief Enable Z direction in tap recognition.[get]
cparata	0:6d69e896ce38	4284	*
cparata	0:6d69e896ce38	4285	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4286	* @param val change the values of tap_z_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4287	*
cparata	0:6d69e896ce38	4288	*/
cparata	0:6d69e896ce38	4289	int32_t lsm6dso_tap_detection_on_z_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4290	{
cparata	4:77faf76e3cd8	4291	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	4292	int32_t ret;
cparata	4:77faf76e3cd8	4293
cparata	4:77faf76e3cd8	4294	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4295	*val = reg.tap_z_en;
cparata	4:77faf76e3cd8	4296
cparata	4:77faf76e3cd8	4297	return ret;
cparata	0:6d69e896ce38	4298	}
cparata	0:6d69e896ce38	4299
cparata	0:6d69e896ce38	4300	/**
cparata	0:6d69e896ce38	4301	* @brief Enable Y direction in tap recognition.[set]
cparata	0:6d69e896ce38	4302	*
cparata	0:6d69e896ce38	4303	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4304	* @param val change the values of tap_y_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4305	*
cparata	0:6d69e896ce38	4306	*/
cparata	0:6d69e896ce38	4307	int32_t lsm6dso_tap_detection_on_y_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4308	{
cparata	4:77faf76e3cd8	4309	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	4310	int32_t ret;
cparata	4:77faf76e3cd8	4311
cparata	4:77faf76e3cd8	4312	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4313	if (ret == 0) {
cparata	4:77faf76e3cd8	4314	reg.tap_y_en = val;
cparata	4:77faf76e3cd8	4315	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4316	}
cparata	4:77faf76e3cd8	4317	return ret;
cparata	0:6d69e896ce38	4318	}
cparata	0:6d69e896ce38	4319
cparata	0:6d69e896ce38	4320	/**
cparata	0:6d69e896ce38	4321	* @brief Enable Y direction in tap recognition.[get]
cparata	0:6d69e896ce38	4322	*
cparata	0:6d69e896ce38	4323	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4324	* @param val change the values of tap_y_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4325	*
cparata	0:6d69e896ce38	4326	*/
cparata	0:6d69e896ce38	4327	int32_t lsm6dso_tap_detection_on_y_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4328	{
cparata	4:77faf76e3cd8	4329	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	4330	int32_t ret;
cparata	4:77faf76e3cd8	4331
cparata	4:77faf76e3cd8	4332	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4333	*val = reg.tap_y_en;
cparata	4:77faf76e3cd8	4334
cparata	4:77faf76e3cd8	4335	return ret;
cparata	0:6d69e896ce38	4336	}
cparata	0:6d69e896ce38	4337
cparata	0:6d69e896ce38	4338	/**
cparata	0:6d69e896ce38	4339	* @brief Enable X direction in tap recognition.[set]
cparata	0:6d69e896ce38	4340	*
cparata	0:6d69e896ce38	4341	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4342	* @param val change the values of tap_x_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4343	*
cparata	0:6d69e896ce38	4344	*/
cparata	0:6d69e896ce38	4345	int32_t lsm6dso_tap_detection_on_x_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4346	{
cparata	4:77faf76e3cd8	4347	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	4348	int32_t ret;
cparata	4:77faf76e3cd8	4349
cparata	4:77faf76e3cd8	4350	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4351	if (ret == 0) {
cparata	4:77faf76e3cd8	4352	reg.tap_x_en = val;
cparata	4:77faf76e3cd8	4353	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4354	}
cparata	4:77faf76e3cd8	4355	return ret;
cparata	0:6d69e896ce38	4356	}
cparata	0:6d69e896ce38	4357
cparata	0:6d69e896ce38	4358	/**
cparata	0:6d69e896ce38	4359	* @brief Enable X direction in tap recognition.[get]
cparata	0:6d69e896ce38	4360	*
cparata	0:6d69e896ce38	4361	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4362	* @param val change the values of tap_x_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4363	*
cparata	0:6d69e896ce38	4364	*/
cparata	0:6d69e896ce38	4365	int32_t lsm6dso_tap_detection_on_x_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4366	{
cparata	4:77faf76e3cd8	4367	lsm6dso_tap_cfg0_t reg;
cparata	4:77faf76e3cd8	4368	int32_t ret;
cparata	4:77faf76e3cd8	4369
cparata	4:77faf76e3cd8	4370	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4371	*val = reg.tap_x_en;
cparata	4:77faf76e3cd8	4372
cparata	4:77faf76e3cd8	4373	return ret;
cparata	0:6d69e896ce38	4374	}
cparata	0:6d69e896ce38	4375
cparata	0:6d69e896ce38	4376	/**
cparata	0:6d69e896ce38	4377	* @brief X-axis tap recognition threshold.[set]
cparata	0:6d69e896ce38	4378	*
cparata	0:6d69e896ce38	4379	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4380	* @param val change the values of tap_ths_x in reg TAP_CFG1
cparata	0:6d69e896ce38	4381	*
cparata	0:6d69e896ce38	4382	*/
cparata	0:6d69e896ce38	4383	int32_t lsm6dso_tap_threshold_x_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4384	{
cparata	4:77faf76e3cd8	4385	lsm6dso_tap_cfg1_t reg;
cparata	4:77faf76e3cd8	4386	int32_t ret;
cparata	4:77faf76e3cd8	4387
cparata	4:77faf76e3cd8	4388	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4389	if (ret == 0) {
cparata	4:77faf76e3cd8	4390	reg.tap_ths_x = val;
cparata	4:77faf76e3cd8	4391	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4392	}
cparata	4:77faf76e3cd8	4393	return ret;
cparata	0:6d69e896ce38	4394	}
cparata	0:6d69e896ce38	4395
cparata	0:6d69e896ce38	4396	/**
cparata	0:6d69e896ce38	4397	* @brief X-axis tap recognition threshold.[get]
cparata	0:6d69e896ce38	4398	*
cparata	0:6d69e896ce38	4399	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4400	* @param val change the values of tap_ths_x in reg TAP_CFG1
cparata	0:6d69e896ce38	4401	*
cparata	0:6d69e896ce38	4402	*/
cparata	0:6d69e896ce38	4403	int32_t lsm6dso_tap_threshold_x_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4404	{
cparata	4:77faf76e3cd8	4405	lsm6dso_tap_cfg1_t reg;
cparata	4:77faf76e3cd8	4406	int32_t ret;
cparata	4:77faf76e3cd8	4407
cparata	4:77faf76e3cd8	4408	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4409	*val = reg.tap_ths_x;
cparata	4:77faf76e3cd8	4410
cparata	4:77faf76e3cd8	4411	return ret;
cparata	0:6d69e896ce38	4412	}
cparata	0:6d69e896ce38	4413
cparata	0:6d69e896ce38	4414	/**
cparata	0:6d69e896ce38	4415	* @brief Selection of axis priority for TAP detection.[set]
cparata	0:6d69e896ce38	4416	*
cparata	0:6d69e896ce38	4417	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4418	* @param val change the values of tap_priority in
cparata	0:6d69e896ce38	4419	* reg TAP_CFG1
cparata	0:6d69e896ce38	4420	*
cparata	0:6d69e896ce38	4421	*/
cparata	0:6d69e896ce38	4422	int32_t lsm6dso_tap_axis_priority_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4423	lsm6dso_tap_priority_t val)
cparata	0:6d69e896ce38	4424	{
cparata	4:77faf76e3cd8	4425	lsm6dso_tap_cfg1_t reg;
cparata	4:77faf76e3cd8	4426	int32_t ret;
cparata	4:77faf76e3cd8	4427
cparata	4:77faf76e3cd8	4428	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4429	if (ret == 0) {
cparata	4:77faf76e3cd8	4430	reg.tap_priority = (uint8_t)val;
cparata	4:77faf76e3cd8	4431	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4432	}
cparata	4:77faf76e3cd8	4433	return ret;
cparata	0:6d69e896ce38	4434	}
cparata	0:6d69e896ce38	4435
cparata	0:6d69e896ce38	4436	/**
cparata	0:6d69e896ce38	4437	* @brief Selection of axis priority for TAP detection.[get]
cparata	0:6d69e896ce38	4438	*
cparata	0:6d69e896ce38	4439	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4440	* @param val Get the values of tap_priority in
cparata	0:6d69e896ce38	4441	* reg TAP_CFG1
cparata	0:6d69e896ce38	4442	*
cparata	0:6d69e896ce38	4443	*/
cparata	0:6d69e896ce38	4444	int32_t lsm6dso_tap_axis_priority_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4445	lsm6dso_tap_priority_t *val)
cparata	0:6d69e896ce38	4446	{
cparata	4:77faf76e3cd8	4447	lsm6dso_tap_cfg1_t reg;
cparata	4:77faf76e3cd8	4448	int32_t ret;
cparata	4:77faf76e3cd8	4449
cparata	4:77faf76e3cd8	4450	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4451	switch (reg.tap_priority) {
cparata	4:77faf76e3cd8	4452	case LSM6DSO_XYZ:
cparata	4:77faf76e3cd8	4453	*val = LSM6DSO_XYZ;
cparata	4:77faf76e3cd8	4454	break;
cparata	4:77faf76e3cd8	4455	case LSM6DSO_YXZ:
cparata	4:77faf76e3cd8	4456	*val = LSM6DSO_YXZ;
cparata	4:77faf76e3cd8	4457	break;
cparata	4:77faf76e3cd8	4458	case LSM6DSO_XZY:
cparata	4:77faf76e3cd8	4459	*val = LSM6DSO_XZY;
cparata	4:77faf76e3cd8	4460	break;
cparata	4:77faf76e3cd8	4461	case LSM6DSO_ZYX:
cparata	4:77faf76e3cd8	4462	*val = LSM6DSO_ZYX;
cparata	4:77faf76e3cd8	4463	break;
cparata	4:77faf76e3cd8	4464	case LSM6DSO_YZX:
cparata	4:77faf76e3cd8	4465	*val = LSM6DSO_YZX;
cparata	4:77faf76e3cd8	4466	break;
cparata	4:77faf76e3cd8	4467	case LSM6DSO_ZXY:
cparata	4:77faf76e3cd8	4468	*val = LSM6DSO_ZXY;
cparata	4:77faf76e3cd8	4469	break;
cparata	4:77faf76e3cd8	4470	default:
cparata	4:77faf76e3cd8	4471	*val = LSM6DSO_XYZ;
cparata	4:77faf76e3cd8	4472	break;
cparata	4:77faf76e3cd8	4473	}
cparata	4:77faf76e3cd8	4474	return ret;
cparata	0:6d69e896ce38	4475	}
cparata	0:6d69e896ce38	4476
cparata	0:6d69e896ce38	4477	/**
cparata	0:6d69e896ce38	4478	* @brief Y-axis tap recognition threshold.[set]
cparata	0:6d69e896ce38	4479	*
cparata	0:6d69e896ce38	4480	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4481	* @param val change the values of tap_ths_y in reg TAP_CFG2
cparata	0:6d69e896ce38	4482	*
cparata	0:6d69e896ce38	4483	*/
cparata	0:6d69e896ce38	4484	int32_t lsm6dso_tap_threshold_y_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4485	{
cparata	4:77faf76e3cd8	4486	lsm6dso_tap_cfg2_t reg;
cparata	4:77faf76e3cd8	4487	int32_t ret;
cparata	4:77faf76e3cd8	4488
cparata	4:77faf76e3cd8	4489	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4490	if (ret == 0) {
cparata	4:77faf76e3cd8	4491	reg.tap_ths_y = val;
cparata	4:77faf76e3cd8	4492	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4493	}
cparata	4:77faf76e3cd8	4494	return ret;
cparata	0:6d69e896ce38	4495	}
cparata	0:6d69e896ce38	4496
cparata	0:6d69e896ce38	4497	/**
cparata	0:6d69e896ce38	4498	* @brief Y-axis tap recognition threshold.[get]
cparata	0:6d69e896ce38	4499	*
cparata	0:6d69e896ce38	4500	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4501	* @param val change the values of tap_ths_y in reg TAP_CFG2
cparata	0:6d69e896ce38	4502	*
cparata	0:6d69e896ce38	4503	*/
cparata	0:6d69e896ce38	4504	int32_t lsm6dso_tap_threshold_y_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4505	{
cparata	4:77faf76e3cd8	4506	lsm6dso_tap_cfg2_t reg;
cparata	4:77faf76e3cd8	4507	int32_t ret;
cparata	4:77faf76e3cd8	4508
cparata	4:77faf76e3cd8	4509	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4510	*val = reg.tap_ths_y;
cparata	4:77faf76e3cd8	4511
cparata	4:77faf76e3cd8	4512	return ret;
cparata	0:6d69e896ce38	4513	}
cparata	0:6d69e896ce38	4514
cparata	0:6d69e896ce38	4515	/**
cparata	0:6d69e896ce38	4516	* @brief Z-axis recognition threshold.[set]
cparata	0:6d69e896ce38	4517	*
cparata	0:6d69e896ce38	4518	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4519	* @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata	0:6d69e896ce38	4520	*
cparata	0:6d69e896ce38	4521	*/
cparata	0:6d69e896ce38	4522	int32_t lsm6dso_tap_threshold_z_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4523	{
cparata	4:77faf76e3cd8	4524	lsm6dso_tap_ths_6d_t reg;
cparata	4:77faf76e3cd8	4525	int32_t ret;
cparata	4:77faf76e3cd8	4526
cparata	4:77faf76e3cd8	4527	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4528	if (ret == 0) {
cparata	4:77faf76e3cd8	4529	reg.tap_ths_z = val;
cparata	4:77faf76e3cd8	4530	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4531	}
cparata	4:77faf76e3cd8	4532	return ret;
cparata	0:6d69e896ce38	4533	}
cparata	0:6d69e896ce38	4534
cparata	0:6d69e896ce38	4535	/**
cparata	0:6d69e896ce38	4536	* @brief Z-axis recognition threshold.[get]
cparata	0:6d69e896ce38	4537	*
cparata	0:6d69e896ce38	4538	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4539	* @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata	0:6d69e896ce38	4540	*
cparata	0:6d69e896ce38	4541	*/
cparata	0:6d69e896ce38	4542	int32_t lsm6dso_tap_threshold_z_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4543	{
cparata	4:77faf76e3cd8	4544	lsm6dso_tap_ths_6d_t reg;
cparata	4:77faf76e3cd8	4545	int32_t ret;
cparata	4:77faf76e3cd8	4546
cparata	4:77faf76e3cd8	4547	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4548	*val = reg.tap_ths_z;
cparata	4:77faf76e3cd8	4549
cparata	4:77faf76e3cd8	4550	return ret;
cparata	0:6d69e896ce38	4551	}
cparata	0:6d69e896ce38	4552
cparata	0:6d69e896ce38	4553	/**
cparata	0:6d69e896ce38	4554	* @brief Maximum duration is the maximum time of an
cparata	0:6d69e896ce38	4555	* over threshold signal detection to be recognized
cparata	0:6d69e896ce38	4556	* as a tap event. The default value of these bits
cparata	0:6d69e896ce38	4557	* is 00b which corresponds to 4*ODR_XL time.
cparata	0:6d69e896ce38	4558	* If the SHOCK[1:0] bits are set to a different
cparata	0:6d69e896ce38	4559	* value, 1LSB corresponds to 8*ODR_XL time.[set]
cparata	0:6d69e896ce38	4560	*
cparata	0:6d69e896ce38	4561	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4562	* @param val change the values of shock in reg INT_DUR2
cparata	0:6d69e896ce38	4563	*
cparata	0:6d69e896ce38	4564	*/
cparata	0:6d69e896ce38	4565	int32_t lsm6dso_tap_shock_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4566	{
cparata	4:77faf76e3cd8	4567	lsm6dso_int_dur2_t reg;
cparata	4:77faf76e3cd8	4568	int32_t ret;
cparata	4:77faf76e3cd8	4569
cparata	4:77faf76e3cd8	4570	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4571	if (ret == 0) {
cparata	4:77faf76e3cd8	4572	reg.shock = val;
cparata	4:77faf76e3cd8	4573	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4574	}
cparata	4:77faf76e3cd8	4575	return ret;
cparata	0:6d69e896ce38	4576	}
cparata	0:6d69e896ce38	4577
cparata	0:6d69e896ce38	4578	/**
cparata	0:6d69e896ce38	4579	* @brief Maximum duration is the maximum time of an
cparata	0:6d69e896ce38	4580	* over threshold signal detection to be recognized
cparata	0:6d69e896ce38	4581	* as a tap event. The default value of these bits
cparata	0:6d69e896ce38	4582	* is 00b which corresponds to 4*ODR_XL time.
cparata	0:6d69e896ce38	4583	* If the SHOCK[1:0] bits are set to a different
cparata	0:6d69e896ce38	4584	* value, 1LSB corresponds to 8*ODR_XL time.[get]
cparata	0:6d69e896ce38	4585	*
cparata	0:6d69e896ce38	4586	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4587	* @param val change the values of shock in reg INT_DUR2
cparata	0:6d69e896ce38	4588	*
cparata	0:6d69e896ce38	4589	*/
cparata	0:6d69e896ce38	4590	int32_t lsm6dso_tap_shock_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4591	{
cparata	4:77faf76e3cd8	4592	lsm6dso_int_dur2_t reg;
cparata	4:77faf76e3cd8	4593	int32_t ret;
cparata	4:77faf76e3cd8	4594
cparata	4:77faf76e3cd8	4595	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4596	*val = reg.shock;
cparata	4:77faf76e3cd8	4597
cparata	4:77faf76e3cd8	4598	return ret;
cparata	0:6d69e896ce38	4599	}
cparata	0:6d69e896ce38	4600
cparata	0:6d69e896ce38	4601	/**
cparata	0:6d69e896ce38	4602	* @brief Quiet time is the time after the first detected
cparata	0:6d69e896ce38	4603	* tap in which there must not be any over threshold
cparata	0:6d69e896ce38	4604	* event.
cparata	0:6d69e896ce38	4605	* The default value of these bits is 00b which
cparata	0:6d69e896ce38	4606	* corresponds to 2*ODR_XL time. If the QUIET[1:0]
cparata	0:6d69e896ce38	4607	* bits are set to a different value,
cparata	0:6d69e896ce38	4608	* 1LSB corresponds to 4*ODR_XL time.[set]
cparata	0:6d69e896ce38	4609	*
cparata	0:6d69e896ce38	4610	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4611	* @param val change the values of quiet in reg INT_DUR2
cparata	0:6d69e896ce38	4612	*
cparata	0:6d69e896ce38	4613	*/
cparata	0:6d69e896ce38	4614	int32_t lsm6dso_tap_quiet_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4615	{
cparata	4:77faf76e3cd8	4616	lsm6dso_int_dur2_t reg;
cparata	4:77faf76e3cd8	4617	int32_t ret;
cparata	4:77faf76e3cd8	4618
cparata	4:77faf76e3cd8	4619	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4620	if (ret == 0) {
cparata	4:77faf76e3cd8	4621	reg.quiet = val;
cparata	4:77faf76e3cd8	4622	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4623	}
cparata	4:77faf76e3cd8	4624	return ret;
cparata	0:6d69e896ce38	4625	}
cparata	0:6d69e896ce38	4626
cparata	0:6d69e896ce38	4627	/**
cparata	0:6d69e896ce38	4628	* @brief Quiet time is the time after the first detected
cparata	0:6d69e896ce38	4629	* tap in which there must not be any over threshold
cparata	0:6d69e896ce38	4630	* event.
cparata	0:6d69e896ce38	4631	* The default value of these bits is 00b which
cparata	0:6d69e896ce38	4632	* corresponds to 2*ODR_XL time.
cparata	0:6d69e896ce38	4633	* If the QUIET[1:0] bits are set to a different
cparata	0:6d69e896ce38	4634	* value, 1LSB corresponds to 4*ODR_XL time.[get]
cparata	0:6d69e896ce38	4635	*
cparata	0:6d69e896ce38	4636	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4637	* @param val change the values of quiet in reg INT_DUR2
cparata	0:6d69e896ce38	4638	*
cparata	0:6d69e896ce38	4639	*/
cparata	0:6d69e896ce38	4640	int32_t lsm6dso_tap_quiet_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4641	{
cparata	4:77faf76e3cd8	4642	lsm6dso_int_dur2_t reg;
cparata	4:77faf76e3cd8	4643	int32_t ret;
cparata	4:77faf76e3cd8	4644
cparata	4:77faf76e3cd8	4645	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4646	*val = reg.quiet;
cparata	4:77faf76e3cd8	4647
cparata	4:77faf76e3cd8	4648	return ret;
cparata	0:6d69e896ce38	4649	}
cparata	0:6d69e896ce38	4650
cparata	0:6d69e896ce38	4651	/**
cparata	0:6d69e896ce38	4652	* @brief When double tap recognition is enabled,
cparata	0:6d69e896ce38	4653	* this register expresses the maximum time
cparata	0:6d69e896ce38	4654	* between two consecutive detected taps to
cparata	0:6d69e896ce38	4655	* determine a double tap event.
cparata	0:6d69e896ce38	4656	* The default value of these bits is 0000b which
cparata	0:6d69e896ce38	4657	* corresponds to 16*ODR_XL time.
cparata	0:6d69e896ce38	4658	* If the DUR[3:0] bits are set to a different value,
cparata	0:6d69e896ce38	4659	* 1LSB corresponds to 32*ODR_XL time.[set]
cparata	0:6d69e896ce38	4660	*
cparata	0:6d69e896ce38	4661	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4662	* @param val change the values of dur in reg INT_DUR2
cparata	0:6d69e896ce38	4663	*
cparata	0:6d69e896ce38	4664	*/
cparata	0:6d69e896ce38	4665	int32_t lsm6dso_tap_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4666	{
cparata	4:77faf76e3cd8	4667	lsm6dso_int_dur2_t reg;
cparata	4:77faf76e3cd8	4668	int32_t ret;
cparata	4:77faf76e3cd8	4669
cparata	4:77faf76e3cd8	4670	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4671	if (ret == 0) {
cparata	4:77faf76e3cd8	4672	reg.dur = val;
cparata	4:77faf76e3cd8	4673	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4674	}
cparata	4:77faf76e3cd8	4675	return ret;
cparata	0:6d69e896ce38	4676	}
cparata	0:6d69e896ce38	4677
cparata	0:6d69e896ce38	4678	/**
cparata	0:6d69e896ce38	4679	* @brief When double tap recognition is enabled,
cparata	0:6d69e896ce38	4680	* this register expresses the maximum time
cparata	0:6d69e896ce38	4681	* between two consecutive detected taps to
cparata	0:6d69e896ce38	4682	* determine a double tap event.
cparata	0:6d69e896ce38	4683	* The default value of these bits is 0000b which
cparata	0:6d69e896ce38	4684	* corresponds to 16*ODR_XL time. If the DUR[3:0]
cparata	0:6d69e896ce38	4685	* bits are set to a different value,
cparata	0:6d69e896ce38	4686	* 1LSB corresponds to 32*ODR_XL time.[get]
cparata	0:6d69e896ce38	4687	*
cparata	0:6d69e896ce38	4688	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4689	* @param val change the values of dur in reg INT_DUR2
cparata	0:6d69e896ce38	4690	*
cparata	0:6d69e896ce38	4691	*/
cparata	0:6d69e896ce38	4692	int32_t lsm6dso_tap_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4693	{
cparata	4:77faf76e3cd8	4694	lsm6dso_int_dur2_t reg;
cparata	4:77faf76e3cd8	4695	int32_t ret;
cparata	4:77faf76e3cd8	4696
cparata	4:77faf76e3cd8	4697	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4698	*val = reg.dur;
cparata	4:77faf76e3cd8	4699
cparata	4:77faf76e3cd8	4700	return ret;
cparata	0:6d69e896ce38	4701	}
cparata	0:6d69e896ce38	4702
cparata	0:6d69e896ce38	4703	/**
cparata	0:6d69e896ce38	4704	* @brief Single/double-tap event enable.[set]
cparata	0:6d69e896ce38	4705	*
cparata	0:6d69e896ce38	4706	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4707	* @param val change the values of single_double_tap in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4708	*
cparata	0:6d69e896ce38	4709	*/
cparata	0:6d69e896ce38	4710	int32_t lsm6dso_tap_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4711	lsm6dso_single_double_tap_t val)
cparata	0:6d69e896ce38	4712	{
cparata	4:77faf76e3cd8	4713	lsm6dso_wake_up_ths_t reg;
cparata	4:77faf76e3cd8	4714	int32_t ret;
cparata	4:77faf76e3cd8	4715
cparata	4:77faf76e3cd8	4716	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4717	if (ret == 0) {
cparata	4:77faf76e3cd8	4718	reg.single_double_tap = (uint8_t)val;
cparata	4:77faf76e3cd8	4719	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4720	}
cparata	4:77faf76e3cd8	4721	return ret;
cparata	0:6d69e896ce38	4722	}
cparata	0:6d69e896ce38	4723
cparata	0:6d69e896ce38	4724	/**
cparata	0:6d69e896ce38	4725	* @brief Single/double-tap event enable.[get]
cparata	0:6d69e896ce38	4726	*
cparata	0:6d69e896ce38	4727	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4728	* @param val Get the values of single_double_tap in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4729	*
cparata	0:6d69e896ce38	4730	*/
cparata	0:6d69e896ce38	4731	int32_t lsm6dso_tap_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4732	lsm6dso_single_double_tap_t *val)
cparata	0:6d69e896ce38	4733	{
cparata	4:77faf76e3cd8	4734	lsm6dso_wake_up_ths_t reg;
cparata	4:77faf76e3cd8	4735	int32_t ret;
cparata	4:77faf76e3cd8	4736
cparata	4:77faf76e3cd8	4737	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4738
cparata	4:77faf76e3cd8	4739	switch (reg.single_double_tap) {
cparata	4:77faf76e3cd8	4740	case LSM6DSO_ONLY_SINGLE:
cparata	4:77faf76e3cd8	4741	*val = LSM6DSO_ONLY_SINGLE;
cparata	4:77faf76e3cd8	4742	break;
cparata	4:77faf76e3cd8	4743	case LSM6DSO_BOTH_SINGLE_DOUBLE:
cparata	4:77faf76e3cd8	4744	*val = LSM6DSO_BOTH_SINGLE_DOUBLE;
cparata	4:77faf76e3cd8	4745	break;
cparata	4:77faf76e3cd8	4746	default:
cparata	4:77faf76e3cd8	4747	*val = LSM6DSO_ONLY_SINGLE;
cparata	4:77faf76e3cd8	4748	break;
cparata	4:77faf76e3cd8	4749	}
cparata	4:77faf76e3cd8	4750
cparata	4:77faf76e3cd8	4751	return ret;
cparata	0:6d69e896ce38	4752	}
cparata	0:6d69e896ce38	4753
cparata	0:6d69e896ce38	4754	/**
cparata	0:6d69e896ce38	4755	* @}
cparata	0:6d69e896ce38	4756	*
cparata	0:6d69e896ce38	4757	*/
cparata	0:6d69e896ce38	4758
cparata	0:6d69e896ce38	4759	/**
cparata	0:6d69e896ce38	4760	* @defgroup LSM6DSO_ Six_position_detection(6D/4D)
cparata	0:6d69e896ce38	4761	* @brief This section groups all the functions concerning six position
cparata	0:6d69e896ce38	4762	* detection (6D).
cparata	0:6d69e896ce38	4763	* @{
cparata	0:6d69e896ce38	4764	*
cparata	0:6d69e896ce38	4765	*/
cparata	0:6d69e896ce38	4766
cparata	0:6d69e896ce38	4767	/**
cparata	0:6d69e896ce38	4768	* @brief Threshold for 4D/6D function.[set]
cparata	0:6d69e896ce38	4769	*
cparata	0:6d69e896ce38	4770	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4771	* @param val change the values of sixd_ths in reg TAP_THS_6D
cparata	0:6d69e896ce38	4772	*
cparata	0:6d69e896ce38	4773	*/
cparata	0:6d69e896ce38	4774	int32_t lsm6dso_6d_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_sixd_ths_t val)
cparata	0:6d69e896ce38	4775	{
cparata	4:77faf76e3cd8	4776	lsm6dso_tap_ths_6d_t reg;
cparata	4:77faf76e3cd8	4777	int32_t ret;
cparata	4:77faf76e3cd8	4778
cparata	4:77faf76e3cd8	4779	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4780	if (ret == 0) {
cparata	4:77faf76e3cd8	4781	reg.sixd_ths = (uint8_t)val;
cparata	4:77faf76e3cd8	4782	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4783	}
cparata	4:77faf76e3cd8	4784	return ret;
cparata	0:6d69e896ce38	4785	}
cparata	0:6d69e896ce38	4786
cparata	0:6d69e896ce38	4787	/**
cparata	0:6d69e896ce38	4788	* @brief Threshold for 4D/6D function.[get]
cparata	0:6d69e896ce38	4789	*
cparata	0:6d69e896ce38	4790	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4791	* @param val Get the values of sixd_ths in reg TAP_THS_6D
cparata	0:6d69e896ce38	4792	*
cparata	0:6d69e896ce38	4793	*/
cparata	0:6d69e896ce38	4794	int32_t lsm6dso_6d_threshold_get(lsm6dso_ctx_t ctx, lsm6dso_sixd_ths_t val)
cparata	0:6d69e896ce38	4795	{
cparata	4:77faf76e3cd8	4796	lsm6dso_tap_ths_6d_t reg;
cparata	4:77faf76e3cd8	4797	int32_t ret;
cparata	4:77faf76e3cd8	4798
cparata	4:77faf76e3cd8	4799	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4800	switch (reg.sixd_ths) {
cparata	4:77faf76e3cd8	4801	case LSM6DSO_DEG_80:
cparata	4:77faf76e3cd8	4802	*val = LSM6DSO_DEG_80;
cparata	4:77faf76e3cd8	4803	break;
cparata	4:77faf76e3cd8	4804	case LSM6DSO_DEG_70:
cparata	4:77faf76e3cd8	4805	*val = LSM6DSO_DEG_70;
cparata	4:77faf76e3cd8	4806	break;
cparata	4:77faf76e3cd8	4807	case LSM6DSO_DEG_60:
cparata	4:77faf76e3cd8	4808	*val = LSM6DSO_DEG_60;
cparata	4:77faf76e3cd8	4809	break;
cparata	4:77faf76e3cd8	4810	case LSM6DSO_DEG_50:
cparata	4:77faf76e3cd8	4811	*val = LSM6DSO_DEG_50;
cparata	4:77faf76e3cd8	4812	break;
cparata	4:77faf76e3cd8	4813	default:
cparata	4:77faf76e3cd8	4814	*val = LSM6DSO_DEG_80;
cparata	4:77faf76e3cd8	4815	break;
cparata	4:77faf76e3cd8	4816	}
cparata	4:77faf76e3cd8	4817	return ret;
cparata	0:6d69e896ce38	4818	}
cparata	0:6d69e896ce38	4819
cparata	0:6d69e896ce38	4820	/**
cparata	0:6d69e896ce38	4821	* @brief 4D orientation detection enable.[set]
cparata	0:6d69e896ce38	4822	*
cparata	0:6d69e896ce38	4823	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4824	* @param val change the values of d4d_en in reg TAP_THS_6D
cparata	0:6d69e896ce38	4825	*
cparata	0:6d69e896ce38	4826	*/
cparata	0:6d69e896ce38	4827	int32_t lsm6dso_4d_mode_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4828	{
cparata	4:77faf76e3cd8	4829	lsm6dso_tap_ths_6d_t reg;
cparata	4:77faf76e3cd8	4830	int32_t ret;
cparata	4:77faf76e3cd8	4831
cparata	4:77faf76e3cd8	4832	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4833	if (ret == 0) {
cparata	4:77faf76e3cd8	4834	reg.d4d_en = val;
cparata	4:77faf76e3cd8	4835	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4836	}
cparata	4:77faf76e3cd8	4837	return ret;
cparata	0:6d69e896ce38	4838	}
cparata	0:6d69e896ce38	4839
cparata	0:6d69e896ce38	4840	/**
cparata	0:6d69e896ce38	4841	* @brief 4D orientation detection enable.[get]
cparata	0:6d69e896ce38	4842	*
cparata	0:6d69e896ce38	4843	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4844	* @param val change the values of d4d_en in reg TAP_THS_6D
cparata	0:6d69e896ce38	4845	*
cparata	0:6d69e896ce38	4846	*/
cparata	0:6d69e896ce38	4847	int32_t lsm6dso_4d_mode_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4848	{
cparata	4:77faf76e3cd8	4849	lsm6dso_tap_ths_6d_t reg;
cparata	4:77faf76e3cd8	4850	int32_t ret;
cparata	4:77faf76e3cd8	4851
cparata	4:77faf76e3cd8	4852	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4853	*val = reg.d4d_en;
cparata	4:77faf76e3cd8	4854
cparata	4:77faf76e3cd8	4855	return ret;
cparata	0:6d69e896ce38	4856	}
cparata	0:6d69e896ce38	4857
cparata	0:6d69e896ce38	4858	/**
cparata	0:6d69e896ce38	4859	* @}
cparata	0:6d69e896ce38	4860	*
cparata	0:6d69e896ce38	4861	*/
cparata	0:6d69e896ce38	4862
cparata	0:6d69e896ce38	4863	/**
cparata	0:6d69e896ce38	4864	* @defgroup LSM6DSO_free_fall
cparata	0:6d69e896ce38	4865	* @brief This section group all the functions concerning the free
cparata	0:6d69e896ce38	4866	* fall detection.
cparata	0:6d69e896ce38	4867	* @{
cparata	0:6d69e896ce38	4868	*
cparata	0:6d69e896ce38	4869	*/
cparata	0:6d69e896ce38	4870	/**
cparata	0:6d69e896ce38	4871	* @brief Free fall threshold setting.[set]
cparata	0:6d69e896ce38	4872	*
cparata	0:6d69e896ce38	4873	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4874	* @param val change the values of ff_ths in reg FREE_FALL
cparata	0:6d69e896ce38	4875	*
cparata	0:6d69e896ce38	4876	*/
cparata	0:6d69e896ce38	4877	int32_t lsm6dso_ff_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_ff_ths_t val)
cparata	0:6d69e896ce38	4878	{
cparata	4:77faf76e3cd8	4879	lsm6dso_free_fall_t reg;
cparata	4:77faf76e3cd8	4880	int32_t ret;
cparata	4:77faf76e3cd8	4881
cparata	4:77faf76e3cd8	4882	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4883	if (ret == 0) {
cparata	4:77faf76e3cd8	4884	reg.ff_ths = (uint8_t)val;
cparata	4:77faf76e3cd8	4885	ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4886	}
cparata	4:77faf76e3cd8	4887	return ret;
cparata	0:6d69e896ce38	4888	}
cparata	0:6d69e896ce38	4889
cparata	0:6d69e896ce38	4890	/**
cparata	0:6d69e896ce38	4891	* @brief Free fall threshold setting.[get]
cparata	0:6d69e896ce38	4892	*
cparata	0:6d69e896ce38	4893	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4894	* @param val Get the values of ff_ths in reg FREE_FALL
cparata	0:6d69e896ce38	4895	*
cparata	0:6d69e896ce38	4896	*/
cparata	0:6d69e896ce38	4897	int32_t lsm6dso_ff_threshold_get(lsm6dso_ctx_t ctx, lsm6dso_ff_ths_t val)
cparata	0:6d69e896ce38	4898	{
cparata	4:77faf76e3cd8	4899	lsm6dso_free_fall_t reg;
cparata	4:77faf76e3cd8	4900	int32_t ret;
cparata	4:77faf76e3cd8	4901
cparata	4:77faf76e3cd8	4902	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	4903	switch (reg.ff_ths) {
cparata	4:77faf76e3cd8	4904	case LSM6DSO_FF_TSH_156mg:
cparata	4:77faf76e3cd8	4905	*val = LSM6DSO_FF_TSH_156mg;
cparata	4:77faf76e3cd8	4906	break;
cparata	4:77faf76e3cd8	4907	case LSM6DSO_FF_TSH_219mg:
cparata	4:77faf76e3cd8	4908	*val = LSM6DSO_FF_TSH_219mg;
cparata	4:77faf76e3cd8	4909	break;
cparata	4:77faf76e3cd8	4910	case LSM6DSO_FF_TSH_250mg:
cparata	4:77faf76e3cd8	4911	*val = LSM6DSO_FF_TSH_250mg;
cparata	4:77faf76e3cd8	4912	break;
cparata	4:77faf76e3cd8	4913	case LSM6DSO_FF_TSH_312mg:
cparata	4:77faf76e3cd8	4914	*val = LSM6DSO_FF_TSH_312mg;
cparata	4:77faf76e3cd8	4915	break;
cparata	4:77faf76e3cd8	4916	case LSM6DSO_FF_TSH_344mg:
cparata	4:77faf76e3cd8	4917	*val = LSM6DSO_FF_TSH_344mg;
cparata	4:77faf76e3cd8	4918	break;
cparata	4:77faf76e3cd8	4919	case LSM6DSO_FF_TSH_406mg:
cparata	4:77faf76e3cd8	4920	*val = LSM6DSO_FF_TSH_406mg;
cparata	4:77faf76e3cd8	4921	break;
cparata	4:77faf76e3cd8	4922	case LSM6DSO_FF_TSH_469mg:
cparata	4:77faf76e3cd8	4923	*val = LSM6DSO_FF_TSH_469mg;
cparata	4:77faf76e3cd8	4924	break;
cparata	4:77faf76e3cd8	4925	case LSM6DSO_FF_TSH_500mg:
cparata	4:77faf76e3cd8	4926	*val = LSM6DSO_FF_TSH_500mg;
cparata	4:77faf76e3cd8	4927	break;
cparata	4:77faf76e3cd8	4928	default:
cparata	4:77faf76e3cd8	4929	*val = LSM6DSO_FF_TSH_156mg;
cparata	4:77faf76e3cd8	4930	break;
cparata	4:77faf76e3cd8	4931	}
cparata	4:77faf76e3cd8	4932	return ret;
cparata	0:6d69e896ce38	4933	}
cparata	0:6d69e896ce38	4934
cparata	0:6d69e896ce38	4935	/**
cparata	0:6d69e896ce38	4936	* @brief Free-fall duration event.[set]
cparata	0:6d69e896ce38	4937	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4938	*
cparata	0:6d69e896ce38	4939	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4940	* @param val change the values of ff_dur in reg FREE_FALL
cparata	0:6d69e896ce38	4941	*
cparata	0:6d69e896ce38	4942	*/
cparata	0:6d69e896ce38	4943	int32_t lsm6dso_ff_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4944	{
cparata	4:77faf76e3cd8	4945	lsm6dso_wake_up_dur_t wake_up_dur;
cparata	4:77faf76e3cd8	4946	lsm6dso_free_fall_t free_fall;
cparata	4:77faf76e3cd8	4947	int32_t ret;
cparata	4:77faf76e3cd8	4948
cparata	4:77faf76e3cd8	4949	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
cparata	4:77faf76e3cd8	4950	if (ret == 0) {
cparata	4:77faf76e3cd8	4951	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata	4:77faf76e3cd8	4952	}
cparata	4:77faf76e3cd8	4953	if (ret == 0) {
cparata	4:77faf76e3cd8	4954	wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
cparata	4:77faf76e3cd8	4955	free_fall.ff_dur = (uint8_t)val & 0x1FU;
cparata	4:77faf76e3cd8	4956	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR,
cparata	4:77faf76e3cd8	4957	(uint8_t*)&wake_up_dur, 1);
cparata	4:77faf76e3cd8	4958	}
cparata	4:77faf76e3cd8	4959	if (ret == 0) {
cparata	4:77faf76e3cd8	4960	ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata	4:77faf76e3cd8	4961	}
cparata	4:77faf76e3cd8	4962	return ret;
cparata	0:6d69e896ce38	4963	}
cparata	0:6d69e896ce38	4964
cparata	0:6d69e896ce38	4965	/**
cparata	0:6d69e896ce38	4966	* @brief Free-fall duration event.[get]
cparata	0:6d69e896ce38	4967	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4968	*
cparata	0:6d69e896ce38	4969	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4970	* @param val change the values of ff_dur in reg FREE_FALL
cparata	0:6d69e896ce38	4971	*
cparata	0:6d69e896ce38	4972	*/
cparata	0:6d69e896ce38	4973	int32_t lsm6dso_ff_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4974	{
cparata	4:77faf76e3cd8	4975	lsm6dso_wake_up_dur_t wake_up_dur;
cparata	4:77faf76e3cd8	4976	lsm6dso_free_fall_t free_fall;
cparata	4:77faf76e3cd8	4977	int32_t ret;
cparata	4:77faf76e3cd8	4978
cparata	4:77faf76e3cd8	4979	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
cparata	4:77faf76e3cd8	4980	if (ret == 0) {
cparata	4:77faf76e3cd8	4981	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata	4:77faf76e3cd8	4982	*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
cparata	4:77faf76e3cd8	4983	}
cparata	4:77faf76e3cd8	4984	return ret;
cparata	0:6d69e896ce38	4985	}
cparata	0:6d69e896ce38	4986
cparata	0:6d69e896ce38	4987	/**
cparata	0:6d69e896ce38	4988	* @}
cparata	0:6d69e896ce38	4989	*
cparata	0:6d69e896ce38	4990	*/
cparata	0:6d69e896ce38	4991
cparata	0:6d69e896ce38	4992	/**
cparata	0:6d69e896ce38	4993	* @defgroup LSM6DSO_fifo
cparata	0:6d69e896ce38	4994	* @brief This section group all the functions concerning the fifo usage
cparata	0:6d69e896ce38	4995	* @{
cparata	0:6d69e896ce38	4996	*
cparata	0:6d69e896ce38	4997	*/
cparata	0:6d69e896ce38	4998
cparata	0:6d69e896ce38	4999	/**
cparata	0:6d69e896ce38	5000	* @brief FIFO watermark level selection.[set]
cparata	0:6d69e896ce38	5001	*
cparata	0:6d69e896ce38	5002	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5003	* @param val change the values of wtm in reg FIFO_CTRL1
cparata	0:6d69e896ce38	5004	*
cparata	0:6d69e896ce38	5005	*/
cparata	0:6d69e896ce38	5006	int32_t lsm6dso_fifo_watermark_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	0:6d69e896ce38	5007	{
cparata	4:77faf76e3cd8	5008	lsm6dso_fifo_ctrl1_t fifo_ctrl1;
cparata	4:77faf76e3cd8	5009	lsm6dso_fifo_ctrl2_t fifo_ctrl2;
cparata	4:77faf76e3cd8	5010	int32_t ret;
cparata	4:77faf76e3cd8	5011
cparata	4:77faf76e3cd8	5012	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata	4:77faf76e3cd8	5013	if (ret == 0) {
cparata	4:77faf76e3cd8	5014	fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
cparata	4:77faf76e3cd8	5015	fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
cparata	4:77faf76e3cd8	5016	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
cparata	4:77faf76e3cd8	5017	}
cparata	4:77faf76e3cd8	5018	if (ret == 0) {
cparata	4:77faf76e3cd8	5019	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata	4:77faf76e3cd8	5020	}
cparata	4:77faf76e3cd8	5021	return ret;
cparata	0:6d69e896ce38	5022	}
cparata	0:6d69e896ce38	5023
cparata	0:6d69e896ce38	5024	/**
cparata	0:6d69e896ce38	5025	* @brief FIFO watermark level selection.[get]
cparata	0:6d69e896ce38	5026	*
cparata	0:6d69e896ce38	5027	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5028	* @param val change the values of wtm in reg FIFO_CTRL1
cparata	0:6d69e896ce38	5029	*
cparata	0:6d69e896ce38	5030	*/
cparata	0:6d69e896ce38	5031	int32_t lsm6dso_fifo_watermark_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	0:6d69e896ce38	5032	{
cparata	4:77faf76e3cd8	5033	lsm6dso_fifo_ctrl1_t fifo_ctrl1;
cparata	4:77faf76e3cd8	5034	lsm6dso_fifo_ctrl2_t fifo_ctrl2;
cparata	4:77faf76e3cd8	5035	int32_t ret;
cparata	4:77faf76e3cd8	5036
cparata	4:77faf76e3cd8	5037	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
cparata	4:77faf76e3cd8	5038	if (ret == 0) {
cparata	4:77faf76e3cd8	5039	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata	4:77faf76e3cd8	5040	*val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
cparata	4:77faf76e3cd8	5041	}
cparata	4:77faf76e3cd8	5042	return ret;
cparata	0:6d69e896ce38	5043	}
cparata	0:6d69e896ce38	5044
cparata	0:6d69e896ce38	5045	/**
cparata	0:6d69e896ce38	5046	* @brief FIFO compression feature initialization request [set].
cparata	0:6d69e896ce38	5047	*
cparata	0:6d69e896ce38	5048	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5049	* @param val change the values of FIFO_COMPR_INIT in
cparata	0:6d69e896ce38	5050	* reg EMB_FUNC_INIT_B
cparata	0:6d69e896ce38	5051	*
cparata	0:6d69e896ce38	5052	*/
cparata	0:6d69e896ce38	5053	int32_t lsm6dso_compression_algo_init_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5054	{
cparata	4:77faf76e3cd8	5055	lsm6dso_emb_func_init_b_t reg;
cparata	4:77faf76e3cd8	5056	int32_t ret;
cparata	4:77faf76e3cd8	5057
cparata	4:77faf76e3cd8	5058	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	5059	if (ret == 0) {
cparata	4:77faf76e3cd8	5060	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5061	}
cparata	4:77faf76e3cd8	5062	if (ret == 0) {
cparata	4:77faf76e3cd8	5063	reg.fifo_compr_init = val;
cparata	4:77faf76e3cd8	5064	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5065	}
cparata	4:77faf76e3cd8	5066	if (ret == 0) {
cparata	4:77faf76e3cd8	5067	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	5068	}
cparata	4:77faf76e3cd8	5069
cparata	4:77faf76e3cd8	5070	return ret;
cparata	0:6d69e896ce38	5071	}
cparata	0:6d69e896ce38	5072
cparata	0:6d69e896ce38	5073	/**
cparata	0:6d69e896ce38	5074	* @brief FIFO compression feature initialization request [get].
cparata	0:6d69e896ce38	5075	*
cparata	0:6d69e896ce38	5076	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5077	* @param val change the values of FIFO_COMPR_INIT in
cparata	0:6d69e896ce38	5078	* reg EMB_FUNC_INIT_B
cparata	0:6d69e896ce38	5079	*
cparata	0:6d69e896ce38	5080	*/
cparata	0:6d69e896ce38	5081	int32_t lsm6dso_compression_algo_init_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5082	{
cparata	4:77faf76e3cd8	5083	lsm6dso_emb_func_init_b_t reg;
cparata	4:77faf76e3cd8	5084	int32_t ret;
cparata	4:77faf76e3cd8	5085
cparata	4:77faf76e3cd8	5086	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	5087	if (ret == 0) {
cparata	4:77faf76e3cd8	5088	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5089	}
cparata	4:77faf76e3cd8	5090	if (ret == 0) {
cparata	4:77faf76e3cd8	5091	*val = reg.fifo_compr_init;
cparata	4:77faf76e3cd8	5092	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	5093	}
cparata	4:77faf76e3cd8	5094
cparata	4:77faf76e3cd8	5095	return ret;
cparata	0:6d69e896ce38	5096	}
cparata	0:6d69e896ce38	5097
cparata	0:6d69e896ce38	5098	/**
cparata	0:6d69e896ce38	5099	* @brief Enable and configure compression algo.[set]
cparata	0:6d69e896ce38	5100	*
cparata	0:6d69e896ce38	5101	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5102	* @param val change the values of uncoptr_rate in
cparata	0:6d69e896ce38	5103	* reg FIFO_CTRL2
cparata	0:6d69e896ce38	5104	*
cparata	0:6d69e896ce38	5105	*/
cparata	0:6d69e896ce38	5106	int32_t lsm6dso_compression_algo_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5107	lsm6dso_uncoptr_rate_t val)
cparata	0:6d69e896ce38	5108	{
cparata	4:77faf76e3cd8	5109	lsm6dso_fifo_ctrl2_t fifo_ctrl2;
cparata	4:77faf76e3cd8	5110	int32_t ret;
cparata	4:77faf76e3cd8	5111
cparata	4:77faf76e3cd8	5112	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
cparata	4:77faf76e3cd8	5113	(uint8_t*)&fifo_ctrl2, 1);
cparata	4:77faf76e3cd8	5114
cparata	4:77faf76e3cd8	5115	if (ret == 0) {
cparata	4:77faf76e3cd8	5116	fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
cparata	4:77faf76e3cd8	5117	fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
cparata	4:77faf76e3cd8	5118	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
cparata	4:77faf76e3cd8	5119	(uint8_t*)&fifo_ctrl2, 1);
cparata	4:77faf76e3cd8	5120	}
cparata	4:77faf76e3cd8	5121	return ret;
cparata	0:6d69e896ce38	5122	}
cparata	0:6d69e896ce38	5123
cparata	0:6d69e896ce38	5124	/**
cparata	0:6d69e896ce38	5125	* @brief Enable and configure compression algo.[get]
cparata	0:6d69e896ce38	5126	*
cparata	0:6d69e896ce38	5127	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5128	* @param val Get the values of uncoptr_rate in
cparata	0:6d69e896ce38	5129	* reg FIFO_CTRL2
cparata	0:6d69e896ce38	5130	*
cparata	0:6d69e896ce38	5131	*/
cparata	0:6d69e896ce38	5132	int32_t lsm6dso_compression_algo_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5133	lsm6dso_uncoptr_rate_t *val)
cparata	0:6d69e896ce38	5134	{
cparata	4:77faf76e3cd8	5135	lsm6dso_fifo_ctrl2_t reg;
cparata	4:77faf76e3cd8	5136	int32_t ret;
cparata	4:77faf76e3cd8	5137
cparata	4:77faf76e3cd8	5138	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5139
cparata	4:77faf76e3cd8	5140	switch ((reg.fifo_compr_rt_en<<2) \| reg.uncoptr_rate) {
cparata	4:77faf76e3cd8	5141	case LSM6DSO_CMP_DISABLE:
cparata	4:77faf76e3cd8	5142	*val = LSM6DSO_CMP_DISABLE;
cparata	4:77faf76e3cd8	5143	break;
cparata	4:77faf76e3cd8	5144	case LSM6DSO_CMP_ALWAYS:
cparata	4:77faf76e3cd8	5145	*val = LSM6DSO_CMP_ALWAYS;
cparata	4:77faf76e3cd8	5146	break;
cparata	4:77faf76e3cd8	5147	case LSM6DSO_CMP_8_TO_1:
cparata	4:77faf76e3cd8	5148	*val = LSM6DSO_CMP_8_TO_1;
cparata	4:77faf76e3cd8	5149	break;
cparata	4:77faf76e3cd8	5150	case LSM6DSO_CMP_16_TO_1:
cparata	4:77faf76e3cd8	5151	*val = LSM6DSO_CMP_16_TO_1;
cparata	4:77faf76e3cd8	5152	break;
cparata	4:77faf76e3cd8	5153	case LSM6DSO_CMP_32_TO_1:
cparata	4:77faf76e3cd8	5154	*val = LSM6DSO_CMP_32_TO_1;
cparata	4:77faf76e3cd8	5155	break;
cparata	4:77faf76e3cd8	5156	default:
cparata	4:77faf76e3cd8	5157	*val = LSM6DSO_CMP_DISABLE;
cparata	4:77faf76e3cd8	5158	break;
cparata	4:77faf76e3cd8	5159	}
cparata	4:77faf76e3cd8	5160	return ret;
cparata	0:6d69e896ce38	5161	}
cparata	0:6d69e896ce38	5162
cparata	0:6d69e896ce38	5163	/**
cparata	0:6d69e896ce38	5164	* @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
cparata	0:6d69e896ce38	5165	*
cparata	0:6d69e896ce38	5166	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5167	* @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5168	*
cparata	0:6d69e896ce38	5169	*/
cparata	0:6d69e896ce38	5170	int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5171	uint8_t val)
cparata	0:6d69e896ce38	5172	{
cparata	4:77faf76e3cd8	5173	lsm6dso_fifo_ctrl2_t reg;
cparata	4:77faf76e3cd8	5174	int32_t ret;
cparata	4:77faf76e3cd8	5175
cparata	4:77faf76e3cd8	5176	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5177	if (ret == 0) {
cparata	4:77faf76e3cd8	5178	reg.odrchg_en = val;
cparata	4:77faf76e3cd8	5179	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5180	}
cparata	4:77faf76e3cd8	5181	return ret;
cparata	0:6d69e896ce38	5182	}
cparata	0:6d69e896ce38	5183
cparata	0:6d69e896ce38	5184	/**
cparata	0:6d69e896ce38	5185	* @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
cparata	0:6d69e896ce38	5186	*
cparata	0:6d69e896ce38	5187	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5188	* @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5189	*
cparata	0:6d69e896ce38	5190	*/
cparata	0:6d69e896ce38	5191	int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5192	uint8_t *val)
cparata	0:6d69e896ce38	5193	{
cparata	4:77faf76e3cd8	5194	lsm6dso_fifo_ctrl2_t reg;
cparata	4:77faf76e3cd8	5195	int32_t ret;
cparata	4:77faf76e3cd8	5196
cparata	4:77faf76e3cd8	5197	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5198	*val = reg.odrchg_en;
cparata	4:77faf76e3cd8	5199
cparata	4:77faf76e3cd8	5200	return ret;
cparata	0:6d69e896ce38	5201	}
cparata	0:6d69e896ce38	5202
cparata	0:6d69e896ce38	5203	/**
cparata	0:6d69e896ce38	5204	* @brief Enables/Disables compression algorithm runtime.[set]
cparata	0:6d69e896ce38	5205	*
cparata	0:6d69e896ce38	5206	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5207	* @param val change the values of fifo_compr_rt_en in
cparata	0:6d69e896ce38	5208	* reg FIFO_CTRL2
cparata	0:6d69e896ce38	5209	*
cparata	0:6d69e896ce38	5210	*/
cparata	0:6d69e896ce38	5211	int32_t lsm6dso_compression_algo_real_time_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5212	uint8_t val)
cparata	0:6d69e896ce38	5213	{
cparata	4:77faf76e3cd8	5214	lsm6dso_fifo_ctrl2_t reg;
cparata	4:77faf76e3cd8	5215	int32_t ret;
cparata	4:77faf76e3cd8	5216
cparata	4:77faf76e3cd8	5217	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5218	if (ret == 0) {
cparata	4:77faf76e3cd8	5219	reg.fifo_compr_rt_en = val;
cparata	4:77faf76e3cd8	5220	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5221	}
cparata	4:77faf76e3cd8	5222	return ret;
cparata	0:6d69e896ce38	5223	}
cparata	0:6d69e896ce38	5224
cparata	0:6d69e896ce38	5225	/**
cparata	0:6d69e896ce38	5226	* @brief Enables/Disables compression algorithm runtime. [get]
cparata	0:6d69e896ce38	5227	*
cparata	0:6d69e896ce38	5228	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5229	* @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5230	*
cparata	0:6d69e896ce38	5231	*/
cparata	0:6d69e896ce38	5232	int32_t lsm6dso_compression_algo_real_time_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5233	uint8_t *val)
cparata	0:6d69e896ce38	5234	{
cparata	4:77faf76e3cd8	5235	lsm6dso_fifo_ctrl2_t reg;
cparata	4:77faf76e3cd8	5236	int32_t ret;
cparata	4:77faf76e3cd8	5237
cparata	4:77faf76e3cd8	5238	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5239	*val = reg.fifo_compr_rt_en;
cparata	4:77faf76e3cd8	5240
cparata	4:77faf76e3cd8	5241	return ret;
cparata	0:6d69e896ce38	5242	}
cparata	0:6d69e896ce38	5243
cparata	0:6d69e896ce38	5244	/**
cparata	0:6d69e896ce38	5245	* @brief Sensing chain FIFO stop values memorization at
cparata	0:6d69e896ce38	5246	* threshold level.[set]
cparata	0:6d69e896ce38	5247	*
cparata	0:6d69e896ce38	5248	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5249	* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5250	*
cparata	0:6d69e896ce38	5251	*/
cparata	0:6d69e896ce38	5252	int32_t lsm6dso_fifo_stop_on_wtm_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5253	{
cparata	4:77faf76e3cd8	5254	lsm6dso_fifo_ctrl2_t reg;
cparata	4:77faf76e3cd8	5255	int32_t ret;
cparata	4:77faf76e3cd8	5256
cparata	4:77faf76e3cd8	5257	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5258	if (ret == 0) {
cparata	4:77faf76e3cd8	5259	reg.stop_on_wtm = val;
cparata	4:77faf76e3cd8	5260	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5261	}
cparata	4:77faf76e3cd8	5262	return ret;
cparata	0:6d69e896ce38	5263	}
cparata	0:6d69e896ce38	5264
cparata	0:6d69e896ce38	5265	/**
cparata	0:6d69e896ce38	5266	* @brief Sensing chain FIFO stop values memorization at
cparata	0:6d69e896ce38	5267	* threshold level.[get]
cparata	0:6d69e896ce38	5268	*
cparata	0:6d69e896ce38	5269	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5270	* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5271	*
cparata	0:6d69e896ce38	5272	*/
cparata	0:6d69e896ce38	5273	int32_t lsm6dso_fifo_stop_on_wtm_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5274	{
cparata	4:77faf76e3cd8	5275	lsm6dso_fifo_ctrl2_t reg;
cparata	4:77faf76e3cd8	5276	int32_t ret;
cparata	4:77faf76e3cd8	5277
cparata	4:77faf76e3cd8	5278	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5279	*val = reg.stop_on_wtm;
cparata	4:77faf76e3cd8	5280
cparata	4:77faf76e3cd8	5281	return ret;
cparata	0:6d69e896ce38	5282	}
cparata	0:6d69e896ce38	5283
cparata	0:6d69e896ce38	5284	/**
cparata	0:6d69e896ce38	5285	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5286	* for accelerometer data.[set]
cparata	0:6d69e896ce38	5287	*
cparata	0:6d69e896ce38	5288	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5289	* @param val change the values of bdr_xl in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5290	*
cparata	0:6d69e896ce38	5291	*/
cparata	0:6d69e896ce38	5292	int32_t lsm6dso_fifo_xl_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_xl_t val)
cparata	0:6d69e896ce38	5293	{
cparata	4:77faf76e3cd8	5294	lsm6dso_fifo_ctrl3_t reg;
cparata	4:77faf76e3cd8	5295	int32_t ret;
cparata	4:77faf76e3cd8	5296
cparata	4:77faf76e3cd8	5297	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5298	if (ret == 0) {
cparata	4:77faf76e3cd8	5299	reg.bdr_xl = (uint8_t)val;
cparata	4:77faf76e3cd8	5300	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5301	}
cparata	4:77faf76e3cd8	5302	return ret;
cparata	0:6d69e896ce38	5303	}
cparata	0:6d69e896ce38	5304
cparata	0:6d69e896ce38	5305	/**
cparata	0:6d69e896ce38	5306	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5307	* for accelerometer data.[get]
cparata	0:6d69e896ce38	5308	*
cparata	0:6d69e896ce38	5309	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5310	* @param val Get the values of bdr_xl in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5311	*
cparata	0:6d69e896ce38	5312	*/
cparata	0:6d69e896ce38	5313	int32_t lsm6dso_fifo_xl_batch_get(lsm6dso_ctx_t ctx, lsm6dso_bdr_xl_t val)
cparata	0:6d69e896ce38	5314	{
cparata	4:77faf76e3cd8	5315	lsm6dso_fifo_ctrl3_t reg;
cparata	4:77faf76e3cd8	5316	int32_t ret;
cparata	4:77faf76e3cd8	5317
cparata	4:77faf76e3cd8	5318	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5319	switch (reg.bdr_xl) {
cparata	4:77faf76e3cd8	5320	case LSM6DSO_XL_NOT_BATCHED:
cparata	4:77faf76e3cd8	5321	*val = LSM6DSO_XL_NOT_BATCHED;
cparata	4:77faf76e3cd8	5322	break;
cparata	4:77faf76e3cd8	5323	case LSM6DSO_XL_BATCHED_AT_12Hz5:
cparata	4:77faf76e3cd8	5324	*val = LSM6DSO_XL_BATCHED_AT_12Hz5;
cparata	4:77faf76e3cd8	5325	break;
cparata	4:77faf76e3cd8	5326	case LSM6DSO_XL_BATCHED_AT_26Hz:
cparata	4:77faf76e3cd8	5327	*val = LSM6DSO_XL_BATCHED_AT_26Hz;
cparata	4:77faf76e3cd8	5328	break;
cparata	4:77faf76e3cd8	5329	case LSM6DSO_XL_BATCHED_AT_52Hz:
cparata	4:77faf76e3cd8	5330	*val = LSM6DSO_XL_BATCHED_AT_52Hz;
cparata	4:77faf76e3cd8	5331	break;
cparata	4:77faf76e3cd8	5332	case LSM6DSO_XL_BATCHED_AT_104Hz:
cparata	4:77faf76e3cd8	5333	*val = LSM6DSO_XL_BATCHED_AT_104Hz;
cparata	4:77faf76e3cd8	5334	break;
cparata	4:77faf76e3cd8	5335	case LSM6DSO_XL_BATCHED_AT_208Hz:
cparata	4:77faf76e3cd8	5336	*val = LSM6DSO_XL_BATCHED_AT_208Hz;
cparata	4:77faf76e3cd8	5337	break;
cparata	4:77faf76e3cd8	5338	case LSM6DSO_XL_BATCHED_AT_417Hz:
cparata	4:77faf76e3cd8	5339	*val = LSM6DSO_XL_BATCHED_AT_417Hz;
cparata	4:77faf76e3cd8	5340	break;
cparata	4:77faf76e3cd8	5341	case LSM6DSO_XL_BATCHED_AT_833Hz:
cparata	4:77faf76e3cd8	5342	*val = LSM6DSO_XL_BATCHED_AT_833Hz;
cparata	4:77faf76e3cd8	5343	break;
cparata	4:77faf76e3cd8	5344	case LSM6DSO_XL_BATCHED_AT_1667Hz:
cparata	4:77faf76e3cd8	5345	*val = LSM6DSO_XL_BATCHED_AT_1667Hz;
cparata	4:77faf76e3cd8	5346	break;
cparata	4:77faf76e3cd8	5347	case LSM6DSO_XL_BATCHED_AT_3333Hz:
cparata	4:77faf76e3cd8	5348	*val = LSM6DSO_XL_BATCHED_AT_3333Hz;
cparata	4:77faf76e3cd8	5349	break;
cparata	4:77faf76e3cd8	5350	case LSM6DSO_XL_BATCHED_AT_6667Hz:
cparata	4:77faf76e3cd8	5351	*val = LSM6DSO_XL_BATCHED_AT_6667Hz;
cparata	4:77faf76e3cd8	5352	break;
cparata	4:77faf76e3cd8	5353	case LSM6DSO_XL_BATCHED_AT_6Hz5:
cparata	4:77faf76e3cd8	5354	*val = LSM6DSO_XL_BATCHED_AT_6Hz5;
cparata	4:77faf76e3cd8	5355	break;
cparata	4:77faf76e3cd8	5356	default:
cparata	4:77faf76e3cd8	5357	*val = LSM6DSO_XL_NOT_BATCHED;
cparata	4:77faf76e3cd8	5358	break;
cparata	4:77faf76e3cd8	5359	}
cparata	4:77faf76e3cd8	5360
cparata	4:77faf76e3cd8	5361	return ret;
cparata	0:6d69e896ce38	5362	}
cparata	0:6d69e896ce38	5363
cparata	0:6d69e896ce38	5364	/**
cparata	0:6d69e896ce38	5365	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5366	* for gyroscope data.[set]
cparata	0:6d69e896ce38	5367	*
cparata	0:6d69e896ce38	5368	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5369	* @param val change the values of bdr_gy in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5370	*
cparata	0:6d69e896ce38	5371	*/
cparata	0:6d69e896ce38	5372	int32_t lsm6dso_fifo_gy_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_gy_t val)
cparata	0:6d69e896ce38	5373	{
cparata	4:77faf76e3cd8	5374	lsm6dso_fifo_ctrl3_t reg;
cparata	4:77faf76e3cd8	5375	int32_t ret;
cparata	4:77faf76e3cd8	5376
cparata	4:77faf76e3cd8	5377	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5378	if (ret == 0) {
cparata	4:77faf76e3cd8	5379	reg.bdr_gy = (uint8_t)val;
cparata	4:77faf76e3cd8	5380	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5381	}
cparata	4:77faf76e3cd8	5382	return ret;
cparata	0:6d69e896ce38	5383	}
cparata	0:6d69e896ce38	5384
cparata	0:6d69e896ce38	5385	/**
cparata	0:6d69e896ce38	5386	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5387	* for gyroscope data.[get]
cparata	0:6d69e896ce38	5388	*
cparata	0:6d69e896ce38	5389	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5390	* @param val Get the values of bdr_gy in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5391	*
cparata	0:6d69e896ce38	5392	*/
cparata	0:6d69e896ce38	5393	int32_t lsm6dso_fifo_gy_batch_get(lsm6dso_ctx_t ctx, lsm6dso_bdr_gy_t val)
cparata	0:6d69e896ce38	5394	{
cparata	4:77faf76e3cd8	5395	lsm6dso_fifo_ctrl3_t reg;
cparata	4:77faf76e3cd8	5396	int32_t ret;
cparata	4:77faf76e3cd8	5397
cparata	4:77faf76e3cd8	5398	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5399	switch (reg.bdr_gy) {
cparata	4:77faf76e3cd8	5400	case LSM6DSO_GY_NOT_BATCHED:
cparata	4:77faf76e3cd8	5401	*val = LSM6DSO_GY_NOT_BATCHED;
cparata	4:77faf76e3cd8	5402	break;
cparata	4:77faf76e3cd8	5403	case LSM6DSO_GY_BATCHED_AT_12Hz5:
cparata	4:77faf76e3cd8	5404	*val = LSM6DSO_GY_BATCHED_AT_12Hz5;
cparata	4:77faf76e3cd8	5405	break;
cparata	4:77faf76e3cd8	5406	case LSM6DSO_GY_BATCHED_AT_26Hz:
cparata	4:77faf76e3cd8	5407	*val = LSM6DSO_GY_BATCHED_AT_26Hz;
cparata	4:77faf76e3cd8	5408	break;
cparata	4:77faf76e3cd8	5409	case LSM6DSO_GY_BATCHED_AT_52Hz:
cparata	4:77faf76e3cd8	5410	*val = LSM6DSO_GY_BATCHED_AT_52Hz;
cparata	4:77faf76e3cd8	5411	break;
cparata	4:77faf76e3cd8	5412	case LSM6DSO_GY_BATCHED_AT_104Hz:
cparata	4:77faf76e3cd8	5413	*val = LSM6DSO_GY_BATCHED_AT_104Hz;
cparata	4:77faf76e3cd8	5414	break;
cparata	4:77faf76e3cd8	5415	case LSM6DSO_GY_BATCHED_AT_208Hz:
cparata	4:77faf76e3cd8	5416	*val = LSM6DSO_GY_BATCHED_AT_208Hz;
cparata	4:77faf76e3cd8	5417	break;
cparata	4:77faf76e3cd8	5418	case LSM6DSO_GY_BATCHED_AT_417Hz:
cparata	4:77faf76e3cd8	5419	*val = LSM6DSO_GY_BATCHED_AT_417Hz;
cparata	4:77faf76e3cd8	5420	break;
cparata	4:77faf76e3cd8	5421	case LSM6DSO_GY_BATCHED_AT_833Hz:
cparata	4:77faf76e3cd8	5422	*val = LSM6DSO_GY_BATCHED_AT_833Hz;
cparata	4:77faf76e3cd8	5423	break;
cparata	4:77faf76e3cd8	5424	case LSM6DSO_GY_BATCHED_AT_1667Hz:
cparata	4:77faf76e3cd8	5425	*val = LSM6DSO_GY_BATCHED_AT_1667Hz;
cparata	4:77faf76e3cd8	5426	break;
cparata	4:77faf76e3cd8	5427	case LSM6DSO_GY_BATCHED_AT_3333Hz:
cparata	4:77faf76e3cd8	5428	*val = LSM6DSO_GY_BATCHED_AT_3333Hz;
cparata	4:77faf76e3cd8	5429	break;
cparata	4:77faf76e3cd8	5430	case LSM6DSO_GY_BATCHED_AT_6667Hz:
cparata	4:77faf76e3cd8	5431	*val = LSM6DSO_GY_BATCHED_AT_6667Hz;
cparata	4:77faf76e3cd8	5432	break;
cparata	4:77faf76e3cd8	5433	case LSM6DSO_GY_BATCHED_AT_6Hz5:
cparata	4:77faf76e3cd8	5434	*val = LSM6DSO_GY_BATCHED_AT_6Hz5;
cparata	4:77faf76e3cd8	5435	break;
cparata	4:77faf76e3cd8	5436	default:
cparata	4:77faf76e3cd8	5437	*val = LSM6DSO_GY_NOT_BATCHED;
cparata	4:77faf76e3cd8	5438	break;
cparata	4:77faf76e3cd8	5439	}
cparata	4:77faf76e3cd8	5440	return ret;
cparata	0:6d69e896ce38	5441	}
cparata	0:6d69e896ce38	5442
cparata	0:6d69e896ce38	5443	/**
cparata	0:6d69e896ce38	5444	* @brief FIFO mode selection.[set]
cparata	0:6d69e896ce38	5445	*
cparata	0:6d69e896ce38	5446	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5447	* @param val change the values of fifo_mode in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5448	*
cparata	0:6d69e896ce38	5449	*/
cparata	0:6d69e896ce38	5450	int32_t lsm6dso_fifo_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_fifo_mode_t val)
cparata	0:6d69e896ce38	5451	{
cparata	4:77faf76e3cd8	5452	lsm6dso_fifo_ctrl4_t reg;
cparata	4:77faf76e3cd8	5453	int32_t ret;
cparata	4:77faf76e3cd8	5454
cparata	4:77faf76e3cd8	5455	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5456	if (ret == 0) {
cparata	4:77faf76e3cd8	5457	reg.fifo_mode = (uint8_t)val;
cparata	4:77faf76e3cd8	5458	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5459	}
cparata	4:77faf76e3cd8	5460	return ret;
cparata	0:6d69e896ce38	5461	}
cparata	0:6d69e896ce38	5462
cparata	0:6d69e896ce38	5463	/**
cparata	0:6d69e896ce38	5464	* @brief FIFO mode selection.[get]
cparata	0:6d69e896ce38	5465	*
cparata	0:6d69e896ce38	5466	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5467	* @param val Get the values of fifo_mode in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5468	*
cparata	0:6d69e896ce38	5469	*/
cparata	0:6d69e896ce38	5470	int32_t lsm6dso_fifo_mode_get(lsm6dso_ctx_t ctx, lsm6dso_fifo_mode_t val)
cparata	0:6d69e896ce38	5471	{
cparata	4:77faf76e3cd8	5472	lsm6dso_fifo_ctrl4_t reg;
cparata	4:77faf76e3cd8	5473	int32_t ret;
cparata	4:77faf76e3cd8	5474
cparata	4:77faf76e3cd8	5475	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5476
cparata	4:77faf76e3cd8	5477	switch (reg.fifo_mode) {
cparata	4:77faf76e3cd8	5478	case LSM6DSO_BYPASS_MODE:
cparata	4:77faf76e3cd8	5479	*val = LSM6DSO_BYPASS_MODE;
cparata	4:77faf76e3cd8	5480	break;
cparata	4:77faf76e3cd8	5481	case LSM6DSO_FIFO_MODE:
cparata	4:77faf76e3cd8	5482	*val = LSM6DSO_FIFO_MODE;
cparata	4:77faf76e3cd8	5483	break;
cparata	4:77faf76e3cd8	5484	case LSM6DSO_STREAM_TO_FIFO_MODE:
cparata	4:77faf76e3cd8	5485	*val = LSM6DSO_STREAM_TO_FIFO_MODE;
cparata	4:77faf76e3cd8	5486	break;
cparata	4:77faf76e3cd8	5487	case LSM6DSO_BYPASS_TO_STREAM_MODE:
cparata	4:77faf76e3cd8	5488	*val = LSM6DSO_BYPASS_TO_STREAM_MODE;
cparata	4:77faf76e3cd8	5489	break;
cparata	4:77faf76e3cd8	5490	case LSM6DSO_STREAM_MODE:
cparata	4:77faf76e3cd8	5491	*val = LSM6DSO_STREAM_MODE;
cparata	4:77faf76e3cd8	5492	break;
cparata	4:77faf76e3cd8	5493	case LSM6DSO_BYPASS_TO_FIFO_MODE:
cparata	4:77faf76e3cd8	5494	*val = LSM6DSO_BYPASS_TO_FIFO_MODE;
cparata	4:77faf76e3cd8	5495	break;
cparata	4:77faf76e3cd8	5496	default:
cparata	4:77faf76e3cd8	5497	*val = LSM6DSO_BYPASS_MODE;
cparata	4:77faf76e3cd8	5498	break;
cparata	4:77faf76e3cd8	5499	}
cparata	4:77faf76e3cd8	5500	return ret;
cparata	0:6d69e896ce38	5501	}
cparata	0:6d69e896ce38	5502
cparata	0:6d69e896ce38	5503	/**
cparata	0:6d69e896ce38	5504	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5505	* for temperature data.[set]
cparata	0:6d69e896ce38	5506	*
cparata	0:6d69e896ce38	5507	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5508	* @param val change the values of odr_t_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5509	*
cparata	0:6d69e896ce38	5510	*/
cparata	0:6d69e896ce38	5511	int32_t lsm6dso_fifo_temp_batch_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5512	lsm6dso_odr_t_batch_t val)
cparata	0:6d69e896ce38	5513	{
cparata	4:77faf76e3cd8	5514	lsm6dso_fifo_ctrl4_t reg;
cparata	4:77faf76e3cd8	5515	int32_t ret;
cparata	4:77faf76e3cd8	5516
cparata	4:77faf76e3cd8	5517	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5518	if (ret == 0) {
cparata	4:77faf76e3cd8	5519	reg.odr_t_batch = (uint8_t)val;
cparata	4:77faf76e3cd8	5520	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5521	}
cparata	4:77faf76e3cd8	5522	return ret;
cparata	0:6d69e896ce38	5523	}
cparata	0:6d69e896ce38	5524
cparata	0:6d69e896ce38	5525	/**
cparata	0:6d69e896ce38	5526	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5527	* for temperature data.[get]
cparata	0:6d69e896ce38	5528	*
cparata	0:6d69e896ce38	5529	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5530	* @param val Get the values of odr_t_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5531	*
cparata	0:6d69e896ce38	5532	*/
cparata	0:6d69e896ce38	5533	int32_t lsm6dso_fifo_temp_batch_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5534	lsm6dso_odr_t_batch_t *val)
cparata	0:6d69e896ce38	5535	{
cparata	4:77faf76e3cd8	5536	lsm6dso_fifo_ctrl4_t reg;
cparata	4:77faf76e3cd8	5537	int32_t ret;
cparata	4:77faf76e3cd8	5538
cparata	4:77faf76e3cd8	5539	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5540
cparata	4:77faf76e3cd8	5541	switch (reg.odr_t_batch) {
cparata	4:77faf76e3cd8	5542	case LSM6DSO_TEMP_NOT_BATCHED:
cparata	4:77faf76e3cd8	5543	*val = LSM6DSO_TEMP_NOT_BATCHED;
cparata	4:77faf76e3cd8	5544	break;
cparata	4:77faf76e3cd8	5545	case LSM6DSO_TEMP_BATCHED_AT_1Hz6:
cparata	4:77faf76e3cd8	5546	*val = LSM6DSO_TEMP_BATCHED_AT_1Hz6;
cparata	4:77faf76e3cd8	5547	break;
cparata	4:77faf76e3cd8	5548	case LSM6DSO_TEMP_BATCHED_AT_12Hz5:
cparata	4:77faf76e3cd8	5549	*val = LSM6DSO_TEMP_BATCHED_AT_12Hz5;
cparata	4:77faf76e3cd8	5550	break;
cparata	4:77faf76e3cd8	5551	case LSM6DSO_TEMP_BATCHED_AT_52Hz:
cparata	4:77faf76e3cd8	5552	*val = LSM6DSO_TEMP_BATCHED_AT_52Hz;
cparata	4:77faf76e3cd8	5553	break;
cparata	4:77faf76e3cd8	5554	default:
cparata	4:77faf76e3cd8	5555	*val = LSM6DSO_TEMP_NOT_BATCHED;
cparata	4:77faf76e3cd8	5556	break;
cparata	4:77faf76e3cd8	5557	}
cparata	4:77faf76e3cd8	5558	return ret;
cparata	0:6d69e896ce38	5559	}
cparata	0:6d69e896ce38	5560
cparata	0:6d69e896ce38	5561	/**
cparata	0:6d69e896ce38	5562	* @brief Selects decimation for timestamp batching in FIFO.
cparata	0:6d69e896ce38	5563	* Writing rate will be the maximum rate between XL and
cparata	0:6d69e896ce38	5564	* GYRO BDR divided by decimation decoder.[set]
cparata	0:6d69e896ce38	5565	*
cparata	0:6d69e896ce38	5566	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5567	* @param val change the values of odr_ts_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5568	*
cparata	0:6d69e896ce38	5569	*/
cparata	0:6d69e896ce38	5570	int32_t lsm6dso_fifo_timestamp_decimation_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5571	lsm6dso_odr_ts_batch_t val)
cparata	0:6d69e896ce38	5572	{
cparata	4:77faf76e3cd8	5573	lsm6dso_fifo_ctrl4_t reg;
cparata	4:77faf76e3cd8	5574	int32_t ret;
cparata	4:77faf76e3cd8	5575
cparata	4:77faf76e3cd8	5576	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5577	if (ret == 0) {
cparata	4:77faf76e3cd8	5578	reg.odr_ts_batch = (uint8_t)val;
cparata	4:77faf76e3cd8	5579	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5580	}
cparata	4:77faf76e3cd8	5581	return ret;
cparata	0:6d69e896ce38	5582	}
cparata	0:6d69e896ce38	5583
cparata	0:6d69e896ce38	5584	/**
cparata	0:6d69e896ce38	5585	* @brief Selects decimation for timestamp batching in FIFO.
cparata	0:6d69e896ce38	5586	* Writing rate will be the maximum rate between XL and
cparata	0:6d69e896ce38	5587	* GYRO BDR divided by decimation decoder.[get]
cparata	0:6d69e896ce38	5588	*
cparata	0:6d69e896ce38	5589	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5590	* @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5591	*
cparata	0:6d69e896ce38	5592	*/
cparata	0:6d69e896ce38	5593	int32_t lsm6dso_fifo_timestamp_decimation_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5594	lsm6dso_odr_ts_batch_t *val)
cparata	0:6d69e896ce38	5595	{
cparata	4:77faf76e3cd8	5596	lsm6dso_fifo_ctrl4_t reg;
cparata	4:77faf76e3cd8	5597	int32_t ret;
cparata	4:77faf76e3cd8	5598
cparata	4:77faf76e3cd8	5599	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5600	switch (reg.odr_ts_batch) {
cparata	4:77faf76e3cd8	5601	case LSM6DSO_NO_DECIMATION:
cparata	4:77faf76e3cd8	5602	*val = LSM6DSO_NO_DECIMATION;
cparata	4:77faf76e3cd8	5603	break;
cparata	4:77faf76e3cd8	5604	case LSM6DSO_DEC_1:
cparata	4:77faf76e3cd8	5605	*val = LSM6DSO_DEC_1;
cparata	4:77faf76e3cd8	5606	break;
cparata	4:77faf76e3cd8	5607	case LSM6DSO_DEC_8:
cparata	4:77faf76e3cd8	5608	*val = LSM6DSO_DEC_8;
cparata	4:77faf76e3cd8	5609	break;
cparata	4:77faf76e3cd8	5610	case LSM6DSO_DEC_32:
cparata	4:77faf76e3cd8	5611	*val = LSM6DSO_DEC_32;
cparata	4:77faf76e3cd8	5612	break;
cparata	4:77faf76e3cd8	5613	default:
cparata	4:77faf76e3cd8	5614	*val = LSM6DSO_NO_DECIMATION;
cparata	4:77faf76e3cd8	5615	break;
cparata	4:77faf76e3cd8	5616	}
cparata	4:77faf76e3cd8	5617	return ret;
cparata	0:6d69e896ce38	5618	}
cparata	0:6d69e896ce38	5619
cparata	0:6d69e896ce38	5620	/**
cparata	0:6d69e896ce38	5621	* @brief Selects the trigger for the internal counter of batching events
cparata	0:6d69e896ce38	5622	* between XL and gyro.[set]
cparata	0:6d69e896ce38	5623	*
cparata	0:6d69e896ce38	5624	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5625	* @param val change the values of trig_counter_bdr
cparata	0:6d69e896ce38	5626	* in reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5627	*
cparata	0:6d69e896ce38	5628	*/
cparata	0:6d69e896ce38	5629	int32_t lsm6dso_fifo_cnt_event_batch_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5630	lsm6dso_trig_counter_bdr_t val)
cparata	0:6d69e896ce38	5631	{
cparata	4:77faf76e3cd8	5632	lsm6dso_counter_bdr_reg1_t reg;
cparata	4:77faf76e3cd8	5633	int32_t ret;
cparata	4:77faf76e3cd8	5634
cparata	4:77faf76e3cd8	5635	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5636	if (ret == 0) {
cparata	4:77faf76e3cd8	5637	reg.trig_counter_bdr = (uint8_t)val;
cparata	4:77faf76e3cd8	5638	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5639	}
cparata	4:77faf76e3cd8	5640	return ret;
cparata	0:6d69e896ce38	5641	}
cparata	0:6d69e896ce38	5642
cparata	0:6d69e896ce38	5643	/**
cparata	0:6d69e896ce38	5644	* @brief Selects the trigger for the internal counter of batching events
cparata	0:6d69e896ce38	5645	* between XL and gyro.[get]
cparata	0:6d69e896ce38	5646	*
cparata	0:6d69e896ce38	5647	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5648	* @param val Get the values of trig_counter_bdr
cparata	0:6d69e896ce38	5649	* in reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5650	*
cparata	0:6d69e896ce38	5651	*/
cparata	0:6d69e896ce38	5652	int32_t lsm6dso_fifo_cnt_event_batch_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5653	lsm6dso_trig_counter_bdr_t *val)
cparata	0:6d69e896ce38	5654	{
cparata	4:77faf76e3cd8	5655	lsm6dso_counter_bdr_reg1_t reg;
cparata	4:77faf76e3cd8	5656	int32_t ret;
cparata	4:77faf76e3cd8	5657
cparata	4:77faf76e3cd8	5658	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5659	switch (reg.trig_counter_bdr) {
cparata	4:77faf76e3cd8	5660	case LSM6DSO_XL_BATCH_EVENT:
cparata	4:77faf76e3cd8	5661	*val = LSM6DSO_XL_BATCH_EVENT;
cparata	4:77faf76e3cd8	5662	break;
cparata	4:77faf76e3cd8	5663	case LSM6DSO_GYRO_BATCH_EVENT:
cparata	4:77faf76e3cd8	5664	*val = LSM6DSO_GYRO_BATCH_EVENT;
cparata	4:77faf76e3cd8	5665	break;
cparata	4:77faf76e3cd8	5666	default:
cparata	4:77faf76e3cd8	5667	*val = LSM6DSO_XL_BATCH_EVENT;
cparata	4:77faf76e3cd8	5668	break;
cparata	4:77faf76e3cd8	5669	}
cparata	4:77faf76e3cd8	5670	return ret;
cparata	0:6d69e896ce38	5671	}
cparata	0:6d69e896ce38	5672
cparata	0:6d69e896ce38	5673	/**
cparata	0:6d69e896ce38	5674	* @brief Resets the internal counter of batching vents for a single sensor.
cparata	0:6d69e896ce38	5675	* This bit is automatically reset to zero if it was set to ‘1’.[set]
cparata	0:6d69e896ce38	5676	*
cparata	0:6d69e896ce38	5677	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5678	* @param val change the values of rst_counter_bdr in
cparata	0:6d69e896ce38	5679	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5680	*
cparata	0:6d69e896ce38	5681	*/
cparata	0:6d69e896ce38	5682	int32_t lsm6dso_rst_batch_counter_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5683	{
cparata	4:77faf76e3cd8	5684	lsm6dso_counter_bdr_reg1_t reg;
cparata	4:77faf76e3cd8	5685	int32_t ret;
cparata	4:77faf76e3cd8	5686
cparata	4:77faf76e3cd8	5687	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5688	if (ret == 0) {
cparata	4:77faf76e3cd8	5689	reg.rst_counter_bdr = val;
cparata	4:77faf76e3cd8	5690	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5691	}
cparata	4:77faf76e3cd8	5692	return ret;
cparata	0:6d69e896ce38	5693	}
cparata	0:6d69e896ce38	5694
cparata	0:6d69e896ce38	5695	/**
cparata	0:6d69e896ce38	5696	* @brief Resets the internal counter of batching events for a single sensor.
cparata	0:6d69e896ce38	5697	* This bit is automatically reset to zero if it was set to ‘1’.[get]
cparata	0:6d69e896ce38	5698	*
cparata	0:6d69e896ce38	5699	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5700	* @param val change the values of rst_counter_bdr in
cparata	0:6d69e896ce38	5701	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5702	*
cparata	0:6d69e896ce38	5703	*/
cparata	0:6d69e896ce38	5704	int32_t lsm6dso_rst_batch_counter_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5705	{
cparata	4:77faf76e3cd8	5706	lsm6dso_counter_bdr_reg1_t reg;
cparata	4:77faf76e3cd8	5707	int32_t ret;
cparata	4:77faf76e3cd8	5708
cparata	4:77faf76e3cd8	5709	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5710	*val = reg.rst_counter_bdr;
cparata	4:77faf76e3cd8	5711
cparata	4:77faf76e3cd8	5712	return ret;
cparata	0:6d69e896ce38	5713	}
cparata	0:6d69e896ce38	5714
cparata	0:6d69e896ce38	5715	/**
cparata	0:6d69e896ce38	5716	* @brief Batch data rate counter.[set]
cparata	0:6d69e896ce38	5717	*
cparata	0:6d69e896ce38	5718	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5719	* @param val change the values of cnt_bdr_th in
cparata	0:6d69e896ce38	5720	* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata	0:6d69e896ce38	5721	*
cparata	0:6d69e896ce38	5722	*/
cparata	0:6d69e896ce38	5723	int32_t lsm6dso_batch_counter_threshold_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	0:6d69e896ce38	5724	{
cparata	4:77faf76e3cd8	5725	lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
cparata	4:77faf76e3cd8	5726	lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
cparata	4:77faf76e3cd8	5727	int32_t ret;
cparata	4:77faf76e3cd8	5728
cparata	4:77faf76e3cd8	5729	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
cparata	4:77faf76e3cd8	5730	(uint8_t*)&counter_bdr_reg1, 1);
cparata	4:77faf76e3cd8	5731	if (ret == 0) {
cparata	4:77faf76e3cd8	5732	counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
cparata	4:77faf76e3cd8	5733	counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
cparata	4:77faf76e3cd8	5734	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
cparata	4:77faf76e3cd8	5735	(uint8_t*)&counter_bdr_reg1, 1);
cparata	4:77faf76e3cd8	5736	}
cparata	4:77faf76e3cd8	5737	if (ret == 0) {
cparata	4:77faf76e3cd8	5738	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
cparata	4:77faf76e3cd8	5739	(uint8_t*)&counter_bdr_reg2, 1);
cparata	4:77faf76e3cd8	5740	}
cparata	4:77faf76e3cd8	5741	return ret;
cparata	0:6d69e896ce38	5742	}
cparata	0:6d69e896ce38	5743
cparata	0:6d69e896ce38	5744	/**
cparata	0:6d69e896ce38	5745	* @brief Batch data rate counter.[get]
cparata	0:6d69e896ce38	5746	*
cparata	0:6d69e896ce38	5747	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5748	* @param val change the values of cnt_bdr_th in
cparata	0:6d69e896ce38	5749	* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata	0:6d69e896ce38	5750	*
cparata	0:6d69e896ce38	5751	*/
cparata	0:6d69e896ce38	5752	int32_t lsm6dso_batch_counter_threshold_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	0:6d69e896ce38	5753	{
cparata	4:77faf76e3cd8	5754	lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
cparata	4:77faf76e3cd8	5755	lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
cparata	4:77faf76e3cd8	5756	int32_t ret;
cparata	4:77faf76e3cd8	5757
cparata	4:77faf76e3cd8	5758	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
cparata	4:77faf76e3cd8	5759	(uint8_t*)&counter_bdr_reg1, 1);
cparata	4:77faf76e3cd8	5760	if (ret == 0) {
cparata	4:77faf76e3cd8	5761	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
cparata	4:77faf76e3cd8	5762	(uint8_t*)&counter_bdr_reg2, 1);
cparata	4:77faf76e3cd8	5763
cparata	4:77faf76e3cd8	5764	*val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
cparata	4:77faf76e3cd8	5765	+ (uint16_t)counter_bdr_reg2.cnt_bdr_th;
cparata	4:77faf76e3cd8	5766	}
cparata	4:77faf76e3cd8	5767
cparata	4:77faf76e3cd8	5768	return ret;
cparata	0:6d69e896ce38	5769	}
cparata	0:6d69e896ce38	5770
cparata	0:6d69e896ce38	5771	/**
cparata	0:6d69e896ce38	5772	* @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
cparata	0:6d69e896ce38	5773	*
cparata	0:6d69e896ce38	5774	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5775	* @param val change the values of diff_fifo in reg FIFO_STATUS1
cparata	0:6d69e896ce38	5776	*
cparata	0:6d69e896ce38	5777	*/
cparata	0:6d69e896ce38	5778	int32_t lsm6dso_fifo_data_level_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	0:6d69e896ce38	5779	{
cparata	4:77faf76e3cd8	5780	lsm6dso_fifo_status1_t fifo_status1;
cparata	4:77faf76e3cd8	5781	lsm6dso_fifo_status2_t fifo_status2;
cparata	4:77faf76e3cd8	5782	int32_t ret;
cparata	4:77faf76e3cd8	5783
cparata	4:77faf76e3cd8	5784	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1,
cparata	4:77faf76e3cd8	5785	(uint8_t*)&fifo_status1, 1);
cparata	4:77faf76e3cd8	5786	if (ret == 0) {
cparata	4:77faf76e3cd8	5787	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2,
cparata	4:77faf76e3cd8	5788	(uint8_t*)&fifo_status2, 1);
cparata	4:77faf76e3cd8	5789	*val = ((uint16_t)fifo_status2.diff_fifo << 8) +
cparata	4:77faf76e3cd8	5790	(uint16_t)fifo_status1.diff_fifo;
cparata	4:77faf76e3cd8	5791	}
cparata	4:77faf76e3cd8	5792	return ret;
cparata	0:6d69e896ce38	5793	}
cparata	0:6d69e896ce38	5794
cparata	0:6d69e896ce38	5795	/**
cparata	0:6d69e896ce38	5796	* @brief FIFO status.[get]
cparata	0:6d69e896ce38	5797	*
cparata	0:6d69e896ce38	5798	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5799	* @param val registers FIFO_STATUS2
cparata	0:6d69e896ce38	5800	*
cparata	0:6d69e896ce38	5801	*/
cparata	0:6d69e896ce38	5802	int32_t lsm6dso_fifo_status_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5803	lsm6dso_fifo_status2_t *val)
cparata	0:6d69e896ce38	5804	{
cparata	4:77faf76e3cd8	5805	int32_t ret;
cparata	4:77faf76e3cd8	5806	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*) val, 1);
cparata	4:77faf76e3cd8	5807	return ret;
cparata	0:6d69e896ce38	5808	}
cparata	0:6d69e896ce38	5809
cparata	0:6d69e896ce38	5810	/**
cparata	0:6d69e896ce38	5811	* @brief Smart FIFO full status.[get]
cparata	0:6d69e896ce38	5812	*
cparata	0:6d69e896ce38	5813	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5814	* @param val change the values of fifo_full_ia in reg FIFO_STATUS2
cparata	0:6d69e896ce38	5815	*
cparata	0:6d69e896ce38	5816	*/
cparata	0:6d69e896ce38	5817	int32_t lsm6dso_fifo_full_flag_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5818	{
cparata	4:77faf76e3cd8	5819	lsm6dso_fifo_status2_t reg;
cparata	4:77faf76e3cd8	5820	int32_t ret;
cparata	4:77faf76e3cd8	5821
cparata	4:77faf76e3cd8	5822	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5823	*val = reg.fifo_full_ia;
cparata	4:77faf76e3cd8	5824
cparata	4:77faf76e3cd8	5825	return ret;
cparata	0:6d69e896ce38	5826	}
cparata	0:6d69e896ce38	5827
cparata	0:6d69e896ce38	5828	/**
cparata	0:6d69e896ce38	5829	* @brief FIFO overrun status.[get]
cparata	0:6d69e896ce38	5830	*
cparata	0:6d69e896ce38	5831	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5832	* @param val change the values of fifo_over_run_latched in
cparata	0:6d69e896ce38	5833	* reg FIFO_STATUS2
cparata	0:6d69e896ce38	5834	*
cparata	0:6d69e896ce38	5835	*/
cparata	0:6d69e896ce38	5836	int32_t lsm6dso_fifo_ovr_flag_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5837	{
cparata	4:77faf76e3cd8	5838	lsm6dso_fifo_status2_t reg;
cparata	4:77faf76e3cd8	5839	int32_t ret;
cparata	4:77faf76e3cd8	5840
cparata	4:77faf76e3cd8	5841	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5842	*val = reg.fifo_ovr_ia;
cparata	4:77faf76e3cd8	5843
cparata	4:77faf76e3cd8	5844	return ret;
cparata	0:6d69e896ce38	5845	}
cparata	0:6d69e896ce38	5846
cparata	0:6d69e896ce38	5847	/**
cparata	0:6d69e896ce38	5848	* @brief FIFO watermark status.[get]
cparata	0:6d69e896ce38	5849	*
cparata	0:6d69e896ce38	5850	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5851	* @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
cparata	0:6d69e896ce38	5852	*
cparata	0:6d69e896ce38	5853	*/
cparata	0:6d69e896ce38	5854	int32_t lsm6dso_fifo_wtm_flag_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5855	{
cparata	4:77faf76e3cd8	5856	lsm6dso_fifo_status2_t reg;
cparata	4:77faf76e3cd8	5857	int32_t ret;
cparata	4:77faf76e3cd8	5858
cparata	4:77faf76e3cd8	5859	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5860	*val = reg.fifo_wtm_ia;
cparata	4:77faf76e3cd8	5861
cparata	4:77faf76e3cd8	5862	return ret;
cparata	0:6d69e896ce38	5863	}
cparata	0:6d69e896ce38	5864
cparata	0:6d69e896ce38	5865	/**
cparata	0:6d69e896ce38	5866	* @brief Identifies the sensor in FIFO_DATA_OUT.[get]
cparata	0:6d69e896ce38	5867	*
cparata	0:6d69e896ce38	5868	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5869	* @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
cparata	0:6d69e896ce38	5870	*
cparata	0:6d69e896ce38	5871	*/
cparata	0:6d69e896ce38	5872	int32_t lsm6dso_fifo_sensor_tag_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5873	lsm6dso_fifo_tag_t *val)
cparata	0:6d69e896ce38	5874	{
cparata	4:77faf76e3cd8	5875	lsm6dso_fifo_data_out_tag_t reg;
cparata	4:77faf76e3cd8	5876	int32_t ret;
cparata	4:77faf76e3cd8	5877
cparata	4:77faf76e3cd8	5878	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5879	switch (reg.tag_sensor) {
cparata	4:77faf76e3cd8	5880	case LSM6DSO_GYRO_NC_TAG:
cparata	4:77faf76e3cd8	5881	*val = LSM6DSO_GYRO_NC_TAG;
cparata	4:77faf76e3cd8	5882	break;
cparata	4:77faf76e3cd8	5883	case LSM6DSO_XL_NC_TAG:
cparata	4:77faf76e3cd8	5884	*val = LSM6DSO_XL_NC_TAG;
cparata	4:77faf76e3cd8	5885	break;
cparata	4:77faf76e3cd8	5886	case LSM6DSO_TEMPERATURE_TAG:
cparata	4:77faf76e3cd8	5887	*val = LSM6DSO_TEMPERATURE_TAG;
cparata	4:77faf76e3cd8	5888	break;
cparata	4:77faf76e3cd8	5889	case LSM6DSO_CFG_CHANGE_TAG:
cparata	4:77faf76e3cd8	5890	*val = LSM6DSO_CFG_CHANGE_TAG;
cparata	4:77faf76e3cd8	5891	break;
cparata	4:77faf76e3cd8	5892	case LSM6DSO_XL_NC_T_2_TAG:
cparata	4:77faf76e3cd8	5893	*val = LSM6DSO_XL_NC_T_2_TAG;
cparata	4:77faf76e3cd8	5894	break;
cparata	4:77faf76e3cd8	5895	case LSM6DSO_XL_NC_T_1_TAG:
cparata	4:77faf76e3cd8	5896	*val = LSM6DSO_XL_NC_T_1_TAG;
cparata	4:77faf76e3cd8	5897	break;
cparata	4:77faf76e3cd8	5898	case LSM6DSO_XL_2XC_TAG:
cparata	4:77faf76e3cd8	5899	*val = LSM6DSO_XL_2XC_TAG;
cparata	4:77faf76e3cd8	5900	break;
cparata	4:77faf76e3cd8	5901	case LSM6DSO_XL_3XC_TAG:
cparata	4:77faf76e3cd8	5902	*val = LSM6DSO_XL_3XC_TAG;
cparata	4:77faf76e3cd8	5903	break;
cparata	4:77faf76e3cd8	5904	case LSM6DSO_GYRO_NC_T_2_TAG:
cparata	4:77faf76e3cd8	5905	*val = LSM6DSO_GYRO_NC_T_2_TAG;
cparata	4:77faf76e3cd8	5906	break;
cparata	4:77faf76e3cd8	5907	case LSM6DSO_GYRO_NC_T_1_TAG:
cparata	4:77faf76e3cd8	5908	*val = LSM6DSO_GYRO_NC_T_1_TAG;
cparata	4:77faf76e3cd8	5909	break;
cparata	4:77faf76e3cd8	5910	case LSM6DSO_GYRO_2XC_TAG:
cparata	4:77faf76e3cd8	5911	*val = LSM6DSO_GYRO_2XC_TAG;
cparata	4:77faf76e3cd8	5912	break;
cparata	4:77faf76e3cd8	5913	case LSM6DSO_GYRO_3XC_TAG:
cparata	4:77faf76e3cd8	5914	*val = LSM6DSO_GYRO_3XC_TAG;
cparata	4:77faf76e3cd8	5915	break;
cparata	4:77faf76e3cd8	5916	case LSM6DSO_SENSORHUB_SLAVE0_TAG:
cparata	4:77faf76e3cd8	5917	*val = LSM6DSO_SENSORHUB_SLAVE0_TAG;
cparata	4:77faf76e3cd8	5918	break;
cparata	4:77faf76e3cd8	5919	case LSM6DSO_SENSORHUB_SLAVE1_TAG:
cparata	4:77faf76e3cd8	5920	*val = LSM6DSO_SENSORHUB_SLAVE1_TAG;
cparata	4:77faf76e3cd8	5921	break;
cparata	4:77faf76e3cd8	5922	case LSM6DSO_SENSORHUB_SLAVE2_TAG:
cparata	4:77faf76e3cd8	5923	*val = LSM6DSO_SENSORHUB_SLAVE2_TAG;
cparata	4:77faf76e3cd8	5924	break;
cparata	4:77faf76e3cd8	5925	case LSM6DSO_SENSORHUB_SLAVE3_TAG:
cparata	4:77faf76e3cd8	5926	*val = LSM6DSO_SENSORHUB_SLAVE3_TAG;
cparata	4:77faf76e3cd8	5927	break;
cparata	4:77faf76e3cd8	5928	case LSM6DSO_STEP_CPUNTER_TAG:
cparata	4:77faf76e3cd8	5929	*val = LSM6DSO_STEP_CPUNTER_TAG;
cparata	4:77faf76e3cd8	5930	break;
cparata	4:77faf76e3cd8	5931	case LSM6DSO_GAME_ROTATION_TAG:
cparata	4:77faf76e3cd8	5932	*val = LSM6DSO_GAME_ROTATION_TAG;
cparata	4:77faf76e3cd8	5933	break;
cparata	4:77faf76e3cd8	5934	case LSM6DSO_GEOMAG_ROTATION_TAG:
cparata	4:77faf76e3cd8	5935	*val = LSM6DSO_GEOMAG_ROTATION_TAG;
cparata	4:77faf76e3cd8	5936	break;
cparata	4:77faf76e3cd8	5937	case LSM6DSO_ROTATION_TAG:
cparata	4:77faf76e3cd8	5938	*val = LSM6DSO_ROTATION_TAG;
cparata	4:77faf76e3cd8	5939	break;
cparata	4:77faf76e3cd8	5940	case LSM6DSO_SENSORHUB_NACK_TAG:
cparata	4:77faf76e3cd8	5941	*val = LSM6DSO_SENSORHUB_NACK_TAG;
cparata	4:77faf76e3cd8	5942	break;
cparata	4:77faf76e3cd8	5943	default:
cparata	4:77faf76e3cd8	5944	*val = LSM6DSO_GYRO_NC_TAG;
cparata	4:77faf76e3cd8	5945	break;
cparata	4:77faf76e3cd8	5946	}
cparata	4:77faf76e3cd8	5947	return ret;
cparata	0:6d69e896ce38	5948	}
cparata	0:6d69e896ce38	5949
cparata	0:6d69e896ce38	5950	/**
cparata	0:6d69e896ce38	5951	* @brief : Enable FIFO batching of pedometer embedded
cparata	0:6d69e896ce38	5952	* function values.[set]
cparata	0:6d69e896ce38	5953	*
cparata	0:6d69e896ce38	5954	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5955	* @param val change the values of gbias_fifo_en in
cparata	0:6d69e896ce38	5956	* reg LSM6DSO_EMB_FUNC_FIFO_CFG
cparata	0:6d69e896ce38	5957	*
cparata	0:6d69e896ce38	5958	*/
cparata	0:6d69e896ce38	5959	int32_t lsm6dso_fifo_pedo_batch_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5960	{
cparata	4:77faf76e3cd8	5961	lsm6dso_emb_func_fifo_cfg_t reg;
cparata	4:77faf76e3cd8	5962	int32_t ret;
cparata	4:77faf76e3cd8	5963
cparata	4:77faf76e3cd8	5964	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	5965	if (ret == 0) {
cparata	4:77faf76e3cd8	5966	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5967	}
cparata	4:77faf76e3cd8	5968	if (ret == 0) {
cparata	4:77faf76e3cd8	5969	reg.pedo_fifo_en = val;
cparata	4:77faf76e3cd8	5970	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
cparata	4:77faf76e3cd8	5971	(uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5972	}
cparata	4:77faf76e3cd8	5973	if (ret == 0) {
cparata	4:77faf76e3cd8	5974	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	5975	}
cparata	4:77faf76e3cd8	5976	return ret;
cparata	0:6d69e896ce38	5977	}
cparata	0:6d69e896ce38	5978
cparata	0:6d69e896ce38	5979	/**
cparata	0:6d69e896ce38	5980	* @brief Enable FIFO batching of pedometer embedded function values.[get]
cparata	0:6d69e896ce38	5981	*
cparata	0:6d69e896ce38	5982	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5983	* @param val change the values of pedo_fifo_en in
cparata	0:6d69e896ce38	5984	* reg LSM6DSO_EMB_FUNC_FIFO_CFG
cparata	0:6d69e896ce38	5985	*
cparata	0:6d69e896ce38	5986	*/
cparata	0:6d69e896ce38	5987	int32_t lsm6dso_fifo_pedo_batch_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5988	{
cparata	4:77faf76e3cd8	5989	lsm6dso_emb_func_fifo_cfg_t reg;
cparata	4:77faf76e3cd8	5990	int32_t ret;
cparata	4:77faf76e3cd8	5991
cparata	4:77faf76e3cd8	5992	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	5993	if (ret == 0) {
cparata	4:77faf76e3cd8	5994	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	5995	}
cparata	4:77faf76e3cd8	5996	if (ret == 0) {
cparata	4:77faf76e3cd8	5997	*val = reg.pedo_fifo_en;
cparata	4:77faf76e3cd8	5998	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	5999	}
cparata	4:77faf76e3cd8	6000	return ret;
cparata	0:6d69e896ce38	6001	}
cparata	0:6d69e896ce38	6002
cparata	0:6d69e896ce38	6003	/**
cparata	0:6d69e896ce38	6004	* @brief Enable FIFO batching data of first slave.[set]
cparata	0:6d69e896ce38	6005	*
cparata	0:6d69e896ce38	6006	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6007	* @param val change the values of batch_ext_sens_0_en in
cparata	0:6d69e896ce38	6008	* reg SLV0_CONFIG
cparata	0:6d69e896ce38	6009	*
cparata	0:6d69e896ce38	6010	*/
cparata	0:6d69e896ce38	6011	int32_t lsm6dso_sh_batch_slave_0_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6012	{
cparata	4:77faf76e3cd8	6013	lsm6dso_slv0_config_t reg;
cparata	4:77faf76e3cd8	6014	int32_t ret;
cparata	4:77faf76e3cd8	6015
cparata	4:77faf76e3cd8	6016	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	6017	if (ret == 0) {
cparata	4:77faf76e3cd8	6018	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6019	}
cparata	4:77faf76e3cd8	6020	if (ret == 0) {
cparata	4:77faf76e3cd8	6021	reg.batch_ext_sens_0_en = val;
cparata	4:77faf76e3cd8	6022	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6023	}
cparata	4:77faf76e3cd8	6024	if (ret == 0) {
cparata	4:77faf76e3cd8	6025	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6026	}
cparata	4:77faf76e3cd8	6027	return ret;
cparata	0:6d69e896ce38	6028	}
cparata	0:6d69e896ce38	6029
cparata	0:6d69e896ce38	6030	/**
cparata	0:6d69e896ce38	6031	* @brief Enable FIFO batching data of first slave.[get]
cparata	0:6d69e896ce38	6032	*
cparata	0:6d69e896ce38	6033	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6034	* @param val change the values of batch_ext_sens_0_en in
cparata	0:6d69e896ce38	6035	* reg SLV0_CONFIG
cparata	0:6d69e896ce38	6036	*
cparata	0:6d69e896ce38	6037	*/
cparata	0:6d69e896ce38	6038	int32_t lsm6dso_sh_batch_slave_0_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6039	{
cparata	4:77faf76e3cd8	6040	lsm6dso_slv0_config_t reg;
cparata	4:77faf76e3cd8	6041	int32_t ret;
cparata	4:77faf76e3cd8	6042
cparata	4:77faf76e3cd8	6043	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	6044	if (ret == 0) {
cparata	4:77faf76e3cd8	6045	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6046	}
cparata	4:77faf76e3cd8	6047	if (ret == 0) {
cparata	4:77faf76e3cd8	6048	*val = reg.batch_ext_sens_0_en;
cparata	4:77faf76e3cd8	6049	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6050	}
cparata	4:77faf76e3cd8	6051	return ret;
cparata	0:6d69e896ce38	6052	}
cparata	0:6d69e896ce38	6053
cparata	0:6d69e896ce38	6054	/**
cparata	0:6d69e896ce38	6055	* @brief Enable FIFO batching data of second slave.[set]
cparata	0:6d69e896ce38	6056	*
cparata	0:6d69e896ce38	6057	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6058	* @param val change the values of batch_ext_sens_1_en in
cparata	0:6d69e896ce38	6059	* reg SLV1_CONFIG
cparata	0:6d69e896ce38	6060	*
cparata	0:6d69e896ce38	6061	*/
cparata	0:6d69e896ce38	6062	int32_t lsm6dso_sh_batch_slave_1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6063	{
cparata	4:77faf76e3cd8	6064	lsm6dso_slv1_config_t reg;
cparata	4:77faf76e3cd8	6065	int32_t ret;
cparata	4:77faf76e3cd8	6066
cparata	4:77faf76e3cd8	6067	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	6068	if (ret == 0) {
cparata	4:77faf76e3cd8	6069	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6070	}
cparata	4:77faf76e3cd8	6071	if (ret == 0) {
cparata	4:77faf76e3cd8	6072	reg.batch_ext_sens_1_en = val;
cparata	4:77faf76e3cd8	6073	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6074	}
cparata	4:77faf76e3cd8	6075	if (ret == 0) {
cparata	4:77faf76e3cd8	6076	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6077	}
cparata	4:77faf76e3cd8	6078
cparata	4:77faf76e3cd8	6079	return ret;
cparata	0:6d69e896ce38	6080	}
cparata	0:6d69e896ce38	6081
cparata	0:6d69e896ce38	6082	/**
cparata	0:6d69e896ce38	6083	* @brief Enable FIFO batching data of second slave.[get]
cparata	0:6d69e896ce38	6084	*
cparata	0:6d69e896ce38	6085	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6086	* @param val change the values of batch_ext_sens_1_en in
cparata	0:6d69e896ce38	6087	* reg SLV1_CONFIG
cparata	0:6d69e896ce38	6088	*
cparata	0:6d69e896ce38	6089	*/
cparata	0:6d69e896ce38	6090	int32_t lsm6dso_sh_batch_slave_1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6091	{
cparata	4:77faf76e3cd8	6092	lsm6dso_slv1_config_t reg;
cparata	4:77faf76e3cd8	6093	int32_t ret;
cparata	4:77faf76e3cd8	6094
cparata	4:77faf76e3cd8	6095	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	6096	if (ret == 0) {
cparata	4:77faf76e3cd8	6097	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6098	*val = reg.batch_ext_sens_1_en;
cparata	4:77faf76e3cd8	6099	}
cparata	4:77faf76e3cd8	6100	if (ret == 0) {
cparata	4:77faf76e3cd8	6101	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6102	}
cparata	4:77faf76e3cd8	6103	return ret;
cparata	0:6d69e896ce38	6104	}
cparata	0:6d69e896ce38	6105
cparata	0:6d69e896ce38	6106	/**
cparata	0:6d69e896ce38	6107	* @brief Enable FIFO batching data of third slave.[set]
cparata	0:6d69e896ce38	6108	*
cparata	0:6d69e896ce38	6109	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6110	* @param val change the values of batch_ext_sens_2_en in
cparata	0:6d69e896ce38	6111	* reg SLV2_CONFIG
cparata	0:6d69e896ce38	6112	*
cparata	0:6d69e896ce38	6113	*/
cparata	0:6d69e896ce38	6114	int32_t lsm6dso_sh_batch_slave_2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6115	{
cparata	4:77faf76e3cd8	6116	lsm6dso_slv2_config_t reg;
cparata	4:77faf76e3cd8	6117	int32_t ret;
cparata	4:77faf76e3cd8	6118
cparata	4:77faf76e3cd8	6119	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	6120
cparata	4:77faf76e3cd8	6121	if (ret == 0) {
cparata	4:77faf76e3cd8	6122	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6123	}
cparata	4:77faf76e3cd8	6124	if (ret == 0) {
cparata	4:77faf76e3cd8	6125	reg.batch_ext_sens_2_en = val;
cparata	4:77faf76e3cd8	6126	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6127	}
cparata	4:77faf76e3cd8	6128	if (ret == 0) {
cparata	4:77faf76e3cd8	6129	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6130	}
cparata	4:77faf76e3cd8	6131	return ret;
cparata	0:6d69e896ce38	6132	}
cparata	0:6d69e896ce38	6133
cparata	0:6d69e896ce38	6134	/**
cparata	0:6d69e896ce38	6135	* @brief Enable FIFO batching data of third slave.[get]
cparata	0:6d69e896ce38	6136	*
cparata	0:6d69e896ce38	6137	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6138	* @param val change the values of batch_ext_sens_2_en in
cparata	0:6d69e896ce38	6139	* reg SLV2_CONFIG
cparata	0:6d69e896ce38	6140	*
cparata	0:6d69e896ce38	6141	*/
cparata	0:6d69e896ce38	6142	int32_t lsm6dso_sh_batch_slave_2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6143	{
cparata	4:77faf76e3cd8	6144	lsm6dso_slv2_config_t reg;
cparata	4:77faf76e3cd8	6145	int32_t ret;
cparata	4:77faf76e3cd8	6146
cparata	4:77faf76e3cd8	6147	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	6148	if (ret == 0) {
cparata	4:77faf76e3cd8	6149	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6150	}
cparata	4:77faf76e3cd8	6151	if (ret == 0) {
cparata	4:77faf76e3cd8	6152	*val = reg.batch_ext_sens_2_en;
cparata	4:77faf76e3cd8	6153	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6154	}
cparata	4:77faf76e3cd8	6155
cparata	4:77faf76e3cd8	6156	return ret;
cparata	0:6d69e896ce38	6157	}
cparata	0:6d69e896ce38	6158
cparata	0:6d69e896ce38	6159	/**
cparata	0:6d69e896ce38	6160	* @brief Enable FIFO batching data of fourth slave.[set]
cparata	0:6d69e896ce38	6161	*
cparata	0:6d69e896ce38	6162	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6163	* @param val change the values of batch_ext_sens_3_en
cparata	0:6d69e896ce38	6164	* in reg SLV3_CONFIG
cparata	0:6d69e896ce38	6165	*
cparata	0:6d69e896ce38	6166	*/
cparata	0:6d69e896ce38	6167	int32_t lsm6dso_sh_batch_slave_3_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6168	{
cparata	4:77faf76e3cd8	6169	lsm6dso_slv3_config_t reg;
cparata	4:77faf76e3cd8	6170	int32_t ret;
cparata	4:77faf76e3cd8	6171
cparata	4:77faf76e3cd8	6172	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	6173	if (ret == 0) {
cparata	4:77faf76e3cd8	6174	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6175	}
cparata	4:77faf76e3cd8	6176	if (ret == 0) {
cparata	4:77faf76e3cd8	6177	reg.batch_ext_sens_3_en = val;
cparata	4:77faf76e3cd8	6178	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6179	}
cparata	4:77faf76e3cd8	6180	if (ret == 0) {
cparata	4:77faf76e3cd8	6181	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6182	}
cparata	4:77faf76e3cd8	6183
cparata	4:77faf76e3cd8	6184	return ret;
cparata	0:6d69e896ce38	6185	}
cparata	0:6d69e896ce38	6186
cparata	0:6d69e896ce38	6187	/**
cparata	0:6d69e896ce38	6188	* @brief Enable FIFO batching data of fourth slave.[get]
cparata	0:6d69e896ce38	6189	*
cparata	0:6d69e896ce38	6190	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6191	* @param val change the values of batch_ext_sens_3_en in
cparata	0:6d69e896ce38	6192	* reg SLV3_CONFIG
cparata	0:6d69e896ce38	6193	*
cparata	0:6d69e896ce38	6194	*/
cparata	0:6d69e896ce38	6195	int32_t lsm6dso_sh_batch_slave_3_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6196	{
cparata	4:77faf76e3cd8	6197	lsm6dso_slv3_config_t reg;
cparata	4:77faf76e3cd8	6198	int32_t ret;
cparata	4:77faf76e3cd8	6199
cparata	4:77faf76e3cd8	6200	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	6201	if (ret == 0) {
cparata	4:77faf76e3cd8	6202	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6203	}
cparata	4:77faf76e3cd8	6204	if (ret == 0) {
cparata	4:77faf76e3cd8	6205	*val = reg.batch_ext_sens_3_en;
cparata	4:77faf76e3cd8	6206	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6207	}
cparata	4:77faf76e3cd8	6208
cparata	4:77faf76e3cd8	6209	return ret;
cparata	0:6d69e896ce38	6210	}
cparata	0:6d69e896ce38	6211
cparata	0:6d69e896ce38	6212	/**
cparata	0:6d69e896ce38	6213	* @}
cparata	0:6d69e896ce38	6214	*
cparata	0:6d69e896ce38	6215	*/
cparata	0:6d69e896ce38	6216
cparata	0:6d69e896ce38	6217	/**
cparata	0:6d69e896ce38	6218	* @defgroup LSM6DSO_DEN_functionality
cparata	0:6d69e896ce38	6219	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	6220	* DEN functionality.
cparata	0:6d69e896ce38	6221	* @{
cparata	0:6d69e896ce38	6222	*
cparata	0:6d69e896ce38	6223	*/
cparata	0:6d69e896ce38	6224
cparata	0:6d69e896ce38	6225	/**
cparata	0:6d69e896ce38	6226	* @brief DEN functionality marking mode.[set]
cparata	0:6d69e896ce38	6227	*
cparata	0:6d69e896ce38	6228	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6229	* @param val change the values of den_mode in reg CTRL6_C
cparata	0:6d69e896ce38	6230	*
cparata	0:6d69e896ce38	6231	*/
cparata	0:6d69e896ce38	6232	int32_t lsm6dso_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_den_mode_t val)
cparata	0:6d69e896ce38	6233	{
cparata	4:77faf76e3cd8	6234	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	6235	int32_t ret;
cparata	4:77faf76e3cd8	6236
cparata	4:77faf76e3cd8	6237	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6238	if (ret == 0) {
cparata	4:77faf76e3cd8	6239	reg.den_mode = (uint8_t)val;
cparata	4:77faf76e3cd8	6240	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6241	}
cparata	4:77faf76e3cd8	6242
cparata	4:77faf76e3cd8	6243	return ret;
cparata	0:6d69e896ce38	6244	}
cparata	0:6d69e896ce38	6245
cparata	0:6d69e896ce38	6246	/**
cparata	0:6d69e896ce38	6247	* @brief DEN functionality marking mode.[get]
cparata	0:6d69e896ce38	6248	*
cparata	0:6d69e896ce38	6249	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6250	* @param val Get the values of den_mode in reg CTRL6_C
cparata	0:6d69e896ce38	6251	*
cparata	0:6d69e896ce38	6252	*/
cparata	0:6d69e896ce38	6253	int32_t lsm6dso_den_mode_get(lsm6dso_ctx_t ctx, lsm6dso_den_mode_t val)
cparata	0:6d69e896ce38	6254	{
cparata	4:77faf76e3cd8	6255	lsm6dso_ctrl6_c_t reg;
cparata	4:77faf76e3cd8	6256	int32_t ret;
cparata	4:77faf76e3cd8	6257
cparata	4:77faf76e3cd8	6258	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6259
cparata	4:77faf76e3cd8	6260	switch (reg.den_mode) {
cparata	4:77faf76e3cd8	6261	case LSM6DSO_DEN_DISABLE:
cparata	4:77faf76e3cd8	6262	*val = LSM6DSO_DEN_DISABLE;
cparata	4:77faf76e3cd8	6263	break;
cparata	4:77faf76e3cd8	6264	case LSM6DSO_LEVEL_FIFO:
cparata	4:77faf76e3cd8	6265	*val = LSM6DSO_LEVEL_FIFO;
cparata	4:77faf76e3cd8	6266	break;
cparata	4:77faf76e3cd8	6267	case LSM6DSO_LEVEL_LETCHED:
cparata	4:77faf76e3cd8	6268	*val = LSM6DSO_LEVEL_LETCHED;
cparata	4:77faf76e3cd8	6269	break;
cparata	4:77faf76e3cd8	6270	case LSM6DSO_LEVEL_TRIGGER:
cparata	4:77faf76e3cd8	6271	*val = LSM6DSO_LEVEL_TRIGGER;
cparata	4:77faf76e3cd8	6272	break;
cparata	4:77faf76e3cd8	6273	case LSM6DSO_EDGE_TRIGGER:
cparata	4:77faf76e3cd8	6274	*val = LSM6DSO_EDGE_TRIGGER;
cparata	4:77faf76e3cd8	6275	break;
cparata	4:77faf76e3cd8	6276	default:
cparata	4:77faf76e3cd8	6277	*val = LSM6DSO_DEN_DISABLE;
cparata	4:77faf76e3cd8	6278	break;
cparata	4:77faf76e3cd8	6279	}
cparata	4:77faf76e3cd8	6280	return ret;
cparata	0:6d69e896ce38	6281	}
cparata	0:6d69e896ce38	6282
cparata	0:6d69e896ce38	6283	/**
cparata	0:6d69e896ce38	6284	* @brief DEN active level configuration.[set]
cparata	0:6d69e896ce38	6285	*
cparata	0:6d69e896ce38	6286	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6287	* @param val change the values of den_lh in reg CTRL9_XL
cparata	0:6d69e896ce38	6288	*
cparata	0:6d69e896ce38	6289	*/
cparata	0:6d69e896ce38	6290	int32_t lsm6dso_den_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_den_lh_t val)
cparata	0:6d69e896ce38	6291	{
cparata	4:77faf76e3cd8	6292	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6293	int32_t ret;
cparata	4:77faf76e3cd8	6294
cparata	4:77faf76e3cd8	6295	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6296	if (ret == 0) {
cparata	4:77faf76e3cd8	6297	reg.den_lh = (uint8_t)val;
cparata	4:77faf76e3cd8	6298	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6299	}
cparata	4:77faf76e3cd8	6300
cparata	4:77faf76e3cd8	6301	return ret;
cparata	0:6d69e896ce38	6302	}
cparata	0:6d69e896ce38	6303
cparata	0:6d69e896ce38	6304	/**
cparata	0:6d69e896ce38	6305	* @brief DEN active level configuration.[get]
cparata	0:6d69e896ce38	6306	*
cparata	0:6d69e896ce38	6307	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6308	* @param val Get the values of den_lh in reg CTRL9_XL
cparata	0:6d69e896ce38	6309	*
cparata	0:6d69e896ce38	6310	*/
cparata	0:6d69e896ce38	6311	int32_t lsm6dso_den_polarity_get(lsm6dso_ctx_t ctx, lsm6dso_den_lh_t val)
cparata	0:6d69e896ce38	6312	{
cparata	4:77faf76e3cd8	6313	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6314	int32_t ret;
cparata	4:77faf76e3cd8	6315
cparata	4:77faf76e3cd8	6316	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6317
cparata	4:77faf76e3cd8	6318	switch (reg.den_lh) {
cparata	4:77faf76e3cd8	6319	case LSM6DSO_DEN_ACT_LOW:
cparata	4:77faf76e3cd8	6320	*val = LSM6DSO_DEN_ACT_LOW;
cparata	4:77faf76e3cd8	6321	break;
cparata	4:77faf76e3cd8	6322	case LSM6DSO_DEN_ACT_HIGH:
cparata	4:77faf76e3cd8	6323	*val = LSM6DSO_DEN_ACT_HIGH;
cparata	4:77faf76e3cd8	6324	break;
cparata	4:77faf76e3cd8	6325	default:
cparata	4:77faf76e3cd8	6326	*val = LSM6DSO_DEN_ACT_LOW;
cparata	4:77faf76e3cd8	6327	break;
cparata	4:77faf76e3cd8	6328	}
cparata	4:77faf76e3cd8	6329	return ret;
cparata	0:6d69e896ce38	6330	}
cparata	0:6d69e896ce38	6331
cparata	0:6d69e896ce38	6332	/**
cparata	0:6d69e896ce38	6333	* @brief DEN enable.[set]
cparata	0:6d69e896ce38	6334	*
cparata	0:6d69e896ce38	6335	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6336	* @param val change the values of den_xl_g in reg CTRL9_XL
cparata	0:6d69e896ce38	6337	*
cparata	0:6d69e896ce38	6338	*/
cparata	0:6d69e896ce38	6339	int32_t lsm6dso_den_enable_set(lsm6dso_ctx_t *ctx, lsm6dso_den_xl_g_t val)
cparata	0:6d69e896ce38	6340	{
cparata	4:77faf76e3cd8	6341	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6342	int32_t ret;
cparata	4:77faf76e3cd8	6343
cparata	4:77faf76e3cd8	6344	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6345	if (ret == 0) {
cparata	4:77faf76e3cd8	6346	reg.den_xl_g = (uint8_t)val;
cparata	4:77faf76e3cd8	6347	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6348	}
cparata	4:77faf76e3cd8	6349
cparata	4:77faf76e3cd8	6350	return ret;
cparata	0:6d69e896ce38	6351	}
cparata	0:6d69e896ce38	6352
cparata	0:6d69e896ce38	6353	/**
cparata	0:6d69e896ce38	6354	* @brief DEN enable.[get]
cparata	0:6d69e896ce38	6355	*
cparata	0:6d69e896ce38	6356	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6357	* @param val Get the values of den_xl_g in reg CTRL9_XL
cparata	0:6d69e896ce38	6358	*
cparata	0:6d69e896ce38	6359	*/
cparata	0:6d69e896ce38	6360	int32_t lsm6dso_den_enable_get(lsm6dso_ctx_t ctx, lsm6dso_den_xl_g_t val)
cparata	0:6d69e896ce38	6361	{
cparata	4:77faf76e3cd8	6362	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6363	int32_t ret;
cparata	4:77faf76e3cd8	6364
cparata	4:77faf76e3cd8	6365	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6366
cparata	4:77faf76e3cd8	6367	switch (reg.den_xl_g) {
cparata	4:77faf76e3cd8	6368	case LSM6DSO_STAMP_IN_GY_DATA:
cparata	4:77faf76e3cd8	6369	*val = LSM6DSO_STAMP_IN_GY_DATA;
cparata	4:77faf76e3cd8	6370	break;
cparata	4:77faf76e3cd8	6371	case LSM6DSO_STAMP_IN_XL_DATA:
cparata	4:77faf76e3cd8	6372	*val = LSM6DSO_STAMP_IN_XL_DATA;
cparata	4:77faf76e3cd8	6373	break;
cparata	4:77faf76e3cd8	6374	case LSM6DSO_STAMP_IN_GY_XL_DATA:
cparata	4:77faf76e3cd8	6375	*val = LSM6DSO_STAMP_IN_GY_XL_DATA;
cparata	4:77faf76e3cd8	6376	break;
cparata	4:77faf76e3cd8	6377	default:
cparata	4:77faf76e3cd8	6378	*val = LSM6DSO_STAMP_IN_GY_DATA;
cparata	4:77faf76e3cd8	6379	break;
cparata	4:77faf76e3cd8	6380	}
cparata	4:77faf76e3cd8	6381	return ret;
cparata	0:6d69e896ce38	6382	}
cparata	0:6d69e896ce38	6383
cparata	0:6d69e896ce38	6384	/**
cparata	0:6d69e896ce38	6385	* @brief DEN value stored in LSB of X-axis.[set]
cparata	0:6d69e896ce38	6386	*
cparata	0:6d69e896ce38	6387	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6388	* @param val change the values of den_z in reg CTRL9_XL
cparata	0:6d69e896ce38	6389	*
cparata	0:6d69e896ce38	6390	*/
cparata	0:6d69e896ce38	6391	int32_t lsm6dso_den_mark_axis_x_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6392	{
cparata	4:77faf76e3cd8	6393	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6394	int32_t ret;
cparata	4:77faf76e3cd8	6395
cparata	4:77faf76e3cd8	6396	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6397	if (ret == 0) {
cparata	4:77faf76e3cd8	6398	reg.den_z = val;
cparata	4:77faf76e3cd8	6399	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6400	}
cparata	4:77faf76e3cd8	6401
cparata	4:77faf76e3cd8	6402	return ret;
cparata	0:6d69e896ce38	6403	}
cparata	0:6d69e896ce38	6404
cparata	0:6d69e896ce38	6405	/**
cparata	0:6d69e896ce38	6406	* @brief DEN value stored in LSB of X-axis.[get]
cparata	0:6d69e896ce38	6407	*
cparata	0:6d69e896ce38	6408	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6409	* @param val change the values of den_z in reg CTRL9_XL
cparata	0:6d69e896ce38	6410	*
cparata	0:6d69e896ce38	6411	*/
cparata	0:6d69e896ce38	6412	int32_t lsm6dso_den_mark_axis_x_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6413	{
cparata	4:77faf76e3cd8	6414	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6415	int32_t ret;
cparata	4:77faf76e3cd8	6416
cparata	4:77faf76e3cd8	6417	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6418	*val = reg.den_z;
cparata	4:77faf76e3cd8	6419
cparata	4:77faf76e3cd8	6420	return ret;
cparata	0:6d69e896ce38	6421	}
cparata	0:6d69e896ce38	6422
cparata	0:6d69e896ce38	6423	/**
cparata	0:6d69e896ce38	6424	* @brief DEN value stored in LSB of Y-axis.[set]
cparata	0:6d69e896ce38	6425	*
cparata	0:6d69e896ce38	6426	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6427	* @param val change the values of den_y in reg CTRL9_XL
cparata	0:6d69e896ce38	6428	*
cparata	0:6d69e896ce38	6429	*/
cparata	0:6d69e896ce38	6430	int32_t lsm6dso_den_mark_axis_y_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6431	{
cparata	4:77faf76e3cd8	6432	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6433	int32_t ret;
cparata	4:77faf76e3cd8	6434
cparata	4:77faf76e3cd8	6435	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6436	if (ret == 0) {
cparata	4:77faf76e3cd8	6437	reg.den_y = val;
cparata	4:77faf76e3cd8	6438	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6439	}
cparata	4:77faf76e3cd8	6440
cparata	4:77faf76e3cd8	6441	return ret;
cparata	0:6d69e896ce38	6442	}
cparata	0:6d69e896ce38	6443
cparata	0:6d69e896ce38	6444	/**
cparata	0:6d69e896ce38	6445	* @brief DEN value stored in LSB of Y-axis.[get]
cparata	0:6d69e896ce38	6446	*
cparata	0:6d69e896ce38	6447	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6448	* @param val change the values of den_y in reg CTRL9_XL
cparata	0:6d69e896ce38	6449	*
cparata	0:6d69e896ce38	6450	*/
cparata	0:6d69e896ce38	6451	int32_t lsm6dso_den_mark_axis_y_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6452	{
cparata	4:77faf76e3cd8	6453	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6454	int32_t ret;
cparata	4:77faf76e3cd8	6455
cparata	4:77faf76e3cd8	6456	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6457	*val = reg.den_y;
cparata	4:77faf76e3cd8	6458
cparata	4:77faf76e3cd8	6459	return ret;
cparata	0:6d69e896ce38	6460	}
cparata	0:6d69e896ce38	6461
cparata	0:6d69e896ce38	6462	/**
cparata	0:6d69e896ce38	6463	* @brief DEN value stored in LSB of Z-axis.[set]
cparata	0:6d69e896ce38	6464	*
cparata	0:6d69e896ce38	6465	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6466	* @param val change the values of den_x in reg CTRL9_XL
cparata	0:6d69e896ce38	6467	*
cparata	0:6d69e896ce38	6468	*/
cparata	0:6d69e896ce38	6469	int32_t lsm6dso_den_mark_axis_z_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6470	{
cparata	4:77faf76e3cd8	6471	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6472	int32_t ret;
cparata	4:77faf76e3cd8	6473
cparata	4:77faf76e3cd8	6474	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6475	if (ret == 0) {
cparata	4:77faf76e3cd8	6476	reg.den_x = val;
cparata	4:77faf76e3cd8	6477	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6478	}
cparata	4:77faf76e3cd8	6479
cparata	4:77faf76e3cd8	6480	return ret;
cparata	0:6d69e896ce38	6481	}
cparata	0:6d69e896ce38	6482
cparata	0:6d69e896ce38	6483	/**
cparata	0:6d69e896ce38	6484	* @brief DEN value stored in LSB of Z-axis.[get]
cparata	0:6d69e896ce38	6485	*
cparata	0:6d69e896ce38	6486	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6487	* @param val change the values of den_x in reg CTRL9_XL
cparata	0:6d69e896ce38	6488	*
cparata	0:6d69e896ce38	6489	*/
cparata	0:6d69e896ce38	6490	int32_t lsm6dso_den_mark_axis_z_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6491	{
cparata	4:77faf76e3cd8	6492	lsm6dso_ctrl9_xl_t reg;
cparata	4:77faf76e3cd8	6493	int32_t ret;
cparata	4:77faf76e3cd8	6494
cparata	4:77faf76e3cd8	6495	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6496	*val = reg.den_x;
cparata	4:77faf76e3cd8	6497
cparata	4:77faf76e3cd8	6498	return ret;
cparata	0:6d69e896ce38	6499	}
cparata	0:6d69e896ce38	6500
cparata	0:6d69e896ce38	6501	/**
cparata	0:6d69e896ce38	6502	* @}
cparata	0:6d69e896ce38	6503	*
cparata	0:6d69e896ce38	6504	*/
cparata	0:6d69e896ce38	6505
cparata	0:6d69e896ce38	6506	/**
cparata	0:6d69e896ce38	6507	* @defgroup LSM6DSO_Pedometer
cparata	0:6d69e896ce38	6508	* @brief This section groups all the functions that manage pedometer.
cparata	0:6d69e896ce38	6509	* @{
cparata	0:6d69e896ce38	6510	*
cparata	0:6d69e896ce38	6511	*/
cparata	0:6d69e896ce38	6512
cparata	0:6d69e896ce38	6513	/**
cparata	0:6d69e896ce38	6514	* @brief Enable pedometer algorithm.[set]
cparata	0:6d69e896ce38	6515	*
cparata	0:6d69e896ce38	6516	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6517	* @param val turn on and configure pedometer
cparata	0:6d69e896ce38	6518	*
cparata	0:6d69e896ce38	6519	*/
cparata	0:6d69e896ce38	6520	int32_t lsm6dso_pedo_sens_set(lsm6dso_ctx_t *ctx, lsm6dso_pedo_md_t val)
cparata	0:6d69e896ce38	6521	{
cparata	4:77faf76e3cd8	6522	lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
cparata	4:77faf76e3cd8	6523	int32_t ret;
cparata	4:77faf76e3cd8	6524
cparata	4:77faf76e3cd8	6525	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	4:77faf76e3cd8	6526	(uint8_t*)&pedo_cmd_reg);
cparata	4:77faf76e3cd8	6527
cparata	4:77faf76e3cd8	6528	if (ret == 0) {
cparata	4:77faf76e3cd8	6529	pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4;
cparata	4:77faf76e3cd8	6530	pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5;
cparata	4:77faf76e3cd8	6531	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	4:77faf76e3cd8	6532	(uint8_t*)&pedo_cmd_reg);
cparata	4:77faf76e3cd8	6533	}
cparata	4:77faf76e3cd8	6534	return ret;
cparata	0:6d69e896ce38	6535	}
cparata	0:6d69e896ce38	6536
cparata	0:6d69e896ce38	6537	/**
cparata	0:6d69e896ce38	6538	* @brief Enable pedometer algorithm.[get]
cparata	0:6d69e896ce38	6539	*
cparata	0:6d69e896ce38	6540	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6541	* @param val turn on and configure pedometer
cparata	0:6d69e896ce38	6542	*
cparata	0:6d69e896ce38	6543	*/
cparata	0:6d69e896ce38	6544	int32_t lsm6dso_pedo_sens_get(lsm6dso_ctx_t ctx, lsm6dso_pedo_md_t val)
cparata	0:6d69e896ce38	6545	{
cparata	4:77faf76e3cd8	6546	lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
cparata	4:77faf76e3cd8	6547	int32_t ret;
cparata	4:77faf76e3cd8	6548
cparata	4:77faf76e3cd8	6549	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	4:77faf76e3cd8	6550	(uint8_t*)&pedo_cmd_reg);
cparata	4:77faf76e3cd8	6551	switch ( (pedo_cmd_reg.ad_det_en <<5) \| (pedo_cmd_reg.fp_rejection_en << 4) ) {
cparata	4:77faf76e3cd8	6552	case LSM6DSO_PEDO_BASE_MODE:
cparata	4:77faf76e3cd8	6553	*val = LSM6DSO_PEDO_BASE_MODE;
cparata	4:77faf76e3cd8	6554	break;
cparata	4:77faf76e3cd8	6555	case LSM6DSO_FALSE_STEP_REJ:
cparata	4:77faf76e3cd8	6556	*val = LSM6DSO_FALSE_STEP_REJ;
cparata	4:77faf76e3cd8	6557	break;
cparata	4:77faf76e3cd8	6558	case LSM6DSO_FALSE_STEP_REJ_ADV_MODE:
cparata	4:77faf76e3cd8	6559	*val = LSM6DSO_FALSE_STEP_REJ_ADV_MODE;
cparata	4:77faf76e3cd8	6560	break;
cparata	4:77faf76e3cd8	6561	default:
cparata	4:77faf76e3cd8	6562	*val = LSM6DSO_PEDO_BASE_MODE;
cparata	4:77faf76e3cd8	6563	break;
cparata	4:77faf76e3cd8	6564	}
cparata	4:77faf76e3cd8	6565	return ret;
cparata	0:6d69e896ce38	6566	}
cparata	0:6d69e896ce38	6567
cparata	0:6d69e896ce38	6568	/**
cparata	0:6d69e896ce38	6569	* @brief Interrupt status bit for step detection.[get]
cparata	0:6d69e896ce38	6570	*
cparata	0:6d69e896ce38	6571	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6572	* @param val change the values of is_step_det in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	6573	*
cparata	0:6d69e896ce38	6574	*/
cparata	0:6d69e896ce38	6575	int32_t lsm6dso_pedo_step_detect_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6576	{
cparata	4:77faf76e3cd8	6577	lsm6dso_emb_func_status_t reg;
cparata	4:77faf76e3cd8	6578	int32_t ret;
cparata	4:77faf76e3cd8	6579
cparata	4:77faf76e3cd8	6580	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	6581	if (ret == 0) {
cparata	4:77faf76e3cd8	6582	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6583	}
cparata	4:77faf76e3cd8	6584	if (ret == 0) {
cparata	4:77faf76e3cd8	6585	*val = reg.is_step_det;
cparata	4:77faf76e3cd8	6586	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6587	}
cparata	4:77faf76e3cd8	6588
cparata	4:77faf76e3cd8	6589	return ret;
cparata	0:6d69e896ce38	6590	}
cparata	0:6d69e896ce38	6591
cparata	0:6d69e896ce38	6592	/**
cparata	0:6d69e896ce38	6593	* @brief Pedometer debounce configuration register (r/w).[set]
cparata	0:6d69e896ce38	6594	*
cparata	0:6d69e896ce38	6595	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6596	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	6597	*
cparata	0:6d69e896ce38	6598	*/
cparata	0:6d69e896ce38	6599	int32_t lsm6dso_pedo_debounce_steps_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6600	{
cparata	4:77faf76e3cd8	6601	int32_t ret;
cparata	4:77faf76e3cd8	6602	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
cparata	4:77faf76e3cd8	6603	return ret;
cparata	0:6d69e896ce38	6604	}
cparata	0:6d69e896ce38	6605
cparata	0:6d69e896ce38	6606	/**
cparata	0:6d69e896ce38	6607	* @brief Pedometer debounce configuration register (r/w).[get]
cparata	0:6d69e896ce38	6608	*
cparata	0:6d69e896ce38	6609	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6610	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	6611	*
cparata	0:6d69e896ce38	6612	*/
cparata	0:6d69e896ce38	6613	int32_t lsm6dso_pedo_debounce_steps_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6614	{
cparata	4:77faf76e3cd8	6615	int32_t ret;
cparata	4:77faf76e3cd8	6616	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
cparata	4:77faf76e3cd8	6617	return ret;
cparata	0:6d69e896ce38	6618	}
cparata	0:6d69e896ce38	6619
cparata	0:6d69e896ce38	6620	/**
cparata	0:6d69e896ce38	6621	* @brief Time period register for step detection on delta time (r/w).[set]
cparata	0:6d69e896ce38	6622	*
cparata	0:6d69e896ce38	6623	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6624	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	6625	*
cparata	0:6d69e896ce38	6626	*/
cparata	0:6d69e896ce38	6627	int32_t lsm6dso_pedo_steps_period_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6628	{
cparata	4:77faf76e3cd8	6629	int32_t ret;
cparata	4:77faf76e3cd8	6630	uint8_t index;
cparata	4:77faf76e3cd8	6631
cparata	4:77faf76e3cd8	6632	index = 0x00U;
cparata	4:77faf76e3cd8	6633	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]);
cparata	4:77faf76e3cd8	6634	if (ret == 0) {
cparata	4:77faf76e3cd8	6635	index++;
cparata	4:77faf76e3cd8	6636	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
cparata	4:77faf76e3cd8	6637	&buff[index]);
cparata	4:77faf76e3cd8	6638	}
cparata	4:77faf76e3cd8	6639	return ret;
cparata	0:6d69e896ce38	6640	}
cparata	0:6d69e896ce38	6641
cparata	0:6d69e896ce38	6642	/**
cparata	0:6d69e896ce38	6643	* @brief Time period register for step detection on delta time (r/w).[get]
cparata	0:6d69e896ce38	6644	*
cparata	0:6d69e896ce38	6645	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6646	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	6647	*
cparata	0:6d69e896ce38	6648	*/
cparata	0:6d69e896ce38	6649	int32_t lsm6dso_pedo_steps_period_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6650	{
cparata	4:77faf76e3cd8	6651	int32_t ret;
cparata	4:77faf76e3cd8	6652	uint8_t index;
cparata	4:77faf76e3cd8	6653
cparata	4:77faf76e3cd8	6654	index = 0x00U;
cparata	4:77faf76e3cd8	6655	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]);
cparata	4:77faf76e3cd8	6656	if (ret == 0) {
cparata	4:77faf76e3cd8	6657	index++;
cparata	4:77faf76e3cd8	6658	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
cparata	4:77faf76e3cd8	6659	&buff[index]);
cparata	4:77faf76e3cd8	6660	}
cparata	4:77faf76e3cd8	6661	return ret;
cparata	0:6d69e896ce38	6662	}
cparata	0:6d69e896ce38	6663
cparata	0:6d69e896ce38	6664	/**
cparata	0:6d69e896ce38	6665	* @brief Set when user wants to generate interrupt on count overflow
cparata	0:6d69e896ce38	6666	* event/every step.[set]
cparata	0:6d69e896ce38	6667	*
cparata	0:6d69e896ce38	6668	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6669	* @param val change the values of carry_count_en in reg PEDO_CMD_REG
cparata	0:6d69e896ce38	6670	*
cparata	0:6d69e896ce38	6671	*/
cparata	0:6d69e896ce38	6672	int32_t lsm6dso_pedo_int_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	6673	lsm6dso_carry_count_en_t val)
cparata	0:6d69e896ce38	6674	{
cparata	4:77faf76e3cd8	6675	lsm6dso_pedo_cmd_reg_t reg;
cparata	4:77faf76e3cd8	6676	int32_t ret;
cparata	4:77faf76e3cd8	6677
cparata	4:77faf76e3cd8	6678	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	6679	if (ret == 0) {
cparata	4:77faf76e3cd8	6680	reg.carry_count_en = (uint8_t)val;
cparata	4:77faf76e3cd8	6681	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	4:77faf76e3cd8	6682	(uint8_t*)&reg);
cparata	4:77faf76e3cd8	6683	}
cparata	4:77faf76e3cd8	6684	return ret;
cparata	0:6d69e896ce38	6685	}
cparata	0:6d69e896ce38	6686
cparata	0:6d69e896ce38	6687	/**
cparata	0:6d69e896ce38	6688	* @brief Set when user wants to generate interrupt on count overflow
cparata	0:6d69e896ce38	6689	* event/every step.[get]
cparata	0:6d69e896ce38	6690	*
cparata	0:6d69e896ce38	6691	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6692	* @param val Get the values of carry_count_en in reg PEDO_CMD_REG
cparata	0:6d69e896ce38	6693	*
cparata	0:6d69e896ce38	6694	*/
cparata	0:6d69e896ce38	6695	int32_t lsm6dso_pedo_int_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	6696	lsm6dso_carry_count_en_t *val)
cparata	0:6d69e896ce38	6697	{
cparata	4:77faf76e3cd8	6698	lsm6dso_pedo_cmd_reg_t reg;
cparata	4:77faf76e3cd8	6699	int32_t ret;
cparata	4:77faf76e3cd8	6700
cparata	4:77faf76e3cd8	6701	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	6702	switch (reg.carry_count_en) {
cparata	4:77faf76e3cd8	6703	case LSM6DSO_EVERY_STEP:
cparata	4:77faf76e3cd8	6704	*val = LSM6DSO_EVERY_STEP;
cparata	4:77faf76e3cd8	6705	break;
cparata	4:77faf76e3cd8	6706	case LSM6DSO_COUNT_OVERFLOW:
cparata	4:77faf76e3cd8	6707	*val = LSM6DSO_COUNT_OVERFLOW;
cparata	4:77faf76e3cd8	6708	break;
cparata	4:77faf76e3cd8	6709	default:
cparata	4:77faf76e3cd8	6710	*val = LSM6DSO_EVERY_STEP;
cparata	4:77faf76e3cd8	6711	break;
cparata	4:77faf76e3cd8	6712	}
cparata	4:77faf76e3cd8	6713	return ret;
cparata	0:6d69e896ce38	6714	}
cparata	0:6d69e896ce38	6715
cparata	0:6d69e896ce38	6716	/**
cparata	0:6d69e896ce38	6717	* @}
cparata	0:6d69e896ce38	6718	*
cparata	0:6d69e896ce38	6719	*/
cparata	0:6d69e896ce38	6720
cparata	0:6d69e896ce38	6721	/**
cparata	0:6d69e896ce38	6722	* @defgroup LSM6DSO_significant_motion
cparata	0:6d69e896ce38	6723	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	6724	* significant motion detection.
cparata	0:6d69e896ce38	6725	* @{
cparata	0:6d69e896ce38	6726	*
cparata	0:6d69e896ce38	6727	*/
cparata	0:6d69e896ce38	6728
cparata	0:6d69e896ce38	6729	/**
cparata	0:6d69e896ce38	6730	* @brief Interrupt status bit for significant motion detection.[get]
cparata	0:6d69e896ce38	6731	*
cparata	0:6d69e896ce38	6732	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6733	* @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	6734	*
cparata	0:6d69e896ce38	6735	*/
cparata	0:6d69e896ce38	6736	int32_t lsm6dso_motion_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6737	{
cparata	4:77faf76e3cd8	6738	lsm6dso_emb_func_status_t reg;
cparata	4:77faf76e3cd8	6739	int32_t ret;
cparata	4:77faf76e3cd8	6740
cparata	4:77faf76e3cd8	6741	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	6742	if (ret == 0) {
cparata	4:77faf76e3cd8	6743	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6744	}
cparata	4:77faf76e3cd8	6745	if (ret == 0) {
cparata	4:77faf76e3cd8	6746	*val = reg.is_sigmot;
cparata	4:77faf76e3cd8	6747	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6748	}
cparata	4:77faf76e3cd8	6749
cparata	4:77faf76e3cd8	6750	return ret;
cparata	0:6d69e896ce38	6751	}
cparata	0:6d69e896ce38	6752
cparata	0:6d69e896ce38	6753	/**
cparata	0:6d69e896ce38	6754	* @}
cparata	0:6d69e896ce38	6755	*
cparata	0:6d69e896ce38	6756	*/
cparata	0:6d69e896ce38	6757
cparata	0:6d69e896ce38	6758	/**
cparata	0:6d69e896ce38	6759	* @defgroup LSM6DSO_tilt_detection
cparata	0:6d69e896ce38	6760	* @brief This section groups all the functions that manage the tilt
cparata	0:6d69e896ce38	6761	* event detection.
cparata	0:6d69e896ce38	6762	* @{
cparata	0:6d69e896ce38	6763	*
cparata	0:6d69e896ce38	6764	*/
cparata	0:6d69e896ce38	6765
cparata	0:6d69e896ce38	6766	/**
cparata	0:6d69e896ce38	6767	* @brief Interrupt status bit for tilt detection.[get]
cparata	0:6d69e896ce38	6768	*
cparata	0:6d69e896ce38	6769	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6770	* @param val change the values of is_tilt in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	6771	*
cparata	0:6d69e896ce38	6772	*/
cparata	0:6d69e896ce38	6773	int32_t lsm6dso_tilt_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6774	{
cparata	4:77faf76e3cd8	6775	lsm6dso_emb_func_status_t reg;
cparata	4:77faf76e3cd8	6776	int32_t ret;
cparata	4:77faf76e3cd8	6777
cparata	4:77faf76e3cd8	6778	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	6779	if (ret == 0) {
cparata	4:77faf76e3cd8	6780	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	6781	}
cparata	4:77faf76e3cd8	6782	if (ret == 0) {
cparata	4:77faf76e3cd8	6783	*val = reg.is_tilt;
cparata	4:77faf76e3cd8	6784	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	6785	}
cparata	4:77faf76e3cd8	6786
cparata	4:77faf76e3cd8	6787	return ret;
cparata	0:6d69e896ce38	6788	}
cparata	0:6d69e896ce38	6789
cparata	0:6d69e896ce38	6790	/**
cparata	0:6d69e896ce38	6791	* @}
cparata	0:6d69e896ce38	6792	*
cparata	0:6d69e896ce38	6793	*/
cparata	0:6d69e896ce38	6794
cparata	0:6d69e896ce38	6795	/**
cparata	0:6d69e896ce38	6796	* @defgroup LSM6DSO_ magnetometer_sensor
cparata	0:6d69e896ce38	6797	* @brief This section groups all the functions that manage additional
cparata	0:6d69e896ce38	6798	* magnetometer sensor.
cparata	0:6d69e896ce38	6799	* @{
cparata	0:6d69e896ce38	6800	*
cparata	0:6d69e896ce38	6801	*/
cparata	0:6d69e896ce38	6802
cparata	0:6d69e896ce38	6803	/**
cparata	0:6d69e896ce38	6804	* @brief External magnetometer sensitivity value register.[set]
cparata	0:6d69e896ce38	6805	*
cparata	0:6d69e896ce38	6806	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6807	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	6808	*
cparata	0:6d69e896ce38	6809	*/
cparata	0:6d69e896ce38	6810	int32_t lsm6dso_mag_sensitivity_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6811	{
cparata	4:77faf76e3cd8	6812	int32_t ret;
cparata	4:77faf76e3cd8	6813	uint8_t index;
cparata	4:77faf76e3cd8	6814
cparata	4:77faf76e3cd8	6815	index = 0x00U;
cparata	4:77faf76e3cd8	6816	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
cparata	4:77faf76e3cd8	6817	&buff[index]);
cparata	4:77faf76e3cd8	6818	if (ret == 0) {
cparata	4:77faf76e3cd8	6819	index++;
cparata	4:77faf76e3cd8	6820	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
cparata	0:6d69e896ce38	6821	&buff[index]);
cparata	4:77faf76e3cd8	6822	}
cparata	4:77faf76e3cd8	6823
cparata	4:77faf76e3cd8	6824	return ret;
cparata	0:6d69e896ce38	6825	}
cparata	0:6d69e896ce38	6826
cparata	0:6d69e896ce38	6827	/**
cparata	0:6d69e896ce38	6828	* @brief External magnetometer sensitivity value register.[get]
cparata	0:6d69e896ce38	6829	*
cparata	0:6d69e896ce38	6830	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6831	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	6832	*
cparata	0:6d69e896ce38	6833	*/
cparata	0:6d69e896ce38	6834	int32_t lsm6dso_mag_sensitivity_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6835	{
cparata	4:77faf76e3cd8	6836	int32_t ret;
cparata	4:77faf76e3cd8	6837	uint8_t index;
cparata	4:77faf76e3cd8	6838
cparata	4:77faf76e3cd8	6839	index = 0x00U;
cparata	4:77faf76e3cd8	6840	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
cparata	4:77faf76e3cd8	6841	&buff[index]);
cparata	4:77faf76e3cd8	6842	if (ret == 0) {
cparata	4:77faf76e3cd8	6843	index++;
cparata	4:77faf76e3cd8	6844	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
cparata	0:6d69e896ce38	6845	&buff[index]);
cparata	4:77faf76e3cd8	6846	}
cparata	4:77faf76e3cd8	6847
cparata	4:77faf76e3cd8	6848	return ret;
cparata	0:6d69e896ce38	6849	}
cparata	0:6d69e896ce38	6850
cparata	0:6d69e896ce38	6851	/**
cparata	0:6d69e896ce38	6852	* @brief Offset for hard-iron compensation register (r/w).[set]
cparata	0:6d69e896ce38	6853	*
cparata	0:6d69e896ce38	6854	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6855	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	6856	*
cparata	0:6d69e896ce38	6857	*/
cparata	0:6d69e896ce38	6858	int32_t lsm6dso_mag_offset_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6859	{
cparata	4:77faf76e3cd8	6860	int32_t ret;
cparata	4:77faf76e3cd8	6861	uint8_t index;
cparata	4:77faf76e3cd8	6862
cparata	4:77faf76e3cd8	6863	index = 0x00U;
cparata	4:77faf76e3cd8	6864	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]);
cparata	4:77faf76e3cd8	6865	if (ret == 0) {
cparata	4:77faf76e3cd8	6866	index++;
cparata	4:77faf76e3cd8	6867	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]);
cparata	4:77faf76e3cd8	6868	}
cparata	4:77faf76e3cd8	6869	if (ret == 0) {
cparata	4:77faf76e3cd8	6870	index++;
cparata	4:77faf76e3cd8	6871	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]);
cparata	4:77faf76e3cd8	6872	}
cparata	4:77faf76e3cd8	6873	if (ret == 0) {
cparata	4:77faf76e3cd8	6874	index++;
cparata	4:77faf76e3cd8	6875	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]);
cparata	4:77faf76e3cd8	6876	}
cparata	4:77faf76e3cd8	6877	if (ret == 0) {
cparata	4:77faf76e3cd8	6878	index++;
cparata	4:77faf76e3cd8	6879
cparata	4:77faf76e3cd8	6880	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]);
cparata	4:77faf76e3cd8	6881	}
cparata	4:77faf76e3cd8	6882	if (ret == 0) {
cparata	4:77faf76e3cd8	6883	index++;
cparata	4:77faf76e3cd8	6884	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]);
cparata	4:77faf76e3cd8	6885	}
cparata	4:77faf76e3cd8	6886
cparata	4:77faf76e3cd8	6887	return ret;
cparata	0:6d69e896ce38	6888	}
cparata	0:6d69e896ce38	6889
cparata	0:6d69e896ce38	6890	/**
cparata	0:6d69e896ce38	6891	* @brief Offset for hard-iron compensation register (r/w).[get]
cparata	0:6d69e896ce38	6892	*
cparata	0:6d69e896ce38	6893	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6894	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	6895	*
cparata	0:6d69e896ce38	6896	*/
cparata	0:6d69e896ce38	6897	int32_t lsm6dso_mag_offset_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6898	{
cparata	4:77faf76e3cd8	6899	int32_t ret;
cparata	4:77faf76e3cd8	6900	uint8_t index;
cparata	4:77faf76e3cd8	6901
cparata	4:77faf76e3cd8	6902	index = 0x00U;
cparata	4:77faf76e3cd8	6903	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]);
cparata	4:77faf76e3cd8	6904	if (ret == 0) {
cparata	4:77faf76e3cd8	6905	index++;
cparata	4:77faf76e3cd8	6906	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]);
cparata	4:77faf76e3cd8	6907	}
cparata	4:77faf76e3cd8	6908	if (ret == 0) {
cparata	4:77faf76e3cd8	6909	index++;
cparata	4:77faf76e3cd8	6910
cparata	4:77faf76e3cd8	6911	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]);
cparata	4:77faf76e3cd8	6912	}
cparata	4:77faf76e3cd8	6913	if (ret == 0) {
cparata	4:77faf76e3cd8	6914	index++;
cparata	4:77faf76e3cd8	6915	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]);
cparata	4:77faf76e3cd8	6916	}
cparata	4:77faf76e3cd8	6917	if (ret == 0) {
cparata	4:77faf76e3cd8	6918	index++;
cparata	4:77faf76e3cd8	6919
cparata	4:77faf76e3cd8	6920	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]);
cparata	4:77faf76e3cd8	6921	}
cparata	4:77faf76e3cd8	6922	if (ret == 0) {
cparata	4:77faf76e3cd8	6923	index++;
cparata	4:77faf76e3cd8	6924	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]);
cparata	4:77faf76e3cd8	6925	}
cparata	4:77faf76e3cd8	6926	return ret;
cparata	0:6d69e896ce38	6927	}
cparata	0:6d69e896ce38	6928
cparata	0:6d69e896ce38	6929	/**
cparata	0:6d69e896ce38	6930	* @brief Soft-iron (3x3 symmetric) matrix correction
cparata	0:6d69e896ce38	6931	* register (r/w). The value is expressed as
cparata	0:6d69e896ce38	6932	* half-precision floating-point format:
cparata	0:6d69e896ce38	6933	* SEEEEEFFFFFFFFFF
cparata	0:6d69e896ce38	6934	* S: 1 sign bit;
cparata	0:6d69e896ce38	6935	* E: 5 exponent bits;
cparata	0:6d69e896ce38	6936	* F: 10 fraction bits).[set]
cparata	0:6d69e896ce38	6937	*
cparata	0:6d69e896ce38	6938	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6939	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	6940	*
cparata	0:6d69e896ce38	6941	*/
cparata	0:6d69e896ce38	6942	int32_t lsm6dso_mag_soft_iron_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6943	{
cparata	4:77faf76e3cd8	6944	int32_t ret;
cparata	4:77faf76e3cd8	6945	uint8_t index;
cparata	4:77faf76e3cd8	6946
cparata	4:77faf76e3cd8	6947	index = 0x00U;
cparata	4:77faf76e3cd8	6948	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
cparata	4:77faf76e3cd8	6949	if (ret == 0) {
cparata	4:77faf76e3cd8	6950	index++;
cparata	4:77faf76e3cd8	6951	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
cparata	4:77faf76e3cd8	6952	}
cparata	4:77faf76e3cd8	6953	if (ret == 0) {
cparata	4:77faf76e3cd8	6954	index++;
cparata	4:77faf76e3cd8	6955
cparata	4:77faf76e3cd8	6956	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
cparata	4:77faf76e3cd8	6957	}
cparata	4:77faf76e3cd8	6958	if (ret == 0) {
cparata	4:77faf76e3cd8	6959	index++;
cparata	4:77faf76e3cd8	6960	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
cparata	4:77faf76e3cd8	6961	}
cparata	4:77faf76e3cd8	6962	if (ret == 0) {
cparata	4:77faf76e3cd8	6963	index++;
cparata	4:77faf76e3cd8	6964
cparata	4:77faf76e3cd8	6965	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
cparata	4:77faf76e3cd8	6966	}
cparata	4:77faf76e3cd8	6967	if (ret == 0) {
cparata	4:77faf76e3cd8	6968	index++;
cparata	4:77faf76e3cd8	6969	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
cparata	4:77faf76e3cd8	6970	}
cparata	4:77faf76e3cd8	6971	if (ret == 0) {
cparata	4:77faf76e3cd8	6972	index++;
cparata	4:77faf76e3cd8	6973
cparata	4:77faf76e3cd8	6974	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
cparata	4:77faf76e3cd8	6975	}
cparata	4:77faf76e3cd8	6976	if (ret == 0) {
cparata	4:77faf76e3cd8	6977	index++;
cparata	4:77faf76e3cd8	6978	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
cparata	4:77faf76e3cd8	6979	}
cparata	4:77faf76e3cd8	6980	if (ret == 0) {
cparata	4:77faf76e3cd8	6981	index++;
cparata	4:77faf76e3cd8	6982
cparata	4:77faf76e3cd8	6983	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
cparata	4:77faf76e3cd8	6984	}
cparata	4:77faf76e3cd8	6985	if (ret == 0) {
cparata	4:77faf76e3cd8	6986	index++;
cparata	4:77faf76e3cd8	6987	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
cparata	4:77faf76e3cd8	6988	}
cparata	4:77faf76e3cd8	6989	if (ret == 0) {
cparata	4:77faf76e3cd8	6990	index++;
cparata	4:77faf76e3cd8	6991
cparata	4:77faf76e3cd8	6992	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
cparata	4:77faf76e3cd8	6993	}
cparata	4:77faf76e3cd8	6994	if (ret == 0) {
cparata	4:77faf76e3cd8	6995	index++;
cparata	4:77faf76e3cd8	6996	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
cparata	4:77faf76e3cd8	6997	}
cparata	4:77faf76e3cd8	6998
cparata	4:77faf76e3cd8	6999	return ret;
cparata	0:6d69e896ce38	7000	}
cparata	0:6d69e896ce38	7001
cparata	0:6d69e896ce38	7002	/**
cparata	0:6d69e896ce38	7003	* @brief Soft-iron (3x3 symmetric) matrix
cparata	0:6d69e896ce38	7004	* correction register (r/w).
cparata	0:6d69e896ce38	7005	* The value is expressed as half-precision
cparata	0:6d69e896ce38	7006	* floating-point format:
cparata	0:6d69e896ce38	7007	* SEEEEEFFFFFFFFFF
cparata	0:6d69e896ce38	7008	* S: 1 sign bit;
cparata	0:6d69e896ce38	7009	* E: 5 exponent bits;
cparata	0:6d69e896ce38	7010	* F: 10 fraction bits.[get]
cparata	0:6d69e896ce38	7011	*
cparata	0:6d69e896ce38	7012	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7013	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7014	*
cparata	0:6d69e896ce38	7015	*/
cparata	0:6d69e896ce38	7016	int32_t lsm6dso_mag_soft_iron_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7017	{
cparata	4:77faf76e3cd8	7018	int32_t ret;
cparata	4:77faf76e3cd8	7019	uint8_t index;
cparata	4:77faf76e3cd8	7020
cparata	4:77faf76e3cd8	7021	index = 0x00U;
cparata	4:77faf76e3cd8	7022	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
cparata	4:77faf76e3cd8	7023	if (ret == 0) {
cparata	4:77faf76e3cd8	7024	index++;
cparata	4:77faf76e3cd8	7025	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
cparata	4:77faf76e3cd8	7026	}
cparata	4:77faf76e3cd8	7027	if (ret == 0) {
cparata	4:77faf76e3cd8	7028	index++;
cparata	4:77faf76e3cd8	7029
cparata	4:77faf76e3cd8	7030	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
cparata	4:77faf76e3cd8	7031	}
cparata	4:77faf76e3cd8	7032	if (ret == 0) {
cparata	4:77faf76e3cd8	7033	index++;
cparata	4:77faf76e3cd8	7034	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
cparata	4:77faf76e3cd8	7035	}
cparata	4:77faf76e3cd8	7036	if (ret == 0) {
cparata	4:77faf76e3cd8	7037	index++;
cparata	4:77faf76e3cd8	7038
cparata	4:77faf76e3cd8	7039	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
cparata	4:77faf76e3cd8	7040	}
cparata	4:77faf76e3cd8	7041	if (ret == 0) {
cparata	4:77faf76e3cd8	7042	index++;
cparata	4:77faf76e3cd8	7043	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
cparata	4:77faf76e3cd8	7044	}
cparata	4:77faf76e3cd8	7045	if (ret == 0) {
cparata	4:77faf76e3cd8	7046	index++;
cparata	4:77faf76e3cd8	7047
cparata	4:77faf76e3cd8	7048	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
cparata	4:77faf76e3cd8	7049	}
cparata	4:77faf76e3cd8	7050	if (ret == 0) {
cparata	4:77faf76e3cd8	7051	index++;
cparata	4:77faf76e3cd8	7052	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
cparata	4:77faf76e3cd8	7053	}
cparata	4:77faf76e3cd8	7054	if (ret == 0) {
cparata	4:77faf76e3cd8	7055	index++;
cparata	4:77faf76e3cd8	7056
cparata	4:77faf76e3cd8	7057	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
cparata	4:77faf76e3cd8	7058	}
cparata	4:77faf76e3cd8	7059	if (ret == 0) {
cparata	4:77faf76e3cd8	7060	index++;
cparata	4:77faf76e3cd8	7061	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
cparata	4:77faf76e3cd8	7062	}
cparata	4:77faf76e3cd8	7063	if (ret == 0) {
cparata	4:77faf76e3cd8	7064	index++;
cparata	4:77faf76e3cd8	7065
cparata	4:77faf76e3cd8	7066	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
cparata	4:77faf76e3cd8	7067	}
cparata	4:77faf76e3cd8	7068	if (ret == 0) {
cparata	4:77faf76e3cd8	7069	index++;
cparata	4:77faf76e3cd8	7070	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
cparata	4:77faf76e3cd8	7071	}
cparata	4:77faf76e3cd8	7072
cparata	4:77faf76e3cd8	7073	return ret;
cparata	0:6d69e896ce38	7074	}
cparata	0:6d69e896ce38	7075
cparata	0:6d69e896ce38	7076	/**
cparata	0:6d69e896ce38	7077	* @brief Magnetometer Z-axis coordinates
cparata	0:6d69e896ce38	7078	* rotation (to be aligned to
cparata	0:6d69e896ce38	7079	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7080	* orientation).[set]
cparata	0:6d69e896ce38	7081	*
cparata	0:6d69e896ce38	7082	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7083	* @param val change the values of mag_z_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7084	*
cparata	0:6d69e896ce38	7085	*/
cparata	0:6d69e896ce38	7086	int32_t lsm6dso_mag_z_orient_set(lsm6dso_ctx_t *ctx, lsm6dso_mag_z_axis_t val)
cparata	0:6d69e896ce38	7087	{
cparata	4:77faf76e3cd8	7088	lsm6dso_mag_cfg_a_t reg;
cparata	4:77faf76e3cd8	7089	int32_t ret;
cparata	4:77faf76e3cd8	7090
cparata	4:77faf76e3cd8	7091	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	7092	if (ret == 0) {
cparata	4:77faf76e3cd8	7093	reg.mag_z_axis = (uint8_t) val;
cparata	4:77faf76e3cd8	7094	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	7095	}
cparata	4:77faf76e3cd8	7096
cparata	4:77faf76e3cd8	7097	return ret;
cparata	0:6d69e896ce38	7098	}
cparata	0:6d69e896ce38	7099
cparata	0:6d69e896ce38	7100	/**
cparata	0:6d69e896ce38	7101	* @brief Magnetometer Z-axis coordinates
cparata	0:6d69e896ce38	7102	* rotation (to be aligned to
cparata	0:6d69e896ce38	7103	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7104	* orientation).[get]
cparata	0:6d69e896ce38	7105	*
cparata	0:6d69e896ce38	7106	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7107	* @param val Get the values of mag_z_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7108	*
cparata	0:6d69e896ce38	7109	*/
cparata	0:6d69e896ce38	7110	int32_t lsm6dso_mag_z_orient_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7111	lsm6dso_mag_z_axis_t *val)
cparata	0:6d69e896ce38	7112	{
cparata	4:77faf76e3cd8	7113	lsm6dso_mag_cfg_a_t reg;
cparata	4:77faf76e3cd8	7114	int32_t ret;
cparata	4:77faf76e3cd8	7115	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	7116	switch (reg.mag_z_axis) {
cparata	4:77faf76e3cd8	7117	case LSM6DSO_Z_EQ_Y:
cparata	4:77faf76e3cd8	7118	*val = LSM6DSO_Z_EQ_Y;
cparata	4:77faf76e3cd8	7119	break;
cparata	4:77faf76e3cd8	7120	case LSM6DSO_Z_EQ_MIN_Y:
cparata	4:77faf76e3cd8	7121	*val = LSM6DSO_Z_EQ_MIN_Y;
cparata	4:77faf76e3cd8	7122	break;
cparata	4:77faf76e3cd8	7123	case LSM6DSO_Z_EQ_X:
cparata	4:77faf76e3cd8	7124	*val = LSM6DSO_Z_EQ_X;
cparata	4:77faf76e3cd8	7125	break;
cparata	4:77faf76e3cd8	7126	case LSM6DSO_Z_EQ_MIN_X:
cparata	4:77faf76e3cd8	7127	*val = LSM6DSO_Z_EQ_MIN_X;
cparata	4:77faf76e3cd8	7128	break;
cparata	4:77faf76e3cd8	7129	case LSM6DSO_Z_EQ_MIN_Z:
cparata	4:77faf76e3cd8	7130	*val = LSM6DSO_Z_EQ_MIN_Z;
cparata	4:77faf76e3cd8	7131	break;
cparata	4:77faf76e3cd8	7132	case LSM6DSO_Z_EQ_Z:
cparata	4:77faf76e3cd8	7133	*val = LSM6DSO_Z_EQ_Z;
cparata	4:77faf76e3cd8	7134	break;
cparata	4:77faf76e3cd8	7135	default:
cparata	4:77faf76e3cd8	7136	*val = LSM6DSO_Z_EQ_Y;
cparata	4:77faf76e3cd8	7137	break;
cparata	4:77faf76e3cd8	7138	}
cparata	4:77faf76e3cd8	7139	return ret;
cparata	0:6d69e896ce38	7140	}
cparata	0:6d69e896ce38	7141
cparata	0:6d69e896ce38	7142	/**
cparata	0:6d69e896ce38	7143	* @brief Magnetometer Y-axis coordinates
cparata	0:6d69e896ce38	7144	* rotation (to be aligned to
cparata	0:6d69e896ce38	7145	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7146	* orientation).[set]
cparata	0:6d69e896ce38	7147	*
cparata	0:6d69e896ce38	7148	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7149	* @param val change the values of mag_y_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7150	*
cparata	0:6d69e896ce38	7151	*/
cparata	0:6d69e896ce38	7152	int32_t lsm6dso_mag_y_orient_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7153	lsm6dso_mag_y_axis_t val)
cparata	0:6d69e896ce38	7154	{
cparata	4:77faf76e3cd8	7155	lsm6dso_mag_cfg_a_t reg;
cparata	4:77faf76e3cd8	7156	int32_t ret;
cparata	4:77faf76e3cd8	7157
cparata	4:77faf76e3cd8	7158	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	7159	if (ret == 0) {
cparata	4:77faf76e3cd8	7160	reg.mag_y_axis = (uint8_t)val;
cparata	4:77faf76e3cd8	7161	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,(uint8_t*) &reg);
cparata	4:77faf76e3cd8	7162	}
cparata	4:77faf76e3cd8	7163	return ret;
cparata	0:6d69e896ce38	7164	}
cparata	0:6d69e896ce38	7165
cparata	0:6d69e896ce38	7166	/**
cparata	0:6d69e896ce38	7167	* @brief Magnetometer Y-axis coordinates
cparata	0:6d69e896ce38	7168	* rotation (to be aligned to
cparata	0:6d69e896ce38	7169	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7170	* orientation).[get]
cparata	0:6d69e896ce38	7171	*
cparata	0:6d69e896ce38	7172	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7173	* @param val Get the values of mag_y_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7174	*
cparata	0:6d69e896ce38	7175	*/
cparata	0:6d69e896ce38	7176	int32_t lsm6dso_mag_y_orient_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7177	lsm6dso_mag_y_axis_t *val)
cparata	0:6d69e896ce38	7178	{
cparata	4:77faf76e3cd8	7179	lsm6dso_mag_cfg_a_t reg;
cparata	4:77faf76e3cd8	7180	int32_t ret;
cparata	4:77faf76e3cd8	7181
cparata	4:77faf76e3cd8	7182	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	7183	switch (reg.mag_y_axis) {
cparata	4:77faf76e3cd8	7184	case LSM6DSO_Y_EQ_Y:
cparata	4:77faf76e3cd8	7185	*val = LSM6DSO_Y_EQ_Y;
cparata	4:77faf76e3cd8	7186	break;
cparata	4:77faf76e3cd8	7187	case LSM6DSO_Y_EQ_MIN_Y:
cparata	4:77faf76e3cd8	7188	*val = LSM6DSO_Y_EQ_MIN_Y;
cparata	4:77faf76e3cd8	7189	break;
cparata	4:77faf76e3cd8	7190	case LSM6DSO_Y_EQ_X:
cparata	4:77faf76e3cd8	7191	*val = LSM6DSO_Y_EQ_X;
cparata	4:77faf76e3cd8	7192	break;
cparata	4:77faf76e3cd8	7193	case LSM6DSO_Y_EQ_MIN_X:
cparata	4:77faf76e3cd8	7194	*val = LSM6DSO_Y_EQ_MIN_X;
cparata	4:77faf76e3cd8	7195	break;
cparata	4:77faf76e3cd8	7196	case LSM6DSO_Y_EQ_MIN_Z:
cparata	4:77faf76e3cd8	7197	*val = LSM6DSO_Y_EQ_MIN_Z;
cparata	4:77faf76e3cd8	7198	break;
cparata	4:77faf76e3cd8	7199	case LSM6DSO_Y_EQ_Z:
cparata	4:77faf76e3cd8	7200	*val = LSM6DSO_Y_EQ_Z;
cparata	4:77faf76e3cd8	7201	break;
cparata	4:77faf76e3cd8	7202	default:
cparata	4:77faf76e3cd8	7203	*val = LSM6DSO_Y_EQ_Y;
cparata	4:77faf76e3cd8	7204	break;
cparata	4:77faf76e3cd8	7205	}
cparata	4:77faf76e3cd8	7206	return ret;
cparata	0:6d69e896ce38	7207	}
cparata	0:6d69e896ce38	7208
cparata	0:6d69e896ce38	7209	/**
cparata	0:6d69e896ce38	7210	* @brief Magnetometer X-axis coordinates
cparata	0:6d69e896ce38	7211	* rotation (to be aligned to
cparata	0:6d69e896ce38	7212	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7213	* orientation).[set]
cparata	0:6d69e896ce38	7214	*
cparata	0:6d69e896ce38	7215	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7216	* @param val change the values of mag_x_axis in reg MAG_CFG_B
cparata	0:6d69e896ce38	7217	*
cparata	0:6d69e896ce38	7218	*/
cparata	0:6d69e896ce38	7219	int32_t lsm6dso_mag_x_orient_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7220	lsm6dso_mag_x_axis_t val)
cparata	0:6d69e896ce38	7221	{
cparata	4:77faf76e3cd8	7222	lsm6dso_mag_cfg_b_t reg;
cparata	4:77faf76e3cd8	7223	int32_t ret;
cparata	4:77faf76e3cd8	7224
cparata	4:77faf76e3cd8	7225	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	7226	if (ret == 0) {
cparata	4:77faf76e3cd8	7227	reg.mag_x_axis = (uint8_t)val;
cparata	4:77faf76e3cd8	7228	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	7229	}
cparata	4:77faf76e3cd8	7230	return ret;
cparata	0:6d69e896ce38	7231	}
cparata	0:6d69e896ce38	7232
cparata	0:6d69e896ce38	7233	/**
cparata	0:6d69e896ce38	7234	* @brief Magnetometer X-axis coordinates
cparata	0:6d69e896ce38	7235	* rotation (to be aligned to
cparata	0:6d69e896ce38	7236	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7237	* orientation).[get]
cparata	0:6d69e896ce38	7238	*
cparata	0:6d69e896ce38	7239	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7240	* @param val Get the values of mag_x_axis in reg MAG_CFG_B
cparata	0:6d69e896ce38	7241	*
cparata	0:6d69e896ce38	7242	*/
cparata	0:6d69e896ce38	7243	int32_t lsm6dso_mag_x_orient_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7244	lsm6dso_mag_x_axis_t *val)
cparata	0:6d69e896ce38	7245	{
cparata	4:77faf76e3cd8	7246	lsm6dso_mag_cfg_b_t reg;
cparata	4:77faf76e3cd8	7247	int32_t ret;
cparata	4:77faf76e3cd8	7248
cparata	4:77faf76e3cd8	7249	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)&reg);
cparata	4:77faf76e3cd8	7250	switch (reg.mag_x_axis) {
cparata	4:77faf76e3cd8	7251	case LSM6DSO_X_EQ_Y:
cparata	4:77faf76e3cd8	7252	*val = LSM6DSO_X_EQ_Y;
cparata	4:77faf76e3cd8	7253	break;
cparata	4:77faf76e3cd8	7254	case LSM6DSO_X_EQ_MIN_Y:
cparata	4:77faf76e3cd8	7255	*val = LSM6DSO_X_EQ_MIN_Y;
cparata	4:77faf76e3cd8	7256	break;
cparata	4:77faf76e3cd8	7257	case LSM6DSO_X_EQ_X:
cparata	4:77faf76e3cd8	7258	*val = LSM6DSO_X_EQ_X;
cparata	4:77faf76e3cd8	7259	break;
cparata	4:77faf76e3cd8	7260	case LSM6DSO_X_EQ_MIN_X:
cparata	4:77faf76e3cd8	7261	*val = LSM6DSO_X_EQ_MIN_X;
cparata	4:77faf76e3cd8	7262	break;
cparata	4:77faf76e3cd8	7263	case LSM6DSO_X_EQ_MIN_Z:
cparata	4:77faf76e3cd8	7264	*val = LSM6DSO_X_EQ_MIN_Z;
cparata	4:77faf76e3cd8	7265	break;
cparata	4:77faf76e3cd8	7266	case LSM6DSO_X_EQ_Z:
cparata	4:77faf76e3cd8	7267	*val = LSM6DSO_X_EQ_Z;
cparata	4:77faf76e3cd8	7268	break;
cparata	4:77faf76e3cd8	7269	default:
cparata	4:77faf76e3cd8	7270	*val = LSM6DSO_X_EQ_Y;
cparata	4:77faf76e3cd8	7271	break;
cparata	4:77faf76e3cd8	7272	}
cparata	4:77faf76e3cd8	7273	return ret;
cparata	0:6d69e896ce38	7274	}
cparata	0:6d69e896ce38	7275
cparata	0:6d69e896ce38	7276	/**
cparata	0:6d69e896ce38	7277	* @}
cparata	0:6d69e896ce38	7278	*
cparata	0:6d69e896ce38	7279	*/
cparata	0:6d69e896ce38	7280
cparata	0:6d69e896ce38	7281	/**
cparata	4:77faf76e3cd8	7282	* @defgroup LSM6DSO_finite_state_machine
cparata	0:6d69e896ce38	7283	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	7284	* state_machine.
cparata	0:6d69e896ce38	7285	* @{
cparata	0:6d69e896ce38	7286	*
cparata	0:6d69e896ce38	7287	*/
cparata	0:6d69e896ce38	7288
cparata	0:6d69e896ce38	7289	/**
cparata	0:6d69e896ce38	7290	* @brief Interrupt status bit for FSM long counter
cparata	0:6d69e896ce38	7291	* timeout interrupt event.[get]
cparata	0:6d69e896ce38	7292	*
cparata	0:6d69e896ce38	7293	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7294	* @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	7295	*
cparata	0:6d69e896ce38	7296	*/
cparata	0:6d69e896ce38	7297	int32_t lsm6dso_long_cnt_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7298	{
cparata	4:77faf76e3cd8	7299	lsm6dso_emb_func_status_t reg;
cparata	4:77faf76e3cd8	7300	int32_t ret;
cparata	4:77faf76e3cd8	7301
cparata	4:77faf76e3cd8	7302	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7303	if (ret == 0) {
cparata	4:77faf76e3cd8	7304	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7305	}
cparata	4:77faf76e3cd8	7306	if (ret == 0) {
cparata	4:77faf76e3cd8	7307	*val = reg.is_fsm_lc;
cparata	4:77faf76e3cd8	7308	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7309	}
cparata	4:77faf76e3cd8	7310	return ret;
cparata	0:6d69e896ce38	7311	}
cparata	0:6d69e896ce38	7312
cparata	0:6d69e896ce38	7313	/**
cparata	0:6d69e896ce38	7314	* @brief Final State Machine enable.[set]
cparata	0:6d69e896ce38	7315	*
cparata	0:6d69e896ce38	7316	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7317	* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata	0:6d69e896ce38	7318	*
cparata	0:6d69e896ce38	7319	*/
cparata	0:6d69e896ce38	7320	int32_t lsm6dso_fsm_enable_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7321	lsm6dso_emb_fsm_enable_t *val)
cparata	0:6d69e896ce38	7322	{
cparata	4:77faf76e3cd8	7323	int32_t ret;
cparata	4:77faf76e3cd8	7324
cparata	4:77faf76e3cd8	7325	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7326	if (ret == 0) {
cparata	4:77faf76e3cd8	7327	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A,
cparata	4:77faf76e3cd8	7328	(uint8_t*)&val->fsm_enable_a, 1);
cparata	4:77faf76e3cd8	7329	}
cparata	4:77faf76e3cd8	7330	if (ret == 0) {
cparata	4:77faf76e3cd8	7331	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B,
cparata	4:77faf76e3cd8	7332	(uint8_t*)&val->fsm_enable_b, 1);
cparata	4:77faf76e3cd8	7333	}
cparata	4:77faf76e3cd8	7334	if (ret == 0) {
cparata	4:77faf76e3cd8	7335	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7336	}
cparata	4:77faf76e3cd8	7337
cparata	4:77faf76e3cd8	7338	return ret;
cparata	0:6d69e896ce38	7339	}
cparata	0:6d69e896ce38	7340
cparata	0:6d69e896ce38	7341	/**
cparata	0:6d69e896ce38	7342	* @brief Final State Machine enable.[get]
cparata	0:6d69e896ce38	7343	*
cparata	0:6d69e896ce38	7344	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7345	* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata	0:6d69e896ce38	7346	*
cparata	0:6d69e896ce38	7347	*/
cparata	0:6d69e896ce38	7348	int32_t lsm6dso_fsm_enable_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7349	lsm6dso_emb_fsm_enable_t *val)
cparata	0:6d69e896ce38	7350	{
cparata	4:77faf76e3cd8	7351	int32_t ret;
cparata	4:77faf76e3cd8	7352
cparata	4:77faf76e3cd8	7353	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7354	if (ret == 0) {
cparata	4:77faf76e3cd8	7355	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t*) val, 2);
cparata	4:77faf76e3cd8	7356	}
cparata	4:77faf76e3cd8	7357	if (ret == 0) {
cparata	4:77faf76e3cd8	7358	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7359	}
cparata	4:77faf76e3cd8	7360	return ret;
cparata	0:6d69e896ce38	7361	}
cparata	0:6d69e896ce38	7362
cparata	0:6d69e896ce38	7363	/**
cparata	0:6d69e896ce38	7364	* @brief FSM long counter status register. Long counter value is an
cparata	0:6d69e896ce38	7365	* unsigned integer value (16-bit format).[set]
cparata	0:6d69e896ce38	7366	*
cparata	0:6d69e896ce38	7367	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7368	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	7369	*
cparata	0:6d69e896ce38	7370	*/
cparata	0:6d69e896ce38	7371	int32_t lsm6dso_long_cnt_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7372	{
cparata	4:77faf76e3cd8	7373	int32_t ret;
cparata	4:77faf76e3cd8	7374
cparata	4:77faf76e3cd8	7375	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7376	if (ret == 0) {
cparata	4:77faf76e3cd8	7377	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
cparata	4:77faf76e3cd8	7378	}
cparata	4:77faf76e3cd8	7379	if (ret == 0) {
cparata	4:77faf76e3cd8	7380	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7381	}
cparata	4:77faf76e3cd8	7382
cparata	4:77faf76e3cd8	7383	return ret;
cparata	0:6d69e896ce38	7384	}
cparata	0:6d69e896ce38	7385
cparata	0:6d69e896ce38	7386	/**
cparata	0:6d69e896ce38	7387	* @brief FSM long counter status register. Long counter value is an
cparata	0:6d69e896ce38	7388	* unsigned integer value (16-bit format).[get]
cparata	0:6d69e896ce38	7389	*
cparata	0:6d69e896ce38	7390	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7391	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7392	*
cparata	0:6d69e896ce38	7393	*/
cparata	0:6d69e896ce38	7394	int32_t lsm6dso_long_cnt_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7395	{
cparata	4:77faf76e3cd8	7396	int32_t ret;
cparata	4:77faf76e3cd8	7397
cparata	4:77faf76e3cd8	7398	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7399	if (ret == 0) {
cparata	4:77faf76e3cd8	7400	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
cparata	4:77faf76e3cd8	7401	}
cparata	4:77faf76e3cd8	7402	if (ret == 0) {
cparata	4:77faf76e3cd8	7403	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7404	}
cparata	4:77faf76e3cd8	7405
cparata	4:77faf76e3cd8	7406	return ret;
cparata	0:6d69e896ce38	7407	}
cparata	0:6d69e896ce38	7408
cparata	0:6d69e896ce38	7409	/**
cparata	0:6d69e896ce38	7410	* @brief Clear FSM long counter value.[set]
cparata	0:6d69e896ce38	7411	*
cparata	0:6d69e896ce38	7412	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7413	* @param val change the values of fsm_lc_clr in
cparata	0:6d69e896ce38	7414	* reg FSM_LONG_COUNTER_CLEAR
cparata	0:6d69e896ce38	7415	*
cparata	0:6d69e896ce38	7416	*/
cparata	0:6d69e896ce38	7417	int32_t lsm6dso_long_clr_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val)
cparata	0:6d69e896ce38	7418	{
cparata	4:77faf76e3cd8	7419	lsm6dso_fsm_long_counter_clear_t reg;
cparata	4:77faf76e3cd8	7420	int32_t ret;
cparata	4:77faf76e3cd8	7421
cparata	4:77faf76e3cd8	7422	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7423	if (ret == 0) {
cparata	4:77faf76e3cd8	7424	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
cparata	4:77faf76e3cd8	7425	(uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7426	}
cparata	4:77faf76e3cd8	7427	if (ret == 0) {
cparata	4:77faf76e3cd8	7428	reg. fsm_lc_clr = (uint8_t)val;
cparata	4:77faf76e3cd8	7429	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
cparata	4:77faf76e3cd8	7430	(uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7431	}
cparata	4:77faf76e3cd8	7432	if (ret == 0) {
cparata	4:77faf76e3cd8	7433	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7434	}
cparata	4:77faf76e3cd8	7435	return ret;
cparata	0:6d69e896ce38	7436	}
cparata	0:6d69e896ce38	7437
cparata	0:6d69e896ce38	7438	/**
cparata	0:6d69e896ce38	7439	* @brief Clear FSM long counter value.[get]
cparata	0:6d69e896ce38	7440	*
cparata	0:6d69e896ce38	7441	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7442	* @param val Get the values of fsm_lc_clr in
cparata	0:6d69e896ce38	7443	* reg FSM_LONG_COUNTER_CLEAR
cparata	0:6d69e896ce38	7444	*
cparata	0:6d69e896ce38	7445	*/
cparata	0:6d69e896ce38	7446	int32_t lsm6dso_long_clr_get(lsm6dso_ctx_t ctx, lsm6dso_fsm_lc_clr_t val)
cparata	0:6d69e896ce38	7447	{
cparata	4:77faf76e3cd8	7448	lsm6dso_fsm_long_counter_clear_t reg;
cparata	4:77faf76e3cd8	7449	int32_t ret;
cparata	4:77faf76e3cd8	7450
cparata	4:77faf76e3cd8	7451	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7452	if (ret == 0) {
cparata	4:77faf76e3cd8	7453	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
cparata	4:77faf76e3cd8	7454	(uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7455	}
cparata	4:77faf76e3cd8	7456	if (ret == 0) {
cparata	4:77faf76e3cd8	7457	switch (reg.fsm_lc_clr) {
cparata	4:77faf76e3cd8	7458	case LSM6DSO_LC_NORMAL:
cparata	4:77faf76e3cd8	7459	*val = LSM6DSO_LC_NORMAL;
cparata	4:77faf76e3cd8	7460	break;
cparata	4:77faf76e3cd8	7461	case LSM6DSO_LC_CLEAR:
cparata	4:77faf76e3cd8	7462	*val = LSM6DSO_LC_CLEAR;
cparata	4:77faf76e3cd8	7463	break;
cparata	4:77faf76e3cd8	7464	case LSM6DSO_LC_CLEAR_DONE:
cparata	4:77faf76e3cd8	7465	*val = LSM6DSO_LC_CLEAR_DONE;
cparata	4:77faf76e3cd8	7466	break;
cparata	4:77faf76e3cd8	7467	default:
cparata	4:77faf76e3cd8	7468	*val = LSM6DSO_LC_NORMAL;
cparata	4:77faf76e3cd8	7469	break;
cparata	3:4274d9103f1d	7470	}
cparata	4:77faf76e3cd8	7471	}
cparata	4:77faf76e3cd8	7472
cparata	4:77faf76e3cd8	7473	if (ret == 0) {
cparata	4:77faf76e3cd8	7474	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7475	}
cparata	4:77faf76e3cd8	7476
cparata	4:77faf76e3cd8	7477	return ret;
cparata	0:6d69e896ce38	7478	}
cparata	0:6d69e896ce38	7479
cparata	0:6d69e896ce38	7480	/**
cparata	0:6d69e896ce38	7481	* @brief FSM output registers[get]
cparata	0:6d69e896ce38	7482	*
cparata	0:6d69e896ce38	7483	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7484	* @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
cparata	0:6d69e896ce38	7485	*
cparata	0:6d69e896ce38	7486	*/
cparata	0:6d69e896ce38	7487	int32_t lsm6dso_fsm_out_get(lsm6dso_ctx_t ctx, lsm6dso_fsm_out_t val)
cparata	0:6d69e896ce38	7488	{
cparata	4:77faf76e3cd8	7489	int32_t ret;
cparata	4:77faf76e3cd8	7490
cparata	4:77faf76e3cd8	7491	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7492	if (ret == 0) {
cparata	4:77faf76e3cd8	7493	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t*)val, 16);
cparata	4:77faf76e3cd8	7494	}
cparata	4:77faf76e3cd8	7495	if (ret == 0) {
cparata	4:77faf76e3cd8	7496	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7497	}
cparata	4:77faf76e3cd8	7498
cparata	4:77faf76e3cd8	7499	return ret;
cparata	0:6d69e896ce38	7500	}
cparata	0:6d69e896ce38	7501
cparata	0:6d69e896ce38	7502	/**
cparata	0:6d69e896ce38	7503	* @brief Finite State Machine ODR configuration.[set]
cparata	0:6d69e896ce38	7504	*
cparata	0:6d69e896ce38	7505	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7506	* @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata	0:6d69e896ce38	7507	*
cparata	0:6d69e896ce38	7508	*/
cparata	0:6d69e896ce38	7509	int32_t lsm6dso_fsm_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_odr_t val)
cparata	0:6d69e896ce38	7510	{
cparata	4:77faf76e3cd8	7511	lsm6dso_emb_func_odr_cfg_b_t reg;
cparata	4:77faf76e3cd8	7512	int32_t ret;
cparata	4:77faf76e3cd8	7513
cparata	4:77faf76e3cd8	7514	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7515	if (ret == 0) {
cparata	4:77faf76e3cd8	7516	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
cparata	4:77faf76e3cd8	7517	(uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7518	}
cparata	4:77faf76e3cd8	7519	if (ret == 0) {
cparata	4:77faf76e3cd8	7520	reg.not_used_01 = 3; /* set default values */
cparata	4:77faf76e3cd8	7521	reg.not_used_02 = 2; /* set default values */
cparata	4:77faf76e3cd8	7522	reg.fsm_odr = (uint8_t)val;
cparata	4:77faf76e3cd8	7523	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
cparata	4:77faf76e3cd8	7524	(uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7525	}
cparata	4:77faf76e3cd8	7526	if (ret == 0) {
cparata	4:77faf76e3cd8	7527	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7528	}
cparata	4:77faf76e3cd8	7529	return ret;
cparata	0:6d69e896ce38	7530	}
cparata	0:6d69e896ce38	7531
cparata	0:6d69e896ce38	7532	/**
cparata	0:6d69e896ce38	7533	* @brief Finite State Machine ODR configuration.[get]
cparata	0:6d69e896ce38	7534	*
cparata	0:6d69e896ce38	7535	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7536	* @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata	0:6d69e896ce38	7537	*
cparata	0:6d69e896ce38	7538	*/
cparata	0:6d69e896ce38	7539	int32_t lsm6dso_fsm_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_fsm_odr_t val)
cparata	0:6d69e896ce38	7540	{
cparata	4:77faf76e3cd8	7541	lsm6dso_emb_func_odr_cfg_b_t reg;
cparata	4:77faf76e3cd8	7542	int32_t ret;
cparata	4:77faf76e3cd8	7543
cparata	4:77faf76e3cd8	7544	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7545	if (ret == 0) {
cparata	4:77faf76e3cd8	7546	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
cparata	4:77faf76e3cd8	7547	(uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7548	}
cparata	4:77faf76e3cd8	7549	if (ret == 0) {
cparata	4:77faf76e3cd8	7550	switch (reg.fsm_odr) {
cparata	4:77faf76e3cd8	7551	case LSM6DSO_ODR_FSM_12Hz5:
cparata	4:77faf76e3cd8	7552	*val = LSM6DSO_ODR_FSM_12Hz5;
cparata	4:77faf76e3cd8	7553	break;
cparata	4:77faf76e3cd8	7554	case LSM6DSO_ODR_FSM_26Hz:
cparata	4:77faf76e3cd8	7555	*val = LSM6DSO_ODR_FSM_26Hz;
cparata	4:77faf76e3cd8	7556	break;
cparata	4:77faf76e3cd8	7557	case LSM6DSO_ODR_FSM_52Hz:
cparata	4:77faf76e3cd8	7558	*val = LSM6DSO_ODR_FSM_52Hz;
cparata	4:77faf76e3cd8	7559	break;
cparata	4:77faf76e3cd8	7560	case LSM6DSO_ODR_FSM_104Hz:
cparata	4:77faf76e3cd8	7561	*val = LSM6DSO_ODR_FSM_104Hz;
cparata	4:77faf76e3cd8	7562	break;
cparata	4:77faf76e3cd8	7563	default:
cparata	4:77faf76e3cd8	7564	*val = LSM6DSO_ODR_FSM_12Hz5;
cparata	4:77faf76e3cd8	7565	break;
cparata	3:4274d9103f1d	7566	}
cparata	4:77faf76e3cd8	7567	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7568	}
cparata	4:77faf76e3cd8	7569
cparata	4:77faf76e3cd8	7570	return ret;
cparata	0:6d69e896ce38	7571	}
cparata	0:6d69e896ce38	7572
cparata	0:6d69e896ce38	7573	/**
cparata	0:6d69e896ce38	7574	* @brief FSM initialization request.[set]
cparata	0:6d69e896ce38	7575	*
cparata	0:6d69e896ce38	7576	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7577	* @param val change the values of fsm_init in reg FSM_INIT
cparata	0:6d69e896ce38	7578	*
cparata	0:6d69e896ce38	7579	*/
cparata	0:6d69e896ce38	7580	int32_t lsm6dso_fsm_init_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	7581	{
cparata	4:77faf76e3cd8	7582	lsm6dso_emb_func_init_b_t reg;
cparata	4:77faf76e3cd8	7583	int32_t ret;
cparata	4:77faf76e3cd8	7584
cparata	4:77faf76e3cd8	7585	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7586	if (ret == 0) {
cparata	4:77faf76e3cd8	7587	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7588	}
cparata	4:77faf76e3cd8	7589	if (ret == 0) {
cparata	4:77faf76e3cd8	7590	reg.fsm_init = val;
cparata	4:77faf76e3cd8	7591	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7592	}
cparata	4:77faf76e3cd8	7593	if (ret == 0) {
cparata	4:77faf76e3cd8	7594	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7595	}
cparata	4:77faf76e3cd8	7596
cparata	4:77faf76e3cd8	7597	return ret;
cparata	0:6d69e896ce38	7598	}
cparata	0:6d69e896ce38	7599
cparata	0:6d69e896ce38	7600	/**
cparata	0:6d69e896ce38	7601	* @brief FSM initialization request.[get]
cparata	0:6d69e896ce38	7602	*
cparata	0:6d69e896ce38	7603	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7604	* @param val change the values of fsm_init in reg FSM_INIT
cparata	0:6d69e896ce38	7605	*
cparata	0:6d69e896ce38	7606	*/
cparata	0:6d69e896ce38	7607	int32_t lsm6dso_fsm_init_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7608	{
cparata	4:77faf76e3cd8	7609	lsm6dso_emb_func_init_b_t reg;
cparata	4:77faf76e3cd8	7610	int32_t ret;
cparata	4:77faf76e3cd8	7611
cparata	4:77faf76e3cd8	7612	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	7613	if (ret == 0) {
cparata	4:77faf76e3cd8	7614	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7615	}
cparata	4:77faf76e3cd8	7616	if (ret == 0) {
cparata	4:77faf76e3cd8	7617	*val = reg.fsm_init;
cparata	4:77faf76e3cd8	7618	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7619	}
cparata	4:77faf76e3cd8	7620	return ret;
cparata	0:6d69e896ce38	7621	}
cparata	0:6d69e896ce38	7622
cparata	0:6d69e896ce38	7623	/**
cparata	0:6d69e896ce38	7624	* @brief FSM long counter timeout register (r/w). The long counter
cparata	0:6d69e896ce38	7625	* timeout value is an unsigned integer value (16-bit format).
cparata	0:6d69e896ce38	7626	* When the long counter value reached this value,
cparata	0:6d69e896ce38	7627	* the FSM generates an interrupt.[set]
cparata	0:6d69e896ce38	7628	*
cparata	0:6d69e896ce38	7629	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	7630	* @param val the value of long counter
cparata	2:4d14e9edf37e	7631	*
cparata	2:4d14e9edf37e	7632	*/
cparata	2:4d14e9edf37e	7633	int32_t lsm6dso_long_cnt_int_value_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	2:4d14e9edf37e	7634	{
cparata	4:77faf76e3cd8	7635	int32_t ret;
cparata	4:77faf76e3cd8	7636	uint8_t add_l;
cparata	4:77faf76e3cd8	7637	uint8_t add_h;
cparata	4:77faf76e3cd8	7638
cparata	4:77faf76e3cd8	7639	add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
cparata	4:77faf76e3cd8	7640	add_l = (uint8_t)( val & 0x00FFU );
cparata	4:77faf76e3cd8	7641
cparata	4:77faf76e3cd8	7642	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l);
cparata	4:77faf76e3cd8	7643	if (ret == 0) {
cparata	4:77faf76e3cd8	7644	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h);
cparata	4:77faf76e3cd8	7645	}
cparata	4:77faf76e3cd8	7646
cparata	4:77faf76e3cd8	7647	return ret;
cparata	0:6d69e896ce38	7648	}
cparata	0:6d69e896ce38	7649
cparata	0:6d69e896ce38	7650	/**
cparata	0:6d69e896ce38	7651	* @brief FSM long counter timeout register (r/w). The long counter
cparata	0:6d69e896ce38	7652	* timeout value is an unsigned integer value (16-bit format).
cparata	0:6d69e896ce38	7653	* When the long counter value reached this value,
cparata	0:6d69e896ce38	7654	* the FSM generates an interrupt.[get]
cparata	0:6d69e896ce38	7655	*
cparata	2:4d14e9edf37e	7656	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	7657	* @param val buffer that stores the value of long counter
cparata	2:4d14e9edf37e	7658	*
cparata	2:4d14e9edf37e	7659	*/
cparata	2:4d14e9edf37e	7660	int32_t lsm6dso_long_cnt_int_value_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	2:4d14e9edf37e	7661	{
cparata	4:77faf76e3cd8	7662	int32_t ret;
cparata	4:77faf76e3cd8	7663	uint8_t add_l;
cparata	4:77faf76e3cd8	7664	uint8_t add_h;
cparata	4:77faf76e3cd8	7665
cparata	4:77faf76e3cd8	7666	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l);
cparata	4:77faf76e3cd8	7667	if (ret == 0) {
cparata	4:77faf76e3cd8	7668	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h);
cparata	4:77faf76e3cd8	7669	*val = add_h;
cparata	4:77faf76e3cd8	7670	val = val << 8;
cparata	4:77faf76e3cd8	7671	*val += add_l;
cparata	4:77faf76e3cd8	7672	}
cparata	4:77faf76e3cd8	7673
cparata	4:77faf76e3cd8	7674	return ret;
cparata	0:6d69e896ce38	7675	}
cparata	0:6d69e896ce38	7676
cparata	0:6d69e896ce38	7677	/**
cparata	0:6d69e896ce38	7678	* @brief FSM number of programs register.[set]
cparata	0:6d69e896ce38	7679	*
cparata	0:6d69e896ce38	7680	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	7681	* @param val value to write
cparata	2:4d14e9edf37e	7682	*
cparata	2:4d14e9edf37e	7683	*/
cparata	2:4d14e9edf37e	7684	int32_t lsm6dso_fsm_number_of_programs_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	2:4d14e9edf37e	7685	{
cparata	4:77faf76e3cd8	7686	int32_t ret;
cparata	4:77faf76e3cd8	7687
cparata	4:77faf76e3cd8	7688	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_PROGRAMS, &val);
cparata	4:77faf76e3cd8	7689
cparata	4:77faf76e3cd8	7690	return ret;
cparata	0:6d69e896ce38	7691	}
cparata	0:6d69e896ce38	7692
cparata	0:6d69e896ce38	7693	/**
cparata	0:6d69e896ce38	7694	* @brief FSM number of programs register.[get]
cparata	0:6d69e896ce38	7695	*
cparata	0:6d69e896ce38	7696	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	7697	* @param val buffer that stores data read.
cparata	2:4d14e9edf37e	7698	*
cparata	2:4d14e9edf37e	7699	*/
cparata	2:4d14e9edf37e	7700	int32_t lsm6dso_fsm_number_of_programs_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	2:4d14e9edf37e	7701	{
cparata	4:77faf76e3cd8	7702	int32_t ret;
cparata	4:77faf76e3cd8	7703
cparata	4:77faf76e3cd8	7704	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_PROGRAMS, val);
cparata	4:77faf76e3cd8	7705
cparata	4:77faf76e3cd8	7706	return ret;
cparata	0:6d69e896ce38	7707	}
cparata	0:6d69e896ce38	7708
cparata	0:6d69e896ce38	7709	/**
cparata	0:6d69e896ce38	7710	* @brief FSM start address register (r/w).
cparata	0:6d69e896ce38	7711	* First available address is 0x033C.[set]
cparata	0:6d69e896ce38	7712	*
cparata	0:6d69e896ce38	7713	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	7714	* @param val the value of start address
cparata	2:4d14e9edf37e	7715	*
cparata	2:4d14e9edf37e	7716	*/
cparata	2:4d14e9edf37e	7717	int32_t lsm6dso_fsm_start_address_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	2:4d14e9edf37e	7718	{
cparata	4:77faf76e3cd8	7719	int32_t ret;
cparata	4:77faf76e3cd8	7720	uint8_t add_l;
cparata	4:77faf76e3cd8	7721	uint8_t add_h;
cparata	4:77faf76e3cd8	7722
cparata	4:77faf76e3cd8	7723	add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
cparata	4:77faf76e3cd8	7724	add_l = (uint8_t)( val & 0x00FFU );
cparata	4:77faf76e3cd8	7725
cparata	4:77faf76e3cd8	7726	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l);
cparata	4:77faf76e3cd8	7727	if (ret == 0) {
cparata	4:77faf76e3cd8	7728	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h);
cparata	4:77faf76e3cd8	7729	}
cparata	4:77faf76e3cd8	7730	return ret;
cparata	0:6d69e896ce38	7731	}
cparata	0:6d69e896ce38	7732
cparata	0:6d69e896ce38	7733	/**
cparata	0:6d69e896ce38	7734	* @brief FSM start address register (r/w).
cparata	0:6d69e896ce38	7735	* First available address is 0x033C.[get]
cparata	0:6d69e896ce38	7736	*
cparata	0:6d69e896ce38	7737	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	7738	* @param val buffer the value of start address.
cparata	2:4d14e9edf37e	7739	*
cparata	2:4d14e9edf37e	7740	*/
cparata	2:4d14e9edf37e	7741	int32_t lsm6dso_fsm_start_address_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	2:4d14e9edf37e	7742	{
cparata	4:77faf76e3cd8	7743	int32_t ret;
cparata	4:77faf76e3cd8	7744	uint8_t add_l;
cparata	4:77faf76e3cd8	7745	uint8_t add_h;
cparata	4:77faf76e3cd8	7746
cparata	4:77faf76e3cd8	7747	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l);
cparata	4:77faf76e3cd8	7748	if (ret == 0) {
cparata	4:77faf76e3cd8	7749	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h);
cparata	4:77faf76e3cd8	7750	*val = add_h;
cparata	4:77faf76e3cd8	7751	val = val << 8;
cparata	4:77faf76e3cd8	7752	*val += add_l;
cparata	4:77faf76e3cd8	7753	}
cparata	4:77faf76e3cd8	7754	return ret;
cparata	0:6d69e896ce38	7755	}
cparata	0:6d69e896ce38	7756
cparata	0:6d69e896ce38	7757	/**
cparata	0:6d69e896ce38	7758	* @}
cparata	0:6d69e896ce38	7759	*
cparata	0:6d69e896ce38	7760	*/
cparata	0:6d69e896ce38	7761
cparata	0:6d69e896ce38	7762	/**
cparata	0:6d69e896ce38	7763	* @defgroup LSM6DSO_Sensor_hub
cparata	0:6d69e896ce38	7764	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	7765	* sensor hub.
cparata	0:6d69e896ce38	7766	* @{
cparata	0:6d69e896ce38	7767	*
cparata	0:6d69e896ce38	7768	*/
cparata	0:6d69e896ce38	7769
cparata	0:6d69e896ce38	7770	/**
cparata	2:4d14e9edf37e	7771	* @brief Sensor hub output registers.[get]
cparata	2:4d14e9edf37e	7772	*
cparata	2:4d14e9edf37e	7773	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	7774	* @param val values read from registers SENSOR_HUB_1 to SENSOR_HUB_18
cparata	2:4d14e9edf37e	7775	* @param len number of consecutive register to read (max 18)
cparata	2:4d14e9edf37e	7776	*
cparata	2:4d14e9edf37e	7777	*/
cparata	2:4d14e9edf37e	7778	int32_t lsm6dso_sh_read_data_raw_get(lsm6dso_ctx_t ctx, uint8_t val,
cparata	2:4d14e9edf37e	7779	uint8_t len)
cparata	0:6d69e896ce38	7780	{
cparata	4:77faf76e3cd8	7781	int32_t ret;
cparata	4:77faf76e3cd8	7782
cparata	4:77faf76e3cd8	7783	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	7784	if (ret == 0) {
cparata	4:77faf76e3cd8	7785	ret = lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t*) val, len);
cparata	4:77faf76e3cd8	7786	}
cparata	4:77faf76e3cd8	7787	if (ret == 0) {
cparata	4:77faf76e3cd8	7788	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7789	}
cparata	4:77faf76e3cd8	7790
cparata	4:77faf76e3cd8	7791	return ret;
cparata	0:6d69e896ce38	7792	}
cparata	0:6d69e896ce38	7793
cparata	0:6d69e896ce38	7794	/**
cparata	0:6d69e896ce38	7795	* @brief Number of external sensors to be read by the sensor hub.[set]
cparata	0:6d69e896ce38	7796	*
cparata	0:6d69e896ce38	7797	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7798	* @param val change the values of aux_sens_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	7799	*
cparata	0:6d69e896ce38	7800	*/
cparata	0:6d69e896ce38	7801	int32_t lsm6dso_sh_slave_connected_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7802	lsm6dso_aux_sens_on_t val)
cparata	0:6d69e896ce38	7803	{
cparata	4:77faf76e3cd8	7804	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	7805	int32_t ret;
cparata	4:77faf76e3cd8	7806
cparata	4:77faf76e3cd8	7807	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	7808	if (ret == 0) {
cparata	4:77faf76e3cd8	7809	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7810	}
cparata	4:77faf76e3cd8	7811	if (ret == 0) {
cparata	4:77faf76e3cd8	7812	reg.aux_sens_on = (uint8_t)val;
cparata	4:77faf76e3cd8	7813	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7814	}
cparata	4:77faf76e3cd8	7815	if (ret == 0) {
cparata	4:77faf76e3cd8	7816	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7817	}
cparata	4:77faf76e3cd8	7818	return ret;
cparata	0:6d69e896ce38	7819	}
cparata	0:6d69e896ce38	7820
cparata	0:6d69e896ce38	7821	/**
cparata	0:6d69e896ce38	7822	* @brief Number of external sensors to be read by the sensor hub.[get]
cparata	0:6d69e896ce38	7823	*
cparata	0:6d69e896ce38	7824	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7825	* @param val Get the values of aux_sens_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	7826	*
cparata	0:6d69e896ce38	7827	*/
cparata	0:6d69e896ce38	7828	int32_t lsm6dso_sh_slave_connected_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7829	lsm6dso_aux_sens_on_t *val)
cparata	0:6d69e896ce38	7830	{
cparata	4:77faf76e3cd8	7831	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	7832	int32_t ret;
cparata	4:77faf76e3cd8	7833
cparata	4:77faf76e3cd8	7834	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	7835	if (ret == 0) {
cparata	4:77faf76e3cd8	7836	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7837	}
cparata	4:77faf76e3cd8	7838	if (ret == 0) {
cparata	4:77faf76e3cd8	7839	switch (reg.aux_sens_on) {
cparata	4:77faf76e3cd8	7840	case LSM6DSO_SLV_0:
cparata	4:77faf76e3cd8	7841	*val = LSM6DSO_SLV_0;
cparata	4:77faf76e3cd8	7842	break;
cparata	4:77faf76e3cd8	7843	case LSM6DSO_SLV_0_1:
cparata	4:77faf76e3cd8	7844	*val = LSM6DSO_SLV_0_1;
cparata	4:77faf76e3cd8	7845	break;
cparata	4:77faf76e3cd8	7846	case LSM6DSO_SLV_0_1_2:
cparata	4:77faf76e3cd8	7847	*val = LSM6DSO_SLV_0_1_2;
cparata	4:77faf76e3cd8	7848	break;
cparata	4:77faf76e3cd8	7849	case LSM6DSO_SLV_0_1_2_3:
cparata	4:77faf76e3cd8	7850	*val = LSM6DSO_SLV_0_1_2_3;
cparata	4:77faf76e3cd8	7851	break;
cparata	4:77faf76e3cd8	7852	default:
cparata	4:77faf76e3cd8	7853	*val = LSM6DSO_SLV_0;
cparata	4:77faf76e3cd8	7854	break;
cparata	3:4274d9103f1d	7855	}
cparata	4:77faf76e3cd8	7856	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7857	}
cparata	4:77faf76e3cd8	7858
cparata	4:77faf76e3cd8	7859	return ret;
cparata	0:6d69e896ce38	7860	}
cparata	0:6d69e896ce38	7861
cparata	0:6d69e896ce38	7862	/**
cparata	0:6d69e896ce38	7863	* @brief Sensor hub I2C master enable.[set]
cparata	0:6d69e896ce38	7864	*
cparata	0:6d69e896ce38	7865	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7866	* @param val change the values of master_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	7867	*
cparata	0:6d69e896ce38	7868	*/
cparata	0:6d69e896ce38	7869	int32_t lsm6dso_sh_master_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	7870	{
cparata	4:77faf76e3cd8	7871	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	7872	int32_t ret;
cparata	4:77faf76e3cd8	7873
cparata	4:77faf76e3cd8	7874	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	7875	if (ret == 0) {
cparata	4:77faf76e3cd8	7876	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7877	}
cparata	4:77faf76e3cd8	7878	if (ret == 0) {
cparata	4:77faf76e3cd8	7879	reg.master_on = val;
cparata	4:77faf76e3cd8	7880	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7881	}
cparata	4:77faf76e3cd8	7882	if (ret == 0) {
cparata	4:77faf76e3cd8	7883	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7884	}
cparata	4:77faf76e3cd8	7885	return ret;
cparata	0:6d69e896ce38	7886	}
cparata	0:6d69e896ce38	7887
cparata	0:6d69e896ce38	7888	/**
cparata	0:6d69e896ce38	7889	* @brief Sensor hub I2C master enable.[get]
cparata	0:6d69e896ce38	7890	*
cparata	0:6d69e896ce38	7891	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7892	* @param val change the values of master_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	7893	*
cparata	0:6d69e896ce38	7894	*/
cparata	0:6d69e896ce38	7895	int32_t lsm6dso_sh_master_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7896	{
cparata	4:77faf76e3cd8	7897	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	7898	int32_t ret;
cparata	4:77faf76e3cd8	7899
cparata	4:77faf76e3cd8	7900	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	7901	if (ret == 0) {
cparata	4:77faf76e3cd8	7902	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7903	}
cparata	4:77faf76e3cd8	7904	if (ret == 0) {
cparata	4:77faf76e3cd8	7905	*val = reg.master_on;
cparata	4:77faf76e3cd8	7906	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7907	}
cparata	4:77faf76e3cd8	7908
cparata	4:77faf76e3cd8	7909	return ret;
cparata	0:6d69e896ce38	7910	}
cparata	0:6d69e896ce38	7911
cparata	0:6d69e896ce38	7912	/**
cparata	0:6d69e896ce38	7913	* @brief Master I2C pull-up enable.[set]
cparata	0:6d69e896ce38	7914	*
cparata	0:6d69e896ce38	7915	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7916	* @param val change the values of shub_pu_en in reg MASTER_CONFIG
cparata	0:6d69e896ce38	7917	*
cparata	0:6d69e896ce38	7918	*/
cparata	0:6d69e896ce38	7919	int32_t lsm6dso_sh_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_pu_en_t val)
cparata	0:6d69e896ce38	7920	{
cparata	4:77faf76e3cd8	7921	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	7922	int32_t ret;
cparata	4:77faf76e3cd8	7923
cparata	4:77faf76e3cd8	7924	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	7925	if (ret == 0) {
cparata	4:77faf76e3cd8	7926	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7927	}
cparata	4:77faf76e3cd8	7928	if (ret == 0) {
cparata	4:77faf76e3cd8	7929	reg.shub_pu_en = (uint8_t)val;
cparata	4:77faf76e3cd8	7930	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7931	}
cparata	4:77faf76e3cd8	7932	if (ret == 0) {
cparata	4:77faf76e3cd8	7933	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7934	}
cparata	4:77faf76e3cd8	7935
cparata	4:77faf76e3cd8	7936	return ret;
cparata	0:6d69e896ce38	7937	}
cparata	0:6d69e896ce38	7938
cparata	0:6d69e896ce38	7939	/**
cparata	0:6d69e896ce38	7940	* @brief Master I2C pull-up enable.[get]
cparata	0:6d69e896ce38	7941	*
cparata	0:6d69e896ce38	7942	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7943	* @param val Get the values of shub_pu_en in reg MASTER_CONFIG
cparata	0:6d69e896ce38	7944	*
cparata	0:6d69e896ce38	7945	*/
cparata	0:6d69e896ce38	7946	int32_t lsm6dso_sh_pin_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7947	lsm6dso_shub_pu_en_t *val)
cparata	0:6d69e896ce38	7948	{
cparata	4:77faf76e3cd8	7949	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	7950	int32_t ret;
cparata	4:77faf76e3cd8	7951
cparata	4:77faf76e3cd8	7952	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	7953	if (ret == 0) {
cparata	4:77faf76e3cd8	7954	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7955	}
cparata	4:77faf76e3cd8	7956	if (ret == 0) {
cparata	4:77faf76e3cd8	7957	switch (reg.shub_pu_en) {
cparata	4:77faf76e3cd8	7958	case LSM6DSO_EXT_PULL_UP:
cparata	4:77faf76e3cd8	7959	*val = LSM6DSO_EXT_PULL_UP;
cparata	4:77faf76e3cd8	7960	break;
cparata	4:77faf76e3cd8	7961	case LSM6DSO_INTERNAL_PULL_UP:
cparata	4:77faf76e3cd8	7962	*val = LSM6DSO_INTERNAL_PULL_UP;
cparata	4:77faf76e3cd8	7963	break;
cparata	4:77faf76e3cd8	7964	default:
cparata	4:77faf76e3cd8	7965	*val = LSM6DSO_EXT_PULL_UP;
cparata	4:77faf76e3cd8	7966	break;
cparata	3:4274d9103f1d	7967	}
cparata	4:77faf76e3cd8	7968	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7969	}
cparata	4:77faf76e3cd8	7970
cparata	4:77faf76e3cd8	7971	return ret;
cparata	0:6d69e896ce38	7972	}
cparata	0:6d69e896ce38	7973
cparata	0:6d69e896ce38	7974	/**
cparata	0:6d69e896ce38	7975	* @brief I2C interface pass-through.[set]
cparata	0:6d69e896ce38	7976	*
cparata	0:6d69e896ce38	7977	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7978	* @param val change the values of pass_through_mode in
cparata	0:6d69e896ce38	7979	* reg MASTER_CONFIG
cparata	0:6d69e896ce38	7980	*
cparata	0:6d69e896ce38	7981	*/
cparata	0:6d69e896ce38	7982	int32_t lsm6dso_sh_pass_through_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	7983	{
cparata	4:77faf76e3cd8	7984	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	7985	int32_t ret;
cparata	4:77faf76e3cd8	7986
cparata	4:77faf76e3cd8	7987	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	7988	if (ret == 0) {
cparata	4:77faf76e3cd8	7989	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7990	}
cparata	4:77faf76e3cd8	7991	if (ret == 0) {
cparata	4:77faf76e3cd8	7992	reg.pass_through_mode = val;
cparata	4:77faf76e3cd8	7993	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	7994	}
cparata	4:77faf76e3cd8	7995	if (ret == 0) {
cparata	4:77faf76e3cd8	7996	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	7997	}
cparata	4:77faf76e3cd8	7998
cparata	4:77faf76e3cd8	7999	return ret;
cparata	0:6d69e896ce38	8000	}
cparata	0:6d69e896ce38	8001
cparata	0:6d69e896ce38	8002	/**
cparata	0:6d69e896ce38	8003	* @brief I2C interface pass-through.[get]
cparata	0:6d69e896ce38	8004	*
cparata	0:6d69e896ce38	8005	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8006	* @param val change the values of pass_through_mode in
cparata	0:6d69e896ce38	8007	* reg MASTER_CONFIG
cparata	0:6d69e896ce38	8008	*
cparata	0:6d69e896ce38	8009	*/
cparata	0:6d69e896ce38	8010	int32_t lsm6dso_sh_pass_through_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8011	{
cparata	4:77faf76e3cd8	8012	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	8013	int32_t ret;
cparata	4:77faf76e3cd8	8014
cparata	4:77faf76e3cd8	8015	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8016	if (ret == 0) {
cparata	4:77faf76e3cd8	8017	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8018	}
cparata	4:77faf76e3cd8	8019	if (ret == 0) {
cparata	4:77faf76e3cd8	8020	*val = reg.pass_through_mode;
cparata	4:77faf76e3cd8	8021	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8022	}
cparata	4:77faf76e3cd8	8023
cparata	4:77faf76e3cd8	8024	return ret;
cparata	0:6d69e896ce38	8025	}
cparata	0:6d69e896ce38	8026
cparata	0:6d69e896ce38	8027	/**
cparata	0:6d69e896ce38	8028	* @brief Sensor hub trigger signal selection.[set]
cparata	0:6d69e896ce38	8029	*
cparata	0:6d69e896ce38	8030	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8031	* @param val change the values of start_config in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8032	*
cparata	0:6d69e896ce38	8033	*/
cparata	0:6d69e896ce38	8034	int32_t lsm6dso_sh_syncro_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8035	lsm6dso_start_config_t val)
cparata	0:6d69e896ce38	8036	{
cparata	4:77faf76e3cd8	8037	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	8038	int32_t ret;
cparata	4:77faf76e3cd8	8039
cparata	4:77faf76e3cd8	8040	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8041	if (ret == 0) {
cparata	4:77faf76e3cd8	8042	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8043	}
cparata	4:77faf76e3cd8	8044	if (ret == 0) {
cparata	4:77faf76e3cd8	8045	reg.start_config = (uint8_t)val;
cparata	4:77faf76e3cd8	8046	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8047	}
cparata	4:77faf76e3cd8	8048	if (ret == 0) {
cparata	4:77faf76e3cd8	8049	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8050	}
cparata	4:77faf76e3cd8	8051
cparata	4:77faf76e3cd8	8052	return ret;
cparata	0:6d69e896ce38	8053	}
cparata	0:6d69e896ce38	8054
cparata	0:6d69e896ce38	8055	/**
cparata	0:6d69e896ce38	8056	* @brief Sensor hub trigger signal selection.[get]
cparata	0:6d69e896ce38	8057	*
cparata	0:6d69e896ce38	8058	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8059	* @param val Get the values of start_config in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8060	*
cparata	0:6d69e896ce38	8061	*/
cparata	0:6d69e896ce38	8062	int32_t lsm6dso_sh_syncro_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8063	lsm6dso_start_config_t *val)
cparata	0:6d69e896ce38	8064	{
cparata	4:77faf76e3cd8	8065	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	8066	int32_t ret;
cparata	4:77faf76e3cd8	8067
cparata	4:77faf76e3cd8	8068	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8069	if (ret == 0) {
cparata	4:77faf76e3cd8	8070	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8071	}
cparata	4:77faf76e3cd8	8072	if (ret == 0) {
cparata	4:77faf76e3cd8	8073	switch (reg.start_config) {
cparata	4:77faf76e3cd8	8074	case LSM6DSO_EXT_ON_INT2_PIN:
cparata	4:77faf76e3cd8	8075	*val = LSM6DSO_EXT_ON_INT2_PIN;
cparata	4:77faf76e3cd8	8076	break;
cparata	4:77faf76e3cd8	8077	case LSM6DSO_XL_GY_DRDY:
cparata	4:77faf76e3cd8	8078	*val = LSM6DSO_XL_GY_DRDY;
cparata	4:77faf76e3cd8	8079	break;
cparata	4:77faf76e3cd8	8080	default:
cparata	4:77faf76e3cd8	8081	*val = LSM6DSO_EXT_ON_INT2_PIN;
cparata	4:77faf76e3cd8	8082	break;
cparata	3:4274d9103f1d	8083	}
cparata	4:77faf76e3cd8	8084	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8085	}
cparata	4:77faf76e3cd8	8086	return ret;
cparata	0:6d69e896ce38	8087	}
cparata	0:6d69e896ce38	8088
cparata	0:6d69e896ce38	8089	/**
cparata	0:6d69e896ce38	8090	* @brief Slave 0 write operation is performed only at the first
cparata	0:6d69e896ce38	8091	* sensor hub cycle.[set]
cparata	0:6d69e896ce38	8092	*
cparata	0:6d69e896ce38	8093	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8094	* @param val change the values of write_once in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8095	*
cparata	0:6d69e896ce38	8096	*/
cparata	0:6d69e896ce38	8097	int32_t lsm6dso_sh_write_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8098	lsm6dso_write_once_t val)
cparata	0:6d69e896ce38	8099	{
cparata	4:77faf76e3cd8	8100	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	8101	int32_t ret;
cparata	4:77faf76e3cd8	8102
cparata	4:77faf76e3cd8	8103	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8104	if (ret == 0) {
cparata	4:77faf76e3cd8	8105	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8106	}
cparata	4:77faf76e3cd8	8107	if (ret == 0) {
cparata	4:77faf76e3cd8	8108	reg.write_once = (uint8_t)val;
cparata	4:77faf76e3cd8	8109	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8110	}
cparata	4:77faf76e3cd8	8111	if (ret == 0) {
cparata	4:77faf76e3cd8	8112	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8113	}
cparata	4:77faf76e3cd8	8114
cparata	4:77faf76e3cd8	8115	return ret;
cparata	0:6d69e896ce38	8116	}
cparata	0:6d69e896ce38	8117
cparata	0:6d69e896ce38	8118	/**
cparata	0:6d69e896ce38	8119	* @brief Slave 0 write operation is performed only at the first sensor
cparata	0:6d69e896ce38	8120	* hub cycle.[get]
cparata	0:6d69e896ce38	8121	*
cparata	0:6d69e896ce38	8122	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8123	* @param val Get the values of write_once in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8124	*
cparata	0:6d69e896ce38	8125	*/
cparata	0:6d69e896ce38	8126	int32_t lsm6dso_sh_write_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8127	lsm6dso_write_once_t *val)
cparata	0:6d69e896ce38	8128	{
cparata	4:77faf76e3cd8	8129	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	8130	int32_t ret;
cparata	4:77faf76e3cd8	8131
cparata	4:77faf76e3cd8	8132	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8133	if (ret == 0) {
cparata	4:77faf76e3cd8	8134	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8135	}
cparata	4:77faf76e3cd8	8136	if (ret == 0) {
cparata	4:77faf76e3cd8	8137	switch (reg.write_once) {
cparata	4:77faf76e3cd8	8138	case LSM6DSO_EACH_SH_CYCLE:
cparata	4:77faf76e3cd8	8139	*val = LSM6DSO_EACH_SH_CYCLE;
cparata	4:77faf76e3cd8	8140	break;
cparata	4:77faf76e3cd8	8141	case LSM6DSO_ONLY_FIRST_CYCLE:
cparata	4:77faf76e3cd8	8142	*val = LSM6DSO_ONLY_FIRST_CYCLE;
cparata	4:77faf76e3cd8	8143	break;
cparata	4:77faf76e3cd8	8144	default:
cparata	4:77faf76e3cd8	8145	*val = LSM6DSO_EACH_SH_CYCLE;
cparata	4:77faf76e3cd8	8146	break;
cparata	3:4274d9103f1d	8147	}
cparata	4:77faf76e3cd8	8148	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8149	}
cparata	4:77faf76e3cd8	8150
cparata	4:77faf76e3cd8	8151	return ret;
cparata	0:6d69e896ce38	8152	}
cparata	0:6d69e896ce38	8153
cparata	0:6d69e896ce38	8154	/**
cparata	0:6d69e896ce38	8155	* @brief Reset Master logic and output registers.[set]
cparata	0:6d69e896ce38	8156	*
cparata	0:6d69e896ce38	8157	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8158	*
cparata	0:6d69e896ce38	8159	*/
cparata	0:6d69e896ce38	8160	int32_t lsm6dso_sh_reset_set(lsm6dso_ctx_t *ctx)
cparata	0:6d69e896ce38	8161	{
cparata	4:77faf76e3cd8	8162	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	8163	int32_t ret;
cparata	4:77faf76e3cd8	8164
cparata	4:77faf76e3cd8	8165	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8166	if (ret == 0) {
cparata	4:77faf76e3cd8	8167	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8168	}
cparata	4:77faf76e3cd8	8169	if (ret == 0) {
cparata	4:77faf76e3cd8	8170	reg.rst_master_regs = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	8171	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8172	}
cparata	4:77faf76e3cd8	8173	if (ret == 0) {
cparata	4:77faf76e3cd8	8174	reg.rst_master_regs = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	8175	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8176	}
cparata	4:77faf76e3cd8	8177	if (ret == 0) {
cparata	4:77faf76e3cd8	8178	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8179	}
cparata	4:77faf76e3cd8	8180
cparata	4:77faf76e3cd8	8181	return ret;
cparata	0:6d69e896ce38	8182	}
cparata	0:6d69e896ce38	8183
cparata	0:6d69e896ce38	8184	/**
cparata	0:6d69e896ce38	8185	* @brief Reset Master logic and output registers.[get]
cparata	0:6d69e896ce38	8186	*
cparata	0:6d69e896ce38	8187	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8188	* @param val change the values of rst_master_regs in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8189	*
cparata	0:6d69e896ce38	8190	*/
cparata	0:6d69e896ce38	8191	int32_t lsm6dso_sh_reset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8192	{
cparata	4:77faf76e3cd8	8193	lsm6dso_master_config_t reg;
cparata	4:77faf76e3cd8	8194	int32_t ret;
cparata	4:77faf76e3cd8	8195
cparata	4:77faf76e3cd8	8196	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8197	if (ret == 0) {
cparata	4:77faf76e3cd8	8198	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8199	}
cparata	4:77faf76e3cd8	8200	if (ret == 0) {
cparata	4:77faf76e3cd8	8201	*val = reg.rst_master_regs;
cparata	4:77faf76e3cd8	8202	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8203	}
cparata	4:77faf76e3cd8	8204	return ret;
cparata	0:6d69e896ce38	8205	}
cparata	0:6d69e896ce38	8206
cparata	0:6d69e896ce38	8207	/**
cparata	0:6d69e896ce38	8208	* @brief Rate at which the master communicates.[set]
cparata	0:6d69e896ce38	8209	*
cparata	0:6d69e896ce38	8210	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8211	* @param val change the values of shub_odr in reg slv1_CONFIG
cparata	0:6d69e896ce38	8212	*
cparata	0:6d69e896ce38	8213	*/
cparata	0:6d69e896ce38	8214	int32_t lsm6dso_sh_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_odr_t val)
cparata	0:6d69e896ce38	8215	{
cparata	4:77faf76e3cd8	8216	lsm6dso_slv0_config_t reg;
cparata	4:77faf76e3cd8	8217	int32_t ret;
cparata	4:77faf76e3cd8	8218
cparata	4:77faf76e3cd8	8219	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8220	if (ret == 0) {
cparata	4:77faf76e3cd8	8221	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8222	}
cparata	4:77faf76e3cd8	8223	if (ret == 0) {
cparata	4:77faf76e3cd8	8224	reg.shub_odr = (uint8_t)val;
cparata	4:77faf76e3cd8	8225	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8226	}
cparata	4:77faf76e3cd8	8227	if (ret == 0) {
cparata	4:77faf76e3cd8	8228	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8229	}
cparata	4:77faf76e3cd8	8230
cparata	4:77faf76e3cd8	8231	return ret;
cparata	0:6d69e896ce38	8232	}
cparata	0:6d69e896ce38	8233
cparata	0:6d69e896ce38	8234	/**
cparata	0:6d69e896ce38	8235	* @brief Rate at which the master communicates.[get]
cparata	0:6d69e896ce38	8236	*
cparata	0:6d69e896ce38	8237	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8238	* @param val Get the values of shub_odr in reg slv1_CONFIG
cparata	0:6d69e896ce38	8239	*
cparata	0:6d69e896ce38	8240	*/
cparata	0:6d69e896ce38	8241	int32_t lsm6dso_sh_data_rate_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8242	lsm6dso_shub_odr_t *val)
cparata	0:6d69e896ce38	8243	{
cparata	4:77faf76e3cd8	8244	lsm6dso_slv0_config_t reg;
cparata	4:77faf76e3cd8	8245	int32_t ret;
cparata	4:77faf76e3cd8	8246
cparata	4:77faf76e3cd8	8247	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8248	if (ret == 0) {
cparata	4:77faf76e3cd8	8249	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8250	}
cparata	4:77faf76e3cd8	8251	if (ret == 0) {
cparata	4:77faf76e3cd8	8252	switch (reg.shub_odr) {
cparata	4:77faf76e3cd8	8253	case LSM6DSO_SH_ODR_104Hz:
cparata	4:77faf76e3cd8	8254	*val = LSM6DSO_SH_ODR_104Hz;
cparata	4:77faf76e3cd8	8255	break;
cparata	4:77faf76e3cd8	8256	case LSM6DSO_SH_ODR_52Hz:
cparata	4:77faf76e3cd8	8257	*val = LSM6DSO_SH_ODR_52Hz;
cparata	4:77faf76e3cd8	8258	break;
cparata	4:77faf76e3cd8	8259	case LSM6DSO_SH_ODR_26Hz:
cparata	4:77faf76e3cd8	8260	*val = LSM6DSO_SH_ODR_26Hz;
cparata	4:77faf76e3cd8	8261	break;
cparata	4:77faf76e3cd8	8262	case LSM6DSO_SH_ODR_13Hz:
cparata	4:77faf76e3cd8	8263	*val = LSM6DSO_SH_ODR_13Hz;
cparata	4:77faf76e3cd8	8264	break;
cparata	4:77faf76e3cd8	8265	default:
cparata	4:77faf76e3cd8	8266	*val = LSM6DSO_SH_ODR_104Hz;
cparata	4:77faf76e3cd8	8267	break;
cparata	3:4274d9103f1d	8268	}
cparata	4:77faf76e3cd8	8269	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8270	}
cparata	4:77faf76e3cd8	8271
cparata	4:77faf76e3cd8	8272	return ret;
cparata	0:6d69e896ce38	8273	}
cparata	0:6d69e896ce38	8274
cparata	0:6d69e896ce38	8275	/**
cparata	0:6d69e896ce38	8276	* @brief Configure slave 0 for perform a write.[set]
cparata	0:6d69e896ce38	8277	*
cparata	0:6d69e896ce38	8278	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8279	* @param val a structure that contain
cparata	0:6d69e896ce38	8280	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8281	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8282	* - uint8_t slv1_data; 8 bit data to write
cparata	0:6d69e896ce38	8283	*
cparata	0:6d69e896ce38	8284	*/
cparata	0:6d69e896ce38	8285	int32_t lsm6dso_sh_cfg_write(lsm6dso_ctx_t ctx, lsm6dso_sh_cfg_write_t val)
cparata	0:6d69e896ce38	8286	{
cparata	4:77faf76e3cd8	8287	lsm6dso_slv0_add_t reg;
cparata	4:77faf76e3cd8	8288	int32_t ret;
cparata	4:77faf76e3cd8	8289
cparata	4:77faf76e3cd8	8290	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8291	if (ret == 0) {
cparata	4:77faf76e3cd8	8292	reg.slave0 = val->slv0_add;
cparata	4:77faf76e3cd8	8293	reg.rw_0 = 0;
cparata	4:77faf76e3cd8	8294	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t*)&reg, 1);
cparata	4:77faf76e3cd8	8295	}
cparata	4:77faf76e3cd8	8296	if (ret == 0) {
cparata	4:77faf76e3cd8	8297	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
cparata	4:77faf76e3cd8	8298	&(val->slv0_subadd), 1);
cparata	4:77faf76e3cd8	8299	}
cparata	4:77faf76e3cd8	8300	if (ret == 0) {
cparata	4:77faf76e3cd8	8301	ret = lsm6dso_write_reg(ctx, LSM6DSO_DATAWRITE_SLV0,
cparata	4:77faf76e3cd8	8302	&(val->slv0_data), 1);
cparata	4:77faf76e3cd8	8303	}
cparata	4:77faf76e3cd8	8304	if (ret == 0) {
cparata	4:77faf76e3cd8	8305	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8306	}
cparata	4:77faf76e3cd8	8307	return ret;
cparata	0:6d69e896ce38	8308	}
cparata	0:6d69e896ce38	8309
cparata	0:6d69e896ce38	8310	/**
cparata	0:6d69e896ce38	8311	* @brief Configure slave 0 for perform a read.[set]
cparata	0:6d69e896ce38	8312	*
cparata	0:6d69e896ce38	8313	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8314	* @param val Structure that contain
cparata	0:6d69e896ce38	8315	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8316	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8317	* - uint8_t slv1_len; num of bit to read
cparata	0:6d69e896ce38	8318	*
cparata	0:6d69e896ce38	8319	*/
cparata	0:6d69e896ce38	8320	int32_t lsm6dso_sh_slv0_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8321	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8322	{
cparata	4:77faf76e3cd8	8323	lsm6dso_slv0_add_t slv0_add;
cparata	4:77faf76e3cd8	8324	lsm6dso_slv0_config_t slv0_config;
cparata	4:77faf76e3cd8	8325	int32_t ret;
cparata	4:77faf76e3cd8	8326
cparata	4:77faf76e3cd8	8327	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8328	if (ret == 0) {
cparata	4:77faf76e3cd8	8329	slv0_add.slave0 = val->slv_add;
cparata	4:77faf76e3cd8	8330	slv0_add.rw_0 = 1;
cparata	4:77faf76e3cd8	8331	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t*)&slv0_add, 1);
cparata	4:77faf76e3cd8	8332	}
cparata	4:77faf76e3cd8	8333	if (ret == 0) {
cparata	4:77faf76e3cd8	8334	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
cparata	4:77faf76e3cd8	8335	&(val->slv_subadd), 1);
cparata	4:77faf76e3cd8	8336	}
cparata	4:77faf76e3cd8	8337	if (ret == 0) {
cparata	4:77faf76e3cd8	8338	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG,
cparata	4:77faf76e3cd8	8339	(uint8_t*)&slv0_config, 1);
cparata	4:77faf76e3cd8	8340	}
cparata	4:77faf76e3cd8	8341	if (ret == 0) {
cparata	4:77faf76e3cd8	8342	slv0_config.slave0_numop = val->slv_len;
cparata	4:77faf76e3cd8	8343	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG,
cparata	4:77faf76e3cd8	8344	(uint8_t*)&slv0_config, 1);
cparata	4:77faf76e3cd8	8345	}
cparata	4:77faf76e3cd8	8346	if (ret == 0) {
cparata	4:77faf76e3cd8	8347	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8348	}
cparata	4:77faf76e3cd8	8349
cparata	4:77faf76e3cd8	8350	return ret;
cparata	0:6d69e896ce38	8351	}
cparata	0:6d69e896ce38	8352
cparata	0:6d69e896ce38	8353	/**
cparata	0:6d69e896ce38	8354	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:6d69e896ce38	8355	*
cparata	0:6d69e896ce38	8356	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8357	* @param val Structure that contain
cparata	0:6d69e896ce38	8358	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8359	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8360	* - uint8_t slv1_len; num of bit to read
cparata	0:6d69e896ce38	8361	*
cparata	0:6d69e896ce38	8362	*/
cparata	0:6d69e896ce38	8363	int32_t lsm6dso_sh_slv1_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8364	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8365	{
cparata	4:77faf76e3cd8	8366	lsm6dso_slv1_add_t slv1_add;
cparata	4:77faf76e3cd8	8367	lsm6dso_slv1_config_t slv1_config;
cparata	4:77faf76e3cd8	8368	int32_t ret;
cparata	4:77faf76e3cd8	8369
cparata	4:77faf76e3cd8	8370	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8371	if (ret == 0) {
cparata	4:77faf76e3cd8	8372	slv1_add.slave1_add = val->slv_add;
cparata	4:77faf76e3cd8	8373	slv1_add.r_1 = 1;
cparata	4:77faf76e3cd8	8374	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_ADD, (uint8_t*)&slv1_add, 1);
cparata	4:77faf76e3cd8	8375	}
cparata	4:77faf76e3cd8	8376	if (ret == 0) {
cparata	4:77faf76e3cd8	8377	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_SUBADD,
cparata	4:77faf76e3cd8	8378	&(val->slv_subadd), 1);
cparata	4:77faf76e3cd8	8379	}
cparata	4:77faf76e3cd8	8380	if (ret == 0) {
cparata	4:77faf76e3cd8	8381	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG,
cparata	4:77faf76e3cd8	8382	(uint8_t*)&slv1_config, 1);
cparata	4:77faf76e3cd8	8383	}
cparata	4:77faf76e3cd8	8384	if (ret == 0) {
cparata	4:77faf76e3cd8	8385	slv1_config.slave1_numop = val->slv_len;
cparata	4:77faf76e3cd8	8386	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG,
cparata	4:77faf76e3cd8	8387	(uint8_t*)&slv1_config, 1);
cparata	4:77faf76e3cd8	8388	}
cparata	4:77faf76e3cd8	8389	if (ret == 0) {
cparata	4:77faf76e3cd8	8390	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8391	}
cparata	4:77faf76e3cd8	8392
cparata	4:77faf76e3cd8	8393	return ret;
cparata	0:6d69e896ce38	8394	}
cparata	0:6d69e896ce38	8395
cparata	0:6d69e896ce38	8396	/**
cparata	0:6d69e896ce38	8397	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:6d69e896ce38	8398	*
cparata	0:6d69e896ce38	8399	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8400	* @param val Structure that contain
cparata	0:6d69e896ce38	8401	* - uint8_t slv2_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8402	* - uint8_t slv2_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8403	* - uint8_t slv2_len; num of bit to read
cparata	0:6d69e896ce38	8404	*
cparata	0:6d69e896ce38	8405	*/
cparata	0:6d69e896ce38	8406	int32_t lsm6dso_sh_slv2_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8407	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8408	{
cparata	4:77faf76e3cd8	8409	lsm6dso_slv2_add_t slv2_add;
cparata	4:77faf76e3cd8	8410	lsm6dso_slv2_config_t slv2_config;
cparata	4:77faf76e3cd8	8411	int32_t ret;
cparata	4:77faf76e3cd8	8412
cparata	4:77faf76e3cd8	8413	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8414	if (ret == 0) {
cparata	4:77faf76e3cd8	8415	slv2_add.slave2_add = val->slv_add;
cparata	4:77faf76e3cd8	8416	slv2_add.r_2 = 1;
cparata	4:77faf76e3cd8	8417	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_ADD, (uint8_t*)&slv2_add, 1);
cparata	4:77faf76e3cd8	8418	}
cparata	4:77faf76e3cd8	8419	if (ret == 0) {
cparata	4:77faf76e3cd8	8420	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_SUBADD,
cparata	4:77faf76e3cd8	8421	&(val->slv_subadd), 1);
cparata	4:77faf76e3cd8	8422	}
cparata	4:77faf76e3cd8	8423	if (ret == 0) {
cparata	4:77faf76e3cd8	8424	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG,
cparata	4:77faf76e3cd8	8425	(uint8_t*)&slv2_config, 1);
cparata	4:77faf76e3cd8	8426	}
cparata	4:77faf76e3cd8	8427	if (ret == 0) {
cparata	4:77faf76e3cd8	8428	slv2_config.slave2_numop = val->slv_len;
cparata	4:77faf76e3cd8	8429	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG,
cparata	4:77faf76e3cd8	8430	(uint8_t*)&slv2_config, 1);
cparata	4:77faf76e3cd8	8431	}
cparata	4:77faf76e3cd8	8432	if (ret == 0) {
cparata	4:77faf76e3cd8	8433	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8434	}
cparata	4:77faf76e3cd8	8435	return ret;
cparata	0:6d69e896ce38	8436	}
cparata	0:6d69e896ce38	8437
cparata	0:6d69e896ce38	8438	/**
cparata	0:6d69e896ce38	8439	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:6d69e896ce38	8440	*
cparata	0:6d69e896ce38	8441	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8442	* @param val Structure that contain
cparata	0:6d69e896ce38	8443	* - uint8_t slv3_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8444	* - uint8_t slv3_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8445	* - uint8_t slv3_len; num of bit to read
cparata	0:6d69e896ce38	8446	*
cparata	0:6d69e896ce38	8447	*/
cparata	0:6d69e896ce38	8448	int32_t lsm6dso_sh_slv3_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8449	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8450	{
cparata	4:77faf76e3cd8	8451	lsm6dso_slv3_add_t slv3_add;
cparata	4:77faf76e3cd8	8452	lsm6dso_slv3_config_t slv3_config;
cparata	4:77faf76e3cd8	8453	int32_t ret;
cparata	4:77faf76e3cd8	8454
cparata	4:77faf76e3cd8	8455	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8456	if (ret == 0) {
cparata	4:77faf76e3cd8	8457	slv3_add.slave3_add = val->slv_add;
cparata	4:77faf76e3cd8	8458	slv3_add.r_3 = 1;
cparata	4:77faf76e3cd8	8459	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_ADD, (uint8_t*)&slv3_add, 1);
cparata	4:77faf76e3cd8	8460	}
cparata	4:77faf76e3cd8	8461	if (ret == 0) {
cparata	4:77faf76e3cd8	8462	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_SUBADD,
cparata	4:77faf76e3cd8	8463	&(val->slv_subadd), 1);
cparata	4:77faf76e3cd8	8464	}
cparata	4:77faf76e3cd8	8465	if (ret == 0) {
cparata	4:77faf76e3cd8	8466	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG,
cparata	4:77faf76e3cd8	8467	(uint8_t*)&slv3_config, 1);
cparata	4:77faf76e3cd8	8468	}
cparata	4:77faf76e3cd8	8469	if (ret == 0) {
cparata	4:77faf76e3cd8	8470	slv3_config.slave3_numop = val->slv_len;
cparata	4:77faf76e3cd8	8471	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG,
cparata	4:77faf76e3cd8	8472	(uint8_t*)&slv3_config, 1);
cparata	4:77faf76e3cd8	8473	}
cparata	4:77faf76e3cd8	8474	if (ret == 0) {
cparata	4:77faf76e3cd8	8475	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8476	}
cparata	4:77faf76e3cd8	8477	return ret;
cparata	0:6d69e896ce38	8478	}
cparata	0:6d69e896ce38	8479
cparata	0:6d69e896ce38	8480	/**
cparata	0:6d69e896ce38	8481	* @brief Sensor hub source register.[get]
cparata	0:6d69e896ce38	8482	*
cparata	0:6d69e896ce38	8483	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8484	* @param val union of registers from STATUS_MASTER to
cparata	0:6d69e896ce38	8485	*
cparata	0:6d69e896ce38	8486	*/
cparata	0:6d69e896ce38	8487	int32_t lsm6dso_sh_status_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8488	lsm6dso_status_master_t *val)
cparata	0:6d69e896ce38	8489	{
cparata	4:77faf76e3cd8	8490	int32_t ret;
cparata	4:77faf76e3cd8	8491
cparata	4:77faf76e3cd8	8492	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	4:77faf76e3cd8	8493	if (ret == 0) {
cparata	4:77faf76e3cd8	8494	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER, (uint8_t*) val, 1);
cparata	4:77faf76e3cd8	8495	}
cparata	4:77faf76e3cd8	8496	if (ret == 0) {
cparata	4:77faf76e3cd8	8497	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8498	}
cparata	4:77faf76e3cd8	8499
cparata	4:77faf76e3cd8	8500	return ret;
cparata	4:77faf76e3cd8	8501	}
cparata	4:77faf76e3cd8	8502
cparata	4:77faf76e3cd8	8503	/**
cparata	4:77faf76e3cd8	8504	* @}
cparata	4:77faf76e3cd8	8505	*
cparata	4:77faf76e3cd8	8506	*/
cparata	4:77faf76e3cd8	8507
cparata	4:77faf76e3cd8	8508	/**
cparata	4:77faf76e3cd8	8509	* @defgroup Basic configuration
cparata	4:77faf76e3cd8	8510	* @brief This section groups all the functions concerning
cparata	4:77faf76e3cd8	8511	* device basic configuration.
cparata	4:77faf76e3cd8	8512	* @{
cparata	4:77faf76e3cd8	8513	*
cparata	4:77faf76e3cd8	8514	*/
cparata	4:77faf76e3cd8	8515
cparata	4:77faf76e3cd8	8516	/**
cparata	4:77faf76e3cd8	8517	* @brief Device "Who am I".[get]
cparata	4:77faf76e3cd8	8518	*
cparata	4:77faf76e3cd8	8519	* @param ctx communication interface handler. Use NULL to ingnore
cparata	4:77faf76e3cd8	8520	* this interface.(ptr)
cparata	4:77faf76e3cd8	8521	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	4:77faf76e3cd8	8522	* to ingnore this interface.(ptr)
cparata	4:77faf76e3cd8	8523	* @param val ID values read from the two interfaces. ID values
cparata	4:77faf76e3cd8	8524	* will be the same.(ptr)
cparata	4:77faf76e3cd8	8525	*
cparata	4:77faf76e3cd8	8526	*/
cparata	4:77faf76e3cd8	8527	int32_t lsm6dso_id_get(lsm6dso_ctx_t ctx, lsm6dso_ctx_t aux_ctx,
cparata	4:77faf76e3cd8	8528	lsm6dso_id_t *val)
cparata	4:77faf76e3cd8	8529	{
cparata	4:77faf76e3cd8	8530	int32_t ret = 0;
cparata	4:77faf76e3cd8	8531
cparata	4:77faf76e3cd8	8532	if (ctx != NULL){
cparata	4:77faf76e3cd8	8533	ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I,
cparata	4:77faf76e3cd8	8534	(uint8_t*)&(val->ui), 1);
cparata	4:77faf76e3cd8	8535	}
cparata	4:77faf76e3cd8	8536	if (aux_ctx != NULL){
cparata	4:77faf76e3cd8	8537	if (ret == 0) {
cparata	4:77faf76e3cd8	8538	ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_WHO_AM_I,
cparata	4:77faf76e3cd8	8539	(uint8_t*)&(val->aux), 1);
cparata	4:77faf76e3cd8	8540	}
cparata	4:77faf76e3cd8	8541	}
cparata	4:77faf76e3cd8	8542	return ret;
cparata	4:77faf76e3cd8	8543	}
cparata	4:77faf76e3cd8	8544
cparata	4:77faf76e3cd8	8545	/**
cparata	4:77faf76e3cd8	8546	* @brief Re-initialize the device.[set]
cparata	4:77faf76e3cd8	8547	*
cparata	4:77faf76e3cd8	8548	* @param ctx communication interface handler.(ptr)
cparata	4:77faf76e3cd8	8549	* @param val re-initialization mode. Refer to datasheet
cparata	4:77faf76e3cd8	8550	* and application note for more information
cparata	4:77faf76e3cd8	8551	* about differencies beetween boot and sw_reset
cparata	4:77faf76e3cd8	8552	* procedure.
cparata	4:77faf76e3cd8	8553	*
cparata	4:77faf76e3cd8	8554	*/
cparata	4:77faf76e3cd8	8555	int32_t lsm6dso_init_set(lsm6dso_ctx_t *ctx, lsm6dso_init_t val)
cparata	4:77faf76e3cd8	8556	{
cparata	4:77faf76e3cd8	8557	lsm6dso_emb_func_init_a_t emb_func_init_a;
cparata	4:77faf76e3cd8	8558	lsm6dso_emb_func_init_b_t emb_func_init_b;
cparata	4:77faf76e3cd8	8559	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	8560	int32_t ret;
cparata	4:77faf76e3cd8	8561
cparata	4:77faf76e3cd8	8562	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	8563	if (ret == 0) {
cparata	4:77faf76e3cd8	8564	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B,
cparata	4:77faf76e3cd8	8565	(uint8_t*)&emb_func_init_b, 1);
cparata	4:77faf76e3cd8	8566	}
cparata	4:77faf76e3cd8	8567	if (ret == 0) {
cparata	4:77faf76e3cd8	8568	emb_func_init_b.fifo_compr_init = (uint8_t)val
cparata	4:77faf76e3cd8	8569	& ( (uint8_t)LSM6DSO_FIFO_COMP >> 2 );
cparata	4:77faf76e3cd8	8570	emb_func_init_b.fsm_init = (uint8_t)val
cparata	4:77faf76e3cd8	8571	& ( (uint8_t)LSM6DSO_FSM >> 3 );
cparata	4:77faf76e3cd8	8572	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B,
cparata	4:77faf76e3cd8	8573	(uint8_t*)&emb_func_init_b, 1);
cparata	4:77faf76e3cd8	8574	}
cparata	4:77faf76e3cd8	8575	if (ret == 0) {
cparata	4:77faf76e3cd8	8576	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A,
cparata	4:77faf76e3cd8	8577	(uint8_t*)&emb_func_init_a, 1);
cparata	4:77faf76e3cd8	8578	}
cparata	4:77faf76e3cd8	8579	if (ret == 0) {
cparata	4:77faf76e3cd8	8580	emb_func_init_a.step_det_init = ( (uint8_t)val
cparata	4:77faf76e3cd8	8581	& (uint8_t)LSM6DSO_PEDO ) >> 5;
cparata	4:77faf76e3cd8	8582	emb_func_init_a.tilt_init = ( (uint8_t)val
cparata	4:77faf76e3cd8	8583	& (uint8_t)LSM6DSO_TILT ) >> 6;
cparata	4:77faf76e3cd8	8584	emb_func_init_a.sig_mot_init = ( (uint8_t)val
cparata	4:77faf76e3cd8	8585	& (uint8_t)LSM6DSO_SMOTION ) >> 7;
cparata	4:77faf76e3cd8	8586	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A,
cparata	4:77faf76e3cd8	8587	(uint8_t*)&emb_func_init_a, 1);
cparata	4:77faf76e3cd8	8588	}
cparata	4:77faf76e3cd8	8589	if (ret == 0) {
cparata	4:77faf76e3cd8	8590	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8591	}
cparata	4:77faf76e3cd8	8592
cparata	4:77faf76e3cd8	8593	if (ret == 0) {
cparata	4:77faf76e3cd8	8594	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8595	}
cparata	4:77faf76e3cd8	8596	if ( ( (val == LSM6DSO_BOOT) \|\| (val == LSM6DSO_RESET) ) && (ret == 0) ) {
cparata	4:77faf76e3cd8	8597	ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSO_BOOT;
cparata	4:77faf76e3cd8	8598	ctrl3_c.sw_reset = ( (uint8_t)val & (uint8_t)LSM6DSO_RESET) >> 1;
cparata	4:77faf76e3cd8	8599	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8600	}
cparata	4:77faf76e3cd8	8601	if ( ( val == LSM6DSO_DRV_RDY )
cparata	4:77faf76e3cd8	8602	&& ( (ctrl3_c.bdu == PROPERTY_DISABLE)
cparata	4:77faf76e3cd8	8603	\|\| (ctrl3_c.if_inc == PROPERTY_DISABLE) ) && (ret == 0) ) {
cparata	4:77faf76e3cd8	8604	ctrl3_c.bdu = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	8605	ctrl3_c.if_inc = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	8606	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8607	}
cparata	4:77faf76e3cd8	8608
cparata	4:77faf76e3cd8	8609	return ret;
cparata	4:77faf76e3cd8	8610	}
cparata	4:77faf76e3cd8	8611
cparata	4:77faf76e3cd8	8612	/**
cparata	4:77faf76e3cd8	8613	* @brief Configures the bus operating mode.[set]
cparata	4:77faf76e3cd8	8614	*
cparata	4:77faf76e3cd8	8615	* @param ctx communication interface handler. Use NULL to ingnore
cparata	4:77faf76e3cd8	8616	* this interface.(ptr)
cparata	4:77faf76e3cd8	8617	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	4:77faf76e3cd8	8618	* to ingnore this interface.(ptr)
cparata	4:77faf76e3cd8	8619	* @param val configures the bus operating mode for both the
cparata	4:77faf76e3cd8	8620	* main and the auxiliary interface.
cparata	4:77faf76e3cd8	8621	*
cparata	4:77faf76e3cd8	8622	*/
cparata	4:77faf76e3cd8	8623	int32_t lsm6dso_bus_mode_set(lsm6dso_ctx_t ctx, lsm6dso_ctx_t aux_ctx,
cparata	4:77faf76e3cd8	8624	lsm6dso_bus_mode_t val)
cparata	4:77faf76e3cd8	8625	{
cparata	4:77faf76e3cd8	8626	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	4:77faf76e3cd8	8627	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	4:77faf76e3cd8	8628	lsm6dso_ctrl9_xl_t ctrl9_xl;
cparata	4:77faf76e3cd8	8629	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	8630	lsm6dso_ctrl4_c_t ctrl4_c;
cparata	4:77faf76e3cd8	8631	uint8_t bit_val;
cparata	4:77faf76e3cd8	8632	int32_t ret;
cparata	4:77faf76e3cd8	8633
cparata	4:77faf76e3cd8	8634	ret = 0;
cparata	4:77faf76e3cd8	8635
cparata	4:77faf76e3cd8	8636	if (aux_ctx != NULL) {
cparata	4:77faf76e3cd8	8637	ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
cparata	4:77faf76e3cd8	8638	(uint8_t*)&ctrl1_ois, 1);
cparata	4:77faf76e3cd8	8639
cparata	4:77faf76e3cd8	8640	bit_val = ( (uint8_t)val.aux_bus_md & 0x04U ) >> 2;
cparata	4:77faf76e3cd8	8641	if ( ( ret == 0 ) && ( ctrl1_ois.sim_ois != bit_val ) ) {
cparata	4:77faf76e3cd8	8642	ctrl1_ois.sim_ois = bit_val;
cparata	4:77faf76e3cd8	8643	ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
cparata	4:77faf76e3cd8	8644	(uint8_t*)&ctrl1_ois, 1);
cparata	4:77faf76e3cd8	8645	}
cparata	4:77faf76e3cd8	8646	}
cparata	4:77faf76e3cd8	8647
cparata	4:77faf76e3cd8	8648	if (ctx != NULL) {
cparata	4:77faf76e3cd8	8649	if (ret == 0) {
cparata	4:77faf76e3cd8	8650	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
cparata	4:77faf76e3cd8	8651	(uint8_t*)&ctrl9_xl, 1);
cparata	4:77faf76e3cd8	8652	}
cparata	4:77faf76e3cd8	8653
cparata	4:77faf76e3cd8	8654	bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
cparata	4:77faf76e3cd8	8655	if ( ( ret == 0 ) && ( ctrl9_xl.i3c_disable != bit_val ) ) {
cparata	4:77faf76e3cd8	8656	ctrl9_xl.i3c_disable = bit_val;
cparata	4:77faf76e3cd8	8657	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL,
cparata	4:77faf76e3cd8	8658	(uint8_t*)&ctrl9_xl, 1);
cparata	4:77faf76e3cd8	8659	}
cparata	4:77faf76e3cd8	8660
cparata	4:77faf76e3cd8	8661	if (ret == 0) {
cparata	4:77faf76e3cd8	8662	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	4:77faf76e3cd8	8663	(uint8_t*)&i3c_bus_avb, 1);
cparata	4:77faf76e3cd8	8664	}
cparata	4:77faf76e3cd8	8665
cparata	4:77faf76e3cd8	8666	bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
cparata	4:77faf76e3cd8	8667	if ( ( ret == 0 ) && ( i3c_bus_avb.i3c_bus_avb_sel != bit_val ) ) {
cparata	4:77faf76e3cd8	8668	i3c_bus_avb.i3c_bus_avb_sel = bit_val;
cparata	4:77faf76e3cd8	8669	ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	4:77faf76e3cd8	8670	(uint8_t*)&i3c_bus_avb, 1);
cparata	4:77faf76e3cd8	8671	}
cparata	4:77faf76e3cd8	8672	if (ret == 0) {
cparata	4:77faf76e3cd8	8673	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
cparata	4:77faf76e3cd8	8674	(uint8_t*)&ctrl4_c, 1);
cparata	4:77faf76e3cd8	8675	}
cparata	4:77faf76e3cd8	8676	bit_val = ( (uint8_t)val.ui_bus_md & 0x02U ) >> 1;
cparata	4:77faf76e3cd8	8677	if ( ( ret == 0 ) && ( ctrl4_c.i2c_disable != bit_val ) ) {
cparata	4:77faf76e3cd8	8678	ctrl4_c.i2c_disable = bit_val;
cparata	4:77faf76e3cd8	8679	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C,
cparata	4:77faf76e3cd8	8680	(uint8_t*)&ctrl4_c, 1);
cparata	4:77faf76e3cd8	8681	}
cparata	4:77faf76e3cd8	8682	if (ret == 0) {
cparata	4:77faf76e3cd8	8683	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
cparata	4:77faf76e3cd8	8684	(uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8685	}
cparata	4:77faf76e3cd8	8686	bit_val = (uint8_t)val.ui_bus_md & 0x01U;
cparata	4:77faf76e3cd8	8687	if ( ( ret == 0 ) && ( ctrl3_c.sim != bit_val ) ) {
cparata	4:77faf76e3cd8	8688	ctrl3_c.sim = bit_val;
cparata	4:77faf76e3cd8	8689	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C,
cparata	4:77faf76e3cd8	8690	(uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8691	}
cparata	4:77faf76e3cd8	8692	}
cparata	4:77faf76e3cd8	8693
cparata	4:77faf76e3cd8	8694	return ret;
cparata	4:77faf76e3cd8	8695
cparata	4:77faf76e3cd8	8696	}
cparata	4:77faf76e3cd8	8697
cparata	4:77faf76e3cd8	8698	/**
cparata	4:77faf76e3cd8	8699	* @brief Get the bus operating mode.[get]
cparata	4:77faf76e3cd8	8700	*
cparata	4:77faf76e3cd8	8701	* @param ctx communication interface handler. Use NULL to ingnore
cparata	4:77faf76e3cd8	8702	* this interface.(ptr)
cparata	4:77faf76e3cd8	8703	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	4:77faf76e3cd8	8704	* to ingnore this interface.(ptr)
cparata	4:77faf76e3cd8	8705	* @param val retrieves the bus operating mode for both the main
cparata	4:77faf76e3cd8	8706	* and the auxiliary interface.(ptr)
cparata	4:77faf76e3cd8	8707	*
cparata	4:77faf76e3cd8	8708	*/
cparata	4:77faf76e3cd8	8709	int32_t lsm6dso_bus_mode_get(lsm6dso_ctx_t ctx, lsm6dso_ctx_t aux_ctx,
cparata	4:77faf76e3cd8	8710	lsm6dso_bus_mode_t *val)
cparata	4:77faf76e3cd8	8711	{
cparata	4:77faf76e3cd8	8712	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	4:77faf76e3cd8	8713	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	4:77faf76e3cd8	8714	lsm6dso_ctrl9_xl_t ctrl9_xl;
cparata	4:77faf76e3cd8	8715	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	8716	lsm6dso_ctrl4_c_t ctrl4_c;
cparata	4:77faf76e3cd8	8717
cparata	4:77faf76e3cd8	8718	int32_t ret = 0;
cparata	4:77faf76e3cd8	8719
cparata	4:77faf76e3cd8	8720	if (aux_ctx != NULL) {
cparata	4:77faf76e3cd8	8721	ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
cparata	4:77faf76e3cd8	8722	(uint8_t*)&ctrl1_ois, 1);
cparata	4:77faf76e3cd8	8723	switch ( ctrl1_ois.sim_ois ) {
cparata	4:77faf76e3cd8	8724	case LSM6DSO_SPI_4W_AUX:
cparata	4:77faf76e3cd8	8725	val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
cparata	4:77faf76e3cd8	8726	break;
cparata	4:77faf76e3cd8	8727	case LSM6DSO_SPI_3W_AUX:
cparata	4:77faf76e3cd8	8728	val->aux_bus_md = LSM6DSO_SPI_3W_AUX;
cparata	4:77faf76e3cd8	8729	break;
cparata	4:77faf76e3cd8	8730	default:
cparata	4:77faf76e3cd8	8731	val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
cparata	4:77faf76e3cd8	8732	break;
cparata	4:77faf76e3cd8	8733	}
cparata	4:77faf76e3cd8	8734	}
cparata	4:77faf76e3cd8	8735
cparata	4:77faf76e3cd8	8736	if (ctx != NULL) {
cparata	4:77faf76e3cd8	8737	if (ret == 0) {
cparata	4:77faf76e3cd8	8738	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
cparata	4:77faf76e3cd8	8739	(uint8_t*)&ctrl9_xl, 1);
cparata	4:77faf76e3cd8	8740	}
cparata	4:77faf76e3cd8	8741	if (ret == 0) {
cparata	4:77faf76e3cd8	8742	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	4:77faf76e3cd8	8743	(uint8_t*)&i3c_bus_avb, 1);
cparata	4:77faf76e3cd8	8744	}
cparata	4:77faf76e3cd8	8745	if (ret == 0) {
cparata	4:77faf76e3cd8	8746	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
cparata	4:77faf76e3cd8	8747	(uint8_t*)&ctrl4_c, 1);
cparata	4:77faf76e3cd8	8748	}
cparata	3:4274d9103f1d	8749	if (ret == 0) {
cparata	4:77faf76e3cd8	8750	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
cparata	4:77faf76e3cd8	8751	(uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8752
cparata	4:77faf76e3cd8	8753	switch ( ( i3c_bus_avb.i3c_bus_avb_sel << 4 ) &
cparata	4:77faf76e3cd8	8754	( ctrl9_xl.i3c_disable << 2 ) &
cparata	4:77faf76e3cd8	8755	( ctrl4_c.i2c_disable << 1) & ctrl3_c.sim ) {
cparata	4:77faf76e3cd8	8756	case LSM6DSO_SEL_BY_HW:
cparata	4:77faf76e3cd8	8757	val->ui_bus_md = LSM6DSO_SEL_BY_HW;
cparata	4:77faf76e3cd8	8758	break;
cparata	4:77faf76e3cd8	8759	case LSM6DSO_SPI_4W:
cparata	4:77faf76e3cd8	8760	val->ui_bus_md = LSM6DSO_SPI_4W;
cparata	4:77faf76e3cd8	8761	break;
cparata	4:77faf76e3cd8	8762	case LSM6DSO_SPI_3W:
cparata	4:77faf76e3cd8	8763	val->ui_bus_md = LSM6DSO_SPI_3W;
cparata	4:77faf76e3cd8	8764	break;
cparata	4:77faf76e3cd8	8765	case LSM6DSO_I2C:
cparata	4:77faf76e3cd8	8766	val->ui_bus_md = LSM6DSO_I2C;
cparata	4:77faf76e3cd8	8767	break;
cparata	4:77faf76e3cd8	8768	case LSM6DSO_I3C_T_50us:
cparata	4:77faf76e3cd8	8769	val->ui_bus_md = LSM6DSO_I3C_T_50us;
cparata	4:77faf76e3cd8	8770	break;
cparata	4:77faf76e3cd8	8771	case LSM6DSO_I3C_T_2us:
cparata	4:77faf76e3cd8	8772	val->ui_bus_md = LSM6DSO_I3C_T_2us;
cparata	4:77faf76e3cd8	8773	break;
cparata	4:77faf76e3cd8	8774	case LSM6DSO_I3C_T_1ms:
cparata	4:77faf76e3cd8	8775	val->ui_bus_md = LSM6DSO_I3C_T_1ms;
cparata	4:77faf76e3cd8	8776	break;
cparata	4:77faf76e3cd8	8777	case LSM6DSO_I3C_T_25ms:
cparata	4:77faf76e3cd8	8778	val->ui_bus_md = LSM6DSO_I3C_T_25ms;
cparata	4:77faf76e3cd8	8779	break;
cparata	4:77faf76e3cd8	8780	default:
cparata	4:77faf76e3cd8	8781	val->ui_bus_md = LSM6DSO_SEL_BY_HW;
cparata	4:77faf76e3cd8	8782	break;
cparata	4:77faf76e3cd8	8783	}
cparata	4:77faf76e3cd8	8784	}
cparata	4:77faf76e3cd8	8785	}
cparata	4:77faf76e3cd8	8786	return ret;
cparata	4:77faf76e3cd8	8787	}
cparata	4:77faf76e3cd8	8788
cparata	4:77faf76e3cd8	8789	/**
cparata	4:77faf76e3cd8	8790	* @brief Get the status of the device.[get]
cparata	4:77faf76e3cd8	8791	*
cparata	4:77faf76e3cd8	8792	* @param ctx communication interface handler. Use NULL to ingnore
cparata	4:77faf76e3cd8	8793	* this interface.(ptr)
cparata	4:77faf76e3cd8	8794	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	4:77faf76e3cd8	8795	* to ingnore this interface.(ptr)
cparata	4:77faf76e3cd8	8796	* @param val the status of the device.(ptr)
cparata	4:77faf76e3cd8	8797	*
cparata	4:77faf76e3cd8	8798	*/
cparata	4:77faf76e3cd8	8799	int32_t lsm6dso_status_get(lsm6dso_ctx_t ctx, lsm6dso_ctx_t aux_ctx,
cparata	4:77faf76e3cd8	8800	lsm6dso_status_t *val)
cparata	4:77faf76e3cd8	8801	{
cparata	4:77faf76e3cd8	8802	lsm6dso_status_spiaux_t status_spiaux;
cparata	4:77faf76e3cd8	8803	lsm6dso_status_reg_t status_reg;
cparata	4:77faf76e3cd8	8804	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	8805	int32_t ret;
cparata	4:77faf76e3cd8	8806
cparata	4:77faf76e3cd8	8807	ret = 0;
cparata	4:77faf76e3cd8	8808
cparata	4:77faf76e3cd8	8809	if (aux_ctx != NULL){
cparata	4:77faf76e3cd8	8810	ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_STATUS_SPIAUX,
cparata	4:77faf76e3cd8	8811	(uint8_t*)&status_spiaux, 1);
cparata	4:77faf76e3cd8	8812	val->ois_drdy_xl = status_spiaux.xlda;
cparata	4:77faf76e3cd8	8813	val->ois_drdy_g = status_spiaux.gda;
cparata	4:77faf76e3cd8	8814	val->ois_gyro_settling = status_spiaux.gyro_settling;
cparata	4:77faf76e3cd8	8815	}
cparata	4:77faf76e3cd8	8816
cparata	4:77faf76e3cd8	8817	if (ctx != NULL){
cparata	4:77faf76e3cd8	8818	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8819	val->sw_reset = ctrl3_c.sw_reset;
cparata	4:77faf76e3cd8	8820	val->boot = ctrl3_c.boot;
cparata	4:77faf76e3cd8	8821
cparata	4:77faf76e3cd8	8822	if ( (ret == 0) && ( ctrl3_c.sw_reset == PROPERTY_DISABLE ) &&
cparata	4:77faf76e3cd8	8823	( ctrl3_c.boot == PROPERTY_DISABLE ) ) {
cparata	4:77faf76e3cd8	8824	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG,
cparata	4:77faf76e3cd8	8825	(uint8_t*)&status_reg, 1);
cparata	4:77faf76e3cd8	8826	val->drdy_xl = status_reg.xlda;
cparata	4:77faf76e3cd8	8827	val->drdy_g = status_reg.gda;
cparata	4:77faf76e3cd8	8828	val->drdy_temp = status_reg.tda;
cparata	4:77faf76e3cd8	8829	}
cparata	4:77faf76e3cd8	8830	}
cparata	4:77faf76e3cd8	8831	return ret;
cparata	4:77faf76e3cd8	8832	}
cparata	4:77faf76e3cd8	8833
cparata	4:77faf76e3cd8	8834	/**
cparata	4:77faf76e3cd8	8835	* @brief Electrical pin configuration.[set]
cparata	4:77faf76e3cd8	8836	*
cparata	4:77faf76e3cd8	8837	* @param ctx communication interface handler.(ptr)
cparata	4:77faf76e3cd8	8838	* @param val the electrical settings for the configurable
cparata	4:77faf76e3cd8	8839	* pins.
cparata	4:77faf76e3cd8	8840	*
cparata	4:77faf76e3cd8	8841	*/
cparata	4:77faf76e3cd8	8842	int32_t lsm6dso_pin_conf_set(lsm6dso_ctx_t *ctx, lsm6dso_pin_conf_t val)
cparata	4:77faf76e3cd8	8843	{
cparata	4:77faf76e3cd8	8844	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	4:77faf76e3cd8	8845	lsm6dso_pin_ctrl_t pin_ctrl;
cparata	4:77faf76e3cd8	8846	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	8847	int32_t ret;
cparata	4:77faf76e3cd8	8848
cparata	4:77faf76e3cd8	8849	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
cparata	4:77faf76e3cd8	8850	if (ret == 0) {
cparata	4:77faf76e3cd8	8851	pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up;
cparata	4:77faf76e3cd8	8852	pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
cparata	4:77faf76e3cd8	8853	ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
cparata	4:77faf76e3cd8	8854	}
cparata	4:77faf76e3cd8	8855	if (ret == 0) {
cparata	4:77faf76e3cd8	8856	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8857	}
cparata	4:77faf76e3cd8	8858	if (ret == 0) {
cparata	4:77faf76e3cd8	8859	ctrl3_c.pp_od = ~val.int1_int2_push_pull;
cparata	4:77faf76e3cd8	8860	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8861	}
cparata	4:77faf76e3cd8	8862	if (ret == 0) {
cparata	4:77faf76e3cd8	8863	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	4:77faf76e3cd8	8864	(uint8_t*)&i3c_bus_avb, 1);
cparata	4:77faf76e3cd8	8865	}
cparata	4:77faf76e3cd8	8866	if (ret == 0) {
cparata	4:77faf76e3cd8	8867	i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
cparata	4:77faf76e3cd8	8868	ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	4:77faf76e3cd8	8869	(uint8_t*)&i3c_bus_avb, 1);
cparata	4:77faf76e3cd8	8870	}
cparata	4:77faf76e3cd8	8871	return ret;
cparata	4:77faf76e3cd8	8872	}
cparata	4:77faf76e3cd8	8873
cparata	4:77faf76e3cd8	8874	/**
cparata	4:77faf76e3cd8	8875	* @brief Electrical pin configuration.[get]
cparata	4:77faf76e3cd8	8876	*
cparata	4:77faf76e3cd8	8877	* @param ctx communication interface handler.(ptr)
cparata	4:77faf76e3cd8	8878	* @param val the electrical settings for the configurable
cparata	4:77faf76e3cd8	8879	* pins.(ptr)
cparata	4:77faf76e3cd8	8880	*
cparata	4:77faf76e3cd8	8881	*/
cparata	4:77faf76e3cd8	8882	int32_t lsm6dso_pin_conf_get(lsm6dso_ctx_t ctx, lsm6dso_pin_conf_t val)
cparata	4:77faf76e3cd8	8883	{
cparata	4:77faf76e3cd8	8884	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	4:77faf76e3cd8	8885	lsm6dso_pin_ctrl_t pin_ctrl;
cparata	4:77faf76e3cd8	8886	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	8887	int32_t ret;
cparata	4:77faf76e3cd8	8888
cparata	4:77faf76e3cd8	8889	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&pin_ctrl, 1);
cparata	4:77faf76e3cd8	8890	if (ret == 0) {
cparata	4:77faf76e3cd8	8891	val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis;
cparata	4:77faf76e3cd8	8892	val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
cparata	4:77faf76e3cd8	8893	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8894	}
cparata	4:77faf76e3cd8	8895	if (ret == 0) {
cparata	4:77faf76e3cd8	8896	val->int1_int2_push_pull = ~ctrl3_c.pp_od;
cparata	4:77faf76e3cd8	8897	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	4:77faf76e3cd8	8898	(uint8_t*)&i3c_bus_avb, 1);
cparata	4:77faf76e3cd8	8899	}
cparata	4:77faf76e3cd8	8900	if (ret == 0) {
cparata	4:77faf76e3cd8	8901	val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
cparata	4:77faf76e3cd8	8902	}
cparata	4:77faf76e3cd8	8903	return ret;
cparata	4:77faf76e3cd8	8904	}
cparata	4:77faf76e3cd8	8905
cparata	4:77faf76e3cd8	8906	/**
cparata	4:77faf76e3cd8	8907	* @brief Interrupt pins hardware signal configuration.[set]
cparata	4:77faf76e3cd8	8908	*
cparata	4:77faf76e3cd8	8909	* @param ctx communication interface handler.(ptr)
cparata	4:77faf76e3cd8	8910	* @param val the pins hardware signal settings.
cparata	4:77faf76e3cd8	8911	*
cparata	4:77faf76e3cd8	8912	*/
cparata	4:77faf76e3cd8	8913	int32_t lsm6dso_interrupt_mode_set(lsm6dso_ctx_t *ctx,
cparata	4:77faf76e3cd8	8914	lsm6dso_int_mode_t val)
cparata	4:77faf76e3cd8	8915	{
cparata	4:77faf76e3cd8	8916	lsm6dso_tap_cfg0_t tap_cfg0;
cparata	4:77faf76e3cd8	8917	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	8918	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	8919	int32_t ret;
cparata	4:77faf76e3cd8	8920
cparata	4:77faf76e3cd8	8921	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8922	if (ret == 0) {
cparata	4:77faf76e3cd8	8923	ctrl3_c.h_lactive = val.active_low;
cparata	4:77faf76e3cd8	8924	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8925	}
cparata	4:77faf76e3cd8	8926	if (ret == 0) {
cparata	4:77faf76e3cd8	8927	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	4:77faf76e3cd8	8928	}
cparata	4:77faf76e3cd8	8929	if (ret == 0) {
cparata	4:77faf76e3cd8	8930	tap_cfg0.lir = val.base_latched;
cparata	4:77faf76e3cd8	8931	tap_cfg0.int_clr_on_read = val.base_latched \| val.emb_latched;
cparata	4:77faf76e3cd8	8932	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	4:77faf76e3cd8	8933	}
cparata	4:77faf76e3cd8	8934	if (ret == 0) {
cparata	4:77faf76e3cd8	8935	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	8936	}
cparata	4:77faf76e3cd8	8937	if (ret == 0) {
cparata	4:77faf76e3cd8	8938	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	8939	}
cparata	4:77faf76e3cd8	8940	if (ret == 0) {
cparata	4:77faf76e3cd8	8941	page_rw.emb_func_lir = val.emb_latched;
cparata	4:77faf76e3cd8	8942	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	8943	}
cparata	4:77faf76e3cd8	8944	if (ret == 0) {
cparata	4:77faf76e3cd8	8945	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8946	}
cparata	4:77faf76e3cd8	8947	return ret;
cparata	4:77faf76e3cd8	8948	}
cparata	4:77faf76e3cd8	8949
cparata	4:77faf76e3cd8	8950	/**
cparata	4:77faf76e3cd8	8951	* @brief Interrupt pins hardware signal configuration.[get]
cparata	4:77faf76e3cd8	8952	*
cparata	4:77faf76e3cd8	8953	* @param ctx communication interface handler.(ptr)
cparata	4:77faf76e3cd8	8954	* @param val the pins hardware signal settings.(ptr)
cparata	4:77faf76e3cd8	8955	*
cparata	4:77faf76e3cd8	8956	*/
cparata	4:77faf76e3cd8	8957	int32_t lsm6dso_interrupt_mode_get(lsm6dso_ctx_t *ctx,
cparata	4:77faf76e3cd8	8958	lsm6dso_int_mode_t *val)
cparata	4:77faf76e3cd8	8959	{
cparata	4:77faf76e3cd8	8960	lsm6dso_tap_cfg0_t tap_cfg0;
cparata	4:77faf76e3cd8	8961	lsm6dso_page_rw_t page_rw;
cparata	4:77faf76e3cd8	8962	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	8963	int32_t ret;
cparata	4:77faf76e3cd8	8964
cparata	4:77faf76e3cd8	8965	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1);
cparata	4:77faf76e3cd8	8966	if (ret == 0) {
cparata	4:77faf76e3cd8	8967	ctrl3_c.h_lactive = val->active_low;
cparata	4:77faf76e3cd8	8968	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	4:77faf76e3cd8	8969	}
cparata	4:77faf76e3cd8	8970	if (ret == 0) {
cparata	4:77faf76e3cd8	8971	tap_cfg0.lir = val->base_latched;
cparata	4:77faf76e3cd8	8972	tap_cfg0.int_clr_on_read = val->base_latched \| val->emb_latched;
cparata	4:77faf76e3cd8	8973	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	8974	}
cparata	4:77faf76e3cd8	8975	if (ret == 0) {
cparata	4:77faf76e3cd8	8976	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	8977	}
cparata	4:77faf76e3cd8	8978	if (ret == 0) {
cparata	4:77faf76e3cd8	8979	page_rw.emb_func_lir = val->emb_latched;
cparata	4:77faf76e3cd8	8980	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	4:77faf76e3cd8	8981	}
cparata	4:77faf76e3cd8	8982	if (ret == 0) {
cparata	4:77faf76e3cd8	8983	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	8984	}
cparata	4:77faf76e3cd8	8985	return ret;
cparata	4:77faf76e3cd8	8986	}
cparata	4:77faf76e3cd8	8987
cparata	4:77faf76e3cd8	8988	/**
cparata	4:77faf76e3cd8	8989	* @brief Route interrupt signals on int1 pin.[set]
cparata	4:77faf76e3cd8	8990	*
cparata	4:77faf76e3cd8	8991	* @param ctx communication interface handler.(ptr)
cparata	4:77faf76e3cd8	8992	* @param val the signals to route on int1 pin.
cparata	4:77faf76e3cd8	8993	*
cparata	4:77faf76e3cd8	8994	*/
cparata	4:77faf76e3cd8	8995	int32_t lsm6dso_pin_int1_route_set(lsm6dso_ctx_t *ctx,
cparata	4:77faf76e3cd8	8996	lsm6dso_pin_int1_route_t val)
cparata	4:77faf76e3cd8	8997	{
cparata	4:77faf76e3cd8	8998	lsm6dso_pin_int2_route_t pin_int2_route;
cparata	4:77faf76e3cd8	8999	lsm6dso_emb_func_int1_t emb_func_int1;
cparata	4:77faf76e3cd8	9000	lsm6dso_fsm_int1_a_t fsm_int1_a;
cparata	4:77faf76e3cd8	9001	lsm6dso_fsm_int1_b_t fsm_int1_b;
cparata	4:77faf76e3cd8	9002	lsm6dso_int1_ctrl_t int1_ctrl;
cparata	4:77faf76e3cd8	9003	lsm6dso_int2_ctrl_t int2_ctrl;
cparata	4:77faf76e3cd8	9004	lsm6dso_tap_cfg2_t tap_cfg2;
cparata	4:77faf76e3cd8	9005	lsm6dso_md2_cfg_t md2_cfg;
cparata	4:77faf76e3cd8	9006	lsm6dso_md1_cfg_t md1_cfg;
cparata	4:77faf76e3cd8	9007	lsm6dso_ctrl4_c_t ctrl4_c;
cparata	4:77faf76e3cd8	9008	int32_t ret;
cparata	4:77faf76e3cd8	9009
cparata	4:77faf76e3cd8	9010	int1_ctrl.int1_drdy_xl = val.drdy_xl;
cparata	4:77faf76e3cd8	9011	int1_ctrl.int1_drdy_g = val.drdy_g;
cparata	4:77faf76e3cd8	9012	int1_ctrl.int1_boot = val.boot;
cparata	4:77faf76e3cd8	9013	int1_ctrl.int1_fifo_th = val.fifo_th;
cparata	4:77faf76e3cd8	9014	int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
cparata	4:77faf76e3cd8	9015	int1_ctrl.int1_fifo_full = val.fifo_full;
cparata	4:77faf76e3cd8	9016	int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
cparata	4:77faf76e3cd8	9017	int1_ctrl.den_drdy_flag = val.den_flag;
cparata	4:77faf76e3cd8	9018
cparata	4:77faf76e3cd8	9019	md1_cfg.int1_shub = val.sh_endop;
cparata	4:77faf76e3cd8	9020	md1_cfg.int1_6d = val.six_d;
cparata	4:77faf76e3cd8	9021	md1_cfg.int1_double_tap = val.double_tap;
cparata	4:77faf76e3cd8	9022	md1_cfg.int1_ff = val.free_fall;
cparata	4:77faf76e3cd8	9023	md1_cfg.int1_wu = val.wake_up;
cparata	4:77faf76e3cd8	9024	md1_cfg.int1_single_tap = val.single_tap;
cparata	4:77faf76e3cd8	9025	md1_cfg.int1_sleep_change = val.sleep_change;
cparata	4:77faf76e3cd8	9026
cparata	4:77faf76e3cd8	9027	emb_func_int1.int1_step_detector = val.step_detector;
cparata	4:77faf76e3cd8	9028	emb_func_int1.int1_tilt = val.tilt;
cparata	4:77faf76e3cd8	9029	emb_func_int1.int1_sig_mot = val.sig_mot;
cparata	4:77faf76e3cd8	9030	emb_func_int1.int1_fsm_lc = val.fsm_lc;
cparata	4:77faf76e3cd8	9031
cparata	4:77faf76e3cd8	9032	fsm_int1_a.int1_fsm1 = val.fsm1;
cparata	4:77faf76e3cd8	9033	fsm_int1_a.int1_fsm2 = val.fsm2;
cparata	4:77faf76e3cd8	9034	fsm_int1_a.int1_fsm3 = val.fsm3;
cparata	4:77faf76e3cd8	9035	fsm_int1_a.int1_fsm4 = val.fsm4;
cparata	4:77faf76e3cd8	9036	fsm_int1_a.int1_fsm5 = val.fsm5;
cparata	4:77faf76e3cd8	9037	fsm_int1_a.int1_fsm6 = val.fsm6;
cparata	4:77faf76e3cd8	9038	fsm_int1_a.int1_fsm7 = val.fsm7;
cparata	4:77faf76e3cd8	9039	fsm_int1_a.int1_fsm8 = val.fsm8;
cparata	4:77faf76e3cd8	9040
cparata	4:77faf76e3cd8	9041	fsm_int1_b.int1_fsm9 = val.fsm9 ;
cparata	4:77faf76e3cd8	9042	fsm_int1_b.int1_fsm10 = val.fsm10;
cparata	4:77faf76e3cd8	9043	fsm_int1_b.int1_fsm11 = val.fsm11;
cparata	4:77faf76e3cd8	9044	fsm_int1_b.int1_fsm12 = val.fsm12;
cparata	4:77faf76e3cd8	9045	fsm_int1_b.int1_fsm13 = val.fsm13;
cparata	4:77faf76e3cd8	9046	fsm_int1_b.int1_fsm14 = val.fsm14;
cparata	4:77faf76e3cd8	9047	fsm_int1_b.int1_fsm15 = val.fsm15;
cparata	4:77faf76e3cd8	9048	fsm_int1_b.int1_fsm16 = val.fsm16;
cparata	4:77faf76e3cd8	9049
cparata	4:77faf76e3cd8	9050	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	4:77faf76e3cd8	9051	if (ret == 0) {
cparata	4:77faf76e3cd8	9052	if( ( val.drdy_temp \| val.timestamp ) != PROPERTY_DISABLE) {
cparata	4:77faf76e3cd8	9053	ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	9054	}
cparata	4:77faf76e3cd8	9055	else{
cparata	4:77faf76e3cd8	9056	ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9057	}
cparata	4:77faf76e3cd8	9058	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	4:77faf76e3cd8	9059	}
cparata	4:77faf76e3cd8	9060
cparata	4:77faf76e3cd8	9061	if (ret == 0) {
cparata	4:77faf76e3cd8	9062	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	9063	}
cparata	4:77faf76e3cd8	9064	if (ret == 0) {
cparata	4:77faf76e3cd8	9065	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
cparata	4:77faf76e3cd8	9066	(uint8_t*)&emb_func_int1, 1);
cparata	4:77faf76e3cd8	9067	}
cparata	4:77faf76e3cd8	9068	if (ret == 0) {
cparata	4:77faf76e3cd8	9069	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_A,
cparata	4:77faf76e3cd8	9070	(uint8_t*)&fsm_int1_a, 1);
cparata	4:77faf76e3cd8	9071	}
cparata	4:77faf76e3cd8	9072	if (ret == 0) {
cparata	4:77faf76e3cd8	9073	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_B,
cparata	4:77faf76e3cd8	9074	(uint8_t*)&fsm_int1_b, 1);
cparata	4:77faf76e3cd8	9075	}
cparata	4:77faf76e3cd8	9076	if (ret == 0) {
cparata	4:77faf76e3cd8	9077	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	9078	}
cparata	4:77faf76e3cd8	9079
cparata	4:77faf76e3cd8	9080	if (ret == 0) {
cparata	4:77faf76e3cd8	9081	if ( ( emb_func_int1.int1_fsm_lc
cparata	4:77faf76e3cd8	9082	\| emb_func_int1.int1_sig_mot
cparata	4:77faf76e3cd8	9083	\| emb_func_int1.int1_step_detector
cparata	4:77faf76e3cd8	9084	\| emb_func_int1.int1_tilt
cparata	4:77faf76e3cd8	9085	\| fsm_int1_a.int1_fsm1
cparata	4:77faf76e3cd8	9086	\| fsm_int1_a.int1_fsm2
cparata	4:77faf76e3cd8	9087	\| fsm_int1_a.int1_fsm3
cparata	4:77faf76e3cd8	9088	\| fsm_int1_a.int1_fsm4
cparata	4:77faf76e3cd8	9089	\| fsm_int1_a.int1_fsm5
cparata	4:77faf76e3cd8	9090	\| fsm_int1_a.int1_fsm6
cparata	4:77faf76e3cd8	9091	\| fsm_int1_a.int1_fsm7
cparata	4:77faf76e3cd8	9092	\| fsm_int1_a.int1_fsm8
cparata	4:77faf76e3cd8	9093	\| fsm_int1_b.int1_fsm9
cparata	4:77faf76e3cd8	9094	\| fsm_int1_b.int1_fsm10
cparata	4:77faf76e3cd8	9095	\| fsm_int1_b.int1_fsm11
cparata	4:77faf76e3cd8	9096	\| fsm_int1_b.int1_fsm12
cparata	4:77faf76e3cd8	9097	\| fsm_int1_b.int1_fsm13
cparata	4:77faf76e3cd8	9098	\| fsm_int1_b.int1_fsm14
cparata	4:77faf76e3cd8	9099	\| fsm_int1_b.int1_fsm15
cparata	4:77faf76e3cd8	9100	\| fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE){
cparata	4:77faf76e3cd8	9101	md1_cfg.int1_emb_func = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	9102	}
cparata	4:77faf76e3cd8	9103	else{
cparata	4:77faf76e3cd8	9104	md1_cfg.int1_emb_func = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9105	}
cparata	4:77faf76e3cd8	9106	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT1_CTRL,
cparata	4:77faf76e3cd8	9107	(uint8_t*)&int1_ctrl, 1);
cparata	4:77faf76e3cd8	9108	}
cparata	4:77faf76e3cd8	9109	if (ret == 0) {
cparata	4:77faf76e3cd8	9110	ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t*)&md1_cfg, 1);
cparata	4:77faf76e3cd8	9111	}
cparata	4:77faf76e3cd8	9112
cparata	4:77faf76e3cd8	9113	if (ret == 0) {
cparata	4:77faf76e3cd8	9114	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
cparata	4:77faf76e3cd8	9115	}
cparata	4:77faf76e3cd8	9116	if (ret == 0) {
cparata	4:77faf76e3cd8	9117	int2_ctrl.int2_drdy_temp = val.drdy_temp;
cparata	4:77faf76e3cd8	9118	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
cparata	4:77faf76e3cd8	9119	}
cparata	4:77faf76e3cd8	9120	if (ret == 0) {
cparata	4:77faf76e3cd8	9121	ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	4:77faf76e3cd8	9122	}
cparata	4:77faf76e3cd8	9123	if (ret == 0) {
cparata	4:77faf76e3cd8	9124	md2_cfg.int2_timestamp = val.timestamp;
cparata	4:77faf76e3cd8	9125	ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	4:77faf76e3cd8	9126	}
cparata	4:77faf76e3cd8	9127
cparata	4:77faf76e3cd8	9128	if (ret == 0) {
cparata	4:77faf76e3cd8	9129	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	4:77faf76e3cd8	9130	}
cparata	4:77faf76e3cd8	9131	if (ret == 0) {
cparata	4:77faf76e3cd8	9132	ret = lsm6dso_pin_int2_route_get(ctx, NULL, &pin_int2_route);
cparata	4:77faf76e3cd8	9133	}
cparata	4:77faf76e3cd8	9134	if (ret == 0) {
cparata	4:77faf76e3cd8	9135	if ( ( pin_int2_route.fifo_bdr
cparata	4:77faf76e3cd8	9136	\| pin_int2_route.drdy_g
cparata	4:77faf76e3cd8	9137	\| pin_int2_route.drdy_temp
cparata	4:77faf76e3cd8	9138	\| pin_int2_route.drdy_xl
cparata	4:77faf76e3cd8	9139	\| pin_int2_route.fifo_full
cparata	4:77faf76e3cd8	9140	\| pin_int2_route.fifo_ovr
cparata	4:77faf76e3cd8	9141	\| pin_int2_route.fifo_th
cparata	4:77faf76e3cd8	9142	\| pin_int2_route.six_d
cparata	4:77faf76e3cd8	9143	\| pin_int2_route.double_tap
cparata	4:77faf76e3cd8	9144	\| pin_int2_route.free_fall
cparata	4:77faf76e3cd8	9145	\| pin_int2_route.wake_up
cparata	4:77faf76e3cd8	9146	\| pin_int2_route.single_tap
cparata	4:77faf76e3cd8	9147	\| pin_int2_route.sleep_change
cparata	4:77faf76e3cd8	9148	\| int1_ctrl.den_drdy_flag
cparata	4:77faf76e3cd8	9149	\| int1_ctrl.int1_boot
cparata	4:77faf76e3cd8	9150	\| int1_ctrl.int1_cnt_bdr
cparata	4:77faf76e3cd8	9151	\| int1_ctrl.int1_drdy_g
cparata	4:77faf76e3cd8	9152	\| int1_ctrl.int1_drdy_xl
cparata	4:77faf76e3cd8	9153	\| int1_ctrl.int1_fifo_full
cparata	4:77faf76e3cd8	9154	\| int1_ctrl.int1_fifo_ovr
cparata	4:77faf76e3cd8	9155	\| int1_ctrl.int1_fifo_th
cparata	4:77faf76e3cd8	9156	\| md1_cfg.int1_shub
cparata	4:77faf76e3cd8	9157	\| md1_cfg.int1_6d
cparata	4:77faf76e3cd8	9158	\| md1_cfg.int1_double_tap
cparata	4:77faf76e3cd8	9159	\| md1_cfg.int1_ff
cparata	4:77faf76e3cd8	9160	\| md1_cfg.int1_wu
cparata	4:77faf76e3cd8	9161	\| md1_cfg.int1_single_tap
cparata	4:77faf76e3cd8	9162	\| md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
cparata	4:77faf76e3cd8	9163	tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	9164	}
cparata	4:77faf76e3cd8	9165	else{
cparata	4:77faf76e3cd8	9166	tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9167	}
cparata	4:77faf76e3cd8	9168	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	4:77faf76e3cd8	9169	}
cparata	4:77faf76e3cd8	9170	return ret;
cparata	4:77faf76e3cd8	9171	}
cparata	4:77faf76e3cd8	9172
cparata	4:77faf76e3cd8	9173	/**
cparata	4:77faf76e3cd8	9174	* @brief Route interrupt signals on int1 pin.[get]
cparata	4:77faf76e3cd8	9175	*
cparata	4:77faf76e3cd8	9176	* @param ctx communication interface handler.(ptr)
cparata	4:77faf76e3cd8	9177	* @param val the signals that are routed on int1 pin.(ptr)
cparata	4:77faf76e3cd8	9178	*
cparata	4:77faf76e3cd8	9179	*/
cparata	4:77faf76e3cd8	9180	int32_t lsm6dso_pin_int1_route_get(lsm6dso_ctx_t *ctx,
cparata	4:77faf76e3cd8	9181	lsm6dso_pin_int1_route_t *val)
cparata	4:77faf76e3cd8	9182	{
cparata	4:77faf76e3cd8	9183	lsm6dso_emb_func_int1_t emb_func_int1;
cparata	4:77faf76e3cd8	9184	lsm6dso_fsm_int1_a_t fsm_int1_a;
cparata	4:77faf76e3cd8	9185	lsm6dso_fsm_int1_b_t fsm_int1_b;
cparata	4:77faf76e3cd8	9186	lsm6dso_int1_ctrl_t int1_ctrl;
cparata	4:77faf76e3cd8	9187	lsm6dso_int2_ctrl_t int2_ctrl;
cparata	4:77faf76e3cd8	9188	lsm6dso_md2_cfg_t md2_cfg;
cparata	4:77faf76e3cd8	9189	lsm6dso_md1_cfg_t md1_cfg;
cparata	4:77faf76e3cd8	9190	lsm6dso_ctrl4_c_t ctrl4_c;
cparata	4:77faf76e3cd8	9191	int32_t ret;
cparata	4:77faf76e3cd8	9192
cparata	4:77faf76e3cd8	9193	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	9194	if (ret == 0) {
cparata	4:77faf76e3cd8	9195	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
cparata	4:77faf76e3cd8	9196	(uint8_t*)&emb_func_int1, 1);
cparata	4:77faf76e3cd8	9197	}
cparata	4:77faf76e3cd8	9198	if (ret == 0) {
cparata	4:77faf76e3cd8	9199	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_A,
cparata	4:77faf76e3cd8	9200	(uint8_t*)&fsm_int1_a, 1);
cparata	4:77faf76e3cd8	9201	}
cparata	4:77faf76e3cd8	9202	if (ret == 0) {
cparata	4:77faf76e3cd8	9203	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_B,
cparata	4:77faf76e3cd8	9204	(uint8_t*)&fsm_int1_b, 1);
cparata	4:77faf76e3cd8	9205	}
cparata	4:77faf76e3cd8	9206	if (ret == 0) {
cparata	4:77faf76e3cd8	9207	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	9208	}
cparata	4:77faf76e3cd8	9209	if (ret == 0) {
cparata	4:77faf76e3cd8	9210	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT1_CTRL,
cparata	4:77faf76e3cd8	9211	(uint8_t*)&int1_ctrl, 1);
cparata	4:77faf76e3cd8	9212	}
cparata	4:77faf76e3cd8	9213	if (ret == 0) {
cparata	4:77faf76e3cd8	9214	ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t*)&md1_cfg, 1);
cparata	4:77faf76e3cd8	9215	}
cparata	4:77faf76e3cd8	9216	if (ret == 0) {
cparata	4:77faf76e3cd8	9217	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	4:77faf76e3cd8	9218	}
cparata	4:77faf76e3cd8	9219	if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE){
cparata	4:77faf76e3cd8	9220	if (ret == 0) {
cparata	4:77faf76e3cd8	9221	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t*)&int2_ctrl, 1);
cparata	4:77faf76e3cd8	9222	val->drdy_temp = int2_ctrl.int2_drdy_temp;
cparata	4:77faf76e3cd8	9223	}
cparata	4:77faf76e3cd8	9224	if (ret == 0) {
cparata	4:77faf76e3cd8	9225	ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	4:77faf76e3cd8	9226	val->timestamp = md2_cfg.int2_timestamp;
cparata	4:77faf76e3cd8	9227	}
cparata	4:77faf76e3cd8	9228	}
cparata	4:77faf76e3cd8	9229	else {
cparata	4:77faf76e3cd8	9230	val->drdy_temp = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9231	val->timestamp = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9232	}
cparata	4:77faf76e3cd8	9233
cparata	4:77faf76e3cd8	9234	val->drdy_xl = int1_ctrl.int1_drdy_xl;
cparata	4:77faf76e3cd8	9235	val->drdy_g = int1_ctrl.int1_drdy_g;
cparata	4:77faf76e3cd8	9236	val->boot = int1_ctrl.int1_boot;
cparata	4:77faf76e3cd8	9237	val->fifo_th = int1_ctrl.int1_fifo_th;
cparata	4:77faf76e3cd8	9238	val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
cparata	4:77faf76e3cd8	9239	val->fifo_full = int1_ctrl.int1_fifo_full;
cparata	4:77faf76e3cd8	9240	val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
cparata	4:77faf76e3cd8	9241	val->den_flag = int1_ctrl.den_drdy_flag;
cparata	4:77faf76e3cd8	9242
cparata	4:77faf76e3cd8	9243	val->sh_endop = md1_cfg.int1_shub;
cparata	4:77faf76e3cd8	9244	val->six_d = md1_cfg.int1_6d;
cparata	4:77faf76e3cd8	9245	val->double_tap = md1_cfg.int1_double_tap;
cparata	4:77faf76e3cd8	9246	val->free_fall = md1_cfg.int1_ff;
cparata	4:77faf76e3cd8	9247	val->wake_up = md1_cfg.int1_wu;
cparata	4:77faf76e3cd8	9248	val->single_tap = md1_cfg.int1_single_tap;
cparata	4:77faf76e3cd8	9249	val->sleep_change = md1_cfg.int1_sleep_change;
cparata	4:77faf76e3cd8	9250
cparata	4:77faf76e3cd8	9251	val->step_detector = emb_func_int1.int1_step_detector;
cparata	4:77faf76e3cd8	9252	val->tilt = emb_func_int1.int1_tilt;
cparata	4:77faf76e3cd8	9253	val->sig_mot = emb_func_int1.int1_sig_mot;
cparata	4:77faf76e3cd8	9254	val->fsm_lc = emb_func_int1.int1_fsm_lc;
cparata	4:77faf76e3cd8	9255
cparata	4:77faf76e3cd8	9256	val->fsm1 = fsm_int1_a.int1_fsm1;
cparata	4:77faf76e3cd8	9257	val->fsm2 = fsm_int1_a.int1_fsm2;
cparata	4:77faf76e3cd8	9258	val->fsm3 = fsm_int1_a.int1_fsm3;
cparata	4:77faf76e3cd8	9259	val->fsm4 = fsm_int1_a.int1_fsm4;
cparata	4:77faf76e3cd8	9260	val->fsm5 = fsm_int1_a.int1_fsm5;
cparata	4:77faf76e3cd8	9261	val->fsm6 = fsm_int1_a.int1_fsm6;
cparata	4:77faf76e3cd8	9262	val->fsm7 = fsm_int1_a.int1_fsm7;
cparata	4:77faf76e3cd8	9263	val->fsm8 = fsm_int1_a.int1_fsm8;
cparata	4:77faf76e3cd8	9264
cparata	4:77faf76e3cd8	9265	val->fsm9 = fsm_int1_b.int1_fsm9;
cparata	4:77faf76e3cd8	9266	val->fsm10 = fsm_int1_b.int1_fsm10;
cparata	4:77faf76e3cd8	9267	val->fsm11 = fsm_int1_b.int1_fsm11;
cparata	4:77faf76e3cd8	9268	val->fsm12 = fsm_int1_b.int1_fsm12;
cparata	4:77faf76e3cd8	9269	val->fsm13 = fsm_int1_b.int1_fsm13;
cparata	4:77faf76e3cd8	9270	val->fsm14 = fsm_int1_b.int1_fsm14;
cparata	4:77faf76e3cd8	9271	val->fsm15 = fsm_int1_b.int1_fsm15;
cparata	4:77faf76e3cd8	9272	val->fsm16 = fsm_int1_b.int1_fsm16;
cparata	4:77faf76e3cd8	9273
cparata	4:77faf76e3cd8	9274	return ret;
cparata	4:77faf76e3cd8	9275	}
cparata	4:77faf76e3cd8	9276
cparata	4:77faf76e3cd8	9277	/**
cparata	4:77faf76e3cd8	9278	* @brief Route interrupt signals on int2 pin.[set]
cparata	4:77faf76e3cd8	9279	*
cparata	4:77faf76e3cd8	9280	* @param ctx communication interface handler. Use NULL to ingnore
cparata	4:77faf76e3cd8	9281	* this interface.(ptr)
cparata	4:77faf76e3cd8	9282	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	4:77faf76e3cd8	9283	* to ingnore this interface.(ptr)
cparata	4:77faf76e3cd8	9284	* @param val the signals to route on int2 pin.
cparata	4:77faf76e3cd8	9285	*
cparata	4:77faf76e3cd8	9286	*/
cparata	4:77faf76e3cd8	9287	int32_t lsm6dso_pin_int2_route_set(lsm6dso_ctx_t ctx, lsm6dso_ctx_t aux_ctx,
cparata	4:77faf76e3cd8	9288	lsm6dso_pin_int2_route_t val)
cparata	4:77faf76e3cd8	9289	{
cparata	4:77faf76e3cd8	9290	lsm6dso_pin_int1_route_t pin_int1_route;
cparata	4:77faf76e3cd8	9291	lsm6dso_emb_func_int2_t emb_func_int2;
cparata	4:77faf76e3cd8	9292	lsm6dso_fsm_int2_a_t fsm_int2_a;
cparata	4:77faf76e3cd8	9293	lsm6dso_fsm_int2_b_t fsm_int2_b;
cparata	4:77faf76e3cd8	9294	lsm6dso_int2_ctrl_t int2_ctrl;
cparata	4:77faf76e3cd8	9295	lsm6dso_tap_cfg2_t tap_cfg2;
cparata	4:77faf76e3cd8	9296	lsm6dso_md2_cfg_t md2_cfg;
cparata	4:77faf76e3cd8	9297	lsm6dso_ctrl4_c_t ctrl4_c;
cparata	4:77faf76e3cd8	9298	lsm6dso_int_ois_t int_ois;
cparata	4:77faf76e3cd8	9299	int32_t ret;
cparata	4:77faf76e3cd8	9300
cparata	4:77faf76e3cd8	9301	ret = 0;
cparata	4:77faf76e3cd8	9302
cparata	4:77faf76e3cd8	9303	if( aux_ctx != NULL ) {
cparata	4:77faf76e3cd8	9304	ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS,
cparata	4:77faf76e3cd8	9305	(uint8_t*)&int_ois, 1);
cparata	4:77faf76e3cd8	9306	if (ret == 0) {
cparata	4:77faf76e3cd8	9307	int_ois.int2_drdy_ois = val.drdy_ois;
cparata	4:77faf76e3cd8	9308	ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_INT_OIS,
cparata	4:77faf76e3cd8	9309	(uint8_t*)&int_ois, 1);
cparata	4:77faf76e3cd8	9310	}
cparata	4:77faf76e3cd8	9311	}
cparata	4:77faf76e3cd8	9312
cparata	4:77faf76e3cd8	9313	if( ctx != NULL ) {
cparata	4:77faf76e3cd8	9314	int2_ctrl.int2_drdy_xl = val.drdy_xl;
cparata	4:77faf76e3cd8	9315	int2_ctrl.int2_drdy_g = val.drdy_g;
cparata	4:77faf76e3cd8	9316	int2_ctrl.int2_drdy_temp = val.drdy_temp;
cparata	4:77faf76e3cd8	9317	int2_ctrl.int2_fifo_th = val.fifo_th;
cparata	4:77faf76e3cd8	9318	int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
cparata	4:77faf76e3cd8	9319	int2_ctrl.int2_fifo_full = val.fifo_full;
cparata	4:77faf76e3cd8	9320	int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
cparata	4:77faf76e3cd8	9321
cparata	4:77faf76e3cd8	9322	md2_cfg.int2_timestamp = val.timestamp;
cparata	4:77faf76e3cd8	9323	md2_cfg.int2_6d = val.six_d;
cparata	4:77faf76e3cd8	9324	md2_cfg.int2_double_tap = val.double_tap;
cparata	4:77faf76e3cd8	9325	md2_cfg.int2_ff = val.free_fall;
cparata	4:77faf76e3cd8	9326	md2_cfg.int2_wu = val.wake_up;
cparata	4:77faf76e3cd8	9327	md2_cfg.int2_single_tap = val.single_tap;
cparata	4:77faf76e3cd8	9328	md2_cfg.int2_sleep_change = val.sleep_change;
cparata	4:77faf76e3cd8	9329
cparata	4:77faf76e3cd8	9330	emb_func_int2. int2_step_detector = val.step_detector;
cparata	4:77faf76e3cd8	9331	emb_func_int2.int2_tilt = val.tilt;
cparata	4:77faf76e3cd8	9332	emb_func_int2.int2_fsm_lc = val.fsm_lc;
cparata	4:77faf76e3cd8	9333
cparata	4:77faf76e3cd8	9334	fsm_int2_a.int2_fsm1 = val.fsm1;
cparata	4:77faf76e3cd8	9335	fsm_int2_a.int2_fsm2 = val.fsm2;
cparata	4:77faf76e3cd8	9336	fsm_int2_a.int2_fsm3 = val.fsm3;
cparata	4:77faf76e3cd8	9337	fsm_int2_a.int2_fsm4 = val.fsm4;
cparata	4:77faf76e3cd8	9338	fsm_int2_a.int2_fsm5 = val.fsm5;
cparata	4:77faf76e3cd8	9339	fsm_int2_a.int2_fsm6 = val.fsm6;
cparata	4:77faf76e3cd8	9340	fsm_int2_a.int2_fsm7 = val.fsm7;
cparata	4:77faf76e3cd8	9341	fsm_int2_a.int2_fsm8 = val.fsm8;
cparata	4:77faf76e3cd8	9342
cparata	4:77faf76e3cd8	9343	fsm_int2_b.int2_fsm9 = val.fsm9 ;
cparata	4:77faf76e3cd8	9344	fsm_int2_b.int2_fsm10 = val.fsm10;
cparata	4:77faf76e3cd8	9345	fsm_int2_b.int2_fsm11 = val.fsm11;
cparata	4:77faf76e3cd8	9346	fsm_int2_b.int2_fsm12 = val.fsm12;
cparata	4:77faf76e3cd8	9347	fsm_int2_b.int2_fsm13 = val.fsm13;
cparata	4:77faf76e3cd8	9348	fsm_int2_b.int2_fsm14 = val.fsm14;
cparata	4:77faf76e3cd8	9349	fsm_int2_b.int2_fsm15 = val.fsm15;
cparata	4:77faf76e3cd8	9350	fsm_int2_b.int2_fsm16 = val.fsm16;
cparata	4:77faf76e3cd8	9351
cparata	4:77faf76e3cd8	9352	if (ret == 0) {
cparata	4:77faf76e3cd8	9353	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	4:77faf76e3cd8	9354	if (ret == 0) {
cparata	4:77faf76e3cd8	9355	if ( ( val.drdy_temp \| val.timestamp ) != PROPERTY_DISABLE ) {
cparata	4:77faf76e3cd8	9356	ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9357	}
cparata	4:77faf76e3cd8	9358	else{
cparata	4:77faf76e3cd8	9359	ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	9360	}
cparata	4:77faf76e3cd8	9361	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	4:77faf76e3cd8	9362	}
cparata	4:77faf76e3cd8	9363	}
cparata	4:77faf76e3cd8	9364
cparata	4:77faf76e3cd8	9365	if (ret == 0) {
cparata	4:77faf76e3cd8	9366	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	9367	}
cparata	4:77faf76e3cd8	9368	if (ret == 0) {
cparata	4:77faf76e3cd8	9369	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
cparata	4:77faf76e3cd8	9370	(uint8_t*)&emb_func_int2, 1);
cparata	4:77faf76e3cd8	9371	}
cparata	4:77faf76e3cd8	9372	if (ret == 0) {
cparata	4:77faf76e3cd8	9373	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_A,
cparata	4:77faf76e3cd8	9374	(uint8_t*)&fsm_int2_a, 1);
cparata	4:77faf76e3cd8	9375	}
cparata	4:77faf76e3cd8	9376	if (ret == 0) {
cparata	4:77faf76e3cd8	9377	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_B,
cparata	4:77faf76e3cd8	9378	(uint8_t*)&fsm_int2_b, 1);
cparata	4:77faf76e3cd8	9379	}
cparata	4:77faf76e3cd8	9380	if (ret == 0) {
cparata	4:77faf76e3cd8	9381	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	9382	}
cparata	4:77faf76e3cd8	9383
cparata	4:77faf76e3cd8	9384	if (ret == 0) {
cparata	4:77faf76e3cd8	9385	if (( emb_func_int2.int2_fsm_lc
cparata	4:77faf76e3cd8	9386	\| emb_func_int2.int2_sig_mot
cparata	4:77faf76e3cd8	9387	\| emb_func_int2.int2_step_detector
cparata	4:77faf76e3cd8	9388	\| emb_func_int2.int2_tilt
cparata	4:77faf76e3cd8	9389	\| fsm_int2_a.int2_fsm1
cparata	4:77faf76e3cd8	9390	\| fsm_int2_a.int2_fsm2
cparata	4:77faf76e3cd8	9391	\| fsm_int2_a.int2_fsm3
cparata	4:77faf76e3cd8	9392	\| fsm_int2_a.int2_fsm4
cparata	4:77faf76e3cd8	9393	\| fsm_int2_a.int2_fsm5
cparata	4:77faf76e3cd8	9394	\| fsm_int2_a.int2_fsm6
cparata	4:77faf76e3cd8	9395	\| fsm_int2_a.int2_fsm7
cparata	4:77faf76e3cd8	9396	\| fsm_int2_a.int2_fsm8
cparata	4:77faf76e3cd8	9397	\| fsm_int2_b.int2_fsm9
cparata	4:77faf76e3cd8	9398	\| fsm_int2_b.int2_fsm10
cparata	4:77faf76e3cd8	9399	\| fsm_int2_b.int2_fsm11
cparata	4:77faf76e3cd8	9400	\| fsm_int2_b.int2_fsm12
cparata	4:77faf76e3cd8	9401	\| fsm_int2_b.int2_fsm13
cparata	4:77faf76e3cd8	9402	\| fsm_int2_b.int2_fsm14
cparata	4:77faf76e3cd8	9403	\| fsm_int2_b.int2_fsm15
cparata	4:77faf76e3cd8	9404	\| fsm_int2_b.int2_fsm16)!= PROPERTY_DISABLE ){
cparata	4:77faf76e3cd8	9405	md2_cfg.int2_emb_func = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	9406	}
cparata	4:77faf76e3cd8	9407	else{
cparata	4:77faf76e3cd8	9408	md2_cfg.int2_emb_func = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9409	}
cparata	4:77faf76e3cd8	9410	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL,
cparata	4:77faf76e3cd8	9411	(uint8_t*)&int2_ctrl, 1);
cparata	4:77faf76e3cd8	9412	}
cparata	4:77faf76e3cd8	9413	if (ret == 0) {
cparata	4:77faf76e3cd8	9414	ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	4:77faf76e3cd8	9415	}
cparata	4:77faf76e3cd8	9416	if (ret == 0) {
cparata	4:77faf76e3cd8	9417	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	4:77faf76e3cd8	9418	}
cparata	4:77faf76e3cd8	9419
cparata	4:77faf76e3cd8	9420	if (ret == 0) {
cparata	4:77faf76e3cd8	9421	ret = lsm6dso_pin_int1_route_get(ctx, &pin_int1_route);
cparata	4:77faf76e3cd8	9422	}
cparata	4:77faf76e3cd8	9423
cparata	4:77faf76e3cd8	9424	if (ret == 0) {
cparata	4:77faf76e3cd8	9425	if ( ( val.fifo_bdr
cparata	4:77faf76e3cd8	9426	\| val.drdy_g
cparata	4:77faf76e3cd8	9427	\| val.drdy_temp
cparata	4:77faf76e3cd8	9428	\| val.drdy_xl
cparata	4:77faf76e3cd8	9429	\| val.fifo_full
cparata	4:77faf76e3cd8	9430	\| val.fifo_ovr
cparata	4:77faf76e3cd8	9431	\| val.fifo_th
cparata	4:77faf76e3cd8	9432	\| val.six_d
cparata	4:77faf76e3cd8	9433	\| val.double_tap
cparata	4:77faf76e3cd8	9434	\| val.free_fall
cparata	4:77faf76e3cd8	9435	\| val.wake_up
cparata	4:77faf76e3cd8	9436	\| val.single_tap
cparata	4:77faf76e3cd8	9437	\| val.sleep_change
cparata	4:77faf76e3cd8	9438	\| pin_int1_route.den_flag
cparata	4:77faf76e3cd8	9439	\| pin_int1_route.boot
cparata	4:77faf76e3cd8	9440	\| pin_int1_route.fifo_bdr
cparata	4:77faf76e3cd8	9441	\| pin_int1_route.drdy_g
cparata	4:77faf76e3cd8	9442	\| pin_int1_route.drdy_xl
cparata	4:77faf76e3cd8	9443	\| pin_int1_route.fifo_full
cparata	4:77faf76e3cd8	9444	\| pin_int1_route.fifo_ovr
cparata	4:77faf76e3cd8	9445	\| pin_int1_route.fifo_th
cparata	4:77faf76e3cd8	9446	\| pin_int1_route.six_d
cparata	4:77faf76e3cd8	9447	\| pin_int1_route.double_tap
cparata	4:77faf76e3cd8	9448	\| pin_int1_route.free_fall
cparata	4:77faf76e3cd8	9449	\| pin_int1_route.wake_up
cparata	4:77faf76e3cd8	9450	\| pin_int1_route.single_tap
cparata	4:77faf76e3cd8	9451	\| pin_int1_route.sleep_change ) != PROPERTY_DISABLE) {
cparata	4:77faf76e3cd8	9452	tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	9453	}
cparata	4:77faf76e3cd8	9454	else{
cparata	4:77faf76e3cd8	9455	tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9456	}
cparata	4:77faf76e3cd8	9457	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	4:77faf76e3cd8	9458	}
cparata	4:77faf76e3cd8	9459	}
cparata	4:77faf76e3cd8	9460	return ret;
cparata	4:77faf76e3cd8	9461	}
cparata	4:77faf76e3cd8	9462
cparata	4:77faf76e3cd8	9463	/**
cparata	4:77faf76e3cd8	9464	* @brief Route interrupt signals on int2 pin.[get]
cparata	4:77faf76e3cd8	9465	*
cparata	4:77faf76e3cd8	9466	* @param ctx communication interface handler. Use NULL to ingnore
cparata	4:77faf76e3cd8	9467	* this interface.(ptr)
cparata	4:77faf76e3cd8	9468	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	4:77faf76e3cd8	9469	* to ingnore this interface.(ptr)
cparata	4:77faf76e3cd8	9470	* @param val the signals that are routed on int2 pin.(ptr)
cparata	4:77faf76e3cd8	9471	*
cparata	4:77faf76e3cd8	9472	*/
cparata	4:77faf76e3cd8	9473	int32_t lsm6dso_pin_int2_route_get(lsm6dso_ctx_t ctx, lsm6dso_ctx_t aux_ctx,
cparata	4:77faf76e3cd8	9474	lsm6dso_pin_int2_route_t *val)
cparata	4:77faf76e3cd8	9475	{
cparata	4:77faf76e3cd8	9476	lsm6dso_emb_func_int2_t emb_func_int2;
cparata	4:77faf76e3cd8	9477	lsm6dso_fsm_int2_a_t fsm_int2_a;
cparata	4:77faf76e3cd8	9478	lsm6dso_fsm_int2_b_t fsm_int2_b;
cparata	4:77faf76e3cd8	9479	lsm6dso_int2_ctrl_t int2_ctrl;
cparata	4:77faf76e3cd8	9480	lsm6dso_md2_cfg_t md2_cfg;
cparata	4:77faf76e3cd8	9481	lsm6dso_ctrl4_c_t ctrl4_c;
cparata	4:77faf76e3cd8	9482	lsm6dso_int_ois_t int_ois;
cparata	4:77faf76e3cd8	9483	int32_t ret;
cparata	4:77faf76e3cd8	9484
cparata	4:77faf76e3cd8	9485	ret = 0;
cparata	4:77faf76e3cd8	9486
cparata	4:77faf76e3cd8	9487	if( aux_ctx != NULL ) {
cparata	4:77faf76e3cd8	9488	ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS,
cparata	4:77faf76e3cd8	9489	(uint8_t*)&int_ois, 1);
cparata	4:77faf76e3cd8	9490	val->drdy_ois = int_ois.int2_drdy_ois;
cparata	4:77faf76e3cd8	9491	}
cparata	4:77faf76e3cd8	9492
cparata	4:77faf76e3cd8	9493	if( ctx != NULL ) {
cparata	4:77faf76e3cd8	9494	if (ret == 0) {
cparata	4:77faf76e3cd8	9495	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	9496	}
cparata	4:77faf76e3cd8	9497	if (ret == 0) {
cparata	4:77faf76e3cd8	9498	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
cparata	4:77faf76e3cd8	9499	(uint8_t*)&emb_func_int2, 1);
cparata	4:77faf76e3cd8	9500	}
cparata	4:77faf76e3cd8	9501	if (ret == 0) {
cparata	4:77faf76e3cd8	9502	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_A,
cparata	4:77faf76e3cd8	9503	(uint8_t*)&fsm_int2_a, 1);
cparata	4:77faf76e3cd8	9504	}
cparata	4:77faf76e3cd8	9505	if (ret == 0) {
cparata	4:77faf76e3cd8	9506	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_B,
cparata	4:77faf76e3cd8	9507	(uint8_t*)&fsm_int2_b, 1);
cparata	4:77faf76e3cd8	9508	}
cparata	4:77faf76e3cd8	9509	if (ret == 0) {
cparata	4:77faf76e3cd8	9510	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	9511	}
cparata	4:77faf76e3cd8	9512	if (ret == 0) {
cparata	4:77faf76e3cd8	9513
cparata	4:77faf76e3cd8	9514	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
cparata	4:77faf76e3cd8	9515	(uint8_t*)&int2_ctrl, 1);
cparata	3:4274d9103f1d	9516	}
cparata	3:4274d9103f1d	9517	if (ret == 0) {
cparata	4:77faf76e3cd8	9518	ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG,
cparata	4:77faf76e3cd8	9519	(uint8_t*)&md2_cfg, 1);
cparata	4:77faf76e3cd8	9520	}
cparata	4:77faf76e3cd8	9521
cparata	4:77faf76e3cd8	9522	if (ret == 0) {
cparata	4:77faf76e3cd8	9523	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1);
cparata	4:77faf76e3cd8	9524	}
cparata	4:77faf76e3cd8	9525	if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE){
cparata	4:77faf76e3cd8	9526	if (ret == 0) {
cparata	4:77faf76e3cd8	9527	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
cparata	4:77faf76e3cd8	9528	(uint8_t*)&int2_ctrl, 1);
cparata	4:77faf76e3cd8	9529	val->drdy_temp = int2_ctrl.int2_drdy_temp;
cparata	4:77faf76e3cd8	9530	}
cparata	4:77faf76e3cd8	9531	if (ret == 0) {
cparata	4:77faf76e3cd8	9532	ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1);
cparata	4:77faf76e3cd8	9533	val->timestamp = md2_cfg.int2_timestamp;
cparata	4:77faf76e3cd8	9534	}
cparata	4:77faf76e3cd8	9535	}
cparata	4:77faf76e3cd8	9536	else {
cparata	4:77faf76e3cd8	9537	val->drdy_temp = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9538	val->timestamp = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9539	}
cparata	4:77faf76e3cd8	9540
cparata	4:77faf76e3cd8	9541	val->drdy_xl = int2_ctrl.int2_drdy_xl;
cparata	4:77faf76e3cd8	9542	val->drdy_g = int2_ctrl.int2_drdy_g;
cparata	4:77faf76e3cd8	9543	val->drdy_temp = int2_ctrl.int2_drdy_temp;
cparata	4:77faf76e3cd8	9544	val->fifo_th = int2_ctrl.int2_fifo_th;
cparata	4:77faf76e3cd8	9545	val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
cparata	4:77faf76e3cd8	9546	val->fifo_full = int2_ctrl.int2_fifo_full;
cparata	4:77faf76e3cd8	9547	val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
cparata	4:77faf76e3cd8	9548
cparata	4:77faf76e3cd8	9549	val->timestamp = md2_cfg.int2_timestamp;
cparata	4:77faf76e3cd8	9550	val->six_d = md2_cfg.int2_6d;
cparata	4:77faf76e3cd8	9551	val->double_tap = md2_cfg.int2_double_tap;
cparata	4:77faf76e3cd8	9552	val->free_fall = md2_cfg.int2_ff;
cparata	4:77faf76e3cd8	9553	val->wake_up = md2_cfg.int2_wu;
cparata	4:77faf76e3cd8	9554	val->single_tap = md2_cfg.int2_single_tap;
cparata	4:77faf76e3cd8	9555	val->sleep_change = md2_cfg.int2_sleep_change;
cparata	4:77faf76e3cd8	9556
cparata	4:77faf76e3cd8	9557	val->step_detector = emb_func_int2. int2_step_detector;
cparata	4:77faf76e3cd8	9558	val->tilt = emb_func_int2.int2_tilt;
cparata	4:77faf76e3cd8	9559	val->fsm_lc = emb_func_int2.int2_fsm_lc;
cparata	4:77faf76e3cd8	9560
cparata	4:77faf76e3cd8	9561	val->fsm1 = fsm_int2_a.int2_fsm1;
cparata	4:77faf76e3cd8	9562	val->fsm2 = fsm_int2_a.int2_fsm2;
cparata	4:77faf76e3cd8	9563	val->fsm3 = fsm_int2_a.int2_fsm3;
cparata	4:77faf76e3cd8	9564	val->fsm4 = fsm_int2_a.int2_fsm4;
cparata	4:77faf76e3cd8	9565	val->fsm5 = fsm_int2_a.int2_fsm5;
cparata	4:77faf76e3cd8	9566	val->fsm6 = fsm_int2_a.int2_fsm6;
cparata	4:77faf76e3cd8	9567	val->fsm7 = fsm_int2_a.int2_fsm7;
cparata	4:77faf76e3cd8	9568	val->fsm8 = fsm_int2_a.int2_fsm8;
cparata	4:77faf76e3cd8	9569
cparata	4:77faf76e3cd8	9570	val->fsm9 = fsm_int2_b.int2_fsm9;
cparata	4:77faf76e3cd8	9571	val->fsm10 = fsm_int2_b.int2_fsm10;
cparata	4:77faf76e3cd8	9572	val->fsm11 = fsm_int2_b.int2_fsm11;
cparata	4:77faf76e3cd8	9573	val->fsm12 = fsm_int2_b.int2_fsm12;
cparata	4:77faf76e3cd8	9574	val->fsm13 = fsm_int2_b.int2_fsm13;
cparata	4:77faf76e3cd8	9575	val->fsm14 = fsm_int2_b.int2_fsm14;
cparata	4:77faf76e3cd8	9576	val->fsm15 = fsm_int2_b.int2_fsm15;
cparata	4:77faf76e3cd8	9577	val->fsm16 = fsm_int2_b.int2_fsm16;
cparata	4:77faf76e3cd8	9578
cparata	4:77faf76e3cd8	9579	}
cparata	4:77faf76e3cd8	9580
cparata	4:77faf76e3cd8	9581	return ret;
cparata	4:77faf76e3cd8	9582	}
cparata	4:77faf76e3cd8	9583
cparata	4:77faf76e3cd8	9584	/**
cparata	4:77faf76e3cd8	9585	* @brief Get the status of all the interrupt sources.[get]
cparata	4:77faf76e3cd8	9586	*
cparata	4:77faf76e3cd8	9587	* @param ctx communication interface handler.(ptr)
cparata	4:77faf76e3cd8	9588	* @param val the status of all the interrupt sources.(ptr)
cparata	4:77faf76e3cd8	9589	*
cparata	4:77faf76e3cd8	9590	*/
cparata	4:77faf76e3cd8	9591	int32_t lsm6dso_all_sources_get(lsm6dso_ctx_t *ctx,
cparata	4:77faf76e3cd8	9592	lsm6dso_all_sources_t *val)
cparata	4:77faf76e3cd8	9593	{
cparata	4:77faf76e3cd8	9594	lsm6dso_emb_func_status_mainpage_t emb_func_status_mainpage;
cparata	4:77faf76e3cd8	9595	lsm6dso_status_master_mainpage_t status_master_mainpage;
cparata	4:77faf76e3cd8	9596	lsm6dso_fsm_status_a_mainpage_t fsm_status_a_mainpage;
cparata	4:77faf76e3cd8	9597	lsm6dso_fsm_status_b_mainpage_t fsm_status_b_mainpage;
cparata	4:77faf76e3cd8	9598	lsm6dso_fifo_status1_t fifo_status1;
cparata	4:77faf76e3cd8	9599	lsm6dso_fifo_status2_t fifo_status2;
cparata	4:77faf76e3cd8	9600	lsm6dso_all_int_src_t all_int_src;
cparata	4:77faf76e3cd8	9601	lsm6dso_wake_up_src_t wake_up_src;
cparata	4:77faf76e3cd8	9602	lsm6dso_status_reg_t status_reg;
cparata	4:77faf76e3cd8	9603	lsm6dso_tap_src_t tap_src;
cparata	4:77faf76e3cd8	9604	lsm6dso_d6d_src_t d6d_src;
cparata	4:77faf76e3cd8	9605	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	4:77faf76e3cd8	9606	uint8_t reg[12];
cparata	4:77faf76e3cd8	9607	int32_t ret;
cparata	4:77faf76e3cd8	9608
cparata	4:77faf76e3cd8	9609	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
cparata	4:77faf76e3cd8	9610	if (ret == 0) {
cparata	4:77faf76e3cd8	9611	ctrl5_c.not_used_01 = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	9612	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
cparata	4:77faf76e3cd8	9613	}
cparata	4:77faf76e3cd8	9614	if (ret == 0) {
cparata	4:77faf76e3cd8	9615	ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC, reg, 12);
cparata	4:77faf76e3cd8	9616	}
cparata	4:77faf76e3cd8	9617
cparata	4:77faf76e3cd8	9618	if (ret == 0) {
cparata	4:77faf76e3cd8	9619	bytecpy(( uint8_t*)&all_int_src, &reg[0]);
cparata	4:77faf76e3cd8	9620	bytecpy(( uint8_t*)&wake_up_src, &reg[1]);
cparata	4:77faf76e3cd8	9621	bytecpy(( uint8_t*)&tap_src, &reg[2]);
cparata	4:77faf76e3cd8	9622	bytecpy(( uint8_t*)&d6d_src, &reg[3]);
cparata	4:77faf76e3cd8	9623	bytecpy(( uint8_t*)&status_reg, &reg[4]);
cparata	4:77faf76e3cd8	9624	bytecpy(( uint8_t*)&emb_func_status_mainpage, &reg[5]);
cparata	4:77faf76e3cd8	9625	bytecpy(( uint8_t*)&fsm_status_a_mainpage, &reg[6]);
cparata	4:77faf76e3cd8	9626	bytecpy(( uint8_t*)&fsm_status_b_mainpage, &reg[7]);
cparata	4:77faf76e3cd8	9627	bytecpy(( uint8_t*)&status_master_mainpage, &reg[9]);
cparata	4:77faf76e3cd8	9628	bytecpy(( uint8_t*)&fifo_status1, &reg[10]);
cparata	4:77faf76e3cd8	9629	bytecpy(( uint8_t*)&fifo_status2, &reg[11]);
cparata	4:77faf76e3cd8	9630
cparata	4:77faf76e3cd8	9631	val->timestamp = all_int_src.timestamp_endcount;
cparata	4:77faf76e3cd8	9632
cparata	4:77faf76e3cd8	9633	val->wake_up_z = wake_up_src.z_wu;
cparata	4:77faf76e3cd8	9634	val->wake_up_y = wake_up_src.y_wu;
cparata	4:77faf76e3cd8	9635	val->wake_up_x = wake_up_src.x_wu;
cparata	4:77faf76e3cd8	9636	val->wake_up = wake_up_src.wu_ia;
cparata	4:77faf76e3cd8	9637	val->sleep_state = wake_up_src.sleep_state;
cparata	4:77faf76e3cd8	9638	val->free_fall = wake_up_src.ff_ia;
cparata	4:77faf76e3cd8	9639	val->sleep_change = wake_up_src.sleep_change_ia;
cparata	4:77faf76e3cd8	9640
cparata	4:77faf76e3cd8	9641	val->tap_x = tap_src.x_tap;
cparata	4:77faf76e3cd8	9642	val->tap_y = tap_src.y_tap;
cparata	4:77faf76e3cd8	9643	val->tap_z = tap_src.z_tap;
cparata	4:77faf76e3cd8	9644	val->tap_sign = tap_src.tap_sign;
cparata	4:77faf76e3cd8	9645	val->double_tap = tap_src.double_tap;
cparata	4:77faf76e3cd8	9646	val->single_tap = tap_src.single_tap;
cparata	4:77faf76e3cd8	9647
cparata	4:77faf76e3cd8	9648	val->six_d_xl = d6d_src.xl;
cparata	4:77faf76e3cd8	9649	val->six_d_xh = d6d_src.xh;
cparata	4:77faf76e3cd8	9650	val->six_d_yl = d6d_src.yl;
cparata	4:77faf76e3cd8	9651	val->six_d_yh = d6d_src.yh;
cparata	4:77faf76e3cd8	9652	val->six_d_zl = d6d_src.zl;
cparata	4:77faf76e3cd8	9653	val->six_d_zh = d6d_src.zh;
cparata	4:77faf76e3cd8	9654	val->six_d = d6d_src.d6d_ia;
cparata	4:77faf76e3cd8	9655	val->den_flag = d6d_src.den_drdy;
cparata	4:77faf76e3cd8	9656
cparata	4:77faf76e3cd8	9657	val->drdy_xl = status_reg.xlda;
cparata	4:77faf76e3cd8	9658	val->drdy_g = status_reg.gda;
cparata	4:77faf76e3cd8	9659	val->drdy_temp = status_reg.tda;
cparata	4:77faf76e3cd8	9660
cparata	4:77faf76e3cd8	9661	val->step_detector = emb_func_status_mainpage.is_step_det;
cparata	4:77faf76e3cd8	9662	val->tilt = emb_func_status_mainpage.is_tilt;
cparata	4:77faf76e3cd8	9663	val->sig_mot = emb_func_status_mainpage.is_sigmot;
cparata	4:77faf76e3cd8	9664	val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
cparata	4:77faf76e3cd8	9665
cparata	4:77faf76e3cd8	9666	val->fsm1 = fsm_status_a_mainpage.is_fsm1;
cparata	4:77faf76e3cd8	9667	val->fsm2 = fsm_status_a_mainpage.is_fsm2;
cparata	4:77faf76e3cd8	9668	val->fsm3 = fsm_status_a_mainpage.is_fsm3;
cparata	4:77faf76e3cd8	9669	val->fsm4 = fsm_status_a_mainpage.is_fsm4;
cparata	4:77faf76e3cd8	9670	val->fsm5 = fsm_status_a_mainpage.is_fsm5;
cparata	4:77faf76e3cd8	9671	val->fsm6 = fsm_status_a_mainpage.is_fsm6;
cparata	4:77faf76e3cd8	9672	val->fsm7 = fsm_status_a_mainpage.is_fsm7;
cparata	4:77faf76e3cd8	9673	val->fsm8 = fsm_status_a_mainpage.is_fsm8;
cparata	4:77faf76e3cd8	9674
cparata	4:77faf76e3cd8	9675	val->fsm9 = fsm_status_b_mainpage.is_fsm9;
cparata	4:77faf76e3cd8	9676	val->fsm10 = fsm_status_b_mainpage.is_fsm10;
cparata	4:77faf76e3cd8	9677	val->fsm11 = fsm_status_b_mainpage.is_fsm11;
cparata	4:77faf76e3cd8	9678	val->fsm12 = fsm_status_b_mainpage.is_fsm12;
cparata	4:77faf76e3cd8	9679	val->fsm13 = fsm_status_b_mainpage.is_fsm13;
cparata	4:77faf76e3cd8	9680	val->fsm14 = fsm_status_b_mainpage.is_fsm14;
cparata	4:77faf76e3cd8	9681	val->fsm15 = fsm_status_b_mainpage.is_fsm15;
cparata	4:77faf76e3cd8	9682	val->fsm16 = fsm_status_b_mainpage.is_fsm16;
cparata	4:77faf76e3cd8	9683
cparata	4:77faf76e3cd8	9684	val->sh_endop = status_master_mainpage.sens_hub_endop;
cparata	4:77faf76e3cd8	9685	val->sh_slave0_nack = status_master_mainpage.slave0_nack;
cparata	4:77faf76e3cd8	9686	val->sh_slave1_nack = status_master_mainpage.slave1_nack;
cparata	4:77faf76e3cd8	9687	val->sh_slave2_nack = status_master_mainpage.slave2_nack;
cparata	4:77faf76e3cd8	9688	val->sh_slave3_nack = status_master_mainpage.slave3_nack;
cparata	4:77faf76e3cd8	9689	val->sh_wr_once = status_master_mainpage.wr_once_done;
cparata	4:77faf76e3cd8	9690
cparata	4:77faf76e3cd8	9691	val->fifo_diff = (256U * fifo_status2.diff_fifo) + fifo_status1.diff_fifo;
cparata	4:77faf76e3cd8	9692
cparata	4:77faf76e3cd8	9693	val->fifo_ovr_latched = fifo_status2.over_run_latched;
cparata	4:77faf76e3cd8	9694	val->fifo_bdr = fifo_status2.counter_bdr_ia;
cparata	4:77faf76e3cd8	9695	val->fifo_full = fifo_status2.fifo_full_ia;
cparata	4:77faf76e3cd8	9696	val->fifo_ovr = fifo_status2.fifo_ovr_ia;
cparata	4:77faf76e3cd8	9697	val->fifo_th = fifo_status2.fifo_wtm_ia;
cparata	4:77faf76e3cd8	9698
cparata	4:77faf76e3cd8	9699	ctrl5_c.not_used_01 = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9700	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&ctrl5_c, 1);
cparata	4:77faf76e3cd8	9701
cparata	4:77faf76e3cd8	9702	}
cparata	4:77faf76e3cd8	9703
cparata	4:77faf76e3cd8	9704	return ret;
cparata	4:77faf76e3cd8	9705	}
cparata	4:77faf76e3cd8	9706
cparata	4:77faf76e3cd8	9707	/**
cparata	4:77faf76e3cd8	9708	* @brief Sensor conversion parameters selection.[set]
cparata	4:77faf76e3cd8	9709	*
cparata	4:77faf76e3cd8	9710	* @param ctx communication interface handler. Use NULL to ingnore
cparata	4:77faf76e3cd8	9711	* this interface.(ptr)
cparata	4:77faf76e3cd8	9712	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	4:77faf76e3cd8	9713	* to ingnore this interface.(ptr)
cparata	4:77faf76e3cd8	9714	* @param val set the sensor conversion parameters by checking
cparata	4:77faf76e3cd8	9715	* the constraints of the device.(ptr)
cparata	4:77faf76e3cd8	9716	*
cparata	4:77faf76e3cd8	9717	*/
cparata	4:77faf76e3cd8	9718	int32_t lsm6dso_mode_set(lsm6dso_ctx_t ctx, lsm6dso_ctx_t aux_ctx,
cparata	4:77faf76e3cd8	9719	lsm6dso_md_t *val)
cparata	4:77faf76e3cd8	9720	{
cparata	4:77faf76e3cd8	9721	lsm6dso_func_cfg_access_t func_cfg_access;
cparata	4:77faf76e3cd8	9722	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	4:77faf76e3cd8	9723	lsm6dso_ctrl2_ois_t ctrl2_ois;
cparata	4:77faf76e3cd8	9724	lsm6dso_ctrl3_ois_t ctrl3_ois;
cparata	4:77faf76e3cd8	9725	lsm6dso_ctrl1_xl_t ctrl1_xl;
cparata	4:77faf76e3cd8	9726	lsm6dso_ctrl8_xl_t ctrl8_xl;
cparata	4:77faf76e3cd8	9727	lsm6dso_ctrl2_g_t ctrl2_g;
cparata	4:77faf76e3cd8	9728	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	9729	lsm6dso_ctrl4_c_t ctrl4_c;
cparata	4:77faf76e3cd8	9730	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	4:77faf76e3cd8	9731	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	4:77faf76e3cd8	9732	lsm6dso_ctrl7_g_t ctrl7_g;
cparata	4:77faf76e3cd8	9733	uint8_t xl_hm_mode;
cparata	4:77faf76e3cd8	9734	uint8_t g_hm_mode;
cparata	4:77faf76e3cd8	9735	uint8_t xl_ulp_en;
cparata	4:77faf76e3cd8	9736	uint8_t odr_gy;
cparata	4:77faf76e3cd8	9737	uint8_t odr_xl;
cparata	4:77faf76e3cd8	9738	uint8_t reg[8];
cparata	4:77faf76e3cd8	9739	int32_t ret;
cparata	4:77faf76e3cd8	9740
cparata	4:77faf76e3cd8	9741	ret = 0;
cparata	4:77faf76e3cd8	9742
cparata	4:77faf76e3cd8	9743	/* reading input configuration */
cparata	4:77faf76e3cd8	9744	xl_hm_mode = ( (uint8_t)val->ui.xl.odr & 0x10U ) >> 4;
cparata	4:77faf76e3cd8	9745	xl_ulp_en = ( (uint8_t)val->ui.xl.odr & 0x20U ) >> 5;
cparata	4:77faf76e3cd8	9746	odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
cparata	4:77faf76e3cd8	9747
cparata	4:77faf76e3cd8	9748	/* if enable xl ultra low power mode disable gy and OIS chain */
cparata	4:77faf76e3cd8	9749	if (xl_ulp_en == PROPERTY_ENABLE) {
cparata	4:77faf76e3cd8	9750	val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
cparata	4:77faf76e3cd8	9751	val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
cparata	4:77faf76e3cd8	9752	val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
cparata	4:77faf76e3cd8	9753	}
cparata	4:77faf76e3cd8	9754	/* if OIS xl is enabled also gyro OIS is enabled */
cparata	4:77faf76e3cd8	9755	if (val->ois.xl.odr == LSM6DSO_XL_OIS_6667Hz_HP){
cparata	4:77faf76e3cd8	9756	val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
cparata	4:77faf76e3cd8	9757	}
cparata	4:77faf76e3cd8	9758	g_hm_mode = ( (uint8_t)val->ui.gy.odr & 0x10U ) >> 4;
cparata	4:77faf76e3cd8	9759	odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
cparata	4:77faf76e3cd8	9760
cparata	4:77faf76e3cd8	9761	/* reading registers to be configured */
cparata	4:77faf76e3cd8	9762	if( ctx != NULL ) {
cparata	4:77faf76e3cd8	9763	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 8);
cparata	4:77faf76e3cd8	9764	bytecpy(( uint8_t*)&ctrl1_xl, &reg[0]);
cparata	4:77faf76e3cd8	9765	bytecpy(( uint8_t*)&ctrl2_g, &reg[1]);
cparata	4:77faf76e3cd8	9766	bytecpy(( uint8_t*)&ctrl3_c, &reg[2]);
cparata	4:77faf76e3cd8	9767	bytecpy(( uint8_t*)&ctrl4_c, &reg[3]);
cparata	4:77faf76e3cd8	9768	bytecpy(( uint8_t*)&ctrl5_c, &reg[4]);
cparata	4:77faf76e3cd8	9769	bytecpy(( uint8_t*)&ctrl6_c, &reg[5]);
cparata	4:77faf76e3cd8	9770	bytecpy(( uint8_t*)&ctrl7_g, &reg[6]);
cparata	4:77faf76e3cd8	9771	bytecpy(( uint8_t*)&ctrl8_xl, &reg[7]);
cparata	4:77faf76e3cd8	9772	if ( ret == 0 ) {
cparata	4:77faf76e3cd8	9773	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
cparata	4:77faf76e3cd8	9774	(uint8_t*)&func_cfg_access, 1);
cparata	4:77faf76e3cd8	9775	}
cparata	4:77faf76e3cd8	9776	/* if toggle xl ultra low power mode, turn off xl before reconfigure */
cparata	4:77faf76e3cd8	9777	if (ctrl5_c.xl_ulp_en != xl_ulp_en) {
cparata	4:77faf76e3cd8	9778	ctrl1_xl.odr_xl = (uint8_t) 0x00U;
cparata	4:77faf76e3cd8	9779	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL,
cparata	4:77faf76e3cd8	9780	(uint8_t*)&ctrl1_xl, 1);
cparata	4:77faf76e3cd8	9781	}
cparata	4:77faf76e3cd8	9782	}
cparata	4:77faf76e3cd8	9783
cparata	4:77faf76e3cd8	9784	/* reading OIS registers to be configured */
cparata	4:77faf76e3cd8	9785	if( aux_ctx != NULL ) {
cparata	4:77faf76e3cd8	9786	if (ret == 0) {
cparata	4:77faf76e3cd8	9787	ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
cparata	4:77faf76e3cd8	9788	}
cparata	4:77faf76e3cd8	9789	bytecpy(( uint8_t*)&ctrl1_ois, &reg[0]);
cparata	4:77faf76e3cd8	9790	bytecpy(( uint8_t*)&ctrl2_ois, &reg[1]);
cparata	4:77faf76e3cd8	9791	bytecpy(( uint8_t*)&ctrl3_ois, &reg[2]);
cparata	4:77faf76e3cd8	9792	}
cparata	4:77faf76e3cd8	9793	else {
cparata	4:77faf76e3cd8	9794	if( ctx != NULL ) {
cparata	4:77faf76e3cd8	9795	if (ret == 0) {
cparata	4:77faf76e3cd8	9796	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
cparata	4:77faf76e3cd8	9797	}
cparata	4:77faf76e3cd8	9798	bytecpy(( uint8_t*)&ctrl1_ois, &reg[0]);
cparata	4:77faf76e3cd8	9799	bytecpy(( uint8_t*)&ctrl2_ois, &reg[1]);
cparata	4:77faf76e3cd8	9800	bytecpy(( uint8_t*)&ctrl3_ois, &reg[2]);
cparata	4:77faf76e3cd8	9801	}
cparata	4:77faf76e3cd8	9802	}
cparata	4:77faf76e3cd8	9803
cparata	4:77faf76e3cd8	9804	/* Check the Finite State Machine data rate constraints */
cparata	4:77faf76e3cd8	9805	if (val->fsm.sens != LSM6DSO_FSM_DISABLE) {
cparata	4:77faf76e3cd8	9806	switch (val->fsm.odr) {
cparata	4:77faf76e3cd8	9807	case LSM6DSO_FSM_12Hz5:
cparata	4:77faf76e3cd8	9808	if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl == 0x00U) ) {
cparata	4:77faf76e3cd8	9809	odr_xl = 0x01U;
cparata	4:77faf76e3cd8	9810	}
cparata	4:77faf76e3cd8	9811	if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy == 0x00U) ) {
cparata	4:77faf76e3cd8	9812	xl_ulp_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9813	odr_gy = 0x01U;
cparata	4:77faf76e3cd8	9814	}
cparata	4:77faf76e3cd8	9815	break;
cparata	4:77faf76e3cd8	9816	case LSM6DSO_FSM_26Hz:
cparata	4:77faf76e3cd8	9817	if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x02U) ) {
cparata	4:77faf76e3cd8	9818	odr_xl = 0x02U;
cparata	4:77faf76e3cd8	9819	}
cparata	4:77faf76e3cd8	9820	if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x02U) ) {
cparata	4:77faf76e3cd8	9821	xl_ulp_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9822	odr_gy = 0x02U;
cparata	4:77faf76e3cd8	9823	}
cparata	4:77faf76e3cd8	9824	break;
cparata	4:77faf76e3cd8	9825	case LSM6DSO_FSM_52Hz:
cparata	4:77faf76e3cd8	9826	if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x03U) ) {
cparata	4:77faf76e3cd8	9827	odr_xl = 0x03U;
cparata	4:77faf76e3cd8	9828	}
cparata	4:77faf76e3cd8	9829	if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x03U) ) {
cparata	4:77faf76e3cd8	9830	xl_ulp_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9831	odr_gy = 0x03U;
cparata	4:77faf76e3cd8	9832	}
cparata	4:77faf76e3cd8	9833	break;
cparata	4:77faf76e3cd8	9834	case LSM6DSO_FSM_104Hz:
cparata	4:77faf76e3cd8	9835	if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x04U) ) {
cparata	4:77faf76e3cd8	9836	odr_xl = 0x04U;
cparata	4:77faf76e3cd8	9837	}
cparata	4:77faf76e3cd8	9838	if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x04U) ) {
cparata	4:77faf76e3cd8	9839	xl_ulp_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9840	odr_gy = 0x04U;
cparata	4:77faf76e3cd8	9841	}
cparata	4:77faf76e3cd8	9842	break;
cparata	4:77faf76e3cd8	9843	default:
cparata	4:77faf76e3cd8	9844	odr_xl = 0x00U;
cparata	4:77faf76e3cd8	9845	odr_gy = 0x00U;
cparata	4:77faf76e3cd8	9846	break;
cparata	4:77faf76e3cd8	9847	}
cparata	4:77faf76e3cd8	9848	}
cparata	4:77faf76e3cd8	9849
cparata	4:77faf76e3cd8	9850	/* Updating the accelerometer data rate configuration */
cparata	4:77faf76e3cd8	9851	switch ( ( ctrl5_c.xl_ulp_en << 5 ) \| ( ctrl6_c.xl_hm_mode << 4 ) \|
cparata	4:77faf76e3cd8	9852	ctrl1_xl.odr_xl ) {
cparata	4:77faf76e3cd8	9853	case LSM6DSO_XL_UI_OFF:
cparata	4:77faf76e3cd8	9854	val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
cparata	4:77faf76e3cd8	9855	break;
cparata	4:77faf76e3cd8	9856	case LSM6DSO_XL_UI_12Hz5_HP:
cparata	4:77faf76e3cd8	9857	val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
cparata	4:77faf76e3cd8	9858	break;
cparata	4:77faf76e3cd8	9859	case LSM6DSO_XL_UI_26Hz_HP:
cparata	4:77faf76e3cd8	9860	val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
cparata	4:77faf76e3cd8	9861	break;
cparata	4:77faf76e3cd8	9862	case LSM6DSO_XL_UI_52Hz_HP:
cparata	4:77faf76e3cd8	9863	val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
cparata	4:77faf76e3cd8	9864	break;
cparata	4:77faf76e3cd8	9865	case LSM6DSO_XL_UI_104Hz_HP:
cparata	4:77faf76e3cd8	9866	val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
cparata	4:77faf76e3cd8	9867	break;
cparata	4:77faf76e3cd8	9868	case LSM6DSO_XL_UI_208Hz_HP:
cparata	4:77faf76e3cd8	9869	val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
cparata	4:77faf76e3cd8	9870	break;
cparata	4:77faf76e3cd8	9871	case LSM6DSO_XL_UI_416Hz_HP:
cparata	4:77faf76e3cd8	9872	val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
cparata	4:77faf76e3cd8	9873	break;
cparata	4:77faf76e3cd8	9874	case LSM6DSO_XL_UI_833Hz_HP:
cparata	4:77faf76e3cd8	9875	val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
cparata	4:77faf76e3cd8	9876	break;
cparata	4:77faf76e3cd8	9877	case LSM6DSO_XL_UI_1667Hz_HP:
cparata	4:77faf76e3cd8	9878	val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
cparata	4:77faf76e3cd8	9879	break;
cparata	4:77faf76e3cd8	9880	case LSM6DSO_XL_UI_3333Hz_HP:
cparata	4:77faf76e3cd8	9881	val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
cparata	4:77faf76e3cd8	9882	break;
cparata	4:77faf76e3cd8	9883	case LSM6DSO_XL_UI_6667Hz_HP:
cparata	4:77faf76e3cd8	9884	val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
cparata	4:77faf76e3cd8	9885	break;
cparata	4:77faf76e3cd8	9886	case LSM6DSO_XL_UI_1Hz6_LP:
cparata	4:77faf76e3cd8	9887	val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
cparata	4:77faf76e3cd8	9888	break;
cparata	4:77faf76e3cd8	9889	case LSM6DSO_XL_UI_12Hz5_LP:
cparata	4:77faf76e3cd8	9890	val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
cparata	4:77faf76e3cd8	9891	break;
cparata	4:77faf76e3cd8	9892	case LSM6DSO_XL_UI_26Hz_LP:
cparata	4:77faf76e3cd8	9893	val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
cparata	4:77faf76e3cd8	9894	break;
cparata	4:77faf76e3cd8	9895	case LSM6DSO_XL_UI_52Hz_LP:
cparata	4:77faf76e3cd8	9896	val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
cparata	4:77faf76e3cd8	9897	break;
cparata	4:77faf76e3cd8	9898	case LSM6DSO_XL_UI_104Hz_NM:
cparata	4:77faf76e3cd8	9899	val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
cparata	4:77faf76e3cd8	9900	break;
cparata	4:77faf76e3cd8	9901	case LSM6DSO_XL_UI_208Hz_NM:
cparata	4:77faf76e3cd8	9902	val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
cparata	4:77faf76e3cd8	9903	break;
cparata	4:77faf76e3cd8	9904	case LSM6DSO_XL_UI_1Hz6_ULP:
cparata	4:77faf76e3cd8	9905	val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
cparata	4:77faf76e3cd8	9906	break;
cparata	4:77faf76e3cd8	9907	case LSM6DSO_XL_UI_12Hz5_ULP:
cparata	4:77faf76e3cd8	9908	val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
cparata	4:77faf76e3cd8	9909	break;
cparata	4:77faf76e3cd8	9910	case LSM6DSO_XL_UI_26Hz_ULP:
cparata	4:77faf76e3cd8	9911	val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
cparata	4:77faf76e3cd8	9912	break;
cparata	4:77faf76e3cd8	9913	case LSM6DSO_XL_UI_52Hz_ULP:
cparata	4:77faf76e3cd8	9914	val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
cparata	4:77faf76e3cd8	9915	break;
cparata	4:77faf76e3cd8	9916	case LSM6DSO_XL_UI_104Hz_ULP:
cparata	4:77faf76e3cd8	9917	val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
cparata	4:77faf76e3cd8	9918	break;
cparata	4:77faf76e3cd8	9919	case LSM6DSO_XL_UI_208Hz_ULP:
cparata	4:77faf76e3cd8	9920	val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
cparata	4:77faf76e3cd8	9921	break;
cparata	4:77faf76e3cd8	9922	default:
cparata	4:77faf76e3cd8	9923	val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
cparata	4:77faf76e3cd8	9924	break;
cparata	4:77faf76e3cd8	9925	}
cparata	4:77faf76e3cd8	9926
cparata	4:77faf76e3cd8	9927	/* Updating the accelerometer data rate configuration */
cparata	4:77faf76e3cd8	9928	switch ( (ctrl7_g.g_hm_mode << 4) \| ctrl2_g.odr_g) {
cparata	4:77faf76e3cd8	9929	case LSM6DSO_GY_UI_OFF:
cparata	4:77faf76e3cd8	9930	val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
cparata	4:77faf76e3cd8	9931	break;
cparata	4:77faf76e3cd8	9932	case LSM6DSO_GY_UI_12Hz5_LP:
cparata	4:77faf76e3cd8	9933	val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
cparata	4:77faf76e3cd8	9934	break;
cparata	4:77faf76e3cd8	9935	case LSM6DSO_GY_UI_12Hz5_HP:
cparata	4:77faf76e3cd8	9936	val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
cparata	4:77faf76e3cd8	9937	break;
cparata	4:77faf76e3cd8	9938	case LSM6DSO_GY_UI_26Hz_LP:
cparata	4:77faf76e3cd8	9939	val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
cparata	4:77faf76e3cd8	9940	break;
cparata	4:77faf76e3cd8	9941	case LSM6DSO_GY_UI_26Hz_HP:
cparata	4:77faf76e3cd8	9942	val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
cparata	4:77faf76e3cd8	9943	break;
cparata	4:77faf76e3cd8	9944	case LSM6DSO_GY_UI_52Hz_LP:
cparata	4:77faf76e3cd8	9945	val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
cparata	4:77faf76e3cd8	9946	break;
cparata	4:77faf76e3cd8	9947	case LSM6DSO_GY_UI_52Hz_HP:
cparata	4:77faf76e3cd8	9948	val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
cparata	4:77faf76e3cd8	9949	break;
cparata	4:77faf76e3cd8	9950	case LSM6DSO_GY_UI_104Hz_NM:
cparata	4:77faf76e3cd8	9951	val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
cparata	4:77faf76e3cd8	9952	break;
cparata	4:77faf76e3cd8	9953	case LSM6DSO_GY_UI_104Hz_HP:
cparata	4:77faf76e3cd8	9954	val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
cparata	4:77faf76e3cd8	9955	break;
cparata	4:77faf76e3cd8	9956	case LSM6DSO_GY_UI_208Hz_NM:
cparata	4:77faf76e3cd8	9957	val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
cparata	4:77faf76e3cd8	9958	break;
cparata	4:77faf76e3cd8	9959	case LSM6DSO_GY_UI_208Hz_HP:
cparata	4:77faf76e3cd8	9960	val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
cparata	4:77faf76e3cd8	9961	break;
cparata	4:77faf76e3cd8	9962	case LSM6DSO_GY_UI_416Hz_HP:
cparata	4:77faf76e3cd8	9963	val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
cparata	4:77faf76e3cd8	9964	break;
cparata	4:77faf76e3cd8	9965	case LSM6DSO_GY_UI_833Hz_HP:
cparata	4:77faf76e3cd8	9966	val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
cparata	4:77faf76e3cd8	9967	break;
cparata	4:77faf76e3cd8	9968	case LSM6DSO_GY_UI_1667Hz_HP:
cparata	4:77faf76e3cd8	9969	val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
cparata	4:77faf76e3cd8	9970	break;
cparata	4:77faf76e3cd8	9971	case LSM6DSO_GY_UI_3333Hz_HP:
cparata	4:77faf76e3cd8	9972	val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
cparata	4:77faf76e3cd8	9973	break;
cparata	4:77faf76e3cd8	9974	case LSM6DSO_GY_UI_6667Hz_HP:
cparata	4:77faf76e3cd8	9975	val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
cparata	4:77faf76e3cd8	9976	break;
cparata	4:77faf76e3cd8	9977	default:
cparata	4:77faf76e3cd8	9978	val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
cparata	4:77faf76e3cd8	9979	break;
cparata	4:77faf76e3cd8	9980	}
cparata	4:77faf76e3cd8	9981
cparata	4:77faf76e3cd8	9982	/* Check accelerometer full scale constraints */
cparata	4:77faf76e3cd8	9983	/* Full scale of 16g must be the same for UI and OIS */
cparata	4:77faf76e3cd8	9984	if ( (val->ui.xl.fs == LSM6DSO_XL_UI_16g) \|\|
cparata	4:77faf76e3cd8	9985	(val->ois.xl.fs == LSM6DSO_XL_OIS_16g) ){
cparata	4:77faf76e3cd8	9986	val->ui.xl.fs = LSM6DSO_XL_UI_16g;
cparata	4:77faf76e3cd8	9987	val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
cparata	4:77faf76e3cd8	9988	}
cparata	4:77faf76e3cd8	9989
cparata	4:77faf76e3cd8	9990	/* prapare new configuration */
cparata	4:77faf76e3cd8	9991
cparata	4:77faf76e3cd8	9992	/* Full scale of 16g must be the same for UI and OIS */
cparata	4:77faf76e3cd8	9993	if (val->ui.xl.fs == LSM6DSO_XL_UI_16g) {
cparata	4:77faf76e3cd8	9994	ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	9995	}
cparata	4:77faf76e3cd8	9996	else {
cparata	4:77faf76e3cd8	9997	ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE;
cparata	4:77faf76e3cd8	9998	}
cparata	4:77faf76e3cd8	9999
cparata	4:77faf76e3cd8	10000	/* OIS new configuration */
cparata	4:77faf76e3cd8	10001	ctrl7_g.ois_on_en = val->ois.ctrl_md & 0x01U;
cparata	4:77faf76e3cd8	10002
cparata	4:77faf76e3cd8	10003	switch (val->ois.ctrl_md) {
cparata	4:77faf76e3cd8	10004	case LSM6DSO_OIS_ONLY_AUX:
cparata	4:77faf76e3cd8	10005	ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
cparata	4:77faf76e3cd8	10006	ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr \| (uint8_t)val->ois.xl.odr;
cparata	4:77faf76e3cd8	10007	ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
cparata	4:77faf76e3cd8	10008	ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
cparata	4:77faf76e3cd8	10009	break;
cparata	4:77faf76e3cd8	10010	case LSM6DSO_OIS_MIXED:
cparata	4:77faf76e3cd8	10011	ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
cparata	4:77faf76e3cd8	10012	ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr \| (uint8_t)val->ois.xl.odr;
cparata	4:77faf76e3cd8	10013	ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
cparata	4:77faf76e3cd8	10014	ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
cparata	4:77faf76e3cd8	10015	break;
cparata	4:77faf76e3cd8	10016	default:
cparata	4:77faf76e3cd8	10017	ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
cparata	4:77faf76e3cd8	10018	ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr \| (uint8_t)val->ois.xl.odr;
cparata	4:77faf76e3cd8	10019	ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
cparata	4:77faf76e3cd8	10020	ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
cparata	4:77faf76e3cd8	10021	break;
cparata	4:77faf76e3cd8	10022	}
cparata	4:77faf76e3cd8	10023
cparata	4:77faf76e3cd8	10024	/* UI new configuration */
cparata	4:77faf76e3cd8	10025	ctrl1_xl.odr_xl = odr_xl;
cparata	4:77faf76e3cd8	10026	ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs;
cparata	4:77faf76e3cd8	10027	ctrl5_c.xl_ulp_en = xl_ulp_en;
cparata	4:77faf76e3cd8	10028	ctrl6_c.xl_hm_mode = xl_hm_mode;
cparata	4:77faf76e3cd8	10029	ctrl7_g.g_hm_mode = g_hm_mode;
cparata	4:77faf76e3cd8	10030	ctrl2_g.odr_g = odr_gy;
cparata	4:77faf76e3cd8	10031	ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
cparata	4:77faf76e3cd8	10032
cparata	4:77faf76e3cd8	10033	/* writing checked configuration */
cparata	4:77faf76e3cd8	10034	if( ctx != NULL ) {
cparata	4:77faf76e3cd8	10035	bytecpy(&reg[0], ( uint8_t*)&ctrl1_xl);
cparata	4:77faf76e3cd8	10036	bytecpy(&reg[1], ( uint8_t*)&ctrl2_g);
cparata	4:77faf76e3cd8	10037	bytecpy(&reg[2], ( uint8_t*)&ctrl3_c);
cparata	4:77faf76e3cd8	10038	bytecpy(&reg[3], ( uint8_t*)&ctrl4_c);
cparata	4:77faf76e3cd8	10039	bytecpy(&reg[4], ( uint8_t*)&ctrl5_c);
cparata	4:77faf76e3cd8	10040	bytecpy(&reg[5], ( uint8_t*)&ctrl6_c);
cparata	4:77faf76e3cd8	10041	bytecpy(&reg[6], ( uint8_t*)&ctrl7_g);
cparata	4:77faf76e3cd8	10042	bytecpy(&reg[7], ( uint8_t*)&ctrl8_xl);
cparata	4:77faf76e3cd8	10043	if ( ret == 0 ) {
cparata	4:77faf76e3cd8	10044	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 8);
cparata	4:77faf76e3cd8	10045	}
cparata	4:77faf76e3cd8	10046	if ( ret == 0 ) {
cparata	4:77faf76e3cd8	10047	ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
cparata	4:77faf76e3cd8	10048	(uint8_t*)&func_cfg_access, 1);
cparata	4:77faf76e3cd8	10049	}
cparata	4:77faf76e3cd8	10050	}
cparata	4:77faf76e3cd8	10051
cparata	4:77faf76e3cd8	10052	/* writing OIS checked configuration */
cparata	4:77faf76e3cd8	10053	if( aux_ctx != NULL ) {
cparata	4:77faf76e3cd8	10054	bytecpy(&reg[0], ( uint8_t*)&ctrl1_ois);
cparata	4:77faf76e3cd8	10055	bytecpy(&reg[1], ( uint8_t*)&ctrl2_ois);
cparata	4:77faf76e3cd8	10056	bytecpy(&reg[2], ( uint8_t*)&ctrl3_ois);
cparata	4:77faf76e3cd8	10057	if (ret == 0) {
cparata	4:77faf76e3cd8	10058	ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
cparata	4:77faf76e3cd8	10059	}
cparata	4:77faf76e3cd8	10060	}
cparata	4:77faf76e3cd8	10061
cparata	4:77faf76e3cd8	10062	return ret;
cparata	4:77faf76e3cd8	10063	}
cparata	4:77faf76e3cd8	10064
cparata	4:77faf76e3cd8	10065	/**
cparata	4:77faf76e3cd8	10066	* @brief Sensor conversion parameters selection.[get]
cparata	4:77faf76e3cd8	10067	*
cparata	4:77faf76e3cd8	10068	* @param ctx communication interface handler. Use NULL to ingnore
cparata	4:77faf76e3cd8	10069	* this interface.(ptr)
cparata	4:77faf76e3cd8	10070	* @param aux_ctx auxiliary communication interface handler. Use NULL
cparata	4:77faf76e3cd8	10071	* to ingnore this interface.(ptr)
cparata	4:77faf76e3cd8	10072	* @param val get the sensor conversion parameters.(ptr)
cparata	4:77faf76e3cd8	10073	*
cparata	4:77faf76e3cd8	10074	*/
cparata	4:77faf76e3cd8	10075	int32_t lsm6dso_mode_get(lsm6dso_ctx_t ctx, lsm6dso_ctx_t aux_ctx,
cparata	4:77faf76e3cd8	10076	lsm6dso_md_t *val)
cparata	4:77faf76e3cd8	10077	{
cparata	4:77faf76e3cd8	10078
cparata	4:77faf76e3cd8	10079	lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
cparata	4:77faf76e3cd8	10080	lsm6dso_func_cfg_access_t func_cfg_access;
cparata	4:77faf76e3cd8	10081	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	4:77faf76e3cd8	10082	lsm6dso_fsm_enable_a_t fsm_enable_a;
cparata	4:77faf76e3cd8	10083	lsm6dso_fsm_enable_b_t fsm_enable_b;
cparata	4:77faf76e3cd8	10084	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	4:77faf76e3cd8	10085	lsm6dso_ctrl2_ois_t ctrl2_ois;
cparata	4:77faf76e3cd8	10086	lsm6dso_ctrl3_ois_t ctrl3_ois;
cparata	4:77faf76e3cd8	10087	lsm6dso_ctrl1_xl_t ctrl1_xl;
cparata	4:77faf76e3cd8	10088	lsm6dso_ctrl2_g_t ctrl2_g;
cparata	4:77faf76e3cd8	10089	lsm6dso_ctrl3_c_t ctrl3_c;
cparata	4:77faf76e3cd8	10090	lsm6dso_ctrl4_c_t ctrl4_c;
cparata	4:77faf76e3cd8	10091	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	4:77faf76e3cd8	10092	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	4:77faf76e3cd8	10093	lsm6dso_ctrl7_g_t ctrl7_g;
cparata	4:77faf76e3cd8	10094
cparata	4:77faf76e3cd8	10095	uint8_t reg[8];
cparata	4:77faf76e3cd8	10096	int32_t ret;
cparata	4:77faf76e3cd8	10097
cparata	4:77faf76e3cd8	10098	ret = 0;
cparata	4:77faf76e3cd8	10099
cparata	4:77faf76e3cd8	10100	/* reading the registers of the device */
cparata	4:77faf76e3cd8	10101	if( ctx != NULL ) {
cparata	4:77faf76e3cd8	10102	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 7);
cparata	4:77faf76e3cd8	10103	bytecpy(( uint8_t*)&ctrl1_xl, &reg[0]);
cparata	4:77faf76e3cd8	10104	bytecpy(( uint8_t*)&ctrl2_g, &reg[1]);
cparata	4:77faf76e3cd8	10105	bytecpy(( uint8_t*)&ctrl3_c, &reg[2]);
cparata	4:77faf76e3cd8	10106	bytecpy(( uint8_t*)&ctrl4_c, &reg[3]);
cparata	4:77faf76e3cd8	10107	bytecpy(( uint8_t*)&ctrl5_c, &reg[4]);
cparata	4:77faf76e3cd8	10108	bytecpy(( uint8_t*)&ctrl6_c, &reg[5]);
cparata	4:77faf76e3cd8	10109	bytecpy(( uint8_t*)&ctrl7_g, &reg[6]);
cparata	4:77faf76e3cd8	10110	if ( ret == 0 ) {
cparata	4:77faf76e3cd8	10111	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
cparata	4:77faf76e3cd8	10112	(uint8_t*)&func_cfg_access, 1);
cparata	4:77faf76e3cd8	10113	}
cparata	4:77faf76e3cd8	10114	if (ret == 0) {
cparata	4:77faf76e3cd8	10115	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	10116	}
cparata	4:77faf76e3cd8	10117	if (ret == 0) {
cparata	4:77faf76e3cd8	10118	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, reg, 1);
cparata	4:77faf76e3cd8	10119	bytecpy(( uint8_t*)&emb_func_odr_cfg_b, &reg[0]);
cparata	4:77faf76e3cd8	10120	}
cparata	4:77faf76e3cd8	10121	if (ret == 0) {
cparata	4:77faf76e3cd8	10122	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	4:77faf76e3cd8	10123	(uint8_t*)&emb_func_en_b, 1);
cparata	4:77faf76e3cd8	10124	}
cparata	4:77faf76e3cd8	10125	if (ret == 0) {
cparata	4:77faf76e3cd8	10126	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, reg, 2);
cparata	4:77faf76e3cd8	10127	bytecpy(( uint8_t*)&fsm_enable_a, &reg[0]);
cparata	4:77faf76e3cd8	10128	bytecpy(( uint8_t*)&fsm_enable_b, &reg[1]);
cparata	4:77faf76e3cd8	10129	}
cparata	4:77faf76e3cd8	10130	if (ret == 0) {
cparata	4:77faf76e3cd8	10131	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	10132	}
cparata	4:77faf76e3cd8	10133	}
cparata	4:77faf76e3cd8	10134
cparata	4:77faf76e3cd8	10135	if( aux_ctx != NULL ) {
cparata	4:77faf76e3cd8	10136	if (ret == 0) {
cparata	4:77faf76e3cd8	10137	ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
cparata	3:4274d9103f1d	10138	}
cparata	4:77faf76e3cd8	10139	bytecpy(( uint8_t*)&ctrl1_ois, &reg[0]);
cparata	4:77faf76e3cd8	10140	bytecpy(( uint8_t*)&ctrl2_ois, &reg[1]);
cparata	4:77faf76e3cd8	10141	bytecpy(( uint8_t*)&ctrl3_ois, &reg[2]);
cparata	4:77faf76e3cd8	10142	}
cparata	4:77faf76e3cd8	10143	else {
cparata	4:77faf76e3cd8	10144	if( ctx != NULL ) {
cparata	4:77faf76e3cd8	10145	if (ret == 0) {
cparata	4:77faf76e3cd8	10146	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
cparata	4:77faf76e3cd8	10147	}
cparata	4:77faf76e3cd8	10148	bytecpy(( uint8_t*)&ctrl1_ois, &reg[0]);
cparata	4:77faf76e3cd8	10149	bytecpy(( uint8_t*)&ctrl2_ois, &reg[1]);
cparata	4:77faf76e3cd8	10150	bytecpy(( uint8_t*)&ctrl3_ois, &reg[2]);
cparata	4:77faf76e3cd8	10151	}
cparata	4:77faf76e3cd8	10152	}
cparata	4:77faf76e3cd8	10153
cparata	4:77faf76e3cd8	10154	/* fill the input structure */
cparata	4:77faf76e3cd8	10155
cparata	4:77faf76e3cd8	10156	/* get accelerometer configuration */
cparata	4:77faf76e3cd8	10157	switch ( (ctrl5_c.xl_ulp_en << 5) \| (ctrl6_c.xl_hm_mode << 4) \|
cparata	4:77faf76e3cd8	10158	ctrl1_xl.odr_xl ) {
cparata	4:77faf76e3cd8	10159	case LSM6DSO_XL_UI_OFF:
cparata	4:77faf76e3cd8	10160	val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
cparata	4:77faf76e3cd8	10161	break;
cparata	4:77faf76e3cd8	10162	case LSM6DSO_XL_UI_12Hz5_HP:
cparata	4:77faf76e3cd8	10163	val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
cparata	4:77faf76e3cd8	10164	break;
cparata	4:77faf76e3cd8	10165	case LSM6DSO_XL_UI_26Hz_HP:
cparata	4:77faf76e3cd8	10166	val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
cparata	4:77faf76e3cd8	10167	break;
cparata	4:77faf76e3cd8	10168	case LSM6DSO_XL_UI_52Hz_HP:
cparata	4:77faf76e3cd8	10169	val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
cparata	4:77faf76e3cd8	10170	break;
cparata	4:77faf76e3cd8	10171	case LSM6DSO_XL_UI_104Hz_HP:
cparata	4:77faf76e3cd8	10172	val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
cparata	4:77faf76e3cd8	10173	break;
cparata	4:77faf76e3cd8	10174	case LSM6DSO_XL_UI_208Hz_HP:
cparata	4:77faf76e3cd8	10175	val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
cparata	4:77faf76e3cd8	10176	break;
cparata	4:77faf76e3cd8	10177	case LSM6DSO_XL_UI_416Hz_HP:
cparata	4:77faf76e3cd8	10178	val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
cparata	4:77faf76e3cd8	10179	break;
cparata	4:77faf76e3cd8	10180	case LSM6DSO_XL_UI_833Hz_HP:
cparata	4:77faf76e3cd8	10181	val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
cparata	4:77faf76e3cd8	10182	break;
cparata	4:77faf76e3cd8	10183	case LSM6DSO_XL_UI_1667Hz_HP:
cparata	4:77faf76e3cd8	10184	val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
cparata	4:77faf76e3cd8	10185	break;
cparata	4:77faf76e3cd8	10186	case LSM6DSO_XL_UI_3333Hz_HP:
cparata	4:77faf76e3cd8	10187	val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
cparata	4:77faf76e3cd8	10188	break;
cparata	4:77faf76e3cd8	10189	case LSM6DSO_XL_UI_6667Hz_HP:
cparata	4:77faf76e3cd8	10190	val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
cparata	4:77faf76e3cd8	10191	break;
cparata	4:77faf76e3cd8	10192	case LSM6DSO_XL_UI_1Hz6_LP:
cparata	4:77faf76e3cd8	10193	val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
cparata	4:77faf76e3cd8	10194	break;
cparata	4:77faf76e3cd8	10195	case LSM6DSO_XL_UI_12Hz5_LP:
cparata	4:77faf76e3cd8	10196	val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
cparata	4:77faf76e3cd8	10197	break;
cparata	4:77faf76e3cd8	10198	case LSM6DSO_XL_UI_26Hz_LP:
cparata	4:77faf76e3cd8	10199	val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
cparata	4:77faf76e3cd8	10200	break;
cparata	4:77faf76e3cd8	10201	case LSM6DSO_XL_UI_52Hz_LP:
cparata	4:77faf76e3cd8	10202	val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
cparata	4:77faf76e3cd8	10203	break;
cparata	4:77faf76e3cd8	10204	case LSM6DSO_XL_UI_104Hz_NM:
cparata	4:77faf76e3cd8	10205	val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
cparata	4:77faf76e3cd8	10206	break;
cparata	4:77faf76e3cd8	10207	case LSM6DSO_XL_UI_208Hz_NM:
cparata	4:77faf76e3cd8	10208	val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
cparata	4:77faf76e3cd8	10209	break;
cparata	4:77faf76e3cd8	10210	case LSM6DSO_XL_UI_1Hz6_ULP:
cparata	4:77faf76e3cd8	10211	val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
cparata	4:77faf76e3cd8	10212	break;
cparata	4:77faf76e3cd8	10213	case LSM6DSO_XL_UI_12Hz5_ULP:
cparata	4:77faf76e3cd8	10214	val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
cparata	4:77faf76e3cd8	10215	break;
cparata	4:77faf76e3cd8	10216	case LSM6DSO_XL_UI_26Hz_ULP:
cparata	4:77faf76e3cd8	10217	val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
cparata	4:77faf76e3cd8	10218	break;
cparata	4:77faf76e3cd8	10219	case LSM6DSO_XL_UI_52Hz_ULP:
cparata	4:77faf76e3cd8	10220	val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
cparata	4:77faf76e3cd8	10221	break;
cparata	4:77faf76e3cd8	10222	case LSM6DSO_XL_UI_104Hz_ULP:
cparata	4:77faf76e3cd8	10223	val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
cparata	4:77faf76e3cd8	10224	break;
cparata	4:77faf76e3cd8	10225	case LSM6DSO_XL_UI_208Hz_ULP:
cparata	4:77faf76e3cd8	10226	val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
cparata	4:77faf76e3cd8	10227	break;
cparata	4:77faf76e3cd8	10228	default:
cparata	4:77faf76e3cd8	10229	val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
cparata	4:77faf76e3cd8	10230	break;
cparata	4:77faf76e3cd8	10231	}
cparata	4:77faf76e3cd8	10232
cparata	4:77faf76e3cd8	10233	switch ( ctrl1_xl.fs_xl ) {
cparata	4:77faf76e3cd8	10234	case LSM6DSO_XL_UI_2g:
cparata	4:77faf76e3cd8	10235	val->ui.xl.fs = LSM6DSO_XL_UI_2g;
cparata	4:77faf76e3cd8	10236	break;
cparata	4:77faf76e3cd8	10237	case LSM6DSO_XL_UI_4g:
cparata	4:77faf76e3cd8	10238	val->ui.xl.fs = LSM6DSO_XL_UI_4g;
cparata	4:77faf76e3cd8	10239	break;
cparata	4:77faf76e3cd8	10240	case LSM6DSO_XL_UI_8g:
cparata	4:77faf76e3cd8	10241	val->ui.xl.fs = LSM6DSO_XL_UI_8g;
cparata	4:77faf76e3cd8	10242	break;
cparata	4:77faf76e3cd8	10243	case LSM6DSO_XL_UI_16g:
cparata	4:77faf76e3cd8	10244	val->ui.xl.fs = LSM6DSO_XL_UI_16g;
cparata	4:77faf76e3cd8	10245	break;
cparata	4:77faf76e3cd8	10246	default:
cparata	4:77faf76e3cd8	10247	val->ui.xl.fs = LSM6DSO_XL_UI_2g;
cparata	4:77faf76e3cd8	10248	break;
cparata	4:77faf76e3cd8	10249	}
cparata	4:77faf76e3cd8	10250
cparata	4:77faf76e3cd8	10251	/* get gyroscope configuration */
cparata	4:77faf76e3cd8	10252	switch ( (ctrl7_g.g_hm_mode << 4) \| ctrl2_g.odr_g) {
cparata	4:77faf76e3cd8	10253	case LSM6DSO_GY_UI_OFF:
cparata	4:77faf76e3cd8	10254	val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
cparata	4:77faf76e3cd8	10255	break;
cparata	4:77faf76e3cd8	10256	case LSM6DSO_GY_UI_12Hz5_LP:
cparata	4:77faf76e3cd8	10257	val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
cparata	4:77faf76e3cd8	10258	break;
cparata	4:77faf76e3cd8	10259	case LSM6DSO_GY_UI_12Hz5_HP:
cparata	4:77faf76e3cd8	10260	val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
cparata	4:77faf76e3cd8	10261	break;
cparata	4:77faf76e3cd8	10262	case LSM6DSO_GY_UI_26Hz_LP:
cparata	4:77faf76e3cd8	10263	val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
cparata	4:77faf76e3cd8	10264	break;
cparata	4:77faf76e3cd8	10265	case LSM6DSO_GY_UI_26Hz_HP:
cparata	4:77faf76e3cd8	10266	val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
cparata	4:77faf76e3cd8	10267	break;
cparata	4:77faf76e3cd8	10268	case LSM6DSO_GY_UI_52Hz_LP:
cparata	4:77faf76e3cd8	10269	val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
cparata	4:77faf76e3cd8	10270	break;
cparata	4:77faf76e3cd8	10271	case LSM6DSO_GY_UI_52Hz_HP:
cparata	4:77faf76e3cd8	10272	val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
cparata	4:77faf76e3cd8	10273	break;
cparata	4:77faf76e3cd8	10274	case LSM6DSO_GY_UI_104Hz_NM:
cparata	4:77faf76e3cd8	10275	val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
cparata	4:77faf76e3cd8	10276	break;
cparata	4:77faf76e3cd8	10277	case LSM6DSO_GY_UI_104Hz_HP:
cparata	4:77faf76e3cd8	10278	val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
cparata	4:77faf76e3cd8	10279	break;
cparata	4:77faf76e3cd8	10280	case LSM6DSO_GY_UI_208Hz_NM:
cparata	4:77faf76e3cd8	10281	val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
cparata	4:77faf76e3cd8	10282	break;
cparata	4:77faf76e3cd8	10283	case LSM6DSO_GY_UI_208Hz_HP:
cparata	4:77faf76e3cd8	10284	val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
cparata	4:77faf76e3cd8	10285	break;
cparata	4:77faf76e3cd8	10286	case LSM6DSO_GY_UI_416Hz_HP:
cparata	4:77faf76e3cd8	10287	val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
cparata	4:77faf76e3cd8	10288	break;
cparata	4:77faf76e3cd8	10289	case LSM6DSO_GY_UI_833Hz_HP:
cparata	4:77faf76e3cd8	10290	val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
cparata	4:77faf76e3cd8	10291	break;
cparata	4:77faf76e3cd8	10292	case LSM6DSO_GY_UI_1667Hz_HP:
cparata	4:77faf76e3cd8	10293	val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
cparata	4:77faf76e3cd8	10294	break;
cparata	4:77faf76e3cd8	10295	case LSM6DSO_GY_UI_3333Hz_HP:
cparata	4:77faf76e3cd8	10296	val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
cparata	4:77faf76e3cd8	10297	break;
cparata	4:77faf76e3cd8	10298	case LSM6DSO_GY_UI_6667Hz_HP:
cparata	4:77faf76e3cd8	10299	val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
cparata	4:77faf76e3cd8	10300	break;
cparata	4:77faf76e3cd8	10301	default:
cparata	4:77faf76e3cd8	10302	val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
cparata	4:77faf76e3cd8	10303	break;
cparata	4:77faf76e3cd8	10304	}
cparata	4:77faf76e3cd8	10305
cparata	4:77faf76e3cd8	10306	switch (ctrl2_g.fs_g) {
cparata	4:77faf76e3cd8	10307	case LSM6DSO_GY_UI_125dps:
cparata	4:77faf76e3cd8	10308	val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
cparata	4:77faf76e3cd8	10309	break;
cparata	4:77faf76e3cd8	10310	case LSM6DSO_GY_UI_250dps:
cparata	4:77faf76e3cd8	10311	val->ui.gy.fs = LSM6DSO_GY_UI_250dps;
cparata	4:77faf76e3cd8	10312	break;
cparata	4:77faf76e3cd8	10313	case LSM6DSO_GY_UI_500dps:
cparata	4:77faf76e3cd8	10314	val->ui.gy.fs = LSM6DSO_GY_UI_500dps;
cparata	4:77faf76e3cd8	10315	break;
cparata	4:77faf76e3cd8	10316	case LSM6DSO_GY_UI_1000dps:
cparata	4:77faf76e3cd8	10317	val->ui.gy.fs = LSM6DSO_GY_UI_1000dps;
cparata	4:77faf76e3cd8	10318	break;
cparata	4:77faf76e3cd8	10319	case LSM6DSO_GY_UI_2000dps:
cparata	4:77faf76e3cd8	10320	val->ui.gy.fs = LSM6DSO_GY_UI_2000dps;
cparata	4:77faf76e3cd8	10321	break;
cparata	4:77faf76e3cd8	10322	default:
cparata	4:77faf76e3cd8	10323	val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
cparata	4:77faf76e3cd8	10324	break;
cparata	4:77faf76e3cd8	10325	}
cparata	4:77faf76e3cd8	10326
cparata	4:77faf76e3cd8	10327	/* get finite state machine configuration */
cparata	4:77faf76e3cd8	10328	if ( (fsm_enable_a.fsm1_en \| fsm_enable_a.fsm2_en \| fsm_enable_a.fsm3_en \|
cparata	4:77faf76e3cd8	10329	fsm_enable_a.fsm4_en \| fsm_enable_a.fsm5_en \| fsm_enable_a.fsm6_en \|
cparata	4:77faf76e3cd8	10330	fsm_enable_a.fsm7_en \| fsm_enable_a.fsm8_en \| fsm_enable_b.fsm9_en \|
cparata	4:77faf76e3cd8	10331	fsm_enable_b.fsm10_en \| fsm_enable_b.fsm11_en \|
cparata	4:77faf76e3cd8	10332	fsm_enable_b.fsm12_en \| fsm_enable_b.fsm13_en \|
cparata	4:77faf76e3cd8	10333	fsm_enable_b.fsm14_en \| fsm_enable_b.fsm15_en \|
cparata	4:77faf76e3cd8	10334	fsm_enable_b.fsm16_en) == PROPERTY_ENABLE ){
cparata	4:77faf76e3cd8	10335	switch (emb_func_odr_cfg_b.fsm_odr) {
cparata	4:77faf76e3cd8	10336	case LSM6DSO_FSM_12Hz5:
cparata	4:77faf76e3cd8	10337	val->fsm.odr = LSM6DSO_FSM_12Hz5;
cparata	4:77faf76e3cd8	10338	break;
cparata	4:77faf76e3cd8	10339	case LSM6DSO_FSM_26Hz:
cparata	4:77faf76e3cd8	10340	val->fsm.odr = LSM6DSO_FSM_26Hz;
cparata	4:77faf76e3cd8	10341	break;
cparata	4:77faf76e3cd8	10342	case LSM6DSO_FSM_52Hz:
cparata	4:77faf76e3cd8	10343	val->fsm.odr = LSM6DSO_FSM_52Hz;
cparata	4:77faf76e3cd8	10344	break;
cparata	4:77faf76e3cd8	10345	case LSM6DSO_FSM_104Hz:
cparata	4:77faf76e3cd8	10346	val->fsm.odr = LSM6DSO_FSM_104Hz;
cparata	4:77faf76e3cd8	10347	break;
cparata	4:77faf76e3cd8	10348	default:
cparata	4:77faf76e3cd8	10349	val->fsm.odr = LSM6DSO_FSM_12Hz5;
cparata	4:77faf76e3cd8	10350	break;
cparata	4:77faf76e3cd8	10351	}
cparata	4:77faf76e3cd8	10352
cparata	4:77faf76e3cd8	10353	val->fsm.sens = LSM6DSO_FSM_XL_GY;
cparata	4:77faf76e3cd8	10354	if (val->ui.gy.odr == LSM6DSO_GY_UI_OFF) {
cparata	4:77faf76e3cd8	10355	val->fsm.sens = LSM6DSO_FSM_XL;
cparata	4:77faf76e3cd8	10356	}
cparata	4:77faf76e3cd8	10357	if (val->ui.xl.odr == LSM6DSO_XL_UI_OFF) {
cparata	4:77faf76e3cd8	10358	val->fsm.sens = LSM6DSO_FSM_GY;
cparata	4:77faf76e3cd8	10359	}
cparata	4:77faf76e3cd8	10360	}
cparata	4:77faf76e3cd8	10361	else {
cparata	4:77faf76e3cd8	10362	val->fsm.sens = LSM6DSO_FSM_DISABLE;
cparata	4:77faf76e3cd8	10363	}
cparata	4:77faf76e3cd8	10364
cparata	4:77faf76e3cd8	10365	/* get ois configuration */
cparata	4:77faf76e3cd8	10366
cparata	4:77faf76e3cd8	10367	/* OIS configuration mode */
cparata	4:77faf76e3cd8	10368	switch ( ctrl7_g.ois_on_en ) {
cparata	4:77faf76e3cd8	10369	case LSM6DSO_OIS_ONLY_AUX:
cparata	4:77faf76e3cd8	10370	switch ( ctrl3_ois.fs_xl_ois ) {
cparata	4:77faf76e3cd8	10371	case LSM6DSO_XL_OIS_2g:
cparata	4:77faf76e3cd8	10372	val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
cparata	4:77faf76e3cd8	10373	break;
cparata	4:77faf76e3cd8	10374	case LSM6DSO_XL_OIS_4g:
cparata	4:77faf76e3cd8	10375	val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
cparata	4:77faf76e3cd8	10376	break;
cparata	4:77faf76e3cd8	10377	case LSM6DSO_XL_OIS_8g:
cparata	4:77faf76e3cd8	10378	val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
cparata	4:77faf76e3cd8	10379	break;
cparata	4:77faf76e3cd8	10380	case LSM6DSO_XL_OIS_16g:
cparata	4:77faf76e3cd8	10381	val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
cparata	4:77faf76e3cd8	10382	break;
cparata	4:77faf76e3cd8	10383	default:
cparata	4:77faf76e3cd8	10384	val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
cparata	4:77faf76e3cd8	10385	break;
cparata	4:77faf76e3cd8	10386	}
cparata	4:77faf76e3cd8	10387	switch ( ctrl1_ois.mode4_en ) {
cparata	4:77faf76e3cd8	10388	case LSM6DSO_XL_OIS_OFF:
cparata	4:77faf76e3cd8	10389	val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
cparata	4:77faf76e3cd8	10390	break;
cparata	4:77faf76e3cd8	10391	case LSM6DSO_XL_OIS_6667Hz_HP:
cparata	4:77faf76e3cd8	10392	val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
cparata	4:77faf76e3cd8	10393	break;
cparata	4:77faf76e3cd8	10394	default:
cparata	4:77faf76e3cd8	10395	val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
cparata	4:77faf76e3cd8	10396	break;
cparata	4:77faf76e3cd8	10397	}
cparata	4:77faf76e3cd8	10398	switch ( ctrl1_ois.fs_g_ois ) {
cparata	4:77faf76e3cd8	10399	case LSM6DSO_GY_OIS_250dps:
cparata	4:77faf76e3cd8	10400	val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
cparata	4:77faf76e3cd8	10401	break;
cparata	4:77faf76e3cd8	10402	case LSM6DSO_GY_OIS_500dps:
cparata	4:77faf76e3cd8	10403	val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
cparata	4:77faf76e3cd8	10404	break;
cparata	4:77faf76e3cd8	10405	case LSM6DSO_GY_OIS_1000dps:
cparata	4:77faf76e3cd8	10406	val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
cparata	4:77faf76e3cd8	10407	break;
cparata	4:77faf76e3cd8	10408	case LSM6DSO_GY_OIS_2000dps:
cparata	4:77faf76e3cd8	10409	val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
cparata	4:77faf76e3cd8	10410	break;
cparata	4:77faf76e3cd8	10411	default:
cparata	4:77faf76e3cd8	10412	val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
cparata	4:77faf76e3cd8	10413	break;
cparata	4:77faf76e3cd8	10414	}
cparata	4:77faf76e3cd8	10415	switch ( ctrl1_ois.ois_en_spi2 ) {
cparata	4:77faf76e3cd8	10416	case LSM6DSO_GY_OIS_OFF:
cparata	4:77faf76e3cd8	10417	val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
cparata	4:77faf76e3cd8	10418	break;
cparata	4:77faf76e3cd8	10419	case LSM6DSO_GY_OIS_6667Hz_HP:
cparata	4:77faf76e3cd8	10420	val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
cparata	4:77faf76e3cd8	10421	break;
cparata	4:77faf76e3cd8	10422	default:
cparata	4:77faf76e3cd8	10423	val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
cparata	4:77faf76e3cd8	10424	break;
cparata	4:77faf76e3cd8	10425	}
cparata	4:77faf76e3cd8	10426	val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
cparata	4:77faf76e3cd8	10427	break;
cparata	4:77faf76e3cd8	10428	case LSM6DSO_OIS_MIXED:
cparata	4:77faf76e3cd8	10429	switch ( ctrl3_ois.fs_xl_ois ) {
cparata	4:77faf76e3cd8	10430	case LSM6DSO_XL_OIS_2g:
cparata	4:77faf76e3cd8	10431	val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
cparata	4:77faf76e3cd8	10432	break;
cparata	4:77faf76e3cd8	10433	case LSM6DSO_XL_OIS_4g:
cparata	4:77faf76e3cd8	10434	val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
cparata	4:77faf76e3cd8	10435	break;
cparata	4:77faf76e3cd8	10436	case LSM6DSO_XL_OIS_8g:
cparata	4:77faf76e3cd8	10437	val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
cparata	4:77faf76e3cd8	10438	break;
cparata	4:77faf76e3cd8	10439	case LSM6DSO_XL_OIS_16g:
cparata	4:77faf76e3cd8	10440	val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
cparata	4:77faf76e3cd8	10441	break;
cparata	4:77faf76e3cd8	10442	default:
cparata	4:77faf76e3cd8	10443	val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
cparata	4:77faf76e3cd8	10444	break;
cparata	4:77faf76e3cd8	10445	}
cparata	4:77faf76e3cd8	10446	switch ( ctrl1_ois.mode4_en ) {
cparata	4:77faf76e3cd8	10447	case LSM6DSO_XL_OIS_OFF:
cparata	4:77faf76e3cd8	10448	val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
cparata	4:77faf76e3cd8	10449	break;
cparata	4:77faf76e3cd8	10450	case LSM6DSO_XL_OIS_6667Hz_HP:
cparata	4:77faf76e3cd8	10451	val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
cparata	4:77faf76e3cd8	10452	break;
cparata	4:77faf76e3cd8	10453	default:
cparata	4:77faf76e3cd8	10454	val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
cparata	4:77faf76e3cd8	10455	break;
cparata	4:77faf76e3cd8	10456	}
cparata	4:77faf76e3cd8	10457	switch ( ctrl1_ois.fs_g_ois ) {
cparata	4:77faf76e3cd8	10458	case LSM6DSO_GY_OIS_250dps:
cparata	4:77faf76e3cd8	10459	val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
cparata	4:77faf76e3cd8	10460	break;
cparata	4:77faf76e3cd8	10461	case LSM6DSO_GY_OIS_500dps:
cparata	4:77faf76e3cd8	10462	val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
cparata	4:77faf76e3cd8	10463	break;
cparata	4:77faf76e3cd8	10464	case LSM6DSO_GY_OIS_1000dps:
cparata	4:77faf76e3cd8	10465	val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
cparata	4:77faf76e3cd8	10466	break;
cparata	4:77faf76e3cd8	10467	case LSM6DSO_GY_OIS_2000dps:
cparata	4:77faf76e3cd8	10468	val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
cparata	4:77faf76e3cd8	10469	break;
cparata	4:77faf76e3cd8	10470	default:
cparata	4:77faf76e3cd8	10471	val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
cparata	4:77faf76e3cd8	10472	break;
cparata	4:77faf76e3cd8	10473	}
cparata	4:77faf76e3cd8	10474	switch ( ctrl1_ois.ois_en_spi2 ) {
cparata	4:77faf76e3cd8	10475	case LSM6DSO_GY_OIS_OFF:
cparata	4:77faf76e3cd8	10476	val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
cparata	4:77faf76e3cd8	10477	break;
cparata	4:77faf76e3cd8	10478	case LSM6DSO_GY_OIS_6667Hz_HP:
cparata	4:77faf76e3cd8	10479	val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
cparata	4:77faf76e3cd8	10480	break;
cparata	4:77faf76e3cd8	10481	default:
cparata	4:77faf76e3cd8	10482	val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
cparata	4:77faf76e3cd8	10483	break;
cparata	4:77faf76e3cd8	10484	}
cparata	4:77faf76e3cd8	10485	val->ois.ctrl_md = LSM6DSO_OIS_MIXED;
cparata	4:77faf76e3cd8	10486	break;
cparata	4:77faf76e3cd8	10487	default:
cparata	4:77faf76e3cd8	10488	ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
cparata	4:77faf76e3cd8	10489	ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr \| (uint8_t)val->ois.xl.odr;
cparata	4:77faf76e3cd8	10490	ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
cparata	4:77faf76e3cd8	10491	ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
cparata	4:77faf76e3cd8	10492	val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
cparata	4:77faf76e3cd8	10493	break;
cparata	4:77faf76e3cd8	10494	}
cparata	4:77faf76e3cd8	10495
cparata	4:77faf76e3cd8	10496	return ret;
cparata	4:77faf76e3cd8	10497	}
cparata	4:77faf76e3cd8	10498
cparata	4:77faf76e3cd8	10499	/**
cparata	4:77faf76e3cd8	10500	* @brief Read data in engineering unit.[get]
cparata	4:77faf76e3cd8	10501	*
cparata	4:77faf76e3cd8	10502	* @param ctx communication interface handler.(ptr)
cparata	4:77faf76e3cd8	10503	* @param md the sensor conversion parameters.(ptr)
cparata	4:77faf76e3cd8	10504	*
cparata	4:77faf76e3cd8	10505	*/
cparata	4:77faf76e3cd8	10506	int32_t lsm6dso_data_get(lsm6dso_ctx_t ctx, lsm6dso_ctx_t aux_ctx,
cparata	4:77faf76e3cd8	10507	lsm6dso_md_t md, lsm6dso_data_t data)
cparata	4:77faf76e3cd8	10508	{
cparata	4:77faf76e3cd8	10509	uint8_t buff[14];
cparata	4:77faf76e3cd8	10510	int32_t ret;
cparata	4:77faf76e3cd8	10511	uint8_t i;
cparata	4:77faf76e3cd8	10512	uint8_t j;
cparata	4:77faf76e3cd8	10513
cparata	4:77faf76e3cd8	10514	ret = 0;
cparata	4:77faf76e3cd8	10515
cparata	4:77faf76e3cd8	10516	/* read data */
cparata	4:77faf76e3cd8	10517	if( ctx != NULL ) {
cparata	4:77faf76e3cd8	10518	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 14);
cparata	4:77faf76e3cd8	10519	}
cparata	4:77faf76e3cd8	10520	j = 0;
cparata	4:77faf76e3cd8	10521
cparata	4:77faf76e3cd8	10522	/* temperature conversion */
cparata	4:77faf76e3cd8	10523	data->ui.heat.raw = (int16_t)buff[j+1U];
cparata	4:77faf76e3cd8	10524	data->ui.heat.raw = ( ((int16_t)data->ui.heat.raw * (int16_t)256) + (int16_t)buff[j] );
cparata	4:77faf76e3cd8	10525	j+=2U;
cparata	4:77faf76e3cd8	10526	data->ui.heat.deg_c = lsm6dso_from_lsb_to_celsius((int16_t)data->ui.heat.raw);
cparata	4:77faf76e3cd8	10527
cparata	4:77faf76e3cd8	10528	/* angular rate conversion */
cparata	4:77faf76e3cd8	10529	for (i = 0U; i < 3U; i++) {
cparata	4:77faf76e3cd8	10530	data->ui.gy.raw[i] = (int16_t)buff[j+1U];
cparata	4:77faf76e3cd8	10531	data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
cparata	4:77faf76e3cd8	10532	j+=2U;
cparata	4:77faf76e3cd8	10533	switch ( md->ui.gy.fs ) {
cparata	4:77faf76e3cd8	10534	case LSM6DSO_GY_UI_250dps:
cparata	4:77faf76e3cd8	10535	data->ui.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ui.gy.raw[i]);
cparata	4:77faf76e3cd8	10536	break;
cparata	4:77faf76e3cd8	10537	case LSM6DSO_GY_UI_125dps:
cparata	4:77faf76e3cd8	10538	data->ui.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ui.gy.raw[i]);
cparata	4:77faf76e3cd8	10539	break;
cparata	4:77faf76e3cd8	10540	case LSM6DSO_GY_UI_500dps:
cparata	4:77faf76e3cd8	10541	data->ui.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ui.gy.raw[i]);
cparata	4:77faf76e3cd8	10542	break;
cparata	4:77faf76e3cd8	10543	case LSM6DSO_GY_UI_1000dps:
cparata	4:77faf76e3cd8	10544	data->ui.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ui.gy.raw[i]);
cparata	4:77faf76e3cd8	10545	break;
cparata	4:77faf76e3cd8	10546	case LSM6DSO_GY_UI_2000dps:
cparata	4:77faf76e3cd8	10547	data->ui.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ui.gy.raw[i]);
cparata	4:77faf76e3cd8	10548	break;
cparata	4:77faf76e3cd8	10549	default:
cparata	4:77faf76e3cd8	10550	data->ui.gy.mdps[i] = 0.0f;
cparata	4:77faf76e3cd8	10551	break;
cparata	4:77faf76e3cd8	10552	}
cparata	4:77faf76e3cd8	10553	}
cparata	4:77faf76e3cd8	10554
cparata	4:77faf76e3cd8	10555	/* acceleration conversion */
cparata	4:77faf76e3cd8	10556	for (i = 0U; i < 3U; i++) {
cparata	4:77faf76e3cd8	10557	data->ui.xl.raw[i] = (int16_t)buff[j+1U];
cparata	4:77faf76e3cd8	10558	data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
cparata	4:77faf76e3cd8	10559	j+=2U;
cparata	4:77faf76e3cd8	10560	switch ( md->ui.xl.fs ) {
cparata	4:77faf76e3cd8	10561	case LSM6DSO_XL_UI_2g:
cparata	4:77faf76e3cd8	10562	data->ui.xl.mg[i] =lsm6dso_from_fs2_to_mg(data->ui.xl.raw[i]);
cparata	4:77faf76e3cd8	10563	break;
cparata	4:77faf76e3cd8	10564	case LSM6DSO_XL_UI_4g:
cparata	4:77faf76e3cd8	10565	data->ui.xl.mg[i] =lsm6dso_from_fs4_to_mg(data->ui.xl.raw[i]);
cparata	4:77faf76e3cd8	10566	break;
cparata	4:77faf76e3cd8	10567	case LSM6DSO_XL_UI_8g:
cparata	4:77faf76e3cd8	10568	data->ui.xl.mg[i] =lsm6dso_from_fs8_to_mg(data->ui.xl.raw[i]);
cparata	4:77faf76e3cd8	10569	break;
cparata	4:77faf76e3cd8	10570	case LSM6DSO_XL_UI_16g:
cparata	4:77faf76e3cd8	10571	data->ui.xl.mg[i] =lsm6dso_from_fs16_to_mg(data->ui.xl.raw[i]);
cparata	4:77faf76e3cd8	10572	break;
cparata	4:77faf76e3cd8	10573	default:
cparata	4:77faf76e3cd8	10574	data->ui.xl.mg[i] = 0.0f;
cparata	4:77faf76e3cd8	10575	break;
cparata	4:77faf76e3cd8	10576	}
cparata	4:77faf76e3cd8	10577
cparata	4:77faf76e3cd8	10578	}
cparata	4:77faf76e3cd8	10579
cparata	4:77faf76e3cd8	10580	/* read data from ois chain */
cparata	4:77faf76e3cd8	10581	if (aux_ctx != NULL) {
cparata	4:77faf76e3cd8	10582	if (ret == 0) {
cparata	4:77faf76e3cd8	10583	ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_OUTX_L_G, buff, 12);
cparata	4:77faf76e3cd8	10584	}
cparata	4:77faf76e3cd8	10585	}
cparata	4:77faf76e3cd8	10586	j = 0;
cparata	4:77faf76e3cd8	10587
cparata	4:77faf76e3cd8	10588	/* ois angular rate conversion */
cparata	4:77faf76e3cd8	10589	for (i = 0U; i < 3U; i++) {
cparata	4:77faf76e3cd8	10590	data->ois.gy.raw[i] = (int16_t) buff[j+1U];
cparata	4:77faf76e3cd8	10591	data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j];
cparata	4:77faf76e3cd8	10592	j+=2U;
cparata	4:77faf76e3cd8	10593	switch ( md->ois.gy.fs ) {
cparata	4:77faf76e3cd8	10594	case LSM6DSO_GY_UI_250dps:
cparata	4:77faf76e3cd8	10595	data->ois.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ois.gy.raw[i]);
cparata	4:77faf76e3cd8	10596	break;
cparata	4:77faf76e3cd8	10597	case LSM6DSO_GY_UI_125dps:
cparata	4:77faf76e3cd8	10598	data->ois.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ois.gy.raw[i]);
cparata	4:77faf76e3cd8	10599	break;
cparata	4:77faf76e3cd8	10600	case LSM6DSO_GY_UI_500dps:
cparata	4:77faf76e3cd8	10601	data->ois.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ois.gy.raw[i]);
cparata	4:77faf76e3cd8	10602	break;
cparata	4:77faf76e3cd8	10603	case LSM6DSO_GY_UI_1000dps:
cparata	4:77faf76e3cd8	10604	data->ois.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ois.gy.raw[i]);
cparata	4:77faf76e3cd8	10605	break;
cparata	4:77faf76e3cd8	10606	case LSM6DSO_GY_UI_2000dps:
cparata	4:77faf76e3cd8	10607	data->ois.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ois.gy.raw[i]);
cparata	4:77faf76e3cd8	10608	break;
cparata	4:77faf76e3cd8	10609	default:
cparata	4:77faf76e3cd8	10610	data->ois.gy.mdps[i] = 0.0f;
cparata	4:77faf76e3cd8	10611	break;
cparata	4:77faf76e3cd8	10612	}
cparata	4:77faf76e3cd8	10613	}
cparata	4:77faf76e3cd8	10614
cparata	4:77faf76e3cd8	10615	/* ois acceleration conversion */
cparata	4:77faf76e3cd8	10616	for (i = 0U; i < 3U; i++) {
cparata	4:77faf76e3cd8	10617	data->ois.xl.raw[i] = (int16_t) buff[j+1U];
cparata	4:77faf76e3cd8	10618	data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j];
cparata	4:77faf76e3cd8	10619	j+=2U;
cparata	4:77faf76e3cd8	10620	switch ( md->ois.xl.fs ) {
cparata	4:77faf76e3cd8	10621	case LSM6DSO_XL_UI_2g:
cparata	4:77faf76e3cd8	10622	data->ois.xl.mg[i] =lsm6dso_from_fs2_to_mg(data->ois.xl.raw[i]);
cparata	4:77faf76e3cd8	10623	break;
cparata	4:77faf76e3cd8	10624	case LSM6DSO_XL_UI_4g:
cparata	4:77faf76e3cd8	10625	data->ois.xl.mg[i] =lsm6dso_from_fs4_to_mg(data->ois.xl.raw[i]);
cparata	4:77faf76e3cd8	10626	break;
cparata	4:77faf76e3cd8	10627	case LSM6DSO_XL_UI_8g:
cparata	4:77faf76e3cd8	10628	data->ois.xl.mg[i] =lsm6dso_from_fs8_to_mg(data->ois.xl.raw[i]);
cparata	4:77faf76e3cd8	10629	break;
cparata	4:77faf76e3cd8	10630	case LSM6DSO_XL_UI_16g:
cparata	4:77faf76e3cd8	10631	data->ois.xl.mg[i] =lsm6dso_from_fs16_to_mg(data->ois.xl.raw[i]);
cparata	4:77faf76e3cd8	10632	break;
cparata	4:77faf76e3cd8	10633	default:
cparata	4:77faf76e3cd8	10634	data->ois.xl.mg[i] = 0.0f;
cparata	4:77faf76e3cd8	10635	break;
cparata	4:77faf76e3cd8	10636	}
cparata	4:77faf76e3cd8	10637	}
cparata	4:77faf76e3cd8	10638
cparata	4:77faf76e3cd8	10639	return ret;
cparata	4:77faf76e3cd8	10640	}
cparata	4:77faf76e3cd8	10641
cparata	4:77faf76e3cd8	10642	/**
cparata	4:77faf76e3cd8	10643	* @brief Embedded functions.[set]
cparata	4:77faf76e3cd8	10644	*
cparata	4:77faf76e3cd8	10645	* @param ctx read / write interface definitions
cparata	4:77faf76e3cd8	10646	* @param val change the values of registers
cparata	4:77faf76e3cd8	10647	* EMB_FUNC_EN_A e EMB_FUNC_EN_B.
cparata	4:77faf76e3cd8	10648	*
cparata	4:77faf76e3cd8	10649	*/
cparata	4:77faf76e3cd8	10650	int32_t lsm6dso_embedded_sens_set(lsm6dso_ctx_t *ctx,
cparata	4:77faf76e3cd8	10651	lsm6dso_emb_sens_t *val)
cparata	4:77faf76e3cd8	10652	{
cparata	4:77faf76e3cd8	10653	lsm6dso_emb_func_en_a_t emb_func_en_a;
cparata	4:77faf76e3cd8	10654	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	4:77faf76e3cd8	10655	int32_t ret;
cparata	4:77faf76e3cd8	10656
cparata	4:77faf76e3cd8	10657	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	10658	if (ret == 0) {
cparata	4:77faf76e3cd8	10659	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	4:77faf76e3cd8	10660	(uint8_t*)&emb_func_en_a, 1);
cparata	4:77faf76e3cd8	10661	}
cparata	4:77faf76e3cd8	10662	if (ret == 0) {
cparata	4:77faf76e3cd8	10663	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	4:77faf76e3cd8	10664	(uint8_t*)&emb_func_en_b, 1);
cparata	4:77faf76e3cd8	10665
cparata	4:77faf76e3cd8	10666	emb_func_en_b.fsm_en = val->fsm;
cparata	4:77faf76e3cd8	10667	emb_func_en_a.tilt_en = val->tilt;
cparata	4:77faf76e3cd8	10668	emb_func_en_a.pedo_en = val->step;
cparata	4:77faf76e3cd8	10669	emb_func_en_b.pedo_adv_en = val->step_adv;
cparata	4:77faf76e3cd8	10670	emb_func_en_a.sign_motion_en = val->sig_mot;
cparata	4:77faf76e3cd8	10671	emb_func_en_b.fifo_compr_en = val->fifo_compr;
cparata	4:77faf76e3cd8	10672
cparata	4:77faf76e3cd8	10673	}
cparata	4:77faf76e3cd8	10674	if (ret == 0) {
cparata	4:77faf76e3cd8	10675	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	4:77faf76e3cd8	10676	(uint8_t*)&emb_func_en_a, 1);
cparata	4:77faf76e3cd8	10677	}
cparata	4:77faf76e3cd8	10678	if (ret == 0) {
cparata	4:77faf76e3cd8	10679	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	4:77faf76e3cd8	10680	(uint8_t*)&emb_func_en_b, 1);
cparata	4:77faf76e3cd8	10681	}
cparata	4:77faf76e3cd8	10682	if (ret == 0) {
cparata	4:77faf76e3cd8	10683	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	10684	}
cparata	4:77faf76e3cd8	10685
cparata	4:77faf76e3cd8	10686	return ret;
cparata	4:77faf76e3cd8	10687	}
cparata	4:77faf76e3cd8	10688
cparata	4:77faf76e3cd8	10689	/**
cparata	4:77faf76e3cd8	10690	* @brief Embedded functions.[get]
cparata	4:77faf76e3cd8	10691	*
cparata	4:77faf76e3cd8	10692	* @param ctx read / write interface definitions
cparata	4:77faf76e3cd8	10693	* @param val get the values of registers
cparata	4:77faf76e3cd8	10694	* EMB_FUNC_EN_A e EMB_FUNC_EN_B.
cparata	4:77faf76e3cd8	10695	*
cparata	4:77faf76e3cd8	10696	*/
cparata	4:77faf76e3cd8	10697	int32_t lsm6dso_embedded_sens_get(lsm6dso_ctx_t *ctx,
cparata	4:77faf76e3cd8	10698	lsm6dso_emb_sens_t *emb_sens)
cparata	4:77faf76e3cd8	10699	{
cparata	4:77faf76e3cd8	10700	lsm6dso_emb_func_en_a_t emb_func_en_a;
cparata	4:77faf76e3cd8	10701	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	4:77faf76e3cd8	10702	int32_t ret;
cparata	4:77faf76e3cd8	10703
cparata	4:77faf76e3cd8	10704	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	10705	if (ret == 0) {
cparata	4:77faf76e3cd8	10706	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	4:77faf76e3cd8	10707	(uint8_t*)&emb_func_en_a, 1);
cparata	4:77faf76e3cd8	10708	}
cparata	4:77faf76e3cd8	10709	if (ret == 0) {
cparata	4:77faf76e3cd8	10710	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	4:77faf76e3cd8	10711	(uint8_t*)&emb_func_en_b, 1);
cparata	4:77faf76e3cd8	10712
cparata	4:77faf76e3cd8	10713	emb_sens->fsm = emb_func_en_b.fsm_en;
cparata	4:77faf76e3cd8	10714	emb_sens->tilt = emb_func_en_a.tilt_en;
cparata	4:77faf76e3cd8	10715	emb_sens->step = emb_func_en_a.pedo_en;
cparata	4:77faf76e3cd8	10716	emb_sens->step_adv = emb_func_en_b.pedo_adv_en;
cparata	4:77faf76e3cd8	10717	emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
cparata	4:77faf76e3cd8	10718	emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
cparata	4:77faf76e3cd8	10719
cparata	4:77faf76e3cd8	10720	}
cparata	4:77faf76e3cd8	10721	if (ret == 0) {
cparata	4:77faf76e3cd8	10722	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	10723	}
cparata	4:77faf76e3cd8	10724
cparata	4:77faf76e3cd8	10725	return ret;
cparata	4:77faf76e3cd8	10726	}
cparata	4:77faf76e3cd8	10727
cparata	4:77faf76e3cd8	10728	/**
cparata	4:77faf76e3cd8	10729	* @brief turn off all embedded functions.[get]
cparata	4:77faf76e3cd8	10730	*
cparata	4:77faf76e3cd8	10731	* @param ctx read / write interface definitions
cparata	4:77faf76e3cd8	10732	* @param val get the values of registers
cparata	4:77faf76e3cd8	10733	* EMB_FUNC_EN_A e EMB_FUNC_EN_B.
cparata	4:77faf76e3cd8	10734	*
cparata	4:77faf76e3cd8	10735	*/
cparata	4:77faf76e3cd8	10736	int32_t lsm6dso_embedded_sens_off(lsm6dso_ctx_t *ctx)
cparata	4:77faf76e3cd8	10737	{
cparata	4:77faf76e3cd8	10738	lsm6dso_emb_func_en_a_t emb_func_en_a;
cparata	4:77faf76e3cd8	10739	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	4:77faf76e3cd8	10740	int32_t ret;
cparata	4:77faf76e3cd8	10741
cparata	4:77faf76e3cd8	10742	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	4:77faf76e3cd8	10743	if (ret == 0) {
cparata	4:77faf76e3cd8	10744	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	4:77faf76e3cd8	10745	(uint8_t*)&emb_func_en_a, 1);
cparata	4:77faf76e3cd8	10746	}
cparata	4:77faf76e3cd8	10747	if (ret == 0) {
cparata	4:77faf76e3cd8	10748	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	4:77faf76e3cd8	10749	(uint8_t*)&emb_func_en_b, 1);
cparata	4:77faf76e3cd8	10750
cparata	4:77faf76e3cd8	10751	emb_func_en_b.fsm_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	10752	emb_func_en_a.tilt_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	10753	emb_func_en_a.pedo_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	10754	emb_func_en_b.pedo_adv_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	10755	emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	10756	emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
cparata	4:77faf76e3cd8	10757
cparata	4:77faf76e3cd8	10758	}
cparata	4:77faf76e3cd8	10759	if (ret == 0) {
cparata	4:77faf76e3cd8	10760	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	4:77faf76e3cd8	10761	(uint8_t*)&emb_func_en_a, 1);
cparata	4:77faf76e3cd8	10762	}
cparata	4:77faf76e3cd8	10763	if (ret == 0) {
cparata	4:77faf76e3cd8	10764	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	4:77faf76e3cd8	10765	(uint8_t*)&emb_func_en_b, 1);
cparata	4:77faf76e3cd8	10766	}
cparata	4:77faf76e3cd8	10767	if (ret == 0) {
cparata	4:77faf76e3cd8	10768	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	4:77faf76e3cd8	10769	}
cparata	4:77faf76e3cd8	10770
cparata	4:77faf76e3cd8	10771	return ret;
cparata	0:6d69e896ce38	10772	}
cparata	0:6d69e896ce38	10773
cparata	0:6d69e896ce38	10774	/**
cparata	0:6d69e896ce38	10775	* @}
cparata	0:6d69e896ce38	10776	*
cparata	0:6d69e896ce38	10777	*/
cparata	0:6d69e896ce38	10778
cparata	0:6d69e896ce38	10779	/**
cparata	0:6d69e896ce38	10780	* @}
cparata	0:6d69e896ce38	10781	*
cparata	0:6d69e896ce38	10782	*/
cparata	0:6d69e896ce38	10783
cparata	0:6d69e896ce38	10784	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	07 Mar 2019
Imports:	15
Forks:	0
Commits:	7
Dependents:	2
Dependencies:	2
Followers:	401

The code in this repository is Apache licensed.

lsm6dso_reg.c@4:77faf76e3cd8, 2020-10-29 (annotated)

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