LSM6DSO - iNEMO inertial module: 3D accelerometer and 3D gy…

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iNEMO inertial module: 3D accelerometer and 3D gyroscope.

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3

lsm6dso_reg.c@2:4d14e9edf37e, 2019-06-03 (annotated)

Committer:: cparata
Date:: Mon Jun 03 09:16:08 2019 +0000
Revision:: 2:4d14e9edf37e
Parent:: 0:6d69e896ce38
Child:: 3:4274d9103f1d

Disable by default I3C

Who changed what in which revision?

User	Revision	Line number	New contents of line
cparata	0:6d69e896ce38	1	/*
cparata	0:6d69e896ce38	2	******************************************************************************
cparata	0:6d69e896ce38	3	* @file lsm6dso_reg.c
cparata	0:6d69e896ce38	4	* @author Sensor Solutions Software Team
cparata	0:6d69e896ce38	5	* @brief LSM6DSO driver file
cparata	0:6d69e896ce38	6	******************************************************************************
cparata	0:6d69e896ce38	7	* @attention
cparata	0:6d69e896ce38	8	*
cparata	0:6d69e896ce38	9	* <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
cparata	0:6d69e896ce38	10	*
cparata	0:6d69e896ce38	11	* Redistribution and use in source and binary forms, with or without
cparata	0:6d69e896ce38	12	* modification, are permitted provided that the following conditions
cparata	0:6d69e896ce38	13	* are met:
cparata	0:6d69e896ce38	14	* 1. Redistributions of source code must retain the above copyright notice,
cparata	0:6d69e896ce38	15	* this list of conditions and the following disclaimer.
cparata	0:6d69e896ce38	16	* 2. Redistributions in binary form must reproduce the above copyright
cparata	0:6d69e896ce38	17	* notice, this list of conditions and the following disclaimer in the
cparata	0:6d69e896ce38	18	* documentation and/or other materials provided with the distribution.
cparata	0:6d69e896ce38	19	* 3. Neither the name of STMicroelectronics nor the names of its
cparata	0:6d69e896ce38	20	* contributors may be used to endorse or promote products derived from
cparata	0:6d69e896ce38	21	* this software without specific prior written permission.
cparata	0:6d69e896ce38	22	*
cparata	0:6d69e896ce38	23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
cparata	0:6d69e896ce38	24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
cparata	0:6d69e896ce38	25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
cparata	0:6d69e896ce38	26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
cparata	0:6d69e896ce38	27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
cparata	0:6d69e896ce38	28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
cparata	0:6d69e896ce38	29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
cparata	0:6d69e896ce38	30	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
cparata	0:6d69e896ce38	31	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
cparata	0:6d69e896ce38	32	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
cparata	0:6d69e896ce38	33	* POSSIBILITY OF SUCH DAMAGE.
cparata	0:6d69e896ce38	34	*
cparata	0:6d69e896ce38	35	*/
cparata	0:6d69e896ce38	36
cparata	0:6d69e896ce38	37	#include "lsm6dso_reg.h"
cparata	0:6d69e896ce38	38
cparata	0:6d69e896ce38	39	/**
cparata	0:6d69e896ce38	40	* @defgroup LSM6DSO
cparata	0:6d69e896ce38	41	* @brief This file provides a set of functions needed to drive the
cparata	0:6d69e896ce38	42	* lsm6dso enhanced inertial module.
cparata	0:6d69e896ce38	43	* @{
cparata	0:6d69e896ce38	44	*
cparata	0:6d69e896ce38	45	*/
cparata	0:6d69e896ce38	46
cparata	0:6d69e896ce38	47	/**
cparata	0:6d69e896ce38	48	* @defgroup LSM6DSO_Interfaces_Functions
cparata	0:6d69e896ce38	49	* @brief This section provide a set of functions used to read and
cparata	0:6d69e896ce38	50	* write a generic register of the device.
cparata	0:6d69e896ce38	51	* MANDATORY: return 0 -> no Error.
cparata	0:6d69e896ce38	52	* @{
cparata	0:6d69e896ce38	53	*
cparata	0:6d69e896ce38	54	*/
cparata	0:6d69e896ce38	55
cparata	0:6d69e896ce38	56	/**
cparata	0:6d69e896ce38	57	* @brief Read generic device register
cparata	0:6d69e896ce38	58	*
cparata	0:6d69e896ce38	59	* @param ctx read / write interface definitions(ptr)
cparata	0:6d69e896ce38	60	* @param reg register to read
cparata	0:6d69e896ce38	61	* @param data pointer to buffer that store the data read(ptr)
cparata	0:6d69e896ce38	62	* @param len number of consecutive register to read
cparata	0:6d69e896ce38	63	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:6d69e896ce38	64	*
cparata	0:6d69e896ce38	65	*/
cparata	0:6d69e896ce38	66	int32_t lsm6dso_read_reg(lsm6dso_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:6d69e896ce38	67	uint16_t len)
cparata	0:6d69e896ce38	68	{
cparata	0:6d69e896ce38	69	int32_t ret;
cparata	0:6d69e896ce38	70	ret = ctx->read_reg(ctx->handle, reg, data, len);
cparata	0:6d69e896ce38	71	return ret;
cparata	0:6d69e896ce38	72	}
cparata	0:6d69e896ce38	73
cparata	0:6d69e896ce38	74	/**
cparata	0:6d69e896ce38	75	* @brief Write generic device register
cparata	0:6d69e896ce38	76	*
cparata	0:6d69e896ce38	77	* @param ctx read / write interface definitions(ptr)
cparata	0:6d69e896ce38	78	* @param reg register to write
cparata	0:6d69e896ce38	79	* @param data pointer to data to write in register reg(ptr)
cparata	0:6d69e896ce38	80	* @param len number of consecutive register to write
cparata	0:6d69e896ce38	81	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:6d69e896ce38	82	*
cparata	0:6d69e896ce38	83	*/
cparata	0:6d69e896ce38	84	int32_t lsm6dso_write_reg(lsm6dso_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:6d69e896ce38	85	uint16_t len)
cparata	0:6d69e896ce38	86	{
cparata	0:6d69e896ce38	87	int32_t ret;
cparata	0:6d69e896ce38	88	ret = ctx->write_reg(ctx->handle, reg, data, len);
cparata	0:6d69e896ce38	89	return ret;
cparata	0:6d69e896ce38	90	}
cparata	0:6d69e896ce38	91
cparata	0:6d69e896ce38	92	/**
cparata	0:6d69e896ce38	93	* @}
cparata	0:6d69e896ce38	94	*
cparata	0:6d69e896ce38	95	*/
cparata	0:6d69e896ce38	96
cparata	0:6d69e896ce38	97	/**
cparata	0:6d69e896ce38	98	* @defgroup LSM6DSO_Sensitivity
cparata	0:6d69e896ce38	99	* @brief These functions convert raw-data into engineering units.
cparata	0:6d69e896ce38	100	* @{
cparata	0:6d69e896ce38	101	*
cparata	0:6d69e896ce38	102	*/
cparata	2:4d14e9edf37e	103	float_t lsm6dso_from_fs2_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	104	{
cparata	2:4d14e9edf37e	105	return ((float_t)lsb) * 0.061f;
cparata	2:4d14e9edf37e	106	}
cparata	2:4d14e9edf37e	107
cparata	2:4d14e9edf37e	108	float_t lsm6dso_from_fs4_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	109	{
cparata	2:4d14e9edf37e	110	return ((float_t)lsb) * 0.122f;
cparata	2:4d14e9edf37e	111	}
cparata	2:4d14e9edf37e	112
cparata	2:4d14e9edf37e	113	float_t lsm6dso_from_fs8_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	114	{
cparata	2:4d14e9edf37e	115	return ((float_t)lsb) * 0.244f;
cparata	2:4d14e9edf37e	116	}
cparata	2:4d14e9edf37e	117
cparata	2:4d14e9edf37e	118	float_t lsm6dso_from_fs16_to_mg(int16_t lsb)
cparata	2:4d14e9edf37e	119	{
cparata	2:4d14e9edf37e	120	return ((float_t)lsb) *0.488f;
cparata	2:4d14e9edf37e	121	}
cparata	2:4d14e9edf37e	122
cparata	2:4d14e9edf37e	123	float_t lsm6dso_from_fs125_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	124	{
cparata	2:4d14e9edf37e	125	return ((float_t)lsb) *4.375f;
cparata	2:4d14e9edf37e	126	}
cparata	2:4d14e9edf37e	127
cparata	2:4d14e9edf37e	128	float_t lsm6dso_from_fs500_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	129	{
cparata	2:4d14e9edf37e	130	return ((float_t)lsb) *17.50f;
cparata	2:4d14e9edf37e	131	}
cparata	2:4d14e9edf37e	132
cparata	2:4d14e9edf37e	133	float_t lsm6dso_from_fs250_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	134	{
cparata	2:4d14e9edf37e	135	return ((float_t)lsb) *8.750f;
cparata	2:4d14e9edf37e	136	}
cparata	2:4d14e9edf37e	137
cparata	2:4d14e9edf37e	138	float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	139	{
cparata	2:4d14e9edf37e	140	return ((float_t)lsb) *35.0f;
cparata	2:4d14e9edf37e	141	}
cparata	2:4d14e9edf37e	142
cparata	2:4d14e9edf37e	143	float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb)
cparata	2:4d14e9edf37e	144	{
cparata	2:4d14e9edf37e	145	return ((float_t)lsb) *70.0f;
cparata	2:4d14e9edf37e	146	}
cparata	2:4d14e9edf37e	147
cparata	2:4d14e9edf37e	148	float_t lsm6dso_from_lsb_to_celsius(int16_t lsb)
cparata	2:4d14e9edf37e	149	{
cparata	2:4d14e9edf37e	150	return (((float_t)lsb / 256.0f) + 25.0f);
cparata	2:4d14e9edf37e	151	}
cparata	2:4d14e9edf37e	152
cparata	2:4d14e9edf37e	153	float_t lsm6dso_from_lsb_to_nsec(int16_t lsb)
cparata	2:4d14e9edf37e	154	{
cparata	2:4d14e9edf37e	155	return ((float_t)lsb * 25000.0f);
cparata	0:6d69e896ce38	156	}
cparata	0:6d69e896ce38	157
cparata	0:6d69e896ce38	158	/**
cparata	0:6d69e896ce38	159	* @}
cparata	0:6d69e896ce38	160	*
cparata	0:6d69e896ce38	161	*/
cparata	0:6d69e896ce38	162
cparata	0:6d69e896ce38	163	/**
cparata	0:6d69e896ce38	164	* @defgroup LSM6DSO_Data_Generation
cparata	0:6d69e896ce38	165	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	166	* data generation.
cparata	0:6d69e896ce38	167	*
cparata	0:6d69e896ce38	168	*/
cparata	0:6d69e896ce38	169
cparata	0:6d69e896ce38	170	/**
cparata	0:6d69e896ce38	171	* @brief Accelerometer full-scale selection.[set]
cparata	0:6d69e896ce38	172	*
cparata	0:6d69e896ce38	173	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	174	* @param val change the values of fs_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	175	*
cparata	0:6d69e896ce38	176	*/
cparata	0:6d69e896ce38	177	int32_t lsm6dso_xl_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	178	lsm6dso_fs_xl_t val)
cparata	0:6d69e896ce38	179	{
cparata	0:6d69e896ce38	180	lsm6dso_ctrl1_xl_t reg;
cparata	0:6d69e896ce38	181	int32_t ret;
cparata	0:6d69e896ce38	182
cparata	0:6d69e896ce38	183	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	184	if (ret == 0) {
cparata	0:6d69e896ce38	185	reg.fs_xl = (uint8_t) val;
cparata	0:6d69e896ce38	186	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	187	}
cparata	0:6d69e896ce38	188	return ret;
cparata	0:6d69e896ce38	189	}
cparata	0:6d69e896ce38	190
cparata	0:6d69e896ce38	191	/**
cparata	0:6d69e896ce38	192	* @brief Accelerometer full-scale selection.[get]
cparata	0:6d69e896ce38	193	*
cparata	0:6d69e896ce38	194	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	195	* @param val Get the values of fs_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	196	*
cparata	0:6d69e896ce38	197	*/
cparata	0:6d69e896ce38	198	int32_t lsm6dso_xl_full_scale_get(lsm6dso_ctx_t ctx, lsm6dso_fs_xl_t val)
cparata	0:6d69e896ce38	199	{
cparata	0:6d69e896ce38	200	lsm6dso_ctrl1_xl_t reg;
cparata	0:6d69e896ce38	201	int32_t ret;
cparata	0:6d69e896ce38	202
cparata	0:6d69e896ce38	203	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	204	switch (reg.fs_xl) {
cparata	0:6d69e896ce38	205	case LSM6DSO_2g:
cparata	0:6d69e896ce38	206	*val = LSM6DSO_2g;
cparata	0:6d69e896ce38	207	break;
cparata	0:6d69e896ce38	208	case LSM6DSO_16g:
cparata	0:6d69e896ce38	209	*val = LSM6DSO_16g;
cparata	0:6d69e896ce38	210	break;
cparata	0:6d69e896ce38	211	case LSM6DSO_4g:
cparata	0:6d69e896ce38	212	*val = LSM6DSO_4g;
cparata	0:6d69e896ce38	213	break;
cparata	0:6d69e896ce38	214	case LSM6DSO_8g:
cparata	0:6d69e896ce38	215	*val = LSM6DSO_8g;
cparata	0:6d69e896ce38	216	break;
cparata	0:6d69e896ce38	217	default:
cparata	0:6d69e896ce38	218	*val = LSM6DSO_2g;
cparata	0:6d69e896ce38	219	break;
cparata	0:6d69e896ce38	220	}
cparata	0:6d69e896ce38	221
cparata	0:6d69e896ce38	222	return ret;
cparata	0:6d69e896ce38	223	}
cparata	0:6d69e896ce38	224
cparata	0:6d69e896ce38	225	/**
cparata	0:6d69e896ce38	226	* @brief Accelerometer UI data rate selection.[set]
cparata	0:6d69e896ce38	227	*
cparata	0:6d69e896ce38	228	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	229	* @param val change the values of odr_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	230	*
cparata	0:6d69e896ce38	231	*/
cparata	0:6d69e896ce38	232	int32_t lsm6dso_xl_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t val)
cparata	0:6d69e896ce38	233	{
cparata	0:6d69e896ce38	234	lsm6dso_ctrl1_xl_t reg;
cparata	0:6d69e896ce38	235	int32_t ret;
cparata	0:6d69e896ce38	236
cparata	0:6d69e896ce38	237	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	238	if (ret == 0) {
cparata	0:6d69e896ce38	239	reg.odr_xl = (uint8_t) val;
cparata	0:6d69e896ce38	240	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	241	}
cparata	0:6d69e896ce38	242	return ret;
cparata	0:6d69e896ce38	243	}
cparata	0:6d69e896ce38	244
cparata	0:6d69e896ce38	245	/**
cparata	0:6d69e896ce38	246	* @brief Accelerometer UI data rate selection.[get]
cparata	0:6d69e896ce38	247	*
cparata	0:6d69e896ce38	248	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	249	* @param val Get the values of odr_xl in reg CTRL1_XL
cparata	0:6d69e896ce38	250	*
cparata	0:6d69e896ce38	251	*/
cparata	0:6d69e896ce38	252	int32_t lsm6dso_xl_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_odr_xl_t val)
cparata	0:6d69e896ce38	253	{
cparata	0:6d69e896ce38	254	lsm6dso_ctrl1_xl_t reg;
cparata	0:6d69e896ce38	255	int32_t ret;
cparata	0:6d69e896ce38	256
cparata	0:6d69e896ce38	257	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	258
cparata	0:6d69e896ce38	259	switch (reg.odr_xl) {
cparata	0:6d69e896ce38	260	case LSM6DSO_XL_ODR_OFF:
cparata	0:6d69e896ce38	261	*val = LSM6DSO_XL_ODR_OFF;
cparata	0:6d69e896ce38	262	break;
cparata	0:6d69e896ce38	263	case LSM6DSO_XL_ODR_12Hz5:
cparata	0:6d69e896ce38	264	*val = LSM6DSO_XL_ODR_12Hz5;
cparata	0:6d69e896ce38	265	break;
cparata	0:6d69e896ce38	266	case LSM6DSO_XL_ODR_26Hz:
cparata	0:6d69e896ce38	267	*val = LSM6DSO_XL_ODR_26Hz;
cparata	0:6d69e896ce38	268	break;
cparata	0:6d69e896ce38	269	case LSM6DSO_XL_ODR_52Hz:
cparata	0:6d69e896ce38	270	*val = LSM6DSO_XL_ODR_52Hz;
cparata	0:6d69e896ce38	271	break;
cparata	0:6d69e896ce38	272	case LSM6DSO_XL_ODR_104Hz:
cparata	0:6d69e896ce38	273	*val = LSM6DSO_XL_ODR_104Hz;
cparata	0:6d69e896ce38	274	break;
cparata	0:6d69e896ce38	275	case LSM6DSO_XL_ODR_208Hz:
cparata	0:6d69e896ce38	276	*val = LSM6DSO_XL_ODR_208Hz;
cparata	0:6d69e896ce38	277	break;
cparata	0:6d69e896ce38	278	case LSM6DSO_XL_ODR_417Hz:
cparata	0:6d69e896ce38	279	*val = LSM6DSO_XL_ODR_417Hz;
cparata	0:6d69e896ce38	280	break;
cparata	0:6d69e896ce38	281	case LSM6DSO_XL_ODR_833Hz:
cparata	0:6d69e896ce38	282	*val = LSM6DSO_XL_ODR_833Hz;
cparata	0:6d69e896ce38	283	break;
cparata	0:6d69e896ce38	284	case LSM6DSO_XL_ODR_1667Hz:
cparata	0:6d69e896ce38	285	*val = LSM6DSO_XL_ODR_1667Hz;
cparata	0:6d69e896ce38	286	break;
cparata	0:6d69e896ce38	287	case LSM6DSO_XL_ODR_3333Hz:
cparata	0:6d69e896ce38	288	*val = LSM6DSO_XL_ODR_3333Hz;
cparata	0:6d69e896ce38	289	break;
cparata	0:6d69e896ce38	290	case LSM6DSO_XL_ODR_6667Hz:
cparata	0:6d69e896ce38	291	*val = LSM6DSO_XL_ODR_6667Hz;
cparata	0:6d69e896ce38	292	break;
cparata	0:6d69e896ce38	293	case LSM6DSO_XL_ODR_6Hz5:
cparata	0:6d69e896ce38	294	*val = LSM6DSO_XL_ODR_6Hz5;
cparata	0:6d69e896ce38	295	break;
cparata	0:6d69e896ce38	296	default:
cparata	0:6d69e896ce38	297	*val = LSM6DSO_XL_ODR_OFF;
cparata	0:6d69e896ce38	298	break;
cparata	0:6d69e896ce38	299	}
cparata	0:6d69e896ce38	300	return ret;
cparata	0:6d69e896ce38	301	}
cparata	0:6d69e896ce38	302
cparata	0:6d69e896ce38	303	/**
cparata	0:6d69e896ce38	304	* @brief Gyroscope UI chain full-scale selection.[set]
cparata	0:6d69e896ce38	305	*
cparata	0:6d69e896ce38	306	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	307	* @param val change the values of fs_g in reg CTRL2_G
cparata	0:6d69e896ce38	308	*
cparata	0:6d69e896ce38	309	*/
cparata	0:6d69e896ce38	310	int32_t lsm6dso_gy_full_scale_set(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t val)
cparata	0:6d69e896ce38	311	{
cparata	0:6d69e896ce38	312	lsm6dso_ctrl2_g_t reg;
cparata	0:6d69e896ce38	313	int32_t ret;
cparata	0:6d69e896ce38	314
cparata	0:6d69e896ce38	315	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	316	if (ret == 0) {
cparata	0:6d69e896ce38	317	reg.fs_g = (uint8_t) val;
cparata	0:6d69e896ce38	318	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	319	}
cparata	0:6d69e896ce38	320
cparata	0:6d69e896ce38	321	return ret;
cparata	0:6d69e896ce38	322	}
cparata	0:6d69e896ce38	323
cparata	0:6d69e896ce38	324	/**
cparata	0:6d69e896ce38	325	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:6d69e896ce38	326	*
cparata	0:6d69e896ce38	327	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	328	* @param val Get the values of fs_g in reg CTRL2_G
cparata	0:6d69e896ce38	329	*
cparata	0:6d69e896ce38	330	*/
cparata	0:6d69e896ce38	331	int32_t lsm6dso_gy_full_scale_get(lsm6dso_ctx_t ctx, lsm6dso_fs_g_t val)
cparata	0:6d69e896ce38	332	{
cparata	0:6d69e896ce38	333	lsm6dso_ctrl2_g_t reg;
cparata	0:6d69e896ce38	334	int32_t ret;
cparata	0:6d69e896ce38	335
cparata	0:6d69e896ce38	336	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	337	switch (reg.fs_g) {
cparata	0:6d69e896ce38	338	case LSM6DSO_250dps:
cparata	0:6d69e896ce38	339	*val = LSM6DSO_250dps;
cparata	0:6d69e896ce38	340	break;
cparata	0:6d69e896ce38	341	case LSM6DSO_125dps:
cparata	0:6d69e896ce38	342	*val = LSM6DSO_125dps;
cparata	0:6d69e896ce38	343	break;
cparata	0:6d69e896ce38	344	case LSM6DSO_500dps:
cparata	0:6d69e896ce38	345	*val = LSM6DSO_500dps;
cparata	0:6d69e896ce38	346	break;
cparata	0:6d69e896ce38	347	case LSM6DSO_1000dps:
cparata	0:6d69e896ce38	348	*val = LSM6DSO_1000dps;
cparata	0:6d69e896ce38	349	break;
cparata	0:6d69e896ce38	350	case LSM6DSO_2000dps:
cparata	0:6d69e896ce38	351	*val = LSM6DSO_2000dps;
cparata	0:6d69e896ce38	352	break;
cparata	0:6d69e896ce38	353	default:
cparata	0:6d69e896ce38	354	*val = LSM6DSO_250dps;
cparata	0:6d69e896ce38	355	break;
cparata	0:6d69e896ce38	356	}
cparata	0:6d69e896ce38	357
cparata	0:6d69e896ce38	358	return ret;
cparata	0:6d69e896ce38	359	}
cparata	0:6d69e896ce38	360
cparata	0:6d69e896ce38	361	/**
cparata	0:6d69e896ce38	362	* @brief Gyroscope UI data rate selection.[set]
cparata	0:6d69e896ce38	363	*
cparata	0:6d69e896ce38	364	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	365	* @param val change the values of odr_g in reg CTRL2_G
cparata	0:6d69e896ce38	366	*
cparata	0:6d69e896ce38	367	*/
cparata	0:6d69e896ce38	368	int32_t lsm6dso_gy_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t val)
cparata	0:6d69e896ce38	369	{
cparata	0:6d69e896ce38	370	lsm6dso_ctrl2_g_t reg;
cparata	0:6d69e896ce38	371	int32_t ret;
cparata	0:6d69e896ce38	372
cparata	0:6d69e896ce38	373	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	374	if (ret == 0) {
cparata	0:6d69e896ce38	375	reg.odr_g = (uint8_t) val;
cparata	0:6d69e896ce38	376	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	377	}
cparata	0:6d69e896ce38	378
cparata	0:6d69e896ce38	379	return ret;
cparata	0:6d69e896ce38	380	}
cparata	0:6d69e896ce38	381
cparata	0:6d69e896ce38	382	/**
cparata	0:6d69e896ce38	383	* @brief Gyroscope UI data rate selection.[get]
cparata	0:6d69e896ce38	384	*
cparata	0:6d69e896ce38	385	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	386	* @param val Get the values of odr_g in reg CTRL2_G
cparata	0:6d69e896ce38	387	*
cparata	0:6d69e896ce38	388	*/
cparata	0:6d69e896ce38	389	int32_t lsm6dso_gy_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_odr_g_t val)
cparata	0:6d69e896ce38	390	{
cparata	0:6d69e896ce38	391	lsm6dso_ctrl2_g_t reg;
cparata	0:6d69e896ce38	392	int32_t ret;
cparata	0:6d69e896ce38	393
cparata	0:6d69e896ce38	394	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	395	switch (reg.odr_g) {
cparata	0:6d69e896ce38	396	case LSM6DSO_GY_ODR_OFF:
cparata	0:6d69e896ce38	397	*val = LSM6DSO_GY_ODR_OFF;
cparata	0:6d69e896ce38	398	break;
cparata	0:6d69e896ce38	399	case LSM6DSO_GY_ODR_12Hz5:
cparata	0:6d69e896ce38	400	*val = LSM6DSO_GY_ODR_12Hz5;
cparata	0:6d69e896ce38	401	break;
cparata	0:6d69e896ce38	402	case LSM6DSO_GY_ODR_26Hz:
cparata	0:6d69e896ce38	403	*val = LSM6DSO_GY_ODR_26Hz;
cparata	0:6d69e896ce38	404	break;
cparata	0:6d69e896ce38	405	case LSM6DSO_GY_ODR_52Hz:
cparata	0:6d69e896ce38	406	*val = LSM6DSO_GY_ODR_52Hz;
cparata	0:6d69e896ce38	407	break;
cparata	0:6d69e896ce38	408	case LSM6DSO_GY_ODR_104Hz:
cparata	0:6d69e896ce38	409	*val = LSM6DSO_GY_ODR_104Hz;
cparata	0:6d69e896ce38	410	break;
cparata	0:6d69e896ce38	411	case LSM6DSO_GY_ODR_208Hz:
cparata	0:6d69e896ce38	412	*val = LSM6DSO_GY_ODR_208Hz;
cparata	0:6d69e896ce38	413	break;
cparata	0:6d69e896ce38	414	case LSM6DSO_GY_ODR_417Hz:
cparata	0:6d69e896ce38	415	*val = LSM6DSO_GY_ODR_417Hz;
cparata	0:6d69e896ce38	416	break;
cparata	0:6d69e896ce38	417	case LSM6DSO_GY_ODR_833Hz:
cparata	0:6d69e896ce38	418	*val = LSM6DSO_GY_ODR_833Hz;
cparata	0:6d69e896ce38	419	break;
cparata	0:6d69e896ce38	420	case LSM6DSO_GY_ODR_1667Hz:
cparata	0:6d69e896ce38	421	*val = LSM6DSO_GY_ODR_1667Hz;
cparata	0:6d69e896ce38	422	break;
cparata	0:6d69e896ce38	423	case LSM6DSO_GY_ODR_3333Hz:
cparata	0:6d69e896ce38	424	*val = LSM6DSO_GY_ODR_3333Hz;
cparata	0:6d69e896ce38	425	break;
cparata	0:6d69e896ce38	426	case LSM6DSO_GY_ODR_6667Hz:
cparata	0:6d69e896ce38	427	*val = LSM6DSO_GY_ODR_6667Hz;
cparata	0:6d69e896ce38	428	break;
cparata	0:6d69e896ce38	429	default:
cparata	0:6d69e896ce38	430	*val = LSM6DSO_GY_ODR_OFF;
cparata	0:6d69e896ce38	431	break;
cparata	0:6d69e896ce38	432	}
cparata	0:6d69e896ce38	433	return ret;
cparata	0:6d69e896ce38	434	}
cparata	0:6d69e896ce38	435
cparata	0:6d69e896ce38	436	/**
cparata	0:6d69e896ce38	437	* @brief Block data update.[set]
cparata	0:6d69e896ce38	438	*
cparata	0:6d69e896ce38	439	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	440	* @param val change the values of bdu in reg CTRL3_C
cparata	0:6d69e896ce38	441	*
cparata	0:6d69e896ce38	442	*/
cparata	0:6d69e896ce38	443	int32_t lsm6dso_block_data_update_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	444	{
cparata	0:6d69e896ce38	445	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	446	int32_t ret;
cparata	0:6d69e896ce38	447
cparata	0:6d69e896ce38	448	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	449	if (ret == 0) {
cparata	0:6d69e896ce38	450	reg.bdu = val;
cparata	0:6d69e896ce38	451	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	452	}
cparata	0:6d69e896ce38	453	return ret;
cparata	0:6d69e896ce38	454	}
cparata	0:6d69e896ce38	455
cparata	0:6d69e896ce38	456	/**
cparata	0:6d69e896ce38	457	* @brief Block data update.[get]
cparata	0:6d69e896ce38	458	*
cparata	0:6d69e896ce38	459	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	460	* @param val change the values of bdu in reg CTRL3_C
cparata	0:6d69e896ce38	461	*
cparata	0:6d69e896ce38	462	*/
cparata	0:6d69e896ce38	463	int32_t lsm6dso_block_data_update_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	464	{
cparata	0:6d69e896ce38	465	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	466	int32_t ret;
cparata	0:6d69e896ce38	467
cparata	0:6d69e896ce38	468	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	469	*val = reg.bdu;
cparata	0:6d69e896ce38	470
cparata	0:6d69e896ce38	471	return ret;
cparata	0:6d69e896ce38	472	}
cparata	0:6d69e896ce38	473
cparata	0:6d69e896ce38	474	/**
cparata	0:6d69e896ce38	475	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:6d69e896ce38	476	* Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
cparata	0:6d69e896ce38	477	*
cparata	0:6d69e896ce38	478	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	479	* @param val change the values of usr_off_w in reg CTRL6_C
cparata	0:6d69e896ce38	480	*
cparata	0:6d69e896ce38	481	*/
cparata	0:6d69e896ce38	482	int32_t lsm6dso_xl_offset_weight_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	483	lsm6dso_usr_off_w_t val)
cparata	0:6d69e896ce38	484	{
cparata	0:6d69e896ce38	485	lsm6dso_ctrl6_c_t reg;
cparata	0:6d69e896ce38	486	int32_t ret;
cparata	0:6d69e896ce38	487
cparata	0:6d69e896ce38	488	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	489	if (ret == 0) {
cparata	0:6d69e896ce38	490	reg.usr_off_w = (uint8_t)val;
cparata	0:6d69e896ce38	491	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	492	}
cparata	0:6d69e896ce38	493	return ret;
cparata	0:6d69e896ce38	494	}
cparata	0:6d69e896ce38	495
cparata	0:6d69e896ce38	496	/**
cparata	0:6d69e896ce38	497	* @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
cparata	0:6d69e896ce38	498	* Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
cparata	0:6d69e896ce38	499	*
cparata	0:6d69e896ce38	500	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	501	* @param val Get the values of usr_off_w in reg CTRL6_C
cparata	0:6d69e896ce38	502	*
cparata	0:6d69e896ce38	503	*/
cparata	0:6d69e896ce38	504	int32_t lsm6dso_xl_offset_weight_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	505	lsm6dso_usr_off_w_t *val)
cparata	0:6d69e896ce38	506	{
cparata	0:6d69e896ce38	507	lsm6dso_ctrl6_c_t reg;
cparata	0:6d69e896ce38	508	int32_t ret;
cparata	0:6d69e896ce38	509
cparata	0:6d69e896ce38	510	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	511
cparata	0:6d69e896ce38	512	switch (reg.usr_off_w) {
cparata	0:6d69e896ce38	513	case LSM6DSO_LSb_1mg:
cparata	0:6d69e896ce38	514	*val = LSM6DSO_LSb_1mg;
cparata	0:6d69e896ce38	515	break;
cparata	0:6d69e896ce38	516	case LSM6DSO_LSb_16mg:
cparata	0:6d69e896ce38	517	*val = LSM6DSO_LSb_16mg;
cparata	0:6d69e896ce38	518	break;
cparata	0:6d69e896ce38	519	default:
cparata	0:6d69e896ce38	520	*val = LSM6DSO_LSb_1mg;
cparata	0:6d69e896ce38	521	break;
cparata	0:6d69e896ce38	522	}
cparata	0:6d69e896ce38	523	return ret;
cparata	0:6d69e896ce38	524	}
cparata	0:6d69e896ce38	525
cparata	0:6d69e896ce38	526	/**
cparata	0:6d69e896ce38	527	* @brief Accelerometer power mode.[set]
cparata	0:6d69e896ce38	528	*
cparata	0:6d69e896ce38	529	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	530	* @param val change the values of xl_hm_mode in
cparata	0:6d69e896ce38	531	* reg CTRL6_C
cparata	0:6d69e896ce38	532	*
cparata	0:6d69e896ce38	533	*/
cparata	0:6d69e896ce38	534	int32_t lsm6dso_xl_power_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	535	lsm6dso_xl_hm_mode_t val)
cparata	0:6d69e896ce38	536	{
cparata	0:6d69e896ce38	537	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	0:6d69e896ce38	538	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	0:6d69e896ce38	539	int32_t ret;
cparata	0:6d69e896ce38	540
cparata	0:6d69e896ce38	541	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	0:6d69e896ce38	542	if (ret == 0) {
cparata	0:6d69e896ce38	543	ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
cparata	0:6d69e896ce38	544	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	0:6d69e896ce38	545	}
cparata	0:6d69e896ce38	546	if (ret == 0) {
cparata	0:6d69e896ce38	547	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	0:6d69e896ce38	548	}
cparata	0:6d69e896ce38	549	if (ret == 0) {
cparata	0:6d69e896ce38	550	ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
cparata	0:6d69e896ce38	551	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	0:6d69e896ce38	552	}
cparata	0:6d69e896ce38	553	return ret;
cparata	0:6d69e896ce38	554	}
cparata	0:6d69e896ce38	555
cparata	0:6d69e896ce38	556	/**
cparata	0:6d69e896ce38	557	* @brief Accelerometer power mode.[get]
cparata	0:6d69e896ce38	558	*
cparata	0:6d69e896ce38	559	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	560	* @param val Get the values of xl_hm_mode in reg CTRL6_C
cparata	0:6d69e896ce38	561	*
cparata	0:6d69e896ce38	562	*/
cparata	0:6d69e896ce38	563	int32_t lsm6dso_xl_power_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	564	lsm6dso_xl_hm_mode_t *val)
cparata	0:6d69e896ce38	565	{
cparata	0:6d69e896ce38	566	lsm6dso_ctrl5_c_t ctrl5_c;
cparata	0:6d69e896ce38	567	lsm6dso_ctrl6_c_t ctrl6_c;
cparata	0:6d69e896ce38	568	int32_t ret;
cparata	0:6d69e896ce38	569
cparata	0:6d69e896ce38	570	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1);
cparata	0:6d69e896ce38	571	if (ret == 0) {
cparata	0:6d69e896ce38	572	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1);
cparata	0:6d69e896ce38	573	switch ( (ctrl5_c.xl_ulp_en << 1) \| ctrl6_c.xl_hm_mode) {
cparata	0:6d69e896ce38	574	case LSM6DSO_HIGH_PERFORMANCE_MD:
cparata	0:6d69e896ce38	575	*val = LSM6DSO_HIGH_PERFORMANCE_MD;
cparata	0:6d69e896ce38	576	break;
cparata	0:6d69e896ce38	577	case LSM6DSO_LOW_NORMAL_POWER_MD:
cparata	0:6d69e896ce38	578	*val = LSM6DSO_LOW_NORMAL_POWER_MD;
cparata	0:6d69e896ce38	579	break;
cparata	0:6d69e896ce38	580	case LSM6DSO_ULTRA_LOW_POWER_MD:
cparata	0:6d69e896ce38	581	*val = LSM6DSO_ULTRA_LOW_POWER_MD;
cparata	0:6d69e896ce38	582	break;
cparata	0:6d69e896ce38	583	default:
cparata	0:6d69e896ce38	584	*val = LSM6DSO_HIGH_PERFORMANCE_MD;
cparata	0:6d69e896ce38	585	break;
cparata	0:6d69e896ce38	586	}
cparata	0:6d69e896ce38	587	}
cparata	0:6d69e896ce38	588	return ret;
cparata	0:6d69e896ce38	589	}
cparata	0:6d69e896ce38	590
cparata	0:6d69e896ce38	591	/**
cparata	0:6d69e896ce38	592	* @brief Operating mode for gyroscope.[set]
cparata	0:6d69e896ce38	593	*
cparata	0:6d69e896ce38	594	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	595	* @param val change the values of g_hm_mode in reg CTRL7_G
cparata	0:6d69e896ce38	596	*
cparata	0:6d69e896ce38	597	*/
cparata	0:6d69e896ce38	598	int32_t lsm6dso_gy_power_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	599	lsm6dso_g_hm_mode_t val)
cparata	0:6d69e896ce38	600	{
cparata	0:6d69e896ce38	601	lsm6dso_ctrl7_g_t reg;
cparata	0:6d69e896ce38	602	int32_t ret;
cparata	0:6d69e896ce38	603
cparata	0:6d69e896ce38	604	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	605	if (ret == 0) {
cparata	0:6d69e896ce38	606	reg.g_hm_mode = (uint8_t)val;
cparata	0:6d69e896ce38	607	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	608	}
cparata	0:6d69e896ce38	609	return ret;
cparata	0:6d69e896ce38	610	}
cparata	0:6d69e896ce38	611
cparata	0:6d69e896ce38	612	/**
cparata	0:6d69e896ce38	613	* @brief Operating mode for gyroscope.[get]
cparata	0:6d69e896ce38	614	*
cparata	0:6d69e896ce38	615	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	616	* @param val Get the values of g_hm_mode in reg CTRL7_G
cparata	0:6d69e896ce38	617	*
cparata	0:6d69e896ce38	618	*/
cparata	0:6d69e896ce38	619	int32_t lsm6dso_gy_power_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	620	lsm6dso_g_hm_mode_t *val)
cparata	0:6d69e896ce38	621	{
cparata	0:6d69e896ce38	622	lsm6dso_ctrl7_g_t reg;
cparata	0:6d69e896ce38	623	int32_t ret;
cparata	0:6d69e896ce38	624
cparata	0:6d69e896ce38	625	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	626	switch (reg.g_hm_mode) {
cparata	0:6d69e896ce38	627	case LSM6DSO_GY_HIGH_PERFORMANCE:
cparata	0:6d69e896ce38	628	*val = LSM6DSO_GY_HIGH_PERFORMANCE;
cparata	0:6d69e896ce38	629	break;
cparata	0:6d69e896ce38	630	case LSM6DSO_GY_NORMAL:
cparata	0:6d69e896ce38	631	*val = LSM6DSO_GY_NORMAL;
cparata	0:6d69e896ce38	632	break;
cparata	0:6d69e896ce38	633	default:
cparata	0:6d69e896ce38	634	*val = LSM6DSO_GY_HIGH_PERFORMANCE;
cparata	0:6d69e896ce38	635	break;
cparata	0:6d69e896ce38	636	}
cparata	0:6d69e896ce38	637	return ret;
cparata	0:6d69e896ce38	638	}
cparata	0:6d69e896ce38	639
cparata	0:6d69e896ce38	640	/**
cparata	0:6d69e896ce38	641	* @brief Read all the interrupt flag of the device.[get]
cparata	0:6d69e896ce38	642	*
cparata	0:6d69e896ce38	643	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	644	* @param val registers ALL_INT_SRC; WAKE_UP_SRC;
cparata	0:6d69e896ce38	645	* TAP_SRC; D6D_SRC; STATUS_REG;
cparata	0:6d69e896ce38	646	* EMB_FUNC_STATUS; FSM_STATUS_A/B
cparata	0:6d69e896ce38	647	*
cparata	0:6d69e896ce38	648	*/
cparata	0:6d69e896ce38	649	int32_t lsm6dso_all_sources_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	650	lsm6dso_all_sources_t *val)
cparata	0:6d69e896ce38	651	{
cparata	0:6d69e896ce38	652	int32_t ret;
cparata	0:6d69e896ce38	653
cparata	0:6d69e896ce38	654	ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC,
cparata	0:6d69e896ce38	655	(uint8_t*)&val->all_int_src, 1);
cparata	0:6d69e896ce38	656	if (ret == 0) {
cparata	0:6d69e896ce38	657	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_SRC,
cparata	0:6d69e896ce38	658	(uint8_t*)&val->wake_up_src, 1);
cparata	0:6d69e896ce38	659	}
cparata	0:6d69e896ce38	660	if (ret == 0) {
cparata	0:6d69e896ce38	661	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_SRC,
cparata	0:6d69e896ce38	662	(uint8_t*)&val->tap_src, 1);
cparata	0:6d69e896ce38	663	}
cparata	0:6d69e896ce38	664	if (ret == 0) {
cparata	0:6d69e896ce38	665	ret = lsm6dso_read_reg(ctx, LSM6DSO_D6D_SRC,
cparata	0:6d69e896ce38	666	(uint8_t*)&val->d6d_src, 1);
cparata	0:6d69e896ce38	667	}
cparata	0:6d69e896ce38	668	if (ret == 0) {
cparata	0:6d69e896ce38	669	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG,
cparata	0:6d69e896ce38	670	(uint8_t*)&val->status_reg, 1);
cparata	0:6d69e896ce38	671	}
cparata	0:6d69e896ce38	672	if (ret == 0) {
cparata	0:6d69e896ce38	673
cparata	0:6d69e896ce38	674	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	675	}
cparata	0:6d69e896ce38	676	if (ret == 0) {
cparata	0:6d69e896ce38	677	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS,
cparata	0:6d69e896ce38	678	(uint8_t*)&val->emb_func_status, 1);
cparata	0:6d69e896ce38	679	}
cparata	0:6d69e896ce38	680	if (ret == 0) {
cparata	0:6d69e896ce38	681	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_STATUS_A,
cparata	0:6d69e896ce38	682	(uint8_t*)&val->fsm_status_a, 1);
cparata	0:6d69e896ce38	683	}
cparata	0:6d69e896ce38	684	if (ret == 0) {
cparata	0:6d69e896ce38	685	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_STATUS_B,
cparata	0:6d69e896ce38	686	(uint8_t*)&val->fsm_status_b, 1);
cparata	0:6d69e896ce38	687	}
cparata	0:6d69e896ce38	688	if (ret == 0) {
cparata	0:6d69e896ce38	689	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	690	}
cparata	0:6d69e896ce38	691	return ret;
cparata	0:6d69e896ce38	692	}
cparata	0:6d69e896ce38	693
cparata	0:6d69e896ce38	694	/**
cparata	0:6d69e896ce38	695	* @brief The STATUS_REG register is read by the primary interface.[get]
cparata	0:6d69e896ce38	696	*
cparata	0:6d69e896ce38	697	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	698	* @param val register STATUS_REG
cparata	0:6d69e896ce38	699	*
cparata	0:6d69e896ce38	700	*/
cparata	0:6d69e896ce38	701	int32_t lsm6dso_status_reg_get(lsm6dso_ctx_t ctx, lsm6dso_status_reg_t val)
cparata	0:6d69e896ce38	702	{
cparata	0:6d69e896ce38	703	int32_t ret;
cparata	0:6d69e896ce38	704	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*) val, 1);
cparata	0:6d69e896ce38	705	return ret;
cparata	0:6d69e896ce38	706	}
cparata	0:6d69e896ce38	707
cparata	0:6d69e896ce38	708	/**
cparata	0:6d69e896ce38	709	* @brief Accelerometer new data available.[get]
cparata	0:6d69e896ce38	710	*
cparata	0:6d69e896ce38	711	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	712	* @param val change the values of xlda in reg STATUS_REG
cparata	0:6d69e896ce38	713	*
cparata	0:6d69e896ce38	714	*/
cparata	0:6d69e896ce38	715	int32_t lsm6dso_xl_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	716	{
cparata	0:6d69e896ce38	717	lsm6dso_status_reg_t reg;
cparata	0:6d69e896ce38	718	int32_t ret;
cparata	0:6d69e896ce38	719
cparata	0:6d69e896ce38	720	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	721	*val = reg.xlda;
cparata	0:6d69e896ce38	722
cparata	0:6d69e896ce38	723	return ret;
cparata	0:6d69e896ce38	724	}
cparata	0:6d69e896ce38	725
cparata	0:6d69e896ce38	726	/**
cparata	0:6d69e896ce38	727	* @brief Gyroscope new data available.[get]
cparata	0:6d69e896ce38	728	*
cparata	0:6d69e896ce38	729	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	730	* @param val change the values of gda in reg STATUS_REG
cparata	0:6d69e896ce38	731	*
cparata	0:6d69e896ce38	732	*/
cparata	0:6d69e896ce38	733	int32_t lsm6dso_gy_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	734	{
cparata	0:6d69e896ce38	735	lsm6dso_status_reg_t reg;
cparata	0:6d69e896ce38	736	int32_t ret;
cparata	0:6d69e896ce38	737
cparata	0:6d69e896ce38	738	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	739	*val = reg.gda;
cparata	0:6d69e896ce38	740
cparata	0:6d69e896ce38	741	return ret;
cparata	0:6d69e896ce38	742	}
cparata	0:6d69e896ce38	743
cparata	0:6d69e896ce38	744	/**
cparata	0:6d69e896ce38	745	* @brief Temperature new data available.[get]
cparata	0:6d69e896ce38	746	*
cparata	0:6d69e896ce38	747	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	748	* @param val change the values of tda in reg STATUS_REG
cparata	0:6d69e896ce38	749	*
cparata	0:6d69e896ce38	750	*/
cparata	0:6d69e896ce38	751	int32_t lsm6dso_temp_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	752	{
cparata	0:6d69e896ce38	753	lsm6dso_status_reg_t reg;
cparata	0:6d69e896ce38	754	int32_t ret;
cparata	0:6d69e896ce38	755
cparata	0:6d69e896ce38	756	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	757	*val = reg.tda;
cparata	0:6d69e896ce38	758
cparata	0:6d69e896ce38	759	return ret;
cparata	0:6d69e896ce38	760	}
cparata	0:6d69e896ce38	761
cparata	0:6d69e896ce38	762	/**
cparata	0:6d69e896ce38	763	* @brief Accelerometer X-axis user offset correction expressed in
cparata	0:6d69e896ce38	764	* two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	765	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	766	*
cparata	0:6d69e896ce38	767	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	768	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	769	*
cparata	0:6d69e896ce38	770	*/
cparata	0:6d69e896ce38	771	int32_t lsm6dso_xl_usr_offset_x_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	772	{
cparata	0:6d69e896ce38	773	int32_t ret;
cparata	0:6d69e896ce38	774	ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
cparata	0:6d69e896ce38	775	return ret;
cparata	0:6d69e896ce38	776	}
cparata	0:6d69e896ce38	777
cparata	0:6d69e896ce38	778	/**
cparata	0:6d69e896ce38	779	* @brief Accelerometer X-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	780	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	781	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	782	*
cparata	0:6d69e896ce38	783	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	784	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	785	*
cparata	0:6d69e896ce38	786	*/
cparata	0:6d69e896ce38	787	int32_t lsm6dso_xl_usr_offset_x_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	788	{
cparata	0:6d69e896ce38	789	int32_t ret;
cparata	0:6d69e896ce38	790	ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
cparata	0:6d69e896ce38	791	return ret;
cparata	0:6d69e896ce38	792	}
cparata	0:6d69e896ce38	793
cparata	0:6d69e896ce38	794	/**
cparata	0:6d69e896ce38	795	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	796	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	797	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	798	*
cparata	0:6d69e896ce38	799	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	800	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	801	*
cparata	0:6d69e896ce38	802	*/
cparata	0:6d69e896ce38	803	int32_t lsm6dso_xl_usr_offset_y_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	804	{
cparata	0:6d69e896ce38	805	int32_t ret;
cparata	0:6d69e896ce38	806	ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
cparata	0:6d69e896ce38	807	return ret;
cparata	0:6d69e896ce38	808	}
cparata	0:6d69e896ce38	809
cparata	0:6d69e896ce38	810	/**
cparata	0:6d69e896ce38	811	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	812	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	813	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	814	*
cparata	0:6d69e896ce38	815	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	816	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	817	*
cparata	0:6d69e896ce38	818	*/
cparata	0:6d69e896ce38	819	int32_t lsm6dso_xl_usr_offset_y_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	820	{
cparata	0:6d69e896ce38	821	int32_t ret;
cparata	0:6d69e896ce38	822	ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
cparata	0:6d69e896ce38	823	return ret;
cparata	0:6d69e896ce38	824	}
cparata	0:6d69e896ce38	825
cparata	0:6d69e896ce38	826	/**
cparata	0:6d69e896ce38	827	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	828	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	829	* The value must be in the range [-127 127].[set]
cparata	0:6d69e896ce38	830	*
cparata	0:6d69e896ce38	831	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	832	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	833	*
cparata	0:6d69e896ce38	834	*/
cparata	0:6d69e896ce38	835	int32_t lsm6dso_xl_usr_offset_z_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	836	{
cparata	0:6d69e896ce38	837	int32_t ret;
cparata	0:6d69e896ce38	838	ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
cparata	0:6d69e896ce38	839	return ret;
cparata	0:6d69e896ce38	840	}
cparata	0:6d69e896ce38	841
cparata	0:6d69e896ce38	842	/**
cparata	0:6d69e896ce38	843	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:6d69e896ce38	844	* complement, weight depends on USR_OFF_W in CTRL6_C (15h).
cparata	0:6d69e896ce38	845	* The value must be in the range [-127 127].[get]
cparata	0:6d69e896ce38	846	*
cparata	0:6d69e896ce38	847	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	848	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	849	*
cparata	0:6d69e896ce38	850	*/
cparata	0:6d69e896ce38	851	int32_t lsm6dso_xl_usr_offset_z_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	852	{
cparata	0:6d69e896ce38	853	int32_t ret;
cparata	0:6d69e896ce38	854	ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
cparata	0:6d69e896ce38	855	return ret;
cparata	0:6d69e896ce38	856	}
cparata	0:6d69e896ce38	857
cparata	0:6d69e896ce38	858	/**
cparata	0:6d69e896ce38	859	* @brief Enables user offset on out.[set]
cparata	0:6d69e896ce38	860	*
cparata	0:6d69e896ce38	861	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	862	* @param val change the values of usr_off_on_out in reg CTRL7_G
cparata	0:6d69e896ce38	863	*
cparata	0:6d69e896ce38	864	*/
cparata	0:6d69e896ce38	865	int32_t lsm6dso_xl_usr_offset_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	866	{
cparata	0:6d69e896ce38	867	lsm6dso_ctrl7_g_t reg;
cparata	0:6d69e896ce38	868	int32_t ret;
cparata	0:6d69e896ce38	869
cparata	0:6d69e896ce38	870	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	871	if (ret == 0) {
cparata	0:6d69e896ce38	872	reg.usr_off_on_out = val;
cparata	0:6d69e896ce38	873	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	874	}
cparata	0:6d69e896ce38	875	return ret;
cparata	0:6d69e896ce38	876	}
cparata	0:6d69e896ce38	877
cparata	0:6d69e896ce38	878	/**
cparata	0:6d69e896ce38	879	* @brief User offset on out flag.[get]
cparata	0:6d69e896ce38	880	*
cparata	0:6d69e896ce38	881	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	882	* @param val values of usr_off_on_out in reg CTRL7_G
cparata	0:6d69e896ce38	883	*
cparata	0:6d69e896ce38	884	*/
cparata	0:6d69e896ce38	885	int32_t lsm6dso_xl_usr_offset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	886	{
cparata	0:6d69e896ce38	887	lsm6dso_ctrl7_g_t reg;
cparata	0:6d69e896ce38	888	int32_t ret;
cparata	0:6d69e896ce38	889
cparata	0:6d69e896ce38	890	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	891	*val = reg.usr_off_on_out;
cparata	0:6d69e896ce38	892
cparata	0:6d69e896ce38	893	return ret;
cparata	0:6d69e896ce38	894	}
cparata	0:6d69e896ce38	895
cparata	0:6d69e896ce38	896	/**
cparata	0:6d69e896ce38	897	* @}
cparata	0:6d69e896ce38	898	*
cparata	0:6d69e896ce38	899	*/
cparata	0:6d69e896ce38	900
cparata	0:6d69e896ce38	901	/**
cparata	0:6d69e896ce38	902	* @defgroup LSM6DSO_Timestamp
cparata	0:6d69e896ce38	903	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	904	* timestamp generation.
cparata	0:6d69e896ce38	905	* @{
cparata	0:6d69e896ce38	906	*
cparata	0:6d69e896ce38	907	*/
cparata	0:6d69e896ce38	908
cparata	0:6d69e896ce38	909	/**
cparata	0:6d69e896ce38	910	* @brief Enables timestamp counter.[set]
cparata	0:6d69e896ce38	911	*
cparata	0:6d69e896ce38	912	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	913	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:6d69e896ce38	914	*
cparata	0:6d69e896ce38	915	*/
cparata	0:6d69e896ce38	916	int32_t lsm6dso_timestamp_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	917	{
cparata	0:6d69e896ce38	918	lsm6dso_ctrl10_c_t reg;
cparata	0:6d69e896ce38	919	int32_t ret;
cparata	0:6d69e896ce38	920
cparata	0:6d69e896ce38	921	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	922	if (ret == 0) {
cparata	0:6d69e896ce38	923	reg.timestamp_en = val;
cparata	0:6d69e896ce38	924	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	925	}
cparata	0:6d69e896ce38	926	return ret;
cparata	0:6d69e896ce38	927	}
cparata	0:6d69e896ce38	928
cparata	0:6d69e896ce38	929	/**
cparata	0:6d69e896ce38	930	* @brief Enables timestamp counter.[get]
cparata	0:6d69e896ce38	931	*
cparata	0:6d69e896ce38	932	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	933	* @param val change the values of timestamp_en in reg CTRL10_C
cparata	0:6d69e896ce38	934	*
cparata	0:6d69e896ce38	935	*/
cparata	0:6d69e896ce38	936	int32_t lsm6dso_timestamp_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	937	{
cparata	0:6d69e896ce38	938	lsm6dso_ctrl10_c_t reg;
cparata	0:6d69e896ce38	939	int32_t ret;
cparata	0:6d69e896ce38	940
cparata	0:6d69e896ce38	941	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	942	*val = reg.timestamp_en;
cparata	0:6d69e896ce38	943
cparata	0:6d69e896ce38	944	return ret;
cparata	0:6d69e896ce38	945	}
cparata	0:6d69e896ce38	946
cparata	0:6d69e896ce38	947	/**
cparata	0:6d69e896ce38	948	* @brief Timestamp first data output register (r).
cparata	0:6d69e896ce38	949	* The value is expressed as a 32-bit word and the bit
cparata	0:6d69e896ce38	950	* resolution is 25 μs.[get]
cparata	0:6d69e896ce38	951	*
cparata	0:6d69e896ce38	952	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	953	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	954	*
cparata	0:6d69e896ce38	955	*/
cparata	0:6d69e896ce38	956	int32_t lsm6dso_timestamp_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	957	{
cparata	0:6d69e896ce38	958	int32_t ret;
cparata	0:6d69e896ce38	959	ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4);
cparata	0:6d69e896ce38	960	return ret;
cparata	0:6d69e896ce38	961	}
cparata	0:6d69e896ce38	962
cparata	0:6d69e896ce38	963	/**
cparata	0:6d69e896ce38	964	* @}
cparata	0:6d69e896ce38	965	*
cparata	0:6d69e896ce38	966	*/
cparata	0:6d69e896ce38	967
cparata	0:6d69e896ce38	968	/**
cparata	0:6d69e896ce38	969	* @defgroup LSM6DSO_Data output
cparata	0:6d69e896ce38	970	* @brief This section groups all the data output functions.
cparata	0:6d69e896ce38	971	* @{
cparata	0:6d69e896ce38	972	*
cparata	0:6d69e896ce38	973	*/
cparata	0:6d69e896ce38	974
cparata	0:6d69e896ce38	975	/**
cparata	0:6d69e896ce38	976	* @brief Circular burst-mode (rounding) read of the output
cparata	0:6d69e896ce38	977	* registers.[set]
cparata	0:6d69e896ce38	978	*
cparata	0:6d69e896ce38	979	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	980	* @param val change the values of rounding in reg CTRL5_C
cparata	0:6d69e896ce38	981	*
cparata	0:6d69e896ce38	982	*/
cparata	0:6d69e896ce38	983	int32_t lsm6dso_rounding_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	984	lsm6dso_rounding_t val)
cparata	0:6d69e896ce38	985	{
cparata	0:6d69e896ce38	986	lsm6dso_ctrl5_c_t reg;
cparata	0:6d69e896ce38	987	int32_t ret;
cparata	0:6d69e896ce38	988
cparata	0:6d69e896ce38	989	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	990	if (ret == 0) {
cparata	0:6d69e896ce38	991	reg.rounding = (uint8_t)val;
cparata	0:6d69e896ce38	992	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	993	}
cparata	0:6d69e896ce38	994	return ret;
cparata	0:6d69e896ce38	995	}
cparata	0:6d69e896ce38	996
cparata	0:6d69e896ce38	997	/**
cparata	0:6d69e896ce38	998	* @brief Gyroscope UI chain full-scale selection.[get]
cparata	0:6d69e896ce38	999	*
cparata	0:6d69e896ce38	1000	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1001	* @param val Get the values of rounding in reg CTRL5_C
cparata	0:6d69e896ce38	1002	*
cparata	0:6d69e896ce38	1003	*/
cparata	0:6d69e896ce38	1004	int32_t lsm6dso_rounding_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1005	lsm6dso_rounding_t *val)
cparata	0:6d69e896ce38	1006	{
cparata	0:6d69e896ce38	1007	lsm6dso_ctrl5_c_t reg;
cparata	0:6d69e896ce38	1008	int32_t ret;
cparata	0:6d69e896ce38	1009
cparata	0:6d69e896ce38	1010	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1011	switch (reg.rounding) {
cparata	0:6d69e896ce38	1012	case LSM6DSO_NO_ROUND:
cparata	0:6d69e896ce38	1013	*val = LSM6DSO_NO_ROUND;
cparata	0:6d69e896ce38	1014	break;
cparata	0:6d69e896ce38	1015	case LSM6DSO_ROUND_XL:
cparata	0:6d69e896ce38	1016	*val = LSM6DSO_ROUND_XL;
cparata	0:6d69e896ce38	1017	break;
cparata	0:6d69e896ce38	1018	case LSM6DSO_ROUND_GY:
cparata	0:6d69e896ce38	1019	*val = LSM6DSO_ROUND_GY;
cparata	0:6d69e896ce38	1020	break;
cparata	0:6d69e896ce38	1021	case LSM6DSO_ROUND_GY_XL:
cparata	0:6d69e896ce38	1022	*val = LSM6DSO_ROUND_GY_XL;
cparata	0:6d69e896ce38	1023	break;
cparata	0:6d69e896ce38	1024	default:
cparata	0:6d69e896ce38	1025	*val = LSM6DSO_NO_ROUND;
cparata	0:6d69e896ce38	1026	break;
cparata	0:6d69e896ce38	1027	}
cparata	0:6d69e896ce38	1028	return ret;
cparata	0:6d69e896ce38	1029	}
cparata	0:6d69e896ce38	1030
cparata	0:6d69e896ce38	1031	/**
cparata	0:6d69e896ce38	1032	* @brief Temperature data output register (r).
cparata	0:6d69e896ce38	1033	* L and H registers together express a 16-bit word in two’s
cparata	0:6d69e896ce38	1034	* complement.[get]
cparata	0:6d69e896ce38	1035	*
cparata	0:6d69e896ce38	1036	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1037	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1038	*
cparata	0:6d69e896ce38	1039	*/
cparata	0:6d69e896ce38	1040	int32_t lsm6dso_temperature_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1041	{
cparata	0:6d69e896ce38	1042	int32_t ret;
cparata	0:6d69e896ce38	1043	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2);
cparata	0:6d69e896ce38	1044	return ret;
cparata	0:6d69e896ce38	1045	}
cparata	0:6d69e896ce38	1046
cparata	0:6d69e896ce38	1047	/**
cparata	0:6d69e896ce38	1048	* @brief Angular rate sensor. The value is expressed as a 16-bit
cparata	0:6d69e896ce38	1049	* word in two’s complement.[get]
cparata	0:6d69e896ce38	1050	*
cparata	0:6d69e896ce38	1051	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1052	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1053	*
cparata	0:6d69e896ce38	1054	*/
cparata	0:6d69e896ce38	1055	int32_t lsm6dso_angular_rate_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1056	{
cparata	0:6d69e896ce38	1057	int32_t ret;
cparata	0:6d69e896ce38	1058	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6);
cparata	0:6d69e896ce38	1059	return ret;
cparata	0:6d69e896ce38	1060	}
cparata	0:6d69e896ce38	1061
cparata	0:6d69e896ce38	1062	/**
cparata	0:6d69e896ce38	1063	* @brief Linear acceleration output register.
cparata	0:6d69e896ce38	1064	* The value is expressed as a 16-bit word in two’s complement.[get]
cparata	0:6d69e896ce38	1065	*
cparata	0:6d69e896ce38	1066	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1067	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1068	*
cparata	0:6d69e896ce38	1069	*/
cparata	0:6d69e896ce38	1070	int32_t lsm6dso_acceleration_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1071	{
cparata	0:6d69e896ce38	1072	int32_t ret;
cparata	0:6d69e896ce38	1073	ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6);
cparata	0:6d69e896ce38	1074	return ret;
cparata	0:6d69e896ce38	1075	}
cparata	0:6d69e896ce38	1076
cparata	0:6d69e896ce38	1077	/**
cparata	0:6d69e896ce38	1078	* @brief FIFO data output [get]
cparata	0:6d69e896ce38	1079	*
cparata	0:6d69e896ce38	1080	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1081	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1082	*
cparata	0:6d69e896ce38	1083	*/
cparata	0:6d69e896ce38	1084	int32_t lsm6dso_fifo_out_raw_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1085	{
cparata	0:6d69e896ce38	1086	int32_t ret;
cparata	0:6d69e896ce38	1087	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6);
cparata	0:6d69e896ce38	1088	return ret;
cparata	0:6d69e896ce38	1089	}
cparata	0:6d69e896ce38	1090
cparata	0:6d69e896ce38	1091	/**
cparata	0:6d69e896ce38	1092	* @brief Step counter output register.[get]
cparata	0:6d69e896ce38	1093	*
cparata	0:6d69e896ce38	1094	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1095	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1096	*
cparata	0:6d69e896ce38	1097	*/
cparata	0:6d69e896ce38	1098	int32_t lsm6dso_number_of_steps_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1099	{
cparata	0:6d69e896ce38	1100	int32_t ret;
cparata	0:6d69e896ce38	1101
cparata	0:6d69e896ce38	1102	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	1103	if (ret == 0) {
cparata	0:6d69e896ce38	1104	ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2);
cparata	0:6d69e896ce38	1105	}
cparata	0:6d69e896ce38	1106	if (ret == 0) {
cparata	0:6d69e896ce38	1107	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	1108	}
cparata	0:6d69e896ce38	1109	return ret;
cparata	0:6d69e896ce38	1110	}
cparata	0:6d69e896ce38	1111
cparata	0:6d69e896ce38	1112	/**
cparata	0:6d69e896ce38	1113	* @brief Reset step counter register.[get]
cparata	0:6d69e896ce38	1114	*
cparata	0:6d69e896ce38	1115	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1116	*
cparata	0:6d69e896ce38	1117	*/
cparata	0:6d69e896ce38	1118	int32_t lsm6dso_steps_reset(lsm6dso_ctx_t *ctx)
cparata	0:6d69e896ce38	1119	{
cparata	0:6d69e896ce38	1120	lsm6dso_emb_func_src_t reg;
cparata	0:6d69e896ce38	1121	int32_t ret;
cparata	0:6d69e896ce38	1122
cparata	0:6d69e896ce38	1123	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	1124	if (ret == 0) {
cparata	0:6d69e896ce38	1125	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1126	}
cparata	0:6d69e896ce38	1127	if (ret == 0) {
cparata	0:6d69e896ce38	1128	reg.pedo_rst_step = PROPERTY_ENABLE;
cparata	0:6d69e896ce38	1129	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1130	}
cparata	0:6d69e896ce38	1131	if (ret == 0) {
cparata	0:6d69e896ce38	1132	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	1133	}
cparata	0:6d69e896ce38	1134	return ret;
cparata	0:6d69e896ce38	1135	}
cparata	0:6d69e896ce38	1136
cparata	0:6d69e896ce38	1137	/**
cparata	0:6d69e896ce38	1138	* @}
cparata	0:6d69e896ce38	1139	*
cparata	0:6d69e896ce38	1140	*/
cparata	0:6d69e896ce38	1141
cparata	0:6d69e896ce38	1142	/**
cparata	0:6d69e896ce38	1143	* @defgroup LSM6DSO_common
cparata	0:6d69e896ce38	1144	* @brief This section groups common usefull functions.
cparata	0:6d69e896ce38	1145	* @{
cparata	0:6d69e896ce38	1146	*
cparata	0:6d69e896ce38	1147	*/
cparata	0:6d69e896ce38	1148
cparata	0:6d69e896ce38	1149	/**
cparata	0:6d69e896ce38	1150	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:6d69e896ce38	1151	* with respect to the typical.
cparata	0:6d69e896ce38	1152	* Step: 0.15%. 8-bit format, 2's complement.[set]
cparata	0:6d69e896ce38	1153	*
cparata	0:6d69e896ce38	1154	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1155	* @param val change the values of freq_fine in reg
cparata	0:6d69e896ce38	1156	* INTERNAL_FREQ_FINE
cparata	0:6d69e896ce38	1157	*
cparata	0:6d69e896ce38	1158	*/
cparata	0:6d69e896ce38	1159	int32_t lsm6dso_odr_cal_reg_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1160	{
cparata	0:6d69e896ce38	1161	lsm6dso_internal_freq_fine_t reg;
cparata	0:6d69e896ce38	1162	int32_t ret;
cparata	0:6d69e896ce38	1163
cparata	0:6d69e896ce38	1164	ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1165	if (ret == 0) {
cparata	0:6d69e896ce38	1166	reg.freq_fine = val;
cparata	0:6d69e896ce38	1167	ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
cparata	0:6d69e896ce38	1168	(uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1169	}
cparata	0:6d69e896ce38	1170	return ret;
cparata	0:6d69e896ce38	1171	}
cparata	0:6d69e896ce38	1172
cparata	0:6d69e896ce38	1173	/**
cparata	0:6d69e896ce38	1174	* @brief Difference in percentage of the effective ODR(and timestamp rate)
cparata	0:6d69e896ce38	1175	* with respect to the typical.
cparata	0:6d69e896ce38	1176	* Step: 0.15%. 8-bit format, 2's complement.[get]
cparata	0:6d69e896ce38	1177	*
cparata	0:6d69e896ce38	1178	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1179	* @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
cparata	0:6d69e896ce38	1180	*
cparata	0:6d69e896ce38	1181	*/
cparata	0:6d69e896ce38	1182	int32_t lsm6dso_odr_cal_reg_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1183	{
cparata	0:6d69e896ce38	1184	lsm6dso_internal_freq_fine_t reg;
cparata	0:6d69e896ce38	1185	int32_t ret;
cparata	0:6d69e896ce38	1186
cparata	0:6d69e896ce38	1187	ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1188	*val = reg.freq_fine;
cparata	0:6d69e896ce38	1189
cparata	0:6d69e896ce38	1190	return ret;
cparata	0:6d69e896ce38	1191	}
cparata	0:6d69e896ce38	1192
cparata	0:6d69e896ce38	1193
cparata	0:6d69e896ce38	1194	/**
cparata	0:6d69e896ce38	1195	* @brief Enable access to the embedded functions/sensor
cparata	0:6d69e896ce38	1196	* hub configuration registers.[set]
cparata	0:6d69e896ce38	1197	*
cparata	0:6d69e896ce38	1198	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1199	* @param val change the values of reg_access in
cparata	0:6d69e896ce38	1200	* reg FUNC_CFG_ACCESS
cparata	0:6d69e896ce38	1201	*
cparata	0:6d69e896ce38	1202	*/
cparata	0:6d69e896ce38	1203	int32_t lsm6dso_mem_bank_set(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t val)
cparata	0:6d69e896ce38	1204	{
cparata	0:6d69e896ce38	1205	lsm6dso_func_cfg_access_t reg;
cparata	0:6d69e896ce38	1206	int32_t ret;
cparata	0:6d69e896ce38	1207
cparata	0:6d69e896ce38	1208	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1209	if (ret == 0) {
cparata	0:6d69e896ce38	1210	reg.reg_access = (uint8_t)val;
cparata	0:6d69e896ce38	1211	ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1212	}
cparata	0:6d69e896ce38	1213	return ret;
cparata	0:6d69e896ce38	1214	}
cparata	0:6d69e896ce38	1215
cparata	0:6d69e896ce38	1216	/**
cparata	0:6d69e896ce38	1217	* @brief Enable access to the embedded functions/sensor
cparata	0:6d69e896ce38	1218	* hub configuration registers.[get]
cparata	0:6d69e896ce38	1219	*
cparata	0:6d69e896ce38	1220	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1221	* @param val Get the values of reg_access in
cparata	0:6d69e896ce38	1222	* reg FUNC_CFG_ACCESS
cparata	0:6d69e896ce38	1223	*
cparata	0:6d69e896ce38	1224	*/
cparata	0:6d69e896ce38	1225	int32_t lsm6dso_mem_bank_get(lsm6dso_ctx_t ctx, lsm6dso_reg_access_t val)
cparata	0:6d69e896ce38	1226	{
cparata	0:6d69e896ce38	1227	lsm6dso_func_cfg_access_t reg;
cparata	0:6d69e896ce38	1228	int32_t ret;
cparata	0:6d69e896ce38	1229
cparata	0:6d69e896ce38	1230	ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1231	switch (reg.reg_access) {
cparata	0:6d69e896ce38	1232	case LSM6DSO_USER_BANK:
cparata	0:6d69e896ce38	1233	*val = LSM6DSO_USER_BANK;
cparata	0:6d69e896ce38	1234	break;
cparata	0:6d69e896ce38	1235	case LSM6DSO_SENSOR_HUB_BANK:
cparata	0:6d69e896ce38	1236	*val = LSM6DSO_SENSOR_HUB_BANK;
cparata	0:6d69e896ce38	1237	break;
cparata	0:6d69e896ce38	1238	case LSM6DSO_EMBEDDED_FUNC_BANK:
cparata	0:6d69e896ce38	1239	*val = LSM6DSO_EMBEDDED_FUNC_BANK;
cparata	0:6d69e896ce38	1240	break;
cparata	0:6d69e896ce38	1241	default:
cparata	0:6d69e896ce38	1242	*val = LSM6DSO_USER_BANK;
cparata	0:6d69e896ce38	1243	break;
cparata	0:6d69e896ce38	1244	}
cparata	0:6d69e896ce38	1245	return ret;
cparata	0:6d69e896ce38	1246	}
cparata	0:6d69e896ce38	1247
cparata	0:6d69e896ce38	1248	/**
cparata	0:6d69e896ce38	1249	* @brief Write a line(byte) in a page.[set]
cparata	0:6d69e896ce38	1250	*
cparata	0:6d69e896ce38	1251	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1252	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1253	* @param val value to write
cparata	0:6d69e896ce38	1254	*
cparata	0:6d69e896ce38	1255	*/
cparata	0:6d69e896ce38	1256	int32_t lsm6dso_ln_pg_write_byte(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1257	uint8_t *val)
cparata	0:6d69e896ce38	1258	{
cparata	0:6d69e896ce38	1259	lsm6dso_page_rw_t page_rw;
cparata	0:6d69e896ce38	1260	lsm6dso_page_sel_t page_sel;
cparata	0:6d69e896ce38	1261	lsm6dso_page_address_t page_address;
cparata	0:6d69e896ce38	1262	int32_t ret;
cparata	0:6d69e896ce38	1263
cparata	0:6d69e896ce38	1264	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	1265
cparata	0:6d69e896ce38	1266	if (ret == 0) {
cparata	0:6d69e896ce38	1267	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1268	}
cparata	0:6d69e896ce38	1269	if (ret == 0) {
cparata	0:6d69e896ce38	1270	page_rw.page_rw = 0x02; /* page_write enable */
cparata	0:6d69e896ce38	1271	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1272	}
cparata	0:6d69e896ce38	1273	if (ret == 0) {
cparata	0:6d69e896ce38	1274	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:6d69e896ce38	1275	}
cparata	0:6d69e896ce38	1276
cparata	0:6d69e896ce38	1277	if (ret == 0) {
cparata	2:4d14e9edf37e	1278	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	0:6d69e896ce38	1279	page_sel.not_used_01 = 1;
cparata	0:6d69e896ce38	1280	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:6d69e896ce38	1281	}
cparata	0:6d69e896ce38	1282	if (ret == 0) {
cparata	0:6d69e896ce38	1283	page_address.page_addr = (uint8_t)address & 0xFFU;
cparata	0:6d69e896ce38	1284	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	0:6d69e896ce38	1285	(uint8_t*)&page_address, 1);
cparata	0:6d69e896ce38	1286	}
cparata	0:6d69e896ce38	1287	if (ret == 0) {
cparata	0:6d69e896ce38	1288	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
cparata	0:6d69e896ce38	1289	}
cparata	0:6d69e896ce38	1290	if (ret == 0) {
cparata	0:6d69e896ce38	1291	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1292	}
cparata	0:6d69e896ce38	1293	if (ret == 0) {
cparata	0:6d69e896ce38	1294	page_rw.page_rw = 0x00; /* page_write disable */
cparata	0:6d69e896ce38	1295	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1296	}
cparata	0:6d69e896ce38	1297	if (ret == 0) {
cparata	0:6d69e896ce38	1298
cparata	0:6d69e896ce38	1299	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	1300	}
cparata	0:6d69e896ce38	1301	return ret;
cparata	0:6d69e896ce38	1302	}
cparata	0:6d69e896ce38	1303
cparata	0:6d69e896ce38	1304	/**
cparata	0:6d69e896ce38	1305	* @brief Write buffer in a page.[set]
cparata	0:6d69e896ce38	1306	*
cparata	0:6d69e896ce38	1307	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1308	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1309	* @param uint8_t *buf: buffer to write
cparata	0:6d69e896ce38	1310	* @param uint8_t len: buffer len
cparata	0:6d69e896ce38	1311	*
cparata	0:6d69e896ce38	1312	*/
cparata	0:6d69e896ce38	1313	int32_t lsm6dso_ln_pg_write(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1314	uint8_t *buf, uint8_t len)
cparata	0:6d69e896ce38	1315	{
cparata	0:6d69e896ce38	1316	lsm6dso_page_rw_t page_rw;
cparata	0:6d69e896ce38	1317	lsm6dso_page_sel_t page_sel;
cparata	0:6d69e896ce38	1318	lsm6dso_page_address_t page_address;
cparata	2:4d14e9edf37e	1319	uint16_t addr_pointed;
cparata	2:4d14e9edf37e	1320	int32_t ret;
cparata	0:6d69e896ce38	1321	uint8_t i ;
cparata	0:6d69e896ce38	1322
cparata	2:4d14e9edf37e	1323	addr_pointed = address;
cparata	0:6d69e896ce38	1324
cparata	0:6d69e896ce38	1325	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	1326	if (ret == 0) {
cparata	0:6d69e896ce38	1327
cparata	0:6d69e896ce38	1328	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1329	}
cparata	0:6d69e896ce38	1330	if (ret == 0) {
cparata	0:6d69e896ce38	1331	page_rw.page_rw = 0x02; /* page_write enable*/
cparata	0:6d69e896ce38	1332	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1333	}
cparata	0:6d69e896ce38	1334	if (ret == 0) {
cparata	0:6d69e896ce38	1335	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:6d69e896ce38	1336	}
cparata	0:6d69e896ce38	1337	if (ret == 0) {
cparata	2:4d14e9edf37e	1338	page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
cparata	0:6d69e896ce38	1339	page_sel.not_used_01 = 1;
cparata	0:6d69e896ce38	1340	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:6d69e896ce38	1341	}
cparata	0:6d69e896ce38	1342	if (ret == 0) {
cparata	2:4d14e9edf37e	1343	page_address.page_addr = (uint8_t)(addr_pointed & 0x00FFU);
cparata	0:6d69e896ce38	1344	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	0:6d69e896ce38	1345	(uint8_t*)&page_address, 1);
cparata	0:6d69e896ce38	1346	}
cparata	0:6d69e896ce38	1347
cparata	0:6d69e896ce38	1348	if (ret == 0) {
cparata	2:4d14e9edf37e	1349	for (i = 0; ( (i < len) && (ret == 0) ); i++) {
cparata	0:6d69e896ce38	1350	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1);
cparata	2:4d14e9edf37e	1351	addr_pointed++;
cparata	0:6d69e896ce38	1352	/* Check if page wrap */
cparata	2:4d14e9edf37e	1353	if ( ( (addr_pointed % 0x0100U) == 0x00U ) && (ret == 0) ) {
cparata	0:6d69e896ce38	1354	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*)&page_sel, 1);
cparata	0:6d69e896ce38	1355	if (ret == 0) {
cparata	2:4d14e9edf37e	1356	page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
cparata	0:6d69e896ce38	1357	page_sel.not_used_01 = 1;
cparata	0:6d69e896ce38	1358	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL,
cparata	0:6d69e896ce38	1359	(uint8_t*)&page_sel, 1);
cparata	0:6d69e896ce38	1360	}
cparata	0:6d69e896ce38	1361	}
cparata	0:6d69e896ce38	1362	}
cparata	0:6d69e896ce38	1363	page_sel.page_sel = 0;
cparata	0:6d69e896ce38	1364	page_sel.not_used_01 = 1;
cparata	0:6d69e896ce38	1365	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:6d69e896ce38	1366	}
cparata	0:6d69e896ce38	1367	if (ret == 0) {
cparata	0:6d69e896ce38	1368	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1369	}
cparata	0:6d69e896ce38	1370	if (ret == 0) {
cparata	0:6d69e896ce38	1371	page_rw.page_rw = 0x00; /* page_write disable */
cparata	0:6d69e896ce38	1372	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1373	}
cparata	2:4d14e9edf37e	1374	if (ret == 0) {
cparata	0:6d69e896ce38	1375	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	1376	}
cparata	0:6d69e896ce38	1377	return ret;
cparata	0:6d69e896ce38	1378	}
cparata	0:6d69e896ce38	1379
cparata	0:6d69e896ce38	1380	/**
cparata	0:6d69e896ce38	1381	* @brief Read a line(byte) in a page.[get]
cparata	0:6d69e896ce38	1382	*
cparata	0:6d69e896ce38	1383	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1384	* @param uint8_t address: page line address
cparata	0:6d69e896ce38	1385	* @param val read value
cparata	0:6d69e896ce38	1386	*
cparata	0:6d69e896ce38	1387	*/
cparata	0:6d69e896ce38	1388	int32_t lsm6dso_ln_pg_read_byte(lsm6dso_ctx_t *ctx, uint16_t address,
cparata	0:6d69e896ce38	1389	uint8_t *val)
cparata	0:6d69e896ce38	1390	{
cparata	0:6d69e896ce38	1391	lsm6dso_page_rw_t page_rw;
cparata	0:6d69e896ce38	1392	lsm6dso_page_sel_t page_sel;
cparata	0:6d69e896ce38	1393	lsm6dso_page_address_t page_address;
cparata	0:6d69e896ce38	1394	int32_t ret;
cparata	0:6d69e896ce38	1395
cparata	0:6d69e896ce38	1396	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	1397	if (ret == 0) {
cparata	0:6d69e896ce38	1398
cparata	0:6d69e896ce38	1399	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1400	}
cparata	0:6d69e896ce38	1401	if (ret == 0) {
cparata	0:6d69e896ce38	1402	page_rw.page_rw = 0x01; /* page_read enable*/
cparata	0:6d69e896ce38	1403	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1404	}
cparata	0:6d69e896ce38	1405	if (ret == 0) {
cparata	0:6d69e896ce38	1406
cparata	0:6d69e896ce38	1407	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:6d69e896ce38	1408	}
cparata	0:6d69e896ce38	1409	if (ret == 0) {
cparata	2:4d14e9edf37e	1410	page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
cparata	0:6d69e896ce38	1411	page_sel.not_used_01 = 1;
cparata	0:6d69e896ce38	1412	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1);
cparata	0:6d69e896ce38	1413	}
cparata	0:6d69e896ce38	1414	if (ret == 0) {
cparata	0:6d69e896ce38	1415	page_address.page_addr = (uint8_t)address & 0x00FFU;
cparata	0:6d69e896ce38	1416	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
cparata	0:6d69e896ce38	1417	(uint8_t*)&page_address, 1);
cparata	0:6d69e896ce38	1418	}
cparata	0:6d69e896ce38	1419	if (ret == 0) {
cparata	0:6d69e896ce38	1420
cparata	0:6d69e896ce38	1421	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, val, 2);
cparata	0:6d69e896ce38	1422	}
cparata	0:6d69e896ce38	1423	if (ret == 0) {
cparata	0:6d69e896ce38	1424	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1425	}
cparata	0:6d69e896ce38	1426	if (ret == 0) {
cparata	0:6d69e896ce38	1427	page_rw.page_rw = 0x00; /* page_read disable */
cparata	0:6d69e896ce38	1428	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	1429	}
cparata	0:6d69e896ce38	1430	if (ret == 0) {
cparata	0:6d69e896ce38	1431	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	1432	}
cparata	0:6d69e896ce38	1433
cparata	0:6d69e896ce38	1434	return ret;
cparata	0:6d69e896ce38	1435	}
cparata	0:6d69e896ce38	1436
cparata	0:6d69e896ce38	1437	/**
cparata	0:6d69e896ce38	1438	* @brief Data-ready pulsed / letched mode.[set]
cparata	0:6d69e896ce38	1439	*
cparata	0:6d69e896ce38	1440	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1441	* @param val change the values of
cparata	0:6d69e896ce38	1442	* dataready_pulsed in
cparata	0:6d69e896ce38	1443	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	1444	*
cparata	0:6d69e896ce38	1445	*/
cparata	0:6d69e896ce38	1446	int32_t lsm6dso_data_ready_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1447	lsm6dso_dataready_pulsed_t val)
cparata	0:6d69e896ce38	1448	{
cparata	0:6d69e896ce38	1449	lsm6dso_counter_bdr_reg1_t reg;
cparata	0:6d69e896ce38	1450	int32_t ret;
cparata	0:6d69e896ce38	1451
cparata	0:6d69e896ce38	1452	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1453	if (ret == 0) {
cparata	0:6d69e896ce38	1454	reg.dataready_pulsed = (uint8_t)val;
cparata	0:6d69e896ce38	1455	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1456	}
cparata	0:6d69e896ce38	1457	return ret;
cparata	0:6d69e896ce38	1458	}
cparata	0:6d69e896ce38	1459
cparata	0:6d69e896ce38	1460	/**
cparata	0:6d69e896ce38	1461	* @brief Data-ready pulsed / letched mode.[get]
cparata	0:6d69e896ce38	1462	*
cparata	0:6d69e896ce38	1463	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1464	* @param val Get the values of
cparata	0:6d69e896ce38	1465	* dataready_pulsed in
cparata	0:6d69e896ce38	1466	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	1467	*
cparata	0:6d69e896ce38	1468	*/
cparata	0:6d69e896ce38	1469	int32_t lsm6dso_data_ready_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1470	lsm6dso_dataready_pulsed_t *val)
cparata	0:6d69e896ce38	1471	{
cparata	0:6d69e896ce38	1472	lsm6dso_counter_bdr_reg1_t reg;
cparata	0:6d69e896ce38	1473	int32_t ret;
cparata	0:6d69e896ce38	1474
cparata	0:6d69e896ce38	1475	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1476	switch (reg.dataready_pulsed) {
cparata	0:6d69e896ce38	1477	case LSM6DSO_DRDY_LATCHED:
cparata	0:6d69e896ce38	1478	*val = LSM6DSO_DRDY_LATCHED;
cparata	0:6d69e896ce38	1479	break;
cparata	0:6d69e896ce38	1480	case LSM6DSO_DRDY_PULSED:
cparata	0:6d69e896ce38	1481	*val = LSM6DSO_DRDY_PULSED;
cparata	0:6d69e896ce38	1482	break;
cparata	0:6d69e896ce38	1483	default:
cparata	0:6d69e896ce38	1484	*val = LSM6DSO_DRDY_LATCHED;
cparata	0:6d69e896ce38	1485	break;
cparata	0:6d69e896ce38	1486	}
cparata	0:6d69e896ce38	1487	return ret;
cparata	0:6d69e896ce38	1488	}
cparata	0:6d69e896ce38	1489
cparata	0:6d69e896ce38	1490	/**
cparata	0:6d69e896ce38	1491	* @brief Device "Who am I".[get]
cparata	0:6d69e896ce38	1492	*
cparata	0:6d69e896ce38	1493	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1494	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	1495	*
cparata	0:6d69e896ce38	1496	*/
cparata	0:6d69e896ce38	1497	int32_t lsm6dso_device_id_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	1498	{
cparata	0:6d69e896ce38	1499	int32_t ret;
cparata	0:6d69e896ce38	1500	ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1);
cparata	0:6d69e896ce38	1501	return ret;
cparata	0:6d69e896ce38	1502	}
cparata	0:6d69e896ce38	1503
cparata	0:6d69e896ce38	1504	/**
cparata	0:6d69e896ce38	1505	* @brief Software reset. Restore the default values
cparata	0:6d69e896ce38	1506	* in user registers[set]
cparata	0:6d69e896ce38	1507	*
cparata	0:6d69e896ce38	1508	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1509	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:6d69e896ce38	1510	*
cparata	0:6d69e896ce38	1511	*/
cparata	0:6d69e896ce38	1512	int32_t lsm6dso_reset_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1513	{
cparata	0:6d69e896ce38	1514	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	1515	int32_t ret;
cparata	0:6d69e896ce38	1516
cparata	0:6d69e896ce38	1517	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1518	if (ret == 0) {
cparata	0:6d69e896ce38	1519	reg.sw_reset = val;
cparata	0:6d69e896ce38	1520	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1521	}
cparata	0:6d69e896ce38	1522
cparata	0:6d69e896ce38	1523	return ret;
cparata	0:6d69e896ce38	1524	}
cparata	0:6d69e896ce38	1525
cparata	0:6d69e896ce38	1526	/**
cparata	0:6d69e896ce38	1527	* @brief Software reset. Restore the default values in user registers.[get]
cparata	0:6d69e896ce38	1528	*
cparata	0:6d69e896ce38	1529	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1530	* @param val change the values of sw_reset in reg CTRL3_C
cparata	0:6d69e896ce38	1531	*
cparata	0:6d69e896ce38	1532	*/
cparata	0:6d69e896ce38	1533	int32_t lsm6dso_reset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1534	{
cparata	0:6d69e896ce38	1535	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	1536	int32_t ret;
cparata	0:6d69e896ce38	1537
cparata	0:6d69e896ce38	1538	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1539	*val = reg.sw_reset;
cparata	0:6d69e896ce38	1540
cparata	0:6d69e896ce38	1541	return ret;
cparata	0:6d69e896ce38	1542	}
cparata	0:6d69e896ce38	1543
cparata	0:6d69e896ce38	1544	/**
cparata	0:6d69e896ce38	1545	* @brief Register address automatically incremented during a multiple byte
cparata	0:6d69e896ce38	1546	* access with a serial interface.[set]
cparata	0:6d69e896ce38	1547	*
cparata	0:6d69e896ce38	1548	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1549	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:6d69e896ce38	1550	*
cparata	0:6d69e896ce38	1551	*/
cparata	0:6d69e896ce38	1552	int32_t lsm6dso_auto_increment_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1553	{
cparata	0:6d69e896ce38	1554	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	1555	int32_t ret;
cparata	0:6d69e896ce38	1556
cparata	0:6d69e896ce38	1557	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1558	if (ret == 0) {
cparata	0:6d69e896ce38	1559	reg.if_inc = val;
cparata	0:6d69e896ce38	1560	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1561	}
cparata	0:6d69e896ce38	1562	return ret;
cparata	0:6d69e896ce38	1563	}
cparata	0:6d69e896ce38	1564
cparata	0:6d69e896ce38	1565	/**
cparata	0:6d69e896ce38	1566	* @brief Register address automatically incremented during a multiple byte
cparata	0:6d69e896ce38	1567	* access with a serial interface.[get]
cparata	0:6d69e896ce38	1568	*
cparata	0:6d69e896ce38	1569	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1570	* @param val change the values of if_inc in reg CTRL3_C
cparata	0:6d69e896ce38	1571	*
cparata	0:6d69e896ce38	1572	*/
cparata	0:6d69e896ce38	1573	int32_t lsm6dso_auto_increment_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1574	{
cparata	0:6d69e896ce38	1575	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	1576	int32_t ret;
cparata	0:6d69e896ce38	1577
cparata	0:6d69e896ce38	1578	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1579	*val = reg.if_inc;
cparata	0:6d69e896ce38	1580
cparata	0:6d69e896ce38	1581	return ret;
cparata	0:6d69e896ce38	1582	}
cparata	0:6d69e896ce38	1583
cparata	0:6d69e896ce38	1584	/**
cparata	0:6d69e896ce38	1585	* @brief Reboot memory content. Reload the calibration parameters.[set]
cparata	0:6d69e896ce38	1586	*
cparata	0:6d69e896ce38	1587	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1588	* @param val change the values of boot in reg CTRL3_C
cparata	0:6d69e896ce38	1589	*
cparata	0:6d69e896ce38	1590	*/
cparata	0:6d69e896ce38	1591	int32_t lsm6dso_boot_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1592	{
cparata	0:6d69e896ce38	1593	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	1594	int32_t ret;
cparata	0:6d69e896ce38	1595
cparata	0:6d69e896ce38	1596	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1597	if (ret == 0) {
cparata	0:6d69e896ce38	1598	reg.boot = val;
cparata	0:6d69e896ce38	1599	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1600	}
cparata	0:6d69e896ce38	1601	return ret;
cparata	0:6d69e896ce38	1602	}
cparata	0:6d69e896ce38	1603
cparata	0:6d69e896ce38	1604	/**
cparata	0:6d69e896ce38	1605	* @brief Reboot memory content. Reload the calibration parameters.[get]
cparata	0:6d69e896ce38	1606	*
cparata	0:6d69e896ce38	1607	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1608	* @param val change the values of boot in reg CTRL3_C
cparata	0:6d69e896ce38	1609	*
cparata	0:6d69e896ce38	1610	*/
cparata	0:6d69e896ce38	1611	int32_t lsm6dso_boot_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1612	{
cparata	0:6d69e896ce38	1613	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	1614	int32_t ret;
cparata	0:6d69e896ce38	1615
cparata	0:6d69e896ce38	1616	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1617	*val = reg.boot;
cparata	0:6d69e896ce38	1618
cparata	0:6d69e896ce38	1619	return ret;
cparata	0:6d69e896ce38	1620	}
cparata	0:6d69e896ce38	1621
cparata	0:6d69e896ce38	1622	/**
cparata	0:6d69e896ce38	1623	* @brief Linear acceleration sensor self-test enable.[set]
cparata	0:6d69e896ce38	1624	*
cparata	0:6d69e896ce38	1625	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1626	* @param val change the values of st_xl in reg CTRL5_C
cparata	0:6d69e896ce38	1627	*
cparata	0:6d69e896ce38	1628	*/
cparata	0:6d69e896ce38	1629	int32_t lsm6dso_xl_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t val)
cparata	0:6d69e896ce38	1630	{
cparata	0:6d69e896ce38	1631	lsm6dso_ctrl5_c_t reg;
cparata	0:6d69e896ce38	1632	int32_t ret;
cparata	0:6d69e896ce38	1633
cparata	0:6d69e896ce38	1634	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1635	if (ret == 0) {
cparata	0:6d69e896ce38	1636	reg.st_xl = (uint8_t)val;
cparata	0:6d69e896ce38	1637	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1638	}
cparata	0:6d69e896ce38	1639	return ret;
cparata	0:6d69e896ce38	1640	}
cparata	0:6d69e896ce38	1641
cparata	0:6d69e896ce38	1642	/**
cparata	0:6d69e896ce38	1643	* @brief Linear acceleration sensor self-test enable.[get]
cparata	0:6d69e896ce38	1644	*
cparata	0:6d69e896ce38	1645	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1646	* @param val Get the values of st_xl in reg CTRL5_C
cparata	0:6d69e896ce38	1647	*
cparata	0:6d69e896ce38	1648	*/
cparata	0:6d69e896ce38	1649	int32_t lsm6dso_xl_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_xl_t val)
cparata	0:6d69e896ce38	1650	{
cparata	0:6d69e896ce38	1651	lsm6dso_ctrl5_c_t reg;
cparata	0:6d69e896ce38	1652	int32_t ret;
cparata	0:6d69e896ce38	1653
cparata	0:6d69e896ce38	1654	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1655	switch (reg.st_xl) {
cparata	0:6d69e896ce38	1656	case LSM6DSO_XL_ST_DISABLE:
cparata	0:6d69e896ce38	1657	*val = LSM6DSO_XL_ST_DISABLE;
cparata	0:6d69e896ce38	1658	break;
cparata	0:6d69e896ce38	1659	case LSM6DSO_XL_ST_POSITIVE:
cparata	0:6d69e896ce38	1660	*val = LSM6DSO_XL_ST_POSITIVE;
cparata	0:6d69e896ce38	1661	break;
cparata	0:6d69e896ce38	1662	case LSM6DSO_XL_ST_NEGATIVE:
cparata	0:6d69e896ce38	1663	*val = LSM6DSO_XL_ST_NEGATIVE;
cparata	0:6d69e896ce38	1664	break;
cparata	0:6d69e896ce38	1665	default:
cparata	0:6d69e896ce38	1666	*val = LSM6DSO_XL_ST_DISABLE;
cparata	0:6d69e896ce38	1667	break;
cparata	0:6d69e896ce38	1668	}
cparata	0:6d69e896ce38	1669	return ret;
cparata	0:6d69e896ce38	1670	}
cparata	0:6d69e896ce38	1671
cparata	0:6d69e896ce38	1672	/**
cparata	0:6d69e896ce38	1673	* @brief Angular rate sensor self-test enable.[set]
cparata	0:6d69e896ce38	1674	*
cparata	0:6d69e896ce38	1675	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1676	* @param val change the values of st_g in reg CTRL5_C
cparata	0:6d69e896ce38	1677	*
cparata	0:6d69e896ce38	1678	*/
cparata	0:6d69e896ce38	1679	int32_t lsm6dso_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t val)
cparata	0:6d69e896ce38	1680	{
cparata	0:6d69e896ce38	1681	lsm6dso_ctrl5_c_t reg;
cparata	0:6d69e896ce38	1682	int32_t ret;
cparata	0:6d69e896ce38	1683
cparata	0:6d69e896ce38	1684	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1685	if (ret == 0) {
cparata	0:6d69e896ce38	1686	reg.st_g = (uint8_t)val;
cparata	0:6d69e896ce38	1687	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1688	}
cparata	0:6d69e896ce38	1689	return ret;
cparata	0:6d69e896ce38	1690	}
cparata	0:6d69e896ce38	1691
cparata	0:6d69e896ce38	1692	/**
cparata	0:6d69e896ce38	1693	* @brief Angular rate sensor self-test enable.[get]
cparata	0:6d69e896ce38	1694	*
cparata	0:6d69e896ce38	1695	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1696	* @param val Get the values of st_g in reg CTRL5_C
cparata	0:6d69e896ce38	1697	*
cparata	0:6d69e896ce38	1698	*/
cparata	0:6d69e896ce38	1699	int32_t lsm6dso_gy_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_g_t val)
cparata	0:6d69e896ce38	1700	{
cparata	0:6d69e896ce38	1701	lsm6dso_ctrl5_c_t reg;
cparata	0:6d69e896ce38	1702	int32_t ret;
cparata	0:6d69e896ce38	1703
cparata	0:6d69e896ce38	1704	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1705	switch (reg.st_g) {
cparata	0:6d69e896ce38	1706	case LSM6DSO_GY_ST_DISABLE:
cparata	0:6d69e896ce38	1707	*val = LSM6DSO_GY_ST_DISABLE;
cparata	0:6d69e896ce38	1708	break;
cparata	0:6d69e896ce38	1709	case LSM6DSO_GY_ST_POSITIVE:
cparata	0:6d69e896ce38	1710	*val = LSM6DSO_GY_ST_POSITIVE;
cparata	0:6d69e896ce38	1711	break;
cparata	0:6d69e896ce38	1712	case LSM6DSO_GY_ST_NEGATIVE:
cparata	0:6d69e896ce38	1713	*val = LSM6DSO_GY_ST_NEGATIVE;
cparata	0:6d69e896ce38	1714	break;
cparata	0:6d69e896ce38	1715	default:
cparata	0:6d69e896ce38	1716	*val = LSM6DSO_GY_ST_DISABLE;
cparata	0:6d69e896ce38	1717	break;
cparata	0:6d69e896ce38	1718	}
cparata	0:6d69e896ce38	1719	return ret;
cparata	0:6d69e896ce38	1720	}
cparata	0:6d69e896ce38	1721
cparata	0:6d69e896ce38	1722	/**
cparata	0:6d69e896ce38	1723	* @}
cparata	0:6d69e896ce38	1724	*
cparata	0:6d69e896ce38	1725	*/
cparata	0:6d69e896ce38	1726
cparata	0:6d69e896ce38	1727	/**
cparata	0:6d69e896ce38	1728	* @defgroup LSM6DSO_filters
cparata	0:6d69e896ce38	1729	* @brief This section group all the functions concerning the
cparata	0:6d69e896ce38	1730	* filters configuration
cparata	0:6d69e896ce38	1731	* @{
cparata	0:6d69e896ce38	1732	*
cparata	0:6d69e896ce38	1733	*/
cparata	0:6d69e896ce38	1734
cparata	0:6d69e896ce38	1735	/**
cparata	0:6d69e896ce38	1736	* @brief Accelerometer output from LPF2 filtering stage selection.[set]
cparata	0:6d69e896ce38	1737	*
cparata	0:6d69e896ce38	1738	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1739	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:6d69e896ce38	1740	*
cparata	0:6d69e896ce38	1741	*/
cparata	0:6d69e896ce38	1742	int32_t lsm6dso_xl_filter_lp2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1743	{
cparata	0:6d69e896ce38	1744	lsm6dso_ctrl1_xl_t reg;
cparata	0:6d69e896ce38	1745	int32_t ret;
cparata	0:6d69e896ce38	1746
cparata	0:6d69e896ce38	1747	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1748	if (ret == 0) {
cparata	0:6d69e896ce38	1749	reg.lpf2_xl_en = val;
cparata	0:6d69e896ce38	1750	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1751	}
cparata	0:6d69e896ce38	1752	return ret;
cparata	0:6d69e896ce38	1753	}
cparata	0:6d69e896ce38	1754
cparata	0:6d69e896ce38	1755	/**
cparata	0:6d69e896ce38	1756	* @brief Accelerometer output from LPF2 filtering stage selection.[get]
cparata	0:6d69e896ce38	1757	*
cparata	0:6d69e896ce38	1758	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1759	* @param val change the values of lpf2_xl_en in reg CTRL1_XL
cparata	0:6d69e896ce38	1760	*
cparata	0:6d69e896ce38	1761	*/
cparata	0:6d69e896ce38	1762	int32_t lsm6dso_xl_filter_lp2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1763	{
cparata	0:6d69e896ce38	1764	lsm6dso_ctrl1_xl_t reg;
cparata	0:6d69e896ce38	1765	int32_t ret;
cparata	0:6d69e896ce38	1766
cparata	0:6d69e896ce38	1767	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1768	*val = reg.lpf2_xl_en;
cparata	0:6d69e896ce38	1769
cparata	0:6d69e896ce38	1770	return ret;
cparata	0:6d69e896ce38	1771	}
cparata	0:6d69e896ce38	1772
cparata	0:6d69e896ce38	1773	/**
cparata	0:6d69e896ce38	1774	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:6d69e896ce38	1775	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:6d69e896ce38	1776	* in CTRL6_C (15h).[set]
cparata	0:6d69e896ce38	1777	*
cparata	0:6d69e896ce38	1778	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1779	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:6d69e896ce38	1780	*
cparata	0:6d69e896ce38	1781	*/
cparata	0:6d69e896ce38	1782	int32_t lsm6dso_gy_filter_lp1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1783	{
cparata	0:6d69e896ce38	1784	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	1785	int32_t ret;
cparata	0:6d69e896ce38	1786
cparata	0:6d69e896ce38	1787	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1788	if (ret == 0) {
cparata	0:6d69e896ce38	1789	reg.lpf1_sel_g = val;
cparata	0:6d69e896ce38	1790	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1791	}
cparata	0:6d69e896ce38	1792	return ret;
cparata	0:6d69e896ce38	1793	}
cparata	0:6d69e896ce38	1794
cparata	0:6d69e896ce38	1795	/**
cparata	0:6d69e896ce38	1796	* @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
cparata	0:6d69e896ce38	1797	* the bandwidth can be selected through FTYPE [2:0]
cparata	0:6d69e896ce38	1798	* in CTRL6_C (15h).[get]
cparata	0:6d69e896ce38	1799	*
cparata	0:6d69e896ce38	1800	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1801	* @param val change the values of lpf1_sel_g in reg CTRL4_C
cparata	0:6d69e896ce38	1802	*
cparata	0:6d69e896ce38	1803	*/
cparata	0:6d69e896ce38	1804	int32_t lsm6dso_gy_filter_lp1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1805	{
cparata	0:6d69e896ce38	1806	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	1807	int32_t ret;
cparata	0:6d69e896ce38	1808
cparata	0:6d69e896ce38	1809	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1810	*val = reg.lpf1_sel_g;
cparata	0:6d69e896ce38	1811
cparata	0:6d69e896ce38	1812	return ret;
cparata	0:6d69e896ce38	1813	}
cparata	0:6d69e896ce38	1814
cparata	0:6d69e896ce38	1815	/**
cparata	0:6d69e896ce38	1816	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:6d69e896ce38	1817	* (XL and Gyro independently masked).[set]
cparata	0:6d69e896ce38	1818	*
cparata	0:6d69e896ce38	1819	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1820	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:6d69e896ce38	1821	*
cparata	0:6d69e896ce38	1822	*/
cparata	0:6d69e896ce38	1823	int32_t lsm6dso_filter_settling_mask_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1824	{
cparata	0:6d69e896ce38	1825	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	1826	int32_t ret;
cparata	0:6d69e896ce38	1827
cparata	0:6d69e896ce38	1828	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1829	if (ret == 0) {
cparata	0:6d69e896ce38	1830	reg.drdy_mask = val;
cparata	0:6d69e896ce38	1831	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1832	}
cparata	0:6d69e896ce38	1833	return ret;
cparata	0:6d69e896ce38	1834	}
cparata	0:6d69e896ce38	1835
cparata	0:6d69e896ce38	1836	/**
cparata	0:6d69e896ce38	1837	* @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
cparata	0:6d69e896ce38	1838	* (XL and Gyro independently masked).[get]
cparata	0:6d69e896ce38	1839	*
cparata	0:6d69e896ce38	1840	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1841	* @param val change the values of drdy_mask in reg CTRL4_C
cparata	0:6d69e896ce38	1842	*
cparata	0:6d69e896ce38	1843	*/
cparata	0:6d69e896ce38	1844	int32_t lsm6dso_filter_settling_mask_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1845	{
cparata	0:6d69e896ce38	1846	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	1847	int32_t ret;
cparata	0:6d69e896ce38	1848
cparata	0:6d69e896ce38	1849	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1850	*val = reg.drdy_mask;
cparata	0:6d69e896ce38	1851
cparata	0:6d69e896ce38	1852	return ret;
cparata	0:6d69e896ce38	1853	}
cparata	0:6d69e896ce38	1854
cparata	0:6d69e896ce38	1855	/**
cparata	0:6d69e896ce38	1856	* @brief Gyroscope lp1 bandwidth.[set]
cparata	0:6d69e896ce38	1857	*
cparata	0:6d69e896ce38	1858	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1859	* @param val change the values of ftype in reg CTRL6_C
cparata	0:6d69e896ce38	1860	*
cparata	0:6d69e896ce38	1861	*/
cparata	0:6d69e896ce38	1862	int32_t lsm6dso_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, lsm6dso_ftype_t val)
cparata	0:6d69e896ce38	1863	{
cparata	0:6d69e896ce38	1864	lsm6dso_ctrl6_c_t reg;
cparata	0:6d69e896ce38	1865	int32_t ret;
cparata	0:6d69e896ce38	1866
cparata	0:6d69e896ce38	1867	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1868	if (ret == 0) {
cparata	0:6d69e896ce38	1869	reg.ftype = (uint8_t)val;
cparata	0:6d69e896ce38	1870	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1871	}
cparata	0:6d69e896ce38	1872	return ret;
cparata	0:6d69e896ce38	1873	}
cparata	0:6d69e896ce38	1874
cparata	0:6d69e896ce38	1875	/**
cparata	0:6d69e896ce38	1876	* @brief Gyroscope lp1 bandwidth.[get]
cparata	0:6d69e896ce38	1877	*
cparata	0:6d69e896ce38	1878	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1879	* @param val Get the values of ftype in reg CTRL6_C
cparata	0:6d69e896ce38	1880	*
cparata	0:6d69e896ce38	1881	*/
cparata	0:6d69e896ce38	1882	int32_t lsm6dso_gy_lp1_bandwidth_get(lsm6dso_ctx_t ctx, lsm6dso_ftype_t val)
cparata	0:6d69e896ce38	1883	{
cparata	0:6d69e896ce38	1884	lsm6dso_ctrl6_c_t reg;
cparata	0:6d69e896ce38	1885	int32_t ret;
cparata	0:6d69e896ce38	1886
cparata	0:6d69e896ce38	1887	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1888	switch (reg.ftype) {
cparata	0:6d69e896ce38	1889	case LSM6DSO_ULTRA_LIGHT:
cparata	0:6d69e896ce38	1890	*val = LSM6DSO_ULTRA_LIGHT;
cparata	0:6d69e896ce38	1891	break;
cparata	0:6d69e896ce38	1892	case LSM6DSO_VERY_LIGHT:
cparata	0:6d69e896ce38	1893	*val = LSM6DSO_VERY_LIGHT;
cparata	0:6d69e896ce38	1894	break;
cparata	0:6d69e896ce38	1895	case LSM6DSO_LIGHT:
cparata	0:6d69e896ce38	1896	*val = LSM6DSO_LIGHT;
cparata	0:6d69e896ce38	1897	break;
cparata	0:6d69e896ce38	1898	case LSM6DSO_MEDIUM:
cparata	0:6d69e896ce38	1899	*val = LSM6DSO_MEDIUM;
cparata	0:6d69e896ce38	1900	break;
cparata	0:6d69e896ce38	1901	case LSM6DSO_STRONG:
cparata	0:6d69e896ce38	1902	*val = LSM6DSO_STRONG;
cparata	0:6d69e896ce38	1903	break;
cparata	0:6d69e896ce38	1904	case LSM6DSO_VERY_STRONG:
cparata	0:6d69e896ce38	1905	*val = LSM6DSO_VERY_STRONG;
cparata	0:6d69e896ce38	1906	break;
cparata	0:6d69e896ce38	1907	case LSM6DSO_AGGRESSIVE:
cparata	0:6d69e896ce38	1908	*val = LSM6DSO_AGGRESSIVE;
cparata	0:6d69e896ce38	1909	break;
cparata	0:6d69e896ce38	1910	case LSM6DSO_XTREME:
cparata	0:6d69e896ce38	1911	*val = LSM6DSO_XTREME;
cparata	0:6d69e896ce38	1912	break;
cparata	0:6d69e896ce38	1913	default:
cparata	0:6d69e896ce38	1914	*val = LSM6DSO_ULTRA_LIGHT;
cparata	0:6d69e896ce38	1915	break;
cparata	0:6d69e896ce38	1916	}
cparata	0:6d69e896ce38	1917	return ret;
cparata	0:6d69e896ce38	1918	}
cparata	0:6d69e896ce38	1919
cparata	0:6d69e896ce38	1920	/**
cparata	0:6d69e896ce38	1921	* @brief Low pass filter 2 on 6D function selection.[set]
cparata	0:6d69e896ce38	1922	*
cparata	0:6d69e896ce38	1923	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1924	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:6d69e896ce38	1925	*
cparata	0:6d69e896ce38	1926	*/
cparata	0:6d69e896ce38	1927	int32_t lsm6dso_xl_lp2_on_6d_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	1928	{
cparata	0:6d69e896ce38	1929	lsm6dso_ctrl8_xl_t reg;
cparata	0:6d69e896ce38	1930	int32_t ret;
cparata	0:6d69e896ce38	1931
cparata	0:6d69e896ce38	1932	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1933	if (ret == 0) {
cparata	0:6d69e896ce38	1934	reg.low_pass_on_6d = val;
cparata	0:6d69e896ce38	1935	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1936	}
cparata	0:6d69e896ce38	1937	return ret;
cparata	0:6d69e896ce38	1938	}
cparata	0:6d69e896ce38	1939
cparata	0:6d69e896ce38	1940	/**
cparata	0:6d69e896ce38	1941	* @brief Low pass filter 2 on 6D function selection.[get]
cparata	0:6d69e896ce38	1942	*
cparata	0:6d69e896ce38	1943	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1944	* @param val change the values of low_pass_on_6d in reg CTRL8_XL
cparata	0:6d69e896ce38	1945	*
cparata	0:6d69e896ce38	1946	*/
cparata	0:6d69e896ce38	1947	int32_t lsm6dso_xl_lp2_on_6d_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	1948	{
cparata	0:6d69e896ce38	1949	lsm6dso_ctrl8_xl_t reg;
cparata	0:6d69e896ce38	1950	int32_t ret;
cparata	0:6d69e896ce38	1951
cparata	0:6d69e896ce38	1952	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1953	*val = reg.low_pass_on_6d;
cparata	0:6d69e896ce38	1954
cparata	0:6d69e896ce38	1955	return ret;
cparata	0:6d69e896ce38	1956	}
cparata	0:6d69e896ce38	1957
cparata	0:6d69e896ce38	1958	/**
cparata	0:6d69e896ce38	1959	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:6d69e896ce38	1960	* on output.[set]
cparata	0:6d69e896ce38	1961	*
cparata	0:6d69e896ce38	1962	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1963	* @param val change the values of hp_slope_xl_en
cparata	0:6d69e896ce38	1964	* in reg CTRL8_XL
cparata	0:6d69e896ce38	1965	*
cparata	0:6d69e896ce38	1966	*/
cparata	0:6d69e896ce38	1967	int32_t lsm6dso_xl_hp_path_on_out_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1968	lsm6dso_hp_slope_xl_en_t val)
cparata	0:6d69e896ce38	1969	{
cparata	0:6d69e896ce38	1970	lsm6dso_ctrl8_xl_t reg;
cparata	0:6d69e896ce38	1971	int32_t ret;
cparata	0:6d69e896ce38	1972
cparata	0:6d69e896ce38	1973	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1974	if (ret == 0) {
cparata	0:6d69e896ce38	1975	reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
cparata	0:6d69e896ce38	1976	reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
cparata	0:6d69e896ce38	1977	reg.hpcf_xl = (uint8_t)val & 0x07U;
cparata	0:6d69e896ce38	1978	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1979	}
cparata	0:6d69e896ce38	1980	return ret;
cparata	0:6d69e896ce38	1981	}
cparata	0:6d69e896ce38	1982
cparata	0:6d69e896ce38	1983	/**
cparata	0:6d69e896ce38	1984	* @brief Accelerometer slope filter / high-pass filter selection
cparata	0:6d69e896ce38	1985	* on output.[get]
cparata	0:6d69e896ce38	1986	*
cparata	0:6d69e896ce38	1987	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	1988	* @param val Get the values of hp_slope_xl_en
cparata	0:6d69e896ce38	1989	* in reg CTRL8_XL
cparata	0:6d69e896ce38	1990	*
cparata	0:6d69e896ce38	1991	*/
cparata	0:6d69e896ce38	1992	int32_t lsm6dso_xl_hp_path_on_out_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	1993	lsm6dso_hp_slope_xl_en_t *val)
cparata	0:6d69e896ce38	1994	{
cparata	0:6d69e896ce38	1995	lsm6dso_ctrl8_xl_t reg;
cparata	0:6d69e896ce38	1996	int32_t ret;
cparata	0:6d69e896ce38	1997
cparata	0:6d69e896ce38	1998	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	1999	switch ((reg.hp_ref_mode_xl << 5) \| (reg.hp_slope_xl_en << 4) \|
cparata	0:6d69e896ce38	2000	reg.hpcf_xl) {
cparata	0:6d69e896ce38	2001	case LSM6DSO_HP_PATH_DISABLE_ON_OUT:
cparata	0:6d69e896ce38	2002	*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
cparata	0:6d69e896ce38	2003	break;
cparata	0:6d69e896ce38	2004	case LSM6DSO_SLOPE_ODR_DIV_4:
cparata	0:6d69e896ce38	2005	*val = LSM6DSO_SLOPE_ODR_DIV_4;
cparata	0:6d69e896ce38	2006	break;
cparata	0:6d69e896ce38	2007	case LSM6DSO_HP_ODR_DIV_10:
cparata	0:6d69e896ce38	2008	*val = LSM6DSO_HP_ODR_DIV_10;
cparata	0:6d69e896ce38	2009	break;
cparata	0:6d69e896ce38	2010	case LSM6DSO_HP_ODR_DIV_20:
cparata	0:6d69e896ce38	2011	*val = LSM6DSO_HP_ODR_DIV_20;
cparata	0:6d69e896ce38	2012	break;
cparata	0:6d69e896ce38	2013	case LSM6DSO_HP_ODR_DIV_45:
cparata	0:6d69e896ce38	2014	*val = LSM6DSO_HP_ODR_DIV_45;
cparata	0:6d69e896ce38	2015	break;
cparata	0:6d69e896ce38	2016	case LSM6DSO_HP_ODR_DIV_100:
cparata	0:6d69e896ce38	2017	*val = LSM6DSO_HP_ODR_DIV_100;
cparata	0:6d69e896ce38	2018	break;
cparata	0:6d69e896ce38	2019	case LSM6DSO_HP_ODR_DIV_200:
cparata	0:6d69e896ce38	2020	*val = LSM6DSO_HP_ODR_DIV_200;
cparata	0:6d69e896ce38	2021	break;
cparata	0:6d69e896ce38	2022	case LSM6DSO_HP_ODR_DIV_400:
cparata	0:6d69e896ce38	2023	*val = LSM6DSO_HP_ODR_DIV_400;
cparata	0:6d69e896ce38	2024	break;
cparata	0:6d69e896ce38	2025	case LSM6DSO_HP_ODR_DIV_800:
cparata	0:6d69e896ce38	2026	*val = LSM6DSO_HP_ODR_DIV_800;
cparata	0:6d69e896ce38	2027	break;
cparata	0:6d69e896ce38	2028	case LSM6DSO_HP_REF_MD_ODR_DIV_10:
cparata	0:6d69e896ce38	2029	*val = LSM6DSO_HP_REF_MD_ODR_DIV_10;
cparata	0:6d69e896ce38	2030	break;
cparata	0:6d69e896ce38	2031	case LSM6DSO_HP_REF_MD_ODR_DIV_20:
cparata	0:6d69e896ce38	2032	*val = LSM6DSO_HP_REF_MD_ODR_DIV_20;
cparata	0:6d69e896ce38	2033	break;
cparata	0:6d69e896ce38	2034	case LSM6DSO_HP_REF_MD_ODR_DIV_45:
cparata	0:6d69e896ce38	2035	*val = LSM6DSO_HP_REF_MD_ODR_DIV_45;
cparata	0:6d69e896ce38	2036	break;
cparata	0:6d69e896ce38	2037	case LSM6DSO_HP_REF_MD_ODR_DIV_100:
cparata	0:6d69e896ce38	2038	*val = LSM6DSO_HP_REF_MD_ODR_DIV_100;
cparata	0:6d69e896ce38	2039	break;
cparata	0:6d69e896ce38	2040	case LSM6DSO_HP_REF_MD_ODR_DIV_200:
cparata	0:6d69e896ce38	2041	*val = LSM6DSO_HP_REF_MD_ODR_DIV_200;
cparata	0:6d69e896ce38	2042	break;
cparata	0:6d69e896ce38	2043	case LSM6DSO_HP_REF_MD_ODR_DIV_400:
cparata	0:6d69e896ce38	2044	*val = LSM6DSO_HP_REF_MD_ODR_DIV_400;
cparata	0:6d69e896ce38	2045	break;
cparata	0:6d69e896ce38	2046	case LSM6DSO_HP_REF_MD_ODR_DIV_800:
cparata	0:6d69e896ce38	2047	*val = LSM6DSO_HP_REF_MD_ODR_DIV_800;
cparata	0:6d69e896ce38	2048	break;
cparata	0:6d69e896ce38	2049	case LSM6DSO_LP_ODR_DIV_10:
cparata	0:6d69e896ce38	2050	*val = LSM6DSO_LP_ODR_DIV_10;
cparata	0:6d69e896ce38	2051	break;
cparata	0:6d69e896ce38	2052	case LSM6DSO_LP_ODR_DIV_20:
cparata	0:6d69e896ce38	2053	*val = LSM6DSO_LP_ODR_DIV_20;
cparata	0:6d69e896ce38	2054	break;
cparata	0:6d69e896ce38	2055	case LSM6DSO_LP_ODR_DIV_45:
cparata	0:6d69e896ce38	2056	*val = LSM6DSO_LP_ODR_DIV_45;
cparata	0:6d69e896ce38	2057	break;
cparata	0:6d69e896ce38	2058	case LSM6DSO_LP_ODR_DIV_100:
cparata	0:6d69e896ce38	2059	*val = LSM6DSO_LP_ODR_DIV_100;
cparata	0:6d69e896ce38	2060	break;
cparata	0:6d69e896ce38	2061	case LSM6DSO_LP_ODR_DIV_200:
cparata	0:6d69e896ce38	2062	*val = LSM6DSO_LP_ODR_DIV_200;
cparata	0:6d69e896ce38	2063	break;
cparata	0:6d69e896ce38	2064	case LSM6DSO_LP_ODR_DIV_400:
cparata	0:6d69e896ce38	2065	*val = LSM6DSO_LP_ODR_DIV_400;
cparata	0:6d69e896ce38	2066	break;
cparata	0:6d69e896ce38	2067	case LSM6DSO_LP_ODR_DIV_800:
cparata	0:6d69e896ce38	2068	*val = LSM6DSO_LP_ODR_DIV_800;
cparata	0:6d69e896ce38	2069	break;
cparata	0:6d69e896ce38	2070	default:
cparata	0:6d69e896ce38	2071	*val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
cparata	0:6d69e896ce38	2072	break;
cparata	0:6d69e896ce38	2073	}
cparata	0:6d69e896ce38	2074
cparata	0:6d69e896ce38	2075	return ret;
cparata	0:6d69e896ce38	2076	}
cparata	0:6d69e896ce38	2077
cparata	0:6d69e896ce38	2078	/**
cparata	0:6d69e896ce38	2079	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:6d69e896ce38	2080	* The filter sets the second samples after writing this bit.
cparata	0:6d69e896ce38	2081	* Active only during device exit from power-down mode.[set]
cparata	0:6d69e896ce38	2082	*
cparata	0:6d69e896ce38	2083	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2084	* @param val change the values of fastsettl_mode_xl in
cparata	0:6d69e896ce38	2085	* reg CTRL8_XL
cparata	0:6d69e896ce38	2086	*
cparata	0:6d69e896ce38	2087	*/
cparata	0:6d69e896ce38	2088	int32_t lsm6dso_xl_fast_settling_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2089	{
cparata	0:6d69e896ce38	2090	lsm6dso_ctrl8_xl_t reg;
cparata	0:6d69e896ce38	2091	int32_t ret;
cparata	0:6d69e896ce38	2092
cparata	0:6d69e896ce38	2093	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2094	if (ret == 0) {
cparata	0:6d69e896ce38	2095	reg.fastsettl_mode_xl = val;
cparata	0:6d69e896ce38	2096	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2097	}
cparata	0:6d69e896ce38	2098	return ret;
cparata	0:6d69e896ce38	2099	}
cparata	0:6d69e896ce38	2100
cparata	0:6d69e896ce38	2101	/**
cparata	0:6d69e896ce38	2102	* @brief Enables accelerometer LPF2 and HPF fast-settling mode.
cparata	0:6d69e896ce38	2103	* The filter sets the second samples after writing this bit.
cparata	0:6d69e896ce38	2104	* Active only during device exit from power-down mode.[get]
cparata	0:6d69e896ce38	2105	*
cparata	0:6d69e896ce38	2106	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2107	* @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
cparata	0:6d69e896ce38	2108	*
cparata	0:6d69e896ce38	2109	*/
cparata	0:6d69e896ce38	2110	int32_t lsm6dso_xl_fast_settling_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2111	{
cparata	0:6d69e896ce38	2112	lsm6dso_ctrl8_xl_t reg;
cparata	0:6d69e896ce38	2113	int32_t ret;
cparata	0:6d69e896ce38	2114
cparata	0:6d69e896ce38	2115	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2116	*val = reg.fastsettl_mode_xl;
cparata	0:6d69e896ce38	2117
cparata	0:6d69e896ce38	2118	return ret;
cparata	0:6d69e896ce38	2119	}
cparata	0:6d69e896ce38	2120
cparata	0:6d69e896ce38	2121	/**
cparata	0:6d69e896ce38	2122	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:6d69e896ce38	2123	* functions.[set]
cparata	0:6d69e896ce38	2124	*
cparata	0:6d69e896ce38	2125	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2126	* @param val change the values of slope_fds in reg TAP_CFG0
cparata	0:6d69e896ce38	2127	*
cparata	0:6d69e896ce38	2128	*/
cparata	0:6d69e896ce38	2129	int32_t lsm6dso_xl_hp_path_internal_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2130	lsm6dso_slope_fds_t val)
cparata	0:6d69e896ce38	2131	{
cparata	0:6d69e896ce38	2132	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	2133	int32_t ret;
cparata	0:6d69e896ce38	2134
cparata	0:6d69e896ce38	2135	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2136	if (ret == 0) {
cparata	0:6d69e896ce38	2137	reg.slope_fds = (uint8_t)val;
cparata	0:6d69e896ce38	2138	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2139	}
cparata	0:6d69e896ce38	2140	return ret;
cparata	0:6d69e896ce38	2141	}
cparata	0:6d69e896ce38	2142
cparata	0:6d69e896ce38	2143	/**
cparata	0:6d69e896ce38	2144	* @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
cparata	0:6d69e896ce38	2145	* functions.[get]
cparata	0:6d69e896ce38	2146	*
cparata	0:6d69e896ce38	2147	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2148	* @param val Get the values of slope_fds in reg TAP_CFG0
cparata	0:6d69e896ce38	2149	*
cparata	0:6d69e896ce38	2150	*/
cparata	0:6d69e896ce38	2151	int32_t lsm6dso_xl_hp_path_internal_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2152	lsm6dso_slope_fds_t *val)
cparata	0:6d69e896ce38	2153	{
cparata	0:6d69e896ce38	2154	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	2155	int32_t ret;
cparata	0:6d69e896ce38	2156
cparata	0:6d69e896ce38	2157	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2158	switch (reg.slope_fds) {
cparata	0:6d69e896ce38	2159	case LSM6DSO_USE_SLOPE:
cparata	0:6d69e896ce38	2160	*val = LSM6DSO_USE_SLOPE;
cparata	0:6d69e896ce38	2161	break;
cparata	0:6d69e896ce38	2162	case LSM6DSO_USE_HPF:
cparata	0:6d69e896ce38	2163	*val = LSM6DSO_USE_HPF;
cparata	0:6d69e896ce38	2164	break;
cparata	0:6d69e896ce38	2165	default:
cparata	0:6d69e896ce38	2166	*val = LSM6DSO_USE_SLOPE;
cparata	0:6d69e896ce38	2167	break;
cparata	0:6d69e896ce38	2168	}
cparata	0:6d69e896ce38	2169	return ret;
cparata	0:6d69e896ce38	2170	}
cparata	0:6d69e896ce38	2171
cparata	0:6d69e896ce38	2172	/**
cparata	0:6d69e896ce38	2173	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:6d69e896ce38	2174	* enabled only if the gyro is in HP mode.[set]
cparata	0:6d69e896ce38	2175	*
cparata	0:6d69e896ce38	2176	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2177	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:6d69e896ce38	2178	* in reg CTRL7_G
cparata	0:6d69e896ce38	2179	*
cparata	0:6d69e896ce38	2180	*/
cparata	0:6d69e896ce38	2181	int32_t lsm6dso_gy_hp_path_internal_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2182	lsm6dso_hpm_g_t val)
cparata	0:6d69e896ce38	2183	{
cparata	0:6d69e896ce38	2184	lsm6dso_ctrl7_g_t reg;
cparata	0:6d69e896ce38	2185	int32_t ret;
cparata	0:6d69e896ce38	2186
cparata	0:6d69e896ce38	2187	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2188	if (ret == 0) {
cparata	0:6d69e896ce38	2189	reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
cparata	0:6d69e896ce38	2190	reg.hpm_g = (uint8_t)val & 0x03U;
cparata	0:6d69e896ce38	2191	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2192	}
cparata	0:6d69e896ce38	2193	return ret;
cparata	0:6d69e896ce38	2194	}
cparata	0:6d69e896ce38	2195
cparata	0:6d69e896ce38	2196	/**
cparata	0:6d69e896ce38	2197	* @brief Enables gyroscope digital high-pass filter. The filter is
cparata	0:6d69e896ce38	2198	* enabled only if the gyro is in HP mode.[get]
cparata	0:6d69e896ce38	2199	*
cparata	0:6d69e896ce38	2200	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2201	* @param val Get the values of hp_en_g and hp_en_g
cparata	0:6d69e896ce38	2202	* in reg CTRL7_G
cparata	0:6d69e896ce38	2203	*
cparata	0:6d69e896ce38	2204	*/
cparata	0:6d69e896ce38	2205	int32_t lsm6dso_gy_hp_path_internal_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2206	lsm6dso_hpm_g_t *val)
cparata	0:6d69e896ce38	2207	{
cparata	0:6d69e896ce38	2208	lsm6dso_ctrl7_g_t reg;
cparata	0:6d69e896ce38	2209	int32_t ret;
cparata	0:6d69e896ce38	2210
cparata	0:6d69e896ce38	2211	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2212	switch ((reg.hp_en_g << 7) + reg.hpm_g) {
cparata	0:6d69e896ce38	2213	case LSM6DSO_HP_FILTER_NONE:
cparata	0:6d69e896ce38	2214	*val = LSM6DSO_HP_FILTER_NONE;
cparata	0:6d69e896ce38	2215	break;
cparata	0:6d69e896ce38	2216	case LSM6DSO_HP_FILTER_16mHz:
cparata	0:6d69e896ce38	2217	*val = LSM6DSO_HP_FILTER_16mHz;
cparata	0:6d69e896ce38	2218	break;
cparata	0:6d69e896ce38	2219	case LSM6DSO_HP_FILTER_65mHz:
cparata	0:6d69e896ce38	2220	*val = LSM6DSO_HP_FILTER_65mHz;
cparata	0:6d69e896ce38	2221	break;
cparata	0:6d69e896ce38	2222	case LSM6DSO_HP_FILTER_260mHz:
cparata	0:6d69e896ce38	2223	*val = LSM6DSO_HP_FILTER_260mHz;
cparata	0:6d69e896ce38	2224	break;
cparata	0:6d69e896ce38	2225	case LSM6DSO_HP_FILTER_1Hz04:
cparata	0:6d69e896ce38	2226	*val = LSM6DSO_HP_FILTER_1Hz04;
cparata	0:6d69e896ce38	2227	break;
cparata	0:6d69e896ce38	2228	default:
cparata	0:6d69e896ce38	2229	*val = LSM6DSO_HP_FILTER_NONE;
cparata	0:6d69e896ce38	2230	break;
cparata	0:6d69e896ce38	2231	}
cparata	0:6d69e896ce38	2232	return ret;
cparata	0:6d69e896ce38	2233	}
cparata	0:6d69e896ce38	2234
cparata	0:6d69e896ce38	2235	/**
cparata	0:6d69e896ce38	2236	* @}
cparata	0:6d69e896ce38	2237	*
cparata	0:6d69e896ce38	2238	*/
cparata	0:6d69e896ce38	2239
cparata	0:6d69e896ce38	2240	/**
cparata	0:6d69e896ce38	2241	* @defgroup LSM6DSO_ Auxiliary_interface
cparata	0:6d69e896ce38	2242	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	2243	* auxiliary interface.
cparata	0:6d69e896ce38	2244	* @{
cparata	0:6d69e896ce38	2245	*
cparata	0:6d69e896ce38	2246	*/
cparata	0:6d69e896ce38	2247
cparata	0:6d69e896ce38	2248	/**
cparata	0:6d69e896ce38	2249	* @brief aOn auxiliary interface connect/disconnect SDO and OCS
cparata	0:6d69e896ce38	2250	* internal pull-up.[set]
cparata	0:6d69e896ce38	2251	*
cparata	0:6d69e896ce38	2252	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2253	* @param val change the values of ois_pu_dis in
cparata	0:6d69e896ce38	2254	* reg PIN_CTRL
cparata	0:6d69e896ce38	2255	*
cparata	0:6d69e896ce38	2256	*/
cparata	0:6d69e896ce38	2257	int32_t lsm6dso_aux_sdo_ocs_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2258	lsm6dso_ois_pu_dis_t val)
cparata	0:6d69e896ce38	2259	{
cparata	0:6d69e896ce38	2260	lsm6dso_pin_ctrl_t reg;
cparata	0:6d69e896ce38	2261	int32_t ret;
cparata	0:6d69e896ce38	2262
cparata	0:6d69e896ce38	2263	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2264	if (ret == 0) {
cparata	0:6d69e896ce38	2265	reg.ois_pu_dis = (uint8_t)val;
cparata	0:6d69e896ce38	2266	ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2267	}
cparata	0:6d69e896ce38	2268	return ret;
cparata	0:6d69e896ce38	2269	}
cparata	0:6d69e896ce38	2270
cparata	0:6d69e896ce38	2271	/**
cparata	0:6d69e896ce38	2272	* @brief On auxiliary interface connect/disconnect SDO and OCS
cparata	0:6d69e896ce38	2273	* internal pull-up.[get]
cparata	0:6d69e896ce38	2274	*
cparata	0:6d69e896ce38	2275	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2276	* @param val Get the values of ois_pu_dis in reg PIN_CTRL
cparata	0:6d69e896ce38	2277	*
cparata	0:6d69e896ce38	2278	*/
cparata	0:6d69e896ce38	2279	int32_t lsm6dso_aux_sdo_ocs_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2280	lsm6dso_ois_pu_dis_t *val)
cparata	0:6d69e896ce38	2281	{
cparata	0:6d69e896ce38	2282	lsm6dso_pin_ctrl_t reg;
cparata	0:6d69e896ce38	2283	int32_t ret;
cparata	0:6d69e896ce38	2284
cparata	0:6d69e896ce38	2285	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2286	switch (reg.ois_pu_dis) {
cparata	0:6d69e896ce38	2287	case LSM6DSO_AUX_PULL_UP_DISC:
cparata	0:6d69e896ce38	2288	*val = LSM6DSO_AUX_PULL_UP_DISC;
cparata	0:6d69e896ce38	2289	break;
cparata	0:6d69e896ce38	2290	case LSM6DSO_AUX_PULL_UP_CONNECT:
cparata	0:6d69e896ce38	2291	*val = LSM6DSO_AUX_PULL_UP_CONNECT;
cparata	0:6d69e896ce38	2292	break;
cparata	0:6d69e896ce38	2293	default:
cparata	0:6d69e896ce38	2294	*val = LSM6DSO_AUX_PULL_UP_DISC;
cparata	0:6d69e896ce38	2295	break;
cparata	0:6d69e896ce38	2296	}
cparata	0:6d69e896ce38	2297	return ret;
cparata	0:6d69e896ce38	2298	}
cparata	0:6d69e896ce38	2299
cparata	0:6d69e896ce38	2300	/**
cparata	0:6d69e896ce38	2301	* @brief OIS chain on aux interface power on mode.[set]
cparata	0:6d69e896ce38	2302	*
cparata	0:6d69e896ce38	2303	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2304	* @param val change the values of ois_on in reg CTRL7_G
cparata	0:6d69e896ce38	2305	*
cparata	0:6d69e896ce38	2306	*/
cparata	0:6d69e896ce38	2307	int32_t lsm6dso_aux_pw_on_ctrl_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t val)
cparata	0:6d69e896ce38	2308	{
cparata	0:6d69e896ce38	2309	lsm6dso_ctrl7_g_t reg;
cparata	0:6d69e896ce38	2310	int32_t ret;
cparata	0:6d69e896ce38	2311
cparata	0:6d69e896ce38	2312	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2313	if (ret == 0) {
cparata	0:6d69e896ce38	2314	reg.ois_on_en = (uint8_t)val & 0x01U;
cparata	0:6d69e896ce38	2315	reg.ois_on = (uint8_t)val & 0x01U;
cparata	0:6d69e896ce38	2316	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2317	}
cparata	0:6d69e896ce38	2318	return ret;
cparata	0:6d69e896ce38	2319	}
cparata	0:6d69e896ce38	2320
cparata	0:6d69e896ce38	2321	/**
cparata	0:6d69e896ce38	2322	* @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode
cparata	0:6d69e896ce38	2323	*
cparata	0:6d69e896ce38	2324	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2325	* @param val Get the values of ois_on in reg CTRL7_G
cparata	0:6d69e896ce38	2326	*
cparata	0:6d69e896ce38	2327	*/
cparata	0:6d69e896ce38	2328	int32_t lsm6dso_aux_pw_on_ctrl_get(lsm6dso_ctx_t ctx, lsm6dso_ois_on_t val)
cparata	0:6d69e896ce38	2329	{
cparata	0:6d69e896ce38	2330	lsm6dso_ctrl7_g_t reg;
cparata	0:6d69e896ce38	2331	int32_t ret;
cparata	0:6d69e896ce38	2332
cparata	0:6d69e896ce38	2333	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2334	switch (reg.ois_on) {
cparata	0:6d69e896ce38	2335	case LSM6DSO_AUX_ON:
cparata	0:6d69e896ce38	2336	*val = LSM6DSO_AUX_ON;
cparata	0:6d69e896ce38	2337	break;
cparata	0:6d69e896ce38	2338	case LSM6DSO_AUX_ON_BY_AUX_INTERFACE:
cparata	0:6d69e896ce38	2339	*val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE;
cparata	0:6d69e896ce38	2340	break;
cparata	0:6d69e896ce38	2341	default:
cparata	0:6d69e896ce38	2342	*val = LSM6DSO_AUX_ON;
cparata	0:6d69e896ce38	2343	break;
cparata	0:6d69e896ce38	2344	}
cparata	0:6d69e896ce38	2345
cparata	0:6d69e896ce38	2346	return ret;
cparata	0:6d69e896ce38	2347	}
cparata	0:6d69e896ce38	2348
cparata	0:6d69e896ce38	2349	/**
cparata	0:6d69e896ce38	2350	* @brief Accelerometer full-scale management between UI chain and
cparata	0:6d69e896ce38	2351	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:6d69e896ce38	2352	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:6d69e896ce38	2353	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:6d69e896ce38	2354	* Full scales are independent between the UI/OIS chain
cparata	0:6d69e896ce38	2355	* but both bound to 8 g.[set]
cparata	0:6d69e896ce38	2356	*
cparata	0:6d69e896ce38	2357	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2358	* @param val change the values of xl_fs_mode in
cparata	0:6d69e896ce38	2359	* reg CTRL8_XL
cparata	0:6d69e896ce38	2360	*
cparata	0:6d69e896ce38	2361	*/
cparata	0:6d69e896ce38	2362	int32_t lsm6dso_aux_xl_fs_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2363	lsm6dso_xl_fs_mode_t val)
cparata	0:6d69e896ce38	2364	{
cparata	0:6d69e896ce38	2365	lsm6dso_ctrl8_xl_t reg;
cparata	0:6d69e896ce38	2366	int32_t ret;
cparata	0:6d69e896ce38	2367
cparata	0:6d69e896ce38	2368	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2369	if (ret == 0) {
cparata	0:6d69e896ce38	2370	reg.xl_fs_mode = (uint8_t)val;
cparata	0:6d69e896ce38	2371	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2372	}
cparata	0:6d69e896ce38	2373	return ret;
cparata	0:6d69e896ce38	2374	}
cparata	0:6d69e896ce38	2375
cparata	0:6d69e896ce38	2376	/**
cparata	0:6d69e896ce38	2377	* @brief Accelerometer full-scale management between UI chain and
cparata	0:6d69e896ce38	2378	* OIS chain. When XL UI is on, the full scale is the same
cparata	0:6d69e896ce38	2379	* between UI/OIS and is chosen by the UI CTRL registers;
cparata	0:6d69e896ce38	2380	* when XL UI is in PD, the OIS can choose the FS.
cparata	0:6d69e896ce38	2381	* Full scales are independent between the UI/OIS chain
cparata	0:6d69e896ce38	2382	* but both bound to 8 g.[get]
cparata	0:6d69e896ce38	2383	*
cparata	0:6d69e896ce38	2384	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2385	* @param val Get the values of xl_fs_mode in reg CTRL8_XL
cparata	0:6d69e896ce38	2386	*
cparata	0:6d69e896ce38	2387	*/
cparata	0:6d69e896ce38	2388	int32_t lsm6dso_aux_xl_fs_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2389	lsm6dso_xl_fs_mode_t *val)
cparata	0:6d69e896ce38	2390	{
cparata	0:6d69e896ce38	2391	lsm6dso_ctrl8_xl_t reg;
cparata	0:6d69e896ce38	2392	int32_t ret;
cparata	0:6d69e896ce38	2393
cparata	0:6d69e896ce38	2394	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2395	switch (reg.xl_fs_mode) {
cparata	0:6d69e896ce38	2396	case LSM6DSO_USE_SAME_XL_FS:
cparata	0:6d69e896ce38	2397	*val = LSM6DSO_USE_SAME_XL_FS;
cparata	0:6d69e896ce38	2398	break;
cparata	0:6d69e896ce38	2399	case LSM6DSO_USE_DIFFERENT_XL_FS:
cparata	0:6d69e896ce38	2400	*val = LSM6DSO_USE_DIFFERENT_XL_FS;
cparata	0:6d69e896ce38	2401	break;
cparata	0:6d69e896ce38	2402	default:
cparata	0:6d69e896ce38	2403	*val = LSM6DSO_USE_SAME_XL_FS;
cparata	0:6d69e896ce38	2404	break;
cparata	0:6d69e896ce38	2405	}
cparata	0:6d69e896ce38	2406
cparata	0:6d69e896ce38	2407	return ret;
cparata	0:6d69e896ce38	2408	}
cparata	0:6d69e896ce38	2409
cparata	0:6d69e896ce38	2410	/**
cparata	0:6d69e896ce38	2411	* @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
cparata	0:6d69e896ce38	2412	*
cparata	0:6d69e896ce38	2413	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2414	* @param lsm6dso_status_spiaux_t: registers STATUS_SPIAUX
cparata	0:6d69e896ce38	2415	*
cparata	0:6d69e896ce38	2416	*/
cparata	0:6d69e896ce38	2417	int32_t lsm6dso_aux_status_reg_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2418	lsm6dso_status_spiaux_t *val)
cparata	0:6d69e896ce38	2419	{
cparata	0:6d69e896ce38	2420	int32_t ret;
cparata	0:6d69e896ce38	2421	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*) val, 1);
cparata	0:6d69e896ce38	2422	return ret;
cparata	0:6d69e896ce38	2423	}
cparata	0:6d69e896ce38	2424
cparata	0:6d69e896ce38	2425	/**
cparata	0:6d69e896ce38	2426	* @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available
cparata	0:6d69e896ce38	2427	*
cparata	0:6d69e896ce38	2428	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2429	* @param val change the values of xlda in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2430	*
cparata	0:6d69e896ce38	2431	*/
cparata	0:6d69e896ce38	2432	int32_t lsm6dso_aux_xl_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2433	{
cparata	0:6d69e896ce38	2434	lsm6dso_status_spiaux_t reg;
cparata	0:6d69e896ce38	2435	int32_t ret;
cparata	0:6d69e896ce38	2436
cparata	0:6d69e896ce38	2437	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2438	*val = reg.xlda;
cparata	0:6d69e896ce38	2439
cparata	0:6d69e896ce38	2440	return ret;
cparata	0:6d69e896ce38	2441	}
cparata	0:6d69e896ce38	2442
cparata	0:6d69e896ce38	2443	/**
cparata	0:6d69e896ce38	2444	* @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available.
cparata	0:6d69e896ce38	2445	*
cparata	0:6d69e896ce38	2446	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2447	* @param val change the values of gda in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2448	*
cparata	0:6d69e896ce38	2449	*/
cparata	0:6d69e896ce38	2450	int32_t lsm6dso_aux_gy_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2451	{
cparata	0:6d69e896ce38	2452	lsm6dso_status_spiaux_t reg;
cparata	0:6d69e896ce38	2453	int32_t ret;
cparata	0:6d69e896ce38	2454
cparata	0:6d69e896ce38	2455	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2456	*val = reg.gda;
cparata	0:6d69e896ce38	2457
cparata	0:6d69e896ce38	2458	return ret;
cparata	0:6d69e896ce38	2459	}
cparata	0:6d69e896ce38	2460
cparata	0:6d69e896ce38	2461	/**
cparata	0:6d69e896ce38	2462	* @brief High when the gyroscope output is in the settling phase.[get]
cparata	0:6d69e896ce38	2463	*
cparata	0:6d69e896ce38	2464	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2465	* @param val change the values of gyro_settling in reg STATUS_SPIAUX
cparata	0:6d69e896ce38	2466	*
cparata	0:6d69e896ce38	2467	*/
cparata	0:6d69e896ce38	2468	int32_t lsm6dso_aux_gy_flag_settling_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2469	{
cparata	0:6d69e896ce38	2470	lsm6dso_status_spiaux_t reg;
cparata	0:6d69e896ce38	2471	int32_t ret;
cparata	0:6d69e896ce38	2472
cparata	0:6d69e896ce38	2473	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2474	*val = reg.gyro_settling;
cparata	0:6d69e896ce38	2475
cparata	0:6d69e896ce38	2476	return ret;
cparata	0:6d69e896ce38	2477	}
cparata	0:6d69e896ce38	2478
cparata	0:6d69e896ce38	2479	/**
cparata	0:6d69e896ce38	2480	* @brief Selects accelerometer self-test. Effective only if XL OIS
cparata	0:6d69e896ce38	2481	* chain is enabled.[set]
cparata	0:6d69e896ce38	2482	*
cparata	0:6d69e896ce38	2483	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2484	* @param val change the values of st_xl_ois in reg INT_OIS
cparata	0:6d69e896ce38	2485	*
cparata	0:6d69e896ce38	2486	*/
cparata	0:6d69e896ce38	2487	int32_t lsm6dso_aux_xl_self_test_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2488	lsm6dso_st_xl_ois_t val)
cparata	0:6d69e896ce38	2489	{
cparata	0:6d69e896ce38	2490	lsm6dso_int_ois_t reg;
cparata	0:6d69e896ce38	2491	int32_t ret;
cparata	0:6d69e896ce38	2492
cparata	0:6d69e896ce38	2493	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2494	if (ret == 0) {
cparata	0:6d69e896ce38	2495	reg.st_xl_ois = (uint8_t)val;
cparata	0:6d69e896ce38	2496	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2497	}
cparata	0:6d69e896ce38	2498	return ret;
cparata	0:6d69e896ce38	2499	}
cparata	0:6d69e896ce38	2500
cparata	0:6d69e896ce38	2501	/**
cparata	0:6d69e896ce38	2502	* @brief Selects accelerometer self-test. Effective only if XL OIS
cparata	0:6d69e896ce38	2503	* chain is enabled.[get]
cparata	0:6d69e896ce38	2504	*
cparata	0:6d69e896ce38	2505	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2506	* @param val Get the values of st_xl_ois in reg INT_OIS
cparata	0:6d69e896ce38	2507	*
cparata	0:6d69e896ce38	2508	*/
cparata	0:6d69e896ce38	2509	int32_t lsm6dso_aux_xl_self_test_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2510	lsm6dso_st_xl_ois_t *val)
cparata	0:6d69e896ce38	2511	{
cparata	0:6d69e896ce38	2512	lsm6dso_int_ois_t reg;
cparata	0:6d69e896ce38	2513	int32_t ret;
cparata	0:6d69e896ce38	2514
cparata	0:6d69e896ce38	2515	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2516	switch (reg.st_xl_ois) {
cparata	0:6d69e896ce38	2517	case LSM6DSO_AUX_XL_DISABLE:
cparata	0:6d69e896ce38	2518	*val = LSM6DSO_AUX_XL_DISABLE;
cparata	0:6d69e896ce38	2519	break;
cparata	0:6d69e896ce38	2520	case LSM6DSO_AUX_XL_POS:
cparata	0:6d69e896ce38	2521	*val = LSM6DSO_AUX_XL_POS;
cparata	0:6d69e896ce38	2522	break;
cparata	0:6d69e896ce38	2523	case LSM6DSO_AUX_XL_NEG:
cparata	0:6d69e896ce38	2524	*val = LSM6DSO_AUX_XL_NEG;
cparata	0:6d69e896ce38	2525	break;
cparata	0:6d69e896ce38	2526	default:
cparata	0:6d69e896ce38	2527	*val = LSM6DSO_AUX_XL_DISABLE;
cparata	0:6d69e896ce38	2528	break;
cparata	0:6d69e896ce38	2529	}
cparata	0:6d69e896ce38	2530	return ret;
cparata	0:6d69e896ce38	2531	}
cparata	0:6d69e896ce38	2532
cparata	0:6d69e896ce38	2533	/**
cparata	0:6d69e896ce38	2534	* @brief Indicates polarity of DEN signal on OIS chain.[set]
cparata	0:6d69e896ce38	2535	*
cparata	0:6d69e896ce38	2536	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2537	* @param val change the values of den_lh_ois in
cparata	0:6d69e896ce38	2538	* reg INT_OIS
cparata	0:6d69e896ce38	2539	*
cparata	0:6d69e896ce38	2540	*/
cparata	0:6d69e896ce38	2541	int32_t lsm6dso_aux_den_polarity_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2542	lsm6dso_den_lh_ois_t val)
cparata	0:6d69e896ce38	2543	{
cparata	0:6d69e896ce38	2544	lsm6dso_int_ois_t reg;
cparata	0:6d69e896ce38	2545	int32_t ret;
cparata	0:6d69e896ce38	2546
cparata	0:6d69e896ce38	2547	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2548	if (ret == 0) {
cparata	0:6d69e896ce38	2549	reg.den_lh_ois = (uint8_t)val;
cparata	0:6d69e896ce38	2550	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2551	}
cparata	0:6d69e896ce38	2552	return ret;
cparata	0:6d69e896ce38	2553	}
cparata	0:6d69e896ce38	2554
cparata	0:6d69e896ce38	2555	/**
cparata	0:6d69e896ce38	2556	* @brief Indicates polarity of DEN signal on OIS chain.[get]
cparata	0:6d69e896ce38	2557	*
cparata	0:6d69e896ce38	2558	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2559	* @param val Get the values of den_lh_ois in reg INT_OIS
cparata	0:6d69e896ce38	2560	*
cparata	0:6d69e896ce38	2561	*/
cparata	0:6d69e896ce38	2562	int32_t lsm6dso_aux_den_polarity_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2563	lsm6dso_den_lh_ois_t *val)
cparata	0:6d69e896ce38	2564	{
cparata	0:6d69e896ce38	2565	lsm6dso_int_ois_t reg;
cparata	0:6d69e896ce38	2566	int32_t ret;
cparata	0:6d69e896ce38	2567
cparata	0:6d69e896ce38	2568	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2569	switch (reg.den_lh_ois) {
cparata	0:6d69e896ce38	2570	case LSM6DSO_AUX_DEN_ACTIVE_LOW:
cparata	0:6d69e896ce38	2571	*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
cparata	0:6d69e896ce38	2572	break;
cparata	0:6d69e896ce38	2573	case LSM6DSO_AUX_DEN_ACTIVE_HIGH:
cparata	0:6d69e896ce38	2574	*val = LSM6DSO_AUX_DEN_ACTIVE_HIGH;
cparata	0:6d69e896ce38	2575	break;
cparata	0:6d69e896ce38	2576	default:
cparata	0:6d69e896ce38	2577	*val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
cparata	0:6d69e896ce38	2578	break;
cparata	0:6d69e896ce38	2579	}
cparata	0:6d69e896ce38	2580	return ret;
cparata	0:6d69e896ce38	2581	}
cparata	0:6d69e896ce38	2582
cparata	0:6d69e896ce38	2583	/**
cparata	0:6d69e896ce38	2584	* @brief Configure DEN mode on the OIS chain.[set]
cparata	0:6d69e896ce38	2585	*
cparata	0:6d69e896ce38	2586	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2587	* @param val change the values of lvl2_ois in reg INT_OIS
cparata	0:6d69e896ce38	2588	*
cparata	0:6d69e896ce38	2589	*/
cparata	0:6d69e896ce38	2590	int32_t lsm6dso_aux_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t val)
cparata	0:6d69e896ce38	2591	{
cparata	0:6d69e896ce38	2592	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	0:6d69e896ce38	2593	lsm6dso_int_ois_t int_ois;
cparata	0:6d69e896ce38	2594	int32_t ret;
cparata	0:6d69e896ce38	2595
cparata	0:6d69e896ce38	2596	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	0:6d69e896ce38	2597	if (ret == 0) {
cparata	0:6d69e896ce38	2598	int_ois.lvl2_ois = (uint8_t)val & 0x01U;
cparata	0:6d69e896ce38	2599	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	0:6d69e896ce38	2600	}
cparata	0:6d69e896ce38	2601	if (ret == 0) {
cparata	0:6d69e896ce38	2602	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	0:6d69e896ce38	2603	}
cparata	0:6d69e896ce38	2604	if (ret == 0) {
cparata	0:6d69e896ce38	2605	ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
cparata	0:6d69e896ce38	2606	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	0:6d69e896ce38	2607	}
cparata	0:6d69e896ce38	2608	return ret;
cparata	0:6d69e896ce38	2609	}
cparata	0:6d69e896ce38	2610
cparata	0:6d69e896ce38	2611	/**
cparata	0:6d69e896ce38	2612	* @brief Configure DEN mode on the OIS chain.[get]
cparata	0:6d69e896ce38	2613	*
cparata	0:6d69e896ce38	2614	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2615	* @param val Get the values of lvl2_ois in reg INT_OIS
cparata	0:6d69e896ce38	2616	*
cparata	0:6d69e896ce38	2617	*/
cparata	0:6d69e896ce38	2618	int32_t lsm6dso_aux_den_mode_get(lsm6dso_ctx_t ctx, lsm6dso_lvl2_ois_t val)
cparata	0:6d69e896ce38	2619	{
cparata	0:6d69e896ce38	2620	lsm6dso_ctrl1_ois_t ctrl1_ois;
cparata	0:6d69e896ce38	2621	lsm6dso_int_ois_t int_ois;
cparata	0:6d69e896ce38	2622	int32_t ret;
cparata	0:6d69e896ce38	2623
cparata	0:6d69e896ce38	2624	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1);
cparata	0:6d69e896ce38	2625	if (ret == 0) {
cparata	0:6d69e896ce38	2626	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1);
cparata	0:6d69e896ce38	2627	switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) {
cparata	0:6d69e896ce38	2628	case LSM6DSO_AUX_DEN_DISABLE:
cparata	0:6d69e896ce38	2629	*val = LSM6DSO_AUX_DEN_DISABLE;
cparata	0:6d69e896ce38	2630	break;
cparata	0:6d69e896ce38	2631	case LSM6DSO_AUX_DEN_LEVEL_LATCH:
cparata	0:6d69e896ce38	2632	*val = LSM6DSO_AUX_DEN_LEVEL_LATCH;
cparata	0:6d69e896ce38	2633	break;
cparata	0:6d69e896ce38	2634	case LSM6DSO_AUX_DEN_LEVEL_TRIG:
cparata	0:6d69e896ce38	2635	*val = LSM6DSO_AUX_DEN_LEVEL_TRIG;
cparata	0:6d69e896ce38	2636	break;
cparata	0:6d69e896ce38	2637	default:
cparata	0:6d69e896ce38	2638	*val = LSM6DSO_AUX_DEN_DISABLE;
cparata	0:6d69e896ce38	2639	break;
cparata	0:6d69e896ce38	2640	}
cparata	0:6d69e896ce38	2641	}
cparata	0:6d69e896ce38	2642	return ret;
cparata	0:6d69e896ce38	2643	}
cparata	0:6d69e896ce38	2644
cparata	0:6d69e896ce38	2645	/**
cparata	0:6d69e896ce38	2646	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:6d69e896ce38	2647	* This setting has priority over all other INT2 settings.[set]
cparata	0:6d69e896ce38	2648	*
cparata	0:6d69e896ce38	2649	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2650	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:6d69e896ce38	2651	*
cparata	0:6d69e896ce38	2652	*/
cparata	0:6d69e896ce38	2653	int32_t lsm6dso_aux_drdy_on_int2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	2654	{
cparata	0:6d69e896ce38	2655	lsm6dso_int_ois_t reg;
cparata	0:6d69e896ce38	2656	int32_t ret;
cparata	0:6d69e896ce38	2657
cparata	0:6d69e896ce38	2658	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2659	if (ret == 0) {
cparata	0:6d69e896ce38	2660	reg.int2_drdy_ois = val;
cparata	0:6d69e896ce38	2661	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2662	}
cparata	0:6d69e896ce38	2663	return ret;
cparata	0:6d69e896ce38	2664	}
cparata	0:6d69e896ce38	2665
cparata	0:6d69e896ce38	2666	/**
cparata	0:6d69e896ce38	2667	* @brief Enables/Disable OIS chain DRDY on INT2 pin.
cparata	0:6d69e896ce38	2668	* This setting has priority over all other INT2 settings.[get]
cparata	0:6d69e896ce38	2669	*
cparata	0:6d69e896ce38	2670	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2671	* @param val change the values of int2_drdy_ois in reg INT_OIS
cparata	0:6d69e896ce38	2672	*
cparata	0:6d69e896ce38	2673	*/
cparata	0:6d69e896ce38	2674	int32_t lsm6dso_aux_drdy_on_int2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	2675	{
cparata	0:6d69e896ce38	2676	lsm6dso_int_ois_t reg;
cparata	0:6d69e896ce38	2677	int32_t ret;
cparata	0:6d69e896ce38	2678
cparata	0:6d69e896ce38	2679	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2680	*val = reg.int2_drdy_ois;
cparata	0:6d69e896ce38	2681
cparata	0:6d69e896ce38	2682	return ret;
cparata	0:6d69e896ce38	2683	}
cparata	0:6d69e896ce38	2684
cparata	0:6d69e896ce38	2685	/**
cparata	0:6d69e896ce38	2686	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:6d69e896ce38	2687	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:6d69e896ce38	2688	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:6d69e896ce38	2689	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:6d69e896ce38	2690	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:6d69e896ce38	2691	* LPF1 is dedicated to this chain.[set]
cparata	0:6d69e896ce38	2692	*
cparata	0:6d69e896ce38	2693	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2694	* @param val change the values of ois_en_spi2 in
cparata	0:6d69e896ce38	2695	* reg CTRL1_OIS
cparata	0:6d69e896ce38	2696	*
cparata	0:6d69e896ce38	2697	*/
cparata	0:6d69e896ce38	2698	int32_t lsm6dso_aux_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t val)
cparata	0:6d69e896ce38	2699	{
cparata	0:6d69e896ce38	2700	lsm6dso_ctrl1_ois_t reg;
cparata	0:6d69e896ce38	2701	int32_t ret;
cparata	0:6d69e896ce38	2702
cparata	0:6d69e896ce38	2703	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2704	if (ret == 0) {
cparata	0:6d69e896ce38	2705	reg.ois_en_spi2 = (uint8_t)val & 0x01U;
cparata	0:6d69e896ce38	2706	reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
cparata	0:6d69e896ce38	2707	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2708	}
cparata	0:6d69e896ce38	2709	return ret;
cparata	0:6d69e896ce38	2710	}
cparata	0:6d69e896ce38	2711
cparata	0:6d69e896ce38	2712	/**
cparata	0:6d69e896ce38	2713	* @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
cparata	0:6d69e896ce38	2714	* (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
cparata	0:6d69e896ce38	2715	* When the OIS chain is enabled, the OIS outputs are available
cparata	0:6d69e896ce38	2716	* through the SPI2 in registers OUTX_L_G (22h) through
cparata	0:6d69e896ce38	2717	* OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
cparata	0:6d69e896ce38	2718	* LPF1 is dedicated to this chain.[get]
cparata	0:6d69e896ce38	2719	*
cparata	0:6d69e896ce38	2720	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2721	* @param val Get the values of ois_en_spi2 in
cparata	0:6d69e896ce38	2722	* reg CTRL1_OIS
cparata	0:6d69e896ce38	2723	*
cparata	0:6d69e896ce38	2724	*/
cparata	0:6d69e896ce38	2725	int32_t lsm6dso_aux_mode_get(lsm6dso_ctx_t ctx, lsm6dso_ois_en_spi2_t val)
cparata	0:6d69e896ce38	2726	{
cparata	0:6d69e896ce38	2727	lsm6dso_ctrl1_ois_t reg;
cparata	0:6d69e896ce38	2728	int32_t ret;
cparata	0:6d69e896ce38	2729
cparata	0:6d69e896ce38	2730	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2731	switch ((reg.mode4_en << 1) \| reg.ois_en_spi2) {
cparata	0:6d69e896ce38	2732	case LSM6DSO_AUX_DISABLE:
cparata	0:6d69e896ce38	2733	*val = LSM6DSO_AUX_DISABLE;
cparata	0:6d69e896ce38	2734	break;
cparata	0:6d69e896ce38	2735	case LSM6DSO_MODE_3_GY:
cparata	0:6d69e896ce38	2736	*val = LSM6DSO_MODE_3_GY;
cparata	0:6d69e896ce38	2737	break;
cparata	0:6d69e896ce38	2738	case LSM6DSO_MODE_4_GY_XL:
cparata	0:6d69e896ce38	2739	*val = LSM6DSO_MODE_4_GY_XL;
cparata	0:6d69e896ce38	2740	break;
cparata	0:6d69e896ce38	2741	default:
cparata	0:6d69e896ce38	2742	*val = LSM6DSO_AUX_DISABLE;
cparata	0:6d69e896ce38	2743	break;
cparata	0:6d69e896ce38	2744	}
cparata	0:6d69e896ce38	2745	return ret;
cparata	0:6d69e896ce38	2746	}
cparata	0:6d69e896ce38	2747
cparata	0:6d69e896ce38	2748	/**
cparata	0:6d69e896ce38	2749	* @brief Selects gyroscope OIS chain full-scale.[set]
cparata	0:6d69e896ce38	2750	*
cparata	0:6d69e896ce38	2751	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2752	* @param val change the values of fs_g_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2753	*
cparata	0:6d69e896ce38	2754	*/
cparata	0:6d69e896ce38	2755	int32_t lsm6dso_aux_gy_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2756	lsm6dso_fs_g_ois_t val)
cparata	0:6d69e896ce38	2757	{
cparata	0:6d69e896ce38	2758	lsm6dso_ctrl1_ois_t reg;
cparata	0:6d69e896ce38	2759	int32_t ret;
cparata	0:6d69e896ce38	2760
cparata	0:6d69e896ce38	2761	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2762	if (ret == 0) {
cparata	0:6d69e896ce38	2763	reg.fs_g_ois = (uint8_t)val;
cparata	0:6d69e896ce38	2764	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2765	}
cparata	0:6d69e896ce38	2766	return ret;
cparata	0:6d69e896ce38	2767	}
cparata	0:6d69e896ce38	2768
cparata	0:6d69e896ce38	2769	/**
cparata	0:6d69e896ce38	2770	* @brief Selects gyroscope OIS chain full-scale.[get]
cparata	0:6d69e896ce38	2771	*
cparata	0:6d69e896ce38	2772	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2773	* @param val Get the values of fs_g_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2774	*
cparata	0:6d69e896ce38	2775	*/
cparata	0:6d69e896ce38	2776	int32_t lsm6dso_aux_gy_full_scale_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2777	lsm6dso_fs_g_ois_t *val)
cparata	0:6d69e896ce38	2778	{
cparata	0:6d69e896ce38	2779	lsm6dso_ctrl1_ois_t reg;
cparata	0:6d69e896ce38	2780	int32_t ret;
cparata	0:6d69e896ce38	2781
cparata	0:6d69e896ce38	2782	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2783	switch (reg.fs_g_ois) {
cparata	0:6d69e896ce38	2784	case LSM6DSO_250dps_AUX:
cparata	0:6d69e896ce38	2785	*val = LSM6DSO_250dps_AUX;
cparata	0:6d69e896ce38	2786	break;
cparata	0:6d69e896ce38	2787	case LSM6DSO_125dps_AUX:
cparata	0:6d69e896ce38	2788	*val = LSM6DSO_125dps_AUX;
cparata	0:6d69e896ce38	2789	break;
cparata	0:6d69e896ce38	2790	case LSM6DSO_500dps_AUX:
cparata	0:6d69e896ce38	2791	*val = LSM6DSO_500dps_AUX;
cparata	0:6d69e896ce38	2792	break;
cparata	0:6d69e896ce38	2793	case LSM6DSO_1000dps_AUX:
cparata	0:6d69e896ce38	2794	*val = LSM6DSO_1000dps_AUX;
cparata	0:6d69e896ce38	2795	break;
cparata	0:6d69e896ce38	2796	case LSM6DSO_2000dps_AUX:
cparata	0:6d69e896ce38	2797	*val = LSM6DSO_2000dps_AUX;
cparata	0:6d69e896ce38	2798	break;
cparata	0:6d69e896ce38	2799	default:
cparata	0:6d69e896ce38	2800	*val = LSM6DSO_250dps_AUX;
cparata	0:6d69e896ce38	2801	break;
cparata	0:6d69e896ce38	2802	}
cparata	0:6d69e896ce38	2803	return ret;
cparata	0:6d69e896ce38	2804	}
cparata	0:6d69e896ce38	2805
cparata	0:6d69e896ce38	2806	/**
cparata	0:6d69e896ce38	2807	* @brief SPI2 3- or 4-wire interface.[set]
cparata	0:6d69e896ce38	2808	*
cparata	0:6d69e896ce38	2809	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2810	* @param val change the values of sim_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2811	*
cparata	0:6d69e896ce38	2812	*/
cparata	0:6d69e896ce38	2813	int32_t lsm6dso_aux_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t val)
cparata	0:6d69e896ce38	2814	{
cparata	0:6d69e896ce38	2815	lsm6dso_ctrl1_ois_t reg;
cparata	0:6d69e896ce38	2816	int32_t ret;
cparata	0:6d69e896ce38	2817
cparata	0:6d69e896ce38	2818	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2819	if (ret == 0) {
cparata	0:6d69e896ce38	2820	reg.sim_ois = (uint8_t)val;
cparata	0:6d69e896ce38	2821	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2822	}
cparata	0:6d69e896ce38	2823	return ret;
cparata	0:6d69e896ce38	2824	}
cparata	0:6d69e896ce38	2825
cparata	0:6d69e896ce38	2826	/**
cparata	0:6d69e896ce38	2827	* @brief SPI2 3- or 4-wire interface.[get]
cparata	0:6d69e896ce38	2828	*
cparata	0:6d69e896ce38	2829	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2830	* @param val Get the values of sim_ois in reg CTRL1_OIS
cparata	0:6d69e896ce38	2831	*
cparata	0:6d69e896ce38	2832	*/
cparata	0:6d69e896ce38	2833	int32_t lsm6dso_aux_spi_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sim_ois_t val)
cparata	0:6d69e896ce38	2834	{
cparata	0:6d69e896ce38	2835	lsm6dso_ctrl1_ois_t reg;
cparata	0:6d69e896ce38	2836	int32_t ret;
cparata	0:6d69e896ce38	2837
cparata	0:6d69e896ce38	2838	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2839	switch (reg.sim_ois) {
cparata	0:6d69e896ce38	2840	case LSM6DSO_AUX_SPI_4_WIRE:
cparata	0:6d69e896ce38	2841	*val = LSM6DSO_AUX_SPI_4_WIRE;
cparata	0:6d69e896ce38	2842	break;
cparata	0:6d69e896ce38	2843	case LSM6DSO_AUX_SPI_3_WIRE:
cparata	0:6d69e896ce38	2844	*val = LSM6DSO_AUX_SPI_3_WIRE;
cparata	0:6d69e896ce38	2845	break;
cparata	0:6d69e896ce38	2846	default:
cparata	0:6d69e896ce38	2847	*val = LSM6DSO_AUX_SPI_4_WIRE;
cparata	0:6d69e896ce38	2848	break;
cparata	0:6d69e896ce38	2849	}
cparata	0:6d69e896ce38	2850	return ret;
cparata	0:6d69e896ce38	2851	}
cparata	0:6d69e896ce38	2852
cparata	0:6d69e896ce38	2853	/**
cparata	0:6d69e896ce38	2854	* @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
cparata	0:6d69e896ce38	2855	*
cparata	0:6d69e896ce38	2856	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2857	* @param val change the values of ftype_ois in
cparata	0:6d69e896ce38	2858	* reg CTRL2_OIS
cparata	0:6d69e896ce38	2859	*
cparata	0:6d69e896ce38	2860	*/
cparata	0:6d69e896ce38	2861	int32_t lsm6dso_aux_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2862	lsm6dso_ftype_ois_t val)
cparata	0:6d69e896ce38	2863	{
cparata	0:6d69e896ce38	2864	lsm6dso_ctrl2_ois_t reg;
cparata	0:6d69e896ce38	2865	int32_t ret;
cparata	0:6d69e896ce38	2866
cparata	0:6d69e896ce38	2867	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2868	if (ret == 0) {
cparata	0:6d69e896ce38	2869	reg.ftype_ois = (uint8_t)val;
cparata	0:6d69e896ce38	2870	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2871	}
cparata	0:6d69e896ce38	2872	return ret;
cparata	0:6d69e896ce38	2873	}
cparata	0:6d69e896ce38	2874
cparata	0:6d69e896ce38	2875	/**
cparata	0:6d69e896ce38	2876	* @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
cparata	0:6d69e896ce38	2877	*
cparata	0:6d69e896ce38	2878	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2879	* @param val Get the values of ftype_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	2880	*
cparata	0:6d69e896ce38	2881	*/
cparata	0:6d69e896ce38	2882	int32_t lsm6dso_aux_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2883	lsm6dso_ftype_ois_t *val)
cparata	0:6d69e896ce38	2884	{
cparata	0:6d69e896ce38	2885	lsm6dso_ctrl2_ois_t reg;
cparata	0:6d69e896ce38	2886	int32_t ret;
cparata	0:6d69e896ce38	2887
cparata	0:6d69e896ce38	2888	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2889	switch (reg.ftype_ois) {
cparata	0:6d69e896ce38	2890	case LSM6DSO_351Hz39:
cparata	0:6d69e896ce38	2891	*val = LSM6DSO_351Hz39;
cparata	0:6d69e896ce38	2892	break;
cparata	0:6d69e896ce38	2893	case LSM6DSO_236Hz63:
cparata	0:6d69e896ce38	2894	*val = LSM6DSO_236Hz63;
cparata	0:6d69e896ce38	2895	break;
cparata	0:6d69e896ce38	2896	case LSM6DSO_172Hz70:
cparata	0:6d69e896ce38	2897	*val = LSM6DSO_172Hz70;
cparata	0:6d69e896ce38	2898	break;
cparata	0:6d69e896ce38	2899	case LSM6DSO_937Hz91:
cparata	0:6d69e896ce38	2900	*val = LSM6DSO_937Hz91;
cparata	0:6d69e896ce38	2901	break;
cparata	0:6d69e896ce38	2902	default:
cparata	0:6d69e896ce38	2903	*val = LSM6DSO_351Hz39;
cparata	0:6d69e896ce38	2904	break;
cparata	0:6d69e896ce38	2905	}
cparata	0:6d69e896ce38	2906	return ret;
cparata	0:6d69e896ce38	2907	}
cparata	0:6d69e896ce38	2908
cparata	0:6d69e896ce38	2909	/**
cparata	0:6d69e896ce38	2910	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
cparata	0:6d69e896ce38	2911	*
cparata	0:6d69e896ce38	2912	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2913	* @param val change the values of hpm_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	2914	*
cparata	0:6d69e896ce38	2915	*/
cparata	0:6d69e896ce38	2916	int32_t lsm6dso_aux_gy_hp_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2917	lsm6dso_hpm_ois_t val)
cparata	0:6d69e896ce38	2918	{
cparata	0:6d69e896ce38	2919	lsm6dso_ctrl2_ois_t reg;
cparata	0:6d69e896ce38	2920	int32_t ret;
cparata	0:6d69e896ce38	2921
cparata	0:6d69e896ce38	2922	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2923	if (ret == 0) {
cparata	0:6d69e896ce38	2924	reg.hpm_ois = (uint8_t)val & 0x03U;
cparata	0:6d69e896ce38	2925	reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
cparata	0:6d69e896ce38	2926	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2927	}
cparata	0:6d69e896ce38	2928	return ret;
cparata	0:6d69e896ce38	2929	}
cparata	0:6d69e896ce38	2930
cparata	0:6d69e896ce38	2931	/**
cparata	0:6d69e896ce38	2932	* @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
cparata	0:6d69e896ce38	2933	*
cparata	0:6d69e896ce38	2934	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2935	* @param val Get the values of hpm_ois in reg CTRL2_OIS
cparata	0:6d69e896ce38	2936	*
cparata	0:6d69e896ce38	2937	*/
cparata	0:6d69e896ce38	2938	int32_t lsm6dso_aux_gy_hp_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2939	lsm6dso_hpm_ois_t *val)
cparata	0:6d69e896ce38	2940	{
cparata	0:6d69e896ce38	2941	lsm6dso_ctrl2_ois_t reg;
cparata	0:6d69e896ce38	2942	int32_t ret;
cparata	0:6d69e896ce38	2943
cparata	0:6d69e896ce38	2944	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2945	switch ((reg.hp_en_ois << 4) \| reg.hpm_ois) {
cparata	0:6d69e896ce38	2946	case LSM6DSO_AUX_HP_DISABLE:
cparata	0:6d69e896ce38	2947	*val = LSM6DSO_AUX_HP_DISABLE;
cparata	0:6d69e896ce38	2948	break;
cparata	0:6d69e896ce38	2949	case LSM6DSO_AUX_HP_Hz016:
cparata	0:6d69e896ce38	2950	*val = LSM6DSO_AUX_HP_Hz016;
cparata	0:6d69e896ce38	2951	break;
cparata	0:6d69e896ce38	2952	case LSM6DSO_AUX_HP_Hz065:
cparata	0:6d69e896ce38	2953	*val = LSM6DSO_AUX_HP_Hz065;
cparata	0:6d69e896ce38	2954	break;
cparata	0:6d69e896ce38	2955	case LSM6DSO_AUX_HP_Hz260:
cparata	0:6d69e896ce38	2956	*val = LSM6DSO_AUX_HP_Hz260;
cparata	0:6d69e896ce38	2957	break;
cparata	0:6d69e896ce38	2958	case LSM6DSO_AUX_HP_1Hz040:
cparata	0:6d69e896ce38	2959	*val = LSM6DSO_AUX_HP_1Hz040;
cparata	0:6d69e896ce38	2960	break;
cparata	0:6d69e896ce38	2961	default:
cparata	0:6d69e896ce38	2962	*val = LSM6DSO_AUX_HP_DISABLE;
cparata	0:6d69e896ce38	2963	break;
cparata	0:6d69e896ce38	2964	}
cparata	0:6d69e896ce38	2965	return ret;
cparata	0:6d69e896ce38	2966	}
cparata	0:6d69e896ce38	2967
cparata	0:6d69e896ce38	2968	/**
cparata	0:6d69e896ce38	2969	* @brief Enable / Disables OIS chain clamp.
cparata	0:6d69e896ce38	2970	* Enable: All OIS chain outputs = 8000h
cparata	0:6d69e896ce38	2971	* during self-test; Disable: OIS chain self-test
cparata	0:6d69e896ce38	2972	* outputs dependent from the aux gyro full
cparata	0:6d69e896ce38	2973	* scale selected.[set]
cparata	0:6d69e896ce38	2974	*
cparata	0:6d69e896ce38	2975	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	2976	* @param val change the values of st_ois_clampdis in
cparata	0:6d69e896ce38	2977	* reg CTRL3_OIS
cparata	0:6d69e896ce38	2978	*
cparata	0:6d69e896ce38	2979	*/
cparata	0:6d69e896ce38	2980	int32_t lsm6dso_aux_gy_clamp_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	2981	lsm6dso_st_ois_clampdis_t val)
cparata	0:6d69e896ce38	2982	{
cparata	0:6d69e896ce38	2983	lsm6dso_ctrl3_ois_t reg;
cparata	0:6d69e896ce38	2984	int32_t ret;
cparata	0:6d69e896ce38	2985
cparata	0:6d69e896ce38	2986	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2987	if (ret == 0) {
cparata	0:6d69e896ce38	2988	reg.st_ois_clampdis = (uint8_t)val;
cparata	0:6d69e896ce38	2989	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	2990	}
cparata	0:6d69e896ce38	2991	return ret;
cparata	0:6d69e896ce38	2992	}
cparata	0:6d69e896ce38	2993
cparata	0:6d69e896ce38	2994	/**
cparata	0:6d69e896ce38	2995	* @brief Enable / Disables OIS chain clamp.
cparata	0:6d69e896ce38	2996	* Enable: All OIS chain outputs = 8000h
cparata	0:6d69e896ce38	2997	* during self-test; Disable: OIS chain self-test
cparata	0:6d69e896ce38	2998	* outputs dependent from the aux gyro full
cparata	0:6d69e896ce38	2999	* scale selected.[set]
cparata	0:6d69e896ce38	3000	*
cparata	0:6d69e896ce38	3001	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3002	* @param val Get the values of st_ois_clampdis in
cparata	0:6d69e896ce38	3003	* reg CTRL3_OIS
cparata	0:6d69e896ce38	3004	*
cparata	0:6d69e896ce38	3005	*/
cparata	0:6d69e896ce38	3006	int32_t lsm6dso_aux_gy_clamp_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3007	lsm6dso_st_ois_clampdis_t *val)
cparata	0:6d69e896ce38	3008	{
cparata	0:6d69e896ce38	3009	lsm6dso_ctrl3_ois_t reg;
cparata	0:6d69e896ce38	3010	int32_t ret;
cparata	0:6d69e896ce38	3011
cparata	0:6d69e896ce38	3012	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3013	switch (reg.st_ois_clampdis) {
cparata	0:6d69e896ce38	3014	case LSM6DSO_ENABLE_CLAMP:
cparata	0:6d69e896ce38	3015	*val = LSM6DSO_ENABLE_CLAMP;
cparata	0:6d69e896ce38	3016	break;
cparata	0:6d69e896ce38	3017	case LSM6DSO_DISABLE_CLAMP:
cparata	0:6d69e896ce38	3018	*val = LSM6DSO_DISABLE_CLAMP;
cparata	0:6d69e896ce38	3019	break;
cparata	0:6d69e896ce38	3020	default:
cparata	0:6d69e896ce38	3021	*val = LSM6DSO_ENABLE_CLAMP;
cparata	0:6d69e896ce38	3022	break;
cparata	0:6d69e896ce38	3023	}
cparata	0:6d69e896ce38	3024	return ret;
cparata	0:6d69e896ce38	3025	}
cparata	0:6d69e896ce38	3026
cparata	0:6d69e896ce38	3027	/**
cparata	0:6d69e896ce38	3028	* @brief Selects gyroscope OIS chain self-test.[set]
cparata	0:6d69e896ce38	3029	*
cparata	0:6d69e896ce38	3030	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3031	* @param val change the values of st_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3032	*
cparata	0:6d69e896ce38	3033	*/
cparata	0:6d69e896ce38	3034	int32_t lsm6dso_aux_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_ois_t val)
cparata	0:6d69e896ce38	3035	{
cparata	0:6d69e896ce38	3036	lsm6dso_ctrl3_ois_t reg;
cparata	0:6d69e896ce38	3037	int32_t ret;
cparata	0:6d69e896ce38	3038
cparata	0:6d69e896ce38	3039	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3040	if (ret == 0) {
cparata	0:6d69e896ce38	3041	reg.st_ois = (uint8_t)val;
cparata	0:6d69e896ce38	3042	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3043	}
cparata	0:6d69e896ce38	3044	return ret;
cparata	0:6d69e896ce38	3045	}
cparata	0:6d69e896ce38	3046
cparata	0:6d69e896ce38	3047	/**
cparata	0:6d69e896ce38	3048	* @brief Selects gyroscope OIS chain self-test.[get]
cparata	0:6d69e896ce38	3049	*
cparata	0:6d69e896ce38	3050	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3051	* @param val Get the values of st_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3052	*
cparata	0:6d69e896ce38	3053	*/
cparata	0:6d69e896ce38	3054	int32_t lsm6dso_aux_gy_self_test_get(lsm6dso_ctx_t ctx, lsm6dso_st_ois_t val)
cparata	0:6d69e896ce38	3055	{
cparata	0:6d69e896ce38	3056	lsm6dso_ctrl3_ois_t reg;
cparata	0:6d69e896ce38	3057	int32_t ret;
cparata	0:6d69e896ce38	3058
cparata	0:6d69e896ce38	3059	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3060	switch (reg.st_ois) {
cparata	0:6d69e896ce38	3061	case LSM6DSO_AUX_GY_DISABLE:
cparata	0:6d69e896ce38	3062	*val = LSM6DSO_AUX_GY_DISABLE;
cparata	0:6d69e896ce38	3063	break;
cparata	0:6d69e896ce38	3064	case LSM6DSO_AUX_GY_POS:
cparata	0:6d69e896ce38	3065	*val = LSM6DSO_AUX_GY_POS;
cparata	0:6d69e896ce38	3066	break;
cparata	0:6d69e896ce38	3067	case LSM6DSO_AUX_GY_NEG:
cparata	0:6d69e896ce38	3068	*val = LSM6DSO_AUX_GY_NEG;
cparata	0:6d69e896ce38	3069	break;
cparata	0:6d69e896ce38	3070	default:
cparata	0:6d69e896ce38	3071	*val = LSM6DSO_AUX_GY_DISABLE;
cparata	0:6d69e896ce38	3072	break;
cparata	0:6d69e896ce38	3073	}
cparata	0:6d69e896ce38	3074	return ret;
cparata	0:6d69e896ce38	3075	}
cparata	0:6d69e896ce38	3076
cparata	0:6d69e896ce38	3077	/**
cparata	0:6d69e896ce38	3078	* @brief Selects accelerometer OIS channel bandwidth.[set]
cparata	0:6d69e896ce38	3079	*
cparata	0:6d69e896ce38	3080	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3081	* @param val change the values of
cparata	0:6d69e896ce38	3082	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3083	*
cparata	0:6d69e896ce38	3084	*/
cparata	0:6d69e896ce38	3085	int32_t lsm6dso_aux_xl_bandwidth_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3086	lsm6dso_filter_xl_conf_ois_t val)
cparata	0:6d69e896ce38	3087	{
cparata	0:6d69e896ce38	3088	lsm6dso_ctrl3_ois_t reg;
cparata	0:6d69e896ce38	3089	int32_t ret;
cparata	0:6d69e896ce38	3090
cparata	0:6d69e896ce38	3091	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3092	if (ret == 0) {
cparata	0:6d69e896ce38	3093	reg.filter_xl_conf_ois = (uint8_t)val;
cparata	0:6d69e896ce38	3094	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3095	}
cparata	0:6d69e896ce38	3096	return ret;
cparata	0:6d69e896ce38	3097	}
cparata	0:6d69e896ce38	3098
cparata	0:6d69e896ce38	3099	/**
cparata	0:6d69e896ce38	3100	* @brief Selects accelerometer OIS channel bandwidth.[get]
cparata	0:6d69e896ce38	3101	*
cparata	0:6d69e896ce38	3102	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3103	* @param val Get the values of
cparata	0:6d69e896ce38	3104	* filter_xl_conf_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3105	*
cparata	0:6d69e896ce38	3106	*/
cparata	0:6d69e896ce38	3107	int32_t lsm6dso_aux_xl_bandwidth_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3108	lsm6dso_filter_xl_conf_ois_t *val)
cparata	0:6d69e896ce38	3109	{
cparata	0:6d69e896ce38	3110	lsm6dso_ctrl3_ois_t reg;
cparata	0:6d69e896ce38	3111	int32_t ret;
cparata	0:6d69e896ce38	3112
cparata	0:6d69e896ce38	3113	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3114
cparata	0:6d69e896ce38	3115	switch (reg.filter_xl_conf_ois) {
cparata	0:6d69e896ce38	3116	case LSM6DSO_289Hz:
cparata	0:6d69e896ce38	3117	*val = LSM6DSO_289Hz;
cparata	0:6d69e896ce38	3118	break;
cparata	0:6d69e896ce38	3119	case LSM6DSO_258Hz:
cparata	0:6d69e896ce38	3120	*val = LSM6DSO_258Hz;
cparata	0:6d69e896ce38	3121	break;
cparata	0:6d69e896ce38	3122	case LSM6DSO_120Hz:
cparata	0:6d69e896ce38	3123	*val = LSM6DSO_120Hz;
cparata	0:6d69e896ce38	3124	break;
cparata	0:6d69e896ce38	3125	case LSM6DSO_65Hz2:
cparata	0:6d69e896ce38	3126	*val = LSM6DSO_65Hz2;
cparata	0:6d69e896ce38	3127	break;
cparata	0:6d69e896ce38	3128	case LSM6DSO_33Hz2:
cparata	0:6d69e896ce38	3129	*val = LSM6DSO_33Hz2;
cparata	0:6d69e896ce38	3130	break;
cparata	0:6d69e896ce38	3131	case LSM6DSO_16Hz6:
cparata	0:6d69e896ce38	3132	*val = LSM6DSO_16Hz6;
cparata	0:6d69e896ce38	3133	break;
cparata	0:6d69e896ce38	3134	case LSM6DSO_8Hz30:
cparata	0:6d69e896ce38	3135	*val = LSM6DSO_8Hz30;
cparata	0:6d69e896ce38	3136	break;
cparata	0:6d69e896ce38	3137	case LSM6DSO_4Hz15:
cparata	0:6d69e896ce38	3138	*val = LSM6DSO_4Hz15;
cparata	0:6d69e896ce38	3139	break;
cparata	0:6d69e896ce38	3140	default:
cparata	0:6d69e896ce38	3141	*val = LSM6DSO_289Hz;
cparata	0:6d69e896ce38	3142	break;
cparata	0:6d69e896ce38	3143	}
cparata	0:6d69e896ce38	3144	return ret;
cparata	0:6d69e896ce38	3145	}
cparata	0:6d69e896ce38	3146
cparata	0:6d69e896ce38	3147	/**
cparata	0:6d69e896ce38	3148	* @brief Selects accelerometer OIS channel full-scale.[set]
cparata	0:6d69e896ce38	3149	*
cparata	0:6d69e896ce38	3150	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3151	* @param val change the values of fs_xl_ois in
cparata	0:6d69e896ce38	3152	* reg CTRL3_OIS
cparata	0:6d69e896ce38	3153	*
cparata	0:6d69e896ce38	3154	*/
cparata	0:6d69e896ce38	3155	int32_t lsm6dso_aux_xl_full_scale_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3156	lsm6dso_fs_xl_ois_t val)
cparata	0:6d69e896ce38	3157	{
cparata	0:6d69e896ce38	3158	lsm6dso_ctrl3_ois_t reg;
cparata	0:6d69e896ce38	3159	int32_t ret;
cparata	0:6d69e896ce38	3160
cparata	0:6d69e896ce38	3161	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3162	if (ret == 0) {
cparata	0:6d69e896ce38	3163	reg.fs_xl_ois = (uint8_t)val;
cparata	0:6d69e896ce38	3164	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3165	}
cparata	0:6d69e896ce38	3166	return ret;
cparata	0:6d69e896ce38	3167	}
cparata	0:6d69e896ce38	3168
cparata	0:6d69e896ce38	3169	/**
cparata	0:6d69e896ce38	3170	* @brief Selects accelerometer OIS channel full-scale.[get]
cparata	0:6d69e896ce38	3171	*
cparata	0:6d69e896ce38	3172	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3173	* @param val Get the values of fs_xl_ois in reg CTRL3_OIS
cparata	0:6d69e896ce38	3174	*
cparata	0:6d69e896ce38	3175	*/
cparata	0:6d69e896ce38	3176	int32_t lsm6dso_aux_xl_full_scale_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3177	lsm6dso_fs_xl_ois_t *val)
cparata	0:6d69e896ce38	3178	{
cparata	0:6d69e896ce38	3179	lsm6dso_ctrl3_ois_t reg;
cparata	0:6d69e896ce38	3180	int32_t ret;
cparata	0:6d69e896ce38	3181
cparata	0:6d69e896ce38	3182	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3183	switch (reg.fs_xl_ois) {
cparata	0:6d69e896ce38	3184	case LSM6DSO_AUX_2g:
cparata	0:6d69e896ce38	3185	*val = LSM6DSO_AUX_2g;
cparata	0:6d69e896ce38	3186	break;
cparata	0:6d69e896ce38	3187	case LSM6DSO_AUX_16g:
cparata	0:6d69e896ce38	3188	*val = LSM6DSO_AUX_16g;
cparata	0:6d69e896ce38	3189	break;
cparata	0:6d69e896ce38	3190	case LSM6DSO_AUX_4g:
cparata	0:6d69e896ce38	3191	*val = LSM6DSO_AUX_4g;
cparata	0:6d69e896ce38	3192	break;
cparata	0:6d69e896ce38	3193	case LSM6DSO_AUX_8g:
cparata	0:6d69e896ce38	3194	*val = LSM6DSO_AUX_8g;
cparata	0:6d69e896ce38	3195	break;
cparata	0:6d69e896ce38	3196	default:
cparata	0:6d69e896ce38	3197	*val = LSM6DSO_AUX_2g;
cparata	0:6d69e896ce38	3198	break;
cparata	0:6d69e896ce38	3199	}
cparata	0:6d69e896ce38	3200	return ret;
cparata	0:6d69e896ce38	3201	}
cparata	0:6d69e896ce38	3202
cparata	0:6d69e896ce38	3203	/**
cparata	0:6d69e896ce38	3204	* @}
cparata	0:6d69e896ce38	3205	*
cparata	0:6d69e896ce38	3206	*/
cparata	0:6d69e896ce38	3207
cparata	0:6d69e896ce38	3208	/**
cparata	0:6d69e896ce38	3209	* @defgroup LSM6DSO_ main_serial_interface
cparata	0:6d69e896ce38	3210	* @brief This section groups all the functions concerning main
cparata	0:6d69e896ce38	3211	* serial interface management (not auxiliary)
cparata	0:6d69e896ce38	3212	* @{
cparata	0:6d69e896ce38	3213	*
cparata	0:6d69e896ce38	3214	*/
cparata	0:6d69e896ce38	3215
cparata	0:6d69e896ce38	3216	/**
cparata	0:6d69e896ce38	3217	* @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
cparata	0:6d69e896ce38	3218	*
cparata	0:6d69e896ce38	3219	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3220	* @param val change the values of sdo_pu_en in
cparata	0:6d69e896ce38	3221	* reg PIN_CTRL
cparata	0:6d69e896ce38	3222	*
cparata	0:6d69e896ce38	3223	*/
cparata	0:6d69e896ce38	3224	int32_t lsm6dso_sdo_sa0_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sdo_pu_en_t val)
cparata	0:6d69e896ce38	3225	{
cparata	0:6d69e896ce38	3226	lsm6dso_pin_ctrl_t reg;
cparata	0:6d69e896ce38	3227	int32_t ret;
cparata	0:6d69e896ce38	3228
cparata	0:6d69e896ce38	3229	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3230	if (ret == 0) {
cparata	0:6d69e896ce38	3231	reg.sdo_pu_en = (uint8_t)val;
cparata	0:6d69e896ce38	3232	ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3233	}
cparata	0:6d69e896ce38	3234	return ret;
cparata	0:6d69e896ce38	3235	}
cparata	0:6d69e896ce38	3236
cparata	0:6d69e896ce38	3237	/**
cparata	0:6d69e896ce38	3238	* @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
cparata	0:6d69e896ce38	3239	*
cparata	0:6d69e896ce38	3240	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3241	* @param val Get the values of sdo_pu_en in reg PIN_CTRL
cparata	0:6d69e896ce38	3242	*
cparata	0:6d69e896ce38	3243	*/
cparata	0:6d69e896ce38	3244	int32_t lsm6dso_sdo_sa0_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sdo_pu_en_t val)
cparata	0:6d69e896ce38	3245	{
cparata	0:6d69e896ce38	3246	lsm6dso_pin_ctrl_t reg;
cparata	0:6d69e896ce38	3247	int32_t ret;
cparata	0:6d69e896ce38	3248
cparata	0:6d69e896ce38	3249	ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3250	switch (reg.sdo_pu_en) {
cparata	0:6d69e896ce38	3251	case LSM6DSO_PULL_UP_DISC:
cparata	0:6d69e896ce38	3252	*val = LSM6DSO_PULL_UP_DISC;
cparata	0:6d69e896ce38	3253	break;
cparata	0:6d69e896ce38	3254	case LSM6DSO_PULL_UP_CONNECT:
cparata	0:6d69e896ce38	3255	*val = LSM6DSO_PULL_UP_CONNECT;
cparata	0:6d69e896ce38	3256	break;
cparata	0:6d69e896ce38	3257	default:
cparata	0:6d69e896ce38	3258	*val = LSM6DSO_PULL_UP_DISC;
cparata	0:6d69e896ce38	3259	break;
cparata	0:6d69e896ce38	3260	}
cparata	0:6d69e896ce38	3261	return ret;
cparata	0:6d69e896ce38	3262	}
cparata	0:6d69e896ce38	3263
cparata	0:6d69e896ce38	3264	/**
cparata	0:6d69e896ce38	3265	* @brief SPI Serial Interface Mode selection.[set]
cparata	0:6d69e896ce38	3266	*
cparata	0:6d69e896ce38	3267	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3268	* @param val change the values of sim in reg CTRL3_C
cparata	0:6d69e896ce38	3269	*
cparata	0:6d69e896ce38	3270	*/
cparata	0:6d69e896ce38	3271	int32_t lsm6dso_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_t val)
cparata	0:6d69e896ce38	3272	{
cparata	0:6d69e896ce38	3273	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	3274	int32_t ret;
cparata	0:6d69e896ce38	3275
cparata	0:6d69e896ce38	3276	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3277	if (ret == 0) {
cparata	0:6d69e896ce38	3278	reg.sim = (uint8_t)val;
cparata	0:6d69e896ce38	3279	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3280	}
cparata	0:6d69e896ce38	3281	return ret;
cparata	0:6d69e896ce38	3282	}
cparata	0:6d69e896ce38	3283
cparata	0:6d69e896ce38	3284	/**
cparata	0:6d69e896ce38	3285	* @brief SPI Serial Interface Mode selection.[get]
cparata	0:6d69e896ce38	3286	*
cparata	0:6d69e896ce38	3287	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3288	* @param val Get the values of sim in reg CTRL3_C
cparata	0:6d69e896ce38	3289	*
cparata	0:6d69e896ce38	3290	*/
cparata	0:6d69e896ce38	3291	int32_t lsm6dso_spi_mode_get(lsm6dso_ctx_t ctx, lsm6dso_sim_t val)
cparata	0:6d69e896ce38	3292	{
cparata	0:6d69e896ce38	3293	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	3294	int32_t ret;
cparata	0:6d69e896ce38	3295
cparata	0:6d69e896ce38	3296	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3297	switch (reg.sim) {
cparata	0:6d69e896ce38	3298	case LSM6DSO_SPI_4_WIRE:
cparata	0:6d69e896ce38	3299	*val = LSM6DSO_SPI_4_WIRE;
cparata	0:6d69e896ce38	3300	break;
cparata	0:6d69e896ce38	3301	case LSM6DSO_SPI_3_WIRE:
cparata	0:6d69e896ce38	3302	*val = LSM6DSO_SPI_3_WIRE;
cparata	0:6d69e896ce38	3303	break;
cparata	0:6d69e896ce38	3304	default:
cparata	0:6d69e896ce38	3305	*val = LSM6DSO_SPI_4_WIRE;
cparata	0:6d69e896ce38	3306	break;
cparata	0:6d69e896ce38	3307	}
cparata	0:6d69e896ce38	3308	return ret;
cparata	0:6d69e896ce38	3309	}
cparata	0:6d69e896ce38	3310
cparata	0:6d69e896ce38	3311	/**
cparata	0:6d69e896ce38	3312	* @brief Disable / Enable I2C interface.[set]
cparata	0:6d69e896ce38	3313	*
cparata	0:6d69e896ce38	3314	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3315	* @param val change the values of i2c_disable in
cparata	0:6d69e896ce38	3316	* reg CTRL4_C
cparata	0:6d69e896ce38	3317	*
cparata	0:6d69e896ce38	3318	*/
cparata	0:6d69e896ce38	3319	int32_t lsm6dso_i2c_interface_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3320	lsm6dso_i2c_disable_t val)
cparata	0:6d69e896ce38	3321	{
cparata	0:6d69e896ce38	3322	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	3323	int32_t ret;
cparata	0:6d69e896ce38	3324
cparata	0:6d69e896ce38	3325	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3326	if (ret == 0) {
cparata	0:6d69e896ce38	3327	reg.i2c_disable = (uint8_t)val;
cparata	0:6d69e896ce38	3328	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3329	}
cparata	0:6d69e896ce38	3330	return ret;
cparata	0:6d69e896ce38	3331	}
cparata	0:6d69e896ce38	3332
cparata	0:6d69e896ce38	3333	/**
cparata	0:6d69e896ce38	3334	* @brief Disable / Enable I2C interface.[get]
cparata	0:6d69e896ce38	3335	*
cparata	0:6d69e896ce38	3336	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3337	* @param val Get the values of i2c_disable in
cparata	0:6d69e896ce38	3338	* reg CTRL4_C
cparata	0:6d69e896ce38	3339	*
cparata	0:6d69e896ce38	3340	*/
cparata	0:6d69e896ce38	3341	int32_t lsm6dso_i2c_interface_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3342	lsm6dso_i2c_disable_t *val)
cparata	0:6d69e896ce38	3343	{
cparata	0:6d69e896ce38	3344	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	3345	int32_t ret;
cparata	0:6d69e896ce38	3346
cparata	0:6d69e896ce38	3347	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3348	switch (reg.i2c_disable) {
cparata	0:6d69e896ce38	3349	case LSM6DSO_I2C_ENABLE:
cparata	0:6d69e896ce38	3350	*val = LSM6DSO_I2C_ENABLE;
cparata	0:6d69e896ce38	3351	break;
cparata	0:6d69e896ce38	3352	case LSM6DSO_I2C_DISABLE:
cparata	0:6d69e896ce38	3353	*val = LSM6DSO_I2C_DISABLE;
cparata	0:6d69e896ce38	3354	break;
cparata	0:6d69e896ce38	3355	default:
cparata	0:6d69e896ce38	3356	*val = LSM6DSO_I2C_ENABLE;
cparata	0:6d69e896ce38	3357	break;
cparata	0:6d69e896ce38	3358	}
cparata	0:6d69e896ce38	3359	return ret;
cparata	0:6d69e896ce38	3360	}
cparata	0:6d69e896ce38	3361
cparata	0:6d69e896ce38	3362	/**
cparata	0:6d69e896ce38	3363	* @brief I3C Enable/Disable communication protocol[.set]
cparata	0:6d69e896ce38	3364	*
cparata	0:6d69e896ce38	3365	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3366	* @param val change the values of i3c_disable
cparata	0:6d69e896ce38	3367	* in reg CTRL9_XL
cparata	0:6d69e896ce38	3368	*
cparata	0:6d69e896ce38	3369	*/
cparata	0:6d69e896ce38	3370	int32_t lsm6dso_i3c_disable_set(lsm6dso_ctx_t *ctx, lsm6dso_i3c_disable_t val)
cparata	0:6d69e896ce38	3371	{
cparata	0:6d69e896ce38	3372	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	0:6d69e896ce38	3373	lsm6dso_ctrl9_xl_t ctrl9_xl;
cparata	0:6d69e896ce38	3374	int32_t ret;
cparata	0:6d69e896ce38	3375
cparata	0:6d69e896ce38	3376	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata	0:6d69e896ce38	3377	if (ret == 0) {
cparata	0:6d69e896ce38	3378	ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
cparata	0:6d69e896ce38	3379	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata	0:6d69e896ce38	3380	}
cparata	0:6d69e896ce38	3381	if (ret == 0) {
cparata	0:6d69e896ce38	3382
cparata	0:6d69e896ce38	3383	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	0:6d69e896ce38	3384	(uint8_t*)&i3c_bus_avb, 1);
cparata	0:6d69e896ce38	3385	}
cparata	0:6d69e896ce38	3386	if (ret == 0) {
cparata	0:6d69e896ce38	3387	i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
cparata	0:6d69e896ce38	3388	ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	0:6d69e896ce38	3389	(uint8_t*)&i3c_bus_avb, 1);
cparata	0:6d69e896ce38	3390	}
cparata	0:6d69e896ce38	3391
cparata	0:6d69e896ce38	3392	return ret;
cparata	0:6d69e896ce38	3393	}
cparata	0:6d69e896ce38	3394
cparata	0:6d69e896ce38	3395	/**
cparata	0:6d69e896ce38	3396	* @brief I3C Enable/Disable communication protocol.[get]
cparata	0:6d69e896ce38	3397	*
cparata	0:6d69e896ce38	3398	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3399	* @param val change the values of i3c_disable in
cparata	0:6d69e896ce38	3400	* reg CTRL9_XL
cparata	0:6d69e896ce38	3401	*
cparata	0:6d69e896ce38	3402	*/
cparata	0:6d69e896ce38	3403	int32_t lsm6dso_i3c_disable_get(lsm6dso_ctx_t ctx, lsm6dso_i3c_disable_t val)
cparata	0:6d69e896ce38	3404	{
cparata	0:6d69e896ce38	3405	lsm6dso_ctrl9_xl_t ctrl9_xl;
cparata	0:6d69e896ce38	3406	lsm6dso_i3c_bus_avb_t i3c_bus_avb;
cparata	0:6d69e896ce38	3407	int32_t ret;
cparata	0:6d69e896ce38	3408
cparata	0:6d69e896ce38	3409	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1);
cparata	0:6d69e896ce38	3410	if (ret == 0) {
cparata	0:6d69e896ce38	3411	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
cparata	0:6d69e896ce38	3412	(uint8_t*)&i3c_bus_avb, 1);
cparata	0:6d69e896ce38	3413
cparata	0:6d69e896ce38	3414	switch ((ctrl9_xl.i3c_disable << 7) \| i3c_bus_avb.i3c_bus_avb_sel) {
cparata	0:6d69e896ce38	3415	case LSM6DSO_I3C_DISABLE:
cparata	0:6d69e896ce38	3416	*val = LSM6DSO_I3C_DISABLE;
cparata	0:6d69e896ce38	3417	break;
cparata	0:6d69e896ce38	3418	case LSM6DSO_I3C_ENABLE_T_50us:
cparata	0:6d69e896ce38	3419	*val = LSM6DSO_I3C_ENABLE_T_50us;
cparata	0:6d69e896ce38	3420	break;
cparata	0:6d69e896ce38	3421	case LSM6DSO_I3C_ENABLE_T_2us:
cparata	0:6d69e896ce38	3422	*val = LSM6DSO_I3C_ENABLE_T_2us;
cparata	0:6d69e896ce38	3423	break;
cparata	0:6d69e896ce38	3424	case LSM6DSO_I3C_ENABLE_T_1ms:
cparata	0:6d69e896ce38	3425	*val = LSM6DSO_I3C_ENABLE_T_1ms;
cparata	0:6d69e896ce38	3426	break;
cparata	0:6d69e896ce38	3427	case LSM6DSO_I3C_ENABLE_T_25ms:
cparata	0:6d69e896ce38	3428	*val = LSM6DSO_I3C_ENABLE_T_25ms;
cparata	0:6d69e896ce38	3429	break;
cparata	0:6d69e896ce38	3430	default:
cparata	0:6d69e896ce38	3431	*val = LSM6DSO_I3C_DISABLE;
cparata	0:6d69e896ce38	3432	break;
cparata	0:6d69e896ce38	3433	}
cparata	0:6d69e896ce38	3434	}
cparata	0:6d69e896ce38	3435	return ret;
cparata	0:6d69e896ce38	3436	}
cparata	0:6d69e896ce38	3437
cparata	0:6d69e896ce38	3438	/**
cparata	0:6d69e896ce38	3439	* @}
cparata	0:6d69e896ce38	3440	*
cparata	0:6d69e896ce38	3441	*/
cparata	0:6d69e896ce38	3442
cparata	0:6d69e896ce38	3443	/**
cparata	0:6d69e896ce38	3444	* @defgroup LSM6DSO_interrupt_pins
cparata	0:6d69e896ce38	3445	* @brief This section groups all the functions that manage interrup pins
cparata	0:6d69e896ce38	3446	* @{
cparata	0:6d69e896ce38	3447	*
cparata	0:6d69e896ce38	3448	*/
cparata	0:6d69e896ce38	3449
cparata	0:6d69e896ce38	3450	/**
cparata	0:6d69e896ce38	3451	* @brief Connect/Disconnect INT1 internal pull-down.[set]
cparata	0:6d69e896ce38	3452	*
cparata	0:6d69e896ce38	3453	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3454	* @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB
cparata	0:6d69e896ce38	3455	*
cparata	0:6d69e896ce38	3456	*/
cparata	0:6d69e896ce38	3457	int32_t lsm6dso_int1_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_int1_pd_en_t val)
cparata	0:6d69e896ce38	3458	{
cparata	0:6d69e896ce38	3459	lsm6dso_i3c_bus_avb_t reg;
cparata	0:6d69e896ce38	3460	int32_t ret;
cparata	0:6d69e896ce38	3461
cparata	0:6d69e896ce38	3462	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3463	if (ret == 0) {
cparata	0:6d69e896ce38	3464	reg.pd_dis_int1 = (uint8_t)val;
cparata	0:6d69e896ce38	3465	ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3466	}
cparata	0:6d69e896ce38	3467	return ret;
cparata	0:6d69e896ce38	3468	}
cparata	0:6d69e896ce38	3469
cparata	0:6d69e896ce38	3470	/**
cparata	0:6d69e896ce38	3471	* @brief Connect/Disconnect INT1 internal pull-down.[get]
cparata	0:6d69e896ce38	3472	*
cparata	0:6d69e896ce38	3473	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3474	* @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
cparata	0:6d69e896ce38	3475	*
cparata	0:6d69e896ce38	3476	*/
cparata	0:6d69e896ce38	3477	int32_t lsm6dso_int1_mode_get(lsm6dso_ctx_t ctx, lsm6dso_int1_pd_en_t val)
cparata	0:6d69e896ce38	3478	{
cparata	0:6d69e896ce38	3479	lsm6dso_i3c_bus_avb_t reg;
cparata	0:6d69e896ce38	3480	int32_t ret;
cparata	0:6d69e896ce38	3481
cparata	0:6d69e896ce38	3482	ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3483	switch (reg.pd_dis_int1) {
cparata	0:6d69e896ce38	3484	case LSM6DSO_PULL_DOWN_DISC:
cparata	0:6d69e896ce38	3485	*val = LSM6DSO_PULL_DOWN_DISC;
cparata	0:6d69e896ce38	3486	break;
cparata	0:6d69e896ce38	3487	case LSM6DSO_PULL_DOWN_CONNECT:
cparata	0:6d69e896ce38	3488	*val = LSM6DSO_PULL_DOWN_CONNECT;
cparata	0:6d69e896ce38	3489	break;
cparata	0:6d69e896ce38	3490	default:
cparata	0:6d69e896ce38	3491	*val = LSM6DSO_PULL_DOWN_DISC;
cparata	0:6d69e896ce38	3492	break;
cparata	0:6d69e896ce38	3493	}
cparata	0:6d69e896ce38	3494	return ret;
cparata	0:6d69e896ce38	3495	}
cparata	0:6d69e896ce38	3496
cparata	0:6d69e896ce38	3497	/**
cparata	0:6d69e896ce38	3498	* @brief Select the signal that need to route on int1 pad.[set]
cparata	0:6d69e896ce38	3499	*
cparata	0:6d69e896ce38	3500	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3501	* @param val struct of registers: INT1_CTRL,
cparata	0:6d69e896ce38	3502	* MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
cparata	0:6d69e896ce38	3503	* FSM_INT1_B
cparata	0:6d69e896ce38	3504	*
cparata	0:6d69e896ce38	3505	*/
cparata	0:6d69e896ce38	3506	int32_t lsm6dso_pin_int1_route_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3507	lsm6dso_pin_int1_route_t *val)
cparata	0:6d69e896ce38	3508	{
cparata	2:4d14e9edf37e	3509	lsm6dso_pin_int2_route_t pin_int2_route;
cparata	0:6d69e896ce38	3510	lsm6dso_tap_cfg2_t tap_cfg2;
cparata	0:6d69e896ce38	3511	int32_t ret;
cparata	0:6d69e896ce38	3512
cparata	0:6d69e896ce38	3513	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	3514	if (ret == 0) {
cparata	0:6d69e896ce38	3515	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
cparata	0:6d69e896ce38	3516	(uint8_t*)&val->emb_func_int1, 1);
cparata	0:6d69e896ce38	3517	}
cparata	0:6d69e896ce38	3518	if (ret == 0) {
cparata	0:6d69e896ce38	3519	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_A,
cparata	0:6d69e896ce38	3520	(uint8_t*)&val->fsm_int1_a, 1);
cparata	0:6d69e896ce38	3521	}
cparata	0:6d69e896ce38	3522	if (ret == 0) {
cparata	0:6d69e896ce38	3523	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_B,
cparata	0:6d69e896ce38	3524	(uint8_t*)&val->fsm_int1_b, 1);
cparata	0:6d69e896ce38	3525	}
cparata	0:6d69e896ce38	3526	if (ret == 0) {
cparata	0:6d69e896ce38	3527	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	3528	}
cparata	2:4d14e9edf37e	3529
cparata	2:4d14e9edf37e	3530	if (ret == 0) {
cparata	2:4d14e9edf37e	3531	if ( ( val->emb_func_int1.int1_fsm_lc
cparata	2:4d14e9edf37e	3532	\| val->emb_func_int1.int1_sig_mot
cparata	2:4d14e9edf37e	3533	\| val->emb_func_int1.int1_step_detector
cparata	2:4d14e9edf37e	3534	\| val->emb_func_int1.int1_tilt
cparata	2:4d14e9edf37e	3535	\| val->fsm_int1_a.int1_fsm1
cparata	2:4d14e9edf37e	3536	\| val->fsm_int1_a.int1_fsm2
cparata	2:4d14e9edf37e	3537	\| val->fsm_int1_a.int1_fsm3
cparata	2:4d14e9edf37e	3538	\| val->fsm_int1_a.int1_fsm4
cparata	2:4d14e9edf37e	3539	\| val->fsm_int1_a.int1_fsm5
cparata	2:4d14e9edf37e	3540	\| val->fsm_int1_a.int1_fsm6
cparata	2:4d14e9edf37e	3541	\| val->fsm_int1_a.int1_fsm7
cparata	2:4d14e9edf37e	3542	\| val->fsm_int1_a.int1_fsm8
cparata	2:4d14e9edf37e	3543	\| val->fsm_int1_b.int1_fsm9
cparata	2:4d14e9edf37e	3544	\| val->fsm_int1_b.int1_fsm10
cparata	2:4d14e9edf37e	3545	\| val->fsm_int1_b.int1_fsm11
cparata	2:4d14e9edf37e	3546	\| val->fsm_int1_b.int1_fsm12
cparata	2:4d14e9edf37e	3547	\| val->fsm_int1_b.int1_fsm13
cparata	2:4d14e9edf37e	3548	\| val->fsm_int1_b.int1_fsm14
cparata	2:4d14e9edf37e	3549	\| val->fsm_int1_b.int1_fsm15
cparata	2:4d14e9edf37e	3550	\| val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE){
cparata	0:6d69e896ce38	3551	val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
cparata	0:6d69e896ce38	3552	}
cparata	0:6d69e896ce38	3553	else{
cparata	0:6d69e896ce38	3554	val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
cparata	0:6d69e896ce38	3555	}
cparata	0:6d69e896ce38	3556	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT1_CTRL,
cparata	0:6d69e896ce38	3557	(uint8_t*)&val->int1_ctrl, 1);
cparata	0:6d69e896ce38	3558	}
cparata	0:6d69e896ce38	3559	if (ret == 0) {
cparata	0:6d69e896ce38	3560	ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t*)&val->md1_cfg, 1);
cparata	0:6d69e896ce38	3561	}
cparata	0:6d69e896ce38	3562	if (ret == 0) {
cparata	0:6d69e896ce38	3563	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	0:6d69e896ce38	3564	}
cparata	2:4d14e9edf37e	3565
cparata	2:4d14e9edf37e	3566	if (ret == 0) {
cparata	2:4d14e9edf37e	3567	ret = lsm6dso_pin_int2_route_get(ctx, &pin_int2_route);
cparata	2:4d14e9edf37e	3568	}
cparata	2:4d14e9edf37e	3569	if (ret == 0) {
cparata	2:4d14e9edf37e	3570	if ( ( pin_int2_route.int2_ctrl.int2_cnt_bdr
cparata	2:4d14e9edf37e	3571	\| pin_int2_route.int2_ctrl.int2_drdy_g
cparata	2:4d14e9edf37e	3572	\| pin_int2_route.int2_ctrl.int2_drdy_temp
cparata	2:4d14e9edf37e	3573	\| pin_int2_route.int2_ctrl.int2_drdy_xl
cparata	2:4d14e9edf37e	3574	\| pin_int2_route.int2_ctrl.int2_fifo_full
cparata	2:4d14e9edf37e	3575	\| pin_int2_route.int2_ctrl.int2_fifo_ovr
cparata	2:4d14e9edf37e	3576	\| pin_int2_route.int2_ctrl.int2_fifo_th
cparata	2:4d14e9edf37e	3577	\| pin_int2_route.md2_cfg.int2_6d
cparata	2:4d14e9edf37e	3578	\| pin_int2_route.md2_cfg.int2_double_tap
cparata	2:4d14e9edf37e	3579	\| pin_int2_route.md2_cfg.int2_ff
cparata	2:4d14e9edf37e	3580	\| pin_int2_route.md2_cfg.int2_wu
cparata	2:4d14e9edf37e	3581	\| pin_int2_route.md2_cfg.int2_single_tap
cparata	2:4d14e9edf37e	3582	\| pin_int2_route.md2_cfg.int2_sleep_change
cparata	2:4d14e9edf37e	3583	\| val->int1_ctrl.den_drdy_flag
cparata	2:4d14e9edf37e	3584	\| val->int1_ctrl.int1_boot
cparata	2:4d14e9edf37e	3585	\| val->int1_ctrl.int1_cnt_bdr
cparata	2:4d14e9edf37e	3586	\| val->int1_ctrl.int1_drdy_g
cparata	2:4d14e9edf37e	3587	\| val->int1_ctrl.int1_drdy_xl
cparata	2:4d14e9edf37e	3588	\| val->int1_ctrl.int1_fifo_full
cparata	2:4d14e9edf37e	3589	\| val->int1_ctrl.int1_fifo_ovr
cparata	2:4d14e9edf37e	3590	\| val->int1_ctrl.int1_fifo_th
cparata	2:4d14e9edf37e	3591	\| val->md1_cfg.int1_6d
cparata	2:4d14e9edf37e	3592	\| val->md1_cfg.int1_double_tap
cparata	2:4d14e9edf37e	3593	\| val->md1_cfg.int1_ff
cparata	2:4d14e9edf37e	3594	\| val->md1_cfg.int1_wu
cparata	2:4d14e9edf37e	3595	\| val->md1_cfg.int1_single_tap
cparata	2:4d14e9edf37e	3596	\| val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) {
cparata	0:6d69e896ce38	3597	tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata	0:6d69e896ce38	3598	}
cparata	0:6d69e896ce38	3599	else{
cparata	0:6d69e896ce38	3600	tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata	0:6d69e896ce38	3601	}
cparata	0:6d69e896ce38	3602	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	0:6d69e896ce38	3603	}
cparata	0:6d69e896ce38	3604	return ret;
cparata	0:6d69e896ce38	3605	}
cparata	0:6d69e896ce38	3606
cparata	0:6d69e896ce38	3607	/**
cparata	0:6d69e896ce38	3608	* @brief Select the signal that need to route on int1 pad.[get]
cparata	0:6d69e896ce38	3609	*
cparata	0:6d69e896ce38	3610	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3611	* @param val struct of registers: INT1_CTRL, MD1_CFG,
cparata	0:6d69e896ce38	3612	* EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
cparata	0:6d69e896ce38	3613	*
cparata	0:6d69e896ce38	3614	*/
cparata	0:6d69e896ce38	3615	int32_t lsm6dso_pin_int1_route_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3616	lsm6dso_pin_int1_route_t *val)
cparata	0:6d69e896ce38	3617	{
cparata	0:6d69e896ce38	3618	int32_t ret;
cparata	0:6d69e896ce38	3619
cparata	0:6d69e896ce38	3620	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	3621	if (ret == 0) {
cparata	0:6d69e896ce38	3622	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
cparata	0:6d69e896ce38	3623	(uint8_t*)&val->emb_func_int1, 1);
cparata	0:6d69e896ce38	3624	}
cparata	0:6d69e896ce38	3625	if (ret == 0) {
cparata	0:6d69e896ce38	3626	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_A,
cparata	0:6d69e896ce38	3627	(uint8_t*)&val->fsm_int1_a, 1);
cparata	0:6d69e896ce38	3628	}
cparata	0:6d69e896ce38	3629	if (ret == 0) {
cparata	0:6d69e896ce38	3630	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_B,
cparata	0:6d69e896ce38	3631	(uint8_t*)&val->fsm_int1_b, 1);
cparata	0:6d69e896ce38	3632	}
cparata	0:6d69e896ce38	3633	if (ret == 0) {
cparata	0:6d69e896ce38	3634	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	3635	}
cparata	0:6d69e896ce38	3636	if (ret == 0) {
cparata	0:6d69e896ce38	3637
cparata	0:6d69e896ce38	3638	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT1_CTRL,
cparata	0:6d69e896ce38	3639	(uint8_t*)&val->int1_ctrl, 1);
cparata	0:6d69e896ce38	3640	}
cparata	0:6d69e896ce38	3641	if (ret == 0) {
cparata	0:6d69e896ce38	3642	ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t*)&val->md1_cfg, 1);
cparata	0:6d69e896ce38	3643	}
cparata	0:6d69e896ce38	3644
cparata	0:6d69e896ce38	3645	return ret;
cparata	0:6d69e896ce38	3646	}
cparata	0:6d69e896ce38	3647
cparata	0:6d69e896ce38	3648	/**
cparata	0:6d69e896ce38	3649	* @brief Select the signal that need to route on int2 pad.[set]
cparata	0:6d69e896ce38	3650	*
cparata	0:6d69e896ce38	3651	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3652	* @param val union of registers INT2_CTRL, MD2_CFG,
cparata	0:6d69e896ce38	3653	* EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
cparata	0:6d69e896ce38	3654	*
cparata	0:6d69e896ce38	3655	*/
cparata	0:6d69e896ce38	3656	int32_t lsm6dso_pin_int2_route_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3657	lsm6dso_pin_int2_route_t *val)
cparata	0:6d69e896ce38	3658	{
cparata	2:4d14e9edf37e	3659	lsm6dso_pin_int1_route_t pin_int1_route;
cparata	0:6d69e896ce38	3660	lsm6dso_tap_cfg2_t tap_cfg2;
cparata	0:6d69e896ce38	3661	int32_t ret;
cparata	0:6d69e896ce38	3662
cparata	0:6d69e896ce38	3663	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	3664	if (ret == 0) {
cparata	0:6d69e896ce38	3665	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
cparata	0:6d69e896ce38	3666	(uint8_t*)&val->emb_func_int2, 1);
cparata	0:6d69e896ce38	3667	}
cparata	0:6d69e896ce38	3668	if (ret == 0) {
cparata	0:6d69e896ce38	3669	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_A,
cparata	0:6d69e896ce38	3670	(uint8_t*)&val->fsm_int2_a, 1);
cparata	0:6d69e896ce38	3671	}
cparata	0:6d69e896ce38	3672	if (ret == 0) {
cparata	0:6d69e896ce38	3673	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_B,
cparata	0:6d69e896ce38	3674	(uint8_t*)&val->fsm_int2_b, 1);
cparata	0:6d69e896ce38	3675	}
cparata	0:6d69e896ce38	3676	if (ret == 0) {
cparata	0:6d69e896ce38	3677	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	3678	}
cparata	2:4d14e9edf37e	3679
cparata	0:6d69e896ce38	3680	if (ret == 0) {
cparata	0:6d69e896ce38	3681	if (( val->emb_func_int2.int2_fsm_lc
cparata	2:4d14e9edf37e	3682	\| val->emb_func_int2.int2_sig_mot
cparata	2:4d14e9edf37e	3683	\| val->emb_func_int2.int2_step_detector
cparata	2:4d14e9edf37e	3684	\| val->emb_func_int2.int2_tilt
cparata	2:4d14e9edf37e	3685	\| val->fsm_int2_a.int2_fsm1
cparata	2:4d14e9edf37e	3686	\| val->fsm_int2_a.int2_fsm2
cparata	2:4d14e9edf37e	3687	\| val->fsm_int2_a.int2_fsm3
cparata	2:4d14e9edf37e	3688	\| val->fsm_int2_a.int2_fsm4
cparata	2:4d14e9edf37e	3689	\| val->fsm_int2_a.int2_fsm5
cparata	2:4d14e9edf37e	3690	\| val->fsm_int2_a.int2_fsm6
cparata	2:4d14e9edf37e	3691	\| val->fsm_int2_a.int2_fsm7
cparata	2:4d14e9edf37e	3692	\| val->fsm_int2_a.int2_fsm8
cparata	2:4d14e9edf37e	3693	\| val->fsm_int2_b.int2_fsm9
cparata	2:4d14e9edf37e	3694	\| val->fsm_int2_b.int2_fsm10
cparata	2:4d14e9edf37e	3695	\| val->fsm_int2_b.int2_fsm11
cparata	2:4d14e9edf37e	3696	\| val->fsm_int2_b.int2_fsm12
cparata	2:4d14e9edf37e	3697	\| val->fsm_int2_b.int2_fsm13
cparata	2:4d14e9edf37e	3698	\| val->fsm_int2_b.int2_fsm14
cparata	2:4d14e9edf37e	3699	\| val->fsm_int2_b.int2_fsm15
cparata	2:4d14e9edf37e	3700	\| val->fsm_int2_b.int2_fsm16 )!= PROPERTY_DISABLE ){
cparata	0:6d69e896ce38	3701	val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
cparata	0:6d69e896ce38	3702	}
cparata	0:6d69e896ce38	3703	else{
cparata	0:6d69e896ce38	3704	val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
cparata	0:6d69e896ce38	3705	}
cparata	0:6d69e896ce38	3706	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL,
cparata	0:6d69e896ce38	3707	(uint8_t*)&val->int2_ctrl, 1);
cparata	0:6d69e896ce38	3708	}
cparata	0:6d69e896ce38	3709	if (ret == 0) {
cparata	0:6d69e896ce38	3710	ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&val->md2_cfg, 1);
cparata	0:6d69e896ce38	3711	}
cparata	0:6d69e896ce38	3712	if (ret == 0) {
cparata	0:6d69e896ce38	3713	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	0:6d69e896ce38	3714	}
cparata	2:4d14e9edf37e	3715
cparata	2:4d14e9edf37e	3716	if (ret == 0) {
cparata	2:4d14e9edf37e	3717	ret = lsm6dso_pin_int1_route_get(ctx, &pin_int1_route);
cparata	2:4d14e9edf37e	3718	}
cparata	2:4d14e9edf37e	3719
cparata	0:6d69e896ce38	3720	if (ret == 0) {
cparata	0:6d69e896ce38	3721	if ( ( val->int2_ctrl.int2_cnt_bdr
cparata	0:6d69e896ce38	3722	\| val->int2_ctrl.int2_drdy_g
cparata	0:6d69e896ce38	3723	\| val->int2_ctrl.int2_drdy_temp
cparata	0:6d69e896ce38	3724	\| val->int2_ctrl.int2_drdy_xl
cparata	0:6d69e896ce38	3725	\| val->int2_ctrl.int2_fifo_full
cparata	0:6d69e896ce38	3726	\| val->int2_ctrl.int2_fifo_ovr
cparata	0:6d69e896ce38	3727	\| val->int2_ctrl.int2_fifo_th
cparata	0:6d69e896ce38	3728	\| val->md2_cfg.int2_6d
cparata	0:6d69e896ce38	3729	\| val->md2_cfg.int2_double_tap
cparata	2:4d14e9edf37e	3730	\| val->md2_cfg.int2_ff
cparata	2:4d14e9edf37e	3731	\| val->md2_cfg.int2_wu
cparata	0:6d69e896ce38	3732	\| val->md2_cfg.int2_single_tap
cparata	2:4d14e9edf37e	3733	\| val->md2_cfg.int2_sleep_change
cparata	2:4d14e9edf37e	3734	\| pin_int1_route.int1_ctrl.den_drdy_flag
cparata	2:4d14e9edf37e	3735	\| pin_int1_route.int1_ctrl.int1_boot
cparata	2:4d14e9edf37e	3736	\| pin_int1_route.int1_ctrl.int1_cnt_bdr
cparata	2:4d14e9edf37e	3737	\| pin_int1_route.int1_ctrl.int1_drdy_g
cparata	2:4d14e9edf37e	3738	\| pin_int1_route.int1_ctrl.int1_drdy_xl
cparata	2:4d14e9edf37e	3739	\| pin_int1_route.int1_ctrl.int1_fifo_full
cparata	2:4d14e9edf37e	3740	\| pin_int1_route.int1_ctrl.int1_fifo_ovr
cparata	2:4d14e9edf37e	3741	\| pin_int1_route.int1_ctrl.int1_fifo_th
cparata	2:4d14e9edf37e	3742	\| pin_int1_route.md1_cfg.int1_6d
cparata	2:4d14e9edf37e	3743	\| pin_int1_route.md1_cfg.int1_double_tap
cparata	2:4d14e9edf37e	3744	\| pin_int1_route.md1_cfg.int1_ff
cparata	2:4d14e9edf37e	3745	\| pin_int1_route.md1_cfg.int1_wu
cparata	2:4d14e9edf37e	3746	\| pin_int1_route.md1_cfg.int1_single_tap
cparata	2:4d14e9edf37e	3747	\| pin_int1_route.md1_cfg.int1_sleep_change ) != PROPERTY_DISABLE) {
cparata	0:6d69e896ce38	3748	tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
cparata	0:6d69e896ce38	3749	}
cparata	0:6d69e896ce38	3750	else{
cparata	0:6d69e896ce38	3751	tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
cparata	0:6d69e896ce38	3752	}
cparata	0:6d69e896ce38	3753	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1);
cparata	0:6d69e896ce38	3754	}
cparata	0:6d69e896ce38	3755	return ret;
cparata	0:6d69e896ce38	3756	}
cparata	0:6d69e896ce38	3757
cparata	0:6d69e896ce38	3758	/**
cparata	0:6d69e896ce38	3759	* @brief Select the signal that need to route on int2 pad.[get]
cparata	0:6d69e896ce38	3760	*
cparata	0:6d69e896ce38	3761	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3762	* @param val union of registers INT2_CTRL, MD2_CFG,
cparata	0:6d69e896ce38	3763	* EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
cparata	0:6d69e896ce38	3764	*
cparata	0:6d69e896ce38	3765	*/
cparata	0:6d69e896ce38	3766	int32_t lsm6dso_pin_int2_route_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	3767	lsm6dso_pin_int2_route_t *val)
cparata	0:6d69e896ce38	3768	{
cparata	0:6d69e896ce38	3769	int32_t ret;
cparata	0:6d69e896ce38	3770
cparata	0:6d69e896ce38	3771	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	3772	if (ret == 0) {
cparata	0:6d69e896ce38	3773	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
cparata	0:6d69e896ce38	3774	(uint8_t*)&val->emb_func_int2, 1);
cparata	0:6d69e896ce38	3775	}
cparata	0:6d69e896ce38	3776	if (ret == 0) {
cparata	0:6d69e896ce38	3777	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_A,
cparata	0:6d69e896ce38	3778	(uint8_t*)&val->fsm_int2_a, 1);
cparata	0:6d69e896ce38	3779	}
cparata	0:6d69e896ce38	3780	if (ret == 0) {
cparata	0:6d69e896ce38	3781	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_B,
cparata	0:6d69e896ce38	3782	(uint8_t*)&val->fsm_int2_b, 1);
cparata	0:6d69e896ce38	3783	}
cparata	0:6d69e896ce38	3784	if (ret == 0) {
cparata	0:6d69e896ce38	3785	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	3786	}
cparata	0:6d69e896ce38	3787	if (ret == 0) {
cparata	0:6d69e896ce38	3788
cparata	0:6d69e896ce38	3789	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
cparata	0:6d69e896ce38	3790	(uint8_t*)&val->int2_ctrl, 1);
cparata	0:6d69e896ce38	3791	}
cparata	0:6d69e896ce38	3792	if (ret == 0) {
cparata	0:6d69e896ce38	3793	ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&val->md2_cfg, 1);
cparata	0:6d69e896ce38	3794	}
cparata	0:6d69e896ce38	3795	return ret;
cparata	0:6d69e896ce38	3796	}
cparata	0:6d69e896ce38	3797
cparata	0:6d69e896ce38	3798	/**
cparata	0:6d69e896ce38	3799	* @brief Push-pull/open drain selection on interrupt pads.[set]
cparata	0:6d69e896ce38	3800	*
cparata	0:6d69e896ce38	3801	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3802	* @param val change the values of pp_od in reg CTRL3_C
cparata	0:6d69e896ce38	3803	*
cparata	0:6d69e896ce38	3804	*/
cparata	0:6d69e896ce38	3805	int32_t lsm6dso_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_pp_od_t val)
cparata	0:6d69e896ce38	3806	{
cparata	0:6d69e896ce38	3807	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	3808	int32_t ret;
cparata	0:6d69e896ce38	3809
cparata	0:6d69e896ce38	3810	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3811	if (ret == 0) {
cparata	0:6d69e896ce38	3812	reg.pp_od = (uint8_t)val;
cparata	0:6d69e896ce38	3813	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3814	}
cparata	0:6d69e896ce38	3815	return ret;
cparata	0:6d69e896ce38	3816	}
cparata	0:6d69e896ce38	3817
cparata	0:6d69e896ce38	3818	/**
cparata	0:6d69e896ce38	3819	* @brief Push-pull/open drain selection on interrupt pads.[get]
cparata	0:6d69e896ce38	3820	*
cparata	0:6d69e896ce38	3821	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3822	* @param val Get the values of pp_od in reg CTRL3_C
cparata	0:6d69e896ce38	3823	*
cparata	0:6d69e896ce38	3824	*/
cparata	0:6d69e896ce38	3825	int32_t lsm6dso_pin_mode_get(lsm6dso_ctx_t ctx, lsm6dso_pp_od_t val)
cparata	0:6d69e896ce38	3826	{
cparata	0:6d69e896ce38	3827	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	3828	int32_t ret;
cparata	0:6d69e896ce38	3829
cparata	0:6d69e896ce38	3830	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3831
cparata	0:6d69e896ce38	3832	switch (reg.pp_od) {
cparata	0:6d69e896ce38	3833	case LSM6DSO_PUSH_PULL:
cparata	0:6d69e896ce38	3834	*val = LSM6DSO_PUSH_PULL;
cparata	0:6d69e896ce38	3835	break;
cparata	0:6d69e896ce38	3836	case LSM6DSO_OPEN_DRAIN:
cparata	0:6d69e896ce38	3837	*val = LSM6DSO_OPEN_DRAIN;
cparata	0:6d69e896ce38	3838	break;
cparata	0:6d69e896ce38	3839	default:
cparata	0:6d69e896ce38	3840	*val = LSM6DSO_PUSH_PULL;
cparata	0:6d69e896ce38	3841	break;
cparata	0:6d69e896ce38	3842	}
cparata	0:6d69e896ce38	3843	return ret;
cparata	0:6d69e896ce38	3844	}
cparata	0:6d69e896ce38	3845
cparata	0:6d69e896ce38	3846	/**
cparata	0:6d69e896ce38	3847	* @brief Interrupt active-high/low.[set]
cparata	0:6d69e896ce38	3848	*
cparata	0:6d69e896ce38	3849	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3850	* @param val change the values of h_lactive in reg CTRL3_C
cparata	0:6d69e896ce38	3851	*
cparata	0:6d69e896ce38	3852	*/
cparata	0:6d69e896ce38	3853	int32_t lsm6dso_pin_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_h_lactive_t val)
cparata	0:6d69e896ce38	3854	{
cparata	0:6d69e896ce38	3855	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	3856	int32_t ret;
cparata	0:6d69e896ce38	3857
cparata	0:6d69e896ce38	3858	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3859	if (ret == 0) {
cparata	0:6d69e896ce38	3860	reg.h_lactive = (uint8_t)val;
cparata	0:6d69e896ce38	3861	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3862	}
cparata	0:6d69e896ce38	3863
cparata	0:6d69e896ce38	3864	return ret;
cparata	0:6d69e896ce38	3865	}
cparata	0:6d69e896ce38	3866
cparata	0:6d69e896ce38	3867	/**
cparata	0:6d69e896ce38	3868	* @brief Interrupt active-high/low.[get]
cparata	0:6d69e896ce38	3869	*
cparata	0:6d69e896ce38	3870	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3871	* @param val Get the values of h_lactive in reg CTRL3_C
cparata	0:6d69e896ce38	3872	*
cparata	0:6d69e896ce38	3873	*/
cparata	0:6d69e896ce38	3874	int32_t lsm6dso_pin_polarity_get(lsm6dso_ctx_t ctx, lsm6dso_h_lactive_t val)
cparata	0:6d69e896ce38	3875	{
cparata	0:6d69e896ce38	3876	lsm6dso_ctrl3_c_t reg;
cparata	0:6d69e896ce38	3877	int32_t ret;
cparata	0:6d69e896ce38	3878
cparata	0:6d69e896ce38	3879	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3880
cparata	0:6d69e896ce38	3881	switch (reg.h_lactive) {
cparata	0:6d69e896ce38	3882	case LSM6DSO_ACTIVE_HIGH:
cparata	0:6d69e896ce38	3883	*val = LSM6DSO_ACTIVE_HIGH;
cparata	0:6d69e896ce38	3884	break;
cparata	0:6d69e896ce38	3885	case LSM6DSO_ACTIVE_LOW:
cparata	0:6d69e896ce38	3886	*val = LSM6DSO_ACTIVE_LOW;
cparata	0:6d69e896ce38	3887	break;
cparata	0:6d69e896ce38	3888	default:
cparata	0:6d69e896ce38	3889	*val = LSM6DSO_ACTIVE_HIGH;
cparata	0:6d69e896ce38	3890	break;
cparata	0:6d69e896ce38	3891	}
cparata	0:6d69e896ce38	3892	return ret;
cparata	0:6d69e896ce38	3893	}
cparata	0:6d69e896ce38	3894
cparata	0:6d69e896ce38	3895	/**
cparata	0:6d69e896ce38	3896	* @brief All interrupt signals become available on INT1 pin.[set]
cparata	0:6d69e896ce38	3897	*
cparata	0:6d69e896ce38	3898	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3899	* @param val change the values of int2_on_int1 in reg CTRL4_C
cparata	0:6d69e896ce38	3900	*
cparata	0:6d69e896ce38	3901	*/
cparata	0:6d69e896ce38	3902	int32_t lsm6dso_all_on_int1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	3903	{
cparata	0:6d69e896ce38	3904	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	3905	int32_t ret;
cparata	0:6d69e896ce38	3906
cparata	0:6d69e896ce38	3907	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3908	if (ret == 0) {
cparata	0:6d69e896ce38	3909	reg.int2_on_int1 = val;
cparata	0:6d69e896ce38	3910	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3911	}
cparata	0:6d69e896ce38	3912
cparata	0:6d69e896ce38	3913	return ret;
cparata	0:6d69e896ce38	3914	}
cparata	0:6d69e896ce38	3915
cparata	0:6d69e896ce38	3916	/**
cparata	0:6d69e896ce38	3917	* @brief All interrupt signals become available on INT1 pin.[get]
cparata	0:6d69e896ce38	3918	*
cparata	0:6d69e896ce38	3919	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3920	* @param val change the values of int2_on_int1 in reg CTRL4_C
cparata	0:6d69e896ce38	3921	*
cparata	0:6d69e896ce38	3922	*/
cparata	0:6d69e896ce38	3923	int32_t lsm6dso_all_on_int1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	3924	{
cparata	0:6d69e896ce38	3925	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	3926	int32_t ret;
cparata	0:6d69e896ce38	3927
cparata	0:6d69e896ce38	3928	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	3929	*val = reg.int2_on_int1;
cparata	0:6d69e896ce38	3930
cparata	0:6d69e896ce38	3931	return ret;
cparata	0:6d69e896ce38	3932	}
cparata	0:6d69e896ce38	3933
cparata	0:6d69e896ce38	3934	/**
cparata	0:6d69e896ce38	3935	* @brief Interrupt notification mode.[set]
cparata	0:6d69e896ce38	3936	*
cparata	0:6d69e896ce38	3937	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3938	* @param val change the values of lir in reg TAP_CFG0
cparata	0:6d69e896ce38	3939	*
cparata	0:6d69e896ce38	3940	*/
cparata	0:6d69e896ce38	3941	int32_t lsm6dso_int_notification_set(lsm6dso_ctx_t *ctx, lsm6dso_lir_t val)
cparata	0:6d69e896ce38	3942	{
cparata	0:6d69e896ce38	3943	lsm6dso_tap_cfg0_t tap_cfg0;
cparata	0:6d69e896ce38	3944	lsm6dso_page_rw_t page_rw;
cparata	0:6d69e896ce38	3945	int32_t ret;
cparata	0:6d69e896ce38	3946
cparata	0:6d69e896ce38	3947	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	0:6d69e896ce38	3948	if (ret == 0) {
cparata	0:6d69e896ce38	3949	tap_cfg0.lir = (uint8_t)val & 0x01U;
cparata	0:6d69e896ce38	3950	tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
cparata	0:6d69e896ce38	3951	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	0:6d69e896ce38	3952	}
cparata	0:6d69e896ce38	3953	if (ret == 0) {
cparata	0:6d69e896ce38	3954
cparata	0:6d69e896ce38	3955	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	3956	}
cparata	0:6d69e896ce38	3957	if (ret == 0) {
cparata	0:6d69e896ce38	3958	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	3959	}
cparata	0:6d69e896ce38	3960	if (ret == 0) {
cparata	0:6d69e896ce38	3961	page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
cparata	0:6d69e896ce38	3962	ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	3963	}
cparata	0:6d69e896ce38	3964	if (ret == 0) {
cparata	0:6d69e896ce38	3965	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	3966	}
cparata	0:6d69e896ce38	3967
cparata	0:6d69e896ce38	3968	return ret;
cparata	0:6d69e896ce38	3969	}
cparata	0:6d69e896ce38	3970
cparata	0:6d69e896ce38	3971	/**
cparata	0:6d69e896ce38	3972	* @brief Interrupt notification mode.[get]
cparata	0:6d69e896ce38	3973	*
cparata	0:6d69e896ce38	3974	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	3975	* @param val Get the values of lir in reg TAP_CFG0
cparata	0:6d69e896ce38	3976	*
cparata	0:6d69e896ce38	3977	*/
cparata	0:6d69e896ce38	3978	int32_t lsm6dso_int_notification_get(lsm6dso_ctx_t ctx, lsm6dso_lir_t val)
cparata	0:6d69e896ce38	3979	{
cparata	0:6d69e896ce38	3980	lsm6dso_tap_cfg0_t tap_cfg0;
cparata	0:6d69e896ce38	3981	lsm6dso_page_rw_t page_rw;
cparata	0:6d69e896ce38	3982	int32_t ret;
cparata	0:6d69e896ce38	3983
cparata	0:6d69e896ce38	3984
cparata	0:6d69e896ce38	3985	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1);
cparata	0:6d69e896ce38	3986	if (ret == 0) {
cparata	0:6d69e896ce38	3987
cparata	0:6d69e896ce38	3988	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	3989	}
cparata	0:6d69e896ce38	3990	if (ret == 0) {
cparata	0:6d69e896ce38	3991	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	3992	}
cparata	0:6d69e896ce38	3993	if (ret == 0) {
cparata	0:6d69e896ce38	3994	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	3995	}
cparata	0:6d69e896ce38	3996	if (ret == 0) {
cparata	0:6d69e896ce38	3997	switch ((page_rw.emb_func_lir << 1) \| tap_cfg0.lir) {
cparata	0:6d69e896ce38	3998	case LSM6DSO_ALL_INT_PULSED:
cparata	0:6d69e896ce38	3999	*val = LSM6DSO_ALL_INT_PULSED;
cparata	0:6d69e896ce38	4000	break;
cparata	0:6d69e896ce38	4001	case LSM6DSO_BASE_LATCHED_EMB_PULSED:
cparata	0:6d69e896ce38	4002	*val = LSM6DSO_BASE_LATCHED_EMB_PULSED;
cparata	0:6d69e896ce38	4003	break;
cparata	0:6d69e896ce38	4004	case LSM6DSO_BASE_PULSED_EMB_LATCHED:
cparata	0:6d69e896ce38	4005	*val = LSM6DSO_BASE_PULSED_EMB_LATCHED;
cparata	0:6d69e896ce38	4006	break;
cparata	0:6d69e896ce38	4007	case LSM6DSO_ALL_INT_LATCHED:
cparata	0:6d69e896ce38	4008	*val = LSM6DSO_ALL_INT_LATCHED;
cparata	0:6d69e896ce38	4009	break;
cparata	0:6d69e896ce38	4010	default:
cparata	0:6d69e896ce38	4011	*val = LSM6DSO_ALL_INT_PULSED;
cparata	0:6d69e896ce38	4012	break;
cparata	0:6d69e896ce38	4013	}
cparata	0:6d69e896ce38	4014	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	4015	}
cparata	0:6d69e896ce38	4016	if (ret == 0) {
cparata	0:6d69e896ce38	4017	ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1);
cparata	0:6d69e896ce38	4018	}
cparata	0:6d69e896ce38	4019	if (ret == 0) {
cparata	0:6d69e896ce38	4020	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	4021	}
cparata	0:6d69e896ce38	4022
cparata	0:6d69e896ce38	4023	return ret;
cparata	0:6d69e896ce38	4024	}
cparata	0:6d69e896ce38	4025
cparata	0:6d69e896ce38	4026	/**
cparata	0:6d69e896ce38	4027	* @}
cparata	0:6d69e896ce38	4028	*
cparata	0:6d69e896ce38	4029	*/
cparata	0:6d69e896ce38	4030
cparata	0:6d69e896ce38	4031	/**
cparata	0:6d69e896ce38	4032	* @defgroup LSM6DSO_Wake_Up_event
cparata	0:6d69e896ce38	4033	* @brief This section groups all the functions that manage the Wake Up
cparata	0:6d69e896ce38	4034	* event generation.
cparata	0:6d69e896ce38	4035	* @{
cparata	0:6d69e896ce38	4036	*
cparata	0:6d69e896ce38	4037	*/
cparata	0:6d69e896ce38	4038
cparata	0:6d69e896ce38	4039	/**
cparata	0:6d69e896ce38	4040	* @brief Weight of 1 LSB of wakeup threshold.[set]
cparata	0:6d69e896ce38	4041	* 0: 1 LSB =FS_XL / 64
cparata	0:6d69e896ce38	4042	* 1: 1 LSB = FS_XL / 256
cparata	0:6d69e896ce38	4043	*
cparata	0:6d69e896ce38	4044	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4045	* @param val change the values of wake_ths_w in
cparata	0:6d69e896ce38	4046	* reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4047	*
cparata	0:6d69e896ce38	4048	*/
cparata	0:6d69e896ce38	4049	int32_t lsm6dso_wkup_ths_weight_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4050	lsm6dso_wake_ths_w_t val)
cparata	0:6d69e896ce38	4051	{
cparata	0:6d69e896ce38	4052	lsm6dso_wake_up_dur_t reg;
cparata	0:6d69e896ce38	4053	int32_t ret;
cparata	0:6d69e896ce38	4054
cparata	0:6d69e896ce38	4055	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4056	if (ret == 0) {
cparata	0:6d69e896ce38	4057	reg.wake_ths_w = (uint8_t)val;
cparata	0:6d69e896ce38	4058	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4059	}
cparata	0:6d69e896ce38	4060	return ret;
cparata	0:6d69e896ce38	4061	}
cparata	0:6d69e896ce38	4062
cparata	0:6d69e896ce38	4063	/**
cparata	0:6d69e896ce38	4064	* @brief Weight of 1 LSB of wakeup threshold.[get]
cparata	0:6d69e896ce38	4065	* 0: 1 LSB =FS_XL / 64
cparata	0:6d69e896ce38	4066	* 1: 1 LSB = FS_XL / 256
cparata	0:6d69e896ce38	4067	*
cparata	0:6d69e896ce38	4068	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4069	* @param val Get the values of wake_ths_w in
cparata	0:6d69e896ce38	4070	* reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4071	*
cparata	0:6d69e896ce38	4072	*/
cparata	0:6d69e896ce38	4073	int32_t lsm6dso_wkup_ths_weight_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4074	lsm6dso_wake_ths_w_t *val)
cparata	0:6d69e896ce38	4075	{
cparata	0:6d69e896ce38	4076	lsm6dso_wake_up_dur_t reg;
cparata	0:6d69e896ce38	4077	int32_t ret;
cparata	0:6d69e896ce38	4078
cparata	0:6d69e896ce38	4079	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4080
cparata	0:6d69e896ce38	4081	switch (reg.wake_ths_w) {
cparata	0:6d69e896ce38	4082	case LSM6DSO_LSb_FS_DIV_64:
cparata	0:6d69e896ce38	4083	*val = LSM6DSO_LSb_FS_DIV_64;
cparata	0:6d69e896ce38	4084	break;
cparata	0:6d69e896ce38	4085	case LSM6DSO_LSb_FS_DIV_256:
cparata	0:6d69e896ce38	4086	*val = LSM6DSO_LSb_FS_DIV_256;
cparata	0:6d69e896ce38	4087	break;
cparata	0:6d69e896ce38	4088	default:
cparata	0:6d69e896ce38	4089	*val = LSM6DSO_LSb_FS_DIV_64;
cparata	0:6d69e896ce38	4090	break;
cparata	0:6d69e896ce38	4091	}
cparata	0:6d69e896ce38	4092	return ret;
cparata	0:6d69e896ce38	4093	}
cparata	0:6d69e896ce38	4094
cparata	0:6d69e896ce38	4095	/**
cparata	0:6d69e896ce38	4096	* @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata	0:6d69e896ce38	4097	* WAKE_UP_DUR.[set]
cparata	0:6d69e896ce38	4098	*
cparata	0:6d69e896ce38	4099	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4100	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4101	*
cparata	0:6d69e896ce38	4102	*/
cparata	0:6d69e896ce38	4103	int32_t lsm6dso_wkup_threshold_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4104	{
cparata	0:6d69e896ce38	4105	lsm6dso_wake_up_ths_t reg;
cparata	0:6d69e896ce38	4106	int32_t ret;
cparata	0:6d69e896ce38	4107
cparata	0:6d69e896ce38	4108	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4109	if (ret == 0) {
cparata	0:6d69e896ce38	4110	reg.wk_ths = val;
cparata	0:6d69e896ce38	4111	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4112	}
cparata	0:6d69e896ce38	4113	return ret;
cparata	0:6d69e896ce38	4114	}
cparata	0:6d69e896ce38	4115
cparata	0:6d69e896ce38	4116	/**
cparata	0:6d69e896ce38	4117	* @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
cparata	0:6d69e896ce38	4118	* WAKE_UP_DUR.[get]
cparata	0:6d69e896ce38	4119	*
cparata	0:6d69e896ce38	4120	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4121	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4122	*
cparata	0:6d69e896ce38	4123	*/
cparata	0:6d69e896ce38	4124	int32_t lsm6dso_wkup_threshold_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4125	{
cparata	0:6d69e896ce38	4126	lsm6dso_wake_up_ths_t reg;
cparata	0:6d69e896ce38	4127	int32_t ret;
cparata	0:6d69e896ce38	4128
cparata	0:6d69e896ce38	4129	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4130	*val = reg.wk_ths;
cparata	0:6d69e896ce38	4131
cparata	0:6d69e896ce38	4132	return ret;
cparata	0:6d69e896ce38	4133	}
cparata	0:6d69e896ce38	4134
cparata	0:6d69e896ce38	4135	/**
cparata	0:6d69e896ce38	4136	* @brief Wake up duration event.[set]
cparata	0:6d69e896ce38	4137	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4138	*
cparata	0:6d69e896ce38	4139	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4140	* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4141	*
cparata	0:6d69e896ce38	4142	*/
cparata	0:6d69e896ce38	4143	int32_t lsm6dso_xl_usr_offset_on_wkup_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4144	{
cparata	0:6d69e896ce38	4145	lsm6dso_wake_up_ths_t reg;
cparata	0:6d69e896ce38	4146	int32_t ret;
cparata	0:6d69e896ce38	4147
cparata	0:6d69e896ce38	4148	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4149	if (ret == 0) {
cparata	0:6d69e896ce38	4150	reg.usr_off_on_wu = val;
cparata	0:6d69e896ce38	4151	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4152	}
cparata	0:6d69e896ce38	4153	return ret;
cparata	0:6d69e896ce38	4154	}
cparata	0:6d69e896ce38	4155
cparata	0:6d69e896ce38	4156	/**
cparata	0:6d69e896ce38	4157	* @brief Wake up duration event.[get]
cparata	0:6d69e896ce38	4158	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4159	*
cparata	0:6d69e896ce38	4160	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4161	* @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4162	*
cparata	0:6d69e896ce38	4163	*/
cparata	0:6d69e896ce38	4164	int32_t lsm6dso_xl_usr_offset_on_wkup_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4165	{
cparata	0:6d69e896ce38	4166	lsm6dso_wake_up_ths_t reg;
cparata	0:6d69e896ce38	4167	int32_t ret;
cparata	0:6d69e896ce38	4168
cparata	0:6d69e896ce38	4169	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4170	*val = reg.usr_off_on_wu;
cparata	0:6d69e896ce38	4171
cparata	0:6d69e896ce38	4172	return ret;
cparata	0:6d69e896ce38	4173	}
cparata	0:6d69e896ce38	4174
cparata	0:6d69e896ce38	4175	/**
cparata	0:6d69e896ce38	4176	* @brief Wake up duration event.[set]
cparata	0:6d69e896ce38	4177	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4178	*
cparata	0:6d69e896ce38	4179	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4180	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4181	*
cparata	0:6d69e896ce38	4182	*/
cparata	0:6d69e896ce38	4183	int32_t lsm6dso_wkup_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4184	{
cparata	0:6d69e896ce38	4185	lsm6dso_wake_up_dur_t reg;
cparata	0:6d69e896ce38	4186	int32_t ret;
cparata	0:6d69e896ce38	4187
cparata	0:6d69e896ce38	4188	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4189	if (ret == 0) {
cparata	0:6d69e896ce38	4190	reg.wake_dur = val;
cparata	0:6d69e896ce38	4191	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4192	}
cparata	0:6d69e896ce38	4193	return ret;
cparata	0:6d69e896ce38	4194	}
cparata	0:6d69e896ce38	4195
cparata	0:6d69e896ce38	4196	/**
cparata	0:6d69e896ce38	4197	* @brief Wake up duration event.[get]
cparata	0:6d69e896ce38	4198	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	4199	*
cparata	0:6d69e896ce38	4200	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4201	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4202	*
cparata	0:6d69e896ce38	4203	*/
cparata	0:6d69e896ce38	4204	int32_t lsm6dso_wkup_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4205	{
cparata	0:6d69e896ce38	4206	lsm6dso_wake_up_dur_t reg;
cparata	0:6d69e896ce38	4207	int32_t ret;
cparata	0:6d69e896ce38	4208
cparata	0:6d69e896ce38	4209	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4210	*val = reg.wake_dur;
cparata	0:6d69e896ce38	4211
cparata	0:6d69e896ce38	4212	return ret;
cparata	0:6d69e896ce38	4213	}
cparata	0:6d69e896ce38	4214
cparata	0:6d69e896ce38	4215	/**
cparata	0:6d69e896ce38	4216	* @}
cparata	0:6d69e896ce38	4217	*
cparata	0:6d69e896ce38	4218	*/
cparata	0:6d69e896ce38	4219
cparata	0:6d69e896ce38	4220	/**
cparata	0:6d69e896ce38	4221	* @defgroup LSM6DSO_ Activity/Inactivity_detection
cparata	0:6d69e896ce38	4222	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	4223	* activity/inactivity detection.
cparata	0:6d69e896ce38	4224	* @{
cparata	0:6d69e896ce38	4225	*
cparata	0:6d69e896ce38	4226	*/
cparata	0:6d69e896ce38	4227
cparata	0:6d69e896ce38	4228	/**
cparata	0:6d69e896ce38	4229	* @brief Enables gyroscope Sleep mode.[set]
cparata	0:6d69e896ce38	4230	*
cparata	0:6d69e896ce38	4231	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4232	* @param val change the values of sleep_g in reg CTRL4_C
cparata	0:6d69e896ce38	4233	*
cparata	0:6d69e896ce38	4234	*/
cparata	0:6d69e896ce38	4235	int32_t lsm6dso_gy_sleep_mode_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4236	{
cparata	0:6d69e896ce38	4237	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	4238	int32_t ret;
cparata	0:6d69e896ce38	4239
cparata	0:6d69e896ce38	4240	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4241	if (ret == 0) {
cparata	0:6d69e896ce38	4242	reg.sleep_g = val;
cparata	0:6d69e896ce38	4243	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4244	}
cparata	0:6d69e896ce38	4245	return ret;
cparata	0:6d69e896ce38	4246	}
cparata	0:6d69e896ce38	4247
cparata	0:6d69e896ce38	4248	/**
cparata	0:6d69e896ce38	4249	* @brief Enables gyroscope Sleep mode.[get]
cparata	0:6d69e896ce38	4250	*
cparata	0:6d69e896ce38	4251	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4252	* @param val change the values of sleep_g in reg CTRL4_C
cparata	0:6d69e896ce38	4253	*
cparata	0:6d69e896ce38	4254	*/
cparata	0:6d69e896ce38	4255	int32_t lsm6dso_gy_sleep_mode_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4256	{
cparata	0:6d69e896ce38	4257	lsm6dso_ctrl4_c_t reg;
cparata	0:6d69e896ce38	4258	int32_t ret;
cparata	0:6d69e896ce38	4259
cparata	0:6d69e896ce38	4260	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4261	*val = reg.sleep_g;
cparata	0:6d69e896ce38	4262
cparata	0:6d69e896ce38	4263	return ret;
cparata	0:6d69e896ce38	4264	}
cparata	0:6d69e896ce38	4265
cparata	0:6d69e896ce38	4266	/**
cparata	0:6d69e896ce38	4267	* @brief Drives the sleep status instead of
cparata	0:6d69e896ce38	4268	* sleep change on INT pins
cparata	0:6d69e896ce38	4269	* (only if INT1_SLEEP_CHANGE or
cparata	0:6d69e896ce38	4270	* INT2_SLEEP_CHANGE bits are enabled).[set]
cparata	0:6d69e896ce38	4271	*
cparata	0:6d69e896ce38	4272	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4273	* @param val change the values of sleep_status_on_int in reg TAP_CFG0
cparata	0:6d69e896ce38	4274	*
cparata	0:6d69e896ce38	4275	*/
cparata	0:6d69e896ce38	4276	int32_t lsm6dso_act_pin_notification_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4277	lsm6dso_sleep_status_on_int_t val)
cparata	0:6d69e896ce38	4278	{
cparata	0:6d69e896ce38	4279	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	4280	int32_t ret;
cparata	0:6d69e896ce38	4281
cparata	0:6d69e896ce38	4282	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4283	if (ret == 0) {
cparata	0:6d69e896ce38	4284	reg.sleep_status_on_int = (uint8_t)val;
cparata	0:6d69e896ce38	4285	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4286	}
cparata	0:6d69e896ce38	4287	return ret;
cparata	0:6d69e896ce38	4288	}
cparata	0:6d69e896ce38	4289
cparata	0:6d69e896ce38	4290	/**
cparata	0:6d69e896ce38	4291	* @brief Drives the sleep status instead of
cparata	0:6d69e896ce38	4292	* sleep change on INT pins (only if
cparata	0:6d69e896ce38	4293	* INT1_SLEEP_CHANGE or
cparata	0:6d69e896ce38	4294	* INT2_SLEEP_CHANGE bits are enabled).[get]
cparata	0:6d69e896ce38	4295	*
cparata	0:6d69e896ce38	4296	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4297	* @param val Get the values of sleep_status_on_int in reg TAP_CFG0
cparata	0:6d69e896ce38	4298	*
cparata	0:6d69e896ce38	4299	*/
cparata	0:6d69e896ce38	4300	int32_t lsm6dso_act_pin_notification_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4301	lsm6dso_sleep_status_on_int_t *val)
cparata	0:6d69e896ce38	4302	{
cparata	0:6d69e896ce38	4303	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	4304	int32_t ret;
cparata	0:6d69e896ce38	4305
cparata	0:6d69e896ce38	4306	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4307	switch (reg.sleep_status_on_int) {
cparata	0:6d69e896ce38	4308	case LSM6DSO_DRIVE_SLEEP_CHG_EVENT:
cparata	0:6d69e896ce38	4309	*val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
cparata	0:6d69e896ce38	4310	break;
cparata	0:6d69e896ce38	4311	case LSM6DSO_DRIVE_SLEEP_STATUS:
cparata	0:6d69e896ce38	4312	*val = LSM6DSO_DRIVE_SLEEP_STATUS;
cparata	0:6d69e896ce38	4313	break;
cparata	0:6d69e896ce38	4314	default:
cparata	0:6d69e896ce38	4315	*val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
cparata	0:6d69e896ce38	4316	break;
cparata	0:6d69e896ce38	4317	}
cparata	0:6d69e896ce38	4318	return ret;
cparata	0:6d69e896ce38	4319	}
cparata	0:6d69e896ce38	4320
cparata	0:6d69e896ce38	4321	/**
cparata	0:6d69e896ce38	4322	* @brief Enable inactivity function.[set]
cparata	0:6d69e896ce38	4323	*
cparata	0:6d69e896ce38	4324	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4325	* @param val change the values of inact_en in reg TAP_CFG2
cparata	0:6d69e896ce38	4326	*
cparata	0:6d69e896ce38	4327	*/
cparata	0:6d69e896ce38	4328	int32_t lsm6dso_act_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_inact_en_t val)
cparata	0:6d69e896ce38	4329	{
cparata	0:6d69e896ce38	4330	lsm6dso_tap_cfg2_t reg;
cparata	0:6d69e896ce38	4331	int32_t ret;
cparata	0:6d69e896ce38	4332
cparata	0:6d69e896ce38	4333	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4334	if (ret == 0) {
cparata	0:6d69e896ce38	4335	reg.inact_en = (uint8_t)val;
cparata	0:6d69e896ce38	4336	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4337	}
cparata	0:6d69e896ce38	4338	return ret;
cparata	0:6d69e896ce38	4339	}
cparata	0:6d69e896ce38	4340
cparata	0:6d69e896ce38	4341	/**
cparata	0:6d69e896ce38	4342	* @brief Enable inactivity function.[get]
cparata	0:6d69e896ce38	4343	*
cparata	0:6d69e896ce38	4344	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4345	* @param val Get the values of inact_en in reg TAP_CFG2
cparata	0:6d69e896ce38	4346	*
cparata	0:6d69e896ce38	4347	*/
cparata	0:6d69e896ce38	4348	int32_t lsm6dso_act_mode_get(lsm6dso_ctx_t ctx, lsm6dso_inact_en_t val)
cparata	0:6d69e896ce38	4349	{
cparata	0:6d69e896ce38	4350	lsm6dso_tap_cfg2_t reg;
cparata	0:6d69e896ce38	4351	int32_t ret;
cparata	0:6d69e896ce38	4352
cparata	0:6d69e896ce38	4353	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4354	switch (reg.inact_en) {
cparata	0:6d69e896ce38	4355	case LSM6DSO_XL_AND_GY_NOT_AFFECTED:
cparata	0:6d69e896ce38	4356	*val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
cparata	0:6d69e896ce38	4357	break;
cparata	0:6d69e896ce38	4358	case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED:
cparata	0:6d69e896ce38	4359	*val = LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED;
cparata	0:6d69e896ce38	4360	break;
cparata	0:6d69e896ce38	4361	case LSM6DSO_XL_12Hz5_GY_SLEEP:
cparata	0:6d69e896ce38	4362	*val = LSM6DSO_XL_12Hz5_GY_SLEEP;
cparata	0:6d69e896ce38	4363	break;
cparata	0:6d69e896ce38	4364	case LSM6DSO_XL_12Hz5_GY_PD:
cparata	0:6d69e896ce38	4365	*val = LSM6DSO_XL_12Hz5_GY_PD;
cparata	0:6d69e896ce38	4366	break;
cparata	0:6d69e896ce38	4367	default:
cparata	0:6d69e896ce38	4368	*val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
cparata	0:6d69e896ce38	4369	break;
cparata	0:6d69e896ce38	4370	}
cparata	0:6d69e896ce38	4371	return ret;
cparata	0:6d69e896ce38	4372	}
cparata	0:6d69e896ce38	4373
cparata	0:6d69e896ce38	4374	/**
cparata	0:6d69e896ce38	4375	* @brief Duration to go in sleep mode.[set]
cparata	0:6d69e896ce38	4376	* 1 LSb = 512 / ODR
cparata	0:6d69e896ce38	4377	*
cparata	0:6d69e896ce38	4378	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4379	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4380	*
cparata	0:6d69e896ce38	4381	*/
cparata	0:6d69e896ce38	4382	int32_t lsm6dso_act_sleep_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4383	{
cparata	0:6d69e896ce38	4384	lsm6dso_wake_up_dur_t reg;
cparata	0:6d69e896ce38	4385	int32_t ret;
cparata	0:6d69e896ce38	4386
cparata	0:6d69e896ce38	4387	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4388	if (ret == 0) {
cparata	0:6d69e896ce38	4389	reg.sleep_dur = val;
cparata	0:6d69e896ce38	4390	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4391	}
cparata	0:6d69e896ce38	4392	return ret;
cparata	0:6d69e896ce38	4393	}
cparata	0:6d69e896ce38	4394
cparata	0:6d69e896ce38	4395	/**
cparata	0:6d69e896ce38	4396	* @brief Duration to go in sleep mode.[get]
cparata	0:6d69e896ce38	4397	* 1 LSb = 512 / ODR
cparata	0:6d69e896ce38	4398	*
cparata	0:6d69e896ce38	4399	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4400	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:6d69e896ce38	4401	*
cparata	0:6d69e896ce38	4402	*/
cparata	0:6d69e896ce38	4403	int32_t lsm6dso_act_sleep_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4404	{
cparata	0:6d69e896ce38	4405	lsm6dso_wake_up_dur_t reg;
cparata	0:6d69e896ce38	4406	int32_t ret;
cparata	0:6d69e896ce38	4407
cparata	0:6d69e896ce38	4408	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4409	*val = reg.sleep_dur;
cparata	0:6d69e896ce38	4410
cparata	0:6d69e896ce38	4411	return ret;
cparata	0:6d69e896ce38	4412	}
cparata	0:6d69e896ce38	4413
cparata	0:6d69e896ce38	4414	/**
cparata	0:6d69e896ce38	4415	* @}
cparata	0:6d69e896ce38	4416	*
cparata	0:6d69e896ce38	4417	*/
cparata	0:6d69e896ce38	4418
cparata	0:6d69e896ce38	4419	/**
cparata	0:6d69e896ce38	4420	* @defgroup LSM6DSO_tap_generator
cparata	0:6d69e896ce38	4421	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	4422	* tap and double tap event generation.
cparata	0:6d69e896ce38	4423	* @{
cparata	0:6d69e896ce38	4424	*
cparata	0:6d69e896ce38	4425	*/
cparata	0:6d69e896ce38	4426
cparata	0:6d69e896ce38	4427	/**
cparata	0:6d69e896ce38	4428	* @brief Enable Z direction in tap recognition.[set]
cparata	0:6d69e896ce38	4429	*
cparata	0:6d69e896ce38	4430	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4431	* @param val change the values of tap_z_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4432	*
cparata	0:6d69e896ce38	4433	*/
cparata	0:6d69e896ce38	4434	int32_t lsm6dso_tap_detection_on_z_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4435	{
cparata	0:6d69e896ce38	4436	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	4437	int32_t ret;
cparata	0:6d69e896ce38	4438
cparata	0:6d69e896ce38	4439	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4440	if (ret == 0) {
cparata	0:6d69e896ce38	4441	reg.tap_z_en = val;
cparata	0:6d69e896ce38	4442	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4443	}
cparata	0:6d69e896ce38	4444	return ret;
cparata	0:6d69e896ce38	4445	}
cparata	0:6d69e896ce38	4446
cparata	0:6d69e896ce38	4447	/**
cparata	0:6d69e896ce38	4448	* @brief Enable Z direction in tap recognition.[get]
cparata	0:6d69e896ce38	4449	*
cparata	0:6d69e896ce38	4450	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4451	* @param val change the values of tap_z_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4452	*
cparata	0:6d69e896ce38	4453	*/
cparata	0:6d69e896ce38	4454	int32_t lsm6dso_tap_detection_on_z_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4455	{
cparata	0:6d69e896ce38	4456	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	4457	int32_t ret;
cparata	0:6d69e896ce38	4458
cparata	0:6d69e896ce38	4459	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4460	*val = reg.tap_z_en;
cparata	0:6d69e896ce38	4461
cparata	0:6d69e896ce38	4462	return ret;
cparata	0:6d69e896ce38	4463	}
cparata	0:6d69e896ce38	4464
cparata	0:6d69e896ce38	4465	/**
cparata	0:6d69e896ce38	4466	* @brief Enable Y direction in tap recognition.[set]
cparata	0:6d69e896ce38	4467	*
cparata	0:6d69e896ce38	4468	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4469	* @param val change the values of tap_y_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4470	*
cparata	0:6d69e896ce38	4471	*/
cparata	0:6d69e896ce38	4472	int32_t lsm6dso_tap_detection_on_y_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4473	{
cparata	0:6d69e896ce38	4474	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	4475	int32_t ret;
cparata	0:6d69e896ce38	4476
cparata	0:6d69e896ce38	4477	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4478	if (ret == 0) {
cparata	0:6d69e896ce38	4479	reg.tap_y_en = val;
cparata	0:6d69e896ce38	4480	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4481	}
cparata	0:6d69e896ce38	4482	return ret;
cparata	0:6d69e896ce38	4483	}
cparata	0:6d69e896ce38	4484
cparata	0:6d69e896ce38	4485	/**
cparata	0:6d69e896ce38	4486	* @brief Enable Y direction in tap recognition.[get]
cparata	0:6d69e896ce38	4487	*
cparata	0:6d69e896ce38	4488	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4489	* @param val change the values of tap_y_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4490	*
cparata	0:6d69e896ce38	4491	*/
cparata	0:6d69e896ce38	4492	int32_t lsm6dso_tap_detection_on_y_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4493	{
cparata	0:6d69e896ce38	4494	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	4495	int32_t ret;
cparata	0:6d69e896ce38	4496
cparata	0:6d69e896ce38	4497	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4498	*val = reg.tap_y_en;
cparata	0:6d69e896ce38	4499
cparata	0:6d69e896ce38	4500	return ret;
cparata	0:6d69e896ce38	4501	}
cparata	0:6d69e896ce38	4502
cparata	0:6d69e896ce38	4503	/**
cparata	0:6d69e896ce38	4504	* @brief Enable X direction in tap recognition.[set]
cparata	0:6d69e896ce38	4505	*
cparata	0:6d69e896ce38	4506	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4507	* @param val change the values of tap_x_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4508	*
cparata	0:6d69e896ce38	4509	*/
cparata	0:6d69e896ce38	4510	int32_t lsm6dso_tap_detection_on_x_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4511	{
cparata	0:6d69e896ce38	4512	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	4513	int32_t ret;
cparata	0:6d69e896ce38	4514
cparata	0:6d69e896ce38	4515	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4516	if (ret == 0) {
cparata	0:6d69e896ce38	4517	reg.tap_x_en = val;
cparata	0:6d69e896ce38	4518	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4519	}
cparata	0:6d69e896ce38	4520	return ret;
cparata	0:6d69e896ce38	4521	}
cparata	0:6d69e896ce38	4522
cparata	0:6d69e896ce38	4523	/**
cparata	0:6d69e896ce38	4524	* @brief Enable X direction in tap recognition.[get]
cparata	0:6d69e896ce38	4525	*
cparata	0:6d69e896ce38	4526	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4527	* @param val change the values of tap_x_en in reg TAP_CFG0
cparata	0:6d69e896ce38	4528	*
cparata	0:6d69e896ce38	4529	*/
cparata	0:6d69e896ce38	4530	int32_t lsm6dso_tap_detection_on_x_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4531	{
cparata	0:6d69e896ce38	4532	lsm6dso_tap_cfg0_t reg;
cparata	0:6d69e896ce38	4533	int32_t ret;
cparata	0:6d69e896ce38	4534
cparata	0:6d69e896ce38	4535	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4536	*val = reg.tap_x_en;
cparata	0:6d69e896ce38	4537
cparata	0:6d69e896ce38	4538	return ret;
cparata	0:6d69e896ce38	4539	}
cparata	0:6d69e896ce38	4540
cparata	0:6d69e896ce38	4541	/**
cparata	0:6d69e896ce38	4542	* @brief X-axis tap recognition threshold.[set]
cparata	0:6d69e896ce38	4543	*
cparata	0:6d69e896ce38	4544	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4545	* @param val change the values of tap_ths_x in reg TAP_CFG1
cparata	0:6d69e896ce38	4546	*
cparata	0:6d69e896ce38	4547	*/
cparata	0:6d69e896ce38	4548	int32_t lsm6dso_tap_threshold_x_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4549	{
cparata	0:6d69e896ce38	4550	lsm6dso_tap_cfg1_t reg;
cparata	0:6d69e896ce38	4551	int32_t ret;
cparata	0:6d69e896ce38	4552
cparata	0:6d69e896ce38	4553	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4554	if (ret == 0) {
cparata	0:6d69e896ce38	4555	reg.tap_ths_x = val;
cparata	0:6d69e896ce38	4556	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4557	}
cparata	0:6d69e896ce38	4558	return ret;
cparata	0:6d69e896ce38	4559	}
cparata	0:6d69e896ce38	4560
cparata	0:6d69e896ce38	4561	/**
cparata	0:6d69e896ce38	4562	* @brief X-axis tap recognition threshold.[get]
cparata	0:6d69e896ce38	4563	*
cparata	0:6d69e896ce38	4564	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4565	* @param val change the values of tap_ths_x in reg TAP_CFG1
cparata	0:6d69e896ce38	4566	*
cparata	0:6d69e896ce38	4567	*/
cparata	0:6d69e896ce38	4568	int32_t lsm6dso_tap_threshold_x_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4569	{
cparata	0:6d69e896ce38	4570	lsm6dso_tap_cfg1_t reg;
cparata	0:6d69e896ce38	4571	int32_t ret;
cparata	0:6d69e896ce38	4572
cparata	0:6d69e896ce38	4573	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4574	*val = reg.tap_ths_x;
cparata	0:6d69e896ce38	4575
cparata	0:6d69e896ce38	4576	return ret;
cparata	0:6d69e896ce38	4577	}
cparata	0:6d69e896ce38	4578
cparata	0:6d69e896ce38	4579	/**
cparata	0:6d69e896ce38	4580	* @brief Selection of axis priority for TAP detection.[set]
cparata	0:6d69e896ce38	4581	*
cparata	0:6d69e896ce38	4582	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4583	* @param val change the values of tap_priority in
cparata	0:6d69e896ce38	4584	* reg TAP_CFG1
cparata	0:6d69e896ce38	4585	*
cparata	0:6d69e896ce38	4586	*/
cparata	0:6d69e896ce38	4587	int32_t lsm6dso_tap_axis_priority_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4588	lsm6dso_tap_priority_t val)
cparata	0:6d69e896ce38	4589	{
cparata	0:6d69e896ce38	4590	lsm6dso_tap_cfg1_t reg;
cparata	0:6d69e896ce38	4591	int32_t ret;
cparata	0:6d69e896ce38	4592
cparata	0:6d69e896ce38	4593	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4594	if (ret == 0) {
cparata	0:6d69e896ce38	4595	reg.tap_priority = (uint8_t)val;
cparata	0:6d69e896ce38	4596	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4597	}
cparata	0:6d69e896ce38	4598	return ret;
cparata	0:6d69e896ce38	4599	}
cparata	0:6d69e896ce38	4600
cparata	0:6d69e896ce38	4601	/**
cparata	0:6d69e896ce38	4602	* @brief Selection of axis priority for TAP detection.[get]
cparata	0:6d69e896ce38	4603	*
cparata	0:6d69e896ce38	4604	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4605	* @param val Get the values of tap_priority in
cparata	0:6d69e896ce38	4606	* reg TAP_CFG1
cparata	0:6d69e896ce38	4607	*
cparata	0:6d69e896ce38	4608	*/
cparata	0:6d69e896ce38	4609	int32_t lsm6dso_tap_axis_priority_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4610	lsm6dso_tap_priority_t *val)
cparata	0:6d69e896ce38	4611	{
cparata	0:6d69e896ce38	4612	lsm6dso_tap_cfg1_t reg;
cparata	0:6d69e896ce38	4613	int32_t ret;
cparata	0:6d69e896ce38	4614
cparata	0:6d69e896ce38	4615	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4616	switch (reg.tap_priority) {
cparata	0:6d69e896ce38	4617	case LSM6DSO_XYZ:
cparata	0:6d69e896ce38	4618	*val = LSM6DSO_XYZ;
cparata	0:6d69e896ce38	4619	break;
cparata	0:6d69e896ce38	4620	case LSM6DSO_YXZ:
cparata	0:6d69e896ce38	4621	*val = LSM6DSO_YXZ;
cparata	0:6d69e896ce38	4622	break;
cparata	0:6d69e896ce38	4623	case LSM6DSO_XZY:
cparata	0:6d69e896ce38	4624	*val = LSM6DSO_XZY;
cparata	0:6d69e896ce38	4625	break;
cparata	0:6d69e896ce38	4626	case LSM6DSO_ZYX:
cparata	0:6d69e896ce38	4627	*val = LSM6DSO_ZYX;
cparata	0:6d69e896ce38	4628	break;
cparata	0:6d69e896ce38	4629	case LSM6DSO_YZX:
cparata	0:6d69e896ce38	4630	*val = LSM6DSO_YZX;
cparata	0:6d69e896ce38	4631	break;
cparata	0:6d69e896ce38	4632	case LSM6DSO_ZXY:
cparata	0:6d69e896ce38	4633	*val = LSM6DSO_ZXY;
cparata	0:6d69e896ce38	4634	break;
cparata	0:6d69e896ce38	4635	default:
cparata	0:6d69e896ce38	4636	*val = LSM6DSO_XYZ;
cparata	0:6d69e896ce38	4637	break;
cparata	0:6d69e896ce38	4638	}
cparata	0:6d69e896ce38	4639	return ret;
cparata	0:6d69e896ce38	4640	}
cparata	0:6d69e896ce38	4641
cparata	0:6d69e896ce38	4642	/**
cparata	0:6d69e896ce38	4643	* @brief Y-axis tap recognition threshold.[set]
cparata	0:6d69e896ce38	4644	*
cparata	0:6d69e896ce38	4645	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4646	* @param val change the values of tap_ths_y in reg TAP_CFG2
cparata	0:6d69e896ce38	4647	*
cparata	0:6d69e896ce38	4648	*/
cparata	0:6d69e896ce38	4649	int32_t lsm6dso_tap_threshold_y_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4650	{
cparata	0:6d69e896ce38	4651	lsm6dso_tap_cfg2_t reg;
cparata	0:6d69e896ce38	4652	int32_t ret;
cparata	0:6d69e896ce38	4653
cparata	0:6d69e896ce38	4654	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4655	if (ret == 0) {
cparata	0:6d69e896ce38	4656	reg.tap_ths_y = val;
cparata	0:6d69e896ce38	4657	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4658	}
cparata	0:6d69e896ce38	4659	return ret;
cparata	0:6d69e896ce38	4660	}
cparata	0:6d69e896ce38	4661
cparata	0:6d69e896ce38	4662	/**
cparata	0:6d69e896ce38	4663	* @brief Y-axis tap recognition threshold.[get]
cparata	0:6d69e896ce38	4664	*
cparata	0:6d69e896ce38	4665	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4666	* @param val change the values of tap_ths_y in reg TAP_CFG2
cparata	0:6d69e896ce38	4667	*
cparata	0:6d69e896ce38	4668	*/
cparata	0:6d69e896ce38	4669	int32_t lsm6dso_tap_threshold_y_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4670	{
cparata	0:6d69e896ce38	4671	lsm6dso_tap_cfg2_t reg;
cparata	0:6d69e896ce38	4672	int32_t ret;
cparata	0:6d69e896ce38	4673
cparata	0:6d69e896ce38	4674	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4675	*val = reg.tap_ths_y;
cparata	0:6d69e896ce38	4676
cparata	0:6d69e896ce38	4677	return ret;
cparata	0:6d69e896ce38	4678	}
cparata	0:6d69e896ce38	4679
cparata	0:6d69e896ce38	4680	/**
cparata	0:6d69e896ce38	4681	* @brief Z-axis recognition threshold.[set]
cparata	0:6d69e896ce38	4682	*
cparata	0:6d69e896ce38	4683	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4684	* @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata	0:6d69e896ce38	4685	*
cparata	0:6d69e896ce38	4686	*/
cparata	0:6d69e896ce38	4687	int32_t lsm6dso_tap_threshold_z_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4688	{
cparata	0:6d69e896ce38	4689	lsm6dso_tap_ths_6d_t reg;
cparata	0:6d69e896ce38	4690	int32_t ret;
cparata	0:6d69e896ce38	4691
cparata	0:6d69e896ce38	4692	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4693	if (ret == 0) {
cparata	0:6d69e896ce38	4694	reg.tap_ths_z = val;
cparata	0:6d69e896ce38	4695	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4696	}
cparata	0:6d69e896ce38	4697	return ret;
cparata	0:6d69e896ce38	4698	}
cparata	0:6d69e896ce38	4699
cparata	0:6d69e896ce38	4700	/**
cparata	0:6d69e896ce38	4701	* @brief Z-axis recognition threshold.[get]
cparata	0:6d69e896ce38	4702	*
cparata	0:6d69e896ce38	4703	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4704	* @param val change the values of tap_ths_z in reg TAP_THS_6D
cparata	0:6d69e896ce38	4705	*
cparata	0:6d69e896ce38	4706	*/
cparata	0:6d69e896ce38	4707	int32_t lsm6dso_tap_threshold_z_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4708	{
cparata	0:6d69e896ce38	4709	lsm6dso_tap_ths_6d_t reg;
cparata	0:6d69e896ce38	4710	int32_t ret;
cparata	0:6d69e896ce38	4711
cparata	0:6d69e896ce38	4712	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4713	*val = reg.tap_ths_z;
cparata	0:6d69e896ce38	4714
cparata	0:6d69e896ce38	4715	return ret;
cparata	0:6d69e896ce38	4716	}
cparata	0:6d69e896ce38	4717
cparata	0:6d69e896ce38	4718	/**
cparata	0:6d69e896ce38	4719	* @brief Maximum duration is the maximum time of an
cparata	0:6d69e896ce38	4720	* over threshold signal detection to be recognized
cparata	0:6d69e896ce38	4721	* as a tap event. The default value of these bits
cparata	0:6d69e896ce38	4722	* is 00b which corresponds to 4*ODR_XL time.
cparata	0:6d69e896ce38	4723	* If the SHOCK[1:0] bits are set to a different
cparata	0:6d69e896ce38	4724	* value, 1LSB corresponds to 8*ODR_XL time.[set]
cparata	0:6d69e896ce38	4725	*
cparata	0:6d69e896ce38	4726	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4727	* @param val change the values of shock in reg INT_DUR2
cparata	0:6d69e896ce38	4728	*
cparata	0:6d69e896ce38	4729	*/
cparata	0:6d69e896ce38	4730	int32_t lsm6dso_tap_shock_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4731	{
cparata	0:6d69e896ce38	4732	lsm6dso_int_dur2_t reg;
cparata	0:6d69e896ce38	4733	int32_t ret;
cparata	0:6d69e896ce38	4734
cparata	0:6d69e896ce38	4735	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4736	if (ret == 0) {
cparata	0:6d69e896ce38	4737	reg.shock = val;
cparata	0:6d69e896ce38	4738	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4739	}
cparata	0:6d69e896ce38	4740	return ret;
cparata	0:6d69e896ce38	4741	}
cparata	0:6d69e896ce38	4742
cparata	0:6d69e896ce38	4743	/**
cparata	0:6d69e896ce38	4744	* @brief Maximum duration is the maximum time of an
cparata	0:6d69e896ce38	4745	* over threshold signal detection to be recognized
cparata	0:6d69e896ce38	4746	* as a tap event. The default value of these bits
cparata	0:6d69e896ce38	4747	* is 00b which corresponds to 4*ODR_XL time.
cparata	0:6d69e896ce38	4748	* If the SHOCK[1:0] bits are set to a different
cparata	0:6d69e896ce38	4749	* value, 1LSB corresponds to 8*ODR_XL time.[get]
cparata	0:6d69e896ce38	4750	*
cparata	0:6d69e896ce38	4751	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4752	* @param val change the values of shock in reg INT_DUR2
cparata	0:6d69e896ce38	4753	*
cparata	0:6d69e896ce38	4754	*/
cparata	0:6d69e896ce38	4755	int32_t lsm6dso_tap_shock_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4756	{
cparata	0:6d69e896ce38	4757	lsm6dso_int_dur2_t reg;
cparata	0:6d69e896ce38	4758	int32_t ret;
cparata	0:6d69e896ce38	4759
cparata	0:6d69e896ce38	4760	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4761	*val = reg.shock;
cparata	0:6d69e896ce38	4762
cparata	0:6d69e896ce38	4763	return ret;
cparata	0:6d69e896ce38	4764	}
cparata	0:6d69e896ce38	4765
cparata	0:6d69e896ce38	4766	/**
cparata	0:6d69e896ce38	4767	* @brief Quiet time is the time after the first detected
cparata	0:6d69e896ce38	4768	* tap in which there must not be any over threshold
cparata	0:6d69e896ce38	4769	* event.
cparata	0:6d69e896ce38	4770	* The default value of these bits is 00b which
cparata	0:6d69e896ce38	4771	* corresponds to 2*ODR_XL time. If the QUIET[1:0]
cparata	0:6d69e896ce38	4772	* bits are set to a different value,
cparata	0:6d69e896ce38	4773	* 1LSB corresponds to 4*ODR_XL time.[set]
cparata	0:6d69e896ce38	4774	*
cparata	0:6d69e896ce38	4775	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4776	* @param val change the values of quiet in reg INT_DUR2
cparata	0:6d69e896ce38	4777	*
cparata	0:6d69e896ce38	4778	*/
cparata	0:6d69e896ce38	4779	int32_t lsm6dso_tap_quiet_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4780	{
cparata	0:6d69e896ce38	4781	lsm6dso_int_dur2_t reg;
cparata	0:6d69e896ce38	4782	int32_t ret;
cparata	0:6d69e896ce38	4783
cparata	0:6d69e896ce38	4784	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4785	if (ret == 0) {
cparata	0:6d69e896ce38	4786	reg.quiet = val;
cparata	0:6d69e896ce38	4787	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4788	}
cparata	0:6d69e896ce38	4789	return ret;
cparata	0:6d69e896ce38	4790	}
cparata	0:6d69e896ce38	4791
cparata	0:6d69e896ce38	4792	/**
cparata	0:6d69e896ce38	4793	* @brief Quiet time is the time after the first detected
cparata	0:6d69e896ce38	4794	* tap in which there must not be any over threshold
cparata	0:6d69e896ce38	4795	* event.
cparata	0:6d69e896ce38	4796	* The default value of these bits is 00b which
cparata	0:6d69e896ce38	4797	* corresponds to 2*ODR_XL time.
cparata	0:6d69e896ce38	4798	* If the QUIET[1:0] bits are set to a different
cparata	0:6d69e896ce38	4799	* value, 1LSB corresponds to 4*ODR_XL time.[get]
cparata	0:6d69e896ce38	4800	*
cparata	0:6d69e896ce38	4801	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4802	* @param val change the values of quiet in reg INT_DUR2
cparata	0:6d69e896ce38	4803	*
cparata	0:6d69e896ce38	4804	*/
cparata	0:6d69e896ce38	4805	int32_t lsm6dso_tap_quiet_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4806	{
cparata	0:6d69e896ce38	4807	lsm6dso_int_dur2_t reg;
cparata	0:6d69e896ce38	4808	int32_t ret;
cparata	0:6d69e896ce38	4809
cparata	0:6d69e896ce38	4810	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4811	*val = reg.quiet;
cparata	0:6d69e896ce38	4812
cparata	0:6d69e896ce38	4813	return ret;
cparata	0:6d69e896ce38	4814	}
cparata	0:6d69e896ce38	4815
cparata	0:6d69e896ce38	4816	/**
cparata	0:6d69e896ce38	4817	* @brief When double tap recognition is enabled,
cparata	0:6d69e896ce38	4818	* this register expresses the maximum time
cparata	0:6d69e896ce38	4819	* between two consecutive detected taps to
cparata	0:6d69e896ce38	4820	* determine a double tap event.
cparata	0:6d69e896ce38	4821	* The default value of these bits is 0000b which
cparata	0:6d69e896ce38	4822	* corresponds to 16*ODR_XL time.
cparata	0:6d69e896ce38	4823	* If the DUR[3:0] bits are set to a different value,
cparata	0:6d69e896ce38	4824	* 1LSB corresponds to 32*ODR_XL time.[set]
cparata	0:6d69e896ce38	4825	*
cparata	0:6d69e896ce38	4826	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4827	* @param val change the values of dur in reg INT_DUR2
cparata	0:6d69e896ce38	4828	*
cparata	0:6d69e896ce38	4829	*/
cparata	0:6d69e896ce38	4830	int32_t lsm6dso_tap_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4831	{
cparata	0:6d69e896ce38	4832	lsm6dso_int_dur2_t reg;
cparata	0:6d69e896ce38	4833	int32_t ret;
cparata	0:6d69e896ce38	4834
cparata	0:6d69e896ce38	4835	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4836	if (ret == 0) {
cparata	0:6d69e896ce38	4837	reg.dur = val;
cparata	0:6d69e896ce38	4838	ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4839	}
cparata	0:6d69e896ce38	4840	return ret;
cparata	0:6d69e896ce38	4841	}
cparata	0:6d69e896ce38	4842
cparata	0:6d69e896ce38	4843	/**
cparata	0:6d69e896ce38	4844	* @brief When double tap recognition is enabled,
cparata	0:6d69e896ce38	4845	* this register expresses the maximum time
cparata	0:6d69e896ce38	4846	* between two consecutive detected taps to
cparata	0:6d69e896ce38	4847	* determine a double tap event.
cparata	0:6d69e896ce38	4848	* The default value of these bits is 0000b which
cparata	0:6d69e896ce38	4849	* corresponds to 16*ODR_XL time. If the DUR[3:0]
cparata	0:6d69e896ce38	4850	* bits are set to a different value,
cparata	0:6d69e896ce38	4851	* 1LSB corresponds to 32*ODR_XL time.[get]
cparata	0:6d69e896ce38	4852	*
cparata	0:6d69e896ce38	4853	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4854	* @param val change the values of dur in reg INT_DUR2
cparata	0:6d69e896ce38	4855	*
cparata	0:6d69e896ce38	4856	*/
cparata	0:6d69e896ce38	4857	int32_t lsm6dso_tap_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	4858	{
cparata	0:6d69e896ce38	4859	lsm6dso_int_dur2_t reg;
cparata	0:6d69e896ce38	4860	int32_t ret;
cparata	0:6d69e896ce38	4861
cparata	0:6d69e896ce38	4862	ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4863	*val = reg.dur;
cparata	0:6d69e896ce38	4864
cparata	0:6d69e896ce38	4865	return ret;
cparata	0:6d69e896ce38	4866	}
cparata	0:6d69e896ce38	4867
cparata	0:6d69e896ce38	4868	/**
cparata	0:6d69e896ce38	4869	* @brief Single/double-tap event enable.[set]
cparata	0:6d69e896ce38	4870	*
cparata	0:6d69e896ce38	4871	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4872	* @param val change the values of single_double_tap in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4873	*
cparata	0:6d69e896ce38	4874	*/
cparata	0:6d69e896ce38	4875	int32_t lsm6dso_tap_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4876	lsm6dso_single_double_tap_t val)
cparata	0:6d69e896ce38	4877	{
cparata	0:6d69e896ce38	4878	lsm6dso_wake_up_ths_t reg;
cparata	0:6d69e896ce38	4879	int32_t ret;
cparata	0:6d69e896ce38	4880
cparata	0:6d69e896ce38	4881	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4882	if (ret == 0) {
cparata	0:6d69e896ce38	4883	reg.single_double_tap = (uint8_t)val;
cparata	0:6d69e896ce38	4884	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4885	}
cparata	0:6d69e896ce38	4886	return ret;
cparata	0:6d69e896ce38	4887	}
cparata	0:6d69e896ce38	4888
cparata	0:6d69e896ce38	4889	/**
cparata	0:6d69e896ce38	4890	* @brief Single/double-tap event enable.[get]
cparata	0:6d69e896ce38	4891	*
cparata	0:6d69e896ce38	4892	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4893	* @param val Get the values of single_double_tap in reg WAKE_UP_THS
cparata	0:6d69e896ce38	4894	*
cparata	0:6d69e896ce38	4895	*/
cparata	0:6d69e896ce38	4896	int32_t lsm6dso_tap_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	4897	lsm6dso_single_double_tap_t *val)
cparata	0:6d69e896ce38	4898	{
cparata	0:6d69e896ce38	4899	lsm6dso_wake_up_ths_t reg;
cparata	0:6d69e896ce38	4900	int32_t ret;
cparata	0:6d69e896ce38	4901
cparata	0:6d69e896ce38	4902	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4903
cparata	0:6d69e896ce38	4904	switch (reg.single_double_tap) {
cparata	0:6d69e896ce38	4905	case LSM6DSO_ONLY_SINGLE:
cparata	0:6d69e896ce38	4906	*val = LSM6DSO_ONLY_SINGLE;
cparata	0:6d69e896ce38	4907	break;
cparata	0:6d69e896ce38	4908	case LSM6DSO_BOTH_SINGLE_DOUBLE:
cparata	0:6d69e896ce38	4909	*val = LSM6DSO_BOTH_SINGLE_DOUBLE;
cparata	0:6d69e896ce38	4910	break;
cparata	0:6d69e896ce38	4911	default:
cparata	0:6d69e896ce38	4912	*val = LSM6DSO_ONLY_SINGLE;
cparata	0:6d69e896ce38	4913	break;
cparata	0:6d69e896ce38	4914	}
cparata	0:6d69e896ce38	4915
cparata	0:6d69e896ce38	4916	return ret;
cparata	0:6d69e896ce38	4917	}
cparata	0:6d69e896ce38	4918
cparata	0:6d69e896ce38	4919	/**
cparata	0:6d69e896ce38	4920	* @}
cparata	0:6d69e896ce38	4921	*
cparata	0:6d69e896ce38	4922	*/
cparata	0:6d69e896ce38	4923
cparata	0:6d69e896ce38	4924	/**
cparata	0:6d69e896ce38	4925	* @defgroup LSM6DSO_ Six_position_detection(6D/4D)
cparata	0:6d69e896ce38	4926	* @brief This section groups all the functions concerning six position
cparata	0:6d69e896ce38	4927	* detection (6D).
cparata	0:6d69e896ce38	4928	* @{
cparata	0:6d69e896ce38	4929	*
cparata	0:6d69e896ce38	4930	*/
cparata	0:6d69e896ce38	4931
cparata	0:6d69e896ce38	4932	/**
cparata	0:6d69e896ce38	4933	* @brief Threshold for 4D/6D function.[set]
cparata	0:6d69e896ce38	4934	*
cparata	0:6d69e896ce38	4935	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4936	* @param val change the values of sixd_ths in reg TAP_THS_6D
cparata	0:6d69e896ce38	4937	*
cparata	0:6d69e896ce38	4938	*/
cparata	0:6d69e896ce38	4939	int32_t lsm6dso_6d_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_sixd_ths_t val)
cparata	0:6d69e896ce38	4940	{
cparata	0:6d69e896ce38	4941	lsm6dso_tap_ths_6d_t reg;
cparata	0:6d69e896ce38	4942	int32_t ret;
cparata	0:6d69e896ce38	4943
cparata	0:6d69e896ce38	4944	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4945	if (ret == 0) {
cparata	0:6d69e896ce38	4946	reg.sixd_ths = (uint8_t)val;
cparata	0:6d69e896ce38	4947	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4948	}
cparata	0:6d69e896ce38	4949	return ret;
cparata	0:6d69e896ce38	4950	}
cparata	0:6d69e896ce38	4951
cparata	0:6d69e896ce38	4952	/**
cparata	0:6d69e896ce38	4953	* @brief Threshold for 4D/6D function.[get]
cparata	0:6d69e896ce38	4954	*
cparata	0:6d69e896ce38	4955	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4956	* @param val Get the values of sixd_ths in reg TAP_THS_6D
cparata	0:6d69e896ce38	4957	*
cparata	0:6d69e896ce38	4958	*/
cparata	0:6d69e896ce38	4959	int32_t lsm6dso_6d_threshold_get(lsm6dso_ctx_t ctx, lsm6dso_sixd_ths_t val)
cparata	0:6d69e896ce38	4960	{
cparata	0:6d69e896ce38	4961	lsm6dso_tap_ths_6d_t reg;
cparata	0:6d69e896ce38	4962	int32_t ret;
cparata	0:6d69e896ce38	4963
cparata	0:6d69e896ce38	4964	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4965	switch (reg.sixd_ths) {
cparata	0:6d69e896ce38	4966	case LSM6DSO_DEG_80:
cparata	0:6d69e896ce38	4967	*val = LSM6DSO_DEG_80;
cparata	0:6d69e896ce38	4968	break;
cparata	0:6d69e896ce38	4969	case LSM6DSO_DEG_70:
cparata	0:6d69e896ce38	4970	*val = LSM6DSO_DEG_70;
cparata	0:6d69e896ce38	4971	break;
cparata	0:6d69e896ce38	4972	case LSM6DSO_DEG_60:
cparata	0:6d69e896ce38	4973	*val = LSM6DSO_DEG_60;
cparata	0:6d69e896ce38	4974	break;
cparata	0:6d69e896ce38	4975	case LSM6DSO_DEG_50:
cparata	0:6d69e896ce38	4976	*val = LSM6DSO_DEG_50;
cparata	0:6d69e896ce38	4977	break;
cparata	0:6d69e896ce38	4978	default:
cparata	0:6d69e896ce38	4979	*val = LSM6DSO_DEG_80;
cparata	0:6d69e896ce38	4980	break;
cparata	0:6d69e896ce38	4981	}
cparata	0:6d69e896ce38	4982	return ret;
cparata	0:6d69e896ce38	4983	}
cparata	0:6d69e896ce38	4984
cparata	0:6d69e896ce38	4985	/**
cparata	0:6d69e896ce38	4986	* @brief 4D orientation detection enable.[set]
cparata	0:6d69e896ce38	4987	*
cparata	0:6d69e896ce38	4988	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	4989	* @param val change the values of d4d_en in reg TAP_THS_6D
cparata	0:6d69e896ce38	4990	*
cparata	0:6d69e896ce38	4991	*/
cparata	0:6d69e896ce38	4992	int32_t lsm6dso_4d_mode_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	4993	{
cparata	0:6d69e896ce38	4994	lsm6dso_tap_ths_6d_t reg;
cparata	0:6d69e896ce38	4995	int32_t ret;
cparata	0:6d69e896ce38	4996
cparata	0:6d69e896ce38	4997	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	4998	if (ret == 0) {
cparata	0:6d69e896ce38	4999	reg.d4d_en = val;
cparata	0:6d69e896ce38	5000	ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5001	}
cparata	0:6d69e896ce38	5002	return ret;
cparata	0:6d69e896ce38	5003	}
cparata	0:6d69e896ce38	5004
cparata	0:6d69e896ce38	5005	/**
cparata	0:6d69e896ce38	5006	* @brief 4D orientation detection enable.[get]
cparata	0:6d69e896ce38	5007	*
cparata	0:6d69e896ce38	5008	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5009	* @param val change the values of d4d_en in reg TAP_THS_6D
cparata	0:6d69e896ce38	5010	*
cparata	0:6d69e896ce38	5011	*/
cparata	0:6d69e896ce38	5012	int32_t lsm6dso_4d_mode_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5013	{
cparata	0:6d69e896ce38	5014	lsm6dso_tap_ths_6d_t reg;
cparata	0:6d69e896ce38	5015	int32_t ret;
cparata	0:6d69e896ce38	5016
cparata	0:6d69e896ce38	5017	ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5018	*val = reg.d4d_en;
cparata	0:6d69e896ce38	5019
cparata	0:6d69e896ce38	5020	return ret;
cparata	0:6d69e896ce38	5021	}
cparata	0:6d69e896ce38	5022
cparata	0:6d69e896ce38	5023	/**
cparata	0:6d69e896ce38	5024	* @}
cparata	0:6d69e896ce38	5025	*
cparata	0:6d69e896ce38	5026	*/
cparata	0:6d69e896ce38	5027
cparata	0:6d69e896ce38	5028	/**
cparata	0:6d69e896ce38	5029	* @defgroup LSM6DSO_free_fall
cparata	0:6d69e896ce38	5030	* @brief This section group all the functions concerning the free
cparata	0:6d69e896ce38	5031	* fall detection.
cparata	0:6d69e896ce38	5032	* @{
cparata	0:6d69e896ce38	5033	*
cparata	0:6d69e896ce38	5034	*/
cparata	0:6d69e896ce38	5035	/**
cparata	0:6d69e896ce38	5036	* @brief Free fall threshold setting.[set]
cparata	0:6d69e896ce38	5037	*
cparata	0:6d69e896ce38	5038	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5039	* @param val change the values of ff_ths in reg FREE_FALL
cparata	0:6d69e896ce38	5040	*
cparata	0:6d69e896ce38	5041	*/
cparata	0:6d69e896ce38	5042	int32_t lsm6dso_ff_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_ff_ths_t val)
cparata	0:6d69e896ce38	5043	{
cparata	0:6d69e896ce38	5044	lsm6dso_free_fall_t reg;
cparata	0:6d69e896ce38	5045	int32_t ret;
cparata	0:6d69e896ce38	5046
cparata	0:6d69e896ce38	5047	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5048	if (ret == 0) {
cparata	0:6d69e896ce38	5049	reg.ff_ths = (uint8_t)val;
cparata	0:6d69e896ce38	5050	ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5051	}
cparata	0:6d69e896ce38	5052	return ret;
cparata	0:6d69e896ce38	5053	}
cparata	0:6d69e896ce38	5054
cparata	0:6d69e896ce38	5055	/**
cparata	0:6d69e896ce38	5056	* @brief Free fall threshold setting.[get]
cparata	0:6d69e896ce38	5057	*
cparata	0:6d69e896ce38	5058	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5059	* @param val Get the values of ff_ths in reg FREE_FALL
cparata	0:6d69e896ce38	5060	*
cparata	0:6d69e896ce38	5061	*/
cparata	0:6d69e896ce38	5062	int32_t lsm6dso_ff_threshold_get(lsm6dso_ctx_t ctx, lsm6dso_ff_ths_t val)
cparata	0:6d69e896ce38	5063	{
cparata	0:6d69e896ce38	5064	lsm6dso_free_fall_t reg;
cparata	0:6d69e896ce38	5065	int32_t ret;
cparata	0:6d69e896ce38	5066
cparata	0:6d69e896ce38	5067	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5068	switch (reg.ff_ths) {
cparata	0:6d69e896ce38	5069	case LSM6DSO_FF_TSH_156mg:
cparata	0:6d69e896ce38	5070	*val = LSM6DSO_FF_TSH_156mg;
cparata	0:6d69e896ce38	5071	break;
cparata	0:6d69e896ce38	5072	case LSM6DSO_FF_TSH_219mg:
cparata	0:6d69e896ce38	5073	*val = LSM6DSO_FF_TSH_219mg;
cparata	0:6d69e896ce38	5074	break;
cparata	0:6d69e896ce38	5075	case LSM6DSO_FF_TSH_250mg:
cparata	0:6d69e896ce38	5076	*val = LSM6DSO_FF_TSH_250mg;
cparata	0:6d69e896ce38	5077	break;
cparata	0:6d69e896ce38	5078	case LSM6DSO_FF_TSH_312mg:
cparata	0:6d69e896ce38	5079	*val = LSM6DSO_FF_TSH_312mg;
cparata	0:6d69e896ce38	5080	break;
cparata	0:6d69e896ce38	5081	case LSM6DSO_FF_TSH_344mg:
cparata	0:6d69e896ce38	5082	*val = LSM6DSO_FF_TSH_344mg;
cparata	0:6d69e896ce38	5083	break;
cparata	0:6d69e896ce38	5084	case LSM6DSO_FF_TSH_406mg:
cparata	0:6d69e896ce38	5085	*val = LSM6DSO_FF_TSH_406mg;
cparata	0:6d69e896ce38	5086	break;
cparata	0:6d69e896ce38	5087	case LSM6DSO_FF_TSH_469mg:
cparata	0:6d69e896ce38	5088	*val = LSM6DSO_FF_TSH_469mg;
cparata	0:6d69e896ce38	5089	break;
cparata	0:6d69e896ce38	5090	case LSM6DSO_FF_TSH_500mg:
cparata	0:6d69e896ce38	5091	*val = LSM6DSO_FF_TSH_500mg;
cparata	0:6d69e896ce38	5092	break;
cparata	0:6d69e896ce38	5093	default:
cparata	0:6d69e896ce38	5094	*val = LSM6DSO_FF_TSH_156mg;
cparata	0:6d69e896ce38	5095	break;
cparata	0:6d69e896ce38	5096	}
cparata	0:6d69e896ce38	5097	return ret;
cparata	0:6d69e896ce38	5098	}
cparata	0:6d69e896ce38	5099
cparata	0:6d69e896ce38	5100	/**
cparata	0:6d69e896ce38	5101	* @brief Free-fall duration event.[set]
cparata	0:6d69e896ce38	5102	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	5103	*
cparata	0:6d69e896ce38	5104	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5105	* @param val change the values of ff_dur in reg FREE_FALL
cparata	0:6d69e896ce38	5106	*
cparata	0:6d69e896ce38	5107	*/
cparata	0:6d69e896ce38	5108	int32_t lsm6dso_ff_dur_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5109	{
cparata	0:6d69e896ce38	5110	lsm6dso_wake_up_dur_t wake_up_dur;
cparata	0:6d69e896ce38	5111	lsm6dso_free_fall_t free_fall;
cparata	0:6d69e896ce38	5112	int32_t ret;
cparata	0:6d69e896ce38	5113
cparata	0:6d69e896ce38	5114	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
cparata	0:6d69e896ce38	5115	if (ret == 0) {
cparata	0:6d69e896ce38	5116	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata	0:6d69e896ce38	5117	}
cparata	0:6d69e896ce38	5118	if (ret == 0) {
cparata	0:6d69e896ce38	5119	wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
cparata	0:6d69e896ce38	5120	free_fall.ff_dur = (uint8_t)val & 0x1FU;
cparata	0:6d69e896ce38	5121	ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR,
cparata	0:6d69e896ce38	5122	(uint8_t*)&wake_up_dur, 1);
cparata	0:6d69e896ce38	5123	}
cparata	0:6d69e896ce38	5124	if (ret == 0) {
cparata	0:6d69e896ce38	5125	ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata	0:6d69e896ce38	5126	}
cparata	0:6d69e896ce38	5127	return ret;
cparata	0:6d69e896ce38	5128	}
cparata	0:6d69e896ce38	5129
cparata	0:6d69e896ce38	5130	/**
cparata	0:6d69e896ce38	5131	* @brief Free-fall duration event.[get]
cparata	0:6d69e896ce38	5132	* 1LSb = 1 / ODR
cparata	0:6d69e896ce38	5133	*
cparata	0:6d69e896ce38	5134	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5135	* @param val change the values of ff_dur in reg FREE_FALL
cparata	0:6d69e896ce38	5136	*
cparata	0:6d69e896ce38	5137	*/
cparata	0:6d69e896ce38	5138	int32_t lsm6dso_ff_dur_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5139	{
cparata	0:6d69e896ce38	5140	lsm6dso_wake_up_dur_t wake_up_dur;
cparata	0:6d69e896ce38	5141	lsm6dso_free_fall_t free_fall;
cparata	0:6d69e896ce38	5142	int32_t ret;
cparata	0:6d69e896ce38	5143
cparata	0:6d69e896ce38	5144	ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
cparata	0:6d69e896ce38	5145	if (ret == 0) {
cparata	0:6d69e896ce38	5146	ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1);
cparata	0:6d69e896ce38	5147	*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
cparata	0:6d69e896ce38	5148	}
cparata	0:6d69e896ce38	5149	return ret;
cparata	0:6d69e896ce38	5150	}
cparata	0:6d69e896ce38	5151
cparata	0:6d69e896ce38	5152	/**
cparata	0:6d69e896ce38	5153	* @}
cparata	0:6d69e896ce38	5154	*
cparata	0:6d69e896ce38	5155	*/
cparata	0:6d69e896ce38	5156
cparata	0:6d69e896ce38	5157	/**
cparata	0:6d69e896ce38	5158	* @defgroup LSM6DSO_fifo
cparata	0:6d69e896ce38	5159	* @brief This section group all the functions concerning the fifo usage
cparata	0:6d69e896ce38	5160	* @{
cparata	0:6d69e896ce38	5161	*
cparata	0:6d69e896ce38	5162	*/
cparata	0:6d69e896ce38	5163
cparata	0:6d69e896ce38	5164	/**
cparata	0:6d69e896ce38	5165	* @brief FIFO watermark level selection.[set]
cparata	0:6d69e896ce38	5166	*
cparata	0:6d69e896ce38	5167	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5168	* @param val change the values of wtm in reg FIFO_CTRL1
cparata	0:6d69e896ce38	5169	*
cparata	0:6d69e896ce38	5170	*/
cparata	0:6d69e896ce38	5171	int32_t lsm6dso_fifo_watermark_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	0:6d69e896ce38	5172	{
cparata	0:6d69e896ce38	5173	lsm6dso_fifo_ctrl1_t fifo_ctrl1;
cparata	0:6d69e896ce38	5174	lsm6dso_fifo_ctrl2_t fifo_ctrl2;
cparata	0:6d69e896ce38	5175	int32_t ret;
cparata	0:6d69e896ce38	5176
cparata	0:6d69e896ce38	5177	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata	0:6d69e896ce38	5178	if (ret == 0) {
cparata	0:6d69e896ce38	5179	fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
cparata	0:6d69e896ce38	5180	fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8);
cparata	0:6d69e896ce38	5181	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
cparata	0:6d69e896ce38	5182	}
cparata	0:6d69e896ce38	5183	if (ret == 0) {
cparata	0:6d69e896ce38	5184	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata	0:6d69e896ce38	5185	}
cparata	0:6d69e896ce38	5186	return ret;
cparata	0:6d69e896ce38	5187	}
cparata	0:6d69e896ce38	5188
cparata	0:6d69e896ce38	5189	/**
cparata	0:6d69e896ce38	5190	* @brief FIFO watermark level selection.[get]
cparata	0:6d69e896ce38	5191	*
cparata	0:6d69e896ce38	5192	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5193	* @param val change the values of wtm in reg FIFO_CTRL1
cparata	0:6d69e896ce38	5194	*
cparata	0:6d69e896ce38	5195	*/
cparata	0:6d69e896ce38	5196	int32_t lsm6dso_fifo_watermark_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	0:6d69e896ce38	5197	{
cparata	0:6d69e896ce38	5198	lsm6dso_fifo_ctrl1_t fifo_ctrl1;
cparata	0:6d69e896ce38	5199	lsm6dso_fifo_ctrl2_t fifo_ctrl2;
cparata	0:6d69e896ce38	5200	int32_t ret;
cparata	0:6d69e896ce38	5201
cparata	0:6d69e896ce38	5202	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1);
cparata	0:6d69e896ce38	5203	if (ret == 0) {
cparata	0:6d69e896ce38	5204	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1);
cparata	0:6d69e896ce38	5205	*val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
cparata	0:6d69e896ce38	5206	}
cparata	0:6d69e896ce38	5207	return ret;
cparata	0:6d69e896ce38	5208	}
cparata	0:6d69e896ce38	5209
cparata	0:6d69e896ce38	5210	/**
cparata	0:6d69e896ce38	5211	* @brief FIFO compression feature initialization request [set].
cparata	0:6d69e896ce38	5212	*
cparata	0:6d69e896ce38	5213	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5214	* @param val change the values of FIFO_COMPR_INIT in
cparata	0:6d69e896ce38	5215	* reg EMB_FUNC_INIT_B
cparata	0:6d69e896ce38	5216	*
cparata	0:6d69e896ce38	5217	*/
cparata	0:6d69e896ce38	5218	int32_t lsm6dso_compression_algo_init_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5219	{
cparata	0:6d69e896ce38	5220	lsm6dso_emb_func_init_b_t reg;
cparata	0:6d69e896ce38	5221	int32_t ret;
cparata	0:6d69e896ce38	5222
cparata	0:6d69e896ce38	5223	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	5224	if (ret == 0) {
cparata	0:6d69e896ce38	5225	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5226	}
cparata	0:6d69e896ce38	5227	if (ret == 0) {
cparata	0:6d69e896ce38	5228	reg.fifo_compr_init = val;
cparata	0:6d69e896ce38	5229	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5230	}
cparata	0:6d69e896ce38	5231	if (ret == 0) {
cparata	0:6d69e896ce38	5232	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	5233	}
cparata	0:6d69e896ce38	5234
cparata	0:6d69e896ce38	5235	return ret;
cparata	0:6d69e896ce38	5236	}
cparata	0:6d69e896ce38	5237
cparata	0:6d69e896ce38	5238	/**
cparata	0:6d69e896ce38	5239	* @brief FIFO compression feature initialization request [get].
cparata	0:6d69e896ce38	5240	*
cparata	0:6d69e896ce38	5241	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5242	* @param val change the values of FIFO_COMPR_INIT in
cparata	0:6d69e896ce38	5243	* reg EMB_FUNC_INIT_B
cparata	0:6d69e896ce38	5244	*
cparata	0:6d69e896ce38	5245	*/
cparata	0:6d69e896ce38	5246	int32_t lsm6dso_compression_algo_init_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5247	{
cparata	0:6d69e896ce38	5248	lsm6dso_emb_func_init_b_t reg;
cparata	0:6d69e896ce38	5249	int32_t ret;
cparata	0:6d69e896ce38	5250
cparata	0:6d69e896ce38	5251	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	5252	if (ret == 0) {
cparata	0:6d69e896ce38	5253	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5254	}
cparata	0:6d69e896ce38	5255	if (ret == 0) {
cparata	0:6d69e896ce38	5256	*val = reg.fifo_compr_init;
cparata	0:6d69e896ce38	5257	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	5258	}
cparata	0:6d69e896ce38	5259
cparata	0:6d69e896ce38	5260	return ret;
cparata	0:6d69e896ce38	5261	}
cparata	0:6d69e896ce38	5262
cparata	0:6d69e896ce38	5263	/**
cparata	0:6d69e896ce38	5264	* @brief Enable and configure compression algo.[set]
cparata	0:6d69e896ce38	5265	*
cparata	0:6d69e896ce38	5266	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5267	* @param val change the values of uncoptr_rate in
cparata	0:6d69e896ce38	5268	* reg FIFO_CTRL2
cparata	0:6d69e896ce38	5269	*
cparata	0:6d69e896ce38	5270	*/
cparata	0:6d69e896ce38	5271	int32_t lsm6dso_compression_algo_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5272	lsm6dso_uncoptr_rate_t val)
cparata	0:6d69e896ce38	5273	{
cparata	0:6d69e896ce38	5274	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	0:6d69e896ce38	5275	lsm6dso_fifo_ctrl2_t fifo_ctrl2;
cparata	0:6d69e896ce38	5276	int32_t ret;
cparata	0:6d69e896ce38	5277
cparata	0:6d69e896ce38	5278	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	5279	if (ret == 0) {
cparata	0:6d69e896ce38	5280	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	0:6d69e896ce38	5281	(uint8_t*)&emb_func_en_b, 1);
cparata	0:6d69e896ce38	5282	}
cparata	0:6d69e896ce38	5283	if (ret == 0) {
cparata	0:6d69e896ce38	5284	emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
cparata	0:6d69e896ce38	5285	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	0:6d69e896ce38	5286	(uint8_t*)&emb_func_en_b, 1);
cparata	0:6d69e896ce38	5287	}
cparata	0:6d69e896ce38	5288	if (ret == 0) {
cparata	0:6d69e896ce38	5289	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	5290	}
cparata	0:6d69e896ce38	5291	if (ret == 0) {
cparata	0:6d69e896ce38	5292
cparata	0:6d69e896ce38	5293	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
cparata	0:6d69e896ce38	5294	(uint8_t*)&fifo_ctrl2, 1);
cparata	0:6d69e896ce38	5295	}
cparata	0:6d69e896ce38	5296	if (ret == 0) {
cparata	0:6d69e896ce38	5297	fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
cparata	0:6d69e896ce38	5298	fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
cparata	0:6d69e896ce38	5299	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
cparata	0:6d69e896ce38	5300	(uint8_t*)&fifo_ctrl2, 1);
cparata	0:6d69e896ce38	5301	}
cparata	0:6d69e896ce38	5302	return ret;
cparata	0:6d69e896ce38	5303	}
cparata	0:6d69e896ce38	5304
cparata	0:6d69e896ce38	5305	/**
cparata	0:6d69e896ce38	5306	* @brief Enable and configure compression algo.[get]
cparata	0:6d69e896ce38	5307	*
cparata	0:6d69e896ce38	5308	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5309	* @param val Get the values of uncoptr_rate in
cparata	0:6d69e896ce38	5310	* reg FIFO_CTRL2
cparata	0:6d69e896ce38	5311	*
cparata	0:6d69e896ce38	5312	*/
cparata	0:6d69e896ce38	5313	int32_t lsm6dso_compression_algo_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5314	lsm6dso_uncoptr_rate_t *val)
cparata	0:6d69e896ce38	5315	{
cparata	0:6d69e896ce38	5316	lsm6dso_fifo_ctrl2_t reg;
cparata	0:6d69e896ce38	5317	int32_t ret;
cparata	0:6d69e896ce38	5318
cparata	0:6d69e896ce38	5319	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5320
cparata	0:6d69e896ce38	5321	switch ((reg.fifo_compr_rt_en<<2) \| reg.uncoptr_rate) {
cparata	0:6d69e896ce38	5322	case LSM6DSO_CMP_DISABLE:
cparata	0:6d69e896ce38	5323	*val = LSM6DSO_CMP_DISABLE;
cparata	0:6d69e896ce38	5324	break;
cparata	0:6d69e896ce38	5325	case LSM6DSO_CMP_ALWAYS:
cparata	0:6d69e896ce38	5326	*val = LSM6DSO_CMP_ALWAYS;
cparata	0:6d69e896ce38	5327	break;
cparata	0:6d69e896ce38	5328	case LSM6DSO_CMP_8_TO_1:
cparata	0:6d69e896ce38	5329	*val = LSM6DSO_CMP_8_TO_1;
cparata	0:6d69e896ce38	5330	break;
cparata	0:6d69e896ce38	5331	case LSM6DSO_CMP_16_TO_1:
cparata	0:6d69e896ce38	5332	*val = LSM6DSO_CMP_16_TO_1;
cparata	0:6d69e896ce38	5333	break;
cparata	0:6d69e896ce38	5334	case LSM6DSO_CMP_32_TO_1:
cparata	0:6d69e896ce38	5335	*val = LSM6DSO_CMP_32_TO_1;
cparata	0:6d69e896ce38	5336	break;
cparata	0:6d69e896ce38	5337	default:
cparata	0:6d69e896ce38	5338	*val = LSM6DSO_CMP_DISABLE;
cparata	0:6d69e896ce38	5339	break;
cparata	0:6d69e896ce38	5340	}
cparata	0:6d69e896ce38	5341	return ret;
cparata	0:6d69e896ce38	5342	}
cparata	0:6d69e896ce38	5343
cparata	0:6d69e896ce38	5344	/**
cparata	0:6d69e896ce38	5345	* @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
cparata	0:6d69e896ce38	5346	*
cparata	0:6d69e896ce38	5347	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5348	* @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5349	*
cparata	0:6d69e896ce38	5350	*/
cparata	0:6d69e896ce38	5351	int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5352	uint8_t val)
cparata	0:6d69e896ce38	5353	{
cparata	0:6d69e896ce38	5354	lsm6dso_fifo_ctrl2_t reg;
cparata	0:6d69e896ce38	5355	int32_t ret;
cparata	0:6d69e896ce38	5356
cparata	0:6d69e896ce38	5357	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5358	if (ret == 0) {
cparata	0:6d69e896ce38	5359	reg.odrchg_en = val;
cparata	0:6d69e896ce38	5360	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5361	}
cparata	0:6d69e896ce38	5362	return ret;
cparata	0:6d69e896ce38	5363	}
cparata	0:6d69e896ce38	5364
cparata	0:6d69e896ce38	5365	/**
cparata	0:6d69e896ce38	5366	* @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
cparata	0:6d69e896ce38	5367	*
cparata	0:6d69e896ce38	5368	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5369	* @param val change the values of odrchg_en in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5370	*
cparata	0:6d69e896ce38	5371	*/
cparata	0:6d69e896ce38	5372	int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5373	uint8_t *val)
cparata	0:6d69e896ce38	5374	{
cparata	0:6d69e896ce38	5375	lsm6dso_fifo_ctrl2_t reg;
cparata	0:6d69e896ce38	5376	int32_t ret;
cparata	0:6d69e896ce38	5377
cparata	0:6d69e896ce38	5378	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5379	*val = reg.odrchg_en;
cparata	0:6d69e896ce38	5380
cparata	0:6d69e896ce38	5381	return ret;
cparata	0:6d69e896ce38	5382	}
cparata	0:6d69e896ce38	5383
cparata	0:6d69e896ce38	5384	/**
cparata	0:6d69e896ce38	5385	* @brief Enables/Disables compression algorithm runtime.[set]
cparata	0:6d69e896ce38	5386	*
cparata	0:6d69e896ce38	5387	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5388	* @param val change the values of fifo_compr_rt_en in
cparata	0:6d69e896ce38	5389	* reg FIFO_CTRL2
cparata	0:6d69e896ce38	5390	*
cparata	0:6d69e896ce38	5391	*/
cparata	0:6d69e896ce38	5392	int32_t lsm6dso_compression_algo_real_time_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5393	uint8_t val)
cparata	0:6d69e896ce38	5394	{
cparata	0:6d69e896ce38	5395	lsm6dso_fifo_ctrl2_t reg;
cparata	0:6d69e896ce38	5396	int32_t ret;
cparata	0:6d69e896ce38	5397
cparata	0:6d69e896ce38	5398	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5399	if (ret == 0) {
cparata	0:6d69e896ce38	5400	reg.fifo_compr_rt_en = val;
cparata	0:6d69e896ce38	5401	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5402	}
cparata	0:6d69e896ce38	5403	return ret;
cparata	0:6d69e896ce38	5404	}
cparata	0:6d69e896ce38	5405
cparata	0:6d69e896ce38	5406	/**
cparata	0:6d69e896ce38	5407	* @brief Enables/Disables compression algorithm runtime. [get]
cparata	0:6d69e896ce38	5408	*
cparata	0:6d69e896ce38	5409	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5410	* @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5411	*
cparata	0:6d69e896ce38	5412	*/
cparata	0:6d69e896ce38	5413	int32_t lsm6dso_compression_algo_real_time_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5414	uint8_t *val)
cparata	0:6d69e896ce38	5415	{
cparata	0:6d69e896ce38	5416	lsm6dso_fifo_ctrl2_t reg;
cparata	0:6d69e896ce38	5417	int32_t ret;
cparata	0:6d69e896ce38	5418
cparata	0:6d69e896ce38	5419	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5420	*val = reg.fifo_compr_rt_en;
cparata	0:6d69e896ce38	5421
cparata	0:6d69e896ce38	5422	return ret;
cparata	0:6d69e896ce38	5423	}
cparata	0:6d69e896ce38	5424
cparata	0:6d69e896ce38	5425	/**
cparata	0:6d69e896ce38	5426	* @brief Sensing chain FIFO stop values memorization at
cparata	0:6d69e896ce38	5427	* threshold level.[set]
cparata	0:6d69e896ce38	5428	*
cparata	0:6d69e896ce38	5429	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5430	* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5431	*
cparata	0:6d69e896ce38	5432	*/
cparata	0:6d69e896ce38	5433	int32_t lsm6dso_fifo_stop_on_wtm_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5434	{
cparata	0:6d69e896ce38	5435	lsm6dso_fifo_ctrl2_t reg;
cparata	0:6d69e896ce38	5436	int32_t ret;
cparata	0:6d69e896ce38	5437
cparata	0:6d69e896ce38	5438	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5439	if (ret == 0) {
cparata	0:6d69e896ce38	5440	reg.stop_on_wtm = val;
cparata	0:6d69e896ce38	5441	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5442	}
cparata	0:6d69e896ce38	5443	return ret;
cparata	0:6d69e896ce38	5444	}
cparata	0:6d69e896ce38	5445
cparata	0:6d69e896ce38	5446	/**
cparata	0:6d69e896ce38	5447	* @brief Sensing chain FIFO stop values memorization at
cparata	0:6d69e896ce38	5448	* threshold level.[get]
cparata	0:6d69e896ce38	5449	*
cparata	0:6d69e896ce38	5450	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5451	* @param val change the values of stop_on_wtm in reg FIFO_CTRL2
cparata	0:6d69e896ce38	5452	*
cparata	0:6d69e896ce38	5453	*/
cparata	0:6d69e896ce38	5454	int32_t lsm6dso_fifo_stop_on_wtm_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5455	{
cparata	0:6d69e896ce38	5456	lsm6dso_fifo_ctrl2_t reg;
cparata	0:6d69e896ce38	5457	int32_t ret;
cparata	0:6d69e896ce38	5458
cparata	0:6d69e896ce38	5459	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5460	*val = reg.stop_on_wtm;
cparata	0:6d69e896ce38	5461
cparata	0:6d69e896ce38	5462	return ret;
cparata	0:6d69e896ce38	5463	}
cparata	0:6d69e896ce38	5464
cparata	0:6d69e896ce38	5465	/**
cparata	0:6d69e896ce38	5466	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5467	* for accelerometer data.[set]
cparata	0:6d69e896ce38	5468	*
cparata	0:6d69e896ce38	5469	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5470	* @param val change the values of bdr_xl in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5471	*
cparata	0:6d69e896ce38	5472	*/
cparata	0:6d69e896ce38	5473	int32_t lsm6dso_fifo_xl_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_xl_t val)
cparata	0:6d69e896ce38	5474	{
cparata	0:6d69e896ce38	5475	lsm6dso_fifo_ctrl3_t reg;
cparata	0:6d69e896ce38	5476	int32_t ret;
cparata	0:6d69e896ce38	5477
cparata	0:6d69e896ce38	5478	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5479	if (ret == 0) {
cparata	0:6d69e896ce38	5480	reg.bdr_xl = (uint8_t)val;
cparata	0:6d69e896ce38	5481	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5482	}
cparata	0:6d69e896ce38	5483	return ret;
cparata	0:6d69e896ce38	5484	}
cparata	0:6d69e896ce38	5485
cparata	0:6d69e896ce38	5486	/**
cparata	0:6d69e896ce38	5487	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5488	* for accelerometer data.[get]
cparata	0:6d69e896ce38	5489	*
cparata	0:6d69e896ce38	5490	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5491	* @param val Get the values of bdr_xl in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5492	*
cparata	0:6d69e896ce38	5493	*/
cparata	0:6d69e896ce38	5494	int32_t lsm6dso_fifo_xl_batch_get(lsm6dso_ctx_t ctx, lsm6dso_bdr_xl_t val)
cparata	0:6d69e896ce38	5495	{
cparata	0:6d69e896ce38	5496	lsm6dso_fifo_ctrl3_t reg;
cparata	0:6d69e896ce38	5497	int32_t ret;
cparata	0:6d69e896ce38	5498
cparata	0:6d69e896ce38	5499	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5500	switch (reg.bdr_xl) {
cparata	0:6d69e896ce38	5501	case LSM6DSO_XL_NOT_BATCHED:
cparata	0:6d69e896ce38	5502	*val = LSM6DSO_XL_NOT_BATCHED;
cparata	0:6d69e896ce38	5503	break;
cparata	0:6d69e896ce38	5504	case LSM6DSO_XL_BATCHED_AT_12Hz5:
cparata	0:6d69e896ce38	5505	*val = LSM6DSO_XL_BATCHED_AT_12Hz5;
cparata	0:6d69e896ce38	5506	break;
cparata	0:6d69e896ce38	5507	case LSM6DSO_XL_BATCHED_AT_26Hz:
cparata	0:6d69e896ce38	5508	*val = LSM6DSO_XL_BATCHED_AT_26Hz;
cparata	0:6d69e896ce38	5509	break;
cparata	0:6d69e896ce38	5510	case LSM6DSO_XL_BATCHED_AT_52Hz:
cparata	0:6d69e896ce38	5511	*val = LSM6DSO_XL_BATCHED_AT_52Hz;
cparata	0:6d69e896ce38	5512	break;
cparata	0:6d69e896ce38	5513	case LSM6DSO_XL_BATCHED_AT_104Hz:
cparata	0:6d69e896ce38	5514	*val = LSM6DSO_XL_BATCHED_AT_104Hz;
cparata	0:6d69e896ce38	5515	break;
cparata	0:6d69e896ce38	5516	case LSM6DSO_XL_BATCHED_AT_208Hz:
cparata	0:6d69e896ce38	5517	*val = LSM6DSO_XL_BATCHED_AT_208Hz;
cparata	0:6d69e896ce38	5518	break;
cparata	0:6d69e896ce38	5519	case LSM6DSO_XL_BATCHED_AT_417Hz:
cparata	0:6d69e896ce38	5520	*val = LSM6DSO_XL_BATCHED_AT_417Hz;
cparata	0:6d69e896ce38	5521	break;
cparata	0:6d69e896ce38	5522	case LSM6DSO_XL_BATCHED_AT_833Hz:
cparata	0:6d69e896ce38	5523	*val = LSM6DSO_XL_BATCHED_AT_833Hz;
cparata	0:6d69e896ce38	5524	break;
cparata	0:6d69e896ce38	5525	case LSM6DSO_XL_BATCHED_AT_1667Hz:
cparata	0:6d69e896ce38	5526	*val = LSM6DSO_XL_BATCHED_AT_1667Hz;
cparata	0:6d69e896ce38	5527	break;
cparata	0:6d69e896ce38	5528	case LSM6DSO_XL_BATCHED_AT_3333Hz:
cparata	0:6d69e896ce38	5529	*val = LSM6DSO_XL_BATCHED_AT_3333Hz;
cparata	0:6d69e896ce38	5530	break;
cparata	0:6d69e896ce38	5531	case LSM6DSO_XL_BATCHED_AT_6667Hz:
cparata	0:6d69e896ce38	5532	*val = LSM6DSO_XL_BATCHED_AT_6667Hz;
cparata	0:6d69e896ce38	5533	break;
cparata	0:6d69e896ce38	5534	case LSM6DSO_XL_BATCHED_AT_6Hz5:
cparata	0:6d69e896ce38	5535	*val = LSM6DSO_XL_BATCHED_AT_6Hz5;
cparata	0:6d69e896ce38	5536	break;
cparata	0:6d69e896ce38	5537	default:
cparata	0:6d69e896ce38	5538	*val = LSM6DSO_XL_NOT_BATCHED;
cparata	0:6d69e896ce38	5539	break;
cparata	0:6d69e896ce38	5540	}
cparata	0:6d69e896ce38	5541
cparata	0:6d69e896ce38	5542	return ret;
cparata	0:6d69e896ce38	5543	}
cparata	0:6d69e896ce38	5544
cparata	0:6d69e896ce38	5545	/**
cparata	0:6d69e896ce38	5546	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5547	* for gyroscope data.[set]
cparata	0:6d69e896ce38	5548	*
cparata	0:6d69e896ce38	5549	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5550	* @param val change the values of bdr_gy in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5551	*
cparata	0:6d69e896ce38	5552	*/
cparata	0:6d69e896ce38	5553	int32_t lsm6dso_fifo_gy_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_gy_t val)
cparata	0:6d69e896ce38	5554	{
cparata	0:6d69e896ce38	5555	lsm6dso_fifo_ctrl3_t reg;
cparata	0:6d69e896ce38	5556	int32_t ret;
cparata	0:6d69e896ce38	5557
cparata	0:6d69e896ce38	5558	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5559	if (ret == 0) {
cparata	0:6d69e896ce38	5560	reg.bdr_gy = (uint8_t)val;
cparata	0:6d69e896ce38	5561	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5562	}
cparata	0:6d69e896ce38	5563	return ret;
cparata	0:6d69e896ce38	5564	}
cparata	0:6d69e896ce38	5565
cparata	0:6d69e896ce38	5566	/**
cparata	0:6d69e896ce38	5567	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5568	* for gyroscope data.[get]
cparata	0:6d69e896ce38	5569	*
cparata	0:6d69e896ce38	5570	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5571	* @param val Get the values of bdr_gy in reg FIFO_CTRL3
cparata	0:6d69e896ce38	5572	*
cparata	0:6d69e896ce38	5573	*/
cparata	0:6d69e896ce38	5574	int32_t lsm6dso_fifo_gy_batch_get(lsm6dso_ctx_t ctx, lsm6dso_bdr_gy_t val)
cparata	0:6d69e896ce38	5575	{
cparata	0:6d69e896ce38	5576	lsm6dso_fifo_ctrl3_t reg;
cparata	0:6d69e896ce38	5577	int32_t ret;
cparata	0:6d69e896ce38	5578
cparata	0:6d69e896ce38	5579	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5580	switch (reg.bdr_gy) {
cparata	0:6d69e896ce38	5581	case LSM6DSO_GY_NOT_BATCHED:
cparata	0:6d69e896ce38	5582	*val = LSM6DSO_GY_NOT_BATCHED;
cparata	0:6d69e896ce38	5583	break;
cparata	0:6d69e896ce38	5584	case LSM6DSO_GY_BATCHED_AT_12Hz5:
cparata	0:6d69e896ce38	5585	*val = LSM6DSO_GY_BATCHED_AT_12Hz5;
cparata	0:6d69e896ce38	5586	break;
cparata	0:6d69e896ce38	5587	case LSM6DSO_GY_BATCHED_AT_26Hz:
cparata	0:6d69e896ce38	5588	*val = LSM6DSO_GY_BATCHED_AT_26Hz;
cparata	0:6d69e896ce38	5589	break;
cparata	0:6d69e896ce38	5590	case LSM6DSO_GY_BATCHED_AT_52Hz:
cparata	0:6d69e896ce38	5591	*val = LSM6DSO_GY_BATCHED_AT_52Hz;
cparata	0:6d69e896ce38	5592	break;
cparata	0:6d69e896ce38	5593	case LSM6DSO_GY_BATCHED_AT_104Hz:
cparata	0:6d69e896ce38	5594	*val = LSM6DSO_GY_BATCHED_AT_104Hz;
cparata	0:6d69e896ce38	5595	break;
cparata	0:6d69e896ce38	5596	case LSM6DSO_GY_BATCHED_AT_208Hz:
cparata	0:6d69e896ce38	5597	*val = LSM6DSO_GY_BATCHED_AT_208Hz;
cparata	0:6d69e896ce38	5598	break;
cparata	0:6d69e896ce38	5599	case LSM6DSO_GY_BATCHED_AT_417Hz:
cparata	0:6d69e896ce38	5600	*val = LSM6DSO_GY_BATCHED_AT_417Hz;
cparata	0:6d69e896ce38	5601	break;
cparata	0:6d69e896ce38	5602	case LSM6DSO_GY_BATCHED_AT_833Hz:
cparata	0:6d69e896ce38	5603	*val = LSM6DSO_GY_BATCHED_AT_833Hz;
cparata	0:6d69e896ce38	5604	break;
cparata	0:6d69e896ce38	5605	case LSM6DSO_GY_BATCHED_AT_1667Hz:
cparata	0:6d69e896ce38	5606	*val = LSM6DSO_GY_BATCHED_AT_1667Hz;
cparata	0:6d69e896ce38	5607	break;
cparata	0:6d69e896ce38	5608	case LSM6DSO_GY_BATCHED_AT_3333Hz:
cparata	0:6d69e896ce38	5609	*val = LSM6DSO_GY_BATCHED_AT_3333Hz;
cparata	0:6d69e896ce38	5610	break;
cparata	0:6d69e896ce38	5611	case LSM6DSO_GY_BATCHED_AT_6667Hz:
cparata	0:6d69e896ce38	5612	*val = LSM6DSO_GY_BATCHED_AT_6667Hz;
cparata	0:6d69e896ce38	5613	break;
cparata	0:6d69e896ce38	5614	case LSM6DSO_GY_BATCHED_AT_6Hz5:
cparata	0:6d69e896ce38	5615	*val = LSM6DSO_GY_BATCHED_AT_6Hz5;
cparata	0:6d69e896ce38	5616	break;
cparata	0:6d69e896ce38	5617	default:
cparata	0:6d69e896ce38	5618	*val = LSM6DSO_GY_NOT_BATCHED;
cparata	0:6d69e896ce38	5619	break;
cparata	0:6d69e896ce38	5620	}
cparata	0:6d69e896ce38	5621	return ret;
cparata	0:6d69e896ce38	5622	}
cparata	0:6d69e896ce38	5623
cparata	0:6d69e896ce38	5624	/**
cparata	0:6d69e896ce38	5625	* @brief FIFO mode selection.[set]
cparata	0:6d69e896ce38	5626	*
cparata	0:6d69e896ce38	5627	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5628	* @param val change the values of fifo_mode in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5629	*
cparata	0:6d69e896ce38	5630	*/
cparata	0:6d69e896ce38	5631	int32_t lsm6dso_fifo_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_fifo_mode_t val)
cparata	0:6d69e896ce38	5632	{
cparata	0:6d69e896ce38	5633	lsm6dso_fifo_ctrl4_t reg;
cparata	0:6d69e896ce38	5634	int32_t ret;
cparata	0:6d69e896ce38	5635
cparata	0:6d69e896ce38	5636	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5637	if (ret == 0) {
cparata	0:6d69e896ce38	5638	reg.fifo_mode = (uint8_t)val;
cparata	0:6d69e896ce38	5639	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5640	}
cparata	0:6d69e896ce38	5641	return ret;
cparata	0:6d69e896ce38	5642	}
cparata	0:6d69e896ce38	5643
cparata	0:6d69e896ce38	5644	/**
cparata	0:6d69e896ce38	5645	* @brief FIFO mode selection.[get]
cparata	0:6d69e896ce38	5646	*
cparata	0:6d69e896ce38	5647	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5648	* @param val Get the values of fifo_mode in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5649	*
cparata	0:6d69e896ce38	5650	*/
cparata	0:6d69e896ce38	5651	int32_t lsm6dso_fifo_mode_get(lsm6dso_ctx_t ctx, lsm6dso_fifo_mode_t val)
cparata	0:6d69e896ce38	5652	{
cparata	0:6d69e896ce38	5653	lsm6dso_fifo_ctrl4_t reg;
cparata	0:6d69e896ce38	5654	int32_t ret;
cparata	0:6d69e896ce38	5655
cparata	0:6d69e896ce38	5656	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5657
cparata	0:6d69e896ce38	5658	switch (reg.fifo_mode) {
cparata	0:6d69e896ce38	5659	case LSM6DSO_BYPASS_MODE:
cparata	0:6d69e896ce38	5660	*val = LSM6DSO_BYPASS_MODE;
cparata	0:6d69e896ce38	5661	break;
cparata	0:6d69e896ce38	5662	case LSM6DSO_FIFO_MODE:
cparata	0:6d69e896ce38	5663	*val = LSM6DSO_FIFO_MODE;
cparata	0:6d69e896ce38	5664	break;
cparata	0:6d69e896ce38	5665	case LSM6DSO_STREAM_TO_FIFO_MODE:
cparata	0:6d69e896ce38	5666	*val = LSM6DSO_STREAM_TO_FIFO_MODE;
cparata	0:6d69e896ce38	5667	break;
cparata	0:6d69e896ce38	5668	case LSM6DSO_BYPASS_TO_STREAM_MODE:
cparata	0:6d69e896ce38	5669	*val = LSM6DSO_BYPASS_TO_STREAM_MODE;
cparata	0:6d69e896ce38	5670	break;
cparata	0:6d69e896ce38	5671	case LSM6DSO_STREAM_MODE:
cparata	0:6d69e896ce38	5672	*val = LSM6DSO_STREAM_MODE;
cparata	0:6d69e896ce38	5673	break;
cparata	0:6d69e896ce38	5674	case LSM6DSO_BYPASS_TO_FIFO_MODE:
cparata	0:6d69e896ce38	5675	*val = LSM6DSO_BYPASS_TO_FIFO_MODE;
cparata	0:6d69e896ce38	5676	break;
cparata	0:6d69e896ce38	5677	default:
cparata	0:6d69e896ce38	5678	*val = LSM6DSO_BYPASS_MODE;
cparata	0:6d69e896ce38	5679	break;
cparata	0:6d69e896ce38	5680	}
cparata	0:6d69e896ce38	5681	return ret;
cparata	0:6d69e896ce38	5682	}
cparata	0:6d69e896ce38	5683
cparata	0:6d69e896ce38	5684	/**
cparata	0:6d69e896ce38	5685	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5686	* for temperature data.[set]
cparata	0:6d69e896ce38	5687	*
cparata	0:6d69e896ce38	5688	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5689	* @param val change the values of odr_t_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5690	*
cparata	0:6d69e896ce38	5691	*/
cparata	0:6d69e896ce38	5692	int32_t lsm6dso_fifo_temp_batch_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5693	lsm6dso_odr_t_batch_t val)
cparata	0:6d69e896ce38	5694	{
cparata	0:6d69e896ce38	5695	lsm6dso_fifo_ctrl4_t reg;
cparata	0:6d69e896ce38	5696	int32_t ret;
cparata	0:6d69e896ce38	5697
cparata	0:6d69e896ce38	5698	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5699	if (ret == 0) {
cparata	0:6d69e896ce38	5700	reg.odr_t_batch = (uint8_t)val;
cparata	0:6d69e896ce38	5701	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5702	}
cparata	0:6d69e896ce38	5703	return ret;
cparata	0:6d69e896ce38	5704	}
cparata	0:6d69e896ce38	5705
cparata	0:6d69e896ce38	5706	/**
cparata	0:6d69e896ce38	5707	* @brief Selects Batching Data Rate (writing frequency in FIFO)
cparata	0:6d69e896ce38	5708	* for temperature data.[get]
cparata	0:6d69e896ce38	5709	*
cparata	0:6d69e896ce38	5710	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5711	* @param val Get the values of odr_t_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5712	*
cparata	0:6d69e896ce38	5713	*/
cparata	0:6d69e896ce38	5714	int32_t lsm6dso_fifo_temp_batch_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5715	lsm6dso_odr_t_batch_t *val)
cparata	0:6d69e896ce38	5716	{
cparata	0:6d69e896ce38	5717	lsm6dso_fifo_ctrl4_t reg;
cparata	0:6d69e896ce38	5718	int32_t ret;
cparata	0:6d69e896ce38	5719
cparata	0:6d69e896ce38	5720	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5721
cparata	0:6d69e896ce38	5722	switch (reg.odr_t_batch) {
cparata	0:6d69e896ce38	5723	case LSM6DSO_TEMP_NOT_BATCHED:
cparata	0:6d69e896ce38	5724	*val = LSM6DSO_TEMP_NOT_BATCHED;
cparata	0:6d69e896ce38	5725	break;
cparata	0:6d69e896ce38	5726	case LSM6DSO_TEMP_BATCHED_AT_1Hz6:
cparata	0:6d69e896ce38	5727	*val = LSM6DSO_TEMP_BATCHED_AT_1Hz6;
cparata	0:6d69e896ce38	5728	break;
cparata	0:6d69e896ce38	5729	case LSM6DSO_TEMP_BATCHED_AT_12Hz5:
cparata	0:6d69e896ce38	5730	*val = LSM6DSO_TEMP_BATCHED_AT_12Hz5;
cparata	0:6d69e896ce38	5731	break;
cparata	0:6d69e896ce38	5732	case LSM6DSO_TEMP_BATCHED_AT_52Hz:
cparata	0:6d69e896ce38	5733	*val = LSM6DSO_TEMP_BATCHED_AT_52Hz;
cparata	0:6d69e896ce38	5734	break;
cparata	0:6d69e896ce38	5735	default:
cparata	0:6d69e896ce38	5736	*val = LSM6DSO_TEMP_NOT_BATCHED;
cparata	0:6d69e896ce38	5737	break;
cparata	0:6d69e896ce38	5738	}
cparata	0:6d69e896ce38	5739	return ret;
cparata	0:6d69e896ce38	5740	}
cparata	0:6d69e896ce38	5741
cparata	0:6d69e896ce38	5742	/**
cparata	0:6d69e896ce38	5743	* @brief Selects decimation for timestamp batching in FIFO.
cparata	0:6d69e896ce38	5744	* Writing rate will be the maximum rate between XL and
cparata	0:6d69e896ce38	5745	* GYRO BDR divided by decimation decoder.[set]
cparata	0:6d69e896ce38	5746	*
cparata	0:6d69e896ce38	5747	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5748	* @param val change the values of odr_ts_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5749	*
cparata	0:6d69e896ce38	5750	*/
cparata	0:6d69e896ce38	5751	int32_t lsm6dso_fifo_timestamp_decimation_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5752	lsm6dso_odr_ts_batch_t val)
cparata	0:6d69e896ce38	5753	{
cparata	0:6d69e896ce38	5754	lsm6dso_fifo_ctrl4_t reg;
cparata	0:6d69e896ce38	5755	int32_t ret;
cparata	0:6d69e896ce38	5756
cparata	0:6d69e896ce38	5757	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5758	if (ret == 0) {
cparata	0:6d69e896ce38	5759	reg.odr_ts_batch = (uint8_t)val;
cparata	0:6d69e896ce38	5760	ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5761	}
cparata	0:6d69e896ce38	5762	return ret;
cparata	0:6d69e896ce38	5763	}
cparata	0:6d69e896ce38	5764
cparata	0:6d69e896ce38	5765	/**
cparata	0:6d69e896ce38	5766	* @brief Selects decimation for timestamp batching in FIFO.
cparata	0:6d69e896ce38	5767	* Writing rate will be the maximum rate between XL and
cparata	0:6d69e896ce38	5768	* GYRO BDR divided by decimation decoder.[get]
cparata	0:6d69e896ce38	5769	*
cparata	0:6d69e896ce38	5770	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5771	* @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
cparata	0:6d69e896ce38	5772	*
cparata	0:6d69e896ce38	5773	*/
cparata	0:6d69e896ce38	5774	int32_t lsm6dso_fifo_timestamp_decimation_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5775	lsm6dso_odr_ts_batch_t *val)
cparata	0:6d69e896ce38	5776	{
cparata	0:6d69e896ce38	5777	lsm6dso_fifo_ctrl4_t reg;
cparata	0:6d69e896ce38	5778	int32_t ret;
cparata	0:6d69e896ce38	5779
cparata	0:6d69e896ce38	5780	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5781	switch (reg.odr_ts_batch) {
cparata	0:6d69e896ce38	5782	case LSM6DSO_NO_DECIMATION:
cparata	0:6d69e896ce38	5783	*val = LSM6DSO_NO_DECIMATION;
cparata	0:6d69e896ce38	5784	break;
cparata	0:6d69e896ce38	5785	case LSM6DSO_DEC_1:
cparata	0:6d69e896ce38	5786	*val = LSM6DSO_DEC_1;
cparata	0:6d69e896ce38	5787	break;
cparata	0:6d69e896ce38	5788	case LSM6DSO_DEC_8:
cparata	0:6d69e896ce38	5789	*val = LSM6DSO_DEC_8;
cparata	0:6d69e896ce38	5790	break;
cparata	0:6d69e896ce38	5791	case LSM6DSO_DEC_32:
cparata	0:6d69e896ce38	5792	*val = LSM6DSO_DEC_32;
cparata	0:6d69e896ce38	5793	break;
cparata	0:6d69e896ce38	5794	default:
cparata	0:6d69e896ce38	5795	*val = LSM6DSO_NO_DECIMATION;
cparata	0:6d69e896ce38	5796	break;
cparata	0:6d69e896ce38	5797	}
cparata	0:6d69e896ce38	5798	return ret;
cparata	0:6d69e896ce38	5799	}
cparata	0:6d69e896ce38	5800
cparata	0:6d69e896ce38	5801	/**
cparata	0:6d69e896ce38	5802	* @brief Selects the trigger for the internal counter of batching events
cparata	0:6d69e896ce38	5803	* between XL and gyro.[set]
cparata	0:6d69e896ce38	5804	*
cparata	0:6d69e896ce38	5805	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5806	* @param val change the values of trig_counter_bdr
cparata	0:6d69e896ce38	5807	* in reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5808	*
cparata	0:6d69e896ce38	5809	*/
cparata	0:6d69e896ce38	5810	int32_t lsm6dso_fifo_cnt_event_batch_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5811	lsm6dso_trig_counter_bdr_t val)
cparata	0:6d69e896ce38	5812	{
cparata	0:6d69e896ce38	5813	lsm6dso_counter_bdr_reg1_t reg;
cparata	0:6d69e896ce38	5814	int32_t ret;
cparata	0:6d69e896ce38	5815
cparata	0:6d69e896ce38	5816	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5817	if (ret == 0) {
cparata	0:6d69e896ce38	5818	reg.trig_counter_bdr = (uint8_t)val;
cparata	0:6d69e896ce38	5819	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5820	}
cparata	0:6d69e896ce38	5821	return ret;
cparata	0:6d69e896ce38	5822	}
cparata	0:6d69e896ce38	5823
cparata	0:6d69e896ce38	5824	/**
cparata	0:6d69e896ce38	5825	* @brief Selects the trigger for the internal counter of batching events
cparata	0:6d69e896ce38	5826	* between XL and gyro.[get]
cparata	0:6d69e896ce38	5827	*
cparata	0:6d69e896ce38	5828	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5829	* @param val Get the values of trig_counter_bdr
cparata	0:6d69e896ce38	5830	* in reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5831	*
cparata	0:6d69e896ce38	5832	*/
cparata	0:6d69e896ce38	5833	int32_t lsm6dso_fifo_cnt_event_batch_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5834	lsm6dso_trig_counter_bdr_t *val)
cparata	0:6d69e896ce38	5835	{
cparata	0:6d69e896ce38	5836	lsm6dso_counter_bdr_reg1_t reg;
cparata	0:6d69e896ce38	5837	int32_t ret;
cparata	0:6d69e896ce38	5838
cparata	0:6d69e896ce38	5839	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5840	switch (reg.trig_counter_bdr) {
cparata	0:6d69e896ce38	5841	case LSM6DSO_XL_BATCH_EVENT:
cparata	0:6d69e896ce38	5842	*val = LSM6DSO_XL_BATCH_EVENT;
cparata	0:6d69e896ce38	5843	break;
cparata	0:6d69e896ce38	5844	case LSM6DSO_GYRO_BATCH_EVENT:
cparata	0:6d69e896ce38	5845	*val = LSM6DSO_GYRO_BATCH_EVENT;
cparata	0:6d69e896ce38	5846	break;
cparata	0:6d69e896ce38	5847	default:
cparata	0:6d69e896ce38	5848	*val = LSM6DSO_XL_BATCH_EVENT;
cparata	0:6d69e896ce38	5849	break;
cparata	0:6d69e896ce38	5850	}
cparata	0:6d69e896ce38	5851	return ret;
cparata	0:6d69e896ce38	5852	}
cparata	0:6d69e896ce38	5853
cparata	0:6d69e896ce38	5854	/**
cparata	0:6d69e896ce38	5855	* @brief Resets the internal counter of batching vents for a single sensor.
cparata	0:6d69e896ce38	5856	* This bit is automatically reset to zero if it was set to ‘1’.[set]
cparata	0:6d69e896ce38	5857	*
cparata	0:6d69e896ce38	5858	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5859	* @param val change the values of rst_counter_bdr in
cparata	0:6d69e896ce38	5860	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5861	*
cparata	0:6d69e896ce38	5862	*/
cparata	0:6d69e896ce38	5863	int32_t lsm6dso_rst_batch_counter_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	5864	{
cparata	0:6d69e896ce38	5865	lsm6dso_counter_bdr_reg1_t reg;
cparata	0:6d69e896ce38	5866	int32_t ret;
cparata	0:6d69e896ce38	5867
cparata	0:6d69e896ce38	5868	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5869	if (ret == 0) {
cparata	0:6d69e896ce38	5870	reg.rst_counter_bdr = val;
cparata	0:6d69e896ce38	5871	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5872	}
cparata	0:6d69e896ce38	5873	return ret;
cparata	0:6d69e896ce38	5874	}
cparata	0:6d69e896ce38	5875
cparata	0:6d69e896ce38	5876	/**
cparata	0:6d69e896ce38	5877	* @brief Resets the internal counter of batching events for a single sensor.
cparata	0:6d69e896ce38	5878	* This bit is automatically reset to zero if it was set to ‘1’.[get]
cparata	0:6d69e896ce38	5879	*
cparata	0:6d69e896ce38	5880	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5881	* @param val change the values of rst_counter_bdr in
cparata	0:6d69e896ce38	5882	* reg COUNTER_BDR_REG1
cparata	0:6d69e896ce38	5883	*
cparata	0:6d69e896ce38	5884	*/
cparata	0:6d69e896ce38	5885	int32_t lsm6dso_rst_batch_counter_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5886	{
cparata	0:6d69e896ce38	5887	lsm6dso_counter_bdr_reg1_t reg;
cparata	0:6d69e896ce38	5888	int32_t ret;
cparata	0:6d69e896ce38	5889
cparata	0:6d69e896ce38	5890	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	5891	*val = reg.rst_counter_bdr;
cparata	0:6d69e896ce38	5892
cparata	0:6d69e896ce38	5893	return ret;
cparata	0:6d69e896ce38	5894	}
cparata	0:6d69e896ce38	5895
cparata	0:6d69e896ce38	5896	/**
cparata	0:6d69e896ce38	5897	* @brief Batch data rate counter.[set]
cparata	0:6d69e896ce38	5898	*
cparata	0:6d69e896ce38	5899	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5900	* @param val change the values of cnt_bdr_th in
cparata	0:6d69e896ce38	5901	* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata	0:6d69e896ce38	5902	*
cparata	0:6d69e896ce38	5903	*/
cparata	0:6d69e896ce38	5904	int32_t lsm6dso_batch_counter_threshold_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	0:6d69e896ce38	5905	{
cparata	0:6d69e896ce38	5906	lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
cparata	0:6d69e896ce38	5907	lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
cparata	0:6d69e896ce38	5908	int32_t ret;
cparata	0:6d69e896ce38	5909
cparata	0:6d69e896ce38	5910	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
cparata	0:6d69e896ce38	5911	(uint8_t*)&counter_bdr_reg1, 1);
cparata	0:6d69e896ce38	5912	if (ret == 0) {
cparata	0:6d69e896ce38	5913	counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
cparata	0:6d69e896ce38	5914	counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
cparata	0:6d69e896ce38	5915	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
cparata	0:6d69e896ce38	5916	(uint8_t*)&counter_bdr_reg1, 1);
cparata	0:6d69e896ce38	5917	}
cparata	0:6d69e896ce38	5918	if (ret == 0) {
cparata	0:6d69e896ce38	5919	ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
cparata	0:6d69e896ce38	5920	(uint8_t*)&counter_bdr_reg2, 1);
cparata	0:6d69e896ce38	5921	}
cparata	0:6d69e896ce38	5922	return ret;
cparata	0:6d69e896ce38	5923	}
cparata	0:6d69e896ce38	5924
cparata	0:6d69e896ce38	5925	/**
cparata	0:6d69e896ce38	5926	* @brief Batch data rate counter.[get]
cparata	0:6d69e896ce38	5927	*
cparata	0:6d69e896ce38	5928	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5929	* @param val change the values of cnt_bdr_th in
cparata	0:6d69e896ce38	5930	* reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
cparata	0:6d69e896ce38	5931	*
cparata	0:6d69e896ce38	5932	*/
cparata	0:6d69e896ce38	5933	int32_t lsm6dso_batch_counter_threshold_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	0:6d69e896ce38	5934	{
cparata	0:6d69e896ce38	5935	lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
cparata	0:6d69e896ce38	5936	lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
cparata	0:6d69e896ce38	5937	int32_t ret;
cparata	0:6d69e896ce38	5938
cparata	0:6d69e896ce38	5939	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
cparata	0:6d69e896ce38	5940	(uint8_t*)&counter_bdr_reg1, 1);
cparata	0:6d69e896ce38	5941	if (ret == 0) {
cparata	0:6d69e896ce38	5942	ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
cparata	0:6d69e896ce38	5943	(uint8_t*)&counter_bdr_reg2, 1);
cparata	0:6d69e896ce38	5944
cparata	0:6d69e896ce38	5945	*val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
cparata	0:6d69e896ce38	5946	+ (uint16_t)counter_bdr_reg2.cnt_bdr_th;
cparata	0:6d69e896ce38	5947	}
cparata	0:6d69e896ce38	5948
cparata	0:6d69e896ce38	5949	return ret;
cparata	0:6d69e896ce38	5950	}
cparata	0:6d69e896ce38	5951
cparata	0:6d69e896ce38	5952	/**
cparata	0:6d69e896ce38	5953	* @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
cparata	0:6d69e896ce38	5954	*
cparata	0:6d69e896ce38	5955	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5956	* @param val change the values of diff_fifo in reg FIFO_STATUS1
cparata	0:6d69e896ce38	5957	*
cparata	0:6d69e896ce38	5958	*/
cparata	0:6d69e896ce38	5959	int32_t lsm6dso_fifo_data_level_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	0:6d69e896ce38	5960	{
cparata	0:6d69e896ce38	5961	lsm6dso_fifo_status1_t fifo_status1;
cparata	0:6d69e896ce38	5962	lsm6dso_fifo_status2_t fifo_status2;
cparata	0:6d69e896ce38	5963	int32_t ret;
cparata	0:6d69e896ce38	5964
cparata	0:6d69e896ce38	5965	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1,
cparata	0:6d69e896ce38	5966	(uint8_t*)&fifo_status1, 1);
cparata	0:6d69e896ce38	5967	if (ret == 0) {
cparata	0:6d69e896ce38	5968	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2,
cparata	0:6d69e896ce38	5969	(uint8_t*)&fifo_status2, 1);
cparata	0:6d69e896ce38	5970	*val = ((uint16_t)fifo_status2.diff_fifo << 8) +
cparata	0:6d69e896ce38	5971	(uint16_t)fifo_status1.diff_fifo;
cparata	0:6d69e896ce38	5972	}
cparata	0:6d69e896ce38	5973	return ret;
cparata	0:6d69e896ce38	5974	}
cparata	0:6d69e896ce38	5975
cparata	0:6d69e896ce38	5976	/**
cparata	0:6d69e896ce38	5977	* @brief FIFO status.[get]
cparata	0:6d69e896ce38	5978	*
cparata	0:6d69e896ce38	5979	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5980	* @param val registers FIFO_STATUS2
cparata	0:6d69e896ce38	5981	*
cparata	0:6d69e896ce38	5982	*/
cparata	0:6d69e896ce38	5983	int32_t lsm6dso_fifo_status_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	5984	lsm6dso_fifo_status2_t *val)
cparata	0:6d69e896ce38	5985	{
cparata	0:6d69e896ce38	5986	int32_t ret;
cparata	0:6d69e896ce38	5987	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*) val, 1);
cparata	0:6d69e896ce38	5988	return ret;
cparata	0:6d69e896ce38	5989	}
cparata	0:6d69e896ce38	5990
cparata	0:6d69e896ce38	5991	/**
cparata	0:6d69e896ce38	5992	* @brief Smart FIFO full status.[get]
cparata	0:6d69e896ce38	5993	*
cparata	0:6d69e896ce38	5994	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	5995	* @param val change the values of fifo_full_ia in reg FIFO_STATUS2
cparata	0:6d69e896ce38	5996	*
cparata	0:6d69e896ce38	5997	*/
cparata	0:6d69e896ce38	5998	int32_t lsm6dso_fifo_full_flag_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	5999	{
cparata	0:6d69e896ce38	6000	lsm6dso_fifo_status2_t reg;
cparata	0:6d69e896ce38	6001	int32_t ret;
cparata	0:6d69e896ce38	6002
cparata	0:6d69e896ce38	6003	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6004	*val = reg.fifo_full_ia;
cparata	0:6d69e896ce38	6005
cparata	0:6d69e896ce38	6006	return ret;
cparata	0:6d69e896ce38	6007	}
cparata	0:6d69e896ce38	6008
cparata	0:6d69e896ce38	6009	/**
cparata	0:6d69e896ce38	6010	* @brief FIFO overrun status.[get]
cparata	0:6d69e896ce38	6011	*
cparata	0:6d69e896ce38	6012	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6013	* @param val change the values of fifo_over_run_latched in
cparata	0:6d69e896ce38	6014	* reg FIFO_STATUS2
cparata	0:6d69e896ce38	6015	*
cparata	0:6d69e896ce38	6016	*/
cparata	0:6d69e896ce38	6017	int32_t lsm6dso_fifo_ovr_flag_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6018	{
cparata	0:6d69e896ce38	6019	lsm6dso_fifo_status2_t reg;
cparata	0:6d69e896ce38	6020	int32_t ret;
cparata	0:6d69e896ce38	6021
cparata	0:6d69e896ce38	6022	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6023	*val = reg.fifo_ovr_ia;
cparata	0:6d69e896ce38	6024
cparata	0:6d69e896ce38	6025	return ret;
cparata	0:6d69e896ce38	6026	}
cparata	0:6d69e896ce38	6027
cparata	0:6d69e896ce38	6028	/**
cparata	0:6d69e896ce38	6029	* @brief FIFO watermark status.[get]
cparata	0:6d69e896ce38	6030	*
cparata	0:6d69e896ce38	6031	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6032	* @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
cparata	0:6d69e896ce38	6033	*
cparata	0:6d69e896ce38	6034	*/
cparata	0:6d69e896ce38	6035	int32_t lsm6dso_fifo_wtm_flag_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6036	{
cparata	0:6d69e896ce38	6037	lsm6dso_fifo_status2_t reg;
cparata	0:6d69e896ce38	6038	int32_t ret;
cparata	0:6d69e896ce38	6039
cparata	0:6d69e896ce38	6040	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6041	*val = reg.fifo_wtm_ia;
cparata	0:6d69e896ce38	6042
cparata	0:6d69e896ce38	6043	return ret;
cparata	0:6d69e896ce38	6044	}
cparata	0:6d69e896ce38	6045
cparata	0:6d69e896ce38	6046	/**
cparata	0:6d69e896ce38	6047	* @brief Identifies the sensor in FIFO_DATA_OUT.[get]
cparata	0:6d69e896ce38	6048	*
cparata	0:6d69e896ce38	6049	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6050	* @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
cparata	0:6d69e896ce38	6051	*
cparata	0:6d69e896ce38	6052	*/
cparata	0:6d69e896ce38	6053	int32_t lsm6dso_fifo_sensor_tag_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	6054	lsm6dso_fifo_tag_t *val)
cparata	0:6d69e896ce38	6055	{
cparata	0:6d69e896ce38	6056	lsm6dso_fifo_data_out_tag_t reg;
cparata	0:6d69e896ce38	6057	int32_t ret;
cparata	0:6d69e896ce38	6058
cparata	0:6d69e896ce38	6059	ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6060	switch (reg.tag_sensor) {
cparata	0:6d69e896ce38	6061	case LSM6DSO_GYRO_NC_TAG:
cparata	0:6d69e896ce38	6062	*val = LSM6DSO_GYRO_NC_TAG;
cparata	0:6d69e896ce38	6063	break;
cparata	0:6d69e896ce38	6064	case LSM6DSO_XL_NC_TAG:
cparata	0:6d69e896ce38	6065	*val = LSM6DSO_XL_NC_TAG;
cparata	0:6d69e896ce38	6066	break;
cparata	0:6d69e896ce38	6067	case LSM6DSO_TEMPERATURE_TAG:
cparata	0:6d69e896ce38	6068	*val = LSM6DSO_TEMPERATURE_TAG;
cparata	0:6d69e896ce38	6069	break;
cparata	0:6d69e896ce38	6070	case LSM6DSO_CFG_CHANGE_TAG:
cparata	0:6d69e896ce38	6071	*val = LSM6DSO_CFG_CHANGE_TAG;
cparata	0:6d69e896ce38	6072	break;
cparata	0:6d69e896ce38	6073	case LSM6DSO_XL_NC_T_2_TAG:
cparata	0:6d69e896ce38	6074	*val = LSM6DSO_XL_NC_T_2_TAG;
cparata	0:6d69e896ce38	6075	break;
cparata	0:6d69e896ce38	6076	case LSM6DSO_XL_NC_T_1_TAG:
cparata	0:6d69e896ce38	6077	*val = LSM6DSO_XL_NC_T_1_TAG;
cparata	0:6d69e896ce38	6078	break;
cparata	0:6d69e896ce38	6079	case LSM6DSO_XL_2XC_TAG:
cparata	0:6d69e896ce38	6080	*val = LSM6DSO_XL_2XC_TAG;
cparata	0:6d69e896ce38	6081	break;
cparata	0:6d69e896ce38	6082	case LSM6DSO_XL_3XC_TAG:
cparata	0:6d69e896ce38	6083	*val = LSM6DSO_XL_3XC_TAG;
cparata	0:6d69e896ce38	6084	break;
cparata	0:6d69e896ce38	6085	case LSM6DSO_GYRO_NC_T_2_TAG:
cparata	0:6d69e896ce38	6086	*val = LSM6DSO_GYRO_NC_T_2_TAG;
cparata	0:6d69e896ce38	6087	break;
cparata	0:6d69e896ce38	6088	case LSM6DSO_GYRO_NC_T_1_TAG:
cparata	0:6d69e896ce38	6089	*val = LSM6DSO_GYRO_NC_T_1_TAG;
cparata	0:6d69e896ce38	6090	break;
cparata	0:6d69e896ce38	6091	case LSM6DSO_GYRO_2XC_TAG:
cparata	0:6d69e896ce38	6092	*val = LSM6DSO_GYRO_2XC_TAG;
cparata	0:6d69e896ce38	6093	break;
cparata	0:6d69e896ce38	6094	case LSM6DSO_GYRO_3XC_TAG:
cparata	0:6d69e896ce38	6095	*val = LSM6DSO_GYRO_3XC_TAG;
cparata	0:6d69e896ce38	6096	break;
cparata	0:6d69e896ce38	6097	case LSM6DSO_SENSORHUB_SLAVE0_TAG:
cparata	0:6d69e896ce38	6098	*val = LSM6DSO_SENSORHUB_SLAVE0_TAG;
cparata	0:6d69e896ce38	6099	break;
cparata	0:6d69e896ce38	6100	case LSM6DSO_SENSORHUB_SLAVE1_TAG:
cparata	0:6d69e896ce38	6101	*val = LSM6DSO_SENSORHUB_SLAVE1_TAG;
cparata	0:6d69e896ce38	6102	break;
cparata	0:6d69e896ce38	6103	case LSM6DSO_SENSORHUB_SLAVE2_TAG:
cparata	0:6d69e896ce38	6104	*val = LSM6DSO_SENSORHUB_SLAVE2_TAG;
cparata	0:6d69e896ce38	6105	break;
cparata	0:6d69e896ce38	6106	case LSM6DSO_SENSORHUB_SLAVE3_TAG:
cparata	0:6d69e896ce38	6107	*val = LSM6DSO_SENSORHUB_SLAVE3_TAG;
cparata	0:6d69e896ce38	6108	break;
cparata	0:6d69e896ce38	6109	case LSM6DSO_STEP_CPUNTER_TAG:
cparata	0:6d69e896ce38	6110	*val = LSM6DSO_STEP_CPUNTER_TAG;
cparata	0:6d69e896ce38	6111	break;
cparata	0:6d69e896ce38	6112	case LSM6DSO_GAME_ROTATION_TAG:
cparata	0:6d69e896ce38	6113	*val = LSM6DSO_GAME_ROTATION_TAG;
cparata	0:6d69e896ce38	6114	break;
cparata	0:6d69e896ce38	6115	case LSM6DSO_GEOMAG_ROTATION_TAG:
cparata	0:6d69e896ce38	6116	*val = LSM6DSO_GEOMAG_ROTATION_TAG;
cparata	0:6d69e896ce38	6117	break;
cparata	0:6d69e896ce38	6118	case LSM6DSO_ROTATION_TAG:
cparata	0:6d69e896ce38	6119	*val = LSM6DSO_ROTATION_TAG;
cparata	0:6d69e896ce38	6120	break;
cparata	0:6d69e896ce38	6121	case LSM6DSO_SENSORHUB_NACK_TAG:
cparata	0:6d69e896ce38	6122	*val = LSM6DSO_SENSORHUB_NACK_TAG;
cparata	0:6d69e896ce38	6123	break;
cparata	0:6d69e896ce38	6124	default:
cparata	0:6d69e896ce38	6125	*val = LSM6DSO_GYRO_NC_TAG;
cparata	0:6d69e896ce38	6126	break;
cparata	0:6d69e896ce38	6127	}
cparata	0:6d69e896ce38	6128	return ret;
cparata	0:6d69e896ce38	6129	}
cparata	0:6d69e896ce38	6130
cparata	0:6d69e896ce38	6131	/**
cparata	0:6d69e896ce38	6132	* @brief : Enable FIFO batching of pedometer embedded
cparata	0:6d69e896ce38	6133	* function values.[set]
cparata	0:6d69e896ce38	6134	*
cparata	0:6d69e896ce38	6135	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6136	* @param val change the values of gbias_fifo_en in
cparata	0:6d69e896ce38	6137	* reg LSM6DSO_EMB_FUNC_FIFO_CFG
cparata	0:6d69e896ce38	6138	*
cparata	0:6d69e896ce38	6139	*/
cparata	0:6d69e896ce38	6140	int32_t lsm6dso_fifo_pedo_batch_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6141	{
cparata	0:6d69e896ce38	6142	lsm6dso_emb_func_fifo_cfg_t reg;
cparata	0:6d69e896ce38	6143	int32_t ret;
cparata	0:6d69e896ce38	6144
cparata	0:6d69e896ce38	6145	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	6146	if (ret == 0) {
cparata	0:6d69e896ce38	6147	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6148	}
cparata	0:6d69e896ce38	6149	if (ret == 0) {
cparata	0:6d69e896ce38	6150	reg.pedo_fifo_en = val;
cparata	0:6d69e896ce38	6151	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
cparata	0:6d69e896ce38	6152	(uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6153	}
cparata	0:6d69e896ce38	6154	if (ret == 0) {
cparata	0:6d69e896ce38	6155	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6156	}
cparata	0:6d69e896ce38	6157	return ret;
cparata	0:6d69e896ce38	6158	}
cparata	0:6d69e896ce38	6159
cparata	0:6d69e896ce38	6160	/**
cparata	0:6d69e896ce38	6161	* @brief Enable FIFO batching of pedometer embedded function values.[get]
cparata	0:6d69e896ce38	6162	*
cparata	0:6d69e896ce38	6163	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6164	* @param val change the values of pedo_fifo_en in
cparata	0:6d69e896ce38	6165	* reg LSM6DSO_EMB_FUNC_FIFO_CFG
cparata	0:6d69e896ce38	6166	*
cparata	0:6d69e896ce38	6167	*/
cparata	0:6d69e896ce38	6168	int32_t lsm6dso_fifo_pedo_batch_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6169	{
cparata	0:6d69e896ce38	6170	lsm6dso_emb_func_fifo_cfg_t reg;
cparata	0:6d69e896ce38	6171	int32_t ret;
cparata	0:6d69e896ce38	6172
cparata	0:6d69e896ce38	6173	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	6174	if (ret == 0) {
cparata	0:6d69e896ce38	6175	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6176	}
cparata	0:6d69e896ce38	6177	if (ret == 0) {
cparata	0:6d69e896ce38	6178	*val = reg.pedo_fifo_en;
cparata	0:6d69e896ce38	6179	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6180	}
cparata	0:6d69e896ce38	6181	return ret;
cparata	0:6d69e896ce38	6182	}
cparata	0:6d69e896ce38	6183
cparata	0:6d69e896ce38	6184	/**
cparata	0:6d69e896ce38	6185	* @brief Enable FIFO batching data of first slave.[set]
cparata	0:6d69e896ce38	6186	*
cparata	0:6d69e896ce38	6187	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6188	* @param val change the values of batch_ext_sens_0_en in
cparata	0:6d69e896ce38	6189	* reg SLV0_CONFIG
cparata	0:6d69e896ce38	6190	*
cparata	0:6d69e896ce38	6191	*/
cparata	0:6d69e896ce38	6192	int32_t lsm6dso_sh_batch_slave_0_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6193	{
cparata	0:6d69e896ce38	6194	lsm6dso_slv0_config_t reg;
cparata	0:6d69e896ce38	6195	int32_t ret;
cparata	0:6d69e896ce38	6196
cparata	0:6d69e896ce38	6197	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	6198	if (ret == 0) {
cparata	0:6d69e896ce38	6199	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6200	}
cparata	0:6d69e896ce38	6201	if (ret == 0) {
cparata	0:6d69e896ce38	6202	reg.batch_ext_sens_0_en = val;
cparata	0:6d69e896ce38	6203	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6204	}
cparata	0:6d69e896ce38	6205	if (ret == 0) {
cparata	0:6d69e896ce38	6206	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6207	}
cparata	0:6d69e896ce38	6208	return ret;
cparata	0:6d69e896ce38	6209	}
cparata	0:6d69e896ce38	6210
cparata	0:6d69e896ce38	6211	/**
cparata	0:6d69e896ce38	6212	* @brief Enable FIFO batching data of first slave.[get]
cparata	0:6d69e896ce38	6213	*
cparata	0:6d69e896ce38	6214	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6215	* @param val change the values of batch_ext_sens_0_en in
cparata	0:6d69e896ce38	6216	* reg SLV0_CONFIG
cparata	0:6d69e896ce38	6217	*
cparata	0:6d69e896ce38	6218	*/
cparata	0:6d69e896ce38	6219	int32_t lsm6dso_sh_batch_slave_0_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6220	{
cparata	0:6d69e896ce38	6221	lsm6dso_slv0_config_t reg;
cparata	0:6d69e896ce38	6222	int32_t ret;
cparata	0:6d69e896ce38	6223
cparata	0:6d69e896ce38	6224	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	6225	if (ret == 0) {
cparata	0:6d69e896ce38	6226	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6227	}
cparata	0:6d69e896ce38	6228	if (ret == 0) {
cparata	0:6d69e896ce38	6229	*val = reg.batch_ext_sens_0_en;
cparata	0:6d69e896ce38	6230	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6231	}
cparata	0:6d69e896ce38	6232	return ret;
cparata	0:6d69e896ce38	6233	}
cparata	0:6d69e896ce38	6234
cparata	0:6d69e896ce38	6235	/**
cparata	0:6d69e896ce38	6236	* @brief Enable FIFO batching data of second slave.[set]
cparata	0:6d69e896ce38	6237	*
cparata	0:6d69e896ce38	6238	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6239	* @param val change the values of batch_ext_sens_1_en in
cparata	0:6d69e896ce38	6240	* reg SLV1_CONFIG
cparata	0:6d69e896ce38	6241	*
cparata	0:6d69e896ce38	6242	*/
cparata	0:6d69e896ce38	6243	int32_t lsm6dso_sh_batch_slave_1_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6244	{
cparata	0:6d69e896ce38	6245	lsm6dso_slv1_config_t reg;
cparata	0:6d69e896ce38	6246	int32_t ret;
cparata	0:6d69e896ce38	6247
cparata	0:6d69e896ce38	6248	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	6249	if (ret == 0) {
cparata	0:6d69e896ce38	6250	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6251	}
cparata	0:6d69e896ce38	6252	if (ret == 0) {
cparata	0:6d69e896ce38	6253	reg.batch_ext_sens_1_en = val;
cparata	0:6d69e896ce38	6254	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6255	}
cparata	0:6d69e896ce38	6256	if (ret == 0) {
cparata	0:6d69e896ce38	6257	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6258	}
cparata	0:6d69e896ce38	6259
cparata	0:6d69e896ce38	6260	return ret;
cparata	0:6d69e896ce38	6261	}
cparata	0:6d69e896ce38	6262
cparata	0:6d69e896ce38	6263	/**
cparata	0:6d69e896ce38	6264	* @brief Enable FIFO batching data of second slave.[get]
cparata	0:6d69e896ce38	6265	*
cparata	0:6d69e896ce38	6266	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6267	* @param val change the values of batch_ext_sens_1_en in
cparata	0:6d69e896ce38	6268	* reg SLV1_CONFIG
cparata	0:6d69e896ce38	6269	*
cparata	0:6d69e896ce38	6270	*/
cparata	0:6d69e896ce38	6271	int32_t lsm6dso_sh_batch_slave_1_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6272	{
cparata	0:6d69e896ce38	6273	lsm6dso_slv1_config_t reg;
cparata	0:6d69e896ce38	6274	int32_t ret;
cparata	0:6d69e896ce38	6275
cparata	0:6d69e896ce38	6276	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	6277	if (ret == 0) {
cparata	0:6d69e896ce38	6278	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6279	*val = reg.batch_ext_sens_1_en;
cparata	0:6d69e896ce38	6280	}
cparata	0:6d69e896ce38	6281	if (ret == 0) {
cparata	0:6d69e896ce38	6282	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6283	}
cparata	0:6d69e896ce38	6284	return ret;
cparata	0:6d69e896ce38	6285	}
cparata	0:6d69e896ce38	6286
cparata	0:6d69e896ce38	6287	/**
cparata	0:6d69e896ce38	6288	* @brief Enable FIFO batching data of third slave.[set]
cparata	0:6d69e896ce38	6289	*
cparata	0:6d69e896ce38	6290	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6291	* @param val change the values of batch_ext_sens_2_en in
cparata	0:6d69e896ce38	6292	* reg SLV2_CONFIG
cparata	0:6d69e896ce38	6293	*
cparata	0:6d69e896ce38	6294	*/
cparata	0:6d69e896ce38	6295	int32_t lsm6dso_sh_batch_slave_2_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6296	{
cparata	0:6d69e896ce38	6297	lsm6dso_slv2_config_t reg;
cparata	0:6d69e896ce38	6298	int32_t ret;
cparata	0:6d69e896ce38	6299
cparata	0:6d69e896ce38	6300	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	6301
cparata	0:6d69e896ce38	6302	if (ret == 0) {
cparata	0:6d69e896ce38	6303	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6304	}
cparata	0:6d69e896ce38	6305	if (ret == 0) {
cparata	0:6d69e896ce38	6306	reg.batch_ext_sens_2_en = val;
cparata	0:6d69e896ce38	6307	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6308	}
cparata	0:6d69e896ce38	6309	if (ret == 0) {
cparata	0:6d69e896ce38	6310	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6311	}
cparata	0:6d69e896ce38	6312	return ret;
cparata	0:6d69e896ce38	6313	}
cparata	0:6d69e896ce38	6314
cparata	0:6d69e896ce38	6315	/**
cparata	0:6d69e896ce38	6316	* @brief Enable FIFO batching data of third slave.[get]
cparata	0:6d69e896ce38	6317	*
cparata	0:6d69e896ce38	6318	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6319	* @param val change the values of batch_ext_sens_2_en in
cparata	0:6d69e896ce38	6320	* reg SLV2_CONFIG
cparata	0:6d69e896ce38	6321	*
cparata	0:6d69e896ce38	6322	*/
cparata	0:6d69e896ce38	6323	int32_t lsm6dso_sh_batch_slave_2_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6324	{
cparata	0:6d69e896ce38	6325	lsm6dso_slv2_config_t reg;
cparata	0:6d69e896ce38	6326	int32_t ret;
cparata	0:6d69e896ce38	6327
cparata	0:6d69e896ce38	6328	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	6329	if (ret == 0) {
cparata	0:6d69e896ce38	6330	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6331	}
cparata	0:6d69e896ce38	6332	if (ret == 0) {
cparata	0:6d69e896ce38	6333	*val = reg.batch_ext_sens_2_en;
cparata	0:6d69e896ce38	6334	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6335	}
cparata	0:6d69e896ce38	6336
cparata	0:6d69e896ce38	6337	return ret;
cparata	0:6d69e896ce38	6338	}
cparata	0:6d69e896ce38	6339
cparata	0:6d69e896ce38	6340	/**
cparata	0:6d69e896ce38	6341	* @brief Enable FIFO batching data of fourth slave.[set]
cparata	0:6d69e896ce38	6342	*
cparata	0:6d69e896ce38	6343	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6344	* @param val change the values of batch_ext_sens_3_en
cparata	0:6d69e896ce38	6345	* in reg SLV3_CONFIG
cparata	0:6d69e896ce38	6346	*
cparata	0:6d69e896ce38	6347	*/
cparata	0:6d69e896ce38	6348	int32_t lsm6dso_sh_batch_slave_3_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6349	{
cparata	0:6d69e896ce38	6350	lsm6dso_slv3_config_t reg;
cparata	0:6d69e896ce38	6351	int32_t ret;
cparata	0:6d69e896ce38	6352
cparata	0:6d69e896ce38	6353	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	6354	if (ret == 0) {
cparata	0:6d69e896ce38	6355	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6356	}
cparata	0:6d69e896ce38	6357	if (ret == 0) {
cparata	0:6d69e896ce38	6358	reg.batch_ext_sens_3_en = val;
cparata	0:6d69e896ce38	6359	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6360	}
cparata	0:6d69e896ce38	6361	if (ret == 0) {
cparata	0:6d69e896ce38	6362	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6363	}
cparata	0:6d69e896ce38	6364
cparata	0:6d69e896ce38	6365	return ret;
cparata	0:6d69e896ce38	6366	}
cparata	0:6d69e896ce38	6367
cparata	0:6d69e896ce38	6368	/**
cparata	0:6d69e896ce38	6369	* @brief Enable FIFO batching data of fourth slave.[get]
cparata	0:6d69e896ce38	6370	*
cparata	0:6d69e896ce38	6371	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6372	* @param val change the values of batch_ext_sens_3_en in
cparata	0:6d69e896ce38	6373	* reg SLV3_CONFIG
cparata	0:6d69e896ce38	6374	*
cparata	0:6d69e896ce38	6375	*/
cparata	0:6d69e896ce38	6376	int32_t lsm6dso_sh_batch_slave_3_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6377	{
cparata	0:6d69e896ce38	6378	lsm6dso_slv3_config_t reg;
cparata	0:6d69e896ce38	6379	int32_t ret;
cparata	0:6d69e896ce38	6380
cparata	0:6d69e896ce38	6381	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	6382	if (ret == 0) {
cparata	0:6d69e896ce38	6383	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6384	}
cparata	0:6d69e896ce38	6385	if (ret == 0) {
cparata	0:6d69e896ce38	6386	*val = reg.batch_ext_sens_3_en;
cparata	0:6d69e896ce38	6387	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6388	}
cparata	0:6d69e896ce38	6389
cparata	0:6d69e896ce38	6390	return ret;
cparata	0:6d69e896ce38	6391	}
cparata	0:6d69e896ce38	6392
cparata	0:6d69e896ce38	6393	/**
cparata	0:6d69e896ce38	6394	* @}
cparata	0:6d69e896ce38	6395	*
cparata	0:6d69e896ce38	6396	*/
cparata	0:6d69e896ce38	6397
cparata	0:6d69e896ce38	6398	/**
cparata	0:6d69e896ce38	6399	* @defgroup LSM6DSO_DEN_functionality
cparata	0:6d69e896ce38	6400	* @brief This section groups all the functions concerning
cparata	0:6d69e896ce38	6401	* DEN functionality.
cparata	0:6d69e896ce38	6402	* @{
cparata	0:6d69e896ce38	6403	*
cparata	0:6d69e896ce38	6404	*/
cparata	0:6d69e896ce38	6405
cparata	0:6d69e896ce38	6406	/**
cparata	0:6d69e896ce38	6407	* @brief DEN functionality marking mode.[set]
cparata	0:6d69e896ce38	6408	*
cparata	0:6d69e896ce38	6409	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6410	* @param val change the values of den_mode in reg CTRL6_C
cparata	0:6d69e896ce38	6411	*
cparata	0:6d69e896ce38	6412	*/
cparata	0:6d69e896ce38	6413	int32_t lsm6dso_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_den_mode_t val)
cparata	0:6d69e896ce38	6414	{
cparata	0:6d69e896ce38	6415	lsm6dso_ctrl6_c_t reg;
cparata	0:6d69e896ce38	6416	int32_t ret;
cparata	0:6d69e896ce38	6417
cparata	0:6d69e896ce38	6418	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6419	if (ret == 0) {
cparata	0:6d69e896ce38	6420	reg.den_mode = (uint8_t)val;
cparata	0:6d69e896ce38	6421	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6422	}
cparata	0:6d69e896ce38	6423
cparata	0:6d69e896ce38	6424	return ret;
cparata	0:6d69e896ce38	6425	}
cparata	0:6d69e896ce38	6426
cparata	0:6d69e896ce38	6427	/**
cparata	0:6d69e896ce38	6428	* @brief DEN functionality marking mode.[get]
cparata	0:6d69e896ce38	6429	*
cparata	0:6d69e896ce38	6430	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6431	* @param val Get the values of den_mode in reg CTRL6_C
cparata	0:6d69e896ce38	6432	*
cparata	0:6d69e896ce38	6433	*/
cparata	0:6d69e896ce38	6434	int32_t lsm6dso_den_mode_get(lsm6dso_ctx_t ctx, lsm6dso_den_mode_t val)
cparata	0:6d69e896ce38	6435	{
cparata	0:6d69e896ce38	6436	lsm6dso_ctrl6_c_t reg;
cparata	0:6d69e896ce38	6437	int32_t ret;
cparata	0:6d69e896ce38	6438
cparata	0:6d69e896ce38	6439	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6440
cparata	0:6d69e896ce38	6441	switch (reg.den_mode) {
cparata	0:6d69e896ce38	6442	case LSM6DSO_DEN_DISABLE:
cparata	0:6d69e896ce38	6443	*val = LSM6DSO_DEN_DISABLE;
cparata	0:6d69e896ce38	6444	break;
cparata	0:6d69e896ce38	6445	case LSM6DSO_LEVEL_FIFO:
cparata	0:6d69e896ce38	6446	*val = LSM6DSO_LEVEL_FIFO;
cparata	0:6d69e896ce38	6447	break;
cparata	0:6d69e896ce38	6448	case LSM6DSO_LEVEL_LETCHED:
cparata	0:6d69e896ce38	6449	*val = LSM6DSO_LEVEL_LETCHED;
cparata	0:6d69e896ce38	6450	break;
cparata	0:6d69e896ce38	6451	case LSM6DSO_LEVEL_TRIGGER:
cparata	0:6d69e896ce38	6452	*val = LSM6DSO_LEVEL_TRIGGER;
cparata	0:6d69e896ce38	6453	break;
cparata	0:6d69e896ce38	6454	case LSM6DSO_EDGE_TRIGGER:
cparata	0:6d69e896ce38	6455	*val = LSM6DSO_EDGE_TRIGGER;
cparata	0:6d69e896ce38	6456	break;
cparata	0:6d69e896ce38	6457	default:
cparata	0:6d69e896ce38	6458	*val = LSM6DSO_DEN_DISABLE;
cparata	0:6d69e896ce38	6459	break;
cparata	0:6d69e896ce38	6460	}
cparata	0:6d69e896ce38	6461	return ret;
cparata	0:6d69e896ce38	6462	}
cparata	0:6d69e896ce38	6463
cparata	0:6d69e896ce38	6464	/**
cparata	0:6d69e896ce38	6465	* @brief DEN active level configuration.[set]
cparata	0:6d69e896ce38	6466	*
cparata	0:6d69e896ce38	6467	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6468	* @param val change the values of den_lh in reg CTRL9_XL
cparata	0:6d69e896ce38	6469	*
cparata	0:6d69e896ce38	6470	*/
cparata	0:6d69e896ce38	6471	int32_t lsm6dso_den_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_den_lh_t val)
cparata	0:6d69e896ce38	6472	{
cparata	0:6d69e896ce38	6473	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6474	int32_t ret;
cparata	0:6d69e896ce38	6475
cparata	0:6d69e896ce38	6476	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6477	if (ret == 0) {
cparata	0:6d69e896ce38	6478	reg.den_lh = (uint8_t)val;
cparata	0:6d69e896ce38	6479	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6480	}
cparata	0:6d69e896ce38	6481
cparata	0:6d69e896ce38	6482	return ret;
cparata	0:6d69e896ce38	6483	}
cparata	0:6d69e896ce38	6484
cparata	0:6d69e896ce38	6485	/**
cparata	0:6d69e896ce38	6486	* @brief DEN active level configuration.[get]
cparata	0:6d69e896ce38	6487	*
cparata	0:6d69e896ce38	6488	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6489	* @param val Get the values of den_lh in reg CTRL9_XL
cparata	0:6d69e896ce38	6490	*
cparata	0:6d69e896ce38	6491	*/
cparata	0:6d69e896ce38	6492	int32_t lsm6dso_den_polarity_get(lsm6dso_ctx_t ctx, lsm6dso_den_lh_t val)
cparata	0:6d69e896ce38	6493	{
cparata	0:6d69e896ce38	6494	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6495	int32_t ret;
cparata	0:6d69e896ce38	6496
cparata	0:6d69e896ce38	6497	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6498
cparata	0:6d69e896ce38	6499	switch (reg.den_lh) {
cparata	0:6d69e896ce38	6500	case LSM6DSO_DEN_ACT_LOW:
cparata	0:6d69e896ce38	6501	*val = LSM6DSO_DEN_ACT_LOW;
cparata	0:6d69e896ce38	6502	break;
cparata	0:6d69e896ce38	6503	case LSM6DSO_DEN_ACT_HIGH:
cparata	0:6d69e896ce38	6504	*val = LSM6DSO_DEN_ACT_HIGH;
cparata	0:6d69e896ce38	6505	break;
cparata	0:6d69e896ce38	6506	default:
cparata	0:6d69e896ce38	6507	*val = LSM6DSO_DEN_ACT_LOW;
cparata	0:6d69e896ce38	6508	break;
cparata	0:6d69e896ce38	6509	}
cparata	0:6d69e896ce38	6510	return ret;
cparata	0:6d69e896ce38	6511	}
cparata	0:6d69e896ce38	6512
cparata	0:6d69e896ce38	6513	/**
cparata	0:6d69e896ce38	6514	* @brief DEN enable.[set]
cparata	0:6d69e896ce38	6515	*
cparata	0:6d69e896ce38	6516	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6517	* @param val change the values of den_xl_g in reg CTRL9_XL
cparata	0:6d69e896ce38	6518	*
cparata	0:6d69e896ce38	6519	*/
cparata	0:6d69e896ce38	6520	int32_t lsm6dso_den_enable_set(lsm6dso_ctx_t *ctx, lsm6dso_den_xl_g_t val)
cparata	0:6d69e896ce38	6521	{
cparata	0:6d69e896ce38	6522	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6523	int32_t ret;
cparata	0:6d69e896ce38	6524
cparata	0:6d69e896ce38	6525	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6526	if (ret == 0) {
cparata	0:6d69e896ce38	6527	reg.den_xl_g = (uint8_t)val;
cparata	0:6d69e896ce38	6528	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6529	}
cparata	0:6d69e896ce38	6530
cparata	0:6d69e896ce38	6531	return ret;
cparata	0:6d69e896ce38	6532	}
cparata	0:6d69e896ce38	6533
cparata	0:6d69e896ce38	6534	/**
cparata	0:6d69e896ce38	6535	* @brief DEN enable.[get]
cparata	0:6d69e896ce38	6536	*
cparata	0:6d69e896ce38	6537	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6538	* @param val Get the values of den_xl_g in reg CTRL9_XL
cparata	0:6d69e896ce38	6539	*
cparata	0:6d69e896ce38	6540	*/
cparata	0:6d69e896ce38	6541	int32_t lsm6dso_den_enable_get(lsm6dso_ctx_t ctx, lsm6dso_den_xl_g_t val)
cparata	0:6d69e896ce38	6542	{
cparata	0:6d69e896ce38	6543	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6544	int32_t ret;
cparata	0:6d69e896ce38	6545
cparata	0:6d69e896ce38	6546	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6547
cparata	0:6d69e896ce38	6548	switch (reg.den_xl_g) {
cparata	0:6d69e896ce38	6549	case LSM6DSO_STAMP_IN_GY_DATA:
cparata	0:6d69e896ce38	6550	*val = LSM6DSO_STAMP_IN_GY_DATA;
cparata	0:6d69e896ce38	6551	break;
cparata	0:6d69e896ce38	6552	case LSM6DSO_STAMP_IN_XL_DATA:
cparata	0:6d69e896ce38	6553	*val = LSM6DSO_STAMP_IN_XL_DATA;
cparata	0:6d69e896ce38	6554	break;
cparata	0:6d69e896ce38	6555	case LSM6DSO_STAMP_IN_GY_XL_DATA:
cparata	0:6d69e896ce38	6556	*val = LSM6DSO_STAMP_IN_GY_XL_DATA;
cparata	0:6d69e896ce38	6557	break;
cparata	0:6d69e896ce38	6558	default:
cparata	0:6d69e896ce38	6559	*val = LSM6DSO_STAMP_IN_GY_DATA;
cparata	0:6d69e896ce38	6560	break;
cparata	0:6d69e896ce38	6561	}
cparata	0:6d69e896ce38	6562	return ret;
cparata	0:6d69e896ce38	6563	}
cparata	0:6d69e896ce38	6564
cparata	0:6d69e896ce38	6565	/**
cparata	0:6d69e896ce38	6566	* @brief DEN value stored in LSB of X-axis.[set]
cparata	0:6d69e896ce38	6567	*
cparata	0:6d69e896ce38	6568	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6569	* @param val change the values of den_z in reg CTRL9_XL
cparata	0:6d69e896ce38	6570	*
cparata	0:6d69e896ce38	6571	*/
cparata	0:6d69e896ce38	6572	int32_t lsm6dso_den_mark_axis_x_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6573	{
cparata	0:6d69e896ce38	6574	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6575	int32_t ret;
cparata	0:6d69e896ce38	6576
cparata	0:6d69e896ce38	6577	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6578	if (ret == 0) {
cparata	0:6d69e896ce38	6579	reg.den_z = val;
cparata	0:6d69e896ce38	6580	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6581	}
cparata	0:6d69e896ce38	6582
cparata	0:6d69e896ce38	6583	return ret;
cparata	0:6d69e896ce38	6584	}
cparata	0:6d69e896ce38	6585
cparata	0:6d69e896ce38	6586	/**
cparata	0:6d69e896ce38	6587	* @brief DEN value stored in LSB of X-axis.[get]
cparata	0:6d69e896ce38	6588	*
cparata	0:6d69e896ce38	6589	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6590	* @param val change the values of den_z in reg CTRL9_XL
cparata	0:6d69e896ce38	6591	*
cparata	0:6d69e896ce38	6592	*/
cparata	0:6d69e896ce38	6593	int32_t lsm6dso_den_mark_axis_x_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6594	{
cparata	0:6d69e896ce38	6595	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6596	int32_t ret;
cparata	0:6d69e896ce38	6597
cparata	0:6d69e896ce38	6598	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6599	*val = reg.den_z;
cparata	0:6d69e896ce38	6600
cparata	0:6d69e896ce38	6601	return ret;
cparata	0:6d69e896ce38	6602	}
cparata	0:6d69e896ce38	6603
cparata	0:6d69e896ce38	6604	/**
cparata	0:6d69e896ce38	6605	* @brief DEN value stored in LSB of Y-axis.[set]
cparata	0:6d69e896ce38	6606	*
cparata	0:6d69e896ce38	6607	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6608	* @param val change the values of den_y in reg CTRL9_XL
cparata	0:6d69e896ce38	6609	*
cparata	0:6d69e896ce38	6610	*/
cparata	0:6d69e896ce38	6611	int32_t lsm6dso_den_mark_axis_y_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6612	{
cparata	0:6d69e896ce38	6613	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6614	int32_t ret;
cparata	0:6d69e896ce38	6615
cparata	0:6d69e896ce38	6616	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6617	if (ret == 0) {
cparata	0:6d69e896ce38	6618	reg.den_y = val;
cparata	0:6d69e896ce38	6619	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6620	}
cparata	0:6d69e896ce38	6621
cparata	0:6d69e896ce38	6622	return ret;
cparata	0:6d69e896ce38	6623	}
cparata	0:6d69e896ce38	6624
cparata	0:6d69e896ce38	6625	/**
cparata	0:6d69e896ce38	6626	* @brief DEN value stored in LSB of Y-axis.[get]
cparata	0:6d69e896ce38	6627	*
cparata	0:6d69e896ce38	6628	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6629	* @param val change the values of den_y in reg CTRL9_XL
cparata	0:6d69e896ce38	6630	*
cparata	0:6d69e896ce38	6631	*/
cparata	0:6d69e896ce38	6632	int32_t lsm6dso_den_mark_axis_y_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6633	{
cparata	0:6d69e896ce38	6634	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6635	int32_t ret;
cparata	0:6d69e896ce38	6636
cparata	0:6d69e896ce38	6637	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6638	*val = reg.den_y;
cparata	0:6d69e896ce38	6639
cparata	0:6d69e896ce38	6640	return ret;
cparata	0:6d69e896ce38	6641	}
cparata	0:6d69e896ce38	6642
cparata	0:6d69e896ce38	6643	/**
cparata	0:6d69e896ce38	6644	* @brief DEN value stored in LSB of Z-axis.[set]
cparata	0:6d69e896ce38	6645	*
cparata	0:6d69e896ce38	6646	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6647	* @param val change the values of den_x in reg CTRL9_XL
cparata	0:6d69e896ce38	6648	*
cparata	0:6d69e896ce38	6649	*/
cparata	0:6d69e896ce38	6650	int32_t lsm6dso_den_mark_axis_z_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6651	{
cparata	0:6d69e896ce38	6652	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6653	int32_t ret;
cparata	0:6d69e896ce38	6654
cparata	0:6d69e896ce38	6655	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6656	if (ret == 0) {
cparata	0:6d69e896ce38	6657	reg.den_x = val;
cparata	0:6d69e896ce38	6658	ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6659	}
cparata	0:6d69e896ce38	6660
cparata	0:6d69e896ce38	6661	return ret;
cparata	0:6d69e896ce38	6662	}
cparata	0:6d69e896ce38	6663
cparata	0:6d69e896ce38	6664	/**
cparata	0:6d69e896ce38	6665	* @brief DEN value stored in LSB of Z-axis.[get]
cparata	0:6d69e896ce38	6666	*
cparata	0:6d69e896ce38	6667	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6668	* @param val change the values of den_x in reg CTRL9_XL
cparata	0:6d69e896ce38	6669	*
cparata	0:6d69e896ce38	6670	*/
cparata	0:6d69e896ce38	6671	int32_t lsm6dso_den_mark_axis_z_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6672	{
cparata	0:6d69e896ce38	6673	lsm6dso_ctrl9_xl_t reg;
cparata	0:6d69e896ce38	6674	int32_t ret;
cparata	0:6d69e896ce38	6675
cparata	0:6d69e896ce38	6676	ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6677	*val = reg.den_x;
cparata	0:6d69e896ce38	6678
cparata	0:6d69e896ce38	6679	return ret;
cparata	0:6d69e896ce38	6680	}
cparata	0:6d69e896ce38	6681
cparata	0:6d69e896ce38	6682	/**
cparata	0:6d69e896ce38	6683	* @}
cparata	0:6d69e896ce38	6684	*
cparata	0:6d69e896ce38	6685	*/
cparata	0:6d69e896ce38	6686
cparata	0:6d69e896ce38	6687	/**
cparata	0:6d69e896ce38	6688	* @defgroup LSM6DSO_Pedometer
cparata	0:6d69e896ce38	6689	* @brief This section groups all the functions that manage pedometer.
cparata	0:6d69e896ce38	6690	* @{
cparata	0:6d69e896ce38	6691	*
cparata	0:6d69e896ce38	6692	*/
cparata	0:6d69e896ce38	6693
cparata	0:6d69e896ce38	6694	/**
cparata	0:6d69e896ce38	6695	* @brief Enable pedometer algorithm.[set]
cparata	0:6d69e896ce38	6696	*
cparata	0:6d69e896ce38	6697	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6698	* @param val turn on and configure pedometer
cparata	0:6d69e896ce38	6699	*
cparata	0:6d69e896ce38	6700	*/
cparata	0:6d69e896ce38	6701	int32_t lsm6dso_pedo_sens_set(lsm6dso_ctx_t *ctx, lsm6dso_pedo_md_t val)
cparata	0:6d69e896ce38	6702	{
cparata	0:6d69e896ce38	6703	lsm6dso_emb_func_en_a_t emb_func_en_a;
cparata	0:6d69e896ce38	6704	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	0:6d69e896ce38	6705	lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
cparata	0:6d69e896ce38	6706	int32_t ret;
cparata	0:6d69e896ce38	6707
cparata	0:6d69e896ce38	6708	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	0:6d69e896ce38	6709	(uint8_t*)&pedo_cmd_reg);
cparata	0:6d69e896ce38	6710	if (ret == 0) {
cparata	0:6d69e896ce38	6711	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	6712	}
cparata	0:6d69e896ce38	6713	if (ret == 0) {
cparata	0:6d69e896ce38	6714	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	0:6d69e896ce38	6715	(uint8_t*)&emb_func_en_a, 1);
cparata	0:6d69e896ce38	6716	}
cparata	0:6d69e896ce38	6717	if (ret == 0) {
cparata	0:6d69e896ce38	6718	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	0:6d69e896ce38	6719	(uint8_t*)&emb_func_en_b, 1);
cparata	0:6d69e896ce38	6720
cparata	0:6d69e896ce38	6721	emb_func_en_a.pedo_en = (uint8_t)val & 0x01U;
cparata	0:6d69e896ce38	6722	emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U)>>1;
cparata	0:6d69e896ce38	6723	pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4;
cparata	0:6d69e896ce38	6724	pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5;
cparata	0:6d69e896ce38	6725	}
cparata	0:6d69e896ce38	6726	if (ret == 0) {
cparata	0:6d69e896ce38	6727	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	0:6d69e896ce38	6728	(uint8_t*)&emb_func_en_a, 1);
cparata	0:6d69e896ce38	6729	}
cparata	0:6d69e896ce38	6730	if (ret == 0) {
cparata	0:6d69e896ce38	6731	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	0:6d69e896ce38	6732	(uint8_t*)&emb_func_en_b, 1);
cparata	0:6d69e896ce38	6733	}
cparata	0:6d69e896ce38	6734	if (ret == 0) {
cparata	0:6d69e896ce38	6735	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6736	}
cparata	0:6d69e896ce38	6737	if (ret == 0) {
cparata	0:6d69e896ce38	6738	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	0:6d69e896ce38	6739	(uint8_t*)&pedo_cmd_reg);
cparata	0:6d69e896ce38	6740	}
cparata	0:6d69e896ce38	6741	return ret;
cparata	0:6d69e896ce38	6742	}
cparata	0:6d69e896ce38	6743
cparata	0:6d69e896ce38	6744	/**
cparata	0:6d69e896ce38	6745	* @brief Enable pedometer algorithm.[get]
cparata	0:6d69e896ce38	6746	*
cparata	0:6d69e896ce38	6747	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6748	* @param val turn on and configure pedometer
cparata	0:6d69e896ce38	6749	*
cparata	0:6d69e896ce38	6750	*/
cparata	0:6d69e896ce38	6751	int32_t lsm6dso_pedo_sens_get(lsm6dso_ctx_t ctx, lsm6dso_pedo_md_t val)
cparata	0:6d69e896ce38	6752	{
cparata	0:6d69e896ce38	6753	lsm6dso_emb_func_en_a_t emb_func_en_a;
cparata	0:6d69e896ce38	6754	lsm6dso_emb_func_en_b_t emb_func_en_b;
cparata	0:6d69e896ce38	6755	lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
cparata	0:6d69e896ce38	6756	int32_t ret;
cparata	0:6d69e896ce38	6757
cparata	0:6d69e896ce38	6758	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	0:6d69e896ce38	6759	(uint8_t*)&pedo_cmd_reg);
cparata	0:6d69e896ce38	6760	if (ret == 0) {
cparata	0:6d69e896ce38	6761	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	6762	}
cparata	0:6d69e896ce38	6763	if (ret == 0) {
cparata	0:6d69e896ce38	6764	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
cparata	0:6d69e896ce38	6765	(uint8_t*)&emb_func_en_a, 1);
cparata	0:6d69e896ce38	6766	}
cparata	0:6d69e896ce38	6767	if (ret == 0) {
cparata	0:6d69e896ce38	6768	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
cparata	0:6d69e896ce38	6769	(uint8_t*)&emb_func_en_b, 1);
cparata	0:6d69e896ce38	6770	}
cparata	0:6d69e896ce38	6771	if (ret == 0) {
cparata	0:6d69e896ce38	6772	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6773	}
cparata	0:6d69e896ce38	6774	switch ( (pedo_cmd_reg.ad_det_en <<5) \| (pedo_cmd_reg.fp_rejection_en << 4) \|
cparata	0:6d69e896ce38	6775	(emb_func_en_b.pedo_adv_en << 1) \| emb_func_en_a.pedo_en) {
cparata	0:6d69e896ce38	6776	case LSM6DSO_PEDO_DISABLE:
cparata	0:6d69e896ce38	6777	*val = LSM6DSO_PEDO_DISABLE;
cparata	0:6d69e896ce38	6778	break;
cparata	0:6d69e896ce38	6779	case LSM6DSO_PEDO_BASE_MODE:
cparata	0:6d69e896ce38	6780	*val = LSM6DSO_PEDO_BASE_MODE;
cparata	0:6d69e896ce38	6781	break;
cparata	0:6d69e896ce38	6782	case LSM6DSO_PEDO_ADV_MODE:
cparata	0:6d69e896ce38	6783	*val = LSM6DSO_PEDO_ADV_MODE;
cparata	0:6d69e896ce38	6784	break;
cparata	0:6d69e896ce38	6785	case LSM6DSO_FALSE_STEP_REJ:
cparata	0:6d69e896ce38	6786	*val = LSM6DSO_FALSE_STEP_REJ;
cparata	0:6d69e896ce38	6787	break;
cparata	0:6d69e896ce38	6788	case LSM6DSO_FALSE_STEP_REJ_ADV_MODE:
cparata	0:6d69e896ce38	6789	*val = LSM6DSO_FALSE_STEP_REJ_ADV_MODE;
cparata	0:6d69e896ce38	6790	break;
cparata	0:6d69e896ce38	6791	default:
cparata	0:6d69e896ce38	6792	*val = LSM6DSO_PEDO_DISABLE;
cparata	0:6d69e896ce38	6793	break;
cparata	0:6d69e896ce38	6794	}
cparata	0:6d69e896ce38	6795	return ret;
cparata	0:6d69e896ce38	6796	}
cparata	0:6d69e896ce38	6797
cparata	0:6d69e896ce38	6798	/**
cparata	0:6d69e896ce38	6799	* @brief Interrupt status bit for step detection.[get]
cparata	0:6d69e896ce38	6800	*
cparata	0:6d69e896ce38	6801	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6802	* @param val change the values of is_step_det in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	6803	*
cparata	0:6d69e896ce38	6804	*/
cparata	0:6d69e896ce38	6805	int32_t lsm6dso_pedo_step_detect_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6806	{
cparata	0:6d69e896ce38	6807	lsm6dso_emb_func_status_t reg;
cparata	0:6d69e896ce38	6808	int32_t ret;
cparata	0:6d69e896ce38	6809
cparata	0:6d69e896ce38	6810	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	6811	if (ret == 0) {
cparata	0:6d69e896ce38	6812	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6813	}
cparata	0:6d69e896ce38	6814	if (ret == 0) {
cparata	0:6d69e896ce38	6815	*val = reg.is_step_det;
cparata	0:6d69e896ce38	6816	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6817	}
cparata	0:6d69e896ce38	6818
cparata	0:6d69e896ce38	6819	return ret;
cparata	0:6d69e896ce38	6820	}
cparata	0:6d69e896ce38	6821
cparata	0:6d69e896ce38	6822	/**
cparata	0:6d69e896ce38	6823	* @brief Pedometer debounce configuration register (r/w).[set]
cparata	0:6d69e896ce38	6824	*
cparata	0:6d69e896ce38	6825	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6826	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	6827	*
cparata	0:6d69e896ce38	6828	*/
cparata	0:6d69e896ce38	6829	int32_t lsm6dso_pedo_debounce_steps_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6830	{
cparata	0:6d69e896ce38	6831	int32_t ret;
cparata	0:6d69e896ce38	6832	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
cparata	0:6d69e896ce38	6833	return ret;
cparata	0:6d69e896ce38	6834	}
cparata	0:6d69e896ce38	6835
cparata	0:6d69e896ce38	6836	/**
cparata	0:6d69e896ce38	6837	* @brief Pedometer debounce configuration register (r/w).[get]
cparata	0:6d69e896ce38	6838	*
cparata	0:6d69e896ce38	6839	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6840	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	6841	*
cparata	0:6d69e896ce38	6842	*/
cparata	0:6d69e896ce38	6843	int32_t lsm6dso_pedo_debounce_steps_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6844	{
cparata	0:6d69e896ce38	6845	int32_t ret;
cparata	0:6d69e896ce38	6846	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
cparata	0:6d69e896ce38	6847	return ret;
cparata	0:6d69e896ce38	6848	}
cparata	0:6d69e896ce38	6849
cparata	0:6d69e896ce38	6850	/**
cparata	0:6d69e896ce38	6851	* @brief Time period register for step detection on delta time (r/w).[set]
cparata	0:6d69e896ce38	6852	*
cparata	0:6d69e896ce38	6853	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6854	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	6855	*
cparata	0:6d69e896ce38	6856	*/
cparata	0:6d69e896ce38	6857	int32_t lsm6dso_pedo_steps_period_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6858	{
cparata	0:6d69e896ce38	6859	int32_t ret;
cparata	0:6d69e896ce38	6860	uint8_t index;
cparata	0:6d69e896ce38	6861
cparata	0:6d69e896ce38	6862	index = 0x00U;
cparata	0:6d69e896ce38	6863	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]);
cparata	0:6d69e896ce38	6864	if (ret == 0) {
cparata	0:6d69e896ce38	6865	index++;
cparata	0:6d69e896ce38	6866	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
cparata	0:6d69e896ce38	6867	&buff[index]);
cparata	0:6d69e896ce38	6868	}
cparata	0:6d69e896ce38	6869	return ret;
cparata	0:6d69e896ce38	6870	}
cparata	0:6d69e896ce38	6871
cparata	0:6d69e896ce38	6872	/**
cparata	0:6d69e896ce38	6873	* @brief Time period register for step detection on delta time (r/w).[get]
cparata	0:6d69e896ce38	6874	*
cparata	0:6d69e896ce38	6875	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6876	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	6877	*
cparata	0:6d69e896ce38	6878	*/
cparata	0:6d69e896ce38	6879	int32_t lsm6dso_pedo_steps_period_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	6880	{
cparata	0:6d69e896ce38	6881	int32_t ret;
cparata	0:6d69e896ce38	6882	uint8_t index;
cparata	0:6d69e896ce38	6883
cparata	0:6d69e896ce38	6884	index = 0x00U;
cparata	0:6d69e896ce38	6885	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]);
cparata	0:6d69e896ce38	6886	if (ret == 0) {
cparata	0:6d69e896ce38	6887	index++;
cparata	0:6d69e896ce38	6888	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
cparata	0:6d69e896ce38	6889	&buff[index]);
cparata	0:6d69e896ce38	6890	}
cparata	0:6d69e896ce38	6891	return ret;
cparata	0:6d69e896ce38	6892	}
cparata	0:6d69e896ce38	6893
cparata	0:6d69e896ce38	6894	/**
cparata	0:6d69e896ce38	6895	* @brief Set when user wants to generate interrupt on count overflow
cparata	0:6d69e896ce38	6896	* event/every step.[set]
cparata	0:6d69e896ce38	6897	*
cparata	0:6d69e896ce38	6898	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6899	* @param val change the values of carry_count_en in reg PEDO_CMD_REG
cparata	0:6d69e896ce38	6900	*
cparata	0:6d69e896ce38	6901	*/
cparata	0:6d69e896ce38	6902	int32_t lsm6dso_pedo_int_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	6903	lsm6dso_carry_count_en_t val)
cparata	0:6d69e896ce38	6904	{
cparata	0:6d69e896ce38	6905	lsm6dso_pedo_cmd_reg_t reg;
cparata	0:6d69e896ce38	6906	int32_t ret;
cparata	0:6d69e896ce38	6907
cparata	0:6d69e896ce38	6908	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t*)&reg);
cparata	0:6d69e896ce38	6909	if (ret == 0) {
cparata	0:6d69e896ce38	6910	reg.carry_count_en = (uint8_t)val;
cparata	0:6d69e896ce38	6911	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
cparata	0:6d69e896ce38	6912	(uint8_t*)&reg);
cparata	0:6d69e896ce38	6913	}
cparata	0:6d69e896ce38	6914	return ret;
cparata	0:6d69e896ce38	6915	}
cparata	0:6d69e896ce38	6916
cparata	0:6d69e896ce38	6917	/**
cparata	0:6d69e896ce38	6918	* @brief Set when user wants to generate interrupt on count overflow
cparata	0:6d69e896ce38	6919	* event/every step.[get]
cparata	0:6d69e896ce38	6920	*
cparata	0:6d69e896ce38	6921	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6922	* @param val Get the values of carry_count_en in reg PEDO_CMD_REG
cparata	0:6d69e896ce38	6923	*
cparata	0:6d69e896ce38	6924	*/
cparata	0:6d69e896ce38	6925	int32_t lsm6dso_pedo_int_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	6926	lsm6dso_carry_count_en_t *val)
cparata	0:6d69e896ce38	6927	{
cparata	0:6d69e896ce38	6928	lsm6dso_pedo_cmd_reg_t reg;
cparata	0:6d69e896ce38	6929	int32_t ret;
cparata	0:6d69e896ce38	6930
cparata	0:6d69e896ce38	6931	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t*)&reg);
cparata	0:6d69e896ce38	6932	switch (reg.carry_count_en) {
cparata	0:6d69e896ce38	6933	case LSM6DSO_EVERY_STEP:
cparata	0:6d69e896ce38	6934	*val = LSM6DSO_EVERY_STEP;
cparata	0:6d69e896ce38	6935	break;
cparata	0:6d69e896ce38	6936	case LSM6DSO_COUNT_OVERFLOW:
cparata	0:6d69e896ce38	6937	*val = LSM6DSO_COUNT_OVERFLOW;
cparata	0:6d69e896ce38	6938	break;
cparata	0:6d69e896ce38	6939	default:
cparata	0:6d69e896ce38	6940	*val = LSM6DSO_EVERY_STEP;
cparata	0:6d69e896ce38	6941	break;
cparata	0:6d69e896ce38	6942	}
cparata	0:6d69e896ce38	6943	return ret;
cparata	0:6d69e896ce38	6944	}
cparata	0:6d69e896ce38	6945
cparata	0:6d69e896ce38	6946	/**
cparata	0:6d69e896ce38	6947	* @}
cparata	0:6d69e896ce38	6948	*
cparata	0:6d69e896ce38	6949	*/
cparata	0:6d69e896ce38	6950
cparata	0:6d69e896ce38	6951	/**
cparata	0:6d69e896ce38	6952	* @defgroup LSM6DSO_significant_motion
cparata	0:6d69e896ce38	6953	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	6954	* significant motion detection.
cparata	0:6d69e896ce38	6955	* @{
cparata	0:6d69e896ce38	6956	*
cparata	0:6d69e896ce38	6957	*/
cparata	0:6d69e896ce38	6958
cparata	0:6d69e896ce38	6959	/**
cparata	0:6d69e896ce38	6960	* @brief Enable significant motion detection function.[set]
cparata	0:6d69e896ce38	6961	*
cparata	0:6d69e896ce38	6962	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6963	* @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
cparata	0:6d69e896ce38	6964	*
cparata	0:6d69e896ce38	6965	*/
cparata	0:6d69e896ce38	6966	int32_t lsm6dso_motion_sens_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	6967	{
cparata	0:6d69e896ce38	6968	lsm6dso_emb_func_en_a_t reg;
cparata	0:6d69e896ce38	6969	int32_t ret;
cparata	0:6d69e896ce38	6970
cparata	0:6d69e896ce38	6971	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	6972	if (ret == 0) {
cparata	0:6d69e896ce38	6973	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6974	}
cparata	0:6d69e896ce38	6975	if (ret == 0) {
cparata	0:6d69e896ce38	6976	reg.sign_motion_en = val;
cparata	0:6d69e896ce38	6977	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	6978	}
cparata	0:6d69e896ce38	6979	if (ret == 0) {
cparata	0:6d69e896ce38	6980	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	6981	}
cparata	0:6d69e896ce38	6982	return ret;
cparata	0:6d69e896ce38	6983	}
cparata	0:6d69e896ce38	6984
cparata	0:6d69e896ce38	6985	/**
cparata	0:6d69e896ce38	6986	* @brief Enable significant motion detection function.[get]
cparata	0:6d69e896ce38	6987	*
cparata	0:6d69e896ce38	6988	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	6989	* @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
cparata	0:6d69e896ce38	6990	*
cparata	0:6d69e896ce38	6991	*/
cparata	0:6d69e896ce38	6992	int32_t lsm6dso_motion_sens_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	6993	{
cparata	0:6d69e896ce38	6994	lsm6dso_emb_func_en_a_t reg;
cparata	0:6d69e896ce38	6995	int32_t ret;
cparata	0:6d69e896ce38	6996
cparata	0:6d69e896ce38	6997	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	6998	if (ret == 0) {
cparata	0:6d69e896ce38	6999	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7000	}
cparata	0:6d69e896ce38	7001	if (ret == 0) {
cparata	0:6d69e896ce38	7002	*val = reg.sign_motion_en;
cparata	0:6d69e896ce38	7003	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7004	}
cparata	0:6d69e896ce38	7005	return ret;
cparata	0:6d69e896ce38	7006	}
cparata	0:6d69e896ce38	7007
cparata	0:6d69e896ce38	7008	/**
cparata	0:6d69e896ce38	7009	* @brief Interrupt status bit for significant motion detection.[get]
cparata	0:6d69e896ce38	7010	*
cparata	0:6d69e896ce38	7011	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7012	* @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	7013	*
cparata	0:6d69e896ce38	7014	*/
cparata	0:6d69e896ce38	7015	int32_t lsm6dso_motion_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7016	{
cparata	0:6d69e896ce38	7017	lsm6dso_emb_func_status_t reg;
cparata	0:6d69e896ce38	7018	int32_t ret;
cparata	0:6d69e896ce38	7019
cparata	0:6d69e896ce38	7020	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7021	if (ret == 0) {
cparata	0:6d69e896ce38	7022	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7023	}
cparata	0:6d69e896ce38	7024	if (ret == 0) {
cparata	0:6d69e896ce38	7025	*val = reg.is_sigmot;
cparata	0:6d69e896ce38	7026	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7027	}
cparata	0:6d69e896ce38	7028
cparata	0:6d69e896ce38	7029	return ret;
cparata	0:6d69e896ce38	7030	}
cparata	0:6d69e896ce38	7031
cparata	0:6d69e896ce38	7032	/**
cparata	0:6d69e896ce38	7033	* @}
cparata	0:6d69e896ce38	7034	*
cparata	0:6d69e896ce38	7035	*/
cparata	0:6d69e896ce38	7036
cparata	0:6d69e896ce38	7037	/**
cparata	0:6d69e896ce38	7038	* @defgroup LSM6DSO_tilt_detection
cparata	0:6d69e896ce38	7039	* @brief This section groups all the functions that manage the tilt
cparata	0:6d69e896ce38	7040	* event detection.
cparata	0:6d69e896ce38	7041	* @{
cparata	0:6d69e896ce38	7042	*
cparata	0:6d69e896ce38	7043	*/
cparata	0:6d69e896ce38	7044
cparata	0:6d69e896ce38	7045	/**
cparata	0:6d69e896ce38	7046	* @brief Enable tilt calculation.[set]
cparata	0:6d69e896ce38	7047	*
cparata	0:6d69e896ce38	7048	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7049	* @param val change the values of tilt_en in reg EMB_FUNC_EN_A
cparata	0:6d69e896ce38	7050	*
cparata	0:6d69e896ce38	7051	*/
cparata	0:6d69e896ce38	7052	int32_t lsm6dso_tilt_sens_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	7053	{
cparata	0:6d69e896ce38	7054	lsm6dso_emb_func_en_a_t reg;
cparata	0:6d69e896ce38	7055	int32_t ret;
cparata	0:6d69e896ce38	7056
cparata	0:6d69e896ce38	7057	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7058	if (ret == 0) {
cparata	0:6d69e896ce38	7059	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7060	}
cparata	0:6d69e896ce38	7061	if (ret == 0) {
cparata	0:6d69e896ce38	7062	reg.tilt_en = val;
cparata	0:6d69e896ce38	7063	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7064	}
cparata	0:6d69e896ce38	7065	if (ret == 0) {
cparata	0:6d69e896ce38	7066	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7067	}
cparata	0:6d69e896ce38	7068	return ret;
cparata	0:6d69e896ce38	7069	}
cparata	0:6d69e896ce38	7070
cparata	0:6d69e896ce38	7071	/**
cparata	0:6d69e896ce38	7072	* @brief Enable tilt calculation.[get]
cparata	0:6d69e896ce38	7073	*
cparata	0:6d69e896ce38	7074	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7075	* @param val change the values of tilt_en in reg EMB_FUNC_EN_A
cparata	0:6d69e896ce38	7076	*
cparata	0:6d69e896ce38	7077	*/
cparata	0:6d69e896ce38	7078	int32_t lsm6dso_tilt_sens_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7079	{
cparata	0:6d69e896ce38	7080	lsm6dso_emb_func_en_a_t reg;
cparata	0:6d69e896ce38	7081	int32_t ret;
cparata	0:6d69e896ce38	7082
cparata	0:6d69e896ce38	7083	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7084	if (ret == 0) {
cparata	0:6d69e896ce38	7085	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7086	}
cparata	0:6d69e896ce38	7087	if (ret == 0) {
cparata	0:6d69e896ce38	7088	*val = reg.tilt_en;
cparata	0:6d69e896ce38	7089	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7090	}
cparata	0:6d69e896ce38	7091
cparata	0:6d69e896ce38	7092	return ret;
cparata	0:6d69e896ce38	7093	}
cparata	0:6d69e896ce38	7094
cparata	0:6d69e896ce38	7095	/**
cparata	0:6d69e896ce38	7096	* @brief Interrupt status bit for tilt detection.[get]
cparata	0:6d69e896ce38	7097	*
cparata	0:6d69e896ce38	7098	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7099	* @param val change the values of is_tilt in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	7100	*
cparata	0:6d69e896ce38	7101	*/
cparata	0:6d69e896ce38	7102	int32_t lsm6dso_tilt_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7103	{
cparata	0:6d69e896ce38	7104	lsm6dso_emb_func_status_t reg;
cparata	0:6d69e896ce38	7105	int32_t ret;
cparata	0:6d69e896ce38	7106
cparata	0:6d69e896ce38	7107	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7108	if (ret == 0) {
cparata	0:6d69e896ce38	7109	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7110	}
cparata	0:6d69e896ce38	7111	if (ret == 0) {
cparata	0:6d69e896ce38	7112	*val = reg.is_tilt;
cparata	0:6d69e896ce38	7113	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7114	}
cparata	0:6d69e896ce38	7115
cparata	0:6d69e896ce38	7116	return ret;
cparata	0:6d69e896ce38	7117	}
cparata	0:6d69e896ce38	7118
cparata	0:6d69e896ce38	7119	/**
cparata	0:6d69e896ce38	7120	* @}
cparata	0:6d69e896ce38	7121	*
cparata	0:6d69e896ce38	7122	*/
cparata	0:6d69e896ce38	7123
cparata	0:6d69e896ce38	7124	/**
cparata	0:6d69e896ce38	7125	* @defgroup LSM6DSO_ magnetometer_sensor
cparata	0:6d69e896ce38	7126	* @brief This section groups all the functions that manage additional
cparata	0:6d69e896ce38	7127	* magnetometer sensor.
cparata	0:6d69e896ce38	7128	* @{
cparata	0:6d69e896ce38	7129	*
cparata	0:6d69e896ce38	7130	*/
cparata	0:6d69e896ce38	7131
cparata	0:6d69e896ce38	7132	/**
cparata	0:6d69e896ce38	7133	* @brief External magnetometer sensitivity value register.[set]
cparata	0:6d69e896ce38	7134	*
cparata	0:6d69e896ce38	7135	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7136	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	7137	*
cparata	0:6d69e896ce38	7138	*/
cparata	0:6d69e896ce38	7139	int32_t lsm6dso_mag_sensitivity_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7140	{
cparata	0:6d69e896ce38	7141	int32_t ret;
cparata	0:6d69e896ce38	7142	uint8_t index;
cparata	0:6d69e896ce38	7143
cparata	0:6d69e896ce38	7144	index = 0x00U;
cparata	0:6d69e896ce38	7145	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
cparata	0:6d69e896ce38	7146	&buff[index]);
cparata	0:6d69e896ce38	7147	if (ret == 0) {
cparata	0:6d69e896ce38	7148	index++;
cparata	0:6d69e896ce38	7149	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
cparata	0:6d69e896ce38	7150	&buff[index]);
cparata	0:6d69e896ce38	7151	}
cparata	0:6d69e896ce38	7152
cparata	0:6d69e896ce38	7153	return ret;
cparata	0:6d69e896ce38	7154	}
cparata	0:6d69e896ce38	7155
cparata	0:6d69e896ce38	7156	/**
cparata	0:6d69e896ce38	7157	* @brief External magnetometer sensitivity value register.[get]
cparata	0:6d69e896ce38	7158	*
cparata	0:6d69e896ce38	7159	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7160	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7161	*
cparata	0:6d69e896ce38	7162	*/
cparata	0:6d69e896ce38	7163	int32_t lsm6dso_mag_sensitivity_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7164	{
cparata	0:6d69e896ce38	7165	int32_t ret;
cparata	0:6d69e896ce38	7166	uint8_t index;
cparata	0:6d69e896ce38	7167
cparata	0:6d69e896ce38	7168	index = 0x00U;
cparata	0:6d69e896ce38	7169	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
cparata	0:6d69e896ce38	7170	&buff[index]);
cparata	0:6d69e896ce38	7171	if (ret == 0) {
cparata	0:6d69e896ce38	7172	index++;
cparata	0:6d69e896ce38	7173	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
cparata	0:6d69e896ce38	7174	&buff[index]);
cparata	0:6d69e896ce38	7175	}
cparata	0:6d69e896ce38	7176
cparata	0:6d69e896ce38	7177	return ret;
cparata	0:6d69e896ce38	7178	}
cparata	0:6d69e896ce38	7179
cparata	0:6d69e896ce38	7180	/**
cparata	0:6d69e896ce38	7181	* @brief Offset for hard-iron compensation register (r/w).[set]
cparata	0:6d69e896ce38	7182	*
cparata	0:6d69e896ce38	7183	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7184	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	7185	*
cparata	0:6d69e896ce38	7186	*/
cparata	0:6d69e896ce38	7187	int32_t lsm6dso_mag_offset_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7188	{
cparata	0:6d69e896ce38	7189	int32_t ret;
cparata	0:6d69e896ce38	7190	uint8_t index;
cparata	0:6d69e896ce38	7191
cparata	0:6d69e896ce38	7192	index = 0x00U;
cparata	0:6d69e896ce38	7193	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]);
cparata	0:6d69e896ce38	7194	if (ret == 0) {
cparata	0:6d69e896ce38	7195	index++;
cparata	0:6d69e896ce38	7196	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]);
cparata	0:6d69e896ce38	7197	}
cparata	0:6d69e896ce38	7198	if (ret == 0) {
cparata	0:6d69e896ce38	7199	index++;
cparata	0:6d69e896ce38	7200	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]);
cparata	0:6d69e896ce38	7201	}
cparata	0:6d69e896ce38	7202	if (ret == 0) {
cparata	0:6d69e896ce38	7203	index++;
cparata	0:6d69e896ce38	7204	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]);
cparata	0:6d69e896ce38	7205	}
cparata	0:6d69e896ce38	7206	if (ret == 0) {
cparata	0:6d69e896ce38	7207	index++;
cparata	0:6d69e896ce38	7208
cparata	0:6d69e896ce38	7209	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]);
cparata	0:6d69e896ce38	7210	}
cparata	0:6d69e896ce38	7211	if (ret == 0) {
cparata	0:6d69e896ce38	7212	index++;
cparata	0:6d69e896ce38	7213	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]);
cparata	0:6d69e896ce38	7214	}
cparata	0:6d69e896ce38	7215
cparata	0:6d69e896ce38	7216	return ret;
cparata	0:6d69e896ce38	7217	}
cparata	0:6d69e896ce38	7218
cparata	0:6d69e896ce38	7219	/**
cparata	0:6d69e896ce38	7220	* @brief Offset for hard-iron compensation register (r/w).[get]
cparata	0:6d69e896ce38	7221	*
cparata	0:6d69e896ce38	7222	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7223	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7224	*
cparata	0:6d69e896ce38	7225	*/
cparata	0:6d69e896ce38	7226	int32_t lsm6dso_mag_offset_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7227	{
cparata	0:6d69e896ce38	7228	int32_t ret;
cparata	0:6d69e896ce38	7229	uint8_t index;
cparata	0:6d69e896ce38	7230
cparata	0:6d69e896ce38	7231	index = 0x00U;
cparata	0:6d69e896ce38	7232	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]);
cparata	0:6d69e896ce38	7233	if (ret == 0) {
cparata	0:6d69e896ce38	7234	index++;
cparata	0:6d69e896ce38	7235	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]);
cparata	0:6d69e896ce38	7236	}
cparata	0:6d69e896ce38	7237	if (ret == 0) {
cparata	0:6d69e896ce38	7238	index++;
cparata	0:6d69e896ce38	7239
cparata	0:6d69e896ce38	7240	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]);
cparata	0:6d69e896ce38	7241	}
cparata	0:6d69e896ce38	7242	if (ret == 0) {
cparata	0:6d69e896ce38	7243	index++;
cparata	0:6d69e896ce38	7244	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]);
cparata	0:6d69e896ce38	7245	}
cparata	0:6d69e896ce38	7246	if (ret == 0) {
cparata	0:6d69e896ce38	7247	index++;
cparata	0:6d69e896ce38	7248
cparata	0:6d69e896ce38	7249	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]);
cparata	0:6d69e896ce38	7250	}
cparata	0:6d69e896ce38	7251	if (ret == 0) {
cparata	0:6d69e896ce38	7252	index++;
cparata	0:6d69e896ce38	7253	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]);
cparata	0:6d69e896ce38	7254	}
cparata	0:6d69e896ce38	7255	return ret;
cparata	0:6d69e896ce38	7256	}
cparata	0:6d69e896ce38	7257
cparata	0:6d69e896ce38	7258	/**
cparata	0:6d69e896ce38	7259	* @brief Soft-iron (3x3 symmetric) matrix correction
cparata	0:6d69e896ce38	7260	* register (r/w). The value is expressed as
cparata	0:6d69e896ce38	7261	* half-precision floating-point format:
cparata	0:6d69e896ce38	7262	* SEEEEEFFFFFFFFFF
cparata	0:6d69e896ce38	7263	* S: 1 sign bit;
cparata	0:6d69e896ce38	7264	* E: 5 exponent bits;
cparata	0:6d69e896ce38	7265	* F: 10 fraction bits).[set]
cparata	0:6d69e896ce38	7266	*
cparata	0:6d69e896ce38	7267	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7268	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	7269	*
cparata	0:6d69e896ce38	7270	*/
cparata	0:6d69e896ce38	7271	int32_t lsm6dso_mag_soft_iron_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7272	{
cparata	0:6d69e896ce38	7273	int32_t ret;
cparata	0:6d69e896ce38	7274	uint8_t index;
cparata	0:6d69e896ce38	7275
cparata	0:6d69e896ce38	7276	index = 0x00U;
cparata	0:6d69e896ce38	7277	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
cparata	0:6d69e896ce38	7278	if (ret == 0) {
cparata	0:6d69e896ce38	7279	index++;
cparata	0:6d69e896ce38	7280	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
cparata	0:6d69e896ce38	7281	}
cparata	0:6d69e896ce38	7282	if (ret == 0) {
cparata	0:6d69e896ce38	7283	index++;
cparata	0:6d69e896ce38	7284
cparata	0:6d69e896ce38	7285	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
cparata	0:6d69e896ce38	7286	}
cparata	0:6d69e896ce38	7287	if (ret == 0) {
cparata	0:6d69e896ce38	7288	index++;
cparata	0:6d69e896ce38	7289	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
cparata	0:6d69e896ce38	7290	}
cparata	0:6d69e896ce38	7291	if (ret == 0) {
cparata	0:6d69e896ce38	7292	index++;
cparata	0:6d69e896ce38	7293
cparata	0:6d69e896ce38	7294	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
cparata	0:6d69e896ce38	7295	}
cparata	0:6d69e896ce38	7296	if (ret == 0) {
cparata	0:6d69e896ce38	7297	index++;
cparata	0:6d69e896ce38	7298	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
cparata	0:6d69e896ce38	7299	}
cparata	0:6d69e896ce38	7300	if (ret == 0) {
cparata	0:6d69e896ce38	7301	index++;
cparata	0:6d69e896ce38	7302
cparata	0:6d69e896ce38	7303	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
cparata	0:6d69e896ce38	7304	}
cparata	0:6d69e896ce38	7305	if (ret == 0) {
cparata	0:6d69e896ce38	7306	index++;
cparata	0:6d69e896ce38	7307	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
cparata	0:6d69e896ce38	7308	}
cparata	0:6d69e896ce38	7309	if (ret == 0) {
cparata	0:6d69e896ce38	7310	index++;
cparata	0:6d69e896ce38	7311
cparata	0:6d69e896ce38	7312	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
cparata	0:6d69e896ce38	7313	}
cparata	0:6d69e896ce38	7314	if (ret == 0) {
cparata	0:6d69e896ce38	7315	index++;
cparata	0:6d69e896ce38	7316	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
cparata	0:6d69e896ce38	7317	}
cparata	0:6d69e896ce38	7318	if (ret == 0) {
cparata	0:6d69e896ce38	7319	index++;
cparata	0:6d69e896ce38	7320
cparata	0:6d69e896ce38	7321	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
cparata	0:6d69e896ce38	7322	}
cparata	0:6d69e896ce38	7323	if (ret == 0) {
cparata	0:6d69e896ce38	7324	index++;
cparata	0:6d69e896ce38	7325	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
cparata	0:6d69e896ce38	7326	}
cparata	0:6d69e896ce38	7327
cparata	0:6d69e896ce38	7328	return ret;
cparata	0:6d69e896ce38	7329	}
cparata	0:6d69e896ce38	7330
cparata	0:6d69e896ce38	7331	/**
cparata	0:6d69e896ce38	7332	* @brief Soft-iron (3x3 symmetric) matrix
cparata	0:6d69e896ce38	7333	* correction register (r/w).
cparata	0:6d69e896ce38	7334	* The value is expressed as half-precision
cparata	0:6d69e896ce38	7335	* floating-point format:
cparata	0:6d69e896ce38	7336	* SEEEEEFFFFFFFFFF
cparata	0:6d69e896ce38	7337	* S: 1 sign bit;
cparata	0:6d69e896ce38	7338	* E: 5 exponent bits;
cparata	0:6d69e896ce38	7339	* F: 10 fraction bits.[get]
cparata	0:6d69e896ce38	7340	*
cparata	0:6d69e896ce38	7341	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7342	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7343	*
cparata	0:6d69e896ce38	7344	*/
cparata	0:6d69e896ce38	7345	int32_t lsm6dso_mag_soft_iron_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7346	{
cparata	0:6d69e896ce38	7347	int32_t ret;
cparata	0:6d69e896ce38	7348	uint8_t index;
cparata	0:6d69e896ce38	7349
cparata	0:6d69e896ce38	7350	index = 0x00U;
cparata	0:6d69e896ce38	7351	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
cparata	0:6d69e896ce38	7352	if (ret == 0) {
cparata	0:6d69e896ce38	7353	index++;
cparata	0:6d69e896ce38	7354	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
cparata	0:6d69e896ce38	7355	}
cparata	0:6d69e896ce38	7356	if (ret == 0) {
cparata	0:6d69e896ce38	7357	index++;
cparata	0:6d69e896ce38	7358
cparata	0:6d69e896ce38	7359	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
cparata	0:6d69e896ce38	7360	}
cparata	0:6d69e896ce38	7361	if (ret == 0) {
cparata	0:6d69e896ce38	7362	index++;
cparata	0:6d69e896ce38	7363	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
cparata	0:6d69e896ce38	7364	}
cparata	0:6d69e896ce38	7365	if (ret == 0) {
cparata	0:6d69e896ce38	7366	index++;
cparata	0:6d69e896ce38	7367
cparata	0:6d69e896ce38	7368	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
cparata	0:6d69e896ce38	7369	}
cparata	0:6d69e896ce38	7370	if (ret == 0) {
cparata	0:6d69e896ce38	7371	index++;
cparata	0:6d69e896ce38	7372	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
cparata	0:6d69e896ce38	7373	}
cparata	0:6d69e896ce38	7374	if (ret == 0) {
cparata	0:6d69e896ce38	7375	index++;
cparata	0:6d69e896ce38	7376
cparata	0:6d69e896ce38	7377	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
cparata	0:6d69e896ce38	7378	}
cparata	0:6d69e896ce38	7379	if (ret == 0) {
cparata	0:6d69e896ce38	7380	index++;
cparata	0:6d69e896ce38	7381	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
cparata	0:6d69e896ce38	7382	}
cparata	0:6d69e896ce38	7383	if (ret == 0) {
cparata	0:6d69e896ce38	7384	index++;
cparata	0:6d69e896ce38	7385
cparata	0:6d69e896ce38	7386	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
cparata	0:6d69e896ce38	7387	}
cparata	0:6d69e896ce38	7388	if (ret == 0) {
cparata	0:6d69e896ce38	7389	index++;
cparata	0:6d69e896ce38	7390	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
cparata	0:6d69e896ce38	7391	}
cparata	0:6d69e896ce38	7392	if (ret == 0) {
cparata	0:6d69e896ce38	7393	index++;
cparata	0:6d69e896ce38	7394
cparata	0:6d69e896ce38	7395	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
cparata	0:6d69e896ce38	7396	}
cparata	0:6d69e896ce38	7397	if (ret == 0) {
cparata	0:6d69e896ce38	7398	index++;
cparata	0:6d69e896ce38	7399	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
cparata	0:6d69e896ce38	7400	}
cparata	0:6d69e896ce38	7401
cparata	0:6d69e896ce38	7402	return ret;
cparata	0:6d69e896ce38	7403	}
cparata	0:6d69e896ce38	7404
cparata	0:6d69e896ce38	7405	/**
cparata	0:6d69e896ce38	7406	* @brief Magnetometer Z-axis coordinates
cparata	0:6d69e896ce38	7407	* rotation (to be aligned to
cparata	0:6d69e896ce38	7408	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7409	* orientation).[set]
cparata	0:6d69e896ce38	7410	*
cparata	0:6d69e896ce38	7411	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7412	* @param val change the values of mag_z_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7413	*
cparata	0:6d69e896ce38	7414	*/
cparata	0:6d69e896ce38	7415	int32_t lsm6dso_mag_z_orient_set(lsm6dso_ctx_t *ctx, lsm6dso_mag_z_axis_t val)
cparata	0:6d69e896ce38	7416	{
cparata	0:6d69e896ce38	7417	lsm6dso_mag_cfg_a_t reg;
cparata	0:6d69e896ce38	7418	int32_t ret;
cparata	0:6d69e896ce38	7419
cparata	0:6d69e896ce38	7420	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:6d69e896ce38	7421	if (ret == 0) {
cparata	0:6d69e896ce38	7422	reg.mag_z_axis = (uint8_t) val;
cparata	0:6d69e896ce38	7423	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:6d69e896ce38	7424	}
cparata	0:6d69e896ce38	7425
cparata	0:6d69e896ce38	7426	return ret;
cparata	0:6d69e896ce38	7427	}
cparata	0:6d69e896ce38	7428
cparata	0:6d69e896ce38	7429	/**
cparata	0:6d69e896ce38	7430	* @brief Magnetometer Z-axis coordinates
cparata	0:6d69e896ce38	7431	* rotation (to be aligned to
cparata	0:6d69e896ce38	7432	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7433	* orientation).[get]
cparata	0:6d69e896ce38	7434	*
cparata	0:6d69e896ce38	7435	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7436	* @param val Get the values of mag_z_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7437	*
cparata	0:6d69e896ce38	7438	*/
cparata	0:6d69e896ce38	7439	int32_t lsm6dso_mag_z_orient_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7440	lsm6dso_mag_z_axis_t *val)
cparata	0:6d69e896ce38	7441	{
cparata	0:6d69e896ce38	7442	lsm6dso_mag_cfg_a_t reg;
cparata	0:6d69e896ce38	7443	int32_t ret;
cparata	0:6d69e896ce38	7444	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:6d69e896ce38	7445	switch (reg.mag_z_axis) {
cparata	0:6d69e896ce38	7446	case LSM6DSO_Z_EQ_Y:
cparata	0:6d69e896ce38	7447	*val = LSM6DSO_Z_EQ_Y;
cparata	0:6d69e896ce38	7448	break;
cparata	0:6d69e896ce38	7449	case LSM6DSO_Z_EQ_MIN_Y:
cparata	0:6d69e896ce38	7450	*val = LSM6DSO_Z_EQ_MIN_Y;
cparata	0:6d69e896ce38	7451	break;
cparata	0:6d69e896ce38	7452	case LSM6DSO_Z_EQ_X:
cparata	0:6d69e896ce38	7453	*val = LSM6DSO_Z_EQ_X;
cparata	0:6d69e896ce38	7454	break;
cparata	0:6d69e896ce38	7455	case LSM6DSO_Z_EQ_MIN_X:
cparata	0:6d69e896ce38	7456	*val = LSM6DSO_Z_EQ_MIN_X;
cparata	0:6d69e896ce38	7457	break;
cparata	0:6d69e896ce38	7458	case LSM6DSO_Z_EQ_MIN_Z:
cparata	0:6d69e896ce38	7459	*val = LSM6DSO_Z_EQ_MIN_Z;
cparata	0:6d69e896ce38	7460	break;
cparata	0:6d69e896ce38	7461	case LSM6DSO_Z_EQ_Z:
cparata	0:6d69e896ce38	7462	*val = LSM6DSO_Z_EQ_Z;
cparata	0:6d69e896ce38	7463	break;
cparata	0:6d69e896ce38	7464	default:
cparata	0:6d69e896ce38	7465	*val = LSM6DSO_Z_EQ_Y;
cparata	0:6d69e896ce38	7466	break;
cparata	0:6d69e896ce38	7467	}
cparata	0:6d69e896ce38	7468	return ret;
cparata	0:6d69e896ce38	7469	}
cparata	0:6d69e896ce38	7470
cparata	0:6d69e896ce38	7471	/**
cparata	0:6d69e896ce38	7472	* @brief Magnetometer Y-axis coordinates
cparata	0:6d69e896ce38	7473	* rotation (to be aligned to
cparata	0:6d69e896ce38	7474	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7475	* orientation).[set]
cparata	0:6d69e896ce38	7476	*
cparata	0:6d69e896ce38	7477	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7478	* @param val change the values of mag_y_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7479	*
cparata	0:6d69e896ce38	7480	*/
cparata	0:6d69e896ce38	7481	int32_t lsm6dso_mag_y_orient_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7482	lsm6dso_mag_y_axis_t val)
cparata	0:6d69e896ce38	7483	{
cparata	0:6d69e896ce38	7484	lsm6dso_mag_cfg_a_t reg;
cparata	0:6d69e896ce38	7485	int32_t ret;
cparata	0:6d69e896ce38	7486
cparata	0:6d69e896ce38	7487	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:6d69e896ce38	7488	if (ret == 0) {
cparata	0:6d69e896ce38	7489	reg.mag_y_axis = (uint8_t)val;
cparata	0:6d69e896ce38	7490	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,(uint8_t*) &reg);
cparata	0:6d69e896ce38	7491	}
cparata	0:6d69e896ce38	7492	return ret;
cparata	0:6d69e896ce38	7493	}
cparata	0:6d69e896ce38	7494
cparata	0:6d69e896ce38	7495	/**
cparata	0:6d69e896ce38	7496	* @brief Magnetometer Y-axis coordinates
cparata	0:6d69e896ce38	7497	* rotation (to be aligned to
cparata	0:6d69e896ce38	7498	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7499	* orientation).[get]
cparata	0:6d69e896ce38	7500	*
cparata	0:6d69e896ce38	7501	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7502	* @param val Get the values of mag_y_axis in reg MAG_CFG_A
cparata	0:6d69e896ce38	7503	*
cparata	0:6d69e896ce38	7504	*/
cparata	0:6d69e896ce38	7505	int32_t lsm6dso_mag_y_orient_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7506	lsm6dso_mag_y_axis_t *val)
cparata	0:6d69e896ce38	7507	{
cparata	0:6d69e896ce38	7508	lsm6dso_mag_cfg_a_t reg;
cparata	0:6d69e896ce38	7509	int32_t ret;
cparata	0:6d69e896ce38	7510
cparata	0:6d69e896ce38	7511	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)&reg);
cparata	0:6d69e896ce38	7512	switch (reg.mag_y_axis) {
cparata	0:6d69e896ce38	7513	case LSM6DSO_Y_EQ_Y:
cparata	0:6d69e896ce38	7514	*val = LSM6DSO_Y_EQ_Y;
cparata	0:6d69e896ce38	7515	break;
cparata	0:6d69e896ce38	7516	case LSM6DSO_Y_EQ_MIN_Y:
cparata	0:6d69e896ce38	7517	*val = LSM6DSO_Y_EQ_MIN_Y;
cparata	0:6d69e896ce38	7518	break;
cparata	0:6d69e896ce38	7519	case LSM6DSO_Y_EQ_X:
cparata	0:6d69e896ce38	7520	*val = LSM6DSO_Y_EQ_X;
cparata	0:6d69e896ce38	7521	break;
cparata	0:6d69e896ce38	7522	case LSM6DSO_Y_EQ_MIN_X:
cparata	0:6d69e896ce38	7523	*val = LSM6DSO_Y_EQ_MIN_X;
cparata	0:6d69e896ce38	7524	break;
cparata	0:6d69e896ce38	7525	case LSM6DSO_Y_EQ_MIN_Z:
cparata	0:6d69e896ce38	7526	*val = LSM6DSO_Y_EQ_MIN_Z;
cparata	0:6d69e896ce38	7527	break;
cparata	0:6d69e896ce38	7528	case LSM6DSO_Y_EQ_Z:
cparata	0:6d69e896ce38	7529	*val = LSM6DSO_Y_EQ_Z;
cparata	0:6d69e896ce38	7530	break;
cparata	0:6d69e896ce38	7531	default:
cparata	0:6d69e896ce38	7532	*val = LSM6DSO_Y_EQ_Y;
cparata	0:6d69e896ce38	7533	break;
cparata	0:6d69e896ce38	7534	}
cparata	0:6d69e896ce38	7535	return ret;
cparata	0:6d69e896ce38	7536	}
cparata	0:6d69e896ce38	7537
cparata	0:6d69e896ce38	7538	/**
cparata	0:6d69e896ce38	7539	* @brief Magnetometer X-axis coordinates
cparata	0:6d69e896ce38	7540	* rotation (to be aligned to
cparata	0:6d69e896ce38	7541	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7542	* orientation).[set]
cparata	0:6d69e896ce38	7543	*
cparata	0:6d69e896ce38	7544	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7545	* @param val change the values of mag_x_axis in reg MAG_CFG_B
cparata	0:6d69e896ce38	7546	*
cparata	0:6d69e896ce38	7547	*/
cparata	0:6d69e896ce38	7548	int32_t lsm6dso_mag_x_orient_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7549	lsm6dso_mag_x_axis_t val)
cparata	0:6d69e896ce38	7550	{
cparata	0:6d69e896ce38	7551	lsm6dso_mag_cfg_b_t reg;
cparata	0:6d69e896ce38	7552	int32_t ret;
cparata	0:6d69e896ce38	7553
cparata	0:6d69e896ce38	7554	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)&reg);
cparata	0:6d69e896ce38	7555	if (ret == 0) {
cparata	0:6d69e896ce38	7556	reg.mag_x_axis = (uint8_t)val;
cparata	0:6d69e896ce38	7557	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)&reg);
cparata	0:6d69e896ce38	7558	}
cparata	0:6d69e896ce38	7559	return ret;
cparata	0:6d69e896ce38	7560	}
cparata	0:6d69e896ce38	7561
cparata	0:6d69e896ce38	7562	/**
cparata	0:6d69e896ce38	7563	* @brief Magnetometer X-axis coordinates
cparata	0:6d69e896ce38	7564	* rotation (to be aligned to
cparata	0:6d69e896ce38	7565	* accelerometer/gyroscope axes
cparata	0:6d69e896ce38	7566	* orientation).[get]
cparata	0:6d69e896ce38	7567	*
cparata	0:6d69e896ce38	7568	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7569	* @param val Get the values of mag_x_axis in reg MAG_CFG_B
cparata	0:6d69e896ce38	7570	*
cparata	0:6d69e896ce38	7571	*/
cparata	0:6d69e896ce38	7572	int32_t lsm6dso_mag_x_orient_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7573	lsm6dso_mag_x_axis_t *val)
cparata	0:6d69e896ce38	7574	{
cparata	0:6d69e896ce38	7575	lsm6dso_mag_cfg_b_t reg;
cparata	0:6d69e896ce38	7576	int32_t ret;
cparata	0:6d69e896ce38	7577
cparata	0:6d69e896ce38	7578	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)&reg);
cparata	0:6d69e896ce38	7579	switch (reg.mag_x_axis) {
cparata	0:6d69e896ce38	7580	case LSM6DSO_X_EQ_Y:
cparata	0:6d69e896ce38	7581	*val = LSM6DSO_X_EQ_Y;
cparata	0:6d69e896ce38	7582	break;
cparata	0:6d69e896ce38	7583	case LSM6DSO_X_EQ_MIN_Y:
cparata	0:6d69e896ce38	7584	*val = LSM6DSO_X_EQ_MIN_Y;
cparata	0:6d69e896ce38	7585	break;
cparata	0:6d69e896ce38	7586	case LSM6DSO_X_EQ_X:
cparata	0:6d69e896ce38	7587	*val = LSM6DSO_X_EQ_X;
cparata	0:6d69e896ce38	7588	break;
cparata	0:6d69e896ce38	7589	case LSM6DSO_X_EQ_MIN_X:
cparata	0:6d69e896ce38	7590	*val = LSM6DSO_X_EQ_MIN_X;
cparata	0:6d69e896ce38	7591	break;
cparata	0:6d69e896ce38	7592	case LSM6DSO_X_EQ_MIN_Z:
cparata	0:6d69e896ce38	7593	*val = LSM6DSO_X_EQ_MIN_Z;
cparata	0:6d69e896ce38	7594	break;
cparata	0:6d69e896ce38	7595	case LSM6DSO_X_EQ_Z:
cparata	0:6d69e896ce38	7596	*val = LSM6DSO_X_EQ_Z;
cparata	0:6d69e896ce38	7597	break;
cparata	0:6d69e896ce38	7598	default:
cparata	0:6d69e896ce38	7599	*val = LSM6DSO_X_EQ_Y;
cparata	0:6d69e896ce38	7600	break;
cparata	0:6d69e896ce38	7601	}
cparata	0:6d69e896ce38	7602	return ret;
cparata	0:6d69e896ce38	7603	}
cparata	0:6d69e896ce38	7604
cparata	0:6d69e896ce38	7605	/**
cparata	0:6d69e896ce38	7606	* @}
cparata	0:6d69e896ce38	7607	*
cparata	0:6d69e896ce38	7608	*/
cparata	0:6d69e896ce38	7609
cparata	0:6d69e896ce38	7610	/**
cparata	0:6d69e896ce38	7611	* @defgroup LSM6DSO_significant_motion
cparata	0:6d69e896ce38	7612	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	7613	* state_machine.
cparata	0:6d69e896ce38	7614	* @{
cparata	0:6d69e896ce38	7615	*
cparata	0:6d69e896ce38	7616	*/
cparata	0:6d69e896ce38	7617
cparata	0:6d69e896ce38	7618	/**
cparata	0:6d69e896ce38	7619	* @brief Interrupt status bit for FSM long counter
cparata	0:6d69e896ce38	7620	* timeout interrupt event.[get]
cparata	0:6d69e896ce38	7621	*
cparata	0:6d69e896ce38	7622	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7623	* @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
cparata	0:6d69e896ce38	7624	*
cparata	0:6d69e896ce38	7625	*/
cparata	0:6d69e896ce38	7626	int32_t lsm6dso_long_cnt_flag_data_ready_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7627	{
cparata	0:6d69e896ce38	7628	lsm6dso_emb_func_status_t reg;
cparata	0:6d69e896ce38	7629	int32_t ret;
cparata	0:6d69e896ce38	7630
cparata	0:6d69e896ce38	7631	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7632	if (ret == 0) {
cparata	0:6d69e896ce38	7633	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7634	}
cparata	0:6d69e896ce38	7635	if (ret == 0) {
cparata	0:6d69e896ce38	7636	*val = reg.is_fsm_lc;
cparata	0:6d69e896ce38	7637	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7638	}
cparata	0:6d69e896ce38	7639	return ret;
cparata	0:6d69e896ce38	7640	}
cparata	0:6d69e896ce38	7641
cparata	0:6d69e896ce38	7642	/**
cparata	0:6d69e896ce38	7643	* @brief Final State Machine global enable.[set]
cparata	0:6d69e896ce38	7644	*
cparata	0:6d69e896ce38	7645	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7646	* @param val change the values of fsm_en in reg EMB_FUNC_EN_B
cparata	0:6d69e896ce38	7647	*
cparata	0:6d69e896ce38	7648	*/
cparata	0:6d69e896ce38	7649	int32_t lsm6dso_emb_fsm_en_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	7650	{
cparata	0:6d69e896ce38	7651	int32_t ret;
cparata	0:6d69e896ce38	7652	lsm6dso_emb_func_en_b_t reg;
cparata	0:6d69e896ce38	7653
cparata	0:6d69e896ce38	7654	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7655	if (ret == 0) {
cparata	0:6d69e896ce38	7656	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7657	}
cparata	0:6d69e896ce38	7658	if (ret == 0) {
cparata	0:6d69e896ce38	7659	reg.fsm_en = val;
cparata	0:6d69e896ce38	7660	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7661	}
cparata	0:6d69e896ce38	7662	if (ret == 0) {
cparata	0:6d69e896ce38	7663	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7664	}
cparata	0:6d69e896ce38	7665	return ret;
cparata	0:6d69e896ce38	7666	}
cparata	0:6d69e896ce38	7667
cparata	0:6d69e896ce38	7668	/**
cparata	0:6d69e896ce38	7669	* @brief Final State Machine global enable.[get]
cparata	0:6d69e896ce38	7670	*
cparata	0:6d69e896ce38	7671	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7672	* @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B
cparata	0:6d69e896ce38	7673	*
cparata	0:6d69e896ce38	7674	*/
cparata	0:6d69e896ce38	7675	int32_t lsm6dso_emb_fsm_en_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	7676	{
cparata	0:6d69e896ce38	7677	int32_t ret;
cparata	0:6d69e896ce38	7678	lsm6dso_emb_func_en_b_t reg;
cparata	0:6d69e896ce38	7679
cparata	0:6d69e896ce38	7680	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7681	if (ret == 0) {
cparata	0:6d69e896ce38	7682	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7683	}
cparata	0:6d69e896ce38	7684	if (ret == 0) {
cparata	0:6d69e896ce38	7685	*val = reg.fsm_en;
cparata	0:6d69e896ce38	7686	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7687	}
cparata	0:6d69e896ce38	7688	if (ret == 0) {
cparata	0:6d69e896ce38	7689	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7690	}
cparata	0:6d69e896ce38	7691
cparata	0:6d69e896ce38	7692	return ret;
cparata	0:6d69e896ce38	7693	}
cparata	0:6d69e896ce38	7694
cparata	0:6d69e896ce38	7695	/**
cparata	0:6d69e896ce38	7696	* @brief Final State Machine enable.[set]
cparata	0:6d69e896ce38	7697	*
cparata	0:6d69e896ce38	7698	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7699	* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata	0:6d69e896ce38	7700	*
cparata	0:6d69e896ce38	7701	*/
cparata	0:6d69e896ce38	7702	int32_t lsm6dso_fsm_enable_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7703	lsm6dso_emb_fsm_enable_t *val)
cparata	0:6d69e896ce38	7704	{
cparata	0:6d69e896ce38	7705	int32_t ret;
cparata	0:6d69e896ce38	7706	lsm6dso_emb_func_en_b_t reg;
cparata	0:6d69e896ce38	7707
cparata	0:6d69e896ce38	7708	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7709	if (ret == 0) {
cparata	0:6d69e896ce38	7710	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A,
cparata	0:6d69e896ce38	7711	(uint8_t*)&val->fsm_enable_a, 1);
cparata	0:6d69e896ce38	7712	}
cparata	0:6d69e896ce38	7713	if (ret == 0) {
cparata	0:6d69e896ce38	7714	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B,
cparata	0:6d69e896ce38	7715	(uint8_t*)&val->fsm_enable_b, 1);
cparata	0:6d69e896ce38	7716	}
cparata	0:6d69e896ce38	7717	if (ret == 0) {
cparata	0:6d69e896ce38	7718	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7719	}
cparata	0:6d69e896ce38	7720	if (ret == 0) {
cparata	0:6d69e896ce38	7721	if ( (val->fsm_enable_a.fsm1_en \|
cparata	2:4d14e9edf37e	7722	val->fsm_enable_a.fsm2_en \|
cparata	2:4d14e9edf37e	7723	val->fsm_enable_a.fsm3_en \|
cparata	2:4d14e9edf37e	7724	val->fsm_enable_a.fsm4_en \|
cparata	2:4d14e9edf37e	7725	val->fsm_enable_a.fsm5_en \|
cparata	2:4d14e9edf37e	7726	val->fsm_enable_a.fsm6_en \|
cparata	2:4d14e9edf37e	7727	val->fsm_enable_a.fsm7_en \|
cparata	2:4d14e9edf37e	7728	val->fsm_enable_a.fsm8_en \|
cparata	2:4d14e9edf37e	7729	val->fsm_enable_b.fsm9_en \|
cparata	2:4d14e9edf37e	7730	val->fsm_enable_b.fsm10_en \|
cparata	2:4d14e9edf37e	7731	val->fsm_enable_b.fsm11_en \|
cparata	2:4d14e9edf37e	7732	val->fsm_enable_b.fsm12_en \|
cparata	2:4d14e9edf37e	7733	val->fsm_enable_b.fsm13_en \|
cparata	2:4d14e9edf37e	7734	val->fsm_enable_b.fsm14_en \|
cparata	2:4d14e9edf37e	7735	val->fsm_enable_b.fsm15_en \|
cparata	2:4d14e9edf37e	7736	val->fsm_enable_b.fsm16_en )
cparata	0:6d69e896ce38	7737	!= PROPERTY_DISABLE)
cparata	0:6d69e896ce38	7738	{
cparata	0:6d69e896ce38	7739	reg.fsm_en = PROPERTY_ENABLE;
cparata	0:6d69e896ce38	7740	}
cparata	0:6d69e896ce38	7741	else
cparata	0:6d69e896ce38	7742	{
cparata	0:6d69e896ce38	7743	reg.fsm_en = PROPERTY_DISABLE;
cparata	0:6d69e896ce38	7744	}
cparata	0:6d69e896ce38	7745
cparata	0:6d69e896ce38	7746	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7747	}
cparata	0:6d69e896ce38	7748	if (ret == 0) {
cparata	0:6d69e896ce38	7749	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7750	}
cparata	0:6d69e896ce38	7751
cparata	0:6d69e896ce38	7752	return ret;
cparata	0:6d69e896ce38	7753	}
cparata	0:6d69e896ce38	7754
cparata	0:6d69e896ce38	7755	/**
cparata	0:6d69e896ce38	7756	* @brief Final State Machine enable.[get]
cparata	0:6d69e896ce38	7757	*
cparata	0:6d69e896ce38	7758	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7759	* @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
cparata	0:6d69e896ce38	7760	*
cparata	0:6d69e896ce38	7761	*/
cparata	0:6d69e896ce38	7762	int32_t lsm6dso_fsm_enable_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	7763	lsm6dso_emb_fsm_enable_t *val)
cparata	0:6d69e896ce38	7764	{
cparata	0:6d69e896ce38	7765	int32_t ret;
cparata	0:6d69e896ce38	7766
cparata	0:6d69e896ce38	7767	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7768	if (ret == 0) {
cparata	0:6d69e896ce38	7769	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t*) val, 2);
cparata	0:6d69e896ce38	7770	}
cparata	0:6d69e896ce38	7771	if (ret == 0) {
cparata	0:6d69e896ce38	7772	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7773	}
cparata	0:6d69e896ce38	7774	return ret;
cparata	0:6d69e896ce38	7775	}
cparata	0:6d69e896ce38	7776
cparata	0:6d69e896ce38	7777	/**
cparata	0:6d69e896ce38	7778	* @brief FSM long counter status register. Long counter value is an
cparata	0:6d69e896ce38	7779	* unsigned integer value (16-bit format).[set]
cparata	0:6d69e896ce38	7780	*
cparata	0:6d69e896ce38	7781	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7782	* @param buff buffer that contains data to write
cparata	0:6d69e896ce38	7783	*
cparata	0:6d69e896ce38	7784	*/
cparata	0:6d69e896ce38	7785	int32_t lsm6dso_long_cnt_set(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7786	{
cparata	0:6d69e896ce38	7787	int32_t ret;
cparata	0:6d69e896ce38	7788
cparata	0:6d69e896ce38	7789	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7790	if (ret == 0) {
cparata	0:6d69e896ce38	7791	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
cparata	0:6d69e896ce38	7792	}
cparata	0:6d69e896ce38	7793	if (ret == 0) {
cparata	0:6d69e896ce38	7794	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7795	}
cparata	0:6d69e896ce38	7796
cparata	0:6d69e896ce38	7797	return ret;
cparata	0:6d69e896ce38	7798	}
cparata	0:6d69e896ce38	7799
cparata	0:6d69e896ce38	7800	/**
cparata	0:6d69e896ce38	7801	* @brief FSM long counter status register. Long counter value is an
cparata	0:6d69e896ce38	7802	* unsigned integer value (16-bit format).[get]
cparata	0:6d69e896ce38	7803	*
cparata	0:6d69e896ce38	7804	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7805	* @param buff buffer that stores data read
cparata	0:6d69e896ce38	7806	*
cparata	0:6d69e896ce38	7807	*/
cparata	0:6d69e896ce38	7808	int32_t lsm6dso_long_cnt_get(lsm6dso_ctx_t ctx, uint8_t buff)
cparata	0:6d69e896ce38	7809	{
cparata	0:6d69e896ce38	7810	int32_t ret;
cparata	0:6d69e896ce38	7811
cparata	0:6d69e896ce38	7812	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7813	if (ret == 0) {
cparata	0:6d69e896ce38	7814	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
cparata	0:6d69e896ce38	7815	}
cparata	0:6d69e896ce38	7816	if (ret == 0) {
cparata	0:6d69e896ce38	7817	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7818	}
cparata	0:6d69e896ce38	7819
cparata	0:6d69e896ce38	7820	return ret;
cparata	0:6d69e896ce38	7821	}
cparata	0:6d69e896ce38	7822
cparata	0:6d69e896ce38	7823	/**
cparata	0:6d69e896ce38	7824	* @brief Clear FSM long counter value.[set]
cparata	0:6d69e896ce38	7825	*
cparata	0:6d69e896ce38	7826	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7827	* @param val change the values of fsm_lc_clr in
cparata	0:6d69e896ce38	7828	* reg FSM_LONG_COUNTER_CLEAR
cparata	0:6d69e896ce38	7829	*
cparata	0:6d69e896ce38	7830	*/
cparata	0:6d69e896ce38	7831	int32_t lsm6dso_long_clr_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val)
cparata	0:6d69e896ce38	7832	{
cparata	0:6d69e896ce38	7833	lsm6dso_fsm_long_counter_clear_t reg;
cparata	0:6d69e896ce38	7834	int32_t ret;
cparata	0:6d69e896ce38	7835
cparata	0:6d69e896ce38	7836	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7837	if (ret == 0) {
cparata	0:6d69e896ce38	7838	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
cparata	0:6d69e896ce38	7839	(uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7840	}
cparata	0:6d69e896ce38	7841	if (ret == 0) {
cparata	0:6d69e896ce38	7842	reg. fsm_lc_clr = (uint8_t)val;
cparata	0:6d69e896ce38	7843	ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
cparata	0:6d69e896ce38	7844	(uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7845	}
cparata	0:6d69e896ce38	7846	if (ret == 0) {
cparata	0:6d69e896ce38	7847	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7848	}
cparata	0:6d69e896ce38	7849	return ret;
cparata	0:6d69e896ce38	7850	}
cparata	0:6d69e896ce38	7851
cparata	0:6d69e896ce38	7852	/**
cparata	0:6d69e896ce38	7853	* @brief Clear FSM long counter value.[get]
cparata	0:6d69e896ce38	7854	*
cparata	0:6d69e896ce38	7855	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7856	* @param val Get the values of fsm_lc_clr in
cparata	0:6d69e896ce38	7857	* reg FSM_LONG_COUNTER_CLEAR
cparata	0:6d69e896ce38	7858	*
cparata	0:6d69e896ce38	7859	*/
cparata	0:6d69e896ce38	7860	int32_t lsm6dso_long_clr_get(lsm6dso_ctx_t ctx, lsm6dso_fsm_lc_clr_t val)
cparata	0:6d69e896ce38	7861	{
cparata	0:6d69e896ce38	7862	lsm6dso_fsm_long_counter_clear_t reg;
cparata	0:6d69e896ce38	7863	int32_t ret;
cparata	0:6d69e896ce38	7864
cparata	0:6d69e896ce38	7865	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7866	if (ret == 0) {
cparata	0:6d69e896ce38	7867	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
cparata	0:6d69e896ce38	7868	(uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7869	}
cparata	0:6d69e896ce38	7870	if (ret == 0) {
cparata	0:6d69e896ce38	7871	switch (reg.fsm_lc_clr) {
cparata	0:6d69e896ce38	7872	case LSM6DSO_LC_NORMAL:
cparata	0:6d69e896ce38	7873	*val = LSM6DSO_LC_NORMAL;
cparata	0:6d69e896ce38	7874	break;
cparata	0:6d69e896ce38	7875	case LSM6DSO_LC_CLEAR:
cparata	0:6d69e896ce38	7876	*val = LSM6DSO_LC_CLEAR;
cparata	0:6d69e896ce38	7877	break;
cparata	0:6d69e896ce38	7878	case LSM6DSO_LC_CLEAR_DONE:
cparata	0:6d69e896ce38	7879	*val = LSM6DSO_LC_CLEAR_DONE;
cparata	0:6d69e896ce38	7880	break;
cparata	0:6d69e896ce38	7881	default:
cparata	0:6d69e896ce38	7882	*val = LSM6DSO_LC_NORMAL;
cparata	0:6d69e896ce38	7883	break;
cparata	0:6d69e896ce38	7884	}
cparata	0:6d69e896ce38	7885	}
cparata	0:6d69e896ce38	7886
cparata	0:6d69e896ce38	7887	if (ret == 0) {
cparata	0:6d69e896ce38	7888	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7889	}
cparata	0:6d69e896ce38	7890
cparata	0:6d69e896ce38	7891	return ret;
cparata	0:6d69e896ce38	7892	}
cparata	0:6d69e896ce38	7893
cparata	0:6d69e896ce38	7894	/**
cparata	0:6d69e896ce38	7895	* @brief FSM output registers[get]
cparata	0:6d69e896ce38	7896	*
cparata	0:6d69e896ce38	7897	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7898	* @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
cparata	0:6d69e896ce38	7899	*
cparata	0:6d69e896ce38	7900	*/
cparata	0:6d69e896ce38	7901	int32_t lsm6dso_fsm_out_get(lsm6dso_ctx_t ctx, lsm6dso_fsm_out_t val)
cparata	0:6d69e896ce38	7902	{
cparata	0:6d69e896ce38	7903	int32_t ret;
cparata	0:6d69e896ce38	7904
cparata	0:6d69e896ce38	7905	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7906	if (ret == 0) {
cparata	2:4d14e9edf37e	7907	ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t*)val, 16);
cparata	0:6d69e896ce38	7908	}
cparata	0:6d69e896ce38	7909	if (ret == 0) {
cparata	0:6d69e896ce38	7910	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7911	}
cparata	0:6d69e896ce38	7912
cparata	0:6d69e896ce38	7913	return ret;
cparata	0:6d69e896ce38	7914	}
cparata	0:6d69e896ce38	7915
cparata	0:6d69e896ce38	7916	/**
cparata	0:6d69e896ce38	7917	* @brief Finite State Machine ODR configuration.[set]
cparata	0:6d69e896ce38	7918	*
cparata	0:6d69e896ce38	7919	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7920	* @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata	0:6d69e896ce38	7921	*
cparata	0:6d69e896ce38	7922	*/
cparata	0:6d69e896ce38	7923	int32_t lsm6dso_fsm_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_odr_t val)
cparata	0:6d69e896ce38	7924	{
cparata	0:6d69e896ce38	7925	lsm6dso_emb_func_odr_cfg_b_t reg;
cparata	0:6d69e896ce38	7926	int32_t ret;
cparata	0:6d69e896ce38	7927
cparata	0:6d69e896ce38	7928	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7929	if (ret == 0) {
cparata	0:6d69e896ce38	7930	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
cparata	0:6d69e896ce38	7931	(uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7932	}
cparata	0:6d69e896ce38	7933	if (ret == 0) {
cparata	0:6d69e896ce38	7934	reg.not_used_01 = 3; /* set default values */
cparata	2:4d14e9edf37e	7935	reg.not_used_02 = 2; /* set default values */
cparata	0:6d69e896ce38	7936	reg.fsm_odr = (uint8_t)val;
cparata	0:6d69e896ce38	7937	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
cparata	0:6d69e896ce38	7938	(uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7939	}
cparata	0:6d69e896ce38	7940	if (ret == 0) {
cparata	0:6d69e896ce38	7941	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7942	}
cparata	0:6d69e896ce38	7943	return ret;
cparata	0:6d69e896ce38	7944	}
cparata	0:6d69e896ce38	7945
cparata	0:6d69e896ce38	7946	/**
cparata	0:6d69e896ce38	7947	* @brief Finite State Machine ODR configuration.[get]
cparata	0:6d69e896ce38	7948	*
cparata	0:6d69e896ce38	7949	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7950	* @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
cparata	0:6d69e896ce38	7951	*
cparata	0:6d69e896ce38	7952	*/
cparata	0:6d69e896ce38	7953	int32_t lsm6dso_fsm_data_rate_get(lsm6dso_ctx_t ctx, lsm6dso_fsm_odr_t val)
cparata	0:6d69e896ce38	7954	{
cparata	0:6d69e896ce38	7955	lsm6dso_emb_func_odr_cfg_b_t reg;
cparata	0:6d69e896ce38	7956	int32_t ret;
cparata	0:6d69e896ce38	7957
cparata	0:6d69e896ce38	7958	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	7959	if (ret == 0) {
cparata	0:6d69e896ce38	7960	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
cparata	0:6d69e896ce38	7961	(uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	7962	}
cparata	0:6d69e896ce38	7963	if (ret == 0) {
cparata	0:6d69e896ce38	7964	switch (reg.fsm_odr) {
cparata	0:6d69e896ce38	7965	case LSM6DSO_ODR_FSM_12Hz5:
cparata	0:6d69e896ce38	7966	*val = LSM6DSO_ODR_FSM_12Hz5;
cparata	0:6d69e896ce38	7967	break;
cparata	0:6d69e896ce38	7968	case LSM6DSO_ODR_FSM_26Hz:
cparata	0:6d69e896ce38	7969	*val = LSM6DSO_ODR_FSM_26Hz;
cparata	0:6d69e896ce38	7970	break;
cparata	0:6d69e896ce38	7971	case LSM6DSO_ODR_FSM_52Hz:
cparata	0:6d69e896ce38	7972	*val = LSM6DSO_ODR_FSM_52Hz;
cparata	0:6d69e896ce38	7973	break;
cparata	0:6d69e896ce38	7974	case LSM6DSO_ODR_FSM_104Hz:
cparata	0:6d69e896ce38	7975	*val = LSM6DSO_ODR_FSM_104Hz;
cparata	0:6d69e896ce38	7976	break;
cparata	0:6d69e896ce38	7977	default:
cparata	0:6d69e896ce38	7978	*val = LSM6DSO_ODR_FSM_12Hz5;
cparata	0:6d69e896ce38	7979	break;
cparata	0:6d69e896ce38	7980	}
cparata	0:6d69e896ce38	7981	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	7982	}
cparata	0:6d69e896ce38	7983
cparata	0:6d69e896ce38	7984	return ret;
cparata	0:6d69e896ce38	7985	}
cparata	0:6d69e896ce38	7986
cparata	0:6d69e896ce38	7987	/**
cparata	0:6d69e896ce38	7988	* @brief FSM initialization request.[set]
cparata	0:6d69e896ce38	7989	*
cparata	0:6d69e896ce38	7990	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	7991	* @param val change the values of fsm_init in reg FSM_INIT
cparata	0:6d69e896ce38	7992	*
cparata	0:6d69e896ce38	7993	*/
cparata	0:6d69e896ce38	7994	int32_t lsm6dso_fsm_init_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	7995	{
cparata	0:6d69e896ce38	7996	lsm6dso_emb_func_init_b_t reg;
cparata	0:6d69e896ce38	7997	int32_t ret;
cparata	0:6d69e896ce38	7998
cparata	0:6d69e896ce38	7999	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	8000	if (ret == 0) {
cparata	0:6d69e896ce38	8001	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8002	}
cparata	0:6d69e896ce38	8003	if (ret == 0) {
cparata	0:6d69e896ce38	8004	reg.fsm_init = val;
cparata	0:6d69e896ce38	8005	ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8006	}
cparata	0:6d69e896ce38	8007	if (ret == 0) {
cparata	0:6d69e896ce38	8008	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8009	}
cparata	0:6d69e896ce38	8010
cparata	0:6d69e896ce38	8011	return ret;
cparata	0:6d69e896ce38	8012	}
cparata	0:6d69e896ce38	8013
cparata	0:6d69e896ce38	8014	/**
cparata	0:6d69e896ce38	8015	* @brief FSM initialization request.[get]
cparata	0:6d69e896ce38	8016	*
cparata	0:6d69e896ce38	8017	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8018	* @param val change the values of fsm_init in reg FSM_INIT
cparata	0:6d69e896ce38	8019	*
cparata	0:6d69e896ce38	8020	*/
cparata	0:6d69e896ce38	8021	int32_t lsm6dso_fsm_init_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8022	{
cparata	0:6d69e896ce38	8023	lsm6dso_emb_func_init_b_t reg;
cparata	0:6d69e896ce38	8024	int32_t ret;
cparata	0:6d69e896ce38	8025
cparata	0:6d69e896ce38	8026	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
cparata	0:6d69e896ce38	8027	if (ret == 0) {
cparata	0:6d69e896ce38	8028	ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8029	}
cparata	0:6d69e896ce38	8030	if (ret == 0) {
cparata	0:6d69e896ce38	8031	*val = reg.fsm_init;
cparata	0:6d69e896ce38	8032	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8033	}
cparata	0:6d69e896ce38	8034	return ret;
cparata	0:6d69e896ce38	8035	}
cparata	0:6d69e896ce38	8036
cparata	0:6d69e896ce38	8037	/**
cparata	0:6d69e896ce38	8038	* @brief FSM long counter timeout register (r/w). The long counter
cparata	0:6d69e896ce38	8039	* timeout value is an unsigned integer value (16-bit format).
cparata	0:6d69e896ce38	8040	* When the long counter value reached this value,
cparata	0:6d69e896ce38	8041	* the FSM generates an interrupt.[set]
cparata	0:6d69e896ce38	8042	*
cparata	0:6d69e896ce38	8043	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8044	* @param val the value of long counter
cparata	2:4d14e9edf37e	8045	*
cparata	2:4d14e9edf37e	8046	*/
cparata	2:4d14e9edf37e	8047	int32_t lsm6dso_long_cnt_int_value_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	2:4d14e9edf37e	8048	{
cparata	2:4d14e9edf37e	8049	int32_t ret;
cparata	2:4d14e9edf37e	8050	uint8_t add_l;
cparata	2:4d14e9edf37e	8051	uint8_t add_h;
cparata	2:4d14e9edf37e	8052
cparata	2:4d14e9edf37e	8053	add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
cparata	2:4d14e9edf37e	8054	add_l = (uint8_t)( val & 0x00FFU );
cparata	2:4d14e9edf37e	8055
cparata	2:4d14e9edf37e	8056	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l);
cparata	2:4d14e9edf37e	8057	if (ret == 0) {
cparata	2:4d14e9edf37e	8058	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h);
cparata	0:6d69e896ce38	8059	}
cparata	0:6d69e896ce38	8060
cparata	0:6d69e896ce38	8061	return ret;
cparata	0:6d69e896ce38	8062	}
cparata	0:6d69e896ce38	8063
cparata	0:6d69e896ce38	8064	/**
cparata	0:6d69e896ce38	8065	* @brief FSM long counter timeout register (r/w). The long counter
cparata	0:6d69e896ce38	8066	* timeout value is an unsigned integer value (16-bit format).
cparata	0:6d69e896ce38	8067	* When the long counter value reached this value,
cparata	0:6d69e896ce38	8068	* the FSM generates an interrupt.[get]
cparata	0:6d69e896ce38	8069	*
cparata	2:4d14e9edf37e	8070	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8071	* @param val buffer that stores the value of long counter
cparata	2:4d14e9edf37e	8072	*
cparata	2:4d14e9edf37e	8073	*/
cparata	2:4d14e9edf37e	8074	int32_t lsm6dso_long_cnt_int_value_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	2:4d14e9edf37e	8075	{
cparata	2:4d14e9edf37e	8076	int32_t ret;
cparata	2:4d14e9edf37e	8077	uint8_t add_l;
cparata	2:4d14e9edf37e	8078	uint8_t add_h;
cparata	2:4d14e9edf37e	8079
cparata	2:4d14e9edf37e	8080	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l);
cparata	2:4d14e9edf37e	8081	if (ret == 0) {
cparata	2:4d14e9edf37e	8082	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h);
cparata	2:4d14e9edf37e	8083	*val = add_h;
cparata	2:4d14e9edf37e	8084	val = val << 8;
cparata	2:4d14e9edf37e	8085	*val += add_l;
cparata	0:6d69e896ce38	8086	}
cparata	0:6d69e896ce38	8087
cparata	0:6d69e896ce38	8088	return ret;
cparata	0:6d69e896ce38	8089	}
cparata	0:6d69e896ce38	8090
cparata	0:6d69e896ce38	8091	/**
cparata	0:6d69e896ce38	8092	* @brief FSM number of programs register.[set]
cparata	0:6d69e896ce38	8093	*
cparata	0:6d69e896ce38	8094	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8095	* @param val value to write
cparata	2:4d14e9edf37e	8096	*
cparata	2:4d14e9edf37e	8097	*/
cparata	2:4d14e9edf37e	8098	int32_t lsm6dso_fsm_number_of_programs_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	2:4d14e9edf37e	8099	{
cparata	2:4d14e9edf37e	8100	int32_t ret;
cparata	2:4d14e9edf37e	8101
cparata	2:4d14e9edf37e	8102	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_PROGRAMS, &val);
cparata	0:6d69e896ce38	8103
cparata	0:6d69e896ce38	8104	return ret;
cparata	0:6d69e896ce38	8105	}
cparata	0:6d69e896ce38	8106
cparata	0:6d69e896ce38	8107	/**
cparata	0:6d69e896ce38	8108	* @brief FSM number of programs register.[get]
cparata	0:6d69e896ce38	8109	*
cparata	0:6d69e896ce38	8110	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8111	* @param val buffer that stores data read.
cparata	2:4d14e9edf37e	8112	*
cparata	2:4d14e9edf37e	8113	*/
cparata	2:4d14e9edf37e	8114	int32_t lsm6dso_fsm_number_of_programs_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	2:4d14e9edf37e	8115	{
cparata	2:4d14e9edf37e	8116	int32_t ret;
cparata	2:4d14e9edf37e	8117
cparata	2:4d14e9edf37e	8118	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_PROGRAMS, val);
cparata	0:6d69e896ce38	8119
cparata	0:6d69e896ce38	8120	return ret;
cparata	0:6d69e896ce38	8121	}
cparata	0:6d69e896ce38	8122
cparata	0:6d69e896ce38	8123	/**
cparata	0:6d69e896ce38	8124	* @brief FSM start address register (r/w).
cparata	0:6d69e896ce38	8125	* First available address is 0x033C.[set]
cparata	0:6d69e896ce38	8126	*
cparata	0:6d69e896ce38	8127	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8128	* @param val the value of start address
cparata	2:4d14e9edf37e	8129	*
cparata	2:4d14e9edf37e	8130	*/
cparata	2:4d14e9edf37e	8131	int32_t lsm6dso_fsm_start_address_set(lsm6dso_ctx_t *ctx, uint16_t val)
cparata	2:4d14e9edf37e	8132	{
cparata	2:4d14e9edf37e	8133	int32_t ret;
cparata	2:4d14e9edf37e	8134	uint8_t add_l;
cparata	2:4d14e9edf37e	8135	uint8_t add_h;
cparata	2:4d14e9edf37e	8136
cparata	2:4d14e9edf37e	8137	add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 );
cparata	2:4d14e9edf37e	8138	add_l = (uint8_t)( val & 0x00FFU );
cparata	2:4d14e9edf37e	8139
cparata	2:4d14e9edf37e	8140	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l);
cparata	2:4d14e9edf37e	8141	if (ret == 0) {
cparata	2:4d14e9edf37e	8142	ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h);
cparata	0:6d69e896ce38	8143	}
cparata	0:6d69e896ce38	8144	return ret;
cparata	0:6d69e896ce38	8145	}
cparata	0:6d69e896ce38	8146
cparata	0:6d69e896ce38	8147	/**
cparata	0:6d69e896ce38	8148	* @brief FSM start address register (r/w).
cparata	0:6d69e896ce38	8149	* First available address is 0x033C.[get]
cparata	0:6d69e896ce38	8150	*
cparata	0:6d69e896ce38	8151	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8152	* @param val buffer the value of start address.
cparata	2:4d14e9edf37e	8153	*
cparata	2:4d14e9edf37e	8154	*/
cparata	2:4d14e9edf37e	8155	int32_t lsm6dso_fsm_start_address_get(lsm6dso_ctx_t ctx, uint16_t val)
cparata	2:4d14e9edf37e	8156	{
cparata	2:4d14e9edf37e	8157	int32_t ret;
cparata	2:4d14e9edf37e	8158	uint8_t add_l;
cparata	2:4d14e9edf37e	8159	uint8_t add_h;
cparata	2:4d14e9edf37e	8160
cparata	2:4d14e9edf37e	8161	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l);
cparata	2:4d14e9edf37e	8162	if (ret == 0) {
cparata	2:4d14e9edf37e	8163	ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h);
cparata	2:4d14e9edf37e	8164	*val = add_h;
cparata	2:4d14e9edf37e	8165	val = val << 8;
cparata	2:4d14e9edf37e	8166	*val += add_l;
cparata	0:6d69e896ce38	8167	}
cparata	0:6d69e896ce38	8168	return ret;
cparata	0:6d69e896ce38	8169	}
cparata	0:6d69e896ce38	8170
cparata	0:6d69e896ce38	8171	/**
cparata	0:6d69e896ce38	8172	* @}
cparata	0:6d69e896ce38	8173	*
cparata	0:6d69e896ce38	8174	*/
cparata	0:6d69e896ce38	8175
cparata	0:6d69e896ce38	8176	/**
cparata	0:6d69e896ce38	8177	* @defgroup LSM6DSO_Sensor_hub
cparata	0:6d69e896ce38	8178	* @brief This section groups all the functions that manage the
cparata	0:6d69e896ce38	8179	* sensor hub.
cparata	0:6d69e896ce38	8180	* @{
cparata	0:6d69e896ce38	8181	*
cparata	0:6d69e896ce38	8182	*/
cparata	0:6d69e896ce38	8183
cparata	0:6d69e896ce38	8184	/**
cparata	2:4d14e9edf37e	8185	* @brief Sensor hub output registers.[get]
cparata	2:4d14e9edf37e	8186	*
cparata	2:4d14e9edf37e	8187	* @param ctx read / write interface definitions
cparata	2:4d14e9edf37e	8188	* @param val values read from registers SENSOR_HUB_1 to SENSOR_HUB_18
cparata	2:4d14e9edf37e	8189	* @param len number of consecutive register to read (max 18)
cparata	2:4d14e9edf37e	8190	*
cparata	2:4d14e9edf37e	8191	*/
cparata	2:4d14e9edf37e	8192	int32_t lsm6dso_sh_read_data_raw_get(lsm6dso_ctx_t ctx, uint8_t val,
cparata	2:4d14e9edf37e	8193	uint8_t len)
cparata	0:6d69e896ce38	8194	{
cparata	0:6d69e896ce38	8195	int32_t ret;
cparata	0:6d69e896ce38	8196
cparata	0:6d69e896ce38	8197	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8198	if (ret == 0) {
cparata	2:4d14e9edf37e	8199	ret = lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t*) val, len);
cparata	0:6d69e896ce38	8200	}
cparata	0:6d69e896ce38	8201	if (ret == 0) {
cparata	0:6d69e896ce38	8202	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8203	}
cparata	0:6d69e896ce38	8204
cparata	0:6d69e896ce38	8205	return ret;
cparata	0:6d69e896ce38	8206	}
cparata	0:6d69e896ce38	8207
cparata	0:6d69e896ce38	8208	/**
cparata	0:6d69e896ce38	8209	* @brief Number of external sensors to be read by the sensor hub.[set]
cparata	0:6d69e896ce38	8210	*
cparata	0:6d69e896ce38	8211	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8212	* @param val change the values of aux_sens_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8213	*
cparata	0:6d69e896ce38	8214	*/
cparata	0:6d69e896ce38	8215	int32_t lsm6dso_sh_slave_connected_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8216	lsm6dso_aux_sens_on_t val)
cparata	0:6d69e896ce38	8217	{
cparata	0:6d69e896ce38	8218	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8219	int32_t ret;
cparata	0:6d69e896ce38	8220
cparata	0:6d69e896ce38	8221	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8222	if (ret == 0) {
cparata	0:6d69e896ce38	8223	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8224	}
cparata	0:6d69e896ce38	8225	if (ret == 0) {
cparata	0:6d69e896ce38	8226	reg.aux_sens_on = (uint8_t)val;
cparata	0:6d69e896ce38	8227	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8228	}
cparata	0:6d69e896ce38	8229	if (ret == 0) {
cparata	0:6d69e896ce38	8230	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8231	}
cparata	0:6d69e896ce38	8232	return ret;
cparata	0:6d69e896ce38	8233	}
cparata	0:6d69e896ce38	8234
cparata	0:6d69e896ce38	8235	/**
cparata	0:6d69e896ce38	8236	* @brief Number of external sensors to be read by the sensor hub.[get]
cparata	0:6d69e896ce38	8237	*
cparata	0:6d69e896ce38	8238	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8239	* @param val Get the values of aux_sens_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8240	*
cparata	0:6d69e896ce38	8241	*/
cparata	0:6d69e896ce38	8242	int32_t lsm6dso_sh_slave_connected_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8243	lsm6dso_aux_sens_on_t *val)
cparata	0:6d69e896ce38	8244	{
cparata	0:6d69e896ce38	8245	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8246	int32_t ret;
cparata	0:6d69e896ce38	8247
cparata	0:6d69e896ce38	8248	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8249	if (ret == 0) {
cparata	0:6d69e896ce38	8250	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8251	}
cparata	0:6d69e896ce38	8252	if (ret == 0) {
cparata	0:6d69e896ce38	8253	switch (reg.aux_sens_on) {
cparata	0:6d69e896ce38	8254	case LSM6DSO_SLV_0:
cparata	0:6d69e896ce38	8255	*val = LSM6DSO_SLV_0;
cparata	0:6d69e896ce38	8256	break;
cparata	0:6d69e896ce38	8257	case LSM6DSO_SLV_0_1:
cparata	0:6d69e896ce38	8258	*val = LSM6DSO_SLV_0_1;
cparata	0:6d69e896ce38	8259	break;
cparata	0:6d69e896ce38	8260	case LSM6DSO_SLV_0_1_2:
cparata	0:6d69e896ce38	8261	*val = LSM6DSO_SLV_0_1_2;
cparata	0:6d69e896ce38	8262	break;
cparata	0:6d69e896ce38	8263	case LSM6DSO_SLV_0_1_2_3:
cparata	0:6d69e896ce38	8264	*val = LSM6DSO_SLV_0_1_2_3;
cparata	0:6d69e896ce38	8265	break;
cparata	0:6d69e896ce38	8266	default:
cparata	0:6d69e896ce38	8267	*val = LSM6DSO_SLV_0;
cparata	0:6d69e896ce38	8268	break;
cparata	0:6d69e896ce38	8269	}
cparata	0:6d69e896ce38	8270	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8271	}
cparata	0:6d69e896ce38	8272
cparata	0:6d69e896ce38	8273	return ret;
cparata	0:6d69e896ce38	8274	}
cparata	0:6d69e896ce38	8275
cparata	0:6d69e896ce38	8276	/**
cparata	0:6d69e896ce38	8277	* @brief Sensor hub I2C master enable.[set]
cparata	0:6d69e896ce38	8278	*
cparata	0:6d69e896ce38	8279	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8280	* @param val change the values of master_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8281	*
cparata	0:6d69e896ce38	8282	*/
cparata	0:6d69e896ce38	8283	int32_t lsm6dso_sh_master_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	8284	{
cparata	0:6d69e896ce38	8285	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8286	int32_t ret;
cparata	0:6d69e896ce38	8287
cparata	0:6d69e896ce38	8288	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8289	if (ret == 0) {
cparata	0:6d69e896ce38	8290	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8291	}
cparata	0:6d69e896ce38	8292	if (ret == 0) {
cparata	0:6d69e896ce38	8293	reg.master_on = val;
cparata	0:6d69e896ce38	8294	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8295	}
cparata	0:6d69e896ce38	8296	if (ret == 0) {
cparata	0:6d69e896ce38	8297	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8298	}
cparata	0:6d69e896ce38	8299	return ret;
cparata	0:6d69e896ce38	8300	}
cparata	0:6d69e896ce38	8301
cparata	0:6d69e896ce38	8302	/**
cparata	0:6d69e896ce38	8303	* @brief Sensor hub I2C master enable.[get]
cparata	0:6d69e896ce38	8304	*
cparata	0:6d69e896ce38	8305	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8306	* @param val change the values of master_on in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8307	*
cparata	0:6d69e896ce38	8308	*/
cparata	0:6d69e896ce38	8309	int32_t lsm6dso_sh_master_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8310	{
cparata	0:6d69e896ce38	8311	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8312	int32_t ret;
cparata	0:6d69e896ce38	8313
cparata	0:6d69e896ce38	8314	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8315	if (ret == 0) {
cparata	0:6d69e896ce38	8316	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8317	}
cparata	0:6d69e896ce38	8318	if (ret == 0) {
cparata	0:6d69e896ce38	8319	*val = reg.master_on;
cparata	0:6d69e896ce38	8320	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8321	}
cparata	0:6d69e896ce38	8322
cparata	0:6d69e896ce38	8323	return ret;
cparata	0:6d69e896ce38	8324	}
cparata	0:6d69e896ce38	8325
cparata	0:6d69e896ce38	8326	/**
cparata	0:6d69e896ce38	8327	* @brief Master I2C pull-up enable.[set]
cparata	0:6d69e896ce38	8328	*
cparata	0:6d69e896ce38	8329	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8330	* @param val change the values of shub_pu_en in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8331	*
cparata	0:6d69e896ce38	8332	*/
cparata	0:6d69e896ce38	8333	int32_t lsm6dso_sh_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_pu_en_t val)
cparata	0:6d69e896ce38	8334	{
cparata	0:6d69e896ce38	8335	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8336	int32_t ret;
cparata	0:6d69e896ce38	8337
cparata	0:6d69e896ce38	8338	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8339	if (ret == 0) {
cparata	0:6d69e896ce38	8340	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8341	}
cparata	0:6d69e896ce38	8342	if (ret == 0) {
cparata	0:6d69e896ce38	8343	reg.shub_pu_en = (uint8_t)val;
cparata	0:6d69e896ce38	8344	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8345	}
cparata	0:6d69e896ce38	8346	if (ret == 0) {
cparata	0:6d69e896ce38	8347	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8348	}
cparata	0:6d69e896ce38	8349
cparata	0:6d69e896ce38	8350	return ret;
cparata	0:6d69e896ce38	8351	}
cparata	0:6d69e896ce38	8352
cparata	0:6d69e896ce38	8353	/**
cparata	0:6d69e896ce38	8354	* @brief Master I2C pull-up enable.[get]
cparata	0:6d69e896ce38	8355	*
cparata	0:6d69e896ce38	8356	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8357	* @param val Get the values of shub_pu_en in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8358	*
cparata	0:6d69e896ce38	8359	*/
cparata	0:6d69e896ce38	8360	int32_t lsm6dso_sh_pin_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8361	lsm6dso_shub_pu_en_t *val)
cparata	0:6d69e896ce38	8362	{
cparata	0:6d69e896ce38	8363	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8364	int32_t ret;
cparata	0:6d69e896ce38	8365
cparata	0:6d69e896ce38	8366	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8367	if (ret == 0) {
cparata	0:6d69e896ce38	8368	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8369	}
cparata	0:6d69e896ce38	8370	if (ret == 0) {
cparata	0:6d69e896ce38	8371	switch (reg.shub_pu_en) {
cparata	0:6d69e896ce38	8372	case LSM6DSO_EXT_PULL_UP:
cparata	0:6d69e896ce38	8373	*val = LSM6DSO_EXT_PULL_UP;
cparata	0:6d69e896ce38	8374	break;
cparata	0:6d69e896ce38	8375	case LSM6DSO_INTERNAL_PULL_UP:
cparata	0:6d69e896ce38	8376	*val = LSM6DSO_INTERNAL_PULL_UP;
cparata	0:6d69e896ce38	8377	break;
cparata	0:6d69e896ce38	8378	default:
cparata	0:6d69e896ce38	8379	*val = LSM6DSO_EXT_PULL_UP;
cparata	0:6d69e896ce38	8380	break;
cparata	0:6d69e896ce38	8381	}
cparata	0:6d69e896ce38	8382	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8383	}
cparata	0:6d69e896ce38	8384
cparata	0:6d69e896ce38	8385	return ret;
cparata	0:6d69e896ce38	8386	}
cparata	0:6d69e896ce38	8387
cparata	0:6d69e896ce38	8388	/**
cparata	0:6d69e896ce38	8389	* @brief I2C interface pass-through.[set]
cparata	0:6d69e896ce38	8390	*
cparata	0:6d69e896ce38	8391	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8392	* @param val change the values of pass_through_mode in
cparata	0:6d69e896ce38	8393	* reg MASTER_CONFIG
cparata	0:6d69e896ce38	8394	*
cparata	0:6d69e896ce38	8395	*/
cparata	0:6d69e896ce38	8396	int32_t lsm6dso_sh_pass_through_set(lsm6dso_ctx_t *ctx, uint8_t val)
cparata	0:6d69e896ce38	8397	{
cparata	0:6d69e896ce38	8398	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8399	int32_t ret;
cparata	0:6d69e896ce38	8400
cparata	0:6d69e896ce38	8401	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8402	if (ret == 0) {
cparata	0:6d69e896ce38	8403	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8404	}
cparata	0:6d69e896ce38	8405	if (ret == 0) {
cparata	0:6d69e896ce38	8406	reg.pass_through_mode = val;
cparata	0:6d69e896ce38	8407	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8408	}
cparata	0:6d69e896ce38	8409	if (ret == 0) {
cparata	0:6d69e896ce38	8410	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8411	}
cparata	0:6d69e896ce38	8412
cparata	0:6d69e896ce38	8413	return ret;
cparata	0:6d69e896ce38	8414	}
cparata	0:6d69e896ce38	8415
cparata	0:6d69e896ce38	8416	/**
cparata	0:6d69e896ce38	8417	* @brief I2C interface pass-through.[get]
cparata	0:6d69e896ce38	8418	*
cparata	0:6d69e896ce38	8419	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8420	* @param val change the values of pass_through_mode in
cparata	0:6d69e896ce38	8421	* reg MASTER_CONFIG
cparata	0:6d69e896ce38	8422	*
cparata	0:6d69e896ce38	8423	*/
cparata	0:6d69e896ce38	8424	int32_t lsm6dso_sh_pass_through_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8425	{
cparata	0:6d69e896ce38	8426	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8427	int32_t ret;
cparata	0:6d69e896ce38	8428
cparata	0:6d69e896ce38	8429	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8430	if (ret == 0) {
cparata	0:6d69e896ce38	8431	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8432	}
cparata	0:6d69e896ce38	8433	if (ret == 0) {
cparata	0:6d69e896ce38	8434	*val = reg.pass_through_mode;
cparata	0:6d69e896ce38	8435	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8436	}
cparata	0:6d69e896ce38	8437
cparata	0:6d69e896ce38	8438	return ret;
cparata	0:6d69e896ce38	8439	}
cparata	0:6d69e896ce38	8440
cparata	0:6d69e896ce38	8441	/**
cparata	0:6d69e896ce38	8442	* @brief Sensor hub trigger signal selection.[set]
cparata	0:6d69e896ce38	8443	*
cparata	0:6d69e896ce38	8444	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8445	* @param val change the values of start_config in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8446	*
cparata	0:6d69e896ce38	8447	*/
cparata	0:6d69e896ce38	8448	int32_t lsm6dso_sh_syncro_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8449	lsm6dso_start_config_t val)
cparata	0:6d69e896ce38	8450	{
cparata	0:6d69e896ce38	8451	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8452	int32_t ret;
cparata	0:6d69e896ce38	8453
cparata	0:6d69e896ce38	8454	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8455	if (ret == 0) {
cparata	0:6d69e896ce38	8456	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8457	}
cparata	0:6d69e896ce38	8458	if (ret == 0) {
cparata	0:6d69e896ce38	8459	reg.start_config = (uint8_t)val;
cparata	0:6d69e896ce38	8460	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8461	}
cparata	0:6d69e896ce38	8462	if (ret == 0) {
cparata	0:6d69e896ce38	8463	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8464	}
cparata	0:6d69e896ce38	8465
cparata	0:6d69e896ce38	8466	return ret;
cparata	0:6d69e896ce38	8467	}
cparata	0:6d69e896ce38	8468
cparata	0:6d69e896ce38	8469	/**
cparata	0:6d69e896ce38	8470	* @brief Sensor hub trigger signal selection.[get]
cparata	0:6d69e896ce38	8471	*
cparata	0:6d69e896ce38	8472	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8473	* @param val Get the values of start_config in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8474	*
cparata	0:6d69e896ce38	8475	*/
cparata	0:6d69e896ce38	8476	int32_t lsm6dso_sh_syncro_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8477	lsm6dso_start_config_t *val)
cparata	0:6d69e896ce38	8478	{
cparata	0:6d69e896ce38	8479	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8480	int32_t ret;
cparata	0:6d69e896ce38	8481
cparata	0:6d69e896ce38	8482	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8483	if (ret == 0) {
cparata	0:6d69e896ce38	8484	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8485	}
cparata	0:6d69e896ce38	8486	if (ret == 0) {
cparata	0:6d69e896ce38	8487	switch (reg.start_config) {
cparata	0:6d69e896ce38	8488	case LSM6DSO_EXT_ON_INT2_PIN:
cparata	0:6d69e896ce38	8489	*val = LSM6DSO_EXT_ON_INT2_PIN;
cparata	0:6d69e896ce38	8490	break;
cparata	0:6d69e896ce38	8491	case LSM6DSO_XL_GY_DRDY:
cparata	0:6d69e896ce38	8492	*val = LSM6DSO_XL_GY_DRDY;
cparata	0:6d69e896ce38	8493	break;
cparata	0:6d69e896ce38	8494	default:
cparata	0:6d69e896ce38	8495	*val = LSM6DSO_EXT_ON_INT2_PIN;
cparata	0:6d69e896ce38	8496	break;
cparata	0:6d69e896ce38	8497	}
cparata	0:6d69e896ce38	8498	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8499	}
cparata	0:6d69e896ce38	8500	return ret;
cparata	0:6d69e896ce38	8501	}
cparata	0:6d69e896ce38	8502
cparata	0:6d69e896ce38	8503	/**
cparata	0:6d69e896ce38	8504	* @brief Slave 0 write operation is performed only at the first
cparata	0:6d69e896ce38	8505	* sensor hub cycle.[set]
cparata	0:6d69e896ce38	8506	*
cparata	0:6d69e896ce38	8507	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8508	* @param val change the values of write_once in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8509	*
cparata	0:6d69e896ce38	8510	*/
cparata	0:6d69e896ce38	8511	int32_t lsm6dso_sh_write_mode_set(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8512	lsm6dso_write_once_t val)
cparata	0:6d69e896ce38	8513	{
cparata	0:6d69e896ce38	8514	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8515	int32_t ret;
cparata	0:6d69e896ce38	8516
cparata	0:6d69e896ce38	8517	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8518	if (ret == 0) {
cparata	0:6d69e896ce38	8519	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8520	}
cparata	0:6d69e896ce38	8521	if (ret == 0) {
cparata	0:6d69e896ce38	8522	reg.write_once = (uint8_t)val;
cparata	0:6d69e896ce38	8523	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8524	}
cparata	0:6d69e896ce38	8525	if (ret == 0) {
cparata	0:6d69e896ce38	8526	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8527	}
cparata	0:6d69e896ce38	8528
cparata	0:6d69e896ce38	8529	return ret;
cparata	0:6d69e896ce38	8530	}
cparata	0:6d69e896ce38	8531
cparata	0:6d69e896ce38	8532	/**
cparata	0:6d69e896ce38	8533	* @brief Slave 0 write operation is performed only at the first sensor
cparata	0:6d69e896ce38	8534	* hub cycle.[get]
cparata	0:6d69e896ce38	8535	*
cparata	0:6d69e896ce38	8536	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8537	* @param val Get the values of write_once in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8538	*
cparata	0:6d69e896ce38	8539	*/
cparata	0:6d69e896ce38	8540	int32_t lsm6dso_sh_write_mode_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8541	lsm6dso_write_once_t *val)
cparata	0:6d69e896ce38	8542	{
cparata	0:6d69e896ce38	8543	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8544	int32_t ret;
cparata	0:6d69e896ce38	8545
cparata	0:6d69e896ce38	8546	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8547	if (ret == 0) {
cparata	0:6d69e896ce38	8548	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8549	}
cparata	0:6d69e896ce38	8550	if (ret == 0) {
cparata	0:6d69e896ce38	8551	switch (reg.write_once) {
cparata	0:6d69e896ce38	8552	case LSM6DSO_EACH_SH_CYCLE:
cparata	0:6d69e896ce38	8553	*val = LSM6DSO_EACH_SH_CYCLE;
cparata	0:6d69e896ce38	8554	break;
cparata	0:6d69e896ce38	8555	case LSM6DSO_ONLY_FIRST_CYCLE:
cparata	0:6d69e896ce38	8556	*val = LSM6DSO_ONLY_FIRST_CYCLE;
cparata	0:6d69e896ce38	8557	break;
cparata	0:6d69e896ce38	8558	default:
cparata	0:6d69e896ce38	8559	*val = LSM6DSO_EACH_SH_CYCLE;
cparata	0:6d69e896ce38	8560	break;
cparata	0:6d69e896ce38	8561	}
cparata	0:6d69e896ce38	8562	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8563	}
cparata	0:6d69e896ce38	8564
cparata	0:6d69e896ce38	8565	return ret;
cparata	0:6d69e896ce38	8566	}
cparata	0:6d69e896ce38	8567
cparata	0:6d69e896ce38	8568	/**
cparata	0:6d69e896ce38	8569	* @brief Reset Master logic and output registers.[set]
cparata	0:6d69e896ce38	8570	*
cparata	0:6d69e896ce38	8571	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8572	*
cparata	0:6d69e896ce38	8573	*/
cparata	0:6d69e896ce38	8574	int32_t lsm6dso_sh_reset_set(lsm6dso_ctx_t *ctx)
cparata	0:6d69e896ce38	8575	{
cparata	0:6d69e896ce38	8576	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8577	int32_t ret;
cparata	0:6d69e896ce38	8578
cparata	0:6d69e896ce38	8579	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8580	if (ret == 0) {
cparata	0:6d69e896ce38	8581	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8582	}
cparata	0:6d69e896ce38	8583	if (ret == 0) {
cparata	0:6d69e896ce38	8584	reg.rst_master_regs = PROPERTY_ENABLE;
cparata	0:6d69e896ce38	8585	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8586	}
cparata	0:6d69e896ce38	8587	if (ret == 0) {
cparata	0:6d69e896ce38	8588	reg.rst_master_regs = PROPERTY_DISABLE;
cparata	0:6d69e896ce38	8589	ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8590	}
cparata	0:6d69e896ce38	8591	if (ret == 0) {
cparata	0:6d69e896ce38	8592	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8593	}
cparata	0:6d69e896ce38	8594
cparata	0:6d69e896ce38	8595	return ret;
cparata	0:6d69e896ce38	8596	}
cparata	0:6d69e896ce38	8597
cparata	0:6d69e896ce38	8598	/**
cparata	0:6d69e896ce38	8599	* @brief Reset Master logic and output registers.[get]
cparata	0:6d69e896ce38	8600	*
cparata	0:6d69e896ce38	8601	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8602	* @param val change the values of rst_master_regs in reg MASTER_CONFIG
cparata	0:6d69e896ce38	8603	*
cparata	0:6d69e896ce38	8604	*/
cparata	0:6d69e896ce38	8605	int32_t lsm6dso_sh_reset_get(lsm6dso_ctx_t ctx, uint8_t val)
cparata	0:6d69e896ce38	8606	{
cparata	0:6d69e896ce38	8607	lsm6dso_master_config_t reg;
cparata	0:6d69e896ce38	8608	int32_t ret;
cparata	0:6d69e896ce38	8609
cparata	0:6d69e896ce38	8610	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8611	if (ret == 0) {
cparata	0:6d69e896ce38	8612	ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8613	}
cparata	0:6d69e896ce38	8614	if (ret == 0) {
cparata	0:6d69e896ce38	8615	*val = reg.rst_master_regs;
cparata	0:6d69e896ce38	8616	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8617	}
cparata	0:6d69e896ce38	8618	return ret;
cparata	0:6d69e896ce38	8619	}
cparata	0:6d69e896ce38	8620
cparata	0:6d69e896ce38	8621	/**
cparata	0:6d69e896ce38	8622	* @brief Rate at which the master communicates.[set]
cparata	0:6d69e896ce38	8623	*
cparata	0:6d69e896ce38	8624	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8625	* @param val change the values of shub_odr in reg slv1_CONFIG
cparata	0:6d69e896ce38	8626	*
cparata	0:6d69e896ce38	8627	*/
cparata	0:6d69e896ce38	8628	int32_t lsm6dso_sh_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_odr_t val)
cparata	0:6d69e896ce38	8629	{
cparata	0:6d69e896ce38	8630	lsm6dso_slv0_config_t reg;
cparata	0:6d69e896ce38	8631	int32_t ret;
cparata	0:6d69e896ce38	8632
cparata	0:6d69e896ce38	8633	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8634	if (ret == 0) {
cparata	0:6d69e896ce38	8635	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8636	}
cparata	0:6d69e896ce38	8637	if (ret == 0) {
cparata	0:6d69e896ce38	8638	reg.shub_odr = (uint8_t)val;
cparata	0:6d69e896ce38	8639	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8640	}
cparata	0:6d69e896ce38	8641	if (ret == 0) {
cparata	0:6d69e896ce38	8642	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8643	}
cparata	0:6d69e896ce38	8644
cparata	0:6d69e896ce38	8645	return ret;
cparata	0:6d69e896ce38	8646	}
cparata	0:6d69e896ce38	8647
cparata	0:6d69e896ce38	8648	/**
cparata	0:6d69e896ce38	8649	* @brief Rate at which the master communicates.[get]
cparata	0:6d69e896ce38	8650	*
cparata	0:6d69e896ce38	8651	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8652	* @param val Get the values of shub_odr in reg slv1_CONFIG
cparata	0:6d69e896ce38	8653	*
cparata	0:6d69e896ce38	8654	*/
cparata	0:6d69e896ce38	8655	int32_t lsm6dso_sh_data_rate_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8656	lsm6dso_shub_odr_t *val)
cparata	0:6d69e896ce38	8657	{
cparata	0:6d69e896ce38	8658	lsm6dso_slv0_config_t reg;
cparata	0:6d69e896ce38	8659	int32_t ret;
cparata	0:6d69e896ce38	8660
cparata	0:6d69e896ce38	8661	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8662	if (ret == 0) {
cparata	0:6d69e896ce38	8663	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8664	}
cparata	0:6d69e896ce38	8665	if (ret == 0) {
cparata	0:6d69e896ce38	8666	switch (reg.shub_odr) {
cparata	0:6d69e896ce38	8667	case LSM6DSO_SH_ODR_104Hz:
cparata	0:6d69e896ce38	8668	*val = LSM6DSO_SH_ODR_104Hz;
cparata	0:6d69e896ce38	8669	break;
cparata	0:6d69e896ce38	8670	case LSM6DSO_SH_ODR_52Hz:
cparata	0:6d69e896ce38	8671	*val = LSM6DSO_SH_ODR_52Hz;
cparata	0:6d69e896ce38	8672	break;
cparata	0:6d69e896ce38	8673	case LSM6DSO_SH_ODR_26Hz:
cparata	0:6d69e896ce38	8674	*val = LSM6DSO_SH_ODR_26Hz;
cparata	0:6d69e896ce38	8675	break;
cparata	0:6d69e896ce38	8676	case LSM6DSO_SH_ODR_13Hz:
cparata	0:6d69e896ce38	8677	*val = LSM6DSO_SH_ODR_13Hz;
cparata	0:6d69e896ce38	8678	break;
cparata	0:6d69e896ce38	8679	default:
cparata	0:6d69e896ce38	8680	*val = LSM6DSO_SH_ODR_104Hz;
cparata	0:6d69e896ce38	8681	break;
cparata	0:6d69e896ce38	8682	}
cparata	0:6d69e896ce38	8683	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8684	}
cparata	0:6d69e896ce38	8685
cparata	0:6d69e896ce38	8686	return ret;
cparata	0:6d69e896ce38	8687	}
cparata	0:6d69e896ce38	8688
cparata	0:6d69e896ce38	8689	/**
cparata	0:6d69e896ce38	8690	* @brief Configure slave 0 for perform a write.[set]
cparata	0:6d69e896ce38	8691	*
cparata	0:6d69e896ce38	8692	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8693	* @param val a structure that contain
cparata	0:6d69e896ce38	8694	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8695	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8696	* - uint8_t slv1_data; 8 bit data to write
cparata	0:6d69e896ce38	8697	*
cparata	0:6d69e896ce38	8698	*/
cparata	0:6d69e896ce38	8699	int32_t lsm6dso_sh_cfg_write(lsm6dso_ctx_t ctx, lsm6dso_sh_cfg_write_t val)
cparata	0:6d69e896ce38	8700	{
cparata	0:6d69e896ce38	8701	lsm6dso_slv0_add_t reg;
cparata	0:6d69e896ce38	8702	int32_t ret;
cparata	0:6d69e896ce38	8703
cparata	0:6d69e896ce38	8704	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8705	if (ret == 0) {
cparata	0:6d69e896ce38	8706	reg.slave0 = val->slv0_add;
cparata	0:6d69e896ce38	8707	reg.rw_0 = 0;
cparata	0:6d69e896ce38	8708	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t*)&reg, 1);
cparata	0:6d69e896ce38	8709	}
cparata	0:6d69e896ce38	8710	if (ret == 0) {
cparata	0:6d69e896ce38	8711	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
cparata	0:6d69e896ce38	8712	&(val->slv0_subadd), 1);
cparata	0:6d69e896ce38	8713	}
cparata	0:6d69e896ce38	8714	if (ret == 0) {
cparata	0:6d69e896ce38	8715	ret = lsm6dso_write_reg(ctx, LSM6DSO_DATAWRITE_SLV0,
cparata	0:6d69e896ce38	8716	&(val->slv0_data), 1);
cparata	0:6d69e896ce38	8717	}
cparata	0:6d69e896ce38	8718	if (ret == 0) {
cparata	0:6d69e896ce38	8719	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8720	}
cparata	0:6d69e896ce38	8721	return ret;
cparata	0:6d69e896ce38	8722	}
cparata	0:6d69e896ce38	8723
cparata	0:6d69e896ce38	8724	/**
cparata	0:6d69e896ce38	8725	* @brief Configure slave 0 for perform a read.[set]
cparata	0:6d69e896ce38	8726	*
cparata	0:6d69e896ce38	8727	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8728	* @param val Structure that contain
cparata	0:6d69e896ce38	8729	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8730	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8731	* - uint8_t slv1_len; num of bit to read
cparata	0:6d69e896ce38	8732	*
cparata	0:6d69e896ce38	8733	*/
cparata	0:6d69e896ce38	8734	int32_t lsm6dso_sh_slv0_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8735	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8736	{
cparata	0:6d69e896ce38	8737	lsm6dso_slv0_add_t slv0_add;
cparata	0:6d69e896ce38	8738	lsm6dso_slv0_config_t slv0_config;
cparata	0:6d69e896ce38	8739	int32_t ret;
cparata	0:6d69e896ce38	8740
cparata	0:6d69e896ce38	8741	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8742	if (ret == 0) {
cparata	0:6d69e896ce38	8743	slv0_add.slave0 = val->slv_add;
cparata	0:6d69e896ce38	8744	slv0_add.rw_0 = 1;
cparata	0:6d69e896ce38	8745	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t*)&slv0_add, 1);
cparata	0:6d69e896ce38	8746	}
cparata	0:6d69e896ce38	8747	if (ret == 0) {
cparata	0:6d69e896ce38	8748	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
cparata	0:6d69e896ce38	8749	&(val->slv_subadd), 1);
cparata	0:6d69e896ce38	8750	}
cparata	0:6d69e896ce38	8751	if (ret == 0) {
cparata	0:6d69e896ce38	8752	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG,
cparata	0:6d69e896ce38	8753	(uint8_t*)&slv0_config, 1);
cparata	0:6d69e896ce38	8754	}
cparata	0:6d69e896ce38	8755	if (ret == 0) {
cparata	0:6d69e896ce38	8756	slv0_config.slave0_numop = val->slv_len;
cparata	0:6d69e896ce38	8757	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG,
cparata	0:6d69e896ce38	8758	(uint8_t*)&slv0_config, 1);
cparata	0:6d69e896ce38	8759	}
cparata	0:6d69e896ce38	8760	if (ret == 0) {
cparata	0:6d69e896ce38	8761	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8762	}
cparata	0:6d69e896ce38	8763
cparata	0:6d69e896ce38	8764	return ret;
cparata	0:6d69e896ce38	8765	}
cparata	0:6d69e896ce38	8766
cparata	0:6d69e896ce38	8767	/**
cparata	0:6d69e896ce38	8768	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:6d69e896ce38	8769	*
cparata	0:6d69e896ce38	8770	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8771	* @param val Structure that contain
cparata	0:6d69e896ce38	8772	* - uint8_t slv1_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8773	* - uint8_t slv1_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8774	* - uint8_t slv1_len; num of bit to read
cparata	0:6d69e896ce38	8775	*
cparata	0:6d69e896ce38	8776	*/
cparata	0:6d69e896ce38	8777	int32_t lsm6dso_sh_slv1_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8778	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8779	{
cparata	0:6d69e896ce38	8780	lsm6dso_slv1_add_t slv1_add;
cparata	0:6d69e896ce38	8781	lsm6dso_slv1_config_t slv1_config;
cparata	0:6d69e896ce38	8782	int32_t ret;
cparata	0:6d69e896ce38	8783
cparata	0:6d69e896ce38	8784	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8785	if (ret == 0) {
cparata	0:6d69e896ce38	8786	slv1_add.slave1_add = val->slv_add;
cparata	0:6d69e896ce38	8787	slv1_add.r_1 = 1;
cparata	0:6d69e896ce38	8788	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_ADD, (uint8_t*)&slv1_add, 1);
cparata	0:6d69e896ce38	8789	}
cparata	0:6d69e896ce38	8790	if (ret == 0) {
cparata	0:6d69e896ce38	8791	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_SUBADD,
cparata	0:6d69e896ce38	8792	&(val->slv_subadd), 1);
cparata	0:6d69e896ce38	8793	}
cparata	0:6d69e896ce38	8794	if (ret == 0) {
cparata	0:6d69e896ce38	8795	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG,
cparata	0:6d69e896ce38	8796	(uint8_t*)&slv1_config, 1);
cparata	0:6d69e896ce38	8797	}
cparata	0:6d69e896ce38	8798	if (ret == 0) {
cparata	0:6d69e896ce38	8799	slv1_config.slave1_numop = val->slv_len;
cparata	0:6d69e896ce38	8800	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG,
cparata	0:6d69e896ce38	8801	(uint8_t*)&slv1_config, 1);
cparata	0:6d69e896ce38	8802	}
cparata	0:6d69e896ce38	8803	if (ret == 0) {
cparata	0:6d69e896ce38	8804	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8805	}
cparata	0:6d69e896ce38	8806
cparata	0:6d69e896ce38	8807	return ret;
cparata	0:6d69e896ce38	8808	}
cparata	0:6d69e896ce38	8809
cparata	0:6d69e896ce38	8810	/**
cparata	0:6d69e896ce38	8811	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:6d69e896ce38	8812	*
cparata	0:6d69e896ce38	8813	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8814	* @param val Structure that contain
cparata	0:6d69e896ce38	8815	* - uint8_t slv2_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8816	* - uint8_t slv2_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8817	* - uint8_t slv2_len; num of bit to read
cparata	0:6d69e896ce38	8818	*
cparata	0:6d69e896ce38	8819	*/
cparata	0:6d69e896ce38	8820	int32_t lsm6dso_sh_slv2_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8821	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8822	{
cparata	0:6d69e896ce38	8823	lsm6dso_slv2_add_t slv2_add;
cparata	0:6d69e896ce38	8824	lsm6dso_slv2_config_t slv2_config;
cparata	0:6d69e896ce38	8825	int32_t ret;
cparata	0:6d69e896ce38	8826
cparata	0:6d69e896ce38	8827	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8828	if (ret == 0) {
cparata	0:6d69e896ce38	8829	slv2_add.slave2_add = val->slv_add;
cparata	0:6d69e896ce38	8830	slv2_add.r_2 = 1;
cparata	0:6d69e896ce38	8831	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_ADD, (uint8_t*)&slv2_add, 1);
cparata	0:6d69e896ce38	8832	}
cparata	0:6d69e896ce38	8833	if (ret == 0) {
cparata	0:6d69e896ce38	8834	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_SUBADD,
cparata	0:6d69e896ce38	8835	&(val->slv_subadd), 1);
cparata	0:6d69e896ce38	8836	}
cparata	0:6d69e896ce38	8837	if (ret == 0) {
cparata	0:6d69e896ce38	8838	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG,
cparata	0:6d69e896ce38	8839	(uint8_t*)&slv2_config, 1);
cparata	0:6d69e896ce38	8840	}
cparata	0:6d69e896ce38	8841	if (ret == 0) {
cparata	0:6d69e896ce38	8842	slv2_config.slave2_numop = val->slv_len;
cparata	0:6d69e896ce38	8843	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG,
cparata	0:6d69e896ce38	8844	(uint8_t*)&slv2_config, 1);
cparata	0:6d69e896ce38	8845	}
cparata	0:6d69e896ce38	8846	if (ret == 0) {
cparata	0:6d69e896ce38	8847	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8848	}
cparata	0:6d69e896ce38	8849	return ret;
cparata	0:6d69e896ce38	8850	}
cparata	0:6d69e896ce38	8851
cparata	0:6d69e896ce38	8852	/**
cparata	0:6d69e896ce38	8853	* @brief Configure slave 0 for perform a write/read.[set]
cparata	0:6d69e896ce38	8854	*
cparata	0:6d69e896ce38	8855	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8856	* @param val Structure that contain
cparata	0:6d69e896ce38	8857	* - uint8_t slv3_add; 8 bit i2c device address
cparata	0:6d69e896ce38	8858	* - uint8_t slv3_subadd; 8 bit register device address
cparata	0:6d69e896ce38	8859	* - uint8_t slv3_len; num of bit to read
cparata	0:6d69e896ce38	8860	*
cparata	0:6d69e896ce38	8861	*/
cparata	0:6d69e896ce38	8862	int32_t lsm6dso_sh_slv3_cfg_read(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8863	lsm6dso_sh_cfg_read_t *val)
cparata	0:6d69e896ce38	8864	{
cparata	0:6d69e896ce38	8865	lsm6dso_slv3_add_t slv3_add;
cparata	0:6d69e896ce38	8866	lsm6dso_slv3_config_t slv3_config;
cparata	0:6d69e896ce38	8867	int32_t ret;
cparata	0:6d69e896ce38	8868
cparata	0:6d69e896ce38	8869	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8870	if (ret == 0) {
cparata	0:6d69e896ce38	8871	slv3_add.slave3_add = val->slv_add;
cparata	0:6d69e896ce38	8872	slv3_add.r_3 = 1;
cparata	0:6d69e896ce38	8873	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_ADD, (uint8_t*)&slv3_add, 1);
cparata	0:6d69e896ce38	8874	}
cparata	0:6d69e896ce38	8875	if (ret == 0) {
cparata	0:6d69e896ce38	8876	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_SUBADD,
cparata	0:6d69e896ce38	8877	&(val->slv_subadd), 1);
cparata	0:6d69e896ce38	8878	}
cparata	0:6d69e896ce38	8879	if (ret == 0) {
cparata	0:6d69e896ce38	8880	ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG,
cparata	0:6d69e896ce38	8881	(uint8_t*)&slv3_config, 1);
cparata	0:6d69e896ce38	8882	}
cparata	0:6d69e896ce38	8883	if (ret == 0) {
cparata	0:6d69e896ce38	8884	slv3_config.slave3_numop = val->slv_len;
cparata	0:6d69e896ce38	8885	ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG,
cparata	0:6d69e896ce38	8886	(uint8_t*)&slv3_config, 1);
cparata	0:6d69e896ce38	8887	}
cparata	0:6d69e896ce38	8888	if (ret == 0) {
cparata	0:6d69e896ce38	8889	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8890	}
cparata	0:6d69e896ce38	8891	return ret;
cparata	0:6d69e896ce38	8892	}
cparata	0:6d69e896ce38	8893
cparata	0:6d69e896ce38	8894	/**
cparata	0:6d69e896ce38	8895	* @brief Sensor hub source register.[get]
cparata	0:6d69e896ce38	8896	*
cparata	0:6d69e896ce38	8897	* @param ctx read / write interface definitions
cparata	0:6d69e896ce38	8898	* @param val union of registers from STATUS_MASTER to
cparata	0:6d69e896ce38	8899	*
cparata	0:6d69e896ce38	8900	*/
cparata	0:6d69e896ce38	8901	int32_t lsm6dso_sh_status_get(lsm6dso_ctx_t *ctx,
cparata	0:6d69e896ce38	8902	lsm6dso_status_master_t *val)
cparata	0:6d69e896ce38	8903	{
cparata	0:6d69e896ce38	8904	int32_t ret;
cparata	0:6d69e896ce38	8905
cparata	0:6d69e896ce38	8906	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
cparata	0:6d69e896ce38	8907	if (ret == 0) {
cparata	0:6d69e896ce38	8908	ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER, (uint8_t*) val, 1);
cparata	0:6d69e896ce38	8909	}
cparata	0:6d69e896ce38	8910	if (ret == 0) {
cparata	0:6d69e896ce38	8911	ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
cparata	0:6d69e896ce38	8912	}
cparata	0:6d69e896ce38	8913
cparata	0:6d69e896ce38	8914	return ret;
cparata	0:6d69e896ce38	8915	}
cparata	0:6d69e896ce38	8916
cparata	0:6d69e896ce38	8917	/**
cparata	0:6d69e896ce38	8918	* @}
cparata	0:6d69e896ce38	8919	*
cparata	0:6d69e896ce38	8920	*/
cparata	0:6d69e896ce38	8921
cparata	0:6d69e896ce38	8922	/**
cparata	0:6d69e896ce38	8923	* @}
cparata	0:6d69e896ce38	8924	*
cparata	0:6d69e896ce38	8925	*/
cparata	0:6d69e896ce38	8926
cparata	0:6d69e896ce38	8927	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	07 Mar 2019
Imports:	15
Forks:	0
Commits:	7
Dependents:	2
Dependencies:	2
Followers:	402

The code in this repository is Apache licensed.

lsm6dso_reg.c@2:4d14e9edf37e, 2019-06-03 (annotated)

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