Dependencies: X_NUCLEO_COMMON ST_INTERFACES
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LSM6DSL_acc_gyro_driver.h
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00001 /** 00002 ****************************************************************************** 00003 * @file LSM6DSL_acc_gyro_driver.h 00004 * @author MEMS Application Team 00005 * @version V1.5 00006 * @date 17-May-2016 00007 * @brief LSM6DSL header driver file 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __LSM6DSL_ACC_GYRO_DRIVER__H 00040 #define __LSM6DSL_ACC_GYRO_DRIVER__H 00041 00042 /* Includes ------------------------------------------------------------------*/ 00043 #include <stdint.h> 00044 /* Exported types ------------------------------------------------------------*/ 00045 00046 #ifdef __cplusplus 00047 extern "C" { 00048 #endif 00049 00050 //these could change accordingly with the architecture 00051 00052 #ifndef __ARCHDEP__TYPES 00053 #define __ARCHDEP__TYPES 00054 00055 typedef unsigned char u8_t; 00056 typedef unsigned short int u16_t; 00057 typedef unsigned int u32_t; 00058 typedef int i32_t; 00059 typedef short int i16_t; 00060 typedef signed char i8_t; 00061 00062 #endif /*__ARCHDEP__TYPES*/ 00063 00064 /* Exported common structure --------------------------------------------------------*/ 00065 00066 #ifndef __SHARED__TYPES 00067 #define __SHARED__TYPES 00068 00069 typedef union{ 00070 i16_t i16bit[3]; 00071 u8_t u8bit[6]; 00072 } Type3Axis16bit_U; 00073 00074 typedef union{ 00075 i16_t i16bit; 00076 u8_t u8bit[2]; 00077 } Type1Axis16bit_U; 00078 00079 typedef union{ 00080 i32_t i32bit; 00081 u8_t u8bit[4]; 00082 } Type1Axis32bit_U; 00083 00084 typedef enum { 00085 MEMS_SUCCESS = 0x01, 00086 MEMS_ERROR = 0x00 00087 } mems_status_t; 00088 00089 #endif /*__SHARED__TYPES*/ 00090 00091 /* Exported macro ------------------------------------------------------------*/ 00092 00093 /* Exported constants --------------------------------------------------------*/ 00094 00095 /************** I2C Address *****************/ 00096 00097 #define LSM6DSL_ACC_GYRO_I2C_ADDRESS_LOW 0xD4 // SAD[0] = 0 00098 #define LSM6DSL_ACC_GYRO_I2C_ADDRESS_HIGH 0xD6 // SAD[0] = 1 00099 00100 /************** Who am I *******************/ 00101 00102 #define LSM6DSL_ACC_GYRO_WHO_AM_I 0x6A 00103 00104 /************** Device Register *******************/ 00105 00106 #define LSM6DSL_ACC_GYRO_FUNC_CFG_ACCESS 0X01 00107 00108 #define LSM6DSL_ACC_GYRO_SENSOR_SYNC_TIME 0X04 00109 #define LSM6DSL_ACC_GYRO_SENSOR_RES_RATIO 0X05 00110 00111 #define LSM6DSL_ACC_GYRO_FIFO_CTRL1 0X06 00112 #define LSM6DSL_ACC_GYRO_FIFO_CTRL2 0X07 00113 #define LSM6DSL_ACC_GYRO_FIFO_CTRL3 0X08 00114 #define LSM6DSL_ACC_GYRO_FIFO_CTRL4 0X09 00115 #define LSM6DSL_ACC_GYRO_FIFO_CTRL5 0X0A 00116 00117 #define LSM6DSL_ACC_GYRO_DRDY_PULSE_CFG_G 0X0B 00118 #define LSM6DSL_ACC_GYRO_INT1_CTRL 0X0D 00119 #define LSM6DSL_ACC_GYRO_INT2_CTRL 0X0E 00120 #define LSM6DSL_ACC_GYRO_WHO_AM_I_REG 0X0F 00121 #define LSM6DSL_ACC_GYRO_CTRL1_XL 0X10 00122 #define LSM6DSL_ACC_GYRO_CTRL2_G 0X11 00123 #define LSM6DSL_ACC_GYRO_CTRL3_C 0X12 00124 #define LSM6DSL_ACC_GYRO_CTRL4_C 0X13 00125 #define LSM6DSL_ACC_GYRO_CTRL5_C 0X14 00126 #define LSM6DSL_ACC_GYRO_CTRL6_G 0X15 00127 #define LSM6DSL_ACC_GYRO_CTRL7_G 0X16 00128 #define LSM6DSL_ACC_GYRO_CTRL8_XL 0X17 00129 #define LSM6DSL_ACC_GYRO_CTRL9_XL 0X18 00130 #define LSM6DSL_ACC_GYRO_CTRL10_C 0X19 00131 00132 #define LSM6DSL_ACC_GYRO_MASTER_CONFIG 0X1A 00133 #define LSM6DSL_ACC_GYRO_WAKE_UP_SRC 0X1B 00134 #define LSM6DSL_ACC_GYRO_TAP_SRC 0X1C 00135 #define LSM6DSL_ACC_GYRO_D6D_SRC 0X1D 00136 #define LSM6DSL_ACC_GYRO_STATUS_REG 0X1E 00137 00138 #define LSM6DSL_ACC_GYRO_OUT_TEMP_L 0X20 00139 #define LSM6DSL_ACC_GYRO_OUT_TEMP_H 0X21 00140 #define LSM6DSL_ACC_GYRO_OUTX_L_G 0X22 00141 #define LSM6DSL_ACC_GYRO_OUTX_H_G 0X23 00142 #define LSM6DSL_ACC_GYRO_OUTY_L_G 0X24 00143 #define LSM6DSL_ACC_GYRO_OUTY_H_G 0X25 00144 #define LSM6DSL_ACC_GYRO_OUTZ_L_G 0X26 00145 #define LSM6DSL_ACC_GYRO_OUTZ_H_G 0X27 00146 #define LSM6DSL_ACC_GYRO_OUTX_L_XL 0X28 00147 #define LSM6DSL_ACC_GYRO_OUTX_H_XL 0X29 00148 #define LSM6DSL_ACC_GYRO_OUTY_L_XL 0X2A 00149 #define LSM6DSL_ACC_GYRO_OUTY_H_XL 0X2B 00150 #define LSM6DSL_ACC_GYRO_OUTZ_L_XL 0X2C 00151 #define LSM6DSL_ACC_GYRO_OUTZ_H_XL 0X2D 00152 #define LSM6DSL_ACC_GYRO_SENSORHUB1_REG 0X2E 00153 #define LSM6DSL_ACC_GYRO_SENSORHUB2_REG 0X2F 00154 #define LSM6DSL_ACC_GYRO_SENSORHUB3_REG 0X30 00155 #define LSM6DSL_ACC_GYRO_SENSORHUB4_REG 0X31 00156 #define LSM6DSL_ACC_GYRO_SENSORHUB5_REG 0X32 00157 #define LSM6DSL_ACC_GYRO_SENSORHUB6_REG 0X33 00158 #define LSM6DSL_ACC_GYRO_SENSORHUB7_REG 0X34 00159 #define LSM6DSL_ACC_GYRO_SENSORHUB8_REG 0X35 00160 #define LSM6DSL_ACC_GYRO_SENSORHUB9_REG 0X36 00161 #define LSM6DSL_ACC_GYRO_SENSORHUB10_REG 0X37 00162 #define LSM6DSL_ACC_GYRO_SENSORHUB11_REG 0X38 00163 #define LSM6DSL_ACC_GYRO_SENSORHUB12_REG 0X39 00164 #define LSM6DSL_ACC_GYRO_FIFO_STATUS1 0X3A 00165 #define LSM6DSL_ACC_GYRO_FIFO_STATUS2 0X3B 00166 #define LSM6DSL_ACC_GYRO_FIFO_STATUS3 0X3C 00167 #define LSM6DSL_ACC_GYRO_FIFO_STATUS4 0X3D 00168 #define LSM6DSL_ACC_GYRO_FIFO_DATA_OUT_L 0X3E 00169 #define LSM6DSL_ACC_GYRO_FIFO_DATA_OUT_H 0X3F 00170 #define LSM6DSL_ACC_GYRO_TIMESTAMP0_REG 0X40 00171 #define LSM6DSL_ACC_GYRO_TIMESTAMP1_REG 0X41 00172 #define LSM6DSL_ACC_GYRO_TIMESTAMP2_REG 0X42 00173 00174 #define LSM6DSL_ACC_GYRO_TIMESTAMP_L 0X49 00175 #define LSM6DSL_ACC_GYRO_TIMESTAMP_H 0X4A 00176 00177 #define LSM6DSL_ACC_GYRO_STEP_COUNTER_L 0X4B 00178 #define LSM6DSL_ACC_GYRO_STEP_COUNTER_H 0X4C 00179 00180 #define LSM6DSL_ACC_GYRO_SENSORHUB13_REG 0X4D 00181 #define LSM6DSL_ACC_GYRO_SENSORHUB14_REG 0X4E 00182 #define LSM6DSL_ACC_GYRO_SENSORHUB15_REG 0X4F 00183 #define LSM6DSL_ACC_GYRO_SENSORHUB16_REG 0X50 00184 #define LSM6DSL_ACC_GYRO_SENSORHUB17_REG 0X51 00185 #define LSM6DSL_ACC_GYRO_SENSORHUB18_REG 0X52 00186 00187 #define LSM6DSL_ACC_GYRO_FUNC_SRC 0X53 00188 #define LSM6DSL_ACC_GYRO_TAP_CFG1 0X58 00189 #define LSM6DSL_ACC_GYRO_TAP_THS_6D 0X59 00190 #define LSM6DSL_ACC_GYRO_INT_DUR2 0X5A 00191 #define LSM6DSL_ACC_GYRO_WAKE_UP_THS 0X5B 00192 #define LSM6DSL_ACC_GYRO_WAKE_UP_DUR 0X5C 00193 #define LSM6DSL_ACC_GYRO_FREE_FALL 0X5D 00194 #define LSM6DSL_ACC_GYRO_MD1_CFG 0X5E 00195 #define LSM6DSL_ACC_GYRO_MD2_CFG 0X5F 00196 00197 #define LSM6DSL_ACC_GYRO_OUT_MAG_RAW_X_L 0X66 00198 #define LSM6DSL_ACC_GYRO_OUT_MAG_RAW_X_H 0X67 00199 #define LSM6DSL_ACC_GYRO_OUT_MAG_RAW_Y_L 0X68 00200 #define LSM6DSL_ACC_GYRO_OUT_MAG_RAW_Y_H 0X69 00201 #define LSM6DSL_ACC_GYRO_OUT_MAG_RAW_Z_L 0X6A 00202 #define LSM6DSL_ACC_GYRO_OUT_MAG_RAW_Z_H 0X6B 00203 00204 #define LSM6DSL_ACC_GYRO_X_OFS_USR 0X73 00205 #define LSM6DSL_ACC_GYRO_Y_OFS_USR 0X74 00206 #define LSM6DSL_ACC_GYRO_Z_OFS_USR 0X75 00207 00208 /************** Embedded functions register mapping *******************/ 00209 #define LSM6DSL_ACC_GYRO_SLV0_ADD 0x02 00210 #define LSM6DSL_ACC_GYRO_SLV0_SUBADD 0x03 00211 #define LSM6DSL_ACC_GYRO_SLAVE0_CONFIG 0x04 00212 #define LSM6DSL_ACC_GYRO_SLV1_ADD 0x05 00213 #define LSM6DSL_ACC_GYRO_SLV1_SUBADD 0x06 00214 #define LSM6DSL_ACC_GYRO_SLAVE1_CONFIG 0x07 00215 #define LSM6DSL_ACC_GYRO_SLV2_ADD 0x08 00216 #define LSM6DSL_ACC_GYRO_SLV2_SUBADD 0x09 00217 #define LSM6DSL_ACC_GYRO_SLAVE2_CONFIG 0x0A 00218 #define LSM6DSL_ACC_GYRO_SLV3_ADD 0x0B 00219 #define LSM6DSL_ACC_GYRO_SLV3_SUBADD 0x0C 00220 #define LSM6DSL_ACC_GYRO_SLAVE3_CONFIG 0x0D 00221 #define LSM6DSL_ACC_GYRO_DATAWRITE_SRC_MODE_SUB_SLV0 0x0E 00222 #define LSM6DSL_ACC_GYRO_CONFIG_PEDO_THS_MIN 0x0F 00223 00224 #define LSM6DSL_ACC_GYRO_SM_STEP_THS 0x13 00225 #define LSM6DSL_ACC_GYRO_PEDO_DEB_REG 0x14 00226 #define LSM6DSL_ACC_GYRO_STEP_COUNT_DELTA 0x15 00227 00228 #define LSM6DSL_ACC_GYRO_MAG_SI_XX 0x24 00229 #define LSM6DSL_ACC_GYRO_MAG_SI_XY 0x25 00230 #define LSM6DSL_ACC_GYRO_MAG_SI_XZ 0x26 00231 #define LSM6DSL_ACC_GYRO_MAG_SI_YX 0x27 00232 #define LSM6DSL_ACC_GYRO_MAG_SI_YY 0x28 00233 #define LSM6DSL_ACC_GYRO_MAG_SI_YZ 0x29 00234 #define LSM6DSL_ACC_GYRO_MAG_SI_ZX 0x2A 00235 #define LSM6DSL_ACC_GYRO_MAG_SI_ZY 0x2B 00236 #define LSM6DSL_ACC_GYRO_MAG_SI_ZZ 0x2C 00237 #define LSM6DSL_ACC_GYRO_MAG_OFFX_L 0x2D 00238 #define LSM6DSL_ACC_GYRO_MAG_OFFX_H 0x2E 00239 #define LSM6DSL_ACC_GYRO_MAG_OFFY_L 0x2F 00240 #define LSM6DSL_ACC_GYRO_MAG_OFFY_H 0x30 00241 #define LSM6DSL_ACC_GYRO_MAG_OFFZ_L 0x31 00242 #define LSM6DSL_ACC_GYRO_MAG_OFFZ_H 0x32 00243 00244 /************** Generic Function *******************/ 00245 00246 /******************************************************************************* 00247 * Register : Generic - All 00248 * Address : Generic - All 00249 * Bit Group Name: None 00250 * Permission : W 00251 *******************************************************************************/ 00252 mems_status_t LSM6DSL_ACC_GYRO_write_reg( void *handle, u8_t Reg, u8_t *Bufp, u16_t len ); 00253 00254 /******************************************************************************* 00255 * Register : Generic - All 00256 * Address : Generic - All 00257 * Bit Group Name: None 00258 * Permission : R 00259 *******************************************************************************/ 00260 mems_status_t LSM6DSL_ACC_GYRO_read_reg( void *handle, u8_t Reg, u8_t *Bufp, u16_t len ); 00261 00262 /**************** Base Function *******************/ 00263 00264 /******************************************************************************* 00265 * Register : WHO_AM_I 00266 * Address : 0X0F 00267 * Bit Group Name: WHO_AM_I_BIT 00268 * Permission : RO 00269 *******************************************************************************/ 00270 #define LSM6DSL_ACC_GYRO_WHO_AM_I_BIT_MASK 0xFF 00271 #define LSM6DSL_ACC_GYRO_WHO_AM_I_BIT_POSITION 0 00272 mems_status_t LSM6DSL_ACC_GYRO_R_WHO_AM_I(void *handle, u8_t *value); 00273 00274 /******************************************************************************* 00275 * Register : CTRL3_C 00276 * Address : 0X12 00277 * Bit Group Name: BDU 00278 * Permission : RW 00279 *******************************************************************************/ 00280 typedef enum { 00281 LSM6DSL_ACC_GYRO_BDU_CONTINUOS =0x00, 00282 LSM6DSL_ACC_GYRO_BDU_BLOCK_UPDATE =0x40, 00283 } LSM6DSL_ACC_GYRO_BDU_t; 00284 00285 #define LSM6DSL_ACC_GYRO_BDU_MASK 0x40 00286 mems_status_t LSM6DSL_ACC_GYRO_W_BDU(void *handle, LSM6DSL_ACC_GYRO_BDU_t newValue); 00287 mems_status_t LSM6DSL_ACC_GYRO_R_BDU(void *handle, LSM6DSL_ACC_GYRO_BDU_t *value); 00288 00289 /******************************************************************************* 00290 * Register : CTRL1_XL 00291 * Address : 0X10 00292 * Bit Group Name: FS_XL 00293 * Permission : RW 00294 *******************************************************************************/ 00295 typedef enum { 00296 LSM6DSL_ACC_GYRO_FS_XL_2g =0x00, 00297 LSM6DSL_ACC_GYRO_FS_XL_16g =0x04, 00298 LSM6DSL_ACC_GYRO_FS_XL_4g =0x08, 00299 LSM6DSL_ACC_GYRO_FS_XL_8g =0x0C, 00300 } LSM6DSL_ACC_GYRO_FS_XL_t; 00301 00302 #define LSM6DSL_ACC_GYRO_FS_XL_MASK 0x0C 00303 mems_status_t LSM6DSL_ACC_GYRO_W_FS_XL(void *handle, LSM6DSL_ACC_GYRO_FS_XL_t newValue); 00304 mems_status_t LSM6DSL_ACC_GYRO_R_FS_XL(void *handle, LSM6DSL_ACC_GYRO_FS_XL_t *value); 00305 00306 /******************************************************************************* 00307 * Register : <REGISTER_L> - <REGISTER_H> 00308 * Output Type : GetAccData 00309 * Permission : RO 00310 *******************************************************************************/ 00311 mems_status_t LSM6DSL_ACC_GYRO_GetRawAccData(void *handle, u8_t *buff); 00312 mems_status_t LSM6DSL_ACC_Get_Acceleration(void *handle, int *buff, u8_t from_fifo); 00313 00314 /******************************************************************************* 00315 * Register : CTRL1_XL 00316 * Address : 0X10 00317 * Bit Group Name: ODR_XL 00318 * Permission : RW 00319 *******************************************************************************/ 00320 typedef enum { 00321 LSM6DSL_ACC_GYRO_ODR_XL_POWER_DOWN =0x00, 00322 LSM6DSL_ACC_GYRO_ODR_XL_13Hz =0x10, 00323 LSM6DSL_ACC_GYRO_ODR_XL_26Hz =0x20, 00324 LSM6DSL_ACC_GYRO_ODR_XL_52Hz =0x30, 00325 LSM6DSL_ACC_GYRO_ODR_XL_104Hz =0x40, 00326 LSM6DSL_ACC_GYRO_ODR_XL_208Hz =0x50, 00327 LSM6DSL_ACC_GYRO_ODR_XL_416Hz =0x60, 00328 LSM6DSL_ACC_GYRO_ODR_XL_833Hz =0x70, 00329 LSM6DSL_ACC_GYRO_ODR_XL_1660Hz =0x80, 00330 LSM6DSL_ACC_GYRO_ODR_XL_3330Hz =0x90, 00331 LSM6DSL_ACC_GYRO_ODR_XL_6660Hz =0xA0, 00332 } LSM6DSL_ACC_GYRO_ODR_XL_t; 00333 00334 #define LSM6DSL_ACC_GYRO_ODR_XL_MASK 0xF0 00335 mems_status_t LSM6DSL_ACC_GYRO_W_ODR_XL(void *handle, LSM6DSL_ACC_GYRO_ODR_XL_t newValue); 00336 mems_status_t LSM6DSL_ACC_GYRO_R_ODR_XL(void *handle, LSM6DSL_ACC_GYRO_ODR_XL_t *value); 00337 mems_status_t LSM6DSL_ACC_GYRO_translate_ODR_XL(LSM6DSL_ACC_GYRO_ODR_XL_t value, u16_t *odr_hz_val); 00338 00339 /******************************************************************************* 00340 * Register : CTRL2_G 00341 * Address : 0X11 00342 * Bit Group Name: FS_G 00343 * Permission : RW 00344 *******************************************************************************/ 00345 typedef enum { 00346 LSM6DSL_ACC_GYRO_FS_G_245dps =0x00, 00347 LSM6DSL_ACC_GYRO_FS_G_500dps =0x04, 00348 LSM6DSL_ACC_GYRO_FS_G_1000dps =0x08, 00349 LSM6DSL_ACC_GYRO_FS_G_2000dps =0x0C, 00350 } LSM6DSL_ACC_GYRO_FS_G_t; 00351 00352 #define LSM6DSL_ACC_GYRO_FS_G_MASK 0x0C 00353 mems_status_t LSM6DSL_ACC_GYRO_W_FS_G(void *handle, LSM6DSL_ACC_GYRO_FS_G_t newValue); 00354 mems_status_t LSM6DSL_ACC_GYRO_R_FS_G(void *handle, LSM6DSL_ACC_GYRO_FS_G_t *value); 00355 00356 /******************************************************************************* 00357 * Register : CTRL2_G 00358 * Address : 0X11 00359 * Bit Group Name: ODR_G 00360 * Permission : RW 00361 *******************************************************************************/ 00362 typedef enum { 00363 LSM6DSL_ACC_GYRO_ODR_G_POWER_DOWN =0x00, 00364 LSM6DSL_ACC_GYRO_ODR_G_13Hz =0x10, 00365 LSM6DSL_ACC_GYRO_ODR_G_26Hz =0x20, 00366 LSM6DSL_ACC_GYRO_ODR_G_52Hz =0x30, 00367 LSM6DSL_ACC_GYRO_ODR_G_104Hz =0x40, 00368 LSM6DSL_ACC_GYRO_ODR_G_208Hz =0x50, 00369 LSM6DSL_ACC_GYRO_ODR_G_416Hz =0x60, 00370 LSM6DSL_ACC_GYRO_ODR_G_833Hz =0x70, 00371 LSM6DSL_ACC_GYRO_ODR_G_1660Hz =0x80, 00372 LSM6DSL_ACC_GYRO_ODR_G_3330Hz =0x90, 00373 LSM6DSL_ACC_GYRO_ODR_G_6660Hz =0xA0, 00374 } LSM6DSL_ACC_GYRO_ODR_G_t; 00375 00376 #define LSM6DSL_ACC_GYRO_ODR_G_MASK 0xF0 00377 mems_status_t LSM6DSL_ACC_GYRO_W_ODR_G(void *handle, LSM6DSL_ACC_GYRO_ODR_G_t newValue); 00378 mems_status_t LSM6DSL_ACC_GYRO_R_ODR_G(void *handle, LSM6DSL_ACC_GYRO_ODR_G_t *value); 00379 mems_status_t LSM6DSL_ACC_GYRO_translate_ODR_G(LSM6DSL_ACC_GYRO_ODR_G_t value, u16_t *odr_hz_val); 00380 00381 /******************************************************************************* 00382 * Register : <REGISTER_L> - <REGISTER_H> 00383 * Output Type : GetGyroData 00384 * Permission : RO 00385 *******************************************************************************/ 00386 mems_status_t LSM6DSL_ACC_GYRO_GetRawGyroData(void *handle, u8_t *buff); 00387 mems_status_t LSM6DSL_ACC_Get_AngularRate(void *handle, int *buff, u8_t from_fifo); 00388 00389 /******************************************************************************* 00390 * Register : CTRL1_XL 00391 * Address : 0X10 00392 * Bit Group Name: BW_SEL 00393 * Permission : RW 00394 *******************************************************************************/ 00395 typedef enum { 00396 LSM6DSL_ACC_GYRO_BW_SEL_ODR2 =0x00, 00397 LSM6DSL_ACC_GYRO_BW_SEL_ODR4 =0x02, 00398 } LSM6DSL_ACC_GYRO_BW_SEL_t; 00399 00400 #define LSM6DSL_ACC_GYRO_BW_SEL_MASK 0x02 00401 mems_status_t LSM6DSL_ACC_GYRO_W_BW_SEL(void *handle, LSM6DSL_ACC_GYRO_BW_SEL_t newValue); 00402 mems_status_t LSM6DSL_ACC_GYRO_R_BW_SEL(void *handle, LSM6DSL_ACC_GYRO_BW_SEL_t *value); 00403 00404 /******************************************************************************* 00405 * Register : CTRL2_G 00406 * Address : 0X11 00407 * Bit Group Name: FS_125 00408 * Permission : RW 00409 *******************************************************************************/ 00410 typedef enum { 00411 LSM6DSL_ACC_GYRO_FS_125_DISABLED =0x00, 00412 LSM6DSL_ACC_GYRO_FS_125_ENABLED =0x02, 00413 } LSM6DSL_ACC_GYRO_FS_125_t; 00414 00415 #define LSM6DSL_ACC_GYRO_FS_125_MASK 0x02 00416 mems_status_t LSM6DSL_ACC_GYRO_W_FS_125(void *handle, LSM6DSL_ACC_GYRO_FS_125_t newValue); 00417 mems_status_t LSM6DSL_ACC_GYRO_R_FS_125(void *handle, LSM6DSL_ACC_GYRO_FS_125_t *value); 00418 00419 /**************** Advanced Function *******************/ 00420 00421 /******************************************************************************* 00422 * Register : CTRL3_C 00423 * Address : 0X12 00424 * Bit Group Name: BLE 00425 * Permission : RW 00426 *******************************************************************************/ 00427 typedef enum { 00428 LSM6DSL_ACC_GYRO_BLE_LSB =0x00, 00429 LSM6DSL_ACC_GYRO_BLE_MSB =0x02, 00430 } LSM6DSL_ACC_GYRO_BLE_t; 00431 00432 #define LSM6DSL_ACC_GYRO_BLE_MASK 0x02 00433 mems_status_t LSM6DSL_ACC_GYRO_W_BLE(void *handle, LSM6DSL_ACC_GYRO_BLE_t newValue); 00434 mems_status_t LSM6DSL_ACC_GYRO_R_BLE(void *handle, LSM6DSL_ACC_GYRO_BLE_t *value); 00435 00436 /******************************************************************************* 00437 * Register : FUNC_CFG_ACCESS 00438 * Address : 0X01 00439 * Bit Group Name: EMB_ACC 00440 * Permission : RW 00441 *******************************************************************************/ 00442 typedef enum { 00443 LSM6DSL_ACC_GYRO_EMBEDDED_ACCESS_DISABLED =0x00, 00444 LSM6DSL_ACC_GYRO_EMBEDDED_ACCESS_ENABLED =0x80, 00445 } LSM6DSL_ACC_GYRO_EMB_ACC_t; 00446 00447 #define LSM6DSL_ACC_GYRO_EMB_ACC_MASK 0x80 00448 mems_status_t LSM6DSL_ACC_GYRO_W_EmbeddedAccess(void *handle, LSM6DSL_ACC_GYRO_EMB_ACC_t newValue); 00449 mems_status_t LSM6DSL_ACC_GYRO_R_EmbeddedAccess(void *handle, LSM6DSL_ACC_GYRO_EMB_ACC_t *value); 00450 00451 /******************************************************************************* 00452 * Register : SENSOR_SYNC_TIME 00453 * Address : 0X04 00454 * Bit Group Name: TPH 00455 * Permission : RW 00456 *******************************************************************************/ 00457 #define LSM6DSL_ACC_GYRO_TPH_MASK 0xFF 00458 #define LSM6DSL_ACC_GYRO_TPH_POSITION 0 00459 mems_status_t LSM6DSL_ACC_GYRO_W_Stamping_Time_Frame(void *handle, u8_t newValue); 00460 mems_status_t LSM6DSL_ACC_GYRO_R_Stamping_Time_Frame(void *handle, u8_t *value); 00461 00462 /******************************************************************************* 00463 * Register : SENSOR_SYNC_RES_RATIO 00464 * Address : 0X05 00465 * Bit Group Name: RR 00466 * Permission : RW 00467 *******************************************************************************/ 00468 typedef enum { 00469 LSM6DSL_ACC_GYRO_TIM_RATIO_2_11 =0x00, 00470 LSM6DSL_ACC_GYRO_TIM_RATIO_2_12 =0x01, 00471 LSM6DSL_ACC_GYRO_TIM_RATIO_2_13 =0x02, 00472 LSM6DSL_ACC_GYRO_TIM_RATIO_2_14 =0x03, 00473 } LSM6DSL_ACC_GYRO_SYNC_RES_RATIO_t; 00474 00475 #define LSM6DSL_ACC_GYRO_SYNC_RES_RATIO_MASK 0x03 00476 mems_status_t LSM6DSL_ACC_GYRO_W_SYNC_RES_RATIO(void *handle, LSM6DSL_ACC_GYRO_SYNC_RES_RATIO_t newValue); 00477 mems_status_t LSM6DSL_ACC_GYRO_R_SYNC_RES_RATIO(void *handle, LSM6DSL_ACC_GYRO_SYNC_RES_RATIO_t *value); 00478 00479 00480 /******************************************************************************* 00481 * Register : FIFO_CTRL1 00482 * Address : 0X06 00483 * Bit Group Name: WTM_FIFO 00484 * Permission : RW 00485 *******************************************************************************/ 00486 #define LSM6DSL_ACC_GYRO_WTM_FIFO_CTRL1_MASK 0xFF 00487 #define LSM6DSL_ACC_GYRO_WTM_FIFO_CTRL1_POSITION 0 00488 #define LSM6DSL_ACC_GYRO_WTM_FIFO_CTRL2_MASK 0x07 00489 #define LSM6DSL_ACC_GYRO_WTM_FIFO_CTRL2_POSITION 0 00490 mems_status_t LSM6DSL_ACC_GYRO_W_FIFO_Watermark(void *handle, u16_t newValue); 00491 mems_status_t LSM6DSL_ACC_GYRO_R_FIFO_Watermark(void *handle, u16_t *value); 00492 00493 /******************************************************************************* 00494 * Register : FIFO_CTRL2 00495 * Address : 0X07 00496 * Bit Group Name: FIFO_TEMP_EN 00497 * Permission : RW 00498 *******************************************************************************/ 00499 typedef enum { 00500 LSM6DSL_ACC_GYRO_FIFO_TEMP_DISABLE =0x00, 00501 LSM6DSL_ACC_GYRO_FIFO_TEMP_ENABLE =0x08, 00502 } LSM6DSL_ACC_GYRO_FIFO_TEMP_t; 00503 00504 #define LSM6DSL_ACC_GYRO_FIFO_TEMP_MASK 0x08 00505 mems_status_t LSM6DSL_ACC_GYRO_W_FIFO_TEMP(void *handle, LSM6DSL_ACC_GYRO_FIFO_TEMP_t newValue); 00506 mems_status_t LSM6DSL_ACC_GYRO_R_FIFO_TEMP(void *handle, LSM6DSL_ACC_GYRO_FIFO_TEMP_t *value); 00507 00508 00509 /******************************************************************************* 00510 * Register : FIFO_CTRL2 00511 * Address : 0X07 00512 * Bit Group Name: TIM_PEDO_FIFO_DRDY 00513 * Permission : RW 00514 *******************************************************************************/ 00515 typedef enum { 00516 LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_DRDY_DISABLED =0x00, 00517 LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_DRDY_ENABLED =0x40, 00518 } LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_DRDY_t; 00519 00520 #define LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_DRDY_MASK 0x40 00521 mems_status_t LSM6DSL_ACC_GYRO_W_TIM_PEDO_FIFO_Write_En(void *handle, LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_DRDY_t newValue); 00522 mems_status_t LSM6DSL_ACC_GYRO_R_TIM_PEDO_FIFO_Write_En(void *handle, LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_DRDY_t *value); 00523 00524 /******************************************************************************* 00525 * Register : FIFO_CTRL2 00526 * Address : 0X07 00527 * Bit Group Name: TIM_PEDO_FIFO_EN 00528 * Permission : RW 00529 *******************************************************************************/ 00530 typedef enum { 00531 LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_EN_DISABLED =0x00, 00532 LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_EN_ENABLED =0x80, 00533 } LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_EN_t; 00534 00535 #define LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_EN_MASK 0x80 00536 mems_status_t LSM6DSL_ACC_GYRO_W_TIM_PEDO_FIFO_En(void *handle, LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_EN_t newValue); 00537 mems_status_t LSM6DSL_ACC_GYRO_R_TIM_PEDO_FIFO_En(void *handle, LSM6DSL_ACC_GYRO_TIM_PEDO_FIFO_EN_t *value); 00538 00539 /******************************************************************************* 00540 * Register : FIFO_CTRL3 00541 * Address : 0X08 00542 * Bit Group Name: DEC_FIFO_XL 00543 * Permission : RW 00544 *******************************************************************************/ 00545 typedef enum { 00546 LSM6DSL_ACC_GYRO_DEC_FIFO_XL_DATA_NOT_IN_FIFO =0x00, 00547 LSM6DSL_ACC_GYRO_DEC_FIFO_XL_NO_DECIMATION =0x01, 00548 LSM6DSL_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_2 =0x02, 00549 LSM6DSL_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_3 =0x03, 00550 LSM6DSL_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_4 =0x04, 00551 LSM6DSL_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_8 =0x05, 00552 LSM6DSL_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_16 =0x06, 00553 LSM6DSL_ACC_GYRO_DEC_FIFO_XL_DECIMATION_BY_32 =0x07, 00554 } LSM6DSL_ACC_GYRO_DEC_FIFO_XL_t; 00555 00556 #define LSM6DSL_ACC_GYRO_DEC_FIFO_XL_MASK 0x07 00557 mems_status_t LSM6DSL_ACC_GYRO_W_DEC_FIFO_XL(void *handle, LSM6DSL_ACC_GYRO_DEC_FIFO_XL_t newValue); 00558 mems_status_t LSM6DSL_ACC_GYRO_W_DEC_FIFO_XL_val(void *handle, u16_t newValue); 00559 mems_status_t LSM6DSL_ACC_GYRO_R_DEC_FIFO_XL(void *handle, LSM6DSL_ACC_GYRO_DEC_FIFO_XL_t *value); 00560 00561 /******************************************************************************* 00562 * Register : FIFO_CTRL3 00563 * Address : 0X08 00564 * Bit Group Name: DEC_FIFO_G 00565 * Permission : RW 00566 *******************************************************************************/ 00567 typedef enum { 00568 LSM6DSL_ACC_GYRO_DEC_FIFO_G_DATA_NOT_IN_FIFO =0x00, 00569 LSM6DSL_ACC_GYRO_DEC_FIFO_G_NO_DECIMATION =0x08, 00570 LSM6DSL_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_2 =0x10, 00571 LSM6DSL_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_3 =0x18, 00572 LSM6DSL_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_4 =0x20, 00573 LSM6DSL_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_8 =0x28, 00574 LSM6DSL_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_16 =0x30, 00575 LSM6DSL_ACC_GYRO_DEC_FIFO_G_DECIMATION_BY_32 =0x38, 00576 } LSM6DSL_ACC_GYRO_DEC_FIFO_G_t; 00577 00578 #define LSM6DSL_ACC_GYRO_DEC_FIFO_G_MASK 0x38 00579 mems_status_t LSM6DSL_ACC_GYRO_W_DEC_FIFO_G(void *handle, LSM6DSL_ACC_GYRO_DEC_FIFO_G_t newValue); 00580 mems_status_t LSM6DSL_ACC_GYRO_W_DEC_FIFO_G_val(void *handle, u16_t newValue); 00581 mems_status_t LSM6DSL_ACC_GYRO_R_DEC_FIFO_G(void *handle, LSM6DSL_ACC_GYRO_DEC_FIFO_G_t *value); 00582 00583 /******************************************************************************* 00584 * Register : FIFO_CTRL4 00585 * Address : 0X09 00586 * Bit Group Name: DEC_DS3_FIFO 00587 * Permission : RW 00588 *******************************************************************************/ 00589 typedef enum { 00590 LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_DATA_NOT_IN_FIFO =0x00, 00591 LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_NO_DECIMATION =0x01, 00592 LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_DECIMATION_BY_2 =0x02, 00593 LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_DECIMATION_BY_3 =0x03, 00594 LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_DECIMATION_BY_4 =0x04, 00595 LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_DECIMATION_BY_8 =0x05, 00596 LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_DECIMATION_BY_16 =0x06, 00597 LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_DECIMATION_BY_32 =0x07, 00598 } LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_t; 00599 00600 #define LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_MASK 0x07 00601 mems_status_t LSM6DSL_ACC_GYRO_W_DEC_FIFO_DS3(void *handle, LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_t newValue); 00602 mems_status_t LSM6DSL_ACC_GYRO_R_DEC_FIFO_DS3(void *handle, LSM6DSL_ACC_GYRO_DEC_FIFO_DS3_t *value); 00603 00604 /******************************************************************************* 00605 * Register : FIFO_CTRL4 00606 * Address : 0X09 00607 * Bit Group Name: DEC_DS4_FIFO 00608 * Permission : RW 00609 *******************************************************************************/ 00610 typedef enum { 00611 LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_DATA_NOT_IN_FIFO =0x00, 00612 LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_NO_DECIMATION =0x08, 00613 LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_DECIMATION_BY_2 =0x10, 00614 LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_DECIMATION_BY_3 =0x18, 00615 LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_DECIMATION_BY_4 =0x20, 00616 LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_DECIMATION_BY_8 =0x28, 00617 LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_DECIMATION_BY_16 =0x30, 00618 LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_DECIMATION_BY_32 =0x38, 00619 } LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_t; 00620 00621 #define LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_MASK 0x38 00622 mems_status_t LSM6DSL_ACC_GYRO_W_DEC_FIFO_DS4(void *handle, LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_t newValue); 00623 mems_status_t LSM6DSL_ACC_GYRO_R_DEC_FIFO_DS4(void *handle, LSM6DSL_ACC_GYRO_DEC_FIFO_DS4_t *value); 00624 00625 /******************************************************************************* 00626 * Register : FIFO_CTRL4 00627 * Address : 0X09 00628 * Bit Group Name: HI_DATA_ONLY 00629 * Permission : RW 00630 *******************************************************************************/ 00631 typedef enum { 00632 LSM6DSL_ACC_GYRO_HI_DATA_ONLY_DISABLED =0x00, 00633 LSM6DSL_ACC_GYRO_HI_DATA_ONLY_ENABLED =0x40, 00634 } LSM6DSL_ACC_GYRO_HI_DATA_ONLY_t; 00635 00636 #define LSM6DSL_ACC_GYRO_HI_DATA_ONLY_MASK 0x40 00637 mems_status_t LSM6DSL_ACC_GYRO_W_HI_DATA_ONLY(void *handle, LSM6DSL_ACC_GYRO_HI_DATA_ONLY_t newValue); 00638 mems_status_t LSM6DSL_ACC_GYRO_R_HI_DATA_ONLY(void *handle, LSM6DSL_ACC_GYRO_HI_DATA_ONLY_t *value); 00639 00640 /******************************************************************************* 00641 * Register : FIFO_CTRL4 00642 * Address : 0X09 00643 * Bit Group Name: STOP_ON_FTH 00644 * Permission : RW 00645 *******************************************************************************/ 00646 typedef enum { 00647 LSM6DSL_ACC_GYRO_STOP_ON_FTH_DISABLED =0x00, 00648 LSM6DSL_ACC_GYRO_STOP_ON_FTH_ENABLED =0x80, 00649 } LSM6DSL_ACC_GYRO_STOP_ON_FTH_t; 00650 00651 #define LSM6DSL_ACC_GYRO_STOP_ON_FTH_MASK 0x80 00652 mems_status_t LSM6DSL_ACC_GYRO_W_STOP_ON_FTH(void *handle, LSM6DSL_ACC_GYRO_STOP_ON_FTH_t newValue); 00653 mems_status_t LSM6DSL_ACC_GYRO_R_STOP_ON_FTH(void *handle, LSM6DSL_ACC_GYRO_STOP_ON_FTH_t *value); 00654 00655 /******************************************************************************* 00656 * Register : FIFO_CTRL5 00657 * Address : 0X0A 00658 * Bit Group Name: FIFO_MODE 00659 * Permission : RW 00660 *******************************************************************************/ 00661 typedef enum { 00662 LSM6DSL_ACC_GYRO_FIFO_MODE_BYPASS =0x00, 00663 LSM6DSL_ACC_GYRO_FIFO_MODE_FIFO =0x01, 00664 LSM6DSL_ACC_GYRO_FIFO_MODE_STREAM =0x02, 00665 LSM6DSL_ACC_GYRO_FIFO_MODE_STF =0x03, 00666 LSM6DSL_ACC_GYRO_FIFO_MODE_BTS =0x04, 00667 LSM6DSL_ACC_GYRO_FIFO_MODE_DYN_STREAM =0x05, 00668 LSM6DSL_ACC_GYRO_FIFO_MODE_DYN_STREAM_2 =0x06, 00669 LSM6DSL_ACC_GYRO_FIFO_MODE_BTF =0x07, 00670 } LSM6DSL_ACC_GYRO_FIFO_MODE_t; 00671 00672 #define LSM6DSL_ACC_GYRO_FIFO_MODE_MASK 0x07 00673 mems_status_t LSM6DSL_ACC_GYRO_W_FIFO_MODE(void *handle, LSM6DSL_ACC_GYRO_FIFO_MODE_t newValue); 00674 mems_status_t LSM6DSL_ACC_GYRO_R_FIFO_MODE(void *handle, LSM6DSL_ACC_GYRO_FIFO_MODE_t *value); 00675 00676 /******************************************************************************* 00677 * Register : FIFO_CTRL5 00678 * Address : 0X0A 00679 * Bit Group Name: ODR_FIFO 00680 * Permission : RW 00681 *******************************************************************************/ 00682 typedef enum { 00683 LSM6DSL_ACC_GYRO_ODR_FIFO_10Hz =0x08, 00684 LSM6DSL_ACC_GYRO_ODR_FIFO_25Hz =0x10, 00685 LSM6DSL_ACC_GYRO_ODR_FIFO_50Hz =0x18, 00686 LSM6DSL_ACC_GYRO_ODR_FIFO_100Hz =0x20, 00687 LSM6DSL_ACC_GYRO_ODR_FIFO_200Hz =0x28, 00688 LSM6DSL_ACC_GYRO_ODR_FIFO_400Hz =0x30, 00689 LSM6DSL_ACC_GYRO_ODR_FIFO_800Hz =0x38, 00690 LSM6DSL_ACC_GYRO_ODR_FIFO_1600Hz =0x40, 00691 LSM6DSL_ACC_GYRO_ODR_FIFO_3300Hz =0x48, 00692 LSM6DSL_ACC_GYRO_ODR_FIFO_6600Hz =0x50, 00693 LSM6DSL_ACC_GYRO_ODR_FIFO_13300Hz =0x58, 00694 } LSM6DSL_ACC_GYRO_ODR_FIFO_t; 00695 00696 #define LSM6DSL_ACC_GYRO_ODR_FIFO_MASK 0x78 00697 mems_status_t LSM6DSL_ACC_GYRO_W_ODR_FIFO(void *handle, LSM6DSL_ACC_GYRO_ODR_FIFO_t newValue); 00698 mems_status_t LSM6DSL_ACC_GYRO_R_ODR_FIFO(void *handle, LSM6DSL_ACC_GYRO_ODR_FIFO_t *value); 00699 00700 /******************************************************************************* 00701 * Register : DRDY_PULSE_CFG_G 00702 * Address : 0X0B 00703 * Bit Group Name: DRDY_PULSE 00704 * Permission : RW 00705 *******************************************************************************/ 00706 typedef enum { 00707 LSM6DSL_ACC_GYRO_DRDY_LATCH =0x00, 00708 LSM6DSL_ACC_GYRO_DRDY_PULSE =0x80, 00709 } LSM6DSL_ACC_GYRO_DRDY_PULSE_t; 00710 00711 #define LSM6DSL_ACC_GYRO_DRDY_PULSE_MASK 0x80 00712 mems_status_t LSM6DSL_ACC_GYRO_W_DRDY_PULSE(void *handle, LSM6DSL_ACC_GYRO_DRDY_PULSE_t newValue); 00713 mems_status_t LSM6DSL_ACC_GYRO_R_DRDY_PULSE(void *handle, LSM6DSL_ACC_GYRO_DRDY_PULSE_t *value); 00714 00715 /******************************************************************************* 00716 * Register : INT1_CTRL 00717 * Address : 0X0D 00718 * Bit Group Name: INT1_DRDY_XL 00719 * Permission : RW 00720 *******************************************************************************/ 00721 typedef enum { 00722 LSM6DSL_ACC_GYRO_INT1_DRDY_XL_DISABLED =0x00, 00723 LSM6DSL_ACC_GYRO_INT1_DRDY_XL_ENABLED =0x01, 00724 } LSM6DSL_ACC_GYRO_INT1_DRDY_XL_t; 00725 00726 #define LSM6DSL_ACC_GYRO_INT1_DRDY_XL_MASK 0x01 00727 mems_status_t LSM6DSL_ACC_GYRO_W_DRDY_XL_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_DRDY_XL_t newValue); 00728 mems_status_t LSM6DSL_ACC_GYRO_R_DRDY_XL_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_DRDY_XL_t *value); 00729 00730 /******************************************************************************* 00731 * Register : INT1_CTRL 00732 * Address : 0X0D 00733 * Bit Group Name: INT1_DRDY_G 00734 * Permission : RW 00735 *******************************************************************************/ 00736 typedef enum { 00737 LSM6DSL_ACC_GYRO_INT1_DRDY_G_DISABLED =0x00, 00738 LSM6DSL_ACC_GYRO_INT1_DRDY_G_ENABLED =0x02, 00739 } LSM6DSL_ACC_GYRO_INT1_DRDY_G_t; 00740 00741 #define LSM6DSL_ACC_GYRO_INT1_DRDY_G_MASK 0x02 00742 mems_status_t LSM6DSL_ACC_GYRO_W_DRDY_G_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_DRDY_G_t newValue); 00743 mems_status_t LSM6DSL_ACC_GYRO_R_DRDY_G_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_DRDY_G_t *value); 00744 00745 /******************************************************************************* 00746 * Register : INT1_CTRL 00747 * Address : 0X0D 00748 * Bit Group Name: INT1_BOOT 00749 * Permission : RW 00750 *******************************************************************************/ 00751 typedef enum { 00752 LSM6DSL_ACC_GYRO_INT1_BOOT_DISABLED =0x00, 00753 LSM6DSL_ACC_GYRO_INT1_BOOT_ENABLED =0x04, 00754 } LSM6DSL_ACC_GYRO_INT1_BOOT_t; 00755 00756 #define LSM6DSL_ACC_GYRO_INT1_BOOT_MASK 0x04 00757 mems_status_t LSM6DSL_ACC_GYRO_W_BOOT_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_BOOT_t newValue); 00758 mems_status_t LSM6DSL_ACC_GYRO_R_BOOT_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_BOOT_t *value); 00759 00760 /******************************************************************************* 00761 * Register : INT1_CTRL 00762 * Address : 0X0D 00763 * Bit Group Name: INT1_FTH 00764 * Permission : RW 00765 *******************************************************************************/ 00766 typedef enum { 00767 LSM6DSL_ACC_GYRO_INT1_FTH_DISABLED =0x00, 00768 LSM6DSL_ACC_GYRO_INT1_FTH_ENABLED =0x08, 00769 } LSM6DSL_ACC_GYRO_INT1_FTH_t; 00770 00771 #define LSM6DSL_ACC_GYRO_INT1_FTH_MASK 0x08 00772 mems_status_t LSM6DSL_ACC_GYRO_W_FIFO_TSHLD_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_FTH_t newValue); 00773 mems_status_t LSM6DSL_ACC_GYRO_R_FIFO_TSHLD_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_FTH_t *value); 00774 00775 /******************************************************************************* 00776 * Register : INT1_CTRL 00777 * Address : 0X0D 00778 * Bit Group Name: INT1_OVR 00779 * Permission : RW 00780 *******************************************************************************/ 00781 typedef enum { 00782 LSM6DSL_ACC_GYRO_INT1_OVR_DISABLED =0x00, 00783 LSM6DSL_ACC_GYRO_INT1_OVR_ENABLED =0x10, 00784 } LSM6DSL_ACC_GYRO_INT1_OVR_t; 00785 00786 #define LSM6DSL_ACC_GYRO_INT1_OVR_MASK 0x10 00787 mems_status_t LSM6DSL_ACC_GYRO_W_OVERRUN_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_OVR_t newValue); 00788 mems_status_t LSM6DSL_ACC_GYRO_R_OVERRUN_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_OVR_t *value); 00789 00790 /******************************************************************************* 00791 * Register : INT1_CTRL 00792 * Address : 0X0D 00793 * Bit Group Name: INT1_FULL_FLAG 00794 * Permission : RW 00795 *******************************************************************************/ 00796 typedef enum { 00797 LSM6DSL_ACC_GYRO_INT1_FULL_FLAG_DISABLED =0x00, 00798 LSM6DSL_ACC_GYRO_INT1_FULL_FLAG_ENABLED =0x20, 00799 } LSM6DSL_ACC_GYRO_INT1_FULL_FLAG_t; 00800 00801 #define LSM6DSL_ACC_GYRO_INT1_FULL_FLAG_MASK 0x20 00802 mems_status_t LSM6DSL_ACC_GYRO_W_FULL_FLAG_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_FULL_FLAG_t newValue); 00803 mems_status_t LSM6DSL_ACC_GYRO_R_FULL_FLAG_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_FULL_FLAG_t *value); 00804 00805 /******************************************************************************* 00806 * Register : INT1_CTRL 00807 * Address : 0X0D 00808 * Bit Group Name: INT1_SIGN_MOT 00809 * Permission : RW 00810 *******************************************************************************/ 00811 typedef enum { 00812 LSM6DSL_ACC_GYRO_INT1_SIGN_MOT_DISABLED =0x00, 00813 LSM6DSL_ACC_GYRO_INT1_SIGN_MOT_ENABLED =0x40, 00814 } LSM6DSL_ACC_GYRO_INT1_SIGN_MOT_t; 00815 00816 #define LSM6DSL_ACC_GYRO_INT1_SIGN_MOT_MASK 0x40 00817 mems_status_t LSM6DSL_ACC_GYRO_W_SIGN_MOT_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_SIGN_MOT_t newValue); 00818 mems_status_t LSM6DSL_ACC_GYRO_R_SIGN_MOT_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_SIGN_MOT_t *value); 00819 00820 /******************************************************************************* 00821 * Register : INT1_CTRL 00822 * Address : 0X0D 00823 * Bit Group Name: INT1_STEP_DETECTOR 00824 * Permission : RW 00825 *******************************************************************************/ 00826 typedef enum { 00827 LSM6DSL_ACC_GYRO_INT1_PEDO_DISABLED =0x00, 00828 LSM6DSL_ACC_GYRO_INT1_PEDO_ENABLED =0x80, 00829 } LSM6DSL_ACC_GYRO_INT1_PEDO_t; 00830 00831 #define LSM6DSL_ACC_GYRO_INT1_PEDO_MASK 0x80 00832 mems_status_t LSM6DSL_ACC_GYRO_W_STEP_DET_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_PEDO_t newValue); 00833 mems_status_t LSM6DSL_ACC_GYRO_R_STEP_DET_on_INT1(void *handle, LSM6DSL_ACC_GYRO_INT1_PEDO_t *value); 00834 00835 /******************************************************************************* 00836 * Register : INT2_CTRL 00837 * Address : 0X0E 00838 * Bit Group Name: INT2_DRDY_XL 00839 * Permission : RW 00840 *******************************************************************************/ 00841 typedef enum { 00842 LSM6DSL_ACC_GYRO_INT2_DRDY_XL_DISABLED =0x00, 00843 LSM6DSL_ACC_GYRO_INT2_DRDY_XL_ENABLED =0x01, 00844 } LSM6DSL_ACC_GYRO_INT2_DRDY_XL_t; 00845 00846 #define LSM6DSL_ACC_GYRO_INT2_DRDY_XL_MASK 0x01 00847 mems_status_t LSM6DSL_ACC_GYRO_W_DRDY_XL_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_DRDY_XL_t newValue); 00848 mems_status_t LSM6DSL_ACC_GYRO_R_DRDY_XL_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_DRDY_XL_t *value); 00849 00850 /******************************************************************************* 00851 * Register : INT2_CTRL 00852 * Address : 0X0E 00853 * Bit Group Name: INT2_DRDY_G 00854 * Permission : RW 00855 *******************************************************************************/ 00856 typedef enum { 00857 LSM6DSL_ACC_GYRO_INT2_DRDY_G_DISABLED =0x00, 00858 LSM6DSL_ACC_GYRO_INT2_DRDY_G_ENABLED =0x02, 00859 } LSM6DSL_ACC_GYRO_INT2_DRDY_G_t; 00860 00861 #define LSM6DSL_ACC_GYRO_INT2_DRDY_G_MASK 0x02 00862 mems_status_t LSM6DSL_ACC_GYRO_W_DRDY_G_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_DRDY_G_t newValue); 00863 mems_status_t LSM6DSL_ACC_GYRO_R_DRDY_G_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_DRDY_G_t *value); 00864 00865 /******************************************************************************* 00866 * Register : INT2_CTRL 00867 * Address : 0X0E 00868 * Bit Group Name: INT2_DRDY_TEMP 00869 * Permission : RW 00870 *******************************************************************************/ 00871 typedef enum { 00872 LSM6DSL_ACC_GYRO_INT2_DRDY_TEMP_DISABLED =0x00, 00873 LSM6DSL_ACC_GYRO_INT2_DRDY_TEMP_ENABLED =0x04, 00874 } LSM6DSL_ACC_GYRO_INT2_DRDY_TEMP_t; 00875 00876 #define LSM6DSL_ACC_GYRO_INT2_DRDY_TEMP_MASK 0x04 00877 mems_status_t LSM6DSL_ACC_GYRO_W_DRDY_TEMP_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_DRDY_TEMP_t newValue); 00878 mems_status_t LSM6DSL_ACC_GYRO_R_DRDY_TEMP_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_DRDY_TEMP_t *value); 00879 00880 00881 /******************************************************************************* 00882 * Register : INT2_CTRL 00883 * Address : 0X0E 00884 * Bit Group Name: INT2_FTH 00885 * Permission : RW 00886 *******************************************************************************/ 00887 typedef enum { 00888 LSM6DSL_ACC_GYRO_INT2_FTH_DISABLED =0x00, 00889 LSM6DSL_ACC_GYRO_INT2_FTH_ENABLED =0x08, 00890 } LSM6DSL_ACC_GYRO_INT2_FTH_t; 00891 00892 #define LSM6DSL_ACC_GYRO_INT2_FTH_MASK 0x08 00893 mems_status_t LSM6DSL_ACC_GYRO_W_FIFO_TSHLD_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_FTH_t newValue); 00894 mems_status_t LSM6DSL_ACC_GYRO_R_FIFO_TSHLD_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_FTH_t *value); 00895 00896 /******************************************************************************* 00897 * Register : INT2_CTRL 00898 * Address : 0X0E 00899 * Bit Group Name: INT2_OVR 00900 * Permission : RW 00901 *******************************************************************************/ 00902 typedef enum { 00903 LSM6DSL_ACC_GYRO_INT2_OVR_DISABLED =0x00, 00904 LSM6DSL_ACC_GYRO_INT2_OVR_ENABLED =0x10, 00905 } LSM6DSL_ACC_GYRO_INT2_OVR_t; 00906 00907 #define LSM6DSL_ACC_GYRO_INT2_OVR_MASK 0x10 00908 mems_status_t LSM6DSL_ACC_GYRO_W_OVERRUN_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_OVR_t newValue); 00909 mems_status_t LSM6DSL_ACC_GYRO_R_OVERRUN_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_OVR_t *value); 00910 00911 /******************************************************************************* 00912 * Register : INT2_CTRL 00913 * Address : 0X0E 00914 * Bit Group Name: INT2_FULL_FLAG 00915 * Permission : RW 00916 *******************************************************************************/ 00917 typedef enum { 00918 LSM6DSL_ACC_GYRO_INT2_FULL_FLAG_DISABLED =0x00, 00919 LSM6DSL_ACC_GYRO_INT2_FULL_FLAG_ENABLED =0x20, 00920 } LSM6DSL_ACC_GYRO_INT2_FULL_FLAG_t; 00921 00922 #define LSM6DSL_ACC_GYRO_INT2_FULL_FLAG_MASK 0x20 00923 mems_status_t LSM6DSL_ACC_GYRO_W_FULL_FLAG_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_FULL_FLAG_t newValue); 00924 mems_status_t LSM6DSL_ACC_GYRO_R_FULL_FLAG_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_FULL_FLAG_t *value); 00925 00926 /******************************************************************************* 00927 * Register : INT2_CTRL 00928 * Address : 0X0E 00929 * Bit Group Name: INT2_STEP_COUNT_OV 00930 * Permission : RW 00931 *******************************************************************************/ 00932 typedef enum { 00933 LSM6DSL_ACC_GYRO_INT2_STEP_COUNT_OV_DISABLED =0x00, 00934 LSM6DSL_ACC_GYRO_INT2_STEP_COUNT_OV_ENABLED =0x40, 00935 } LSM6DSL_ACC_GYRO_INT2_STEP_COUNT_OV_t; 00936 00937 #define LSM6DSL_ACC_GYRO_INT2_STEP_COUNT_OV_MASK 0x40 00938 mems_status_t LSM6DSL_ACC_GYRO_W_STEP_COUNT_OV_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_STEP_COUNT_OV_t newValue); 00939 mems_status_t LSM6DSL_ACC_GYRO_R_STEP_COUNT_OV_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_STEP_COUNT_OV_t *value); 00940 00941 /******************************************************************************* 00942 * Register : INT2_CTRL 00943 * Address : 0X0E 00944 * Bit Group Name: INT2_STEP_DELTA 00945 * Permission : RW 00946 *******************************************************************************/ 00947 typedef enum { 00948 LSM6DSL_ACC_GYRO_INT2_STEP_DELTA_DISABLED =0x00, 00949 LSM6DSL_ACC_GYRO_INT2_STEP_DELTA_ENABLED =0x80, 00950 } LSM6DSL_ACC_GYRO_INT2_STEP_DELTA_t; 00951 00952 #define LSM6DSL_ACC_GYRO_INT2_STEP_DELTA_MASK 0x80 00953 mems_status_t LSM6DSL_ACC_GYRO_W_STEP_DELTA_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_STEP_DELTA_t newValue); 00954 mems_status_t LSM6DSL_ACC_GYRO_R_STEP_DELTA_on_INT2(void *handle, LSM6DSL_ACC_GYRO_INT2_STEP_DELTA_t *value); 00955 00956 /******************************************************************************* 00957 * Register : CTRL3_C 00958 * Address : 0X12 00959 * Bit Group Name: SW_RESET 00960 * Permission : RW 00961 *******************************************************************************/ 00962 typedef enum { 00963 LSM6DSL_ACC_GYRO_SW_RESET_NORMAL_MODE =0x00, 00964 LSM6DSL_ACC_GYRO_SW_RESET_RESET_DEVICE =0x01, 00965 } LSM6DSL_ACC_GYRO_SW_RESET_t; 00966 00967 #define LSM6DSL_ACC_GYRO_SW_RESET_MASK 0x01 00968 mems_status_t LSM6DSL_ACC_GYRO_W_SW_RESET(void *handle, LSM6DSL_ACC_GYRO_SW_RESET_t newValue); 00969 mems_status_t LSM6DSL_ACC_GYRO_R_SW_RESET(void *handle, LSM6DSL_ACC_GYRO_SW_RESET_t *value); 00970 00971 00972 /******************************************************************************* 00973 * Register : CTRL3_C 00974 * Address : 0X12 00975 * Bit Group Name: IF_INC 00976 * Permission : RW 00977 *******************************************************************************/ 00978 typedef enum { 00979 LSM6DSL_ACC_GYRO_IF_INC_DISABLED =0x00, 00980 LSM6DSL_ACC_GYRO_IF_INC_ENABLED =0x04, 00981 } LSM6DSL_ACC_GYRO_IF_INC_t; 00982 00983 #define LSM6DSL_ACC_GYRO_IF_INC_MASK 0x04 00984 mems_status_t LSM6DSL_ACC_GYRO_W_IF_Addr_Incr(void *handle, LSM6DSL_ACC_GYRO_IF_INC_t newValue); 00985 mems_status_t LSM6DSL_ACC_GYRO_R_IF_Addr_Incr(void *handle, LSM6DSL_ACC_GYRO_IF_INC_t *value); 00986 00987 /******************************************************************************* 00988 * Register : CTRL3_C 00989 * Address : 0X12 00990 * Bit Group Name: SIM 00991 * Permission : RW 00992 *******************************************************************************/ 00993 typedef enum { 00994 LSM6DSL_ACC_GYRO_SIM_4_WIRE =0x00, 00995 LSM6DSL_ACC_GYRO_SIM_3_WIRE =0x08, 00996 } LSM6DSL_ACC_GYRO_SIM_t; 00997 00998 #define LSM6DSL_ACC_GYRO_SIM_MASK 0x08 00999 mems_status_t LSM6DSL_ACC_GYRO_W_SPI_Mode(void *handle, LSM6DSL_ACC_GYRO_SIM_t newValue); 01000 mems_status_t LSM6DSL_ACC_GYRO_R_SPI_Mode(void *handle, LSM6DSL_ACC_GYRO_SIM_t *value); 01001 01002 /******************************************************************************* 01003 * Register : CTRL3_C 01004 * Address : 0X12 01005 * Bit Group Name: PP_OD 01006 * Permission : RW 01007 *******************************************************************************/ 01008 typedef enum { 01009 LSM6DSL_ACC_GYRO_PP_OD_PUSH_PULL =0x00, 01010 LSM6DSL_ACC_GYRO_PP_OD_OPEN_DRAIN =0x10, 01011 } LSM6DSL_ACC_GYRO_PP_OD_t; 01012 01013 #define LSM6DSL_ACC_GYRO_PP_OD_MASK 0x10 01014 mems_status_t LSM6DSL_ACC_GYRO_W_PadSel(void *handle, LSM6DSL_ACC_GYRO_PP_OD_t newValue); 01015 mems_status_t LSM6DSL_ACC_GYRO_R_PadSel(void *handle, LSM6DSL_ACC_GYRO_PP_OD_t *value); 01016 01017 /******************************************************************************* 01018 * Register : CTRL3_C 01019 * Address : 0X12 01020 * Bit Group Name: H_LACTIVE 01021 * Permission : RW 01022 *******************************************************************************/ 01023 typedef enum { 01024 LSM6DSL_ACC_GYRO_INT_ACT_LEVEL_ACTIVE_HI =0x00, 01025 LSM6DSL_ACC_GYRO_INT_ACT_LEVEL_ACTIVE_LO =0x20, 01026 } LSM6DSL_ACC_GYRO_INT_ACT_LEVEL_t; 01027 01028 #define LSM6DSL_ACC_GYRO_INT_ACT_LEVEL_MASK 0x20 01029 mems_status_t LSM6DSL_ACC_GYRO_W_INT_ACT_LEVEL(void *handle, LSM6DSL_ACC_GYRO_INT_ACT_LEVEL_t newValue); 01030 mems_status_t LSM6DSL_ACC_GYRO_R_INT_ACT_LEVEL(void *handle, LSM6DSL_ACC_GYRO_INT_ACT_LEVEL_t *value); 01031 01032 01033 /******************************************************************************* 01034 * Register : CTRL3_C 01035 * Address : 0X12 01036 * Bit Group Name: BOOT 01037 * Permission : RW 01038 *******************************************************************************/ 01039 typedef enum { 01040 LSM6DSL_ACC_GYRO_BOOT_NORMAL_MODE =0x00, 01041 LSM6DSL_ACC_GYRO_BOOT_REBOOT_MODE =0x80, 01042 } LSM6DSL_ACC_GYRO_BOOT_t; 01043 01044 #define LSM6DSL_ACC_GYRO_BOOT_MASK 0x80 01045 mems_status_t LSM6DSL_ACC_GYRO_W_BOOT(void *handle, LSM6DSL_ACC_GYRO_BOOT_t newValue); 01046 mems_status_t LSM6DSL_ACC_GYRO_R_BOOT(void *handle, LSM6DSL_ACC_GYRO_BOOT_t *value); 01047 01048 /******************************************************************************* 01049 * Register : CTRL4_C 01050 * Address : 0X13 01051 * Bit Group Name: LPF1_SEL_G 01052 * Permission : RW 01053 *******************************************************************************/ 01054 typedef enum { 01055 LSM6DSL_ACC_GYRO_MODE3_LPF1_G_DISABLED =0x00, 01056 LSM6DSL_ACC_GYRO_MODE3_LPF1_G_ENABLED =0x02, 01057 } LSM6DSL_ACC_GYRO_LPF1_SEL_G_t; 01058 01059 #define LSM6DSL_ACC_GYRO_LPF1_SEL_G_MASK 0x02 01060 mems_status_t LSM6DSL_ACC_GYRO_W_LPF1_SEL_G(void *handle, LSM6DSL_ACC_GYRO_LPF1_SEL_G_t newValue); 01061 mems_status_t LSM6DSL_ACC_GYRO_R_LPF1_SEL_G(void *handle, LSM6DSL_ACC_GYRO_LPF1_SEL_G_t *value); 01062 01063 /******************************************************************************* 01064 * Register : CTRL4_C 01065 * Address : 0X13 01066 * Bit Group Name: I2C_DISABLE 01067 * Permission : RW 01068 *******************************************************************************/ 01069 typedef enum { 01070 LSM6DSL_ACC_GYRO_I2C_DISABLE_I2C_AND_SPI =0x00, 01071 LSM6DSL_ACC_GYRO_I2C_DISABLE_SPI_ONLY =0x04, 01072 } LSM6DSL_ACC_GYRO_I2C_DISABLE_t; 01073 01074 #define LSM6DSL_ACC_GYRO_I2C_DISABLE_MASK 0x04 01075 mems_status_t LSM6DSL_ACC_GYRO_W_I2C_DISABLE(void *handle, LSM6DSL_ACC_GYRO_I2C_DISABLE_t newValue); 01076 mems_status_t LSM6DSL_ACC_GYRO_R_I2C_DISABLE(void *handle, LSM6DSL_ACC_GYRO_I2C_DISABLE_t *value); 01077 01078 /******************************************************************************* 01079 * Register : CTRL4_C 01080 * Address : 0X13 01081 * Bit Group Name: DRDY_MSK 01082 * Permission : RW 01083 *******************************************************************************/ 01084 typedef enum { 01085 LSM6DSL_ACC_GYRO_DRDY_MSK_DISABLED =0x00, 01086 LSM6DSL_ACC_GYRO_DRDY_MSK_ENABLED =0x08, 01087 } LSM6DSL_ACC_GYRO_DRDY_MSK_t; 01088 01089 #define LSM6DSL_ACC_GYRO_DRDY_MSK_MASK 0x08 01090 mems_status_t LSM6DSL_ACC_GYRO_W_DRDY_MSK(void *handle, LSM6DSL_ACC_GYRO_DRDY_MSK_t newValue); 01091 mems_status_t LSM6DSL_ACC_GYRO_R_DRDY_MSK(void *handle, LSM6DSL_ACC_GYRO_DRDY_MSK_t *value); 01092 01093 /******************************************************************************* 01094 * Register : CTRL4_C 01095 * Address : 0X13 01096 * Bit Group Name: INT2_ON_INT1 01097 * Permission : RW 01098 *******************************************************************************/ 01099 typedef enum { 01100 LSM6DSL_ACC_GYRO_INT2_ON_INT1_DISABLED =0x00, 01101 LSM6DSL_ACC_GYRO_INT2_ON_INT1_ENABLED =0x20, 01102 } LSM6DSL_ACC_GYRO_INT2_ON_INT1_t; 01103 01104 #define LSM6DSL_ACC_GYRO_INT2_ON_INT1_MASK 0x20 01105 mems_status_t LSM6DSL_ACC_GYRO_W_INT2_ON_INT1(void *handle, LSM6DSL_ACC_GYRO_INT2_ON_INT1_t newValue); 01106 mems_status_t LSM6DSL_ACC_GYRO_R_INT2_ON_INT1(void *handle, LSM6DSL_ACC_GYRO_INT2_ON_INT1_t *value); 01107 01108 /******************************************************************************* 01109 * Register : CTRL4_C 01110 * Address : 0X13 01111 * Bit Group Name: SLEEP_G 01112 * Permission : RW 01113 *******************************************************************************/ 01114 typedef enum { 01115 LSM6DSL_ACC_GYRO_SLEEP_G_DISABLED =0x00, 01116 LSM6DSL_ACC_GYRO_SLEEP_G_ENABLED =0x40, 01117 } LSM6DSL_ACC_GYRO_SLEEP_G_t; 01118 01119 #define LSM6DSL_ACC_GYRO_SLEEP_G_MASK 0x40 01120 mems_status_t LSM6DSL_ACC_GYRO_W_SleepMode_G(void *handle, LSM6DSL_ACC_GYRO_SLEEP_G_t newValue); 01121 mems_status_t LSM6DSL_ACC_GYRO_R_SleepMode_G(void *handle, LSM6DSL_ACC_GYRO_SLEEP_G_t *value); 01122 01123 /******************************************************************************* 01124 * Register : CTRL5_C 01125 * Address : 0X14 01126 * Bit Group Name: ST_XL 01127 * Permission : RW 01128 *******************************************************************************/ 01129 typedef enum { 01130 LSM6DSL_ACC_GYRO_ST_XL_NORMAL_MODE =0x00, 01131 LSM6DSL_ACC_GYRO_ST_XL_POS_SIGN_TEST =0x01, 01132 LSM6DSL_ACC_GYRO_ST_XL_NEG_SIGN_TEST =0x02, 01133 LSM6DSL_ACC_GYRO_ST_XL_NA =0x03, 01134 } LSM6DSL_ACC_GYRO_ST_XL_t; 01135 01136 #define LSM6DSL_ACC_GYRO_ST_XL_MASK 0x03 01137 mems_status_t LSM6DSL_ACC_GYRO_W_SelfTest_XL(void *handle, LSM6DSL_ACC_GYRO_ST_XL_t newValue); 01138 mems_status_t LSM6DSL_ACC_GYRO_R_SelfTest_XL(void *handle, LSM6DSL_ACC_GYRO_ST_XL_t *value); 01139 01140 /******************************************************************************* 01141 * Register : CTRL5_C 01142 * Address : 0X14 01143 * Bit Group Name: ST_G 01144 * Permission : RW 01145 *******************************************************************************/ 01146 typedef enum { 01147 LSM6DSL_ACC_GYRO_ST_G_NORMAL_MODE =0x00, 01148 LSM6DSL_ACC_GYRO_ST_G_POS_SIGN_TEST =0x04, 01149 LSM6DSL_ACC_GYRO_ST_G_NA =0x08, 01150 LSM6DSL_ACC_GYRO_ST_G_NEG_SIGN_TEST =0x0C, 01151 } LSM6DSL_ACC_GYRO_ST_G_t; 01152 01153 #define LSM6DSL_ACC_GYRO_ST_G_MASK 0x0C 01154 mems_status_t LSM6DSL_ACC_GYRO_W_SelfTest_G(void *handle, LSM6DSL_ACC_GYRO_ST_G_t newValue); 01155 mems_status_t LSM6DSL_ACC_GYRO_R_SelfTest_G(void *handle, LSM6DSL_ACC_GYRO_ST_G_t *value); 01156 01157 /******************************************************************************* 01158 * Register : CTRL5_C 01159 * Address : 0X14 01160 * Bit Group Name: DEN_LH 01161 * Permission : RW 01162 *******************************************************************************/ 01163 typedef enum { 01164 LSM6DSL_ACC_GYRO_DEN_LOW =0x00, 01165 LSM6DSL_ACC_GYRO_DEN_HIGH =0x10, 01166 } LSM6DSL_ACC_GYRO_DEN_LH_t; 01167 01168 #define LSM6DSL_ACC_GYRO_DEN_LH_MASK 0x10 01169 mems_status_t LSM6DSL_ACC_GYRO_W_DEN_Polarity(void *handle, LSM6DSL_ACC_GYRO_DEN_LH_t newValue); 01170 mems_status_t LSM6DSL_ACC_GYRO_R_DEN_Polarity(void *handle, LSM6DSL_ACC_GYRO_DEN_LH_t *value); 01171 01172 /******************************************************************************* 01173 * Register : CTRL5_C 01174 * Address : 0X14 01175 * Bit Group Name: ST_ROUNDING 01176 * Permission : RW 01177 *******************************************************************************/ 01178 typedef enum { 01179 LSM6DSL_ACC_GYRO_NO_ROUNDING =0x00, 01180 LSM6DSL_ACC_GYRO_ACC_ONLY =0x20, 01181 LSM6DSL_ACC_GYRO_GYRO_ONLY =0x40, 01182 LSM6DSL_ACC_GYRO_ACC_GYRO =0x60, 01183 LSM6DSL_ACC_GYRO_SH1_SH6 =0x80, 01184 LSM6DSL_ACC_GYRO_ACC_SH1_SH6 =0xA0, 01185 LSM6DSL_ACC_GYRO_ACC_GYRO_SH1_SH6_SH7_SH12 =0xC0, 01186 LSM6DSL_ACC_GYRO_ACC_GYRO_SH1_SH6 =0xE0, 01187 } LSM6DSL_ACC_GYRO_ROUNDING_t; 01188 01189 #define LSM6DSL_ACC_GYRO_LSM6DSL_ACC_GYRO_ROUNDING_t_MASK 0xE0 01190 mems_status_t LSM6DSL_ACC_GYRO_W_CircularBurstMode(void *handle, LSM6DSL_ACC_GYRO_ROUNDING_t newValue); 01191 mems_status_t LSM6DSL_ACC_GYRO_R_CircularBurstMode(void *handle, LSM6DSL_ACC_GYRO_ROUNDING_t *value); 01192 01193 /******************************************************************************* 01194 * Register : CTRL6_G 01195 * Address : 0X15 01196 * Bit Group Name: FTYPE 01197 * Permission : RW 01198 *******************************************************************************/ 01199 typedef enum { 01200 LSM6DSL_ACC_GYRO_LP_G_NORMAL =0x00, 01201 LSM6DSL_ACC_GYRO_LP_G_NARROW =0x01, 01202 LSM6DSL_ACC_GYRO_LP_G_VERY_NARROW =0x02, 01203 LSM6DSL_ACC_GYRO_LP_G_WIDE =0x03, 01204 } LSM6DSL_ACC_GYRO_FTYPE_t; 01205 01206 #define LSM6DSL_ACC_GYRO_FTYPE_MASK 0x03 01207 mems_status_t LSM6DSL_ACC_GYRO_W_LP_BW_G(void *handle, LSM6DSL_ACC_GYRO_FTYPE_t newValue); 01208 mems_status_t LSM6DSL_ACC_GYRO_R_LP_BW_G(void *handle, LSM6DSL_ACC_GYRO_FTYPE_t *value); 01209 01210 /******************************************************************************* 01211 * Register : CTRL6_G 01212 * Address : 0X15 01213 * Bit Group Name: USR_OFF_W 01214 * Permission : RW 01215 *******************************************************************************/ 01216 typedef enum { 01217 LSM6DSL_ACC_GYRO_2Emin10 =0x00, 01218 LSM6DSL_ACC_GYRO_2Emin6 =0x08, 01219 } LSM6DSL_ACC_GYRO_USR_OFF_W_t; 01220 01221 #define LSM6DSL_ACC_GYRO_USR_OFF_W_MASK 0x08 01222 mems_status_t LSM6DSL_ACC_GYRO_W_UserOffsetWeight(void *handle, LSM6DSL_ACC_GYRO_USR_OFF_W_t newValue); 01223 mems_status_t LSM6DSL_ACC_GYRO_R_UserOffsetWeight(void *handle, LSM6DSL_ACC_GYRO_USR_OFF_W_t *value); 01224 01225 01226 /******************************************************************************* 01227 * Register : CTRL6_G 01228 * Address : 0X15 01229 * Bit Group Name: LP_XL 01230 * Permission : RW 01231 *******************************************************************************/ 01232 typedef enum { 01233 LSM6DSL_ACC_GYRO_LP_XL_DISABLED =0x00, 01234 LSM6DSL_ACC_GYRO_LP_XL_ENABLED =0x10, 01235 } LSM6DSL_ACC_GYRO_LP_XL_t; 01236 01237 #define LSM6DSL_ACC_GYRO_LP_XL_MASK 0x10 01238 mems_status_t LSM6DSL_ACC_GYRO_W_LowPower_XL(void *handle, LSM6DSL_ACC_GYRO_LP_XL_t newValue); 01239 mems_status_t LSM6DSL_ACC_GYRO_R_LowPower_XL(void *handle, LSM6DSL_ACC_GYRO_LP_XL_t *value); 01240 01241 /******************************************************************************* 01242 * Register : CTRL6_G 01243 * Address : 0X15 01244 * Bit Group Name: DEN_LVL2_EN 01245 * Permission : RW 01246 *******************************************************************************/ 01247 typedef enum { 01248 LSM6DSL_ACC_GYRO_DEN_LVL2_EN_DISABLED =0x00, 01249 LSM6DSL_ACC_GYRO_DEN_LVL2_EN_ENABLED =0x20, 01250 } LSM6DSL_ACC_GYRO_DEN_LVL2_EN_t; 01251 01252 #define LSM6DSL_ACC_GYRO_DEN_LVL2_EN_MASK 0x20 01253 mems_status_t LSM6DSL_ACC_GYRO_W_DEN_LVL2_EN(void *handle, LSM6DSL_ACC_GYRO_DEN_LVL2_EN_t newValue); 01254 mems_status_t LSM6DSL_ACC_GYRO_R_DEN_LVL2_EN(void *handle, LSM6DSL_ACC_GYRO_DEN_LVL2_EN_t *value); 01255 01256 /******************************************************************************* 01257 * Register : CTRL6_G 01258 * Address : 0X15 01259 * Bit Group Name: DEN_LVL_EN 01260 * Permission : RW 01261 *******************************************************************************/ 01262 typedef enum { 01263 LSM6DSL_ACC_GYRO_DEN_LVL_EN_DISABLED =0x00, 01264 LSM6DSL_ACC_GYRO_DEN_LVL_EN_ENABLED =0x40, 01265 } LSM6DSL_ACC_GYRO_DEN_LVL_EN_t; 01266 01267 #define LSM6DSL_ACC_GYRO_DEN_LVL_EN_MASK 0x40 01268 mems_status_t LSM6DSL_ACC_GYRO_W_DEN_LVL_EN(void *handle, LSM6DSL_ACC_GYRO_DEN_LVL_EN_t newValue); 01269 mems_status_t LSM6DSL_ACC_GYRO_R_DEN_LVL_EN(void *handle, LSM6DSL_ACC_GYRO_DEN_LVL_EN_t *value); 01270 01271 /******************************************************************************* 01272 * Register : CTRL6_G 01273 * Address : 0X15 01274 * Bit Group Name: TRIG_EN 01275 * Permission : RW 01276 *******************************************************************************/ 01277 typedef enum { 01278 LSM6DSL_ACC_GYRO_DEN_EDGE_EN_DISABLED =0x00, 01279 LSM6DSL_ACC_GYRO_DEN_EDGE_EN_ENABLED =0x80, 01280 } LSM6DSL_ACC_GYRO_DEN_EDGE_EN_t; 01281 01282 #define LSM6DSL_ACC_GYRO_DEN_EDGE_EN_MASK 0x80 01283 mems_status_t LSM6DSL_ACC_GYRO_W_ExternalTrigger(void *handle, LSM6DSL_ACC_GYRO_DEN_EDGE_EN_t newValue); 01284 mems_status_t LSM6DSL_ACC_GYRO_R_ExternalTrigger(void *handle, LSM6DSL_ACC_GYRO_DEN_EDGE_EN_t *value); 01285 01286 /******************************************************************************* 01287 * Register : CTRL7_G 01288 * Address : 0X16 01289 * Bit Group Name: ROUNDING_STATUS 01290 * Permission : RW 01291 *******************************************************************************/ 01292 typedef enum { 01293 LSM6DSL_ACC_GYRO_RND_DISABLE =0x00, 01294 LSM6DSL_ACC_GYRO_RND_ENABLE =0x04, 01295 } LSM6DSL_ACC_GYRO_RND_STATUS_t; 01296 01297 #define LSM6DSL_ACC_GYRO_RND_STATUS_MASK 0x04 01298 mems_status_t LSM6DSL_ACC_GYRO_W_RoundingOnStatusRegisters(void *handle, LSM6DSL_ACC_GYRO_RND_STATUS_t newValue); 01299 mems_status_t LSM6DSL_ACC_GYRO_R_RoundingOnStatusRegisters(void *handle, LSM6DSL_ACC_GYRO_RND_STATUS_t *value); 01300 01301 01302 /******************************************************************************* 01303 * Register : CTRL7_G 01304 * Address : 0X16 01305 * Bit Group Name: HPM_G 01306 * Permission : RW 01307 *******************************************************************************/ 01308 typedef enum { 01309 LSM6DSL_ACC_GYRO_HPM_G_0Hz016 =0x00, 01310 LSM6DSL_ACC_GYRO_HPM_G_0Hz065 =0x10, 01311 LSM6DSL_ACC_GYRO_HPM_G_2Hz260 =0x20, 01312 LSM6DSL_ACC_GYRO_HPM_G_1Hz04 =0x30, 01313 } LSM6DSL_ACC_GYRO_HPM_G_t; 01314 01315 #define LSM6DSL_ACC_GYRO_HPM_G_MASK 0x30 01316 mems_status_t LSM6DSL_ACC_GYRO_W_HPM_G(void *handle, LSM6DSL_ACC_GYRO_HPM_G_t newValue); 01317 mems_status_t LSM6DSL_ACC_GYRO_R_HPM_G(void *handle, LSM6DSL_ACC_GYRO_HPM_G_t *value); 01318 01319 /******************************************************************************* 01320 * Register : CTRL7_G 01321 * Address : 0X16 01322 * Bit Group Name: HP_EN_G 01323 * Permission : RW 01324 *******************************************************************************/ 01325 typedef enum { 01326 LSM6DSL_ACC_GYRO_HP_EN_DISABLED =0x00, 01327 LSM6DSL_ACC_GYRO_HP_EN_ENABLED =0x40, 01328 } LSM6DSL_ACC_GYRO_HP_EN_t; 01329 01330 #define LSM6DSL_ACC_GYRO_HP_EN_MASK 0x40 01331 mems_status_t LSM6DSL_ACC_GYRO_W_HPFilter_En(void *handle, LSM6DSL_ACC_GYRO_HP_EN_t newValue); 01332 mems_status_t LSM6DSL_ACC_GYRO_R_HPFilter_En(void *handle, LSM6DSL_ACC_GYRO_HP_EN_t *value); 01333 01334 /******************************************************************************* 01335 * Register : CTRL7_G 01336 * Address : 0X16 01337 * Bit Group Name: LP_EN 01338 * Permission : RW 01339 *******************************************************************************/ 01340 typedef enum { 01341 LSM6DSL_ACC_GYRO_LP_EN_DISABLED =0x00, 01342 LSM6DSL_ACC_GYRO_LP_EN_ENABLED =0x80, 01343 } LSM6DSL_ACC_GYRO_LP_EN_t; 01344 01345 #define LSM6DSL_ACC_GYRO_LP_EN_MASK 0x80 01346 mems_status_t LSM6DSL_ACC_GYRO_W_LP_Mode(void *handle, LSM6DSL_ACC_GYRO_LP_EN_t newValue); 01347 mems_status_t LSM6DSL_ACC_GYRO_R_LP_Mode(void *handle, LSM6DSL_ACC_GYRO_LP_EN_t *value); 01348 01349 /******************************************************************************* 01350 * Register : CTRL7_G 01351 * Address : 0X16 01352 * Bit Group Name: ROUNDING_STATUS 01353 * Permission : RW 01354 *******************************************************************************/ 01355 typedef enum { 01356 LSM6DSL_ACC_GYRO_ROUNDING_STATUS_DISABLED =0x00, 01357 LSM6DSL_ACC_GYRO_ROUNDING_STATUS_ENABLED =0x04, 01358 } LSM6DSL_ACC_GYRO_ROUNDING_STATUS_t; 01359 01360 #define LSM6DSL_ACC_GYRO_ROUNDING_STATUS_MASK 0x04 01361 mems_status_t LSM6DSL_ACC_GYRO_W_ROUNDING_STATUS(void *handle, LSM6DSL_ACC_GYRO_ROUNDING_STATUS_t newValue); 01362 mems_status_t LSM6DSL_ACC_GYRO_R_ROUNDING_STATUS(void *handle, LSM6DSL_ACC_GYRO_ROUNDING_STATUS_t *value); 01363 01364 /******************************************************************************* 01365 * Register : CTRL7_G 01366 * Address : 0X16 01367 * Bit Group Name: HP_G_RST 01368 * Permission : RW 01369 *******************************************************************************/ 01370 typedef enum { 01371 LSM6DSL_ACC_GYRO_HP_G_RST_OFF =0x00, 01372 LSM6DSL_ACC_GYRO_HP_G_RST_ON =0x08, 01373 } LSM6DSL_ACC_GYRO_HP_G_RST_t; 01374 01375 #define LSM6DSL_ACC_GYRO_HP_G_RST_MASK 0x08 01376 mems_status_t LSM6DSL_ACC_GYRO_W_HP_G_RST(void *handle, LSM6DSL_ACC_GYRO_HP_G_RST_t newValue); 01377 mems_status_t LSM6DSL_ACC_GYRO_R_HP_G_RST(void *handle, LSM6DSL_ACC_GYRO_HP_G_RST_t *value); 01378 01379 /******************************************************************************* 01380 * Register : CTRL8_XL 01381 * Address : 0X17 01382 * Bit Group Name: LOW_PASS_ON_6D 01383 * Permission : RW 01384 *******************************************************************************/ 01385 typedef enum { 01386 LSM6DSL_ACC_GYRO_LOW_PASS_ON_6D_OFF =0x00, 01387 LSM6DSL_ACC_GYRO_LOW_PASS_ON_6D_ON =0x01, 01388 } LSM6DSL_ACC_GYRO_LOW_PASS_ON_6D_t; 01389 01390 #define LSM6DSL_ACC_GYRO_LOW_PASS_ON_6D_MASK 0x01 01391 mems_status_t LSM6DSL_ACC_GYRO_W_LOW_PASS_ON_6D(void *handle, LSM6DSL_ACC_GYRO_LOW_PASS_ON_6D_t newValue); 01392 mems_status_t LSM6DSL_ACC_GYRO_R_LOW_PASS_ON_6D(void *handle, LSM6DSL_ACC_GYRO_LOW_PASS_ON_6D_t *value); 01393 01394 /******************************************************************************* 01395 * Register : CTRL8_XL 01396 * Address : 0X17 01397 * Bit Group Name: HP_SLOPE_XL_EN 01398 * Permission : RW 01399 *******************************************************************************/ 01400 typedef enum { 01401 LSM6DSL_ACC_GYRO_HP_SLOPE_XL_EN =0x00, 01402 LSM6DSL_ACC_GYRO_HP_SLOPE_XL_DIS =0x04, 01403 } LSM6DSL_ACC_GYRO_HP_SLOPE_XL_t; 01404 01405 #define LSM6DSL_ACC_GYRO_HP_SLOPE_XL_MASK 0x04 01406 mems_status_t LSM6DSL_ACC_GYRO_W_HP_SLOPE_XL(void *handle, LSM6DSL_ACC_GYRO_HP_SLOPE_XL_t newValue); 01407 mems_status_t LSM6DSL_ACC_GYRO_R_HP_SLOPE_XL(void *handle, LSM6DSL_ACC_GYRO_HP_SLOPE_XL_t *value); 01408 01409 /******************************************************************************* 01410 * Register : CTRL8_XL 01411 * Address : 0X17 01412 * Bit Group Name: INPUT_COMPOSITE 01413 * Permission : RW 01414 *******************************************************************************/ 01415 typedef enum { 01416 LSM6DSL_ACC_GYRO_IN_ODR_DIV_2 =0x00, 01417 LSM6DSL_ACC_GYRO_IN_ODR_DIV_4 =0x80, 01418 } LSM6DSL_ACC_GYRO_IN_COMP_t; 01419 01420 #define LSM6DSL_ACC_GYRO_IN_COMP_MASK 0x80 01421 mems_status_t LSM6DSL_ACC_GYRO_W_InComposit(void *handle, LSM6DSL_ACC_GYRO_IN_COMP_t newValue); 01422 mems_status_t LSM6DSL_ACC_GYRO_R_InComposit(void *handle, LSM6DSL_ACC_GYRO_IN_COMP_t *value); 01423 01424 /******************************************************************************* 01425 * Register : CTRL8_XL 01426 * Address : 0X17 01427 * Bit Group Name: HP_REF_MODE 01428 * Permission : RW 01429 *******************************************************************************/ 01430 typedef enum { 01431 LSM6DSL_ACC_GYRO_HP_REF_DISABLE =0x00, 01432 LSM6DSL_ACC_GYRO_HP_REF_ENABLE =0x10, 01433 } LSM6DSL_ACC_GYRO_HP_REF_MODE_t; 01434 01435 #define LSM6DSL_ACC_GYRO_HP_REF_MODE_MASK 0x10 01436 mems_status_t LSM6DSL_ACC_GYRO_W_HPfilterReference(void *handle, LSM6DSL_ACC_GYRO_HP_REF_MODE_t newValue); 01437 mems_status_t LSM6DSL_ACC_GYRO_R_HPfilterReference(void *handle, LSM6DSL_ACC_GYRO_HP_REF_MODE_t *value); 01438 01439 /******************************************************************************* 01440 * Register : CTRL8_XL 01441 * Address : 0X17 01442 * Bit Group Name: HPCF_XL 01443 * Permission : RW 01444 *******************************************************************************/ 01445 typedef enum { 01446 LSM6DSL_ACC_GYRO_HPCF_XL_DIV4 =0x00, 01447 LSM6DSL_ACC_GYRO_HPCF_XL_DIV100 =0x20, 01448 LSM6DSL_ACC_GYRO_HPCF_XL_DIV9 =0x40, 01449 LSM6DSL_ACC_GYRO_HPCF_XL_DIV400 =0x60, 01450 } LSM6DSL_ACC_GYRO_HPCF_XL_t; 01451 01452 #define LSM6DSL_ACC_GYRO_HPCF_XL_MASK 0x60 01453 mems_status_t LSM6DSL_ACC_GYRO_W_HPCF_XL(void *handle, LSM6DSL_ACC_GYRO_HPCF_XL_t newValue); 01454 mems_status_t LSM6DSL_ACC_GYRO_R_HPCF_XL(void *handle, LSM6DSL_ACC_GYRO_HPCF_XL_t *value); 01455 01456 /******************************************************************************* 01457 * Register : CTRL8_XL 01458 * Address : 0X17 01459 * Bit Group Name: LPF2_XL_EN 01460 * Permission : RW 01461 *******************************************************************************/ 01462 typedef enum { 01463 LSM6DSL_ACC_GYRO_LPF2_XL_DISABLE =0x00, 01464 LSM6DSL_ACC_GYRO_LPF2_XL_ENABLE =0x80, 01465 } LSM6DSL_ACC_GYRO_LPF2_XL_t; 01466 01467 #define LSM6DSL_ACC_GYRO_LPF2_XL_MASK 0x80 01468 mems_status_t LSM6DSL_ACC_GYRO_W_LowPassFiltSel_XL(void *handle, LSM6DSL_ACC_GYRO_LPF2_XL_t newValue); 01469 mems_status_t LSM6DSL_ACC_GYRO_R_LowPassFiltSel_XL(void *handle, LSM6DSL_ACC_GYRO_LPF2_XL_t *value); 01470 01471 01472 /******************************************************************************* 01473 * Register : CTRL9_XL 01474 * Address : 0X18 01475 * Bit Group Name: SOFT_EN 01476 * Permission : RW 01477 *******************************************************************************/ 01478 typedef enum { 01479 LSM6DSL_ACC_GYRO_SOFT_DISABLED =0x00, 01480 LSM6DSL_ACC_GYRO_SOFT_ENABLE =0x04, 01481 } LSM6DSL_ACC_GYRO_SOFT_t; 01482 01483 #define LSM6DSL_ACC_GYRO_SOFT_MASK 0x04 01484 mems_status_t LSM6DSL_ACC_GYRO_W_SOFT(void *handle, LSM6DSL_ACC_GYRO_SOFT_t newValue); 01485 mems_status_t LSM6DSL_ACC_GYRO_R_SOFT(void *handle, LSM6DSL_ACC_GYRO_SOFT_t *value); 01486 01487 /******************************************************************************* 01488 * Register : CTRL10_C 01489 * Address : 0X19 01490 * Bit Group Name: SIGN_MOTION_EN 01491 * Permission : RW 01492 *******************************************************************************/ 01493 typedef enum { 01494 LSM6DSL_ACC_GYRO_SIGN_MOTION_EN_DISABLED =0x00, 01495 LSM6DSL_ACC_GYRO_SIGN_MOTION_EN_ENABLED =0x01, 01496 } LSM6DSL_ACC_GYRO_SIGN_MOTION_EN_t; 01497 01498 #define LSM6DSL_ACC_GYRO_SIGN_MOTION_EN_MASK 0x01 01499 mems_status_t LSM6DSL_ACC_GYRO_W_SignifcantMotion(void *handle, LSM6DSL_ACC_GYRO_SIGN_MOTION_EN_t newValue); 01500 mems_status_t LSM6DSL_ACC_GYRO_R_SignifcantMotion(void *handle, LSM6DSL_ACC_GYRO_SIGN_MOTION_EN_t *value); 01501 01502 /******************************************************************************* 01503 * Register : CTRL10_C 01504 * Address : 0X19 01505 * Bit Group Name: PEDO_RST_STEP 01506 * Permission : RW 01507 *******************************************************************************/ 01508 typedef enum { 01509 LSM6DSL_ACC_GYRO_PEDO_RST_STEP_DISABLED =0x00, 01510 LSM6DSL_ACC_GYRO_PEDO_RST_STEP_ENABLED =0x02, 01511 } LSM6DSL_ACC_GYRO_PEDO_RST_STEP_t; 01512 01513 #define LSM6DSL_ACC_GYRO_PEDO_RST_STEP_MASK 0x02 01514 mems_status_t LSM6DSL_ACC_GYRO_W_PedoStepReset(void *handle, LSM6DSL_ACC_GYRO_PEDO_RST_STEP_t newValue); 01515 mems_status_t LSM6DSL_ACC_GYRO_R_PedoStepReset(void *handle, LSM6DSL_ACC_GYRO_PEDO_RST_STEP_t *value); 01516 01517 /******************************************************************************* 01518 * Register : CTRL10_C 01519 * Address : 0X19 01520 * Bit Group Name: FUNC_EN 01521 * Permission : RW 01522 *******************************************************************************/ 01523 typedef enum { 01524 LSM6DSL_ACC_GYRO_FUNC_EN_DISABLED =0x00, 01525 LSM6DSL_ACC_GYRO_FUNC_EN_ENABLED =0x04, 01526 } LSM6DSL_ACC_GYRO_FUNC_EN_t; 01527 01528 #define LSM6DSL_ACC_GYRO_FUNC_EN_MASK 0x04 01529 mems_status_t LSM6DSL_ACC_GYRO_W_FUNC_EN(void *handle, LSM6DSL_ACC_GYRO_FUNC_EN_t newValue); 01530 mems_status_t LSM6DSL_ACC_GYRO_R_FUNC_EN(void *handle, LSM6DSL_ACC_GYRO_FUNC_EN_t *value); 01531 01532 /******************************************************************************* 01533 * Register : CTRL10_C 01534 * Address : 0X19 01535 * Bit Group Name: TILT_EN 01536 * Permission : RW 01537 *******************************************************************************/ 01538 typedef enum { 01539 LSM6DSL_ACC_GYRO_TILT_DISABLED =0x00, 01540 LSM6DSL_ACC_GYRO_TILT_ENABLED =0x08, 01541 } LSM6DSL_ACC_GYRO_TILT_G_t; 01542 01543 #define LSM6DSL_ACC_GYRO_TILT_MASK 0x08 01544 mems_status_t LSM6DSL_ACC_GYRO_W_TILT(void *handle, LSM6DSL_ACC_GYRO_TILT_G_t newValue); 01545 mems_status_t LSM6DSL_ACC_GYRO_R_TILT(void *handle, LSM6DSL_ACC_GYRO_TILT_G_t *value); 01546 01547 /******************************************************************************* 01548 * Register : CTRL10_C 01549 * Address : 0X19 01550 * Bit Group Name: PEDO_EN 01551 * Permission : RW 01552 *******************************************************************************/ 01553 typedef enum { 01554 LSM6DSL_ACC_GYRO_PEDO_DISABLED =0x00, 01555 LSM6DSL_ACC_GYRO_PEDO_ENABLED =0x10, 01556 } LSM6DSL_ACC_GYRO_PEDO_t; 01557 01558 #define LSM6DSL_ACC_GYRO_PEDO_MASK 0x10 01559 mems_status_t LSM6DSL_ACC_GYRO_W_PEDO(void *handle, LSM6DSL_ACC_GYRO_PEDO_t newValue); 01560 mems_status_t LSM6DSL_ACC_GYRO_R_PEDO(void *handle, LSM6DSL_ACC_GYRO_PEDO_t *value); 01561 01562 /******************************************************************************* 01563 * Register : CTRL10_C 01564 * Address : 0X19 01565 * Bit Group Name: TIMER_EN 01566 * Permission : RW 01567 *******************************************************************************/ 01568 typedef enum { 01569 LSM6DSL_ACC_GYRO_TIMER_DISABLED =0x00, 01570 LSM6DSL_ACC_GYRO_TIMER_ENABLED =0x20, 01571 } LSM6DSL_ACC_GYRO_TIMER_t; 01572 01573 #define LSM6DSL_ACC_GYRO_TIMER_MASK 0x20 01574 mems_status_t LSM6DSL_ACC_GYRO_W_TIMER(void *handle, LSM6DSL_ACC_GYRO_TIMER_t newValue); 01575 mems_status_t LSM6DSL_ACC_GYRO_R_TIMER(void *handle, LSM6DSL_ACC_GYRO_TIMER_t *value); 01576 01577 01578 /******************************************************************************* 01579 * Register : MASTER_CONFIG 01580 * Address : 0X1A 01581 * Bit Group Name: MASTER_ON 01582 * Permission : RW 01583 *******************************************************************************/ 01584 typedef enum { 01585 LSM6DSL_ACC_GYRO_MASTER_ON_DISABLED =0x00, 01586 LSM6DSL_ACC_GYRO_MASTER_ON_ENABLED =0x01, 01587 } LSM6DSL_ACC_GYRO_MASTER_ON_t; 01588 01589 #define LSM6DSL_ACC_GYRO_MASTER_ON_MASK 0x01 01590 mems_status_t LSM6DSL_ACC_GYRO_W_I2C_MASTER_Enable(void *handle, LSM6DSL_ACC_GYRO_MASTER_ON_t newValue); 01591 mems_status_t LSM6DSL_ACC_GYRO_R_I2C_MASTER_Enable(void *handle, LSM6DSL_ACC_GYRO_MASTER_ON_t *value); 01592 01593 /******************************************************************************* 01594 * Register : MASTER_CONFIG 01595 * Address : 0X1A 01596 * Bit Group Name: IRON_EN 01597 * Permission : RW 01598 *******************************************************************************/ 01599 typedef enum { 01600 LSM6DSL_ACC_GYRO_IRON_EN_DISABLED =0x00, 01601 LSM6DSL_ACC_GYRO_IRON_EN_ENABLED =0x02, 01602 } LSM6DSL_ACC_GYRO_IRON_EN_t; 01603 01604 #define LSM6DSL_ACC_GYRO_IRON_EN_MASK 0x02 01605 mems_status_t LSM6DSL_ACC_GYRO_W_IronCorrection_EN(void *handle, LSM6DSL_ACC_GYRO_IRON_EN_t newValue); 01606 mems_status_t LSM6DSL_ACC_GYRO_R_IronCorrection_EN(void *handle, LSM6DSL_ACC_GYRO_IRON_EN_t *value); 01607 01608 /******************************************************************************* 01609 * Register : MASTER_CONFIG 01610 * Address : 0X1A 01611 * Bit Group Name: PASS_THRU_MODE 01612 * Permission : RW 01613 *******************************************************************************/ 01614 typedef enum { 01615 LSM6DSL_ACC_GYRO_PASS_THRU_MODE_DISABLED =0x00, 01616 LSM6DSL_ACC_GYRO_PASS_THRU_MODE_ENABLED =0x04, 01617 } LSM6DSL_ACC_GYRO_PASS_THRU_MODE_t; 01618 01619 #define LSM6DSL_ACC_GYRO_PASS_THRU_MODE_MASK 0x04 01620 mems_status_t LSM6DSL_ACC_GYRO_W_PASS_THRU_MODE(void *handle, LSM6DSL_ACC_GYRO_PASS_THRU_MODE_t newValue); 01621 mems_status_t LSM6DSL_ACC_GYRO_R_PASS_THRU_MODE(void *handle, LSM6DSL_ACC_GYRO_PASS_THRU_MODE_t *value); 01622 01623 /******************************************************************************* 01624 * Register : MASTER_CONFIG 01625 * Address : 0X1A 01626 * Bit Group Name: PULL_UP_EN 01627 * Permission : RW 01628 *******************************************************************************/ 01629 typedef enum { 01630 LSM6DSL_ACC_GYRO_PULL_UP_EN_DISABLED =0x00, 01631 LSM6DSL_ACC_GYRO_PULL_UP_EN_ENABLED =0x08, 01632 } LSM6DSL_ACC_GYRO_PULL_UP_EN_t; 01633 01634 #define LSM6DSL_ACC_GYRO_PULL_UP_EN_MASK 0x08 01635 mems_status_t LSM6DSL_ACC_GYRO_W_PULL_UP_EN(void *handle, LSM6DSL_ACC_GYRO_PULL_UP_EN_t newValue); 01636 mems_status_t LSM6DSL_ACC_GYRO_R_PULL_UP_EN(void *handle, LSM6DSL_ACC_GYRO_PULL_UP_EN_t *value); 01637 01638 /******************************************************************************* 01639 * Register : MASTER_CONFIG 01640 * Address : 0X1A 01641 * Bit Group Name: START_CONFIG 01642 * Permission : RW 01643 *******************************************************************************/ 01644 typedef enum { 01645 LSM6DSL_ACC_GYRO_START_CONFIG_XL_G_DRDY =0x00, 01646 LSM6DSL_ACC_GYRO_START_CONFIG_EXT_INT2 =0x10, 01647 } LSM6DSL_ACC_GYRO_START_CONFIG_t; 01648 01649 #define LSM6DSL_ACC_GYRO_START_CONFIG_MASK 0x10 01650 mems_status_t LSM6DSL_ACC_GYRO_W_SensorHUB_Trigger_Sel(void *handle, LSM6DSL_ACC_GYRO_START_CONFIG_t newValue); 01651 mems_status_t LSM6DSL_ACC_GYRO_R_SensorHUB_Trigger_Sel(void *handle, LSM6DSL_ACC_GYRO_START_CONFIG_t *value); 01652 01653 /******************************************************************************* 01654 * Register : MASTER_CONFIG 01655 * Address : 0X1A 01656 * Bit Group Name: DATA_VAL_SEL_FIFO 01657 * Permission : RW 01658 *******************************************************************************/ 01659 typedef enum { 01660 LSM6DSL_ACC_GYRO_DATA_VAL_SEL_FIFO_XL_G_DRDY =0x00, 01661 LSM6DSL_ACC_GYRO_DATA_VAL_SEL_FIFO_SHUB_DRDY =0x40, 01662 } LSM6DSL_ACC_GYRO_DATA_VAL_SEL_FIFO_t; 01663 01664 #define LSM6DSL_ACC_GYRO_DATA_VAL_SEL_FIFO_MASK 0x40 01665 mems_status_t LSM6DSL_ACC_GYRO_W_DATA_VAL_SEL_FIFO(void *handle, LSM6DSL_ACC_GYRO_DATA_VAL_SEL_FIFO_t newValue); 01666 mems_status_t LSM6DSL_ACC_GYRO_R_DATA_VAL_SEL_FIFO(void *handle, LSM6DSL_ACC_GYRO_DATA_VAL_SEL_FIFO_t *value); 01667 01668 /******************************************************************************* 01669 * Register : MASTER_CONFIG 01670 * Address : 0X1A 01671 * Bit Group Name: DRDY_ON_INT1 01672 * Permission : RW 01673 *******************************************************************************/ 01674 typedef enum { 01675 LSM6DSL_ACC_GYRO_DRDY_ON_INT1_DISABLED =0x00, 01676 LSM6DSL_ACC_GYRO_DRDY_ON_INT1_ENABLED =0x80, 01677 } LSM6DSL_ACC_GYRO_DRDY_ON_INT1_t; 01678 01679 #define LSM6DSL_ACC_GYRO_DRDY_ON_INT1_MASK 0x80 01680 mems_status_t LSM6DSL_ACC_GYRO_W_DRDY_ON_INT1(void *handle, LSM6DSL_ACC_GYRO_DRDY_ON_INT1_t newValue); 01681 mems_status_t LSM6DSL_ACC_GYRO_R_DRDY_ON_INT1(void *handle, LSM6DSL_ACC_GYRO_DRDY_ON_INT1_t *value); 01682 01683 /******************************************************************************* 01684 * Register : WAKE_UP_SRC 01685 * Address : 0X1B 01686 * Bit Group Name: Z_WU 01687 * Permission : RO 01688 *******************************************************************************/ 01689 typedef enum { 01690 LSM6DSL_ACC_GYRO_Z_WU_NOT_DETECTED =0x00, 01691 LSM6DSL_ACC_GYRO_Z_WU_DETECTED =0x01, 01692 } LSM6DSL_ACC_GYRO_Z_WU_t; 01693 01694 #define LSM6DSL_ACC_GYRO_Z_WU_MASK 0x01 01695 mems_status_t LSM6DSL_ACC_GYRO_R_Z_WU(void *handle, LSM6DSL_ACC_GYRO_Z_WU_t *value); 01696 01697 /******************************************************************************* 01698 * Register : WAKE_UP_SRC 01699 * Address : 0X1B 01700 * Bit Group Name: Y_WU 01701 * Permission : RO 01702 *******************************************************************************/ 01703 typedef enum { 01704 LSM6DSL_ACC_GYRO_Y_WU_NOT_DETECTED =0x00, 01705 LSM6DSL_ACC_GYRO_Y_WU_DETECTED =0x02, 01706 } LSM6DSL_ACC_GYRO_Y_WU_t; 01707 01708 #define LSM6DSL_ACC_GYRO_Y_WU_MASK 0x02 01709 mems_status_t LSM6DSL_ACC_GYRO_R_Y_WU(void *handle, LSM6DSL_ACC_GYRO_Y_WU_t *value); 01710 01711 /******************************************************************************* 01712 * Register : WAKE_UP_SRC 01713 * Address : 0X1B 01714 * Bit Group Name: X_WU 01715 * Permission : RO 01716 *******************************************************************************/ 01717 typedef enum { 01718 LSM6DSL_ACC_GYRO_X_WU_NOT_DETECTED =0x00, 01719 LSM6DSL_ACC_GYRO_X_WU_DETECTED =0x04, 01720 } LSM6DSL_ACC_GYRO_X_WU_t; 01721 01722 #define LSM6DSL_ACC_GYRO_X_WU_MASK 0x04 01723 mems_status_t LSM6DSL_ACC_GYRO_R_X_WU(void *handle, LSM6DSL_ACC_GYRO_X_WU_t *value); 01724 01725 /******************************************************************************* 01726 * Register : WAKE_UP_SRC 01727 * Address : 0X1B 01728 * Bit Group Name: WU_EV_STATUS 01729 * Permission : RO 01730 *******************************************************************************/ 01731 typedef enum { 01732 LSM6DSL_ACC_GYRO_WU_EV_STATUS_NOT_DETECTED =0x00, 01733 LSM6DSL_ACC_GYRO_WU_EV_STATUS_DETECTED =0x08, 01734 } LSM6DSL_ACC_GYRO_WU_EV_STATUS_t; 01735 01736 #define LSM6DSL_ACC_GYRO_WU_EV_STATUS_MASK 0x08 01737 mems_status_t LSM6DSL_ACC_GYRO_R_WU_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_WU_EV_STATUS_t *value); 01738 01739 /******************************************************************************* 01740 * Register : WAKE_UP_SRC 01741 * Address : 0X1B 01742 * Bit Group Name: SLEEP_EV_STATUS 01743 * Permission : RO 01744 *******************************************************************************/ 01745 typedef enum { 01746 LSM6DSL_ACC_GYRO_SLEEP_EV_STATUS_NOT_DETECTED =0x00, 01747 LSM6DSL_ACC_GYRO_SLEEP_EV_STATUS_DETECTED =0x10, 01748 } LSM6DSL_ACC_GYRO_SLEEP_EV_STATUS_t; 01749 01750 #define LSM6DSL_ACC_GYRO_SLEEP_EV_STATUS_MASK 0x10 01751 mems_status_t LSM6DSL_ACC_GYRO_R_SLEEP_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_SLEEP_EV_STATUS_t *value); 01752 01753 /******************************************************************************* 01754 * Register : WAKE_UP_SRC 01755 * Address : 0X1B 01756 * Bit Group Name: FF_EV_STATUS 01757 * Permission : RO 01758 *******************************************************************************/ 01759 typedef enum { 01760 LSM6DSL_ACC_GYRO_FF_EV_STATUS_NOT_DETECTED =0x00, 01761 LSM6DSL_ACC_GYRO_FF_EV_STATUS_DETECTED =0x20, 01762 } LSM6DSL_ACC_GYRO_FF_EV_STATUS_t; 01763 01764 #define LSM6DSL_ACC_GYRO_FF_EV_STATUS_MASK 0x20 01765 mems_status_t LSM6DSL_ACC_GYRO_R_FF_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_FF_EV_STATUS_t *value); 01766 01767 /******************************************************************************* 01768 * Register : TAP_SRC 01769 * Address : 0X1C 01770 * Bit Group Name: Z_TAP 01771 * Permission : RO 01772 *******************************************************************************/ 01773 typedef enum { 01774 LSM6DSL_ACC_GYRO_Z_TAP_NOT_DETECTED =0x00, 01775 LSM6DSL_ACC_GYRO_Z_TAP_DETECTED =0x01, 01776 } LSM6DSL_ACC_GYRO_Z_TAP_t; 01777 01778 #define LSM6DSL_ACC_GYRO_Z_TAP_MASK 0x01 01779 mems_status_t LSM6DSL_ACC_GYRO_R_Z_TAP(void *handle, LSM6DSL_ACC_GYRO_Z_TAP_t *value); 01780 01781 /******************************************************************************* 01782 * Register : TAP_SRC 01783 * Address : 0X1C 01784 * Bit Group Name: Y_TAP 01785 * Permission : RO 01786 *******************************************************************************/ 01787 typedef enum { 01788 LSM6DSL_ACC_GYRO_Y_TAP_NOT_DETECTED =0x00, 01789 LSM6DSL_ACC_GYRO_Y_TAP_DETECTED =0x02, 01790 } LSM6DSL_ACC_GYRO_Y_TAP_t; 01791 01792 #define LSM6DSL_ACC_GYRO_Y_TAP_MASK 0x02 01793 mems_status_t LSM6DSL_ACC_GYRO_R_Y_TAP(void *handle, LSM6DSL_ACC_GYRO_Y_TAP_t *value); 01794 01795 /******************************************************************************* 01796 * Register : TAP_SRC 01797 * Address : 0X1C 01798 * Bit Group Name: X_TAP 01799 * Permission : RO 01800 *******************************************************************************/ 01801 typedef enum { 01802 LSM6DSL_ACC_GYRO_X_TAP_NOT_DETECTED =0x00, 01803 LSM6DSL_ACC_GYRO_X_TAP_DETECTED =0x04, 01804 } LSM6DSL_ACC_GYRO_X_TAP_t; 01805 01806 #define LSM6DSL_ACC_GYRO_X_TAP_MASK 0x04 01807 mems_status_t LSM6DSL_ACC_GYRO_R_X_TAP(void *handle, LSM6DSL_ACC_GYRO_X_TAP_t *value); 01808 01809 /******************************************************************************* 01810 * Register : TAP_SRC 01811 * Address : 0X1C 01812 * Bit Group Name: TAP_SIGN 01813 * Permission : RO 01814 *******************************************************************************/ 01815 typedef enum { 01816 LSM6DSL_ACC_GYRO_TAP_SIGN_POS_SIGN =0x00, 01817 LSM6DSL_ACC_GYRO_TAP_SIGN_NEG_SIGN =0x08, 01818 } LSM6DSL_ACC_GYRO_TAP_SIGN_t; 01819 01820 #define LSM6DSL_ACC_GYRO_TAP_SIGN_MASK 0x08 01821 mems_status_t LSM6DSL_ACC_GYRO_R_TAP_SIGN(void *handle, LSM6DSL_ACC_GYRO_TAP_SIGN_t *value); 01822 01823 /******************************************************************************* 01824 * Register : TAP_SRC 01825 * Address : 0X1C 01826 * Bit Group Name: DOUBLE_TAP_EV_STATUS 01827 * Permission : RO 01828 *******************************************************************************/ 01829 typedef enum { 01830 LSM6DSL_ACC_GYRO_DOUBLE_TAP_EV_STATUS_NOT_DETECTED =0x00, 01831 LSM6DSL_ACC_GYRO_DOUBLE_TAP_EV_STATUS_DETECTED =0x10, 01832 } LSM6DSL_ACC_GYRO_DOUBLE_TAP_EV_STATUS_t; 01833 01834 #define LSM6DSL_ACC_GYRO_DOUBLE_TAP_EV_STATUS_MASK 0x10 01835 mems_status_t LSM6DSL_ACC_GYRO_R_DOUBLE_TAP_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_DOUBLE_TAP_EV_STATUS_t *value); 01836 01837 /******************************************************************************* 01838 * Register : TAP_SRC 01839 * Address : 0X1C 01840 * Bit Group Name: SINGLE_TAP_EV_STATUS 01841 * Permission : RO 01842 *******************************************************************************/ 01843 typedef enum { 01844 LSM6DSL_ACC_GYRO_SINGLE_TAP_EV_STATUS_NOT_DETECTED =0x00, 01845 LSM6DSL_ACC_GYRO_SINGLE_TAP_EV_STATUS_DETECTED =0x20, 01846 } LSM6DSL_ACC_GYRO_SINGLE_TAP_EV_STATUS_t; 01847 01848 #define LSM6DSL_ACC_GYRO_SINGLE_TAP_EV_STATUS_MASK 0x20 01849 mems_status_t LSM6DSL_ACC_GYRO_R_SINGLE_TAP_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_SINGLE_TAP_EV_STATUS_t *value); 01850 01851 /******************************************************************************* 01852 * Register : TAP_SRC 01853 * Address : 0X1C 01854 * Bit Group Name: TAP_EV_STATUS 01855 * Permission : RO 01856 *******************************************************************************/ 01857 typedef enum { 01858 LSM6DSL_ACC_GYRO_TAP_EV_STATUS_NOT_DETECTED =0x00, 01859 LSM6DSL_ACC_GYRO_TAP_EV_STATUS_DETECTED =0x40, 01860 } LSM6DSL_ACC_GYRO_TAP_EV_STATUS_t; 01861 01862 #define LSM6DSL_ACC_GYRO_TAP_EV_STATUS_MASK 0x40 01863 mems_status_t LSM6DSL_ACC_GYRO_R_TAP_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_TAP_EV_STATUS_t *value); 01864 01865 /******************************************************************************* 01866 * Register : D6D_SRC 01867 * Address : 0X1D 01868 * Bit Group Name: DSD_XL 01869 * Permission : RO 01870 *******************************************************************************/ 01871 typedef enum { 01872 LSM6DSL_ACC_GYRO_DSD_XL_NOT_DETECTED =0x00, 01873 LSM6DSL_ACC_GYRO_DSD_XL_DETECTED =0x01, 01874 } LSM6DSL_ACC_GYRO_DSD_XL_t; 01875 01876 #define LSM6DSL_ACC_GYRO_DSD_XL_MASK 0x01 01877 mems_status_t LSM6DSL_ACC_GYRO_R_DSD_XL(void *handle, LSM6DSL_ACC_GYRO_DSD_XL_t *value); 01878 01879 /******************************************************************************* 01880 * Register : D6D_SRC 01881 * Address : 0X1D 01882 * Bit Group Name: DSD_XH 01883 * Permission : RO 01884 *******************************************************************************/ 01885 typedef enum { 01886 LSM6DSL_ACC_GYRO_DSD_XH_NOT_DETECTED =0x00, 01887 LSM6DSL_ACC_GYRO_DSD_XH_DETECTED =0x02, 01888 } LSM6DSL_ACC_GYRO_DSD_XH_t; 01889 01890 #define LSM6DSL_ACC_GYRO_DSD_XH_MASK 0x02 01891 mems_status_t LSM6DSL_ACC_GYRO_R_DSD_XH(void *handle, LSM6DSL_ACC_GYRO_DSD_XH_t *value); 01892 01893 /******************************************************************************* 01894 * Register : D6D_SRC 01895 * Address : 0X1D 01896 * Bit Group Name: DSD_YL 01897 * Permission : RO 01898 *******************************************************************************/ 01899 typedef enum { 01900 LSM6DSL_ACC_GYRO_DSD_YL_NOT_DETECTED =0x00, 01901 LSM6DSL_ACC_GYRO_DSD_YL_DETECTED =0x04, 01902 } LSM6DSL_ACC_GYRO_DSD_YL_t; 01903 01904 #define LSM6DSL_ACC_GYRO_DSD_YL_MASK 0x04 01905 mems_status_t LSM6DSL_ACC_GYRO_R_DSD_YL(void *handle, LSM6DSL_ACC_GYRO_DSD_YL_t *value); 01906 01907 /******************************************************************************* 01908 * Register : D6D_SRC 01909 * Address : 0X1D 01910 * Bit Group Name: DSD_YH 01911 * Permission : RO 01912 *******************************************************************************/ 01913 typedef enum { 01914 LSM6DSL_ACC_GYRO_DSD_YH_NOT_DETECTED =0x00, 01915 LSM6DSL_ACC_GYRO_DSD_YH_DETECTED =0x08, 01916 } LSM6DSL_ACC_GYRO_DSD_YH_t; 01917 01918 #define LSM6DSL_ACC_GYRO_DSD_YH_MASK 0x08 01919 mems_status_t LSM6DSL_ACC_GYRO_R_DSD_YH(void *handle, LSM6DSL_ACC_GYRO_DSD_YH_t *value); 01920 01921 /******************************************************************************* 01922 * Register : D6D_SRC 01923 * Address : 0X1D 01924 * Bit Group Name: DSD_ZL 01925 * Permission : RO 01926 *******************************************************************************/ 01927 typedef enum { 01928 LSM6DSL_ACC_GYRO_DSD_ZL_NOT_DETECTED =0x00, 01929 LSM6DSL_ACC_GYRO_DSD_ZL_DETECTED =0x10, 01930 } LSM6DSL_ACC_GYRO_DSD_ZL_t; 01931 01932 #define LSM6DSL_ACC_GYRO_DSD_ZL_MASK 0x10 01933 mems_status_t LSM6DSL_ACC_GYRO_R_DSD_ZL(void *handle, LSM6DSL_ACC_GYRO_DSD_ZL_t *value); 01934 01935 /******************************************************************************* 01936 * Register : D6D_SRC 01937 * Address : 0X1D 01938 * Bit Group Name: DSD_ZH 01939 * Permission : RO 01940 *******************************************************************************/ 01941 typedef enum { 01942 LSM6DSL_ACC_GYRO_DSD_ZH_NOT_DETECTED =0x00, 01943 LSM6DSL_ACC_GYRO_DSD_ZH_DETECTED =0x20, 01944 } LSM6DSL_ACC_GYRO_DSD_ZH_t; 01945 01946 #define LSM6DSL_ACC_GYRO_DSD_ZH_MASK 0x20 01947 mems_status_t LSM6DSL_ACC_GYRO_R_DSD_ZH(void *handle, LSM6DSL_ACC_GYRO_DSD_ZH_t *value); 01948 01949 /******************************************************************************* 01950 * Register : D6D_SRC 01951 * Address : 0X1D 01952 * Bit Group Name: D6D_EV_STATUS 01953 * Permission : RO 01954 *******************************************************************************/ 01955 typedef enum { 01956 LSM6DSL_ACC_GYRO_D6D_EV_STATUS_NOT_DETECTED =0x00, 01957 LSM6DSL_ACC_GYRO_D6D_EV_STATUS_DETECTED =0x40, 01958 } LSM6DSL_ACC_GYRO_D6D_EV_STATUS_t; 01959 01960 #define LSM6DSL_ACC_GYRO_D6D_EV_STATUS_MASK 0x40 01961 mems_status_t LSM6DSL_ACC_GYRO_R_D6D_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_D6D_EV_STATUS_t *value); 01962 01963 /******************************************************************************* 01964 * Register : STATUS_REG 01965 * Address : 0X1E 01966 * Bit Group Name: XLDA 01967 * Permission : RO 01968 *******************************************************************************/ 01969 typedef enum { 01970 LSM6DSL_ACC_GYRO_XLDA_NO_DATA_AVAIL =0x00, 01971 LSM6DSL_ACC_GYRO_XLDA_DATA_AVAIL =0x01, 01972 } LSM6DSL_ACC_GYRO_XLDA_t; 01973 01974 #define LSM6DSL_ACC_GYRO_XLDA_MASK 0x01 01975 mems_status_t LSM6DSL_ACC_GYRO_R_XLDA(void *handle, LSM6DSL_ACC_GYRO_XLDA_t *value); 01976 01977 /******************************************************************************* 01978 * Register : STATUS_REG 01979 * Address : 0X1E 01980 * Bit Group Name: GDA 01981 * Permission : RO 01982 *******************************************************************************/ 01983 typedef enum { 01984 LSM6DSL_ACC_GYRO_GDA_NO_DATA_AVAIL =0x00, 01985 LSM6DSL_ACC_GYRO_GDA_DATA_AVAIL =0x02, 01986 } LSM6DSL_ACC_GYRO_GDA_t; 01987 01988 #define LSM6DSL_ACC_GYRO_GDA_MASK 0x02 01989 mems_status_t LSM6DSL_ACC_GYRO_R_GDA(void *handle, LSM6DSL_ACC_GYRO_GDA_t *value); 01990 01991 /******************************************************************************* 01992 * Register : STATUS_REG 01993 * Address : 0X1E 01994 * Bit Group Name: TDA 01995 * Permission : RO 01996 *******************************************************************************/ 01997 typedef enum { 01998 LSM6DSL_ACC_GYRO_TDA_NO_DATA_AVAIL =0x00, 01999 LSM6DSL_ACC_GYRO_TDA_DATA_AVAIL =0x04, 02000 } LSM6DSL_ACC_GYRO_TDA_t; 02001 02002 #define LSM6DSL_ACC_GYRO_TDA_MASK 0x04 02003 mems_status_t LSM6DSL_ACC_GYRO_R_TDA(void *handle, LSM6DSL_ACC_GYRO_TDA_t *value); 02004 02005 /******************************************************************************* 02006 * Register : FIFO_STATUS1 02007 * Address : 0X3A 02008 * Bit Group Name: DIFF_FIFO 02009 * Permission : RO 02010 *******************************************************************************/ 02011 #define LSM6DSL_ACC_GYRO_DIFF_FIFO_STATUS1_MASK 0xFF 02012 #define LSM6DSL_ACC_GYRO_DIFF_FIFO_STATUS1_POSITION 0 02013 #define LSM6DSL_ACC_GYRO_DIFF_FIFO_STATUS2_MASK 0xF 02014 #define LSM6DSL_ACC_GYRO_DIFF_FIFO_STATUS2_POSITION 0 02015 mems_status_t LSM6DSL_ACC_GYRO_R_FIFONumOfEntries(void *handle, u16_t *value); 02016 02017 /******************************************************************************* 02018 * Register : FIFO_STATUS2 02019 * Address : 0X3B 02020 * Bit Group Name: FIFO_EMPTY 02021 * Permission : RO 02022 *******************************************************************************/ 02023 typedef enum { 02024 LSM6DSL_ACC_GYRO_FIFO_EMPTY_FIFO_NOT_EMPTY =0x00, 02025 LSM6DSL_ACC_GYRO_FIFO_EMPTY_FIFO_EMPTY =0x10, 02026 } LSM6DSL_ACC_GYRO_FIFO_EMPTY_t; 02027 02028 #define LSM6DSL_ACC_GYRO_FIFO_EMPTY_MASK 0x10 02029 mems_status_t LSM6DSL_ACC_GYRO_R_FIFOEmpty(void *handle, LSM6DSL_ACC_GYRO_FIFO_EMPTY_t *value); 02030 02031 /******************************************************************************* 02032 * Register : FIFO_STATUS2 02033 * Address : 0X3B 02034 * Bit Group Name: FIFO_FULL 02035 * Permission : RO 02036 *******************************************************************************/ 02037 typedef enum { 02038 LSM6DSL_ACC_GYRO_FIFO_FULL_FIFO_NOT_FULL =0x00, 02039 LSM6DSL_ACC_GYRO_FIFO_FULL_FIFO_FULL =0x20, 02040 } LSM6DSL_ACC_GYRO_FIFO_FULL_t; 02041 02042 #define LSM6DSL_ACC_GYRO_FIFO_FULL_MASK 0x20 02043 mems_status_t LSM6DSL_ACC_GYRO_R_FIFOFull(void *handle, LSM6DSL_ACC_GYRO_FIFO_FULL_t *value); 02044 02045 /******************************************************************************* 02046 * Register : FIFO_STATUS2 02047 * Address : 0X3B 02048 * Bit Group Name: OVERRUN 02049 * Permission : RO 02050 *******************************************************************************/ 02051 typedef enum { 02052 LSM6DSL_ACC_GYRO_OVERRUN_NO_OVERRUN =0x00, 02053 LSM6DSL_ACC_GYRO_OVERRUN_OVERRUN =0x40, 02054 } LSM6DSL_ACC_GYRO_OVERRUN_t; 02055 02056 #define LSM6DSL_ACC_GYRO_OVERRUN_MASK 0x40 02057 mems_status_t LSM6DSL_ACC_GYRO_R_OVERRUN(void *handle, LSM6DSL_ACC_GYRO_OVERRUN_t *value); 02058 02059 /******************************************************************************* 02060 * Register : FIFO_STATUS2 02061 * Address : 0X3B 02062 * Bit Group Name: WTM 02063 * Permission : RO 02064 *******************************************************************************/ 02065 typedef enum { 02066 LSM6DSL_ACC_GYRO_WTM_BELOW_WTM =0x00, 02067 LSM6DSL_ACC_GYRO_WTM_ABOVE_OR_EQUAL_WTM =0x80, 02068 } LSM6DSL_ACC_GYRO_WTM_t; 02069 02070 #define LSM6DSL_ACC_GYRO_WTM_MASK 0x80 02071 mems_status_t LSM6DSL_ACC_GYRO_R_WaterMark(void *handle, LSM6DSL_ACC_GYRO_WTM_t *value); 02072 02073 /******************************************************************************* 02074 * Register : FIFO_STATUS3 02075 * Address : 0X3C 02076 * Bit Group Name: FIFO_PATTERN 02077 * Permission : RO 02078 *******************************************************************************/ 02079 #define LSM6DSL_ACC_GYRO_FIFO_STATUS3_PATTERN_MASK 0xFF 02080 #define LSM6DSL_ACC_GYRO_FIFO_STATUS3_PATTERN_POSITION 0 02081 #define LSM6DSL_ACC_GYRO_FIFO_STATUS4_PATTERN_MASK 0x03 02082 #define LSM6DSL_ACC_GYRO_FIFO_STATUS4_PATTERN_POSITION 0 02083 mems_status_t LSM6DSL_ACC_GYRO_R_FIFOPattern(void *handle, u16_t *value); 02084 02085 /******************************************************************************* 02086 * Register : FUNC_SRC 02087 * Address : 0X53 02088 * Bit Group Name: SENS_HUB_END 02089 * Permission : RO 02090 *******************************************************************************/ 02091 typedef enum { 02092 LSM6DSL_ACC_GYRO_SENS_HUB_END_STILL_ONGOING =0x00, 02093 LSM6DSL_ACC_GYRO_SENS_HUB_END_OP_COMPLETED =0x01, 02094 } LSM6DSL_ACC_GYRO_SENS_HUB_END_t; 02095 02096 #define LSM6DSL_ACC_GYRO_SENS_HUB_END_MASK 0x01 02097 mems_status_t LSM6DSL_ACC_GYRO_R_SENS_HUB_END(void *handle, LSM6DSL_ACC_GYRO_SENS_HUB_END_t *value); 02098 02099 /******************************************************************************* 02100 * Register : FUNC_SRC 02101 * Address : 0X53 02102 * Bit Group Name: SOFT_IRON_END 02103 * Permission : RO 02104 *******************************************************************************/ 02105 typedef enum { 02106 LSM6DSL_ACC_GYRO_SOFT_IRON_END_NOT_COMPLETED =0x00, 02107 LSM6DSL_ACC_GYRO_SOFT_IRON_END_COMPLETED =0x02, 02108 } LSM6DSL_ACC_GYRO_SOFT_IRON_END_t; 02109 02110 #define LSM6DSL_ACC_GYRO_SOFT_IRON_END_MASK 0x02 02111 mems_status_t LSM6DSL_ACC_GYRO_R_SOFT_IRON_END(void *handle, LSM6DSL_ACC_GYRO_SOFT_IRON_END_t *value); 02112 02113 /******************************************************************************* 02114 * Register : FUNC_SRC 02115 * Address : 0X53 02116 * Bit Group Name: HI_FAIL 02117 * Permission : RO 02118 *******************************************************************************/ 02119 typedef enum { 02120 LSM6DSL_ACC_GYRO_HARD_IRON_NORMAL =0x00, 02121 LSM6DSL_ACC_GYRO_HARD_IRON_FAIL =0x04, 02122 } LSM6DSL_ACC_GYRO_SOFT_HARD_IRON_STAT_t; 02123 02124 #define LSM6DSL_ACC_GYRO_HARD_IRON_STAT_MASK 0x04 02125 mems_status_t LSM6DSL_ACC_GYRO_R_HardIron(void *handle, LSM6DSL_ACC_GYRO_SOFT_HARD_IRON_STAT_t *value); 02126 02127 /******************************************************************************* 02128 * Register : FUNC_SRC 02129 * Address : 0X53 02130 * Bit Group Name: STEP_OVERFLOW 02131 * Permission : RO 02132 *******************************************************************************/ 02133 typedef enum { 02134 LSM6DSL_ACC_GYRO_PEDO_STEP_IN_RANGE =0x00, 02135 LSM6DSL_ACC_GYRO_PEDO_ESTEP_OVERFLOW =0x08, 02136 } LSM6DSL_ACC_GYRO_STEP_OVERFLOW_t; 02137 02138 #define LSM6DSL_ACC_GYRO_STEP_OVERFLOW_MASK 0x08 02139 mems_status_t LSM6DSL_ACC_GYRO_R_STEP_OVERFLOW(void *handle, LSM6DSL_ACC_GYRO_STEP_OVERFLOW_t *value); 02140 02141 /******************************************************************************* 02142 * Register : FUNC_SRC 02143 * Address : 0X53 02144 * Bit Group Name: PEDO_EV_STATUS 02145 * Permission : RO 02146 *******************************************************************************/ 02147 typedef enum { 02148 LSM6DSL_ACC_GYRO_PEDO_EV_STATUS_NOT_DETECTED =0x00, 02149 LSM6DSL_ACC_GYRO_PEDO_EV_STATUS_DETECTED =0x10, 02150 } LSM6DSL_ACC_GYRO_PEDO_EV_STATUS_t; 02151 02152 #define LSM6DSL_ACC_GYRO_PEDO_EV_STATUS_MASK 0x10 02153 mems_status_t LSM6DSL_ACC_GYRO_R_PEDO_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_PEDO_EV_STATUS_t *value); 02154 02155 /******************************************************************************* 02156 * Register : FUNC_SRC 02157 * Address : 0X53 02158 * Bit Group Name: TILT_EV_STATUS 02159 * Permission : RO 02160 *******************************************************************************/ 02161 typedef enum { 02162 LSM6DSL_ACC_GYRO_TILT_EV_STATUS_NOT_DETECTED =0x00, 02163 LSM6DSL_ACC_GYRO_TILT_EV_STATUS_DETECTED =0x20, 02164 } LSM6DSL_ACC_GYRO_TILT_EV_STATUS_t; 02165 02166 #define LSM6DSL_ACC_GYRO_TILT_EV_STATUS_MASK 0x20 02167 mems_status_t LSM6DSL_ACC_GYRO_R_TILT_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_TILT_EV_STATUS_t *value); 02168 02169 /******************************************************************************* 02170 * Register : FUNC_SRC 02171 * Address : 0X53 02172 * Bit Group Name: SIGN_MOT_EV_STATUS 02173 * Permission : RO 02174 *******************************************************************************/ 02175 typedef enum { 02176 LSM6DSL_ACC_GYRO_SIGN_MOT_EV_STATUS_NOT_DETECTED =0x00, 02177 LSM6DSL_ACC_GYRO_SIGN_MOT_EV_STATUS_DETECTED =0x40, 02178 } LSM6DSL_ACC_GYRO_SIGN_MOT_EV_STATUS_t; 02179 02180 #define LSM6DSL_ACC_GYRO_SIGN_MOT_EV_STATUS_MASK 0x40 02181 mems_status_t LSM6DSL_ACC_GYRO_R_SIGN_MOT_EV_STATUS(void *handle, LSM6DSL_ACC_GYRO_SIGN_MOT_EV_STATUS_t *value); 02182 02183 /******************************************************************************* 02184 * Register : FUNC_SRC 02185 * Address : 0X53 02186 * Bit Group Name: STEP_COUNT_DELTA_IA 02187 * Permission : RO 02188 *******************************************************************************/ 02189 typedef enum { 02190 LSM6DSL_ACC_GYRO_NO_STEP_COUNT_IN_DELTA =0x00, 02191 LSM6DSL_ACC_GYRO_STEP_COUNT_IN_DELTA =0x80, 02192 } LSM6DSL_ACC_GYRO_STEP_COUNT_DELTA_t; 02193 02194 #define LSM6DSL_ACC_GYRO_STEP_COUNT_DELTA_MASK 0x80 02195 mems_status_t LSM6DSL_ACC_GYRO_R_STEP_COUNT_DELTA(void *handle, LSM6DSL_ACC_GYRO_STEP_COUNT_DELTA_t *value); 02196 02197 /******************************************************************************* 02198 * Register : TAP_CFG1 02199 * Address : 0X58 02200 * Bit Group Name: LIR 02201 * Permission : RW 02202 *******************************************************************************/ 02203 typedef enum { 02204 LSM6DSL_ACC_GYRO_LIR_DISABLED =0x00, 02205 LSM6DSL_ACC_GYRO_LIR_ENABLED =0x01, 02206 } LSM6DSL_ACC_GYRO_LIR_t; 02207 02208 #define LSM6DSL_ACC_GYRO_LIR_MASK 0x01 02209 mems_status_t LSM6DSL_ACC_GYRO_W_LIR(void *handle, LSM6DSL_ACC_GYRO_LIR_t newValue); 02210 mems_status_t LSM6DSL_ACC_GYRO_R_LIR(void *handle, LSM6DSL_ACC_GYRO_LIR_t *value); 02211 02212 /******************************************************************************* 02213 * Register : TAP_CFG1 02214 * Address : 0X58 02215 * Bit Group Name: TAP_Z_EN 02216 * Permission : RW 02217 *******************************************************************************/ 02218 typedef enum { 02219 LSM6DSL_ACC_GYRO_TAP_Z_EN_DISABLED =0x00, 02220 LSM6DSL_ACC_GYRO_TAP_Z_EN_ENABLED =0x02, 02221 } LSM6DSL_ACC_GYRO_TAP_Z_EN_t; 02222 02223 #define LSM6DSL_ACC_GYRO_TAP_Z_EN_MASK 0x02 02224 mems_status_t LSM6DSL_ACC_GYRO_W_TAP_Z_EN(void *handle, LSM6DSL_ACC_GYRO_TAP_Z_EN_t newValue); 02225 mems_status_t LSM6DSL_ACC_GYRO_R_TAP_Z_EN(void *handle, LSM6DSL_ACC_GYRO_TAP_Z_EN_t *value); 02226 02227 /******************************************************************************* 02228 * Register : TAP_CFG1 02229 * Address : 0X58 02230 * Bit Group Name: TAP_Y_EN 02231 * Permission : RW 02232 *******************************************************************************/ 02233 typedef enum { 02234 LSM6DSL_ACC_GYRO_TAP_Y_EN_DISABLED =0x00, 02235 LSM6DSL_ACC_GYRO_TAP_Y_EN_ENABLED =0x04, 02236 } LSM6DSL_ACC_GYRO_TAP_Y_EN_t; 02237 02238 #define LSM6DSL_ACC_GYRO_TAP_Y_EN_MASK 0x04 02239 mems_status_t LSM6DSL_ACC_GYRO_W_TAP_Y_EN(void *handle, LSM6DSL_ACC_GYRO_TAP_Y_EN_t newValue); 02240 mems_status_t LSM6DSL_ACC_GYRO_R_TAP_Y_EN(void *handle, LSM6DSL_ACC_GYRO_TAP_Y_EN_t *value); 02241 02242 /******************************************************************************* 02243 * Register : TAP_CFG1 02244 * Address : 0X58 02245 * Bit Group Name: TAP_X_EN 02246 * Permission : RW 02247 *******************************************************************************/ 02248 typedef enum { 02249 LSM6DSL_ACC_GYRO_TAP_X_EN_DISABLED =0x00, 02250 LSM6DSL_ACC_GYRO_TAP_X_EN_ENABLED =0x08, 02251 } LSM6DSL_ACC_GYRO_TAP_X_EN_t; 02252 02253 #define LSM6DSL_ACC_GYRO_TAP_X_EN_MASK 0x08 02254 mems_status_t LSM6DSL_ACC_GYRO_W_TAP_X_EN(void *handle, LSM6DSL_ACC_GYRO_TAP_X_EN_t newValue); 02255 mems_status_t LSM6DSL_ACC_GYRO_R_TAP_X_EN(void *handle, LSM6DSL_ACC_GYRO_TAP_X_EN_t *value); 02256 /******************************************************************************* 02257 * Register : TAP_CFG1 02258 * Address : 0X58 02259 * Bit Group Name: SLOPE_FDS 02260 * Permission : RW 02261 *******************************************************************************/ 02262 typedef enum { 02263 LSM6DSL_ACC_GYRO_SLOPE_FDS_DISABLED =0x00, 02264 LSM6DSL_ACC_GYRO_SLOPE_FDS_ENABLED =0x10, 02265 } LSM6DSL_ACC_GYRO_SLOPE_FDS_t; 02266 02267 #define LSM6DSL_ACC_GYRO_SLOPE_FDS_MASK 0x10 02268 mems_status_t LSM6DSL_ACC_GYRO_W_SLOPE_FDS(void *handle, LSM6DSL_ACC_GYRO_SLOPE_FDS_t newValue); 02269 mems_status_t LSM6DSL_ACC_GYRO_R_SLOPE_FDS(void *handle, LSM6DSL_ACC_GYRO_SLOPE_FDS_t *value); 02270 02271 /******************************************************************************* 02272 * Register : TAP_CFG1 02273 * Address : 0X58 02274 * Bit Group Name: INTERRUPTS_ENABLE 02275 * Permission : RW 02276 *******************************************************************************/ 02277 typedef enum { 02278 LSM6DSL_ACC_GYRO_BASIC_INT_DISABLED =0x00, 02279 LSM6DSL_ACC_GYRO_BASIC_INT_ENABLED =0x80, 02280 } LSM6DSL_ACC_GYRO_INT_EN_t; 02281 02282 #define LSM6DSL_ACC_GYRO_INT_EN_MASK 0x80 02283 mems_status_t LSM6DSL_ACC_GYRO_W_BASIC_INT(void *handle, LSM6DSL_ACC_GYRO_INT_EN_t newValue); 02284 mems_status_t LSM6DSL_ACC_GYRO_R_BASIC_INT(void *handle, LSM6DSL_ACC_GYRO_INT_EN_t *value); 02285 02286 /******************************************************************************* 02287 * Register : TAP_THS_6D 02288 * Address : 0X59 02289 * Bit Group Name: TAP_THS 02290 * Permission : RW 02291 *******************************************************************************/ 02292 #define LSM6DSL_ACC_GYRO_TAP_THS_MASK 0x1F 02293 #define LSM6DSL_ACC_GYRO_TAP_THS_POSITION 0 02294 mems_status_t LSM6DSL_ACC_GYRO_W_TAP_THS(void *handle, u8_t newValue); 02295 mems_status_t LSM6DSL_ACC_GYRO_R_TAP_THS(void *handle, u8_t *value); 02296 02297 /******************************************************************************* 02298 * Register : TAP_THS_6D 02299 * Address : 0X59 02300 * Bit Group Name: SIXD_THS 02301 * Permission : RW 02302 *******************************************************************************/ 02303 typedef enum { 02304 LSM6DSL_ACC_GYRO_SIXD_THS_80_degree =0x00, 02305 LSM6DSL_ACC_GYRO_SIXD_THS_70_degree =0x20, 02306 LSM6DSL_ACC_GYRO_SIXD_THS_60_degree =0x40, 02307 LSM6DSL_ACC_GYRO_SIXD_THS_50_degree =0x60, 02308 } LSM6DSL_ACC_GYRO_SIXD_THS_t; 02309 02310 #define LSM6DSL_ACC_GYRO_SIXD_THS_MASK 0x60 02311 mems_status_t LSM6DSL_ACC_GYRO_W_SIXD_THS(void *handle, LSM6DSL_ACC_GYRO_SIXD_THS_t newValue); 02312 mems_status_t LSM6DSL_ACC_GYRO_R_SIXD_THS(void *handle, LSM6DSL_ACC_GYRO_SIXD_THS_t *value); 02313 02314 /******************************************************************************* 02315 * Register : TAP_THS_6D 02316 * Address : 0X59 02317 * Bit Group Name: D4D_EN 02318 * Permission : RW 02319 *******************************************************************************/ 02320 typedef enum { 02321 LSM6DSL_ACC_GYRO_D4D_DIS =0x00, 02322 LSM6DSL_ACC_GYRO_D4D_EN =0x80, 02323 } LSM6DSL_ACC_GYRO_D4D_t; 02324 02325 #define LSM6DSL_ACC_GYRO_D4D_MASK 0x80 02326 mems_status_t LSM6DSL_ACC_GYRO_W_D4D(void *handle, LSM6DSL_ACC_GYRO_D4D_t newValue); 02327 mems_status_t LSM6DSL_ACC_GYRO_R_D4D(void *handle, LSM6DSL_ACC_GYRO_D4D_t *value); 02328 02329 /******************************************************************************* 02330 * Register : INT_DUR2 02331 * Address : 0X5A 02332 * Bit Group Name: SHOCK 02333 * Permission : RW 02334 *******************************************************************************/ 02335 #define LSM6DSL_ACC_GYRO_SHOCK_MASK 0x03 02336 #define LSM6DSL_ACC_GYRO_SHOCK_POSITION 0 02337 mems_status_t LSM6DSL_ACC_GYRO_W_SHOCK_Duration(void *handle, u8_t newValue); 02338 mems_status_t LSM6DSL_ACC_GYRO_R_SHOCK_Duration(void *handle, u8_t *value); 02339 02340 /******************************************************************************* 02341 * Register : INT_DUR2 02342 * Address : 0X5A 02343 * Bit Group Name: QUIET 02344 * Permission : RW 02345 *******************************************************************************/ 02346 #define LSM6DSL_ACC_GYRO_QUIET_MASK 0x0C 02347 #define LSM6DSL_ACC_GYRO_QUIET_POSITION 2 02348 mems_status_t LSM6DSL_ACC_GYRO_W_QUIET_Duration(void *handle, u8_t newValue); 02349 mems_status_t LSM6DSL_ACC_GYRO_R_QUIET_Duration(void *handle, u8_t *value); 02350 02351 /******************************************************************************* 02352 * Register : INT_DUR2 02353 * Address : 0X5A 02354 * Bit Group Name: DUR 02355 * Permission : RW 02356 *******************************************************************************/ 02357 #define LSM6DSL_ACC_GYRO_DUR_MASK 0xF0 02358 #define LSM6DSL_ACC_GYRO_DUR_POSITION 4 02359 mems_status_t LSM6DSL_ACC_GYRO_W_DUR(void *handle, u8_t newValue); 02360 mems_status_t LSM6DSL_ACC_GYRO_R_DUR(void *handle, u8_t *value); 02361 02362 /******************************************************************************* 02363 * Register : WAKE_UP_THS 02364 * Address : 0X5B 02365 * Bit Group Name: WK_THS 02366 * Permission : RW 02367 *******************************************************************************/ 02368 #define LSM6DSL_ACC_GYRO_WK_THS_MASK 0x3F 02369 #define LSM6DSL_ACC_GYRO_WK_THS_POSITION 0 02370 mems_status_t LSM6DSL_ACC_GYRO_W_WK_THS(void *handle, u8_t newValue); 02371 mems_status_t LSM6DSL_ACC_GYRO_R_WK_THS(void *handle, u8_t *value); 02372 02373 /******************************************************************************* 02374 * Register : WAKE_UP_THS 02375 * Address : 0X5B 02376 * Bit Group Name: SINGLE_DOUBLE_TAP 02377 * Permission : RW 02378 *******************************************************************************/ 02379 typedef enum { 02380 LSM6DSL_ACC_GYRO_SINGLE_DOUBLE_TAP_SINGLE_TAP =0x00, 02381 LSM6DSL_ACC_GYRO_SINGLE_DOUBLE_TAP_DOUBLE_TAP =0x80, 02382 } LSM6DSL_ACC_GYRO_SINGLE_DOUBLE_TAP_t; 02383 02384 #define LSM6DSL_ACC_GYRO_SINGLE_DOUBLE_TAP_MASK 0x80 02385 mems_status_t LSM6DSL_ACC_GYRO_W_SINGLE_DOUBLE_TAP_EV(void *handle, LSM6DSL_ACC_GYRO_SINGLE_DOUBLE_TAP_t newValue); 02386 mems_status_t LSM6DSL_ACC_GYRO_R_SINGLE_DOUBLE_TAP_EV(void *handle, LSM6DSL_ACC_GYRO_SINGLE_DOUBLE_TAP_t *value); 02387 02388 /******************************************************************************* 02389 * Register : WAKE_UP_DUR 02390 * Address : 0X5C 02391 * Bit Group Name: SLEEP_DUR 02392 * Permission : RW 02393 *******************************************************************************/ 02394 #define LSM6DSL_ACC_GYRO_SLEEP_DUR_MASK 0x0F 02395 #define LSM6DSL_ACC_GYRO_SLEEP_DUR_POSITION 0 02396 mems_status_t LSM6DSL_ACC_GYRO_W_SLEEP_DUR(void *handle, u8_t newValue); 02397 mems_status_t LSM6DSL_ACC_GYRO_R_SLEEP_DUR(void *handle, u8_t *value); 02398 02399 /******************************************************************************* 02400 * Register : WAKE_UP_DUR 02401 * Address : 0X5C 02402 * Bit Group Name: TIMER_HR 02403 * Permission : RW 02404 *******************************************************************************/ 02405 typedef enum { 02406 LSM6DSL_ACC_GYRO_TIMER_HR_6_4ms =0x00, 02407 LSM6DSL_ACC_GYRO_TIMER_HR_25us =0x10, 02408 } LSM6DSL_ACC_GYRO_TIMER_HR_t; 02409 02410 #define LSM6DSL_ACC_GYRO_TIMER_HR_MASK 0x10 02411 mems_status_t LSM6DSL_ACC_GYRO_W_TIMER_HR(void *handle, LSM6DSL_ACC_GYRO_TIMER_HR_t newValue); 02412 mems_status_t LSM6DSL_ACC_GYRO_R_TIMER_HR(void *handle, LSM6DSL_ACC_GYRO_TIMER_HR_t *value); 02413 02414 /******************************************************************************* 02415 * Register : WAKE_UP_DUR 02416 * Address : 0X5C 02417 * Bit Group Name: WAKE_DUR 02418 * Permission : RW 02419 *******************************************************************************/ 02420 #define LSM6DSL_ACC_GYRO_WAKE_DUR_MASK 0x60 02421 #define LSM6DSL_ACC_GYRO_WAKE_DUR_POSITION 5 02422 mems_status_t LSM6DSL_ACC_GYRO_W_WAKE_DUR(void *handle, u8_t newValue); 02423 mems_status_t LSM6DSL_ACC_GYRO_R_WAKE_DUR(void *handle, u8_t *value); 02424 02425 /******************************************************************************* 02426 * Register : FREE_FALL 02427 * Address : 0X5D 02428 * Bit Group Name: FF_DUR 02429 * Permission : RW 02430 *******************************************************************************/ 02431 #define LSM6DSL_ACC_GYRO_FF_FREE_FALL_DUR_MASK 0xF8 02432 #define LSM6DSL_ACC_GYRO_FF_FREE_FALL_DUR_POSITION 3 02433 #define LSM6DSL_ACC_GYRO_FF_WAKE_UP_DUR_MASK 0x80 02434 #define LSM6DSL_ACC_GYRO_FF_WAKE_UP_DUR_POSITION 7 02435 mems_status_t LSM6DSL_ACC_GYRO_W_FF_Duration(void *handle, u8_t newValue); 02436 mems_status_t LSM6DSL_ACC_GYRO_R_FF_Duration(void *handle, u8_t *value); 02437 02438 02439 /******************************************************************************* 02440 * Register : FREE_FALL 02441 * Address : 0X5D 02442 * Bit Group Name: FF_THS 02443 * Permission : RW 02444 *******************************************************************************/ 02445 typedef enum { 02446 LSM6DSL_ACC_GYRO_FF_THS_156mg =0x00, 02447 LSM6DSL_ACC_GYRO_FF_THS_219mg =0x01, 02448 LSM6DSL_ACC_GYRO_FF_THS_250mg =0x02, 02449 LSM6DSL_ACC_GYRO_FF_THS_312mg =0x03, 02450 LSM6DSL_ACC_GYRO_FF_THS_344mg =0x04, 02451 LSM6DSL_ACC_GYRO_FF_THS_406mg =0x05, 02452 LSM6DSL_ACC_GYRO_FF_THS_469mg =0x06, 02453 LSM6DSL_ACC_GYRO_FF_THS_500mg =0x07, 02454 } LSM6DSL_ACC_GYRO_FF_THS_t; 02455 02456 #define LSM6DSL_ACC_GYRO_FF_THS_MASK 0x07 02457 mems_status_t LSM6DSL_ACC_GYRO_W_FF_THS(void *handle, LSM6DSL_ACC_GYRO_FF_THS_t newValue); 02458 mems_status_t LSM6DSL_ACC_GYRO_R_FF_THS(void *handle, LSM6DSL_ACC_GYRO_FF_THS_t *value); 02459 02460 /******************************************************************************* 02461 * Register : MD1_CFG 02462 * Address : 0X5E 02463 * Bit Group Name: INT1_TIMER 02464 * Permission : RW 02465 *******************************************************************************/ 02466 typedef enum { 02467 LSM6DSL_ACC_GYRO_INT1_TIMER_DISABLED =0x00, 02468 LSM6DSL_ACC_GYRO_INT1_TIMER_ENABLED =0x01, 02469 } LSM6DSL_ACC_GYRO_INT1_TIMER_t; 02470 02471 #define LSM6DSL_ACC_GYRO_INT1_TIMER_MASK 0x01 02472 mems_status_t LSM6DSL_ACC_GYRO_W_TimerEvRouteInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_TIMER_t newValue); 02473 mems_status_t LSM6DSL_ACC_GYRO_R_TimerEvRouteInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_TIMER_t *value); 02474 02475 /******************************************************************************* 02476 * Register : MD1_CFG 02477 * Address : 0X5E 02478 * Bit Group Name: INT1_TILT 02479 * Permission : RW 02480 *******************************************************************************/ 02481 typedef enum { 02482 LSM6DSL_ACC_GYRO_INT1_TILT_DISABLED =0x00, 02483 LSM6DSL_ACC_GYRO_INT1_TILT_ENABLED =0x02, 02484 } LSM6DSL_ACC_GYRO_INT1_TILT_t; 02485 02486 #define LSM6DSL_ACC_GYRO_INT1_TILT_MASK 0x02 02487 mems_status_t LSM6DSL_ACC_GYRO_W_TiltEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_TILT_t newValue); 02488 mems_status_t LSM6DSL_ACC_GYRO_R_TiltEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_TILT_t *value); 02489 02490 /******************************************************************************* 02491 * Register : MD1_CFG 02492 * Address : 0X5E 02493 * Bit Group Name: INT1_6D 02494 * Permission : RW 02495 *******************************************************************************/ 02496 typedef enum { 02497 LSM6DSL_ACC_GYRO_INT1_6D_DISABLED =0x00, 02498 LSM6DSL_ACC_GYRO_INT1_6D_ENABLED =0x04, 02499 } LSM6DSL_ACC_GYRO_INT1_6D_t; 02500 02501 #define LSM6DSL_ACC_GYRO_INT1_6D_MASK 0x04 02502 mems_status_t LSM6DSL_ACC_GYRO_W_6DEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_6D_t newValue); 02503 mems_status_t LSM6DSL_ACC_GYRO_R_6DEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_6D_t *value); 02504 02505 /******************************************************************************* 02506 * Register : MD1_CFG 02507 * Address : 0X5E 02508 * Bit Group Name: INT1_TAP 02509 * Permission : RW 02510 *******************************************************************************/ 02511 typedef enum { 02512 LSM6DSL_ACC_GYRO_INT1_TAP_DISABLED =0x00, 02513 LSM6DSL_ACC_GYRO_INT1_TAP_ENABLED =0x08, 02514 } LSM6DSL_ACC_GYRO_INT1_TAP_t; 02515 02516 #define LSM6DSL_ACC_GYRO_INT1_TAP_MASK 0x08 02517 mems_status_t LSM6DSL_ACC_GYRO_W_TapEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_TAP_t newValue); 02518 mems_status_t LSM6DSL_ACC_GYRO_R_TapEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_TAP_t *value); 02519 02520 /******************************************************************************* 02521 * Register : MD1_CFG 02522 * Address : 0X5E 02523 * Bit Group Name: INT1_FF 02524 * Permission : RW 02525 *******************************************************************************/ 02526 typedef enum { 02527 LSM6DSL_ACC_GYRO_INT1_FF_DISABLED =0x00, 02528 LSM6DSL_ACC_GYRO_INT1_FF_ENABLED =0x10, 02529 } LSM6DSL_ACC_GYRO_INT1_FF_t; 02530 02531 #define LSM6DSL_ACC_GYRO_INT1_FF_MASK 0x10 02532 mems_status_t LSM6DSL_ACC_GYRO_W_FFEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_FF_t newValue); 02533 mems_status_t LSM6DSL_ACC_GYRO_R_FFEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_FF_t *value); 02534 02535 /******************************************************************************* 02536 * Register : MD1_CFG 02537 * Address : 0X5E 02538 * Bit Group Name: INT1_WU 02539 * Permission : RW 02540 *******************************************************************************/ 02541 typedef enum { 02542 LSM6DSL_ACC_GYRO_INT1_WU_DISABLED =0x00, 02543 LSM6DSL_ACC_GYRO_INT1_WU_ENABLED =0x20, 02544 } LSM6DSL_ACC_GYRO_INT1_WU_t; 02545 02546 #define LSM6DSL_ACC_GYRO_INT1_WU_MASK 0x20 02547 mems_status_t LSM6DSL_ACC_GYRO_W_WUEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_WU_t newValue); 02548 mems_status_t LSM6DSL_ACC_GYRO_R_WUEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_WU_t *value); 02549 02550 /******************************************************************************* 02551 * Register : MD1_CFG 02552 * Address : 0X5E 02553 * Bit Group Name: INT1_SINGLE_TAP 02554 * Permission : RW 02555 *******************************************************************************/ 02556 typedef enum { 02557 LSM6DSL_ACC_GYRO_INT1_SINGLE_TAP_DISABLED =0x00, 02558 LSM6DSL_ACC_GYRO_INT1_SINGLE_TAP_ENABLED =0x40, 02559 } LSM6DSL_ACC_GYRO_INT1_SINGLE_TAP_t; 02560 02561 #define LSM6DSL_ACC_GYRO_INT1_SINGLE_TAP_MASK 0x40 02562 mems_status_t LSM6DSL_ACC_GYRO_W_SingleTapOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_SINGLE_TAP_t newValue); 02563 mems_status_t LSM6DSL_ACC_GYRO_R_SingleTapOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_SINGLE_TAP_t *value); 02564 02565 /******************************************************************************* 02566 * Register : MD1_CFG 02567 * Address : 0X5E 02568 * Bit Group Name: INT1_INACT_STATE 02569 * Permission : RW 02570 *******************************************************************************/ 02571 typedef enum { 02572 LSM6DSL_ACC_GYRO_INT1_SLEEP_DISABLED =0x00, 02573 LSM6DSL_ACC_GYRO_INT1_SLEEP_ENABLED =0x80, 02574 } LSM6DSL_ACC_GYRO_INT1_SLEEP_t; 02575 02576 #define LSM6DSL_ACC_GYRO_INT1_SLEEP_MASK 0x80 02577 mems_status_t LSM6DSL_ACC_GYRO_W_SleepEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_SLEEP_t newValue); 02578 mems_status_t LSM6DSL_ACC_GYRO_R_SleepEvOnInt1(void *handle, LSM6DSL_ACC_GYRO_INT1_SLEEP_t *value); 02579 02580 /******************************************************************************* 02581 * Register : MD2_CFG 02582 * Address : 0X5F 02583 * Bit Group Name: INT2_IRON 02584 * Permission : RW 02585 *******************************************************************************/ 02586 typedef enum { 02587 LSM6DSL_ACC_GYRO_INT2_IRON_DISABLED =0x00, 02588 LSM6DSL_ACC_GYRO_INT2_IRON_ENABLED =0x01, 02589 } LSM6DSL_ACC_GYRO_INT2_IRON_t; 02590 02591 #define LSM6DSL_ACC_GYRO_INT2_IRON_MASK 0x01 02592 mems_status_t LSM6DSL_ACC_GYRO_W_MagCorrection_Int2(void *handle, LSM6DSL_ACC_GYRO_INT2_IRON_t newValue); 02593 mems_status_t LSM6DSL_ACC_GYRO_R_MagCorrection_Int2(void *handle, LSM6DSL_ACC_GYRO_INT2_IRON_t *value); 02594 02595 /******************************************************************************* 02596 * Register : MD2_CFG 02597 * Address : 0X5F 02598 * Bit Group Name: INT2_TILT 02599 * Permission : RW 02600 *******************************************************************************/ 02601 typedef enum { 02602 LSM6DSL_ACC_GYRO_INT2_TILT_DISABLED =0x00, 02603 LSM6DSL_ACC_GYRO_INT2_TILT_ENABLED =0x02, 02604 } LSM6DSL_ACC_GYRO_INT2_TILT_t; 02605 02606 #define LSM6DSL_ACC_GYRO_INT2_TILT_MASK 0x02 02607 mems_status_t LSM6DSL_ACC_GYRO_W_TiltEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_TILT_t newValue); 02608 mems_status_t LSM6DSL_ACC_GYRO_R_TiltEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_TILT_t *value); 02609 02610 /******************************************************************************* 02611 * Register : MD2_CFG 02612 * Address : 0X5F 02613 * Bit Group Name: INT2_6D 02614 * Permission : RW 02615 *******************************************************************************/ 02616 typedef enum { 02617 LSM6DSL_ACC_GYRO_INT2_6D_DISABLED =0x00, 02618 LSM6DSL_ACC_GYRO_INT2_6D_ENABLED =0x04, 02619 } LSM6DSL_ACC_GYRO_INT2_6D_t; 02620 02621 #define LSM6DSL_ACC_GYRO_INT2_6D_MASK 0x04 02622 mems_status_t LSM6DSL_ACC_GYRO_W_6DEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_6D_t newValue); 02623 mems_status_t LSM6DSL_ACC_GYRO_R_6DEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_6D_t *value); 02624 02625 /******************************************************************************* 02626 * Register : MD2_CFG 02627 * Address : 0X5F 02628 * Bit Group Name: INT2_TAP 02629 * Permission : RW 02630 *******************************************************************************/ 02631 typedef enum { 02632 LSM6DSL_ACC_GYRO_INT2_TAP_DISABLED =0x00, 02633 LSM6DSL_ACC_GYRO_INT2_TAP_ENABLED =0x08, 02634 } LSM6DSL_ACC_GYRO_INT2_TAP_t; 02635 02636 #define LSM6DSL_ACC_GYRO_INT2_TAP_MASK 0x08 02637 mems_status_t LSM6DSL_ACC_GYRO_W_TapEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_TAP_t newValue); 02638 mems_status_t LSM6DSL_ACC_GYRO_R_TapEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_TAP_t *value); 02639 02640 /******************************************************************************* 02641 * Register : MD2_CFG 02642 * Address : 0X5F 02643 * Bit Group Name: INT2_FF 02644 * Permission : RW 02645 *******************************************************************************/ 02646 typedef enum { 02647 LSM6DSL_ACC_GYRO_INT2_FF_DISABLED =0x00, 02648 LSM6DSL_ACC_GYRO_INT2_FF_ENABLED =0x10, 02649 } LSM6DSL_ACC_GYRO_INT2_FF_t; 02650 02651 #define LSM6DSL_ACC_GYRO_INT2_FF_MASK 0x10 02652 mems_status_t LSM6DSL_ACC_GYRO_W_FFEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_FF_t newValue); 02653 mems_status_t LSM6DSL_ACC_GYRO_R_FFEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_FF_t *value); 02654 02655 /******************************************************************************* 02656 * Register : MD2_CFG 02657 * Address : 0X5F 02658 * Bit Group Name: INT2_WU 02659 * Permission : RW 02660 *******************************************************************************/ 02661 typedef enum { 02662 LSM6DSL_ACC_GYRO_INT2_WU_DISABLED =0x00, 02663 LSM6DSL_ACC_GYRO_INT2_WU_ENABLED =0x20, 02664 } LSM6DSL_ACC_GYRO_INT2_WU_t; 02665 02666 #define LSM6DSL_ACC_GYRO_INT2_WU_MASK 0x20 02667 mems_status_t LSM6DSL_ACC_GYRO_W_WUEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_WU_t newValue); 02668 mems_status_t LSM6DSL_ACC_GYRO_R_WUEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_WU_t *value); 02669 02670 /******************************************************************************* 02671 * Register : MD2_CFG 02672 * Address : 0X5F 02673 * Bit Group Name: INT2_SINGLE_TAP 02674 * Permission : RW 02675 *******************************************************************************/ 02676 typedef enum { 02677 LSM6DSL_ACC_GYRO_INT2_SINGLE_TAP_DISABLED =0x00, 02678 LSM6DSL_ACC_GYRO_INT2_SINGLE_TAP_ENABLED =0x40, 02679 } LSM6DSL_ACC_GYRO_INT2_SINGLE_TAP_t; 02680 02681 #define LSM6DSL_ACC_GYRO_INT2_SINGLE_TAP_MASK 0x40 02682 mems_status_t LSM6DSL_ACC_GYRO_W_SingleTapOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_SINGLE_TAP_t newValue); 02683 mems_status_t LSM6DSL_ACC_GYRO_R_SingleTapOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_SINGLE_TAP_t *value); 02684 02685 /******************************************************************************* 02686 * Register : MD2_CFG 02687 * Address : 0X5F 02688 * Bit Group Name: INT2_INACT_STATE 02689 * Permission : RW 02690 *******************************************************************************/ 02691 typedef enum { 02692 LSM6DSL_ACC_GYRO_INT2_SLEEP_DISABLED =0x00, 02693 LSM6DSL_ACC_GYRO_INT2_SLEEP_ENABLED =0x80, 02694 } LSM6DSL_ACC_GYRO_INT2_SLEEP_t; 02695 02696 #define LSM6DSL_ACC_GYRO_INT2_SLEEP_MASK 0x80 02697 mems_status_t LSM6DSL_ACC_GYRO_W_SleepEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_SLEEP_t newValue); 02698 mems_status_t LSM6DSL_ACC_GYRO_R_SleepEvOnInt2(void *handle, LSM6DSL_ACC_GYRO_INT2_SLEEP_t *value); 02699 02700 /******************************************************************************* 02701 * Register : <REGISTER_L> - <REGISTER_H> 02702 * Output Type : GetAccData 02703 * Permission : RO 02704 *******************************************************************************/ 02705 mems_status_t LSM6DSL_ACC_GYRO_GetRawAccData(void *handle, u8_t *buff); 02706 mems_status_t LSM6DSL_ACC_Get_Acceleration(void *handle, int *buff, u8_t from_fifo); 02707 02708 /******************************************************************************* 02709 * Register : <REGISTER_L> - <REGISTER_H> 02710 * Output Type : GetFIFOData 02711 * Permission : RO 02712 *******************************************************************************/ 02713 mems_status_t LSM6DSL_ACC_GYRO_Get_GetFIFOData(void *handle, u8_t *buff); 02714 /******************************************************************************* 02715 * Register : <REGISTER_L> - <REGISTER_H> 02716 * Output Type : GetTimestamp 02717 * Permission : RO 02718 *******************************************************************************/ 02719 mems_status_t LSM6DSL_ACC_GYRO_Get_GetTimestamp(void *handle, u8_t *buff); 02720 /******************************************************************************* 02721 * Register : <REGISTER_L> - <REGISTER_H> 02722 * Output Type : GetStepCounter 02723 * Permission : RO 02724 *******************************************************************************/ 02725 mems_status_t LSM6DSL_ACC_GYRO_Get_GetStepCounter(void *handle, u8_t *buff); 02726 02727 /******************************************************************************* 02728 * Register : <REGISTER_L> - <REGISTER_H> 02729 * Output Type : Pedometer Threshold 02730 * Permission : RO 02731 *******************************************************************************/ 02732 mems_status_t LSM6DSL_ACC_GYRO_W_PedoThreshold(void *handle, u8_t newValue); 02733 02734 /************** Use Sensor Hub *******************/ 02735 02736 /* program to .... */ 02737 mems_status_t LSM6DSL_ACC_GYRO_SH0_Program(void *handle, u8_t SlvAddr, u8_t Reg, u8_t len); 02738 02739 /* Program the six Soft Iron Matrix coefficients. */ 02740 mems_status_t LSM6DSL_ACC_GYRO_SH_init_SI_Matrix(void *handle, u8_t *SI_matrix); 02741 02742 /* Read a remote device through I2C Sensor Hub Slave 0 */ 02743 mems_status_t LSM6DSL_ACC_GYRO_SH0_ReadMem(void *handle, u8_t SlvAddr, u8_t Reg, u8_t *Bufp, u8_t len, u8_t stop); 02744 02745 /* Write a remote device through I2C Sensor Hub Slave 0 */ 02746 mems_status_t LSM6DSL_ACC_GYRO_SH0_WriteByte(void *handle, u8_t SlvAddr, u8_t Reg, u8_t Bufp); 02747 02748 #ifdef __cplusplus 02749 } 02750 #endif 02751 02752 #endif
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