LSM303AGR_acc_driver.h

00001 /**
00002  ******************************************************************************
00003  * @file    LSM303AGR_acc_driver.h
00004  * @author  MEMS Application Team
00005  * @version V1.1
00006  * @date    24-February-2016
00007  * @brief   LSM303AGR Accelerometer header driver file
00008  ******************************************************************************
00009  * @attention
00010  *
00011  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012  *
00013  * Redistribution and use in source and binary forms, with or without modification,
00014  * are permitted provided that the following conditions are met:
00015  *   1. Redistributions of source code must retain the above copyright notice,
00016  *      this list of conditions and the following disclaimer.
00017  *   2. Redistributions in binary form must reproduce the above copyright notice,
00018  *      this list of conditions and the following disclaimer in the documentation
00019  *      and/or other materials provided with the distribution.
00020  *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021  *      may be used to endorse or promote products derived from this software
00022  *      without specific prior written permission.
00023  *
00024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034  *
00035  ******************************************************************************
00036  */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __LSM303AGR_ACC_DRIVER__H
00040 #define __LSM303AGR_ACC_DRIVER__H
00041 
00042 /* Includes ------------------------------------------------------------------*/
00043 #include <stdint.h>
00044 
00045 /* Exported types ------------------------------------------------------------*/
00046 
00047 #ifdef __cplusplus
00048 extern "C" {
00049 #endif
00050 
00051 //these could change accordingly with the architecture
00052 
00053 #ifndef __ARCHDEP__TYPES
00054 #define __ARCHDEP__TYPES
00055 
00056 typedef unsigned char u8_t;
00057 typedef unsigned short int u16_t;
00058 typedef unsigned int u32_t;
00059 typedef int i32_t;
00060 typedef short int i16_t;
00061 typedef signed char i8_t;
00062 
00063 #endif /*__ARCHDEP__TYPES*/
00064 
00065 /* Exported common structure --------------------------------------------------------*/
00066 
00067 #ifndef __SHARED__TYPES
00068 #define __SHARED__TYPES
00069 
00070 typedef union{
00071     i16_t i16bit[3];
00072     u8_t u8bit[6];
00073 } Type3Axis16bit_U; 
00074 
00075 typedef union{
00076     i16_t i16bit;
00077     u8_t u8bit[2];
00078 } Type1Axis16bit_U;
00079 
00080 typedef union{
00081     i32_t i32bit;
00082     u8_t u8bit[4];
00083 } Type1Axis32bit_U;
00084 
00085 typedef enum {
00086   MEMS_SUCCESS = 0x01,
00087   MEMS_ERROR   = 0x00   
00088 } mems_status_t;
00089 
00090 #endif /*__SHARED__TYPES*/
00091 
00092 /* Exported macro ------------------------------------------------------------*/
00093 
00094 /* Exported constants --------------------------------------------------------*/
00095 
00096 /************** I2C Address *****************/
00097 
00098 #define LSM303AGR_ACC_I2C_ADDRESS         0x32
00099 
00100 /************** Who am I  *******************/
00101 
00102 #define LSM303AGR_ACC_WHO_AM_I         0x33
00103 
00104 /* Private Function Prototype -------------------------------------------------------*/
00105 
00106 void LSM303AGR_ACC_SwapHighLowByte(u8_t *bufferToSwap, u8_t numberOfByte, u8_t dimension);
00107 
00108 /* Public Function Prototypes ------------------------------------------------*/
00109 
00110 mems_status_t LSM303AGR_ACC_read_reg( void *handle, u8_t Reg, u8_t* Data );
00111 mems_status_t LSM303AGR_ACC_write_reg( void *handle, u8_t Reg, u8_t Data ); 
00112 
00113 
00114 /************** Device Register  *******************/
00115 #define LSM303AGR_ACC_STATUS_REG_AUX    0X07
00116 #define LSM303AGR_ACC_OUT_ADC1_L    0X08
00117 #define LSM303AGR_ACC_OUT_ADC1_H    0X09
00118 #define LSM303AGR_ACC_OUT_ADC2_L    0X0A
00119 #define LSM303AGR_ACC_OUT_ADC2_H    0X0B
00120 #define LSM303AGR_ACC_OUT_ADC3_L    0X0C
00121 #define LSM303AGR_ACC_OUT_ADC3_H    0X0D
00122 #define LSM303AGR_ACC_INT_COUNTER_REG   0X0E
00123 #define LSM303AGR_ACC_WHO_AM_I_REG      0X0F
00124 #define LSM303AGR_ACC_TEMP_CFG_REG      0X1F
00125 #define LSM303AGR_ACC_CTRL_REG1     0X20
00126 #define LSM303AGR_ACC_CTRL_REG2     0X21
00127 #define LSM303AGR_ACC_CTRL_REG3     0X22
00128 #define LSM303AGR_ACC_CTRL_REG4     0X23
00129 #define LSM303AGR_ACC_CTRL_REG5     0X24
00130 #define LSM303AGR_ACC_CTRL_REG6     0X25
00131 #define LSM303AGR_ACC_REFERENCE     0X26
00132 #define LSM303AGR_ACC_STATUS_REG2   0X27
00133 #define LSM303AGR_ACC_OUT_X_L   0X28
00134 #define LSM303AGR_ACC_OUT_X_H   0X29
00135 #define LSM303AGR_ACC_OUT_Y_L   0X2A
00136 #define LSM303AGR_ACC_OUT_Y_H   0X2B
00137 #define LSM303AGR_ACC_OUT_Z_L   0X2C
00138 #define LSM303AGR_ACC_OUT_Z_H   0X2D
00139 #define LSM303AGR_ACC_FIFO_CTRL_REG     0X2E
00140 #define LSM303AGR_ACC_FIFO_SRC_REG      0X2F
00141 #define LSM303AGR_ACC_INT1_CFG      0X30
00142 #define LSM303AGR_ACC_INT1_SOURCE   0X31
00143 #define LSM303AGR_ACC_INT1_THS      0X32
00144 #define LSM303AGR_ACC_INT1_DURATION     0X33
00145 #define LSM303AGR_ACC_INT2_CFG      0X34
00146 #define LSM303AGR_ACC_INT2_SOURCE   0X35
00147 #define LSM303AGR_ACC_INT2_THS      0X36
00148 #define LSM303AGR_ACC_INT2_DURATION     0X37
00149 #define LSM303AGR_ACC_CLICK_CFG     0X38
00150 #define LSM303AGR_ACC_CLICK_SRC     0X39
00151 #define LSM303AGR_ACC_CLICK_THS     0X3A
00152 #define LSM303AGR_ACC_TIME_LIMIT    0X3B
00153 #define LSM303AGR_ACC_TIME_LATENCY      0X3C
00154 #define LSM303AGR_ACC_TIME_WINDOW   0X3D
00155 
00156 /*******************************************************************************
00157 * Register      : STATUS_REG_AUX
00158 * Address       : 0X07
00159 * Bit Group Name: 1DA
00160 * Permission    : RO
00161 *******************************************************************************/
00162 typedef enum {
00163     LSM303AGR_ACC_1DA_NOT_AVAILABLE          =0x00,
00164     LSM303AGR_ACC_1DA_AVAILABLE          =0x01,
00165 } LSM303AGR_ACC_1DA_t;
00166 
00167 #define       LSM303AGR_ACC_1DA_MASK      0x01
00168 mems_status_t LSM303AGR_ACC_R_x_data_avail(void *handle, LSM303AGR_ACC_1DA_t *value);
00169 
00170 /*******************************************************************************
00171 * Register      : STATUS_REG_AUX
00172 * Address       : 0X07
00173 * Bit Group Name: 2DA_
00174 * Permission    : RO
00175 *******************************************************************************/
00176 typedef enum {
00177     LSM303AGR_ACC_2DA__NOT_AVAILABLE         =0x00,
00178     LSM303AGR_ACC_2DA__AVAILABLE         =0x02,
00179 } LSM303AGR_ACC_2DA__t;
00180 
00181 #define       LSM303AGR_ACC_2DA__MASK     0x02
00182 mems_status_t LSM303AGR_ACC_R_y_data_avail(void *handle, LSM303AGR_ACC_2DA__t *value);
00183 
00184 /*******************************************************************************
00185 * Register      : STATUS_REG_AUX
00186 * Address       : 0X07
00187 * Bit Group Name: 3DA_
00188 * Permission    : RO
00189 *******************************************************************************/
00190 typedef enum {
00191     LSM303AGR_ACC_3DA__NOT_AVAILABLE         =0x00,
00192     LSM303AGR_ACC_3DA__AVAILABLE         =0x04,
00193 } LSM303AGR_ACC_3DA__t;
00194 
00195 #define       LSM303AGR_ACC_3DA__MASK     0x04
00196 mems_status_t LSM303AGR_ACC_R_z_data_avail(void *handle, LSM303AGR_ACC_3DA__t *value);
00197 
00198 /*******************************************************************************
00199 * Register      : STATUS_REG_AUX
00200 * Address       : 0X07
00201 * Bit Group Name: 321DA_
00202 * Permission    : RO
00203 *******************************************************************************/
00204 typedef enum {
00205     LSM303AGR_ACC_321DA__NOT_AVAILABLE       =0x00,
00206     LSM303AGR_ACC_321DA__AVAILABLE       =0x08,
00207 } LSM303AGR_ACC_321DA__t;
00208 
00209 #define       LSM303AGR_ACC_321DA__MASK   0x08
00210 mems_status_t LSM303AGR_ACC_R_xyz_data_avail(void *handle, LSM303AGR_ACC_321DA__t *value);
00211 
00212 /*******************************************************************************
00213 * Register      : STATUS_REG_AUX
00214 * Address       : 0X07
00215 * Bit Group Name: 1OR_
00216 * Permission    : RO
00217 *******************************************************************************/
00218 typedef enum {
00219     LSM303AGR_ACC_1OR__NO_OVERRUN        =0x00,
00220     LSM303AGR_ACC_1OR__OVERRUN       =0x10,
00221 } LSM303AGR_ACC_1OR__t;
00222 
00223 #define       LSM303AGR_ACC_1OR__MASK     0x10
00224 mems_status_t LSM303AGR_ACC_R_DataXOverrun(void *handle, LSM303AGR_ACC_1OR__t *value);
00225 
00226 /*******************************************************************************
00227 * Register      : STATUS_REG_AUX
00228 * Address       : 0X07
00229 * Bit Group Name: 2OR_
00230 * Permission    : RO
00231 *******************************************************************************/
00232 typedef enum {
00233     LSM303AGR_ACC_2OR__NO_OVERRUN        =0x00,
00234     LSM303AGR_ACC_2OR__OVERRUN       =0x20,
00235 } LSM303AGR_ACC_2OR__t;
00236 
00237 #define       LSM303AGR_ACC_2OR__MASK     0x20
00238 mems_status_t LSM303AGR_ACC_R_DataYOverrun(void *handle, LSM303AGR_ACC_2OR__t *value);
00239 
00240 /*******************************************************************************
00241 * Register      : STATUS_REG_AUX
00242 * Address       : 0X07
00243 * Bit Group Name: 3OR_
00244 * Permission    : RO
00245 *******************************************************************************/
00246 typedef enum {
00247     LSM303AGR_ACC_3OR__NO_OVERRUN        =0x00,
00248     LSM303AGR_ACC_3OR__OVERRUN       =0x40,
00249 } LSM303AGR_ACC_3OR__t;
00250 
00251 #define       LSM303AGR_ACC_3OR__MASK     0x40
00252 mems_status_t LSM303AGR_ACC_R_DataZOverrun(void *handle, LSM303AGR_ACC_3OR__t *value);
00253 
00254 /*******************************************************************************
00255 * Register      : STATUS_REG_AUX
00256 * Address       : 0X07
00257 * Bit Group Name: 321OR_
00258 * Permission    : RO
00259 *******************************************************************************/
00260 typedef enum {
00261     LSM303AGR_ACC_321OR__NO_OVERRUN          =0x00,
00262     LSM303AGR_ACC_321OR__OVERRUN         =0x80,
00263 } LSM303AGR_ACC_321OR__t;
00264 
00265 #define       LSM303AGR_ACC_321OR__MASK   0x80
00266 mems_status_t LSM303AGR_ACC_R_DataXYZOverrun(void *handle, LSM303AGR_ACC_321OR__t *value);
00267 
00268 /*******************************************************************************
00269 * Register      : INT_COUNTER_REG
00270 * Address       : 0X0E
00271 * Bit Group Name: IC
00272 * Permission    : RO
00273 *******************************************************************************/
00274 #define       LSM303AGR_ACC_IC_MASK   0xFF
00275 #define       LSM303AGR_ACC_IC_POSITION   0
00276 mems_status_t LSM303AGR_ACC_R_int_counter(void *handle, u8_t *value);
00277 
00278 /*******************************************************************************
00279 * Register      : WHO_AM_I
00280 * Address       : 0X0F
00281 * Bit Group Name: WHO_AM_I
00282 * Permission    : RO
00283 *******************************************************************************/
00284 #define       LSM303AGR_ACC_WHO_AM_I_MASK     0xFF
00285 #define       LSM303AGR_ACC_WHO_AM_I_POSITION     0
00286 mems_status_t LSM303AGR_ACC_R_WHO_AM_I(void *handle, u8_t *value);
00287 
00288 /*******************************************************************************
00289 * Register      : TEMP_CFG_REG
00290 * Address       : 0X1F
00291 * Bit Group Name: TEMP_EN
00292 * Permission    : RW
00293 *******************************************************************************/
00294 typedef enum {
00295     LSM303AGR_ACC_TEMP_EN_DISABLED       =0x00,
00296     LSM303AGR_ACC_TEMP_EN_ENABLED        =0x40,
00297 } LSM303AGR_ACC_TEMP_EN_t;
00298 
00299 #define       LSM303AGR_ACC_TEMP_EN_MASK      0x40
00300 mems_status_t LSM303AGR_ACC_W_TEMP_EN_bits(void *handle, LSM303AGR_ACC_TEMP_EN_t newValue);
00301 mems_status_t LSM303AGR_ACC_R_TEMP_EN_bits(void *handle, LSM303AGR_ACC_TEMP_EN_t *value);
00302 
00303 /*******************************************************************************
00304 * Register      : TEMP_CFG_REG
00305 * Address       : 0X1F
00306 * Bit Group Name: ADC_PD
00307 * Permission    : RW
00308 *******************************************************************************/
00309 typedef enum {
00310     LSM303AGR_ACC_ADC_PD_DISABLED        =0x00,
00311     LSM303AGR_ACC_ADC_PD_ENABLED         =0x80,
00312 } LSM303AGR_ACC_ADC_PD_t;
00313 
00314 #define       LSM303AGR_ACC_ADC_PD_MASK   0x80
00315 mems_status_t LSM303AGR_ACC_W_ADC_PD(void *handle, LSM303AGR_ACC_ADC_PD_t newValue);
00316 mems_status_t LSM303AGR_ACC_R_ADC_PD(void *handle, LSM303AGR_ACC_ADC_PD_t *value);
00317 
00318 /*******************************************************************************
00319 * Register      : CTRL_REG1
00320 * Address       : 0X20
00321 * Bit Group Name: XEN
00322 * Permission    : RW
00323 *******************************************************************************/
00324 typedef enum {
00325     LSM303AGR_ACC_XEN_DISABLED       =0x00,
00326     LSM303AGR_ACC_XEN_ENABLED        =0x01,
00327 } LSM303AGR_ACC_XEN_t;
00328 
00329 #define       LSM303AGR_ACC_XEN_MASK      0x01
00330 mems_status_t LSM303AGR_ACC_W_XEN(void *handle, LSM303AGR_ACC_XEN_t newValue);
00331 mems_status_t LSM303AGR_ACC_R_XEN(void *handle, LSM303AGR_ACC_XEN_t *value);
00332 
00333 /*******************************************************************************
00334 * Register      : CTRL_REG1
00335 * Address       : 0X20
00336 * Bit Group Name: YEN
00337 * Permission    : RW
00338 *******************************************************************************/
00339 typedef enum {
00340     LSM303AGR_ACC_YEN_DISABLED       =0x00,
00341     LSM303AGR_ACC_YEN_ENABLED        =0x02,
00342 } LSM303AGR_ACC_YEN_t;
00343 
00344 #define       LSM303AGR_ACC_YEN_MASK      0x02
00345 mems_status_t LSM303AGR_ACC_W_YEN(void *handle, LSM303AGR_ACC_YEN_t newValue);
00346 mems_status_t LSM303AGR_ACC_R_YEN(void *handle, LSM303AGR_ACC_YEN_t *value);
00347 
00348 /*******************************************************************************
00349 * Register      : CTRL_REG1
00350 * Address       : 0X20
00351 * Bit Group Name: ZEN
00352 * Permission    : RW
00353 *******************************************************************************/
00354 typedef enum {
00355     LSM303AGR_ACC_ZEN_DISABLED       =0x00,
00356     LSM303AGR_ACC_ZEN_ENABLED        =0x04,
00357 } LSM303AGR_ACC_ZEN_t;
00358 
00359 #define       LSM303AGR_ACC_ZEN_MASK      0x04
00360 mems_status_t LSM303AGR_ACC_W_ZEN(void *handle, LSM303AGR_ACC_ZEN_t newValue);
00361 mems_status_t LSM303AGR_ACC_R_ZEN(void *handle, LSM303AGR_ACC_ZEN_t *value);
00362 
00363 /*******************************************************************************
00364 * Register      : CTRL_REG1
00365 * Address       : 0X20
00366 * Bit Group Name: LPEN
00367 * Permission    : RW
00368 *******************************************************************************/
00369 typedef enum {
00370     LSM303AGR_ACC_LPEN_DISABLED          =0x00,
00371     LSM303AGR_ACC_LPEN_ENABLED       =0x08,
00372 } LSM303AGR_ACC_LPEN_t;
00373 
00374 #define       LSM303AGR_ACC_LPEN_MASK     0x08
00375 mems_status_t LSM303AGR_ACC_W_LOWPWR_EN(void *handle, LSM303AGR_ACC_LPEN_t newValue);
00376 mems_status_t LSM303AGR_ACC_R_LOWPWR_EN(void *handle, LSM303AGR_ACC_LPEN_t *value);
00377 
00378 /*******************************************************************************
00379 * Register      : CTRL_REG1
00380 * Address       : 0X20
00381 * Bit Group Name: ODR
00382 * Permission    : RW
00383 *******************************************************************************/
00384 typedef enum {
00385     LSM303AGR_ACC_ODR_DO_PWR_DOWN        =0x00,
00386     LSM303AGR_ACC_ODR_DO_1Hz         =0x10,
00387     LSM303AGR_ACC_ODR_DO_10Hz        =0x20,
00388     LSM303AGR_ACC_ODR_DO_25Hz        =0x30,
00389     LSM303AGR_ACC_ODR_DO_50Hz        =0x40,
00390     LSM303AGR_ACC_ODR_DO_100Hz       =0x50,
00391     LSM303AGR_ACC_ODR_DO_200Hz       =0x60,
00392     LSM303AGR_ACC_ODR_DO_400Hz       =0x70,
00393     LSM303AGR_ACC_ODR_DO_1_6KHz          =0x80,
00394     LSM303AGR_ACC_ODR_DO_1_25KHz         =0x90,
00395 } LSM303AGR_ACC_ODR_t;
00396 
00397 #define       LSM303AGR_ACC_ODR_MASK      0xF0
00398 mems_status_t LSM303AGR_ACC_W_ODR(void *handle, LSM303AGR_ACC_ODR_t newValue);
00399 mems_status_t LSM303AGR_ACC_R_ODR(void *handle, LSM303AGR_ACC_ODR_t *value);
00400 
00401 /*******************************************************************************
00402 * Register      : CTRL_REG2
00403 * Address       : 0X21
00404 * Bit Group Name: HPIS1
00405 * Permission    : RW
00406 *******************************************************************************/
00407 typedef enum {
00408     LSM303AGR_ACC_HPIS1_DISABLED         =0x00,
00409     LSM303AGR_ACC_HPIS1_ENABLED          =0x01,
00410 } LSM303AGR_ACC_HPIS1_t;
00411 
00412 #define       LSM303AGR_ACC_HPIS1_MASK    0x01
00413 mems_status_t LSM303AGR_ACC_W_hpf_aoi_en_int1(void *handle, LSM303AGR_ACC_HPIS1_t newValue);
00414 mems_status_t LSM303AGR_ACC_R_hpf_aoi_en_int1(void *handle, LSM303AGR_ACC_HPIS1_t *value);
00415 
00416 /*******************************************************************************
00417 * Register      : CTRL_REG2
00418 * Address       : 0X21
00419 * Bit Group Name: HPIS2
00420 * Permission    : RW
00421 *******************************************************************************/
00422 typedef enum {
00423     LSM303AGR_ACC_HPIS2_DISABLED         =0x00,
00424     LSM303AGR_ACC_HPIS2_ENABLED          =0x02,
00425 } LSM303AGR_ACC_HPIS2_t;
00426 
00427 #define       LSM303AGR_ACC_HPIS2_MASK    0x02
00428 mems_status_t LSM303AGR_ACC_W_hpf_aoi_en_int2(void *handle, LSM303AGR_ACC_HPIS2_t newValue);
00429 mems_status_t LSM303AGR_ACC_R_hpf_aoi_en_int2(void *handle, LSM303AGR_ACC_HPIS2_t *value);
00430 
00431 /*******************************************************************************
00432 * Register      : CTRL_REG2
00433 * Address       : 0X21
00434 * Bit Group Name: HPCLICK
00435 * Permission    : RW
00436 *******************************************************************************/
00437 typedef enum {
00438     LSM303AGR_ACC_HPCLICK_DISABLED       =0x00,
00439     LSM303AGR_ACC_HPCLICK_ENABLED        =0x04,
00440 } LSM303AGR_ACC_HPCLICK_t;
00441 
00442 #define       LSM303AGR_ACC_HPCLICK_MASK      0x04
00443 mems_status_t LSM303AGR_ACC_W_hpf_click_en(void *handle, LSM303AGR_ACC_HPCLICK_t newValue);
00444 mems_status_t LSM303AGR_ACC_R_hpf_click_en(void *handle, LSM303AGR_ACC_HPCLICK_t *value);
00445 
00446 /*******************************************************************************
00447 * Register      : CTRL_REG2
00448 * Address       : 0X21
00449 * Bit Group Name: FDS
00450 * Permission    : RW
00451 *******************************************************************************/
00452 typedef enum {
00453     LSM303AGR_ACC_FDS_BYPASSED       =0x00,
00454     LSM303AGR_ACC_FDS_ENABLED        =0x08,
00455 } LSM303AGR_ACC_FDS_t;
00456 
00457 #define       LSM303AGR_ACC_FDS_MASK      0x08
00458 mems_status_t LSM303AGR_ACC_W_Data_Filter(void *handle, LSM303AGR_ACC_FDS_t newValue);
00459 mems_status_t LSM303AGR_ACC_R_Data_Filter(void *handle, LSM303AGR_ACC_FDS_t *value);
00460 
00461 /*******************************************************************************
00462 * Register      : CTRL_REG2
00463 * Address       : 0X21
00464 * Bit Group Name: HPCF
00465 * Permission    : RW
00466 *******************************************************************************/
00467 typedef enum {
00468     LSM303AGR_ACC_HPCF_00        =0x00,
00469     LSM303AGR_ACC_HPCF_01        =0x10,
00470     LSM303AGR_ACC_HPCF_10        =0x20,
00471     LSM303AGR_ACC_HPCF_11        =0x30,
00472 } LSM303AGR_ACC_HPCF_t;
00473 
00474 #define       LSM303AGR_ACC_HPCF_MASK     0x30
00475 mems_status_t LSM303AGR_ACC_W_hpf_cutoff_freq(void *handle, LSM303AGR_ACC_HPCF_t newValue);
00476 mems_status_t LSM303AGR_ACC_R_hpf_cutoff_freq(void *handle, LSM303AGR_ACC_HPCF_t *value);
00477 
00478 /*******************************************************************************
00479 * Register      : CTRL_REG2
00480 * Address       : 0X21
00481 * Bit Group Name: HPM
00482 * Permission    : RW
00483 *******************************************************************************/
00484 typedef enum {
00485     LSM303AGR_ACC_HPM_NORMAL         =0x00,
00486     LSM303AGR_ACC_HPM_REFERENCE_SIGNAL       =0x40,
00487     LSM303AGR_ACC_HPM_NORMAL_2       =0x80,
00488     LSM303AGR_ACC_HPM_AUTORST_ON_INT         =0xC0,
00489 } LSM303AGR_ACC_HPM_t;
00490 
00491 #define       LSM303AGR_ACC_HPM_MASK      0xC0
00492 mems_status_t LSM303AGR_ACC_W_hpf_mode(void *handle, LSM303AGR_ACC_HPM_t newValue);
00493 mems_status_t LSM303AGR_ACC_R_hpf_mode(void *handle, LSM303AGR_ACC_HPM_t *value);
00494 
00495 /*******************************************************************************
00496 * Register      : CTRL_REG3
00497 * Address       : 0X22
00498 * Bit Group Name: I1_OVERRUN
00499 * Permission    : RW
00500 *******************************************************************************/
00501 typedef enum {
00502     LSM303AGR_ACC_I1_OVERRUN_DISABLED        =0x00,
00503     LSM303AGR_ACC_I1_OVERRUN_ENABLED         =0x02,
00504 } LSM303AGR_ACC_I1_OVERRUN_t;
00505 
00506 #define       LSM303AGR_ACC_I1_OVERRUN_MASK   0x02
00507 mems_status_t LSM303AGR_ACC_W_FIFO_Overrun_on_INT1(void *handle, LSM303AGR_ACC_I1_OVERRUN_t newValue);
00508 mems_status_t LSM303AGR_ACC_R_FIFO_Overrun_on_INT1(void *handle, LSM303AGR_ACC_I1_OVERRUN_t *value);
00509 
00510 /*******************************************************************************
00511 * Register      : CTRL_REG3
00512 * Address       : 0X22
00513 * Bit Group Name: I1_WTM
00514 * Permission    : RW
00515 *******************************************************************************/
00516 typedef enum {
00517     LSM303AGR_ACC_I1_WTM_DISABLED        =0x00,
00518     LSM303AGR_ACC_I1_WTM_ENABLED         =0x04,
00519 } LSM303AGR_ACC_I1_WTM_t;
00520 
00521 #define       LSM303AGR_ACC_I1_WTM_MASK   0x04
00522 mems_status_t LSM303AGR_ACC_W_FIFO_Watermark_on_INT1(void *handle, LSM303AGR_ACC_I1_WTM_t newValue);
00523 mems_status_t LSM303AGR_ACC_R_FIFO_Watermark_on_INT1(void *handle, LSM303AGR_ACC_I1_WTM_t *value);
00524 
00525 /*******************************************************************************
00526 * Register      : CTRL_REG3
00527 * Address       : 0X22
00528 * Bit Group Name: I1_DRDY2
00529 * Permission    : RW
00530 *******************************************************************************/
00531 typedef enum {
00532     LSM303AGR_ACC_I1_DRDY2_DISABLED          =0x00,
00533     LSM303AGR_ACC_I1_DRDY2_ENABLED       =0x08,
00534 } LSM303AGR_ACC_I1_DRDY2_t;
00535 
00536 #define       LSM303AGR_ACC_I1_DRDY2_MASK     0x08
00537 mems_status_t LSM303AGR_ACC_W_FIFO_DRDY2_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY2_t newValue);
00538 mems_status_t LSM303AGR_ACC_R_FIFO_DRDY2_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY2_t *value);
00539 
00540 /*******************************************************************************
00541 * Register      : CTRL_REG3
00542 * Address       : 0X22
00543 * Bit Group Name: I1_DRDY1
00544 * Permission    : RW
00545 *******************************************************************************/
00546 typedef enum {
00547     LSM303AGR_ACC_I1_DRDY1_DISABLED          =0x00,
00548     LSM303AGR_ACC_I1_DRDY1_ENABLED       =0x10,
00549 } LSM303AGR_ACC_I1_DRDY1_t;
00550 
00551 #define       LSM303AGR_ACC_I1_DRDY1_MASK     0x10
00552 mems_status_t LSM303AGR_ACC_W_FIFO_DRDY1_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY1_t newValue);
00553 mems_status_t LSM303AGR_ACC_R_FIFO_DRDY1_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY1_t *value);
00554 
00555 /*******************************************************************************
00556 * Register      : CTRL_REG3
00557 * Address       : 0X22
00558 * Bit Group Name: I1_AOI2
00559 * Permission    : RW
00560 *******************************************************************************/
00561 typedef enum {
00562     LSM303AGR_ACC_I1_AOI2_DISABLED       =0x00,
00563     LSM303AGR_ACC_I1_AOI2_ENABLED        =0x20,
00564 } LSM303AGR_ACC_I1_AOI2_t;
00565 
00566 #define       LSM303AGR_ACC_I1_AOI2_MASK      0x20
00567 mems_status_t LSM303AGR_ACC_W_FIFO_AOL2_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI2_t newValue);
00568 mems_status_t LSM303AGR_ACC_R_FIFO_AOL2_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI2_t *value);
00569 
00570 /*******************************************************************************
00571 * Register      : CTRL_REG3
00572 * Address       : 0X22
00573 * Bit Group Name: I1_AOI1
00574 * Permission    : RW
00575 *******************************************************************************/
00576 typedef enum {
00577     LSM303AGR_ACC_I1_AOI1_DISABLED       =0x00,
00578     LSM303AGR_ACC_I1_AOI1_ENABLED        =0x40,
00579 } LSM303AGR_ACC_I1_AOI1_t;
00580 
00581 #define       LSM303AGR_ACC_I1_AOI1_MASK      0x40
00582 mems_status_t LSM303AGR_ACC_W_FIFO_AOL1_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI1_t newValue);
00583 mems_status_t LSM303AGR_ACC_R_FIFO_AOL1_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI1_t *value);
00584 
00585 /*******************************************************************************
00586 * Register      : CTRL_REG3
00587 * Address       : 0X22
00588 * Bit Group Name: I1_CLICK
00589 * Permission    : RW
00590 *******************************************************************************/
00591 typedef enum {
00592     LSM303AGR_ACC_I1_CLICK_DISABLED          =0x00,
00593     LSM303AGR_ACC_I1_CLICK_ENABLED       =0x80,
00594 } LSM303AGR_ACC_I1_CLICK_t;
00595 
00596 #define       LSM303AGR_ACC_I1_CLICK_MASK     0x80
00597 mems_status_t LSM303AGR_ACC_W_FIFO_Click_on_INT1(void *handle, LSM303AGR_ACC_I1_CLICK_t newValue);
00598 mems_status_t LSM303AGR_ACC_R_FIFO_Click_on_INT1(void *handle, LSM303AGR_ACC_I1_CLICK_t *value);
00599 
00600 /*******************************************************************************
00601 * Register      : CTRL_REG4
00602 * Address       : 0X23
00603 * Bit Group Name: SIM
00604 * Permission    : RW
00605 *******************************************************************************/
00606 typedef enum {
00607 //    LSM303AGR_ACC_SIM_4_WIRES        =0x00,  // FIXME not allowed by the component
00608     LSM303AGR_ACC_SIM_3_WIRES        =0x01
00609 } LSM303AGR_ACC_SIM_t;
00610 
00611 #define       LSM303AGR_ACC_SIM_MASK      0x01
00612 mems_status_t LSM303AGR_ACC_W_SPI_mode(void *handle, LSM303AGR_ACC_SIM_t newValue);
00613 mems_status_t LSM303AGR_ACC_R_SPI_mode(void *handle, LSM303AGR_ACC_SIM_t *value);
00614 
00615 /*******************************************************************************
00616 * Register      : CTRL_REG4
00617 * Address       : 0X23
00618 * Bit Group Name: ST
00619 * Permission    : RW
00620 *******************************************************************************/
00621 typedef enum {
00622     LSM303AGR_ACC_ST_DISABLED        =0x00,
00623     LSM303AGR_ACC_ST_SELF_TEST_0         =0x02,
00624     LSM303AGR_ACC_ST_SELF_TEST_1         =0x04,
00625     LSM303AGR_ACC_ST_NOT_APPLICABLE          =0x06,
00626 } LSM303AGR_ACC_ST_t;
00627 
00628 #define       LSM303AGR_ACC_ST_MASK   0x06
00629 mems_status_t LSM303AGR_ACC_W_SelfTest(void *handle, LSM303AGR_ACC_ST_t newValue);
00630 mems_status_t LSM303AGR_ACC_R_SelfTest(void *handle, LSM303AGR_ACC_ST_t *value);
00631 
00632 /*******************************************************************************
00633 * Register      : CTRL_REG4
00634 * Address       : 0X23
00635 * Bit Group Name: HR
00636 * Permission    : RW
00637 *******************************************************************************/
00638 typedef enum {
00639     LSM303AGR_ACC_HR_DISABLED        =0x00,
00640     LSM303AGR_ACC_HR_ENABLED         =0x08,
00641 } LSM303AGR_ACC_HR_t;
00642 
00643 #define       LSM303AGR_ACC_HR_MASK   0x08
00644 mems_status_t LSM303AGR_ACC_W_HiRes(void *handle, LSM303AGR_ACC_HR_t newValue);
00645 mems_status_t LSM303AGR_ACC_R_HiRes(void *handle, LSM303AGR_ACC_HR_t *value);
00646 
00647 /*******************************************************************************
00648 * Register      : CTRL_REG4
00649 * Address       : 0X23
00650 * Bit Group Name: FS
00651 * Permission    : RW
00652 *******************************************************************************/
00653 typedef enum {
00654     LSM303AGR_ACC_FS_2G          =0x00,
00655     LSM303AGR_ACC_FS_4G          =0x10,
00656     LSM303AGR_ACC_FS_8G          =0x20,
00657     LSM303AGR_ACC_FS_16G         =0x30,
00658 } LSM303AGR_ACC_FS_t;
00659 
00660 #define       LSM303AGR_ACC_FS_MASK   0x30
00661 mems_status_t LSM303AGR_ACC_W_FullScale(void *handle, LSM303AGR_ACC_FS_t newValue);
00662 mems_status_t LSM303AGR_ACC_R_FullScale(void *handle, LSM303AGR_ACC_FS_t *value);
00663 
00664 /*******************************************************************************
00665 * Register      : CTRL_REG4
00666 * Address       : 0X23
00667 * Bit Group Name: BLE
00668 * Permission    : RW
00669 *******************************************************************************/
00670 typedef enum {
00671     LSM303AGR_ACC_BLE_LITTLE_ENDIAN          =0x00,
00672     LSM303AGR_ACC_BLE_BIG_ENDIAN         =0x40,
00673 } LSM303AGR_ACC_BLE_t;
00674 
00675 #define       LSM303AGR_ACC_BLE_MASK      0x40
00676 mems_status_t LSM303AGR_ACC_W_LittleBigEndian(void *handle, LSM303AGR_ACC_BLE_t newValue);
00677 mems_status_t LSM303AGR_ACC_R_LittleBigEndian(void *handle, LSM303AGR_ACC_BLE_t *value);
00678 
00679 /*******************************************************************************
00680 * Register      : CTRL_REG4
00681 * Address       : 0X23
00682 * Bit Group Name: BDU
00683 * Permission    : RW
00684 *******************************************************************************/
00685 typedef enum {
00686     LSM303AGR_ACC_BDU_DISABLED       =0x00,
00687     LSM303AGR_ACC_BDU_ENABLED        =0x80,
00688 } LSM303AGR_ACC_BDU_t;
00689 
00690 #define       LSM303AGR_ACC_BDU_MASK      0x80
00691 mems_status_t LSM303AGR_ACC_W_BlockDataUpdate(void *handle, LSM303AGR_ACC_BDU_t newValue);
00692 mems_status_t LSM303AGR_ACC_R_BlockDataUpdate(void *handle, LSM303AGR_ACC_BDU_t *value);
00693 
00694 /*******************************************************************************
00695 * Register      : CTRL_REG5
00696 * Address       : 0X24
00697 * Bit Group Name: D4D_INT2
00698 * Permission    : RW
00699 *******************************************************************************/
00700 typedef enum {
00701     LSM303AGR_ACC_D4D_INT2_DISABLED          =0x00,
00702     LSM303AGR_ACC_D4D_INT2_ENABLED       =0x01,
00703 } LSM303AGR_ACC_D4D_INT2_t;
00704 
00705 #define       LSM303AGR_ACC_D4D_INT2_MASK     0x01
00706 mems_status_t LSM303AGR_ACC_W_4D_on_INT2(void *handle, LSM303AGR_ACC_D4D_INT2_t newValue);
00707 mems_status_t LSM303AGR_ACC_R_4D_on_INT2(void *handle, LSM303AGR_ACC_D4D_INT2_t *value);
00708 
00709 /*******************************************************************************
00710 * Register      : CTRL_REG5
00711 * Address       : 0X24
00712 * Bit Group Name: LIR_INT2
00713 * Permission    : RW
00714 *******************************************************************************/
00715 typedef enum {
00716     LSM303AGR_ACC_LIR_INT2_DISABLED          =0x00,
00717     LSM303AGR_ACC_LIR_INT2_ENABLED       =0x02,
00718 } LSM303AGR_ACC_LIR_INT2_t;
00719 
00720 #define       LSM303AGR_ACC_LIR_INT2_MASK     0x02
00721 mems_status_t LSM303AGR_ACC_W_LatchInterrupt_on_INT2(void *handle, LSM303AGR_ACC_LIR_INT2_t newValue);
00722 mems_status_t LSM303AGR_ACC_R_LatchInterrupt_on_INT2(void *handle, LSM303AGR_ACC_LIR_INT2_t *value);
00723 
00724 /*******************************************************************************
00725 * Register      : CTRL_REG5
00726 * Address       : 0X24
00727 * Bit Group Name: D4D_INT1
00728 * Permission    : RW
00729 *******************************************************************************/
00730 typedef enum {
00731     LSM303AGR_ACC_D4D_INT1_DISABLED          =0x00,
00732     LSM303AGR_ACC_D4D_INT1_ENABLED       =0x04,
00733 } LSM303AGR_ACC_D4D_INT1_t;
00734 
00735 #define       LSM303AGR_ACC_D4D_INT1_MASK     0x04
00736 mems_status_t LSM303AGR_ACC_W_4D_on_INT1(void *handle, LSM303AGR_ACC_D4D_INT1_t newValue);
00737 mems_status_t LSM303AGR_ACC_R_4D_on_INT1(void *handle, LSM303AGR_ACC_D4D_INT1_t *value);
00738 
00739 /*******************************************************************************
00740 * Register      : CTRL_REG5
00741 * Address       : 0X24
00742 * Bit Group Name: LIR_INT1
00743 * Permission    : RW
00744 *******************************************************************************/
00745 typedef enum {
00746     LSM303AGR_ACC_LIR_INT1_DISABLED          =0x00,
00747     LSM303AGR_ACC_LIR_INT1_ENABLED       =0x08,
00748 } LSM303AGR_ACC_LIR_INT1_t;
00749 
00750 #define       LSM303AGR_ACC_LIR_INT1_MASK     0x08
00751 mems_status_t LSM303AGR_ACC_W_LatchInterrupt_on_INT1(void *handle, LSM303AGR_ACC_LIR_INT1_t newValue);
00752 mems_status_t LSM303AGR_ACC_R_LatchInterrupt_on_INT1(void *handle, LSM303AGR_ACC_LIR_INT1_t *value);
00753 
00754 /*******************************************************************************
00755 * Register      : CTRL_REG5
00756 * Address       : 0X24
00757 * Bit Group Name: FIFO_EN
00758 * Permission    : RW
00759 *******************************************************************************/
00760 typedef enum {
00761     LSM303AGR_ACC_FIFO_EN_DISABLED       =0x00,
00762     LSM303AGR_ACC_FIFO_EN_ENABLED        =0x40,
00763 } LSM303AGR_ACC_FIFO_EN_t;
00764 
00765 #define       LSM303AGR_ACC_FIFO_EN_MASK      0x40
00766 mems_status_t LSM303AGR_ACC_W_FIFO_EN(void *handle, LSM303AGR_ACC_FIFO_EN_t newValue);
00767 mems_status_t LSM303AGR_ACC_R_FIFO_EN(void *handle, LSM303AGR_ACC_FIFO_EN_t *value);
00768 
00769 /*******************************************************************************
00770 * Register      : CTRL_REG5
00771 * Address       : 0X24
00772 * Bit Group Name: BOOT
00773 * Permission    : RW
00774 *******************************************************************************/
00775 typedef enum {
00776     LSM303AGR_ACC_BOOT_NORMAL_MODE       =0x00,
00777     LSM303AGR_ACC_BOOT_REBOOT        =0x80,
00778 } LSM303AGR_ACC_BOOT_t;
00779 
00780 #define       LSM303AGR_ACC_BOOT_MASK     0x80
00781 mems_status_t LSM303AGR_ACC_W_RebootMemory(void *handle, LSM303AGR_ACC_BOOT_t newValue);
00782 mems_status_t LSM303AGR_ACC_R_RebootMemory(void *handle, LSM303AGR_ACC_BOOT_t *value);
00783 
00784 /*******************************************************************************
00785 * Register      : CTRL_REG6
00786 * Address       : 0X25
00787 * Bit Group Name: H_LACTIVE
00788 * Permission    : RW
00789 *******************************************************************************/
00790 typedef enum {
00791     LSM303AGR_ACC_H_LACTIVE_ACTIVE_HI        =0x00,
00792     LSM303AGR_ACC_H_LACTIVE_ACTIVE_LO        =0x02,
00793 } LSM303AGR_ACC_H_LACTIVE_t;
00794 
00795 #define       LSM303AGR_ACC_H_LACTIVE_MASK    0x02
00796 mems_status_t LSM303AGR_ACC_W_IntActive(void *handle, LSM303AGR_ACC_H_LACTIVE_t newValue);
00797 mems_status_t LSM303AGR_ACC_R_IntActive(void *handle, LSM303AGR_ACC_H_LACTIVE_t *value);
00798 
00799 /*******************************************************************************
00800 * Register      : CTRL_REG6
00801 * Address       : 0X25
00802 * Bit Group Name: P2_ACT
00803 * Permission    : RW
00804 *******************************************************************************/
00805 typedef enum {
00806     LSM303AGR_ACC_P2_ACT_DISABLED        =0x00,
00807     LSM303AGR_ACC_P2_ACT_ENABLED         =0x08,
00808 } LSM303AGR_ACC_P2_ACT_t;
00809 
00810 #define       LSM303AGR_ACC_P2_ACT_MASK   0x08
00811 mems_status_t LSM303AGR_ACC_W_P2_ACT(void *handle, LSM303AGR_ACC_P2_ACT_t newValue);
00812 mems_status_t LSM303AGR_ACC_R_P2_ACT(void *handle, LSM303AGR_ACC_P2_ACT_t *value);
00813 
00814 /*******************************************************************************
00815 * Register      : CTRL_REG6
00816 * Address       : 0X25
00817 * Bit Group Name: BOOT_I1
00818 * Permission    : RW
00819 *******************************************************************************/
00820 typedef enum {
00821     LSM303AGR_ACC_BOOT_I1_DISABLED       =0x00,
00822     LSM303AGR_ACC_BOOT_I1_ENABLED        =0x10,
00823 } LSM303AGR_ACC_BOOT_I1_t;
00824 
00825 #define       LSM303AGR_ACC_BOOT_I1_MASK      0x10
00826 mems_status_t LSM303AGR_ACC_W_Boot_on_INT2(void *handle, LSM303AGR_ACC_BOOT_I1_t newValue);
00827 mems_status_t LSM303AGR_ACC_R_Boot_on_INT2(void *handle, LSM303AGR_ACC_BOOT_I1_t *value);
00828 
00829 /*******************************************************************************
00830 * Register      : CTRL_REG6
00831 * Address       : 0X25
00832 * Bit Group Name: I2_INT2
00833 * Permission    : RW
00834 *******************************************************************************/
00835 typedef enum {
00836     LSM303AGR_ACC_I2_INT2_DISABLED       =0x00,
00837     LSM303AGR_ACC_I2_INT2_ENABLED        =0x20,
00838 } LSM303AGR_ACC_I2_INT2_t;
00839 
00840 #define       LSM303AGR_ACC_I2_INT2_MASK      0x20
00841 mems_status_t LSM303AGR_ACC_W_I2_on_INT2(void *handle, LSM303AGR_ACC_I2_INT2_t newValue);
00842 mems_status_t LSM303AGR_ACC_R_I2_on_INT2(void *handle, LSM303AGR_ACC_I2_INT2_t *value);
00843 
00844 /*******************************************************************************
00845 * Register      : CTRL_REG6
00846 * Address       : 0X25
00847 * Bit Group Name: I2_INT1
00848 * Permission    : RW
00849 *******************************************************************************/
00850 typedef enum {
00851     LSM303AGR_ACC_I2_INT1_DISABLED       =0x00,
00852     LSM303AGR_ACC_I2_INT1_ENABLED        =0x40,
00853 } LSM303AGR_ACC_I2_INT1_t;
00854 
00855 #define       LSM303AGR_ACC_I2_INT1_MASK      0x40
00856 mems_status_t LSM303AGR_ACC_W_I2_on_INT1(void *handle, LSM303AGR_ACC_I2_INT1_t newValue);
00857 mems_status_t LSM303AGR_ACC_R_I2_on_INT1(void *handle, LSM303AGR_ACC_I2_INT1_t *value);
00858 
00859 /*******************************************************************************
00860 * Register      : CTRL_REG6
00861 * Address       : 0X25
00862 * Bit Group Name: I2_CLICKEN
00863 * Permission    : RW
00864 *******************************************************************************/
00865 typedef enum {
00866     LSM303AGR_ACC_I2_CLICKEN_DISABLED        =0x00,
00867     LSM303AGR_ACC_I2_CLICKEN_ENABLED         =0x80,
00868 } LSM303AGR_ACC_I2_CLICKEN_t;
00869 
00870 #define       LSM303AGR_ACC_I2_CLICKEN_MASK   0x80
00871 mems_status_t LSM303AGR_ACC_W_Click_on_INT2(void *handle, LSM303AGR_ACC_I2_CLICKEN_t newValue);
00872 mems_status_t LSM303AGR_ACC_R_Click_on_INT2(void *handle, LSM303AGR_ACC_I2_CLICKEN_t *value);
00873 
00874 /*******************************************************************************
00875 * Register      : REFERENCE
00876 * Address       : 0X26
00877 * Bit Group Name: REF
00878 * Permission    : RW
00879 *******************************************************************************/
00880 #define       LSM303AGR_ACC_REF_MASK      0xFF
00881 #define       LSM303AGR_ACC_REF_POSITION      0
00882 mems_status_t LSM303AGR_ACC_W_ReferenceVal(void *handle, u8_t newValue);
00883 mems_status_t LSM303AGR_ACC_R_ReferenceVal(void *handle, u8_t *value);
00884 
00885 /*******************************************************************************
00886 * Register      : STATUS_REG2
00887 * Address       : 0X27
00888 * Bit Group Name: XDA
00889 * Permission    : RO
00890 *******************************************************************************/
00891 typedef enum {
00892     LSM303AGR_ACC_XDA_NOT_AVAILABLE          =0x00,
00893     LSM303AGR_ACC_XDA_AVAILABLE          =0x01,
00894 } LSM303AGR_ACC_XDA_t;
00895 
00896 #define       LSM303AGR_ACC_XDA_MASK      0x01
00897 mems_status_t LSM303AGR_ACC_R_XDataAvail(void *handle, LSM303AGR_ACC_XDA_t *value);
00898 
00899 /*******************************************************************************
00900 * Register      : STATUS_REG2
00901 * Address       : 0X27
00902 * Bit Group Name: YDA
00903 * Permission    : RO
00904 *******************************************************************************/
00905 typedef enum {
00906     LSM303AGR_ACC_YDA_NOT_AVAILABLE          =0x00,
00907     LSM303AGR_ACC_YDA_AVAILABLE          =0x02,
00908 } LSM303AGR_ACC_YDA_t;
00909 
00910 #define       LSM303AGR_ACC_YDA_MASK      0x02
00911 mems_status_t LSM303AGR_ACC_R_YDataAvail(void *handle, LSM303AGR_ACC_YDA_t *value);
00912 
00913 /*******************************************************************************
00914 * Register      : STATUS_REG2
00915 * Address       : 0X27
00916 * Bit Group Name: ZDA
00917 * Permission    : RO
00918 *******************************************************************************/
00919 typedef enum {
00920     LSM303AGR_ACC_ZDA_NOT_AVAILABLE          =0x00,
00921     LSM303AGR_ACC_ZDA_AVAILABLE          =0x04,
00922 } LSM303AGR_ACC_ZDA_t;
00923 
00924 #define       LSM303AGR_ACC_ZDA_MASK      0x04
00925 mems_status_t LSM303AGR_ACC_R_ZDataAvail(void *handle, LSM303AGR_ACC_ZDA_t *value);
00926 
00927 /*******************************************************************************
00928 * Register      : STATUS_REG2
00929 * Address       : 0X27
00930 * Bit Group Name: ZYXDA
00931 * Permission    : RO
00932 *******************************************************************************/
00933 typedef enum {
00934     LSM303AGR_ACC_ZYXDA_NOT_AVAILABLE        =0x00,
00935     LSM303AGR_ACC_ZYXDA_AVAILABLE        =0x08,
00936 } LSM303AGR_ACC_ZYXDA_t;
00937 
00938 #define       LSM303AGR_ACC_ZYXDA_MASK    0x08
00939 mems_status_t LSM303AGR_ACC_R_XYZDataAvail(void *handle, LSM303AGR_ACC_ZYXDA_t *value);
00940 
00941 /*******************************************************************************
00942 * Register      : STATUS_REG2
00943 * Address       : 0X27
00944 * Bit Group Name: XOR
00945 * Permission    : RO
00946 *******************************************************************************/
00947 typedef enum {
00948     LSM303AGR_ACC_XOR_NO_OVERRUN         =0x00,
00949     LSM303AGR_ACC_XOR_OVERRUN        =0x10,
00950 } LSM303AGR_ACC_XOR_t;
00951 
00952 #define       LSM303AGR_ACC_XOR_MASK      0x10
00953 mems_status_t LSM303AGR_ACC_R_XDataOverrun(void *handle, LSM303AGR_ACC_XOR_t *value);
00954 
00955 /*******************************************************************************
00956 * Register      : STATUS_REG2
00957 * Address       : 0X27
00958 * Bit Group Name: YOR
00959 * Permission    : RO
00960 *******************************************************************************/
00961 typedef enum {
00962     LSM303AGR_ACC_YOR_NO_OVERRUN         =0x00,
00963     LSM303AGR_ACC_YOR_OVERRUN        =0x20,
00964 } LSM303AGR_ACC_YOR_t;
00965 
00966 #define       LSM303AGR_ACC_YOR_MASK      0x20
00967 mems_status_t LSM303AGR_ACC_R_YDataOverrun(void *handle, LSM303AGR_ACC_YOR_t *value);
00968 
00969 /*******************************************************************************
00970 * Register      : STATUS_REG2
00971 * Address       : 0X27
00972 * Bit Group Name: ZOR
00973 * Permission    : RO
00974 *******************************************************************************/
00975 typedef enum {
00976     LSM303AGR_ACC_ZOR_NO_OVERRUN         =0x00,
00977     LSM303AGR_ACC_ZOR_OVERRUN        =0x40,
00978 } LSM303AGR_ACC_ZOR_t;
00979 
00980 #define       LSM303AGR_ACC_ZOR_MASK      0x40
00981 mems_status_t LSM303AGR_ACC_R_ZDataOverrun(void *handle, LSM303AGR_ACC_ZOR_t *value);
00982 
00983 /*******************************************************************************
00984 * Register      : STATUS_REG2
00985 * Address       : 0X27
00986 * Bit Group Name: ZYXOR
00987 * Permission    : RO
00988 *******************************************************************************/
00989 typedef enum {
00990     LSM303AGR_ACC_ZYXOR_NO_OVERRUN       =0x00,
00991     LSM303AGR_ACC_ZYXOR_OVERRUN          =0x80,
00992 } LSM303AGR_ACC_ZYXOR_t;
00993 
00994 #define       LSM303AGR_ACC_ZYXOR_MASK    0x80
00995 mems_status_t LSM303AGR_ACC_R_XYZDataOverrun(void *handle, LSM303AGR_ACC_ZYXOR_t *value);
00996 
00997 /*******************************************************************************
00998 * Register      : FIFO_CTRL_REG
00999 * Address       : 0X2E
01000 * Bit Group Name: FTH
01001 * Permission    : RW
01002 *******************************************************************************/
01003 #define       LSM303AGR_ACC_FTH_MASK      0x1F
01004 #define       LSM303AGR_ACC_FTH_POSITION      0
01005 mems_status_t LSM303AGR_ACC_W_FifoThreshold(void *handle, u8_t newValue);
01006 mems_status_t LSM303AGR_ACC_R_FifoThreshold(void *handle, u8_t *value);
01007 
01008 /*******************************************************************************
01009 * Register      : FIFO_CTRL_REG
01010 * Address       : 0X2E
01011 * Bit Group Name: TR
01012 * Permission    : RW
01013 *******************************************************************************/
01014 typedef enum {
01015     LSM303AGR_ACC_TR_TRIGGER_ON_INT1         =0x00,
01016     LSM303AGR_ACC_TR_TRIGGER_ON_INT2         =0x20,
01017 } LSM303AGR_ACC_TR_t;
01018 
01019 #define       LSM303AGR_ACC_TR_MASK   0x20
01020 mems_status_t LSM303AGR_ACC_W_TriggerSel(void *handle, LSM303AGR_ACC_TR_t newValue);
01021 mems_status_t LSM303AGR_ACC_R_TriggerSel(void *handle, LSM303AGR_ACC_TR_t *value);
01022 
01023 /*******************************************************************************
01024 * Register      : FIFO_CTRL_REG
01025 * Address       : 0X2E
01026 * Bit Group Name: FM
01027 * Permission    : RW
01028 *******************************************************************************/
01029 typedef enum {
01030     LSM303AGR_ACC_FM_BYPASS          =0x00,
01031     LSM303AGR_ACC_FM_FIFO        =0x40,
01032     LSM303AGR_ACC_FM_STREAM          =0x80,
01033     LSM303AGR_ACC_FM_TRIGGER         =0xC0,
01034 } LSM303AGR_ACC_FM_t;
01035 
01036 #define       LSM303AGR_ACC_FM_MASK   0xC0
01037 mems_status_t LSM303AGR_ACC_W_FifoMode(void *handle, LSM303AGR_ACC_FM_t newValue);
01038 mems_status_t LSM303AGR_ACC_R_FifoMode(void *handle, LSM303AGR_ACC_FM_t *value);
01039 
01040 /*******************************************************************************
01041 * Register      : FIFO_SRC_REG
01042 * Address       : 0X2F
01043 * Bit Group Name: FSS
01044 * Permission    : RO
01045 *******************************************************************************/
01046 #define       LSM303AGR_ACC_FSS_MASK      0x1F
01047 #define       LSM303AGR_ACC_FSS_POSITION      0
01048 mems_status_t LSM303AGR_ACC_R_FifoSamplesAvail(void *handle, u8_t *value);
01049 
01050 /*******************************************************************************
01051 * Register      : FIFO_SRC_REG
01052 * Address       : 0X2F
01053 * Bit Group Name: EMPTY
01054 * Permission    : RO
01055 *******************************************************************************/
01056 typedef enum {
01057     LSM303AGR_ACC_EMPTY_NOT_EMPTY        =0x00,
01058     LSM303AGR_ACC_EMPTY_EMPTY        =0x20,
01059 } LSM303AGR_ACC_EMPTY_t;
01060 
01061 #define       LSM303AGR_ACC_EMPTY_MASK    0x20
01062 mems_status_t LSM303AGR_ACC_R_FifoEmpty(void *handle, LSM303AGR_ACC_EMPTY_t *value);
01063 
01064 /*******************************************************************************
01065 * Register      : FIFO_SRC_REG
01066 * Address       : 0X2F
01067 * Bit Group Name: OVRN_FIFO
01068 * Permission    : RO
01069 *******************************************************************************/
01070 typedef enum {
01071     LSM303AGR_ACC_OVRN_FIFO_NO_OVERRUN       =0x00,
01072     LSM303AGR_ACC_OVRN_FIFO_OVERRUN          =0x40,
01073 } LSM303AGR_ACC_OVRN_FIFO_t;
01074 
01075 #define       LSM303AGR_ACC_OVRN_FIFO_MASK    0x40
01076 mems_status_t LSM303AGR_ACC_R_FifoOverrun(void *handle, LSM303AGR_ACC_OVRN_FIFO_t *value);
01077 
01078 /*******************************************************************************
01079 * Register      : FIFO_SRC_REG
01080 * Address       : 0X2F
01081 * Bit Group Name: WTM
01082 * Permission    : RO
01083 *******************************************************************************/
01084 typedef enum {
01085     LSM303AGR_ACC_WTM_NORMAL         =0x00,
01086     LSM303AGR_ACC_WTM_OVERFLOW       =0x80,
01087 } LSM303AGR_ACC_WTM_t;
01088 
01089 #define       LSM303AGR_ACC_WTM_MASK      0x80
01090 mems_status_t LSM303AGR_ACC_R_WatermarkLevel(void *handle, LSM303AGR_ACC_WTM_t *value);
01091 
01092 /*******************************************************************************
01093 * Register      : INT1_CFG/INT2_CFG
01094 * Address       : 0X30/0x34
01095 * Bit Group Name: XLIE
01096 * Permission    : RW
01097 *******************************************************************************/
01098 typedef enum {
01099     LSM303AGR_ACC_XLIE_DISABLED          =0x00,
01100     LSM303AGR_ACC_XLIE_ENABLED       =0x01,
01101 } LSM303AGR_ACC_XLIE_t;
01102 
01103 #define       LSM303AGR_ACC_XLIE_MASK     0x01
01104 mems_status_t LSM303AGR_ACC_W_Int1EnXLo(void *handle, LSM303AGR_ACC_XLIE_t newValue);
01105 mems_status_t LSM303AGR_ACC_R_Int1EnXLo(void *handle, LSM303AGR_ACC_XLIE_t *value);
01106 mems_status_t LSM303AGR_ACC_W_Int2EnXLo(void *handle, LSM303AGR_ACC_XLIE_t newValue);
01107 mems_status_t LSM303AGR_ACC_R_Int2EnXLo(void *handle, LSM303AGR_ACC_XLIE_t *value);
01108 
01109 /*******************************************************************************
01110 * Register      : INT1_CFG/INT2_CFG
01111 * Address       : 0X30/0x34
01112 * Bit Group Name: XHIE
01113 * Permission    : RW
01114 *******************************************************************************/
01115 typedef enum {
01116     LSM303AGR_ACC_XHIE_DISABLED          =0x00,
01117     LSM303AGR_ACC_XHIE_ENABLED       =0x02,
01118 } LSM303AGR_ACC_XHIE_t;
01119 
01120 #define       LSM303AGR_ACC_XHIE_MASK     0x02
01121 mems_status_t LSM303AGR_ACC_W_Int1EnXHi(void *handle, LSM303AGR_ACC_XHIE_t newValue);
01122 mems_status_t LSM303AGR_ACC_R_Int1EnXHi(void *handle, LSM303AGR_ACC_XHIE_t *value);
01123 mems_status_t LSM303AGR_ACC_W_Int2EnXHi(void *handle, LSM303AGR_ACC_XHIE_t newValue);
01124 mems_status_t LSM303AGR_ACC_R_Int2EnXHi(void *handle, LSM303AGR_ACC_XHIE_t *value);
01125 
01126 /*******************************************************************************
01127 * Register      : INT1_CFG/INT2_CFG
01128 * Address       : 0X30/0x34
01129 * Bit Group Name: YLIE
01130 * Permission    : RW
01131 *******************************************************************************/
01132 typedef enum {
01133     LSM303AGR_ACC_YLIE_DISABLED          =0x00,
01134     LSM303AGR_ACC_YLIE_ENABLED       =0x04,
01135 } LSM303AGR_ACC_YLIE_t;
01136 
01137 #define       LSM303AGR_ACC_YLIE_MASK     0x04
01138 mems_status_t LSM303AGR_ACC_W_Int1EnYLo(void *handle, LSM303AGR_ACC_YLIE_t newValue);
01139 mems_status_t LSM303AGR_ACC_R_Int1EnYLo(void *handle, LSM303AGR_ACC_YLIE_t *value);
01140 mems_status_t LSM303AGR_ACC_W_Int2EnYLo(void *handle, LSM303AGR_ACC_YLIE_t newValue);
01141 mems_status_t LSM303AGR_ACC_R_Int2EnYLo(void *handle, LSM303AGR_ACC_YLIE_t *value);
01142 
01143 /*******************************************************************************
01144 * Register      : INT1_CFG/INT2_CFG
01145 * Address       : 0X30/0x34
01146 * Bit Group Name: YHIE
01147 * Permission    : RW
01148 *******************************************************************************/
01149 typedef enum {
01150     LSM303AGR_ACC_YHIE_DISABLED          =0x00,
01151     LSM303AGR_ACC_YHIE_ENABLED       =0x08,
01152 } LSM303AGR_ACC_YHIE_t;
01153 
01154 #define       LSM303AGR_ACC_YHIE_MASK     0x08
01155 mems_status_t LSM303AGR_ACC_W_Int1EnYHi(void *handle, LSM303AGR_ACC_YHIE_t newValue);
01156 mems_status_t LSM303AGR_ACC_R_Int1EnYHi(void *handle, LSM303AGR_ACC_YHIE_t *value);
01157 mems_status_t LSM303AGR_ACC_W_Int2EnYHi(void *handle, LSM303AGR_ACC_YHIE_t newValue);
01158 mems_status_t LSM303AGR_ACC_R_Int2EnYHi(void *handle, LSM303AGR_ACC_YHIE_t *value);
01159 
01160 /*******************************************************************************
01161 * Register      : INT1_CFG/INT2_CFG
01162 * Address       : 0X30/0x34
01163 * Bit Group Name: ZLIE
01164 * Permission    : RW
01165 *******************************************************************************/
01166 typedef enum {
01167     LSM303AGR_ACC_ZLIE_DISABLED          =0x00,
01168     LSM303AGR_ACC_ZLIE_ENABLED       =0x10,
01169 } LSM303AGR_ACC_ZLIE_t;
01170 
01171 #define       LSM303AGR_ACC_ZLIE_MASK     0x10
01172 mems_status_t LSM303AGR_ACC_W_Int1EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t newValue);
01173 mems_status_t LSM303AGR_ACC_R_Int1EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t *value);
01174 mems_status_t LSM303AGR_ACC_W_Int2EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t newValue);
01175 mems_status_t LSM303AGR_ACC_R_Int2EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t *value);
01176 
01177 /*******************************************************************************
01178 * Register      : INT1_CFG/INT2_CFG
01179 * Address       : 0X30/0x34
01180 * Bit Group Name: ZHIE
01181 * Permission    : RW
01182 *******************************************************************************/
01183 typedef enum {
01184     LSM303AGR_ACC_ZHIE_DISABLED          =0x00,
01185     LSM303AGR_ACC_ZHIE_ENABLED       =0x20,
01186 } LSM303AGR_ACC_ZHIE_t;
01187 
01188 #define       LSM303AGR_ACC_ZHIE_MASK     0x20
01189 mems_status_t LSM303AGR_ACC_W_Int1EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t newValue);
01190 mems_status_t LSM303AGR_ACC_R_Int1EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t *value);
01191 mems_status_t LSM303AGR_ACC_W_Int2EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t newValue);
01192 mems_status_t LSM303AGR_ACC_R_Int2EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t *value);
01193 
01194 /*******************************************************************************
01195 * Register      : INT1_CFG/INT2_CFG
01196 * Address       : 0X30/0x34
01197 * Bit Group Name: 6D
01198 * Permission    : RW
01199 *******************************************************************************/
01200 typedef enum {
01201     LSM303AGR_ACC_6D_DISABLED        =0x00,
01202     LSM303AGR_ACC_6D_ENABLED         =0x40,
01203 } LSM303AGR_ACC_6D_t;
01204 
01205 #define       LSM303AGR_ACC_6D_MASK   0x40
01206 mems_status_t LSM303AGR_ACC_W_Int1_6D(void *handle, LSM303AGR_ACC_6D_t newValue);
01207 mems_status_t LSM303AGR_ACC_R_Int1_6D(void *handle, LSM303AGR_ACC_6D_t *value);
01208 mems_status_t LSM303AGR_ACC_W_Int2_6D(void *handle, LSM303AGR_ACC_6D_t newValue);
01209 mems_status_t LSM303AGR_ACC_R_Int2_6D(void *handle, LSM303AGR_ACC_6D_t *value);
01210 
01211 /*******************************************************************************
01212 * Register      : INT1_CFG/INT2_CFG
01213 * Address       : 0X30/0x34
01214 * Bit Group Name: AOI
01215 * Permission    : RW
01216 *******************************************************************************/
01217 typedef enum {
01218     LSM303AGR_ACC_AOI_OR         =0x00,
01219     LSM303AGR_ACC_AOI_AND        =0x80,
01220 } LSM303AGR_ACC_AOI_t;
01221 
01222 #define       LSM303AGR_ACC_AOI_MASK      0x80
01223 mems_status_t LSM303AGR_ACC_W_Int1_AOI(void *handle, LSM303AGR_ACC_AOI_t newValue);
01224 mems_status_t LSM303AGR_ACC_R_Int1_AOI(void *handle, LSM303AGR_ACC_AOI_t *value);
01225 mems_status_t LSM303AGR_ACC_W_Int2_AOI(void *handle, LSM303AGR_ACC_AOI_t newValue);
01226 mems_status_t LSM303AGR_ACC_R_Int2_AOI(void *handle, LSM303AGR_ACC_AOI_t *value);
01227 
01228 /*******************************************************************************
01229 * Register      : INT1_SOURCE/INT2_SOURCE
01230 * Address       : 0X31/0x35
01231 * Bit Group Name: XL
01232 * Permission    : RO
01233 *******************************************************************************/
01234 typedef enum {
01235     LSM303AGR_ACC_XL_DOWN        =0x00,
01236     LSM303AGR_ACC_XL_UP          =0x01,
01237 } LSM303AGR_ACC_XL_t;
01238 
01239 #define       LSM303AGR_ACC_XL_MASK   0x01
01240 mems_status_t LSM303AGR_ACC_R_Int1_Xlo(void *handle, LSM303AGR_ACC_XL_t *value);
01241 mems_status_t LSM303AGR_ACC_R_Int2_Xlo(void *handle, LSM303AGR_ACC_XL_t *value);
01242 
01243 /*******************************************************************************
01244 * Register      : INT1_SOURCE/INT2_SOURCE
01245 * Address       : 0X31/0x35
01246 * Bit Group Name: XH
01247 * Permission    : RO
01248 *******************************************************************************/
01249 typedef enum {
01250     LSM303AGR_ACC_XH_DOWN        =0x00,
01251     LSM303AGR_ACC_XH_UP          =0x02,
01252 } LSM303AGR_ACC_XH_t;
01253 
01254 #define       LSM303AGR_ACC_XH_MASK   0x02
01255 mems_status_t LSM303AGR_ACC_R_Int1_XHi(void *handle, LSM303AGR_ACC_XH_t *value);
01256 mems_status_t LSM303AGR_ACC_R_Int2_XHi(void *handle, LSM303AGR_ACC_XH_t *value);
01257 
01258 /*******************************************************************************
01259 * Register      : INT1_SOURCE/INT2_SOURCE
01260 * Address       : 0X31/0x35
01261 * Bit Group Name: YL
01262 * Permission    : RO
01263 *******************************************************************************/
01264 typedef enum {
01265     LSM303AGR_ACC_YL_DOWN        =0x00,
01266     LSM303AGR_ACC_YL_UP          =0x04,
01267 } LSM303AGR_ACC_YL_t;
01268 
01269 #define       LSM303AGR_ACC_YL_MASK   0x04
01270 mems_status_t LSM303AGR_ACC_R_Int1_YLo(void *handle, LSM303AGR_ACC_YL_t *value);
01271 mems_status_t LSM303AGR_ACC_R_Int2_YLo(void *handle, LSM303AGR_ACC_YL_t *value);
01272 
01273 /*******************************************************************************
01274 * Register      : INT1_SOURCE/INT2_SOURCE
01275 * Address       : 0X31/0x35
01276 * Bit Group Name: YH
01277 * Permission    : RO
01278 *******************************************************************************/
01279 typedef enum {
01280     LSM303AGR_ACC_YH_DOWN        =0x00,
01281     LSM303AGR_ACC_YH_UP          =0x08,
01282 } LSM303AGR_ACC_YH_t;
01283 
01284 #define       LSM303AGR_ACC_YH_MASK   0x08
01285 mems_status_t LSM303AGR_ACC_R_Int1_YHi(void *handle, LSM303AGR_ACC_YH_t *value);
01286 mems_status_t LSM303AGR_ACC_R_Int2_YHi(void *handle, LSM303AGR_ACC_YH_t *value);
01287 
01288 /*******************************************************************************
01289 * Register      : INT1_SOURCE/INT2_SOURCE
01290 * Address       : 0X31/0x35
01291 * Bit Group Name: ZL
01292 * Permission    : RO
01293 *******************************************************************************/
01294 typedef enum {
01295     LSM303AGR_ACC_ZL_DOWN        =0x00,
01296     LSM303AGR_ACC_ZL_UP          =0x10,
01297 } LSM303AGR_ACC_ZL_t;
01298 
01299 #define       LSM303AGR_ACC_ZL_MASK   0x10
01300 mems_status_t LSM303AGR_ACC_R_Int1_Zlo(void *handle, LSM303AGR_ACC_ZL_t *value);
01301 mems_status_t LSM303AGR_ACC_R_Int2_Zlo(void *handle, LSM303AGR_ACC_ZL_t *value);
01302 
01303 /*******************************************************************************
01304 * Register      : INT1_SOURCE/INT2_SOURCE
01305 * Address       : 0X31/0x35
01306 * Bit Group Name: ZH
01307 * Permission    : RO
01308 *******************************************************************************/
01309 typedef enum {
01310     LSM303AGR_ACC_ZH_DOWN        =0x00,
01311     LSM303AGR_ACC_ZH_UP          =0x20,
01312 } LSM303AGR_ACC_ZH_t;
01313 
01314 #define       LSM303AGR_ACC_ZH_MASK   0x20
01315 mems_status_t LSM303AGR_ACC_R_Int1_ZHi(void *handle, LSM303AGR_ACC_ZH_t *value);
01316 mems_status_t LSM303AGR_ACC_R_Int2_ZHi(void *handle, LSM303AGR_ACC_ZH_t *value);
01317 
01318 /*******************************************************************************
01319 * Register      : INT1_SOURCE/INT2_SOURCE
01320 * Address       : 0X31/0x35
01321 * Bit Group Name: IA
01322 * Permission    : RO
01323 *******************************************************************************/
01324 typedef enum {
01325     LSM303AGR_ACC_IA_DOWN        =0x00,
01326     LSM303AGR_ACC_IA_UP          =0x40,
01327 } LSM303AGR_ACC_IA_t;
01328 
01329 #define       LSM303AGR_ACC_IA_MASK   0x40
01330 mems_status_t LSM303AGR_ACC_R_Int1_IA(void *handle, LSM303AGR_ACC_IA_t *value);
01331 mems_status_t LSM303AGR_ACC_R_Int2_IA(void *handle, LSM303AGR_ACC_IA_t *value);
01332 
01333 /*******************************************************************************
01334 * Register      : INT1_THS/INT2_THS
01335 * Address       : 0X32/0x36
01336 * Bit Group Name: THS
01337 * Permission    : RW
01338 *******************************************************************************/
01339 #define       LSM303AGR_ACC_THS_MASK      0x7F
01340 #define       LSM303AGR_ACC_THS_POSITION      0
01341 mems_status_t LSM303AGR_ACC_W_Int1_Threshold(void *handle, u8_t newValue);
01342 mems_status_t LSM303AGR_ACC_R_Int1_Threshold(void *handle, u8_t *value);
01343 mems_status_t LSM303AGR_ACC_W_Int2_Threshold(void *handle, u8_t newValue);
01344 mems_status_t LSM303AGR_ACC_R_Int2_Threshold(void *handle, u8_t *value);
01345 
01346 /*******************************************************************************
01347 * Register      : INT1_DURATION/INT2_DURATION
01348 * Address       : 0X33/0x37
01349 * Bit Group Name: D
01350 * Permission    : RW
01351 *******************************************************************************/
01352 #define       LSM303AGR_ACC_D_MASK    0x7F
01353 #define       LSM303AGR_ACC_D_POSITION    0
01354 mems_status_t LSM303AGR_ACC_W_Int1_Duration(void *handle, u8_t newValue);
01355 mems_status_t LSM303AGR_ACC_R_Int1_Duration(void *handle, u8_t *value);
01356 mems_status_t LSM303AGR_ACC_W_Int2_Duration(void *handle, u8_t newValue);
01357 mems_status_t LSM303AGR_ACC_R_Int2_Duration(void *handle, u8_t *value);
01358 
01359 /*******************************************************************************
01360 * Register      : CLICK_CFG
01361 * Address       : 0X38
01362 * Bit Group Name: XS
01363 * Permission    : RW
01364 *******************************************************************************/
01365 typedef enum {
01366     LSM303AGR_ACC_XS_DISABLED        =0x00,
01367     LSM303AGR_ACC_XS_ENABLED         =0x01,
01368 } LSM303AGR_ACC_XS_t;
01369 
01370 #define       LSM303AGR_ACC_XS_MASK   0x01
01371 mems_status_t LSM303AGR_ACC_W_XSingle(void *handle, LSM303AGR_ACC_XS_t newValue);
01372 mems_status_t LSM303AGR_ACC_R_XSingle(void *handle, LSM303AGR_ACC_XS_t *value);
01373 
01374 /*******************************************************************************
01375 * Register      : CLICK_CFG
01376 * Address       : 0X38
01377 * Bit Group Name: XD
01378 * Permission    : RW
01379 *******************************************************************************/
01380 typedef enum {
01381     LSM303AGR_ACC_XD_DISABLED        =0x00,
01382     LSM303AGR_ACC_XD_ENABLED         =0x02,
01383 } LSM303AGR_ACC_XD_t;
01384 
01385 #define       LSM303AGR_ACC_XD_MASK   0x02
01386 mems_status_t LSM303AGR_ACC_W_XDouble(void *handle, LSM303AGR_ACC_XD_t newValue);
01387 mems_status_t LSM303AGR_ACC_R_XDouble(void *handle, LSM303AGR_ACC_XD_t *value);
01388 
01389 /*******************************************************************************
01390 * Register      : CLICK_CFG
01391 * Address       : 0X38
01392 * Bit Group Name: YS
01393 * Permission    : RW
01394 *******************************************************************************/
01395 typedef enum {
01396     LSM303AGR_ACC_YS_DISABLED        =0x00,
01397     LSM303AGR_ACC_YS_ENABLED         =0x04,
01398 } LSM303AGR_ACC_YS_t;
01399 
01400 #define       LSM303AGR_ACC_YS_MASK   0x04
01401 mems_status_t LSM303AGR_ACC_W_YSingle(void *handle, LSM303AGR_ACC_YS_t newValue);
01402 mems_status_t LSM303AGR_ACC_R_YSingle(void *handle, LSM303AGR_ACC_YS_t *value);
01403 
01404 /*******************************************************************************
01405 * Register      : CLICK_CFG
01406 * Address       : 0X38
01407 * Bit Group Name: YD
01408 * Permission    : RW
01409 *******************************************************************************/
01410 typedef enum {
01411     LSM303AGR_ACC_YD_DISABLED        =0x00,
01412     LSM303AGR_ACC_YD_ENABLED         =0x08,
01413 } LSM303AGR_ACC_YD_t;
01414 
01415 #define       LSM303AGR_ACC_YD_MASK   0x08
01416 mems_status_t LSM303AGR_ACC_W_YDouble(void *handle, LSM303AGR_ACC_YD_t newValue);
01417 mems_status_t LSM303AGR_ACC_R_YDouble(void *handle, LSM303AGR_ACC_YD_t *value);
01418 
01419 /*******************************************************************************
01420 * Register      : CLICK_CFG
01421 * Address       : 0X38
01422 * Bit Group Name: ZS
01423 * Permission    : RW
01424 *******************************************************************************/
01425 typedef enum {
01426     LSM303AGR_ACC_ZS_DISABLED        =0x00,
01427     LSM303AGR_ACC_ZS_ENABLED         =0x10,
01428 } LSM303AGR_ACC_ZS_t;
01429 
01430 #define       LSM303AGR_ACC_ZS_MASK   0x10
01431 mems_status_t LSM303AGR_ACC_W_ZSingle(void *handle, LSM303AGR_ACC_ZS_t newValue);
01432 mems_status_t LSM303AGR_ACC_R_ZSingle(void *handle, LSM303AGR_ACC_ZS_t *value);
01433 
01434 /*******************************************************************************
01435 * Register      : CLICK_CFG
01436 * Address       : 0X38
01437 * Bit Group Name: ZD
01438 * Permission    : RW
01439 *******************************************************************************/
01440 typedef enum {
01441     LSM303AGR_ACC_ZD_DISABLED        =0x00,
01442     LSM303AGR_ACC_ZD_ENABLED         =0x20,
01443 } LSM303AGR_ACC_ZD_t;
01444 
01445 #define       LSM303AGR_ACC_ZD_MASK   0x20
01446 mems_status_t LSM303AGR_ACC_W_ZDouble(void *handle, LSM303AGR_ACC_ZD_t newValue);
01447 mems_status_t LSM303AGR_ACC_R_ZDouble(void *handle, LSM303AGR_ACC_ZD_t *value);
01448 
01449 /*******************************************************************************
01450 * Register      : CLICK_SRC
01451 * Address       : 0X39
01452 * Bit Group Name: X
01453 * Permission    : RO
01454 *******************************************************************************/
01455 typedef enum {
01456     LSM303AGR_ACC_X_DOWN         =0x00,
01457     LSM303AGR_ACC_X_UP       =0x01,
01458 } LSM303AGR_ACC_X_t;
01459 
01460 #define       LSM303AGR_ACC_X_MASK    0x01
01461 mems_status_t LSM303AGR_ACC_R_ClickX(void *handle, LSM303AGR_ACC_X_t *value);
01462 
01463 /*******************************************************************************
01464 * Register      : CLICK_SRC
01465 * Address       : 0X39
01466 * Bit Group Name: Y
01467 * Permission    : RO
01468 *******************************************************************************/
01469 typedef enum {
01470     LSM303AGR_ACC_Y_DOWN         =0x00,
01471     LSM303AGR_ACC_Y_UP       =0x02,
01472 } LSM303AGR_ACC_Y_t;
01473 
01474 #define       LSM303AGR_ACC_Y_MASK    0x02
01475 mems_status_t LSM303AGR_ACC_R_ClickY(void *handle, LSM303AGR_ACC_Y_t *value);
01476 
01477 /*******************************************************************************
01478 * Register      : CLICK_SRC
01479 * Address       : 0X39
01480 * Bit Group Name: Z
01481 * Permission    : RO
01482 *******************************************************************************/
01483 typedef enum {
01484     LSM303AGR_ACC_Z_DOWN         =0x00,
01485     LSM303AGR_ACC_Z_UP       =0x04,
01486 } LSM303AGR_ACC_Z_t;
01487 
01488 #define       LSM303AGR_ACC_Z_MASK    0x04
01489 mems_status_t LSM303AGR_ACC_R_ClickZ(void *handle, LSM303AGR_ACC_Z_t *value);
01490 
01491 /*******************************************************************************
01492 * Register      : CLICK_SRC
01493 * Address       : 0X39
01494 * Bit Group Name: SIGN
01495 * Permission    : RO
01496 *******************************************************************************/
01497 typedef enum {
01498     LSM303AGR_ACC_SIGN_POSITIVE          =0x00,
01499     LSM303AGR_ACC_SIGN_NEGATIVE          =0x08,
01500 } LSM303AGR_ACC_SIGN_t;
01501 
01502 #define       LSM303AGR_ACC_SIGN_MASK     0x08
01503 mems_status_t LSM303AGR_ACC_R_ClickSign(void *handle, LSM303AGR_ACC_SIGN_t *value);
01504 
01505 /*******************************************************************************
01506 * Register      : CLICK_SRC
01507 * Address       : 0X39
01508 * Bit Group Name: SCLICK
01509 * Permission    : RO
01510 *******************************************************************************/
01511 typedef enum {
01512     LSM303AGR_ACC_SCLICK_DISABLED        =0x00,
01513     LSM303AGR_ACC_SCLICK_ENABLED         =0x10,
01514 } LSM303AGR_ACC_SCLICK_t;
01515 
01516 #define       LSM303AGR_ACC_SCLICK_MASK   0x10
01517 mems_status_t LSM303AGR_ACC_R_SingleCLICK(void *handle, LSM303AGR_ACC_SCLICK_t *value);
01518 
01519 /*******************************************************************************
01520 * Register      : CLICK_SRC
01521 * Address       : 0X39
01522 * Bit Group Name: DCLICK
01523 * Permission    : RO
01524 *******************************************************************************/
01525 typedef enum {
01526     LSM303AGR_ACC_DCLICK_DISABLED        =0x00,
01527     LSM303AGR_ACC_DCLICK_ENABLED         =0x20,
01528 } LSM303AGR_ACC_DCLICK_t;
01529 
01530 #define       LSM303AGR_ACC_DCLICK_MASK   0x20
01531 mems_status_t LSM303AGR_ACC_R_DoubleCLICK(void *handle, LSM303AGR_ACC_DCLICK_t *value);
01532 
01533 /*******************************************************************************
01534 * Register      : CLICK_SRC
01535 * Address       : 0X39
01536 * Bit Group Name: IA
01537 * Permission    : RO
01538 *******************************************************************************/
01539 typedef enum {
01540     LSM303AGR_ACC_CLICK_IA_DOWN          =0x00,
01541     LSM303AGR_ACC_CLICK_IA_UP        =0x40,
01542 } LSM303AGR_ACC_CLICK_IA_t;
01543 
01544 #define       LSM303AGR_ACC_IA_MASK   0x40
01545 mems_status_t LSM303AGR_ACC_R_CLICK_IA(void *handle, LSM303AGR_ACC_CLICK_IA_t *value);
01546 
01547 /*******************************************************************************
01548 * Register      : CLICK_THS
01549 * Address       : 0X3A
01550 * Bit Group Name: THS
01551 * Permission    : RW
01552 *******************************************************************************/
01553 #define       LSM303AGR_ACC_THS_MASK      0x7F
01554 #define       LSM303AGR_ACC_THS_POSITION      0
01555 mems_status_t LSM303AGR_ACC_W_ClickThreshold(void *handle, u8_t newValue);
01556 mems_status_t LSM303AGR_ACC_R_ClickThreshold(void *handle, u8_t *value);
01557 
01558 /*******************************************************************************
01559 * Register      : TIME_LIMIT
01560 * Address       : 0X3B
01561 * Bit Group Name: TLI
01562 * Permission    : RW
01563 *******************************************************************************/
01564 #define       LSM303AGR_ACC_TLI_MASK      0x7F
01565 #define       LSM303AGR_ACC_TLI_POSITION      0
01566 mems_status_t LSM303AGR_ACC_W_ClickTimeLimit(void *handle, u8_t newValue);
01567 mems_status_t LSM303AGR_ACC_R_ClickTimeLimit(void *handle, u8_t *value);
01568 
01569 /*******************************************************************************
01570 * Register      : TIME_LATENCY
01571 * Address       : 0X3C
01572 * Bit Group Name: TLA
01573 * Permission    : RW
01574 *******************************************************************************/
01575 #define       LSM303AGR_ACC_TLA_MASK      0xFF
01576 #define       LSM303AGR_ACC_TLA_POSITION      0
01577 mems_status_t LSM303AGR_ACC_W_ClickTimeLatency(void *handle, u8_t newValue);
01578 mems_status_t LSM303AGR_ACC_R_ClickTimeLatency(void *handle, u8_t *value);
01579 
01580 /*******************************************************************************
01581 * Register      : TIME_WINDOW
01582 * Address       : 0X3D
01583 * Bit Group Name: TW
01584 * Permission    : RW
01585 *******************************************************************************/
01586 #define       LSM303AGR_ACC_TW_MASK   0xFF
01587 #define       LSM303AGR_ACC_TW_POSITION   0
01588 mems_status_t LSM303AGR_ACC_W_ClickTimeWindow(void *handle, u8_t newValue);
01589 mems_status_t LSM303AGR_ACC_R_ClickTimeWindow(void *handle, u8_t *value);
01590 /*******************************************************************************
01591 * Register      : <REGISTER_L> - <REGISTER_H>
01592 * Output Type   : Voltage_ADC
01593 * Permission    : RO 
01594 *******************************************************************************/
01595 mems_status_t LSM303AGR_ACC_Get_Voltage_ADC(void *handle, u8_t *buff); 
01596 /*******************************************************************************
01597 * Register      : <REGISTER_L> - <REGISTER_H>
01598 * Output Type   : Acceleration
01599 * Permission    : RO 
01600 *******************************************************************************/
01601 mems_status_t LSM303AGR_ACC_Get_Raw_Acceleration(void *handle, u8_t *buff); 
01602 mems_status_t LSM303AGR_ACC_Get_Acceleration(void *handle, int *buff);
01603 
01604 #ifdef __cplusplus
01605 }
01606 #endif
01607 
01608 #endif