3-axis MEMS ultra low power accelerometer
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3
lis2dw12_reg.c@2:a94816b14e3d, 2018-11-21 (annotated)
- Committer:
- cparata
- Date:
- Wed Nov 21 15:41:28 2018 +0000
- Revision:
- 2:a94816b14e3d
- Parent:
- 1:94e908301953
- Child:
- 3:111317ba9301
Update PID files
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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cparata | 2:a94816b14e3d | 1 | /* |
cparata | 0:dff8803aace7 | 2 | ****************************************************************************** |
cparata | 0:dff8803aace7 | 3 | * @file lis2dw12_reg.c |
cparata | 2:a94816b14e3d | 4 | * @author Sensors Software Solution Team |
cparata | 0:dff8803aace7 | 5 | * @brief LIS2DW12 driver file |
cparata | 0:dff8803aace7 | 6 | ****************************************************************************** |
cparata | 0:dff8803aace7 | 7 | * @attention |
cparata | 0:dff8803aace7 | 8 | * |
cparata | 0:dff8803aace7 | 9 | * <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2> |
cparata | 0:dff8803aace7 | 10 | * |
cparata | 2:a94816b14e3d | 11 | * Redistribution and use in source and binary forms, with or without |
cparata | 2:a94816b14e3d | 12 | * modification, are permitted provided that the following conditions |
cparata | 2:a94816b14e3d | 13 | * are met: |
cparata | 0:dff8803aace7 | 14 | * 1. Redistributions of source code must retain the above copyright notice, |
cparata | 0:dff8803aace7 | 15 | * this list of conditions and the following disclaimer. |
cparata | 2:a94816b14e3d | 16 | * 2. Redistributions in binary form must reproduce the above copyright |
cparata | 2:a94816b14e3d | 17 | * notice, this list of conditions and the following disclaimer in the |
cparata | 2:a94816b14e3d | 18 | * documentation and/or other materials provided with the distribution. |
cparata | 2:a94816b14e3d | 19 | * 3. Neither the name of STMicroelectronics nor the names of its |
cparata | 2:a94816b14e3d | 20 | * contributors may be used to endorse or promote products derived from |
cparata | 2:a94816b14e3d | 21 | * this software without specific prior written permission. |
cparata | 0:dff8803aace7 | 22 | * |
cparata | 0:dff8803aace7 | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
cparata | 0:dff8803aace7 | 24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
cparata | 2:a94816b14e3d | 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
cparata | 2:a94816b14e3d | 26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
cparata | 2:a94816b14e3d | 27 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
cparata | 2:a94816b14e3d | 28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
cparata | 2:a94816b14e3d | 29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
cparata | 2:a94816b14e3d | 30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
cparata | 2:a94816b14e3d | 31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
cparata | 2:a94816b14e3d | 32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
cparata | 2:a94816b14e3d | 33 | * POSSIBILITY OF SUCH DAMAGE. |
cparata | 0:dff8803aace7 | 34 | * |
cparata | 0:dff8803aace7 | 35 | */ |
cparata | 0:dff8803aace7 | 36 | |
cparata | 0:dff8803aace7 | 37 | #include "lis2dw12_reg.h" |
cparata | 0:dff8803aace7 | 38 | |
cparata | 0:dff8803aace7 | 39 | /** |
cparata | 2:a94816b14e3d | 40 | * @defgroup LIS2DW12 |
cparata | 2:a94816b14e3d | 41 | * @brief This file provides a set of functions needed to drive the |
cparata | 2:a94816b14e3d | 42 | * lis2dw12 enhanced inertial module. |
cparata | 0:dff8803aace7 | 43 | * @{ |
cparata | 2:a94816b14e3d | 44 | * |
cparata | 0:dff8803aace7 | 45 | */ |
cparata | 0:dff8803aace7 | 46 | |
cparata | 2:a94816b14e3d | 47 | /** |
cparata | 2:a94816b14e3d | 48 | * @defgroup LIS2DW12_Interfaces_Functions |
cparata | 2:a94816b14e3d | 49 | * @brief This section provide a set of functions used to read and |
cparata | 2:a94816b14e3d | 50 | * write a generic register of the device. |
cparata | 2:a94816b14e3d | 51 | * MANDATORY: return 0 -> no Error. |
cparata | 0:dff8803aace7 | 52 | * @{ |
cparata | 2:a94816b14e3d | 53 | * |
cparata | 0:dff8803aace7 | 54 | */ |
cparata | 0:dff8803aace7 | 55 | |
cparata | 0:dff8803aace7 | 56 | /** |
cparata | 0:dff8803aace7 | 57 | * @brief Read generic device register |
cparata | 2:a94816b14e3d | 58 | * |
cparata | 2:a94816b14e3d | 59 | * @param ctx read / write interface definitions(ptr) |
cparata | 2:a94816b14e3d | 60 | * @param reg register to read |
cparata | 2:a94816b14e3d | 61 | * @param data pointer to buffer that store the data read(ptr) |
cparata | 2:a94816b14e3d | 62 | * @param len number of consecutive register to read |
cparata | 2:a94816b14e3d | 63 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 64 | * |
cparata | 0:dff8803aace7 | 65 | */ |
cparata | 0:dff8803aace7 | 66 | int32_t lis2dw12_read_reg(lis2dw12_ctx_t* ctx, uint8_t reg, uint8_t* data, |
cparata | 0:dff8803aace7 | 67 | uint16_t len) |
cparata | 0:dff8803aace7 | 68 | { |
cparata | 2:a94816b14e3d | 69 | int32_t ret; |
cparata | 2:a94816b14e3d | 70 | ret = ctx->read_reg(ctx->handle, reg, data, len); |
cparata | 2:a94816b14e3d | 71 | return ret; |
cparata | 0:dff8803aace7 | 72 | } |
cparata | 0:dff8803aace7 | 73 | |
cparata | 0:dff8803aace7 | 74 | /** |
cparata | 0:dff8803aace7 | 75 | * @brief Write generic device register |
cparata | 0:dff8803aace7 | 76 | * |
cparata | 2:a94816b14e3d | 77 | * @param ctx read / write interface definitions(ptr) |
cparata | 2:a94816b14e3d | 78 | * @param reg register to write |
cparata | 2:a94816b14e3d | 79 | * @param data pointer to data to write in register reg(ptr) |
cparata | 2:a94816b14e3d | 80 | * @param len number of consecutive register to write |
cparata | 2:a94816b14e3d | 81 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 2:a94816b14e3d | 82 | * |
cparata | 2:a94816b14e3d | 83 | */ |
cparata | 0:dff8803aace7 | 84 | int32_t lis2dw12_write_reg(lis2dw12_ctx_t* ctx, uint8_t reg, uint8_t* data, |
cparata | 0:dff8803aace7 | 85 | uint16_t len) |
cparata | 0:dff8803aace7 | 86 | { |
cparata | 2:a94816b14e3d | 87 | int32_t ret; |
cparata | 2:a94816b14e3d | 88 | ret = ctx->write_reg(ctx->handle, reg, data, len); |
cparata | 2:a94816b14e3d | 89 | return ret; |
cparata | 0:dff8803aace7 | 90 | } |
cparata | 0:dff8803aace7 | 91 | |
cparata | 0:dff8803aace7 | 92 | /** |
cparata | 0:dff8803aace7 | 93 | * @} |
cparata | 2:a94816b14e3d | 94 | * |
cparata | 2:a94816b14e3d | 95 | */ |
cparata | 2:a94816b14e3d | 96 | |
cparata | 2:a94816b14e3d | 97 | /** |
cparata | 2:a94816b14e3d | 98 | * @defgroup LIS2DW12_Sensitivity |
cparata | 2:a94816b14e3d | 99 | * @brief These functions convert raw-data into engineering units. |
cparata | 2:a94816b14e3d | 100 | * @{ |
cparata | 2:a94816b14e3d | 101 | * |
cparata | 2:a94816b14e3d | 102 | */ |
cparata | 2:a94816b14e3d | 103 | |
cparata | 2:a94816b14e3d | 104 | float lis2dw12_from_fs2_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 105 | { |
cparata | 2:a94816b14e3d | 106 | return ((float)lsb) * 0.061f; |
cparata | 2:a94816b14e3d | 107 | } |
cparata | 2:a94816b14e3d | 108 | |
cparata | 2:a94816b14e3d | 109 | float lis2dw12_from_fs4_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 110 | { |
cparata | 2:a94816b14e3d | 111 | return ((float)lsb) * 0.122f; |
cparata | 2:a94816b14e3d | 112 | } |
cparata | 2:a94816b14e3d | 113 | |
cparata | 2:a94816b14e3d | 114 | float lis2dw12_from_fs8_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 115 | { |
cparata | 2:a94816b14e3d | 116 | return ((float)lsb) * 0.244f; |
cparata | 2:a94816b14e3d | 117 | } |
cparata | 2:a94816b14e3d | 118 | |
cparata | 2:a94816b14e3d | 119 | float lis2dw12_from_fs16_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 120 | { |
cparata | 2:a94816b14e3d | 121 | return ((float)lsb) *0.488f; |
cparata | 2:a94816b14e3d | 122 | } |
cparata | 2:a94816b14e3d | 123 | |
cparata | 2:a94816b14e3d | 124 | float lis2dw12_from_fs2_lp1_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 125 | { |
cparata | 2:a94816b14e3d | 126 | return ((float)lsb) * 0.061f; |
cparata | 2:a94816b14e3d | 127 | } |
cparata | 2:a94816b14e3d | 128 | |
cparata | 2:a94816b14e3d | 129 | float lis2dw12_from_fs4_lp1_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 130 | { |
cparata | 2:a94816b14e3d | 131 | return ((float)lsb) * 0.122f; |
cparata | 2:a94816b14e3d | 132 | } |
cparata | 2:a94816b14e3d | 133 | |
cparata | 2:a94816b14e3d | 134 | float lis2dw12_from_fs8_lp1_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 135 | { |
cparata | 2:a94816b14e3d | 136 | return ((float)lsb) * 0.244f; |
cparata | 2:a94816b14e3d | 137 | } |
cparata | 2:a94816b14e3d | 138 | |
cparata | 2:a94816b14e3d | 139 | float lis2dw12_from_fs16_lp1_to_mg(int16_t lsb) |
cparata | 2:a94816b14e3d | 140 | { |
cparata | 2:a94816b14e3d | 141 | return ((float)lsb) * 0.488f; |
cparata | 2:a94816b14e3d | 142 | } |
cparata | 2:a94816b14e3d | 143 | |
cparata | 2:a94816b14e3d | 144 | float lis2dw12_from_lsb_to_celsius(int16_t lsb) |
cparata | 2:a94816b14e3d | 145 | { |
cparata | 2:a94816b14e3d | 146 | return (((float)lsb / 16.0f) + 25.0f); |
cparata | 2:a94816b14e3d | 147 | } |
cparata | 2:a94816b14e3d | 148 | |
cparata | 2:a94816b14e3d | 149 | /** |
cparata | 2:a94816b14e3d | 150 | * @} |
cparata | 2:a94816b14e3d | 151 | * |
cparata | 0:dff8803aace7 | 152 | */ |
cparata | 0:dff8803aace7 | 153 | |
cparata | 0:dff8803aace7 | 154 | /** |
cparata | 2:a94816b14e3d | 155 | * @defgroup LIS2DW12_Data_Generation |
cparata | 2:a94816b14e3d | 156 | * @brief This section groups all the functions concerning |
cparata | 2:a94816b14e3d | 157 | * data generation |
cparata | 0:dff8803aace7 | 158 | * @{ |
cparata | 2:a94816b14e3d | 159 | * |
cparata | 0:dff8803aace7 | 160 | */ |
cparata | 0:dff8803aace7 | 161 | |
cparata | 0:dff8803aace7 | 162 | /** |
cparata | 2:a94816b14e3d | 163 | * @brief Select accelerometer operating modes.[set] |
cparata | 0:dff8803aace7 | 164 | * |
cparata | 2:a94816b14e3d | 165 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 166 | * @param val change the values of mode / lp_mode in reg CTRL1 |
cparata | 2:a94816b14e3d | 167 | * and low_noise in reg CTRL6 |
cparata | 2:a94816b14e3d | 168 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 169 | * |
cparata | 0:dff8803aace7 | 170 | */ |
cparata | 0:dff8803aace7 | 171 | int32_t lis2dw12_power_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_mode_t val) |
cparata | 0:dff8803aace7 | 172 | { |
cparata | 2:a94816b14e3d | 173 | lis2dw12_ctrl1_t ctrl1; |
cparata | 2:a94816b14e3d | 174 | lis2dw12_ctrl6_t ctrl6; |
cparata | 2:a94816b14e3d | 175 | int32_t ret; |
cparata | 0:dff8803aace7 | 176 | |
cparata | 2:a94816b14e3d | 177 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1); |
cparata | 2:a94816b14e3d | 178 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 179 | ctrl1.mode = ( (uint8_t) val & 0x0CU ) >> 2; |
cparata | 2:a94816b14e3d | 180 | ctrl1.lp_mode = (uint8_t) val & 0x03U ; |
cparata | 2:a94816b14e3d | 181 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1); |
cparata | 2:a94816b14e3d | 182 | } |
cparata | 2:a94816b14e3d | 183 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 184 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1); |
cparata | 2:a94816b14e3d | 185 | } |
cparata | 2:a94816b14e3d | 186 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 187 | ctrl6.low_noise = ( (uint8_t) val & 0x10U ) >> 4; |
cparata | 2:a94816b14e3d | 188 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1); |
cparata | 2:a94816b14e3d | 189 | } |
cparata | 2:a94816b14e3d | 190 | return ret; |
cparata | 0:dff8803aace7 | 191 | } |
cparata | 0:dff8803aace7 | 192 | |
cparata | 0:dff8803aace7 | 193 | /** |
cparata | 2:a94816b14e3d | 194 | * @brief Select accelerometer operating modes.[get] |
cparata | 0:dff8803aace7 | 195 | * |
cparata | 2:a94816b14e3d | 196 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 197 | * @param val change the values of mode / lp_mode in reg CTRL1 |
cparata | 2:a94816b14e3d | 198 | * and low_noise in reg CTRL6 |
cparata | 2:a94816b14e3d | 199 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 200 | * |
cparata | 0:dff8803aace7 | 201 | */ |
cparata | 0:dff8803aace7 | 202 | int32_t lis2dw12_power_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_mode_t *val) |
cparata | 0:dff8803aace7 | 203 | { |
cparata | 2:a94816b14e3d | 204 | lis2dw12_ctrl1_t ctrl1; |
cparata | 2:a94816b14e3d | 205 | lis2dw12_ctrl6_t ctrl6; |
cparata | 2:a94816b14e3d | 206 | int32_t ret; |
cparata | 2:a94816b14e3d | 207 | |
cparata | 2:a94816b14e3d | 208 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1); |
cparata | 2:a94816b14e3d | 209 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 210 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1); |
cparata | 0:dff8803aace7 | 211 | |
cparata | 2:a94816b14e3d | 212 | switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) + |
cparata | 2:a94816b14e3d | 213 | ctrl1.lp_mode)) { |
cparata | 2:a94816b14e3d | 214 | case LIS2DW12_HIGH_PERFORMANCE: |
cparata | 2:a94816b14e3d | 215 | *val = LIS2DW12_HIGH_PERFORMANCE; |
cparata | 2:a94816b14e3d | 216 | break; |
cparata | 2:a94816b14e3d | 217 | case LIS2DW12_CONT_LOW_PWR_4: |
cparata | 2:a94816b14e3d | 218 | *val = LIS2DW12_CONT_LOW_PWR_4; |
cparata | 2:a94816b14e3d | 219 | break; |
cparata | 2:a94816b14e3d | 220 | case LIS2DW12_CONT_LOW_PWR_3: |
cparata | 2:a94816b14e3d | 221 | *val = LIS2DW12_CONT_LOW_PWR_3; |
cparata | 2:a94816b14e3d | 222 | break; |
cparata | 2:a94816b14e3d | 223 | case LIS2DW12_CONT_LOW_PWR_2: |
cparata | 2:a94816b14e3d | 224 | *val = LIS2DW12_CONT_LOW_PWR_2; |
cparata | 2:a94816b14e3d | 225 | break; |
cparata | 2:a94816b14e3d | 226 | case LIS2DW12_CONT_LOW_PWR_12bit: |
cparata | 2:a94816b14e3d | 227 | *val = LIS2DW12_CONT_LOW_PWR_12bit; |
cparata | 2:a94816b14e3d | 228 | break; |
cparata | 2:a94816b14e3d | 229 | case LIS2DW12_SINGLE_LOW_PWR_4: |
cparata | 2:a94816b14e3d | 230 | *val = LIS2DW12_SINGLE_LOW_PWR_4; |
cparata | 2:a94816b14e3d | 231 | break; |
cparata | 2:a94816b14e3d | 232 | case LIS2DW12_SINGLE_LOW_PWR_3: |
cparata | 2:a94816b14e3d | 233 | *val = LIS2DW12_SINGLE_LOW_PWR_3; |
cparata | 2:a94816b14e3d | 234 | break; |
cparata | 2:a94816b14e3d | 235 | case LIS2DW12_SINGLE_LOW_PWR_2: |
cparata | 2:a94816b14e3d | 236 | *val = LIS2DW12_SINGLE_LOW_PWR_2; |
cparata | 2:a94816b14e3d | 237 | break; |
cparata | 2:a94816b14e3d | 238 | case LIS2DW12_SINGLE_LOW_PWR_12bit: |
cparata | 2:a94816b14e3d | 239 | *val = LIS2DW12_SINGLE_LOW_PWR_12bit; |
cparata | 2:a94816b14e3d | 240 | break; |
cparata | 2:a94816b14e3d | 241 | case LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE: |
cparata | 2:a94816b14e3d | 242 | *val = LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE; |
cparata | 2:a94816b14e3d | 243 | break; |
cparata | 2:a94816b14e3d | 244 | case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4: |
cparata | 2:a94816b14e3d | 245 | *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4; |
cparata | 2:a94816b14e3d | 246 | break; |
cparata | 2:a94816b14e3d | 247 | case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3: |
cparata | 2:a94816b14e3d | 248 | *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3; |
cparata | 2:a94816b14e3d | 249 | break; |
cparata | 2:a94816b14e3d | 250 | case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2: |
cparata | 2:a94816b14e3d | 251 | *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2; |
cparata | 2:a94816b14e3d | 252 | break; |
cparata | 2:a94816b14e3d | 253 | case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit: |
cparata | 2:a94816b14e3d | 254 | *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit; |
cparata | 2:a94816b14e3d | 255 | break; |
cparata | 2:a94816b14e3d | 256 | case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4: |
cparata | 2:a94816b14e3d | 257 | *val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4; |
cparata | 2:a94816b14e3d | 258 | break; |
cparata | 2:a94816b14e3d | 259 | case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3: |
cparata | 2:a94816b14e3d | 260 | *val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3; |
cparata | 2:a94816b14e3d | 261 | break; |
cparata | 2:a94816b14e3d | 262 | case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2: |
cparata | 2:a94816b14e3d | 263 | *val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2; |
cparata | 2:a94816b14e3d | 264 | break; |
cparata | 2:a94816b14e3d | 265 | case LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit: |
cparata | 2:a94816b14e3d | 266 | *val = LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit; |
cparata | 2:a94816b14e3d | 267 | break; |
cparata | 2:a94816b14e3d | 268 | default: |
cparata | 2:a94816b14e3d | 269 | *val = LIS2DW12_HIGH_PERFORMANCE; |
cparata | 2:a94816b14e3d | 270 | break; |
cparata | 2:a94816b14e3d | 271 | } |
cparata | 2:a94816b14e3d | 272 | } |
cparata | 2:a94816b14e3d | 273 | return ret; |
cparata | 0:dff8803aace7 | 274 | } |
cparata | 0:dff8803aace7 | 275 | |
cparata | 0:dff8803aace7 | 276 | /** |
cparata | 2:a94816b14e3d | 277 | * @brief Accelerometer data rate selection.[set] |
cparata | 0:dff8803aace7 | 278 | * |
cparata | 2:a94816b14e3d | 279 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 280 | * @param val change the values of odr in reg CTRL1 |
cparata | 2:a94816b14e3d | 281 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 282 | * |
cparata | 0:dff8803aace7 | 283 | */ |
cparata | 0:dff8803aace7 | 284 | int32_t lis2dw12_data_rate_set(lis2dw12_ctx_t *ctx, lis2dw12_odr_t val) |
cparata | 0:dff8803aace7 | 285 | { |
cparata | 2:a94816b14e3d | 286 | lis2dw12_ctrl1_t ctrl1; |
cparata | 2:a94816b14e3d | 287 | lis2dw12_ctrl3_t ctrl3; |
cparata | 2:a94816b14e3d | 288 | int32_t ret; |
cparata | 0:dff8803aace7 | 289 | |
cparata | 2:a94816b14e3d | 290 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1); |
cparata | 2:a94816b14e3d | 291 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 292 | ctrl1.odr = (uint8_t) val; |
cparata | 2:a94816b14e3d | 293 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1); |
cparata | 2:a94816b14e3d | 294 | } |
cparata | 2:a94816b14e3d | 295 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 296 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1); |
cparata | 2:a94816b14e3d | 297 | } |
cparata | 2:a94816b14e3d | 298 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 299 | ctrl3.slp_mode = ( (uint8_t) val & 0x30U ) >> 4; |
cparata | 2:a94816b14e3d | 300 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1); |
cparata | 2:a94816b14e3d | 301 | } |
cparata | 2:a94816b14e3d | 302 | return ret; |
cparata | 0:dff8803aace7 | 303 | } |
cparata | 0:dff8803aace7 | 304 | |
cparata | 0:dff8803aace7 | 305 | /** |
cparata | 2:a94816b14e3d | 306 | * @brief Accelerometer data rate selection.[get] |
cparata | 0:dff8803aace7 | 307 | * |
cparata | 2:a94816b14e3d | 308 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 309 | * @param val Get the values of odr in reg CTRL1 |
cparata | 2:a94816b14e3d | 310 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 311 | * |
cparata | 0:dff8803aace7 | 312 | */ |
cparata | 0:dff8803aace7 | 313 | int32_t lis2dw12_data_rate_get(lis2dw12_ctx_t *ctx, lis2dw12_odr_t *val) |
cparata | 0:dff8803aace7 | 314 | { |
cparata | 2:a94816b14e3d | 315 | lis2dw12_ctrl1_t ctrl1; |
cparata | 2:a94816b14e3d | 316 | lis2dw12_ctrl3_t ctrl3; |
cparata | 2:a94816b14e3d | 317 | int32_t ret; |
cparata | 0:dff8803aace7 | 318 | |
cparata | 2:a94816b14e3d | 319 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1,(uint8_t*) &ctrl1, 1); |
cparata | 2:a94816b14e3d | 320 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 321 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) &ctrl3, 1); |
cparata | 2:a94816b14e3d | 322 | |
cparata | 2:a94816b14e3d | 323 | switch ((ctrl3.slp_mode << 4) + ctrl1.odr) { |
cparata | 2:a94816b14e3d | 324 | case LIS2DW12_XL_ODR_OFF: |
cparata | 2:a94816b14e3d | 325 | *val = LIS2DW12_XL_ODR_OFF; |
cparata | 2:a94816b14e3d | 326 | break; |
cparata | 2:a94816b14e3d | 327 | case LIS2DW12_XL_ODR_1Hz6_LP_ONLY: |
cparata | 2:a94816b14e3d | 328 | *val = LIS2DW12_XL_ODR_1Hz6_LP_ONLY; |
cparata | 2:a94816b14e3d | 329 | break; |
cparata | 2:a94816b14e3d | 330 | case LIS2DW12_XL_ODR_12Hz5: |
cparata | 2:a94816b14e3d | 331 | *val = LIS2DW12_XL_ODR_12Hz5; |
cparata | 2:a94816b14e3d | 332 | break; |
cparata | 2:a94816b14e3d | 333 | case LIS2DW12_XL_ODR_25Hz: |
cparata | 2:a94816b14e3d | 334 | *val = LIS2DW12_XL_ODR_25Hz; |
cparata | 2:a94816b14e3d | 335 | break; |
cparata | 2:a94816b14e3d | 336 | case LIS2DW12_XL_ODR_50Hz: |
cparata | 2:a94816b14e3d | 337 | *val = LIS2DW12_XL_ODR_50Hz; |
cparata | 2:a94816b14e3d | 338 | break; |
cparata | 2:a94816b14e3d | 339 | case LIS2DW12_XL_ODR_100Hz: |
cparata | 2:a94816b14e3d | 340 | *val = LIS2DW12_XL_ODR_100Hz; |
cparata | 2:a94816b14e3d | 341 | break; |
cparata | 2:a94816b14e3d | 342 | case LIS2DW12_XL_ODR_200Hz: |
cparata | 2:a94816b14e3d | 343 | *val = LIS2DW12_XL_ODR_200Hz; |
cparata | 2:a94816b14e3d | 344 | break; |
cparata | 2:a94816b14e3d | 345 | case LIS2DW12_XL_ODR_400Hz: |
cparata | 2:a94816b14e3d | 346 | *val = LIS2DW12_XL_ODR_400Hz; |
cparata | 2:a94816b14e3d | 347 | break; |
cparata | 2:a94816b14e3d | 348 | case LIS2DW12_XL_ODR_800Hz: |
cparata | 2:a94816b14e3d | 349 | *val = LIS2DW12_XL_ODR_800Hz; |
cparata | 2:a94816b14e3d | 350 | break; |
cparata | 2:a94816b14e3d | 351 | case LIS2DW12_XL_ODR_1k6Hz: |
cparata | 2:a94816b14e3d | 352 | *val = LIS2DW12_XL_ODR_1k6Hz; |
cparata | 2:a94816b14e3d | 353 | break; |
cparata | 2:a94816b14e3d | 354 | case LIS2DW12_XL_SET_SW_TRIG: |
cparata | 2:a94816b14e3d | 355 | *val = LIS2DW12_XL_SET_SW_TRIG; |
cparata | 2:a94816b14e3d | 356 | break; |
cparata | 2:a94816b14e3d | 357 | case LIS2DW12_XL_SET_PIN_TRIG: |
cparata | 2:a94816b14e3d | 358 | *val = LIS2DW12_XL_SET_PIN_TRIG; |
cparata | 2:a94816b14e3d | 359 | break; |
cparata | 2:a94816b14e3d | 360 | default: |
cparata | 2:a94816b14e3d | 361 | *val = LIS2DW12_XL_ODR_OFF; |
cparata | 2:a94816b14e3d | 362 | break; |
cparata | 2:a94816b14e3d | 363 | } |
cparata | 2:a94816b14e3d | 364 | } |
cparata | 2:a94816b14e3d | 365 | return ret; |
cparata | 0:dff8803aace7 | 366 | } |
cparata | 0:dff8803aace7 | 367 | |
cparata | 0:dff8803aace7 | 368 | /** |
cparata | 2:a94816b14e3d | 369 | * @brief Block data update.[set] |
cparata | 0:dff8803aace7 | 370 | * |
cparata | 2:a94816b14e3d | 371 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 372 | * @param val change the values of bdu in reg CTRL2 |
cparata | 2:a94816b14e3d | 373 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 374 | * |
cparata | 0:dff8803aace7 | 375 | */ |
cparata | 0:dff8803aace7 | 376 | int32_t lis2dw12_block_data_update_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 377 | { |
cparata | 2:a94816b14e3d | 378 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 379 | int32_t ret; |
cparata | 0:dff8803aace7 | 380 | |
cparata | 2:a94816b14e3d | 381 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 382 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 383 | reg.bdu = val; |
cparata | 2:a94816b14e3d | 384 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 385 | } |
cparata | 2:a94816b14e3d | 386 | return ret; |
cparata | 0:dff8803aace7 | 387 | } |
cparata | 0:dff8803aace7 | 388 | |
cparata | 0:dff8803aace7 | 389 | /** |
cparata | 2:a94816b14e3d | 390 | * @brief Block data update.[get] |
cparata | 0:dff8803aace7 | 391 | * |
cparata | 2:a94816b14e3d | 392 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 393 | * @param val change the values of bdu in reg CTRL2 |
cparata | 2:a94816b14e3d | 394 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 395 | * |
cparata | 0:dff8803aace7 | 396 | */ |
cparata | 0:dff8803aace7 | 397 | int32_t lis2dw12_block_data_update_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 398 | { |
cparata | 2:a94816b14e3d | 399 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 400 | int32_t ret; |
cparata | 0:dff8803aace7 | 401 | |
cparata | 2:a94816b14e3d | 402 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 403 | *val = reg.bdu; |
cparata | 0:dff8803aace7 | 404 | |
cparata | 2:a94816b14e3d | 405 | return ret; |
cparata | 0:dff8803aace7 | 406 | } |
cparata | 0:dff8803aace7 | 407 | |
cparata | 0:dff8803aace7 | 408 | /** |
cparata | 2:a94816b14e3d | 409 | * @brief Accelerometer full-scale selection.[set] |
cparata | 0:dff8803aace7 | 410 | * |
cparata | 2:a94816b14e3d | 411 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 412 | * @param val change the values of fs in reg CTRL6 |
cparata | 2:a94816b14e3d | 413 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 414 | * |
cparata | 0:dff8803aace7 | 415 | */ |
cparata | 0:dff8803aace7 | 416 | int32_t lis2dw12_full_scale_set(lis2dw12_ctx_t *ctx, lis2dw12_fs_t val) |
cparata | 0:dff8803aace7 | 417 | { |
cparata | 2:a94816b14e3d | 418 | lis2dw12_ctrl6_t reg; |
cparata | 2:a94816b14e3d | 419 | int32_t ret; |
cparata | 0:dff8803aace7 | 420 | |
cparata | 2:a94816b14e3d | 421 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 422 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 423 | reg.fs = (uint8_t) val; |
cparata | 2:a94816b14e3d | 424 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 425 | } |
cparata | 2:a94816b14e3d | 426 | return ret; |
cparata | 0:dff8803aace7 | 427 | } |
cparata | 0:dff8803aace7 | 428 | |
cparata | 0:dff8803aace7 | 429 | /** |
cparata | 2:a94816b14e3d | 430 | * @brief Accelerometer full-scale selection.[get] |
cparata | 0:dff8803aace7 | 431 | * |
cparata | 2:a94816b14e3d | 432 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 433 | * @param val Get the values of fs in reg CTRL6 |
cparata | 2:a94816b14e3d | 434 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 435 | * |
cparata | 0:dff8803aace7 | 436 | */ |
cparata | 0:dff8803aace7 | 437 | int32_t lis2dw12_full_scale_get(lis2dw12_ctx_t *ctx, lis2dw12_fs_t *val) |
cparata | 0:dff8803aace7 | 438 | { |
cparata | 2:a94816b14e3d | 439 | lis2dw12_ctrl6_t reg; |
cparata | 2:a94816b14e3d | 440 | int32_t ret; |
cparata | 2:a94816b14e3d | 441 | |
cparata | 2:a94816b14e3d | 442 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 443 | |
cparata | 2:a94816b14e3d | 444 | switch (reg.fs) { |
cparata | 2:a94816b14e3d | 445 | case LIS2DW12_2g: |
cparata | 2:a94816b14e3d | 446 | *val = LIS2DW12_2g; |
cparata | 2:a94816b14e3d | 447 | break; |
cparata | 2:a94816b14e3d | 448 | case LIS2DW12_4g: |
cparata | 2:a94816b14e3d | 449 | *val = LIS2DW12_4g; |
cparata | 2:a94816b14e3d | 450 | break; |
cparata | 2:a94816b14e3d | 451 | case LIS2DW12_8g: |
cparata | 2:a94816b14e3d | 452 | *val = LIS2DW12_8g; |
cparata | 2:a94816b14e3d | 453 | break; |
cparata | 2:a94816b14e3d | 454 | case LIS2DW12_16g: |
cparata | 2:a94816b14e3d | 455 | *val = LIS2DW12_16g; |
cparata | 2:a94816b14e3d | 456 | break; |
cparata | 2:a94816b14e3d | 457 | default: |
cparata | 2:a94816b14e3d | 458 | *val = LIS2DW12_2g; |
cparata | 2:a94816b14e3d | 459 | break; |
cparata | 2:a94816b14e3d | 460 | } |
cparata | 2:a94816b14e3d | 461 | return ret; |
cparata | 0:dff8803aace7 | 462 | } |
cparata | 0:dff8803aace7 | 463 | |
cparata | 0:dff8803aace7 | 464 | /** |
cparata | 2:a94816b14e3d | 465 | * @brief The STATUS_REG register of the device.[get] |
cparata | 0:dff8803aace7 | 466 | * |
cparata | 2:a94816b14e3d | 467 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 468 | * @param val union of registers from STATUS to |
cparata | 2:a94816b14e3d | 469 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 470 | * |
cparata | 0:dff8803aace7 | 471 | */ |
cparata | 0:dff8803aace7 | 472 | int32_t lis2dw12_status_reg_get(lis2dw12_ctx_t *ctx, lis2dw12_status_t *val) |
cparata | 0:dff8803aace7 | 473 | { |
cparata | 2:a94816b14e3d | 474 | int32_t ret; |
cparata | 2:a94816b14e3d | 475 | ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t*) val, 1); |
cparata | 2:a94816b14e3d | 476 | return ret; |
cparata | 0:dff8803aace7 | 477 | } |
cparata | 2:a94816b14e3d | 478 | |
cparata | 0:dff8803aace7 | 479 | /** |
cparata | 2:a94816b14e3d | 480 | * @brief Accelerometer new data available.[get] |
cparata | 0:dff8803aace7 | 481 | * |
cparata | 2:a94816b14e3d | 482 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 483 | * @param val change the values of drdy in reg STATUS |
cparata | 2:a94816b14e3d | 484 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 485 | * |
cparata | 0:dff8803aace7 | 486 | */ |
cparata | 0:dff8803aace7 | 487 | int32_t lis2dw12_flag_data_ready_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 488 | { |
cparata | 2:a94816b14e3d | 489 | lis2dw12_status_t reg; |
cparata | 2:a94816b14e3d | 490 | int32_t ret; |
cparata | 0:dff8803aace7 | 491 | |
cparata | 2:a94816b14e3d | 492 | ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 493 | *val = reg.drdy; |
cparata | 0:dff8803aace7 | 494 | |
cparata | 2:a94816b14e3d | 495 | return ret; |
cparata | 0:dff8803aace7 | 496 | } |
cparata | 0:dff8803aace7 | 497 | /** |
cparata | 2:a94816b14e3d | 498 | * @brief Read all the interrupt/status flag of the device.[get] |
cparata | 2:a94816b14e3d | 499 | * |
cparata | 2:a94816b14e3d | 500 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 501 | * @param val registers STATUS_DUP, WAKE_UP_SRC, |
cparata | 2:a94816b14e3d | 502 | * TAP_SRC, SIXD_SRC, ALL_INT_SRC |
cparata | 2:a94816b14e3d | 503 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 504 | * |
cparata | 0:dff8803aace7 | 505 | */ |
cparata | 0:dff8803aace7 | 506 | int32_t lis2dw12_all_sources_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 507 | lis2dw12_all_sources_t *val) |
cparata | 0:dff8803aace7 | 508 | { |
cparata | 2:a94816b14e3d | 509 | int32_t ret; |
cparata | 2:a94816b14e3d | 510 | ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS_DUP, (uint8_t*) val, 5); |
cparata | 2:a94816b14e3d | 511 | return ret; |
cparata | 0:dff8803aace7 | 512 | } |
cparata | 2:a94816b14e3d | 513 | |
cparata | 0:dff8803aace7 | 514 | /** |
cparata | 2:a94816b14e3d | 515 | * @brief Accelerometer X-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 516 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 2:a94816b14e3d | 517 | * in the range [-127 127].[set] |
cparata | 0:dff8803aace7 | 518 | * |
cparata | 2:a94816b14e3d | 519 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 520 | * @param buff buffer that contains data to write |
cparata | 2:a94816b14e3d | 521 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 522 | * |
cparata | 0:dff8803aace7 | 523 | */ |
cparata | 0:dff8803aace7 | 524 | int32_t lis2dw12_usr_offset_x_set(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 525 | { |
cparata | 2:a94816b14e3d | 526 | int32_t ret; |
cparata | 2:a94816b14e3d | 527 | ret = lis2dw12_write_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1); |
cparata | 2:a94816b14e3d | 528 | return ret; |
cparata | 0:dff8803aace7 | 529 | } |
cparata | 0:dff8803aace7 | 530 | |
cparata | 0:dff8803aace7 | 531 | /** |
cparata | 2:a94816b14e3d | 532 | * @brief Accelerometer X-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 533 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 2:a94816b14e3d | 534 | * in the range [-127 127].[get] |
cparata | 0:dff8803aace7 | 535 | * |
cparata | 2:a94816b14e3d | 536 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 537 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 538 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 539 | * |
cparata | 0:dff8803aace7 | 540 | */ |
cparata | 0:dff8803aace7 | 541 | int32_t lis2dw12_usr_offset_x_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 542 | { |
cparata | 2:a94816b14e3d | 543 | int32_t ret; |
cparata | 2:a94816b14e3d | 544 | ret = lis2dw12_read_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1); |
cparata | 2:a94816b14e3d | 545 | return ret; |
cparata | 0:dff8803aace7 | 546 | } |
cparata | 2:a94816b14e3d | 547 | |
cparata | 0:dff8803aace7 | 548 | /** |
cparata | 2:a94816b14e3d | 549 | * @brief Accelerometer Y-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 550 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 2:a94816b14e3d | 551 | * in the range [-127 127].[set] |
cparata | 0:dff8803aace7 | 552 | * |
cparata | 2:a94816b14e3d | 553 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 554 | * @param buff buffer that contains data to write |
cparata | 2:a94816b14e3d | 555 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 556 | * |
cparata | 0:dff8803aace7 | 557 | */ |
cparata | 0:dff8803aace7 | 558 | int32_t lis2dw12_usr_offset_y_set(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 559 | { |
cparata | 2:a94816b14e3d | 560 | int32_t ret; |
cparata | 2:a94816b14e3d | 561 | ret = lis2dw12_write_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1); |
cparata | 2:a94816b14e3d | 562 | return ret; |
cparata | 0:dff8803aace7 | 563 | } |
cparata | 0:dff8803aace7 | 564 | |
cparata | 0:dff8803aace7 | 565 | /** |
cparata | 2:a94816b14e3d | 566 | * @brief Accelerometer Y-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 567 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 2:a94816b14e3d | 568 | * in the range [-127 127].[get] |
cparata | 0:dff8803aace7 | 569 | * |
cparata | 2:a94816b14e3d | 570 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 571 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 572 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 573 | * |
cparata | 0:dff8803aace7 | 574 | */ |
cparata | 0:dff8803aace7 | 575 | int32_t lis2dw12_usr_offset_y_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 576 | { |
cparata | 2:a94816b14e3d | 577 | int32_t ret; |
cparata | 2:a94816b14e3d | 578 | ret = lis2dw12_read_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1); |
cparata | 2:a94816b14e3d | 579 | return ret; |
cparata | 0:dff8803aace7 | 580 | } |
cparata | 2:a94816b14e3d | 581 | |
cparata | 0:dff8803aace7 | 582 | /** |
cparata | 2:a94816b14e3d | 583 | * @brief Accelerometer Z-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 584 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 2:a94816b14e3d | 585 | * in the range [-127 127].[set] |
cparata | 0:dff8803aace7 | 586 | * |
cparata | 2:a94816b14e3d | 587 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 588 | * @param buff buffer that contains data to write |
cparata | 2:a94816b14e3d | 589 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 590 | * |
cparata | 0:dff8803aace7 | 591 | */ |
cparata | 0:dff8803aace7 | 592 | int32_t lis2dw12_usr_offset_z_set(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 593 | { |
cparata | 2:a94816b14e3d | 594 | int32_t ret; |
cparata | 2:a94816b14e3d | 595 | ret = lis2dw12_write_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1); |
cparata | 2:a94816b14e3d | 596 | return ret; |
cparata | 0:dff8803aace7 | 597 | } |
cparata | 0:dff8803aace7 | 598 | |
cparata | 0:dff8803aace7 | 599 | /** |
cparata | 2:a94816b14e3d | 600 | * @brief Accelerometer Z-axis user offset correction expressed in two’s |
cparata | 2:a94816b14e3d | 601 | * complement, weight depends on bit USR_OFF_W. The value must be |
cparata | 2:a94816b14e3d | 602 | * in the range [-127 127].[get] |
cparata | 0:dff8803aace7 | 603 | * |
cparata | 2:a94816b14e3d | 604 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 605 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 606 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 607 | * |
cparata | 0:dff8803aace7 | 608 | */ |
cparata | 0:dff8803aace7 | 609 | int32_t lis2dw12_usr_offset_z_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 610 | { |
cparata | 2:a94816b14e3d | 611 | int32_t ret; |
cparata | 2:a94816b14e3d | 612 | ret = lis2dw12_read_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1); |
cparata | 2:a94816b14e3d | 613 | return ret; |
cparata | 0:dff8803aace7 | 614 | } |
cparata | 2:a94816b14e3d | 615 | |
cparata | 0:dff8803aace7 | 616 | /** |
cparata | 2:a94816b14e3d | 617 | * @brief Weight of XL user offset bits of registers X_OFS_USR, |
cparata | 2:a94816b14e3d | 618 | * Y_OFS_USR, Z_OFS_USR.[set] |
cparata | 0:dff8803aace7 | 619 | * |
cparata | 2:a94816b14e3d | 620 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 621 | * @param val change the values of usr_off_w in |
cparata | 0:dff8803aace7 | 622 | * reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 623 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 624 | * |
cparata | 0:dff8803aace7 | 625 | */ |
cparata | 0:dff8803aace7 | 626 | int32_t lis2dw12_offset_weight_set(lis2dw12_ctx_t *ctx, |
cparata | 2:a94816b14e3d | 627 | lis2dw12_usr_off_w_t val) |
cparata | 0:dff8803aace7 | 628 | { |
cparata | 2:a94816b14e3d | 629 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 630 | int32_t ret; |
cparata | 0:dff8803aace7 | 631 | |
cparata | 2:a94816b14e3d | 632 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 633 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 634 | reg.usr_off_w = (uint8_t) val; |
cparata | 2:a94816b14e3d | 635 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 636 | } |
cparata | 2:a94816b14e3d | 637 | return ret; |
cparata | 0:dff8803aace7 | 638 | } |
cparata | 0:dff8803aace7 | 639 | |
cparata | 0:dff8803aace7 | 640 | /** |
cparata | 2:a94816b14e3d | 641 | * @brief Weight of XL user offset bits of registers X_OFS_USR, |
cparata | 2:a94816b14e3d | 642 | * Y_OFS_USR, Z_OFS_USR.[get] |
cparata | 0:dff8803aace7 | 643 | * |
cparata | 2:a94816b14e3d | 644 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 645 | * @param val Get the values of usr_off_w in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 646 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 647 | * |
cparata | 0:dff8803aace7 | 648 | */ |
cparata | 0:dff8803aace7 | 649 | int32_t lis2dw12_offset_weight_get(lis2dw12_ctx_t *ctx, |
cparata | 2:a94816b14e3d | 650 | lis2dw12_usr_off_w_t *val) |
cparata | 0:dff8803aace7 | 651 | { |
cparata | 2:a94816b14e3d | 652 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 653 | int32_t ret; |
cparata | 0:dff8803aace7 | 654 | |
cparata | 2:a94816b14e3d | 655 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 656 | switch (reg.usr_off_w) { |
cparata | 2:a94816b14e3d | 657 | case LIS2DW12_LSb_977ug: |
cparata | 2:a94816b14e3d | 658 | *val = LIS2DW12_LSb_977ug; |
cparata | 2:a94816b14e3d | 659 | break; |
cparata | 2:a94816b14e3d | 660 | case LIS2DW12_LSb_15mg6: |
cparata | 2:a94816b14e3d | 661 | *val = LIS2DW12_LSb_15mg6; |
cparata | 2:a94816b14e3d | 662 | break; |
cparata | 2:a94816b14e3d | 663 | default: |
cparata | 2:a94816b14e3d | 664 | *val = LIS2DW12_LSb_977ug; |
cparata | 2:a94816b14e3d | 665 | break; |
cparata | 2:a94816b14e3d | 666 | } |
cparata | 2:a94816b14e3d | 667 | return ret; |
cparata | 0:dff8803aace7 | 668 | } |
cparata | 0:dff8803aace7 | 669 | |
cparata | 0:dff8803aace7 | 670 | /** |
cparata | 0:dff8803aace7 | 671 | * @} |
cparata | 2:a94816b14e3d | 672 | * |
cparata | 0:dff8803aace7 | 673 | */ |
cparata | 0:dff8803aace7 | 674 | |
cparata | 0:dff8803aace7 | 675 | /** |
cparata | 2:a94816b14e3d | 676 | * @defgroup LIS2DW12_Data_Output |
cparata | 2:a94816b14e3d | 677 | * @brief This section groups all the data output functions. |
cparata | 0:dff8803aace7 | 678 | * @{ |
cparata | 2:a94816b14e3d | 679 | * |
cparata | 0:dff8803aace7 | 680 | */ |
cparata | 0:dff8803aace7 | 681 | |
cparata | 0:dff8803aace7 | 682 | /** |
cparata | 2:a94816b14e3d | 683 | * @brief Temperature data output register (r). L and H registers |
cparata | 2:a94816b14e3d | 684 | * together express a 16-bit word in two’s complement.[get] |
cparata | 0:dff8803aace7 | 685 | * |
cparata | 2:a94816b14e3d | 686 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 687 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 688 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 689 | * |
cparata | 0:dff8803aace7 | 690 | */ |
cparata | 0:dff8803aace7 | 691 | int32_t lis2dw12_temperature_raw_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 692 | { |
cparata | 2:a94816b14e3d | 693 | int32_t ret; |
cparata | 2:a94816b14e3d | 694 | ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_T_L, buff, 2); |
cparata | 2:a94816b14e3d | 695 | return ret; |
cparata | 0:dff8803aace7 | 696 | } |
cparata | 0:dff8803aace7 | 697 | |
cparata | 0:dff8803aace7 | 698 | /** |
cparata | 2:a94816b14e3d | 699 | * @brief Linear acceleration output register. The value is expressed as |
cparata | 2:a94816b14e3d | 700 | * a 16-bit word in two’s complement.[get] |
cparata | 0:dff8803aace7 | 701 | * |
cparata | 2:a94816b14e3d | 702 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 703 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 704 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 705 | * |
cparata | 0:dff8803aace7 | 706 | */ |
cparata | 0:dff8803aace7 | 707 | int32_t lis2dw12_acceleration_raw_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 708 | { |
cparata | 2:a94816b14e3d | 709 | int32_t ret; |
cparata | 2:a94816b14e3d | 710 | ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_X_L, buff, 6); |
cparata | 2:a94816b14e3d | 711 | return ret; |
cparata | 0:dff8803aace7 | 712 | } |
cparata | 0:dff8803aace7 | 713 | |
cparata | 0:dff8803aace7 | 714 | /** |
cparata | 0:dff8803aace7 | 715 | * @} |
cparata | 2:a94816b14e3d | 716 | * |
cparata | 0:dff8803aace7 | 717 | */ |
cparata | 0:dff8803aace7 | 718 | |
cparata | 0:dff8803aace7 | 719 | /** |
cparata | 2:a94816b14e3d | 720 | * @defgroup LIS2DW12_Common |
cparata | 2:a94816b14e3d | 721 | * @brief This section groups common useful functions. |
cparata | 0:dff8803aace7 | 722 | * @{ |
cparata | 2:a94816b14e3d | 723 | * |
cparata | 0:dff8803aace7 | 724 | */ |
cparata | 0:dff8803aace7 | 725 | |
cparata | 0:dff8803aace7 | 726 | /** |
cparata | 2:a94816b14e3d | 727 | * @brief Device Who am I.[get] |
cparata | 0:dff8803aace7 | 728 | * |
cparata | 2:a94816b14e3d | 729 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 730 | * @param buff buffer that stores data read |
cparata | 2:a94816b14e3d | 731 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 732 | * |
cparata | 0:dff8803aace7 | 733 | */ |
cparata | 0:dff8803aace7 | 734 | int32_t lis2dw12_device_id_get(lis2dw12_ctx_t *ctx, uint8_t *buff) |
cparata | 0:dff8803aace7 | 735 | { |
cparata | 2:a94816b14e3d | 736 | int32_t ret; |
cparata | 2:a94816b14e3d | 737 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WHO_AM_I, buff, 1); |
cparata | 2:a94816b14e3d | 738 | return ret; |
cparata | 0:dff8803aace7 | 739 | } |
cparata | 0:dff8803aace7 | 740 | |
cparata | 0:dff8803aace7 | 741 | /** |
cparata | 2:a94816b14e3d | 742 | * @brief Register address automatically incremented during multiple byte |
cparata | 2:a94816b14e3d | 743 | * access with a serial interface.[set] |
cparata | 0:dff8803aace7 | 744 | * |
cparata | 2:a94816b14e3d | 745 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 746 | * @param val change the values of if_add_inc in reg CTRL2 |
cparata | 2:a94816b14e3d | 747 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 748 | * |
cparata | 0:dff8803aace7 | 749 | */ |
cparata | 0:dff8803aace7 | 750 | int32_t lis2dw12_auto_increment_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 751 | { |
cparata | 2:a94816b14e3d | 752 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 753 | int32_t ret; |
cparata | 0:dff8803aace7 | 754 | |
cparata | 2:a94816b14e3d | 755 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 756 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 757 | reg.if_add_inc = val; |
cparata | 2:a94816b14e3d | 758 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 759 | } |
cparata | 2:a94816b14e3d | 760 | return ret; |
cparata | 0:dff8803aace7 | 761 | } |
cparata | 0:dff8803aace7 | 762 | |
cparata | 0:dff8803aace7 | 763 | /** |
cparata | 2:a94816b14e3d | 764 | * @brief Register address automatically incremented during multiple |
cparata | 2:a94816b14e3d | 765 | * byte access with a serial interface.[get] |
cparata | 0:dff8803aace7 | 766 | * |
cparata | 2:a94816b14e3d | 767 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 768 | * @param val change the values of if_add_inc in reg CTRL2 |
cparata | 2:a94816b14e3d | 769 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 770 | * |
cparata | 0:dff8803aace7 | 771 | */ |
cparata | 0:dff8803aace7 | 772 | int32_t lis2dw12_auto_increment_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 773 | { |
cparata | 2:a94816b14e3d | 774 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 775 | int32_t ret; |
cparata | 0:dff8803aace7 | 776 | |
cparata | 2:a94816b14e3d | 777 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 778 | *val = reg.if_add_inc; |
cparata | 0:dff8803aace7 | 779 | |
cparata | 2:a94816b14e3d | 780 | return ret; |
cparata | 0:dff8803aace7 | 781 | } |
cparata | 0:dff8803aace7 | 782 | |
cparata | 0:dff8803aace7 | 783 | /** |
cparata | 2:a94816b14e3d | 784 | * @brief Software reset. Restore the default values in user registers.[set] |
cparata | 0:dff8803aace7 | 785 | * |
cparata | 2:a94816b14e3d | 786 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 787 | * @param val change the values of soft_reset in reg CTRL2 |
cparata | 2:a94816b14e3d | 788 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 789 | * |
cparata | 0:dff8803aace7 | 790 | */ |
cparata | 0:dff8803aace7 | 791 | int32_t lis2dw12_reset_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 792 | { |
cparata | 2:a94816b14e3d | 793 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 794 | int32_t ret; |
cparata | 0:dff8803aace7 | 795 | |
cparata | 2:a94816b14e3d | 796 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 797 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 798 | reg.soft_reset = val; |
cparata | 2:a94816b14e3d | 799 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 800 | } |
cparata | 0:dff8803aace7 | 801 | |
cparata | 2:a94816b14e3d | 802 | return ret; |
cparata | 0:dff8803aace7 | 803 | } |
cparata | 0:dff8803aace7 | 804 | |
cparata | 0:dff8803aace7 | 805 | /** |
cparata | 2:a94816b14e3d | 806 | * @brief Software reset. Restore the default values in user registers.[get] |
cparata | 0:dff8803aace7 | 807 | * |
cparata | 2:a94816b14e3d | 808 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 809 | * @param val change the values of soft_reset in reg CTRL2 |
cparata | 2:a94816b14e3d | 810 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 811 | * |
cparata | 0:dff8803aace7 | 812 | */ |
cparata | 0:dff8803aace7 | 813 | int32_t lis2dw12_reset_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 814 | { |
cparata | 2:a94816b14e3d | 815 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 816 | int32_t ret; |
cparata | 0:dff8803aace7 | 817 | |
cparata | 2:a94816b14e3d | 818 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 819 | *val = reg.soft_reset; |
cparata | 0:dff8803aace7 | 820 | |
cparata | 2:a94816b14e3d | 821 | return ret; |
cparata | 0:dff8803aace7 | 822 | } |
cparata | 0:dff8803aace7 | 823 | |
cparata | 0:dff8803aace7 | 824 | /** |
cparata | 2:a94816b14e3d | 825 | * @brief Reboot memory content. Reload the calibration parameters.[set] |
cparata | 0:dff8803aace7 | 826 | * |
cparata | 2:a94816b14e3d | 827 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 828 | * @param val change the values of boot in reg CTRL2 |
cparata | 2:a94816b14e3d | 829 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 830 | * |
cparata | 0:dff8803aace7 | 831 | */ |
cparata | 0:dff8803aace7 | 832 | int32_t lis2dw12_boot_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 833 | { |
cparata | 2:a94816b14e3d | 834 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 835 | int32_t ret; |
cparata | 0:dff8803aace7 | 836 | |
cparata | 2:a94816b14e3d | 837 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 838 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 839 | reg.boot = val; |
cparata | 2:a94816b14e3d | 840 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 841 | } |
cparata | 2:a94816b14e3d | 842 | return ret; |
cparata | 0:dff8803aace7 | 843 | } |
cparata | 0:dff8803aace7 | 844 | |
cparata | 0:dff8803aace7 | 845 | /** |
cparata | 2:a94816b14e3d | 846 | * @brief Reboot memory content. Reload the calibration parameters.[get] |
cparata | 0:dff8803aace7 | 847 | * |
cparata | 2:a94816b14e3d | 848 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 849 | * @param val change the values of boot in reg CTRL2 |
cparata | 2:a94816b14e3d | 850 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 851 | * |
cparata | 0:dff8803aace7 | 852 | */ |
cparata | 0:dff8803aace7 | 853 | int32_t lis2dw12_boot_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 854 | { |
cparata | 2:a94816b14e3d | 855 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 856 | int32_t ret; |
cparata | 0:dff8803aace7 | 857 | |
cparata | 2:a94816b14e3d | 858 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 859 | *val = reg.boot; |
cparata | 0:dff8803aace7 | 860 | |
cparata | 2:a94816b14e3d | 861 | return ret; |
cparata | 0:dff8803aace7 | 862 | } |
cparata | 0:dff8803aace7 | 863 | |
cparata | 0:dff8803aace7 | 864 | /** |
cparata | 2:a94816b14e3d | 865 | * @brief Sensor self-test enable.[set] |
cparata | 0:dff8803aace7 | 866 | * |
cparata | 2:a94816b14e3d | 867 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 868 | * @param val change the values of st in reg CTRL3 |
cparata | 2:a94816b14e3d | 869 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 870 | * |
cparata | 0:dff8803aace7 | 871 | */ |
cparata | 0:dff8803aace7 | 872 | int32_t lis2dw12_self_test_set(lis2dw12_ctx_t *ctx, lis2dw12_st_t val) |
cparata | 0:dff8803aace7 | 873 | { |
cparata | 2:a94816b14e3d | 874 | lis2dw12_ctrl3_t reg; |
cparata | 2:a94816b14e3d | 875 | int32_t ret; |
cparata | 0:dff8803aace7 | 876 | |
cparata | 2:a94816b14e3d | 877 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 878 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 879 | reg.st = (uint8_t) val; |
cparata | 2:a94816b14e3d | 880 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 881 | } |
cparata | 0:dff8803aace7 | 882 | |
cparata | 2:a94816b14e3d | 883 | return ret; |
cparata | 0:dff8803aace7 | 884 | } |
cparata | 0:dff8803aace7 | 885 | |
cparata | 0:dff8803aace7 | 886 | /** |
cparata | 2:a94816b14e3d | 887 | * @brief Sensor self-test enable.[get] |
cparata | 0:dff8803aace7 | 888 | * |
cparata | 2:a94816b14e3d | 889 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 890 | * @param val Get the values of st in reg CTRL3 |
cparata | 2:a94816b14e3d | 891 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 892 | * |
cparata | 0:dff8803aace7 | 893 | */ |
cparata | 0:dff8803aace7 | 894 | int32_t lis2dw12_self_test_get(lis2dw12_ctx_t *ctx, lis2dw12_st_t *val) |
cparata | 0:dff8803aace7 | 895 | { |
cparata | 2:a94816b14e3d | 896 | lis2dw12_ctrl3_t reg; |
cparata | 2:a94816b14e3d | 897 | int32_t ret; |
cparata | 2:a94816b14e3d | 898 | |
cparata | 2:a94816b14e3d | 899 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 900 | |
cparata | 2:a94816b14e3d | 901 | switch (reg.st) { |
cparata | 2:a94816b14e3d | 902 | case LIS2DW12_XL_ST_DISABLE: |
cparata | 2:a94816b14e3d | 903 | *val = LIS2DW12_XL_ST_DISABLE; |
cparata | 2:a94816b14e3d | 904 | break; |
cparata | 2:a94816b14e3d | 905 | case LIS2DW12_XL_ST_POSITIVE: |
cparata | 2:a94816b14e3d | 906 | *val = LIS2DW12_XL_ST_POSITIVE; |
cparata | 2:a94816b14e3d | 907 | break; |
cparata | 2:a94816b14e3d | 908 | case LIS2DW12_XL_ST_NEGATIVE: |
cparata | 2:a94816b14e3d | 909 | *val = LIS2DW12_XL_ST_NEGATIVE; |
cparata | 2:a94816b14e3d | 910 | break; |
cparata | 2:a94816b14e3d | 911 | default: |
cparata | 2:a94816b14e3d | 912 | *val = LIS2DW12_XL_ST_DISABLE; |
cparata | 2:a94816b14e3d | 913 | break; |
cparata | 2:a94816b14e3d | 914 | } |
cparata | 2:a94816b14e3d | 915 | return ret; |
cparata | 0:dff8803aace7 | 916 | } |
cparata | 0:dff8803aace7 | 917 | |
cparata | 0:dff8803aace7 | 918 | /** |
cparata | 2:a94816b14e3d | 919 | * @brief Data-ready pulsed / letched mode.[set] |
cparata | 0:dff8803aace7 | 920 | * |
cparata | 2:a94816b14e3d | 921 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 922 | * @param val change the values of drdy_pulsed in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 923 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 924 | * |
cparata | 0:dff8803aace7 | 925 | */ |
cparata | 0:dff8803aace7 | 926 | int32_t lis2dw12_data_ready_mode_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 927 | lis2dw12_drdy_pulsed_t val) |
cparata | 0:dff8803aace7 | 928 | { |
cparata | 2:a94816b14e3d | 929 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 930 | int32_t ret; |
cparata | 0:dff8803aace7 | 931 | |
cparata | 2:a94816b14e3d | 932 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 933 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 934 | reg.drdy_pulsed = (uint8_t) val; |
cparata | 2:a94816b14e3d | 935 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 936 | } |
cparata | 0:dff8803aace7 | 937 | |
cparata | 2:a94816b14e3d | 938 | return ret; |
cparata | 0:dff8803aace7 | 939 | } |
cparata | 0:dff8803aace7 | 940 | |
cparata | 0:dff8803aace7 | 941 | /** |
cparata | 2:a94816b14e3d | 942 | * @brief Data-ready pulsed / letched mode.[get] |
cparata | 0:dff8803aace7 | 943 | * |
cparata | 2:a94816b14e3d | 944 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 945 | * @param val Get the values of drdy_pulsed in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 946 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 947 | * |
cparata | 0:dff8803aace7 | 948 | */ |
cparata | 0:dff8803aace7 | 949 | int32_t lis2dw12_data_ready_mode_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 950 | lis2dw12_drdy_pulsed_t *val) |
cparata | 0:dff8803aace7 | 951 | { |
cparata | 2:a94816b14e3d | 952 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 953 | int32_t ret; |
cparata | 2:a94816b14e3d | 954 | |
cparata | 2:a94816b14e3d | 955 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 956 | |
cparata | 2:a94816b14e3d | 957 | switch (reg.drdy_pulsed) { |
cparata | 2:a94816b14e3d | 958 | case LIS2DW12_DRDY_LATCHED: |
cparata | 2:a94816b14e3d | 959 | *val = LIS2DW12_DRDY_LATCHED; |
cparata | 2:a94816b14e3d | 960 | break; |
cparata | 2:a94816b14e3d | 961 | case LIS2DW12_DRDY_PULSED: |
cparata | 2:a94816b14e3d | 962 | *val = LIS2DW12_DRDY_PULSED; |
cparata | 2:a94816b14e3d | 963 | break; |
cparata | 2:a94816b14e3d | 964 | default: |
cparata | 2:a94816b14e3d | 965 | *val = LIS2DW12_DRDY_LATCHED; |
cparata | 2:a94816b14e3d | 966 | break; |
cparata | 2:a94816b14e3d | 967 | } |
cparata | 2:a94816b14e3d | 968 | return ret; |
cparata | 0:dff8803aace7 | 969 | } |
cparata | 0:dff8803aace7 | 970 | |
cparata | 0:dff8803aace7 | 971 | /** |
cparata | 0:dff8803aace7 | 972 | * @} |
cparata | 2:a94816b14e3d | 973 | * |
cparata | 0:dff8803aace7 | 974 | */ |
cparata | 0:dff8803aace7 | 975 | |
cparata | 0:dff8803aace7 | 976 | /** |
cparata | 2:a94816b14e3d | 977 | * @defgroup LIS2DW12_Filters |
cparata | 2:a94816b14e3d | 978 | * @brief This section group all the functions concerning the filters |
cparata | 2:a94816b14e3d | 979 | * configuration. |
cparata | 0:dff8803aace7 | 980 | * @{ |
cparata | 2:a94816b14e3d | 981 | * |
cparata | 0:dff8803aace7 | 982 | */ |
cparata | 0:dff8803aace7 | 983 | |
cparata | 0:dff8803aace7 | 984 | /** |
cparata | 2:a94816b14e3d | 985 | * @brief Accelerometer filtering path for outputs.[set] |
cparata | 0:dff8803aace7 | 986 | * |
cparata | 2:a94816b14e3d | 987 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 988 | * @param val change the values of fds in reg CTRL6 |
cparata | 2:a94816b14e3d | 989 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 990 | * |
cparata | 0:dff8803aace7 | 991 | */ |
cparata | 0:dff8803aace7 | 992 | int32_t lis2dw12_filter_path_set(lis2dw12_ctx_t *ctx, lis2dw12_fds_t val) |
cparata | 0:dff8803aace7 | 993 | { |
cparata | 2:a94816b14e3d | 994 | lis2dw12_ctrl6_t ctrl6; |
cparata | 2:a94816b14e3d | 995 | lis2dw12_ctrl_reg7_t ctrl_reg7; |
cparata | 2:a94816b14e3d | 996 | int32_t ret; |
cparata | 0:dff8803aace7 | 997 | |
cparata | 2:a94816b14e3d | 998 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1); |
cparata | 2:a94816b14e3d | 999 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1000 | ctrl6.fds = ( (uint8_t) val & 0x10U ) >> 4; |
cparata | 2:a94816b14e3d | 1001 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1); |
cparata | 2:a94816b14e3d | 1002 | } |
cparata | 2:a94816b14e3d | 1003 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1004 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1); |
cparata | 2:a94816b14e3d | 1005 | } |
cparata | 2:a94816b14e3d | 1006 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1007 | ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U; |
cparata | 2:a94816b14e3d | 1008 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1); |
cparata | 2:a94816b14e3d | 1009 | } |
cparata | 0:dff8803aace7 | 1010 | |
cparata | 2:a94816b14e3d | 1011 | return ret; |
cparata | 0:dff8803aace7 | 1012 | } |
cparata | 0:dff8803aace7 | 1013 | |
cparata | 0:dff8803aace7 | 1014 | /** |
cparata | 2:a94816b14e3d | 1015 | * @brief Accelerometer filtering path for outputs.[get] |
cparata | 0:dff8803aace7 | 1016 | * |
cparata | 2:a94816b14e3d | 1017 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1018 | * @param val Get the values of fds in reg CTRL6 |
cparata | 2:a94816b14e3d | 1019 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1020 | * |
cparata | 0:dff8803aace7 | 1021 | */ |
cparata | 0:dff8803aace7 | 1022 | int32_t lis2dw12_filter_path_get(lis2dw12_ctx_t *ctx, lis2dw12_fds_t *val) |
cparata | 0:dff8803aace7 | 1023 | { |
cparata | 2:a94816b14e3d | 1024 | lis2dw12_ctrl6_t ctrl6; |
cparata | 2:a94816b14e3d | 1025 | lis2dw12_ctrl_reg7_t ctrl_reg7; |
cparata | 2:a94816b14e3d | 1026 | int32_t ret; |
cparata | 0:dff8803aace7 | 1027 | |
cparata | 2:a94816b14e3d | 1028 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) &ctrl6, 1); |
cparata | 2:a94816b14e3d | 1029 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1030 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1); |
cparata | 0:dff8803aace7 | 1031 | |
cparata | 2:a94816b14e3d | 1032 | switch ((ctrl6.fds << 4 ) + ctrl_reg7.usr_off_on_out) { |
cparata | 2:a94816b14e3d | 1033 | case LIS2DW12_LPF_ON_OUT: |
cparata | 2:a94816b14e3d | 1034 | *val = LIS2DW12_LPF_ON_OUT; |
cparata | 2:a94816b14e3d | 1035 | break; |
cparata | 2:a94816b14e3d | 1036 | case LIS2DW12_USER_OFFSET_ON_OUT: |
cparata | 2:a94816b14e3d | 1037 | *val = LIS2DW12_USER_OFFSET_ON_OUT; |
cparata | 2:a94816b14e3d | 1038 | break; |
cparata | 2:a94816b14e3d | 1039 | case LIS2DW12_HIGH_PASS_ON_OUT: |
cparata | 2:a94816b14e3d | 1040 | *val = LIS2DW12_HIGH_PASS_ON_OUT; |
cparata | 2:a94816b14e3d | 1041 | break; |
cparata | 2:a94816b14e3d | 1042 | default: |
cparata | 2:a94816b14e3d | 1043 | *val = LIS2DW12_LPF_ON_OUT; |
cparata | 2:a94816b14e3d | 1044 | break; |
cparata | 2:a94816b14e3d | 1045 | } |
cparata | 2:a94816b14e3d | 1046 | } |
cparata | 2:a94816b14e3d | 1047 | return ret; |
cparata | 0:dff8803aace7 | 1048 | } |
cparata | 0:dff8803aace7 | 1049 | |
cparata | 0:dff8803aace7 | 1050 | /** |
cparata | 2:a94816b14e3d | 1051 | * @brief Accelerometer cutoff filter frequency. Valid for low and high |
cparata | 2:a94816b14e3d | 1052 | * pass filter.[set] |
cparata | 0:dff8803aace7 | 1053 | * |
cparata | 2:a94816b14e3d | 1054 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1055 | * @param val change the values of bw_filt in reg CTRL6 |
cparata | 2:a94816b14e3d | 1056 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1057 | * |
cparata | 0:dff8803aace7 | 1058 | */ |
cparata | 0:dff8803aace7 | 1059 | int32_t lis2dw12_filter_bandwidth_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1060 | lis2dw12_bw_filt_t val) |
cparata | 0:dff8803aace7 | 1061 | { |
cparata | 2:a94816b14e3d | 1062 | lis2dw12_ctrl6_t reg; |
cparata | 2:a94816b14e3d | 1063 | int32_t ret; |
cparata | 0:dff8803aace7 | 1064 | |
cparata | 2:a94816b14e3d | 1065 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1066 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1067 | reg.bw_filt = (uint8_t) val; |
cparata | 2:a94816b14e3d | 1068 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1069 | } |
cparata | 0:dff8803aace7 | 1070 | |
cparata | 2:a94816b14e3d | 1071 | return ret; |
cparata | 0:dff8803aace7 | 1072 | } |
cparata | 0:dff8803aace7 | 1073 | |
cparata | 0:dff8803aace7 | 1074 | /** |
cparata | 2:a94816b14e3d | 1075 | * @brief Accelerometer cutoff filter frequency. Valid for low and |
cparata | 2:a94816b14e3d | 1076 | * high pass filter.[get] |
cparata | 0:dff8803aace7 | 1077 | * |
cparata | 2:a94816b14e3d | 1078 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1079 | * @param val Get the values of bw_filt in reg CTRL6 |
cparata | 2:a94816b14e3d | 1080 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1081 | * |
cparata | 0:dff8803aace7 | 1082 | */ |
cparata | 0:dff8803aace7 | 1083 | int32_t lis2dw12_filter_bandwidth_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1084 | lis2dw12_bw_filt_t *val) |
cparata | 0:dff8803aace7 | 1085 | { |
cparata | 2:a94816b14e3d | 1086 | lis2dw12_ctrl6_t reg; |
cparata | 2:a94816b14e3d | 1087 | int32_t ret; |
cparata | 2:a94816b14e3d | 1088 | |
cparata | 2:a94816b14e3d | 1089 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 1090 | |
cparata | 2:a94816b14e3d | 1091 | switch (reg.bw_filt) { |
cparata | 2:a94816b14e3d | 1092 | case LIS2DW12_ODR_DIV_2: |
cparata | 2:a94816b14e3d | 1093 | *val = LIS2DW12_ODR_DIV_2; |
cparata | 2:a94816b14e3d | 1094 | break; |
cparata | 2:a94816b14e3d | 1095 | case LIS2DW12_ODR_DIV_4: |
cparata | 2:a94816b14e3d | 1096 | *val = LIS2DW12_ODR_DIV_4; |
cparata | 2:a94816b14e3d | 1097 | break; |
cparata | 2:a94816b14e3d | 1098 | case LIS2DW12_ODR_DIV_10: |
cparata | 2:a94816b14e3d | 1099 | *val = LIS2DW12_ODR_DIV_10; |
cparata | 2:a94816b14e3d | 1100 | break; |
cparata | 2:a94816b14e3d | 1101 | case LIS2DW12_ODR_DIV_20: |
cparata | 2:a94816b14e3d | 1102 | *val = LIS2DW12_ODR_DIV_20; |
cparata | 2:a94816b14e3d | 1103 | break; |
cparata | 2:a94816b14e3d | 1104 | default: |
cparata | 2:a94816b14e3d | 1105 | *val = LIS2DW12_ODR_DIV_2; |
cparata | 2:a94816b14e3d | 1106 | break; |
cparata | 2:a94816b14e3d | 1107 | } |
cparata | 2:a94816b14e3d | 1108 | return ret; |
cparata | 0:dff8803aace7 | 1109 | } |
cparata | 0:dff8803aace7 | 1110 | |
cparata | 0:dff8803aace7 | 1111 | /** |
cparata | 2:a94816b14e3d | 1112 | * @brief Enable HP filter reference mode.[set] |
cparata | 0:dff8803aace7 | 1113 | * |
cparata | 2:a94816b14e3d | 1114 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1115 | * @param val change the values of hp_ref_mode in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1116 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1117 | * |
cparata | 0:dff8803aace7 | 1118 | */ |
cparata | 0:dff8803aace7 | 1119 | int32_t lis2dw12_reference_mode_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1120 | { |
cparata | 2:a94816b14e3d | 1121 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 1122 | int32_t ret; |
cparata | 0:dff8803aace7 | 1123 | |
cparata | 2:a94816b14e3d | 1124 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1125 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1126 | reg.hp_ref_mode = val; |
cparata | 2:a94816b14e3d | 1127 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1128 | } |
cparata | 2:a94816b14e3d | 1129 | return ret; |
cparata | 0:dff8803aace7 | 1130 | } |
cparata | 0:dff8803aace7 | 1131 | |
cparata | 0:dff8803aace7 | 1132 | /** |
cparata | 2:a94816b14e3d | 1133 | * @brief Enable HP filter reference mode.[get] |
cparata | 0:dff8803aace7 | 1134 | * |
cparata | 2:a94816b14e3d | 1135 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1136 | * @param val change the values of hp_ref_mode in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1137 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1138 | * |
cparata | 0:dff8803aace7 | 1139 | */ |
cparata | 0:dff8803aace7 | 1140 | int32_t lis2dw12_reference_mode_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1141 | { |
cparata | 2:a94816b14e3d | 1142 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 1143 | int32_t ret; |
cparata | 0:dff8803aace7 | 1144 | |
cparata | 2:a94816b14e3d | 1145 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1146 | *val = reg.hp_ref_mode; |
cparata | 0:dff8803aace7 | 1147 | |
cparata | 2:a94816b14e3d | 1148 | return ret; |
cparata | 0:dff8803aace7 | 1149 | } |
cparata | 0:dff8803aace7 | 1150 | |
cparata | 0:dff8803aace7 | 1151 | /** |
cparata | 0:dff8803aace7 | 1152 | * @} |
cparata | 2:a94816b14e3d | 1153 | * |
cparata | 0:dff8803aace7 | 1154 | */ |
cparata | 0:dff8803aace7 | 1155 | |
cparata | 0:dff8803aace7 | 1156 | /** |
cparata | 2:a94816b14e3d | 1157 | * @defgroup LIS2DW12_Serial_Interface |
cparata | 2:a94816b14e3d | 1158 | * @brief This section groups all the functions concerning main serial |
cparata | 2:a94816b14e3d | 1159 | * interface management (not auxiliary) |
cparata | 0:dff8803aace7 | 1160 | * @{ |
cparata | 2:a94816b14e3d | 1161 | * |
cparata | 0:dff8803aace7 | 1162 | */ |
cparata | 0:dff8803aace7 | 1163 | |
cparata | 0:dff8803aace7 | 1164 | /** |
cparata | 2:a94816b14e3d | 1165 | * @brief SPI Serial Interface Mode selection.[set] |
cparata | 0:dff8803aace7 | 1166 | * |
cparata | 2:a94816b14e3d | 1167 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1168 | * @param val change the values of sim in reg CTRL2 |
cparata | 2:a94816b14e3d | 1169 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1170 | * |
cparata | 0:dff8803aace7 | 1171 | */ |
cparata | 0:dff8803aace7 | 1172 | int32_t lis2dw12_spi_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sim_t val) |
cparata | 0:dff8803aace7 | 1173 | { |
cparata | 2:a94816b14e3d | 1174 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 1175 | int32_t ret; |
cparata | 0:dff8803aace7 | 1176 | |
cparata | 2:a94816b14e3d | 1177 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1178 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1179 | reg.sim = (uint8_t) val; |
cparata | 2:a94816b14e3d | 1180 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1181 | } |
cparata | 2:a94816b14e3d | 1182 | return ret; |
cparata | 0:dff8803aace7 | 1183 | } |
cparata | 0:dff8803aace7 | 1184 | |
cparata | 0:dff8803aace7 | 1185 | /** |
cparata | 2:a94816b14e3d | 1186 | * @brief SPI Serial Interface Mode selection.[get] |
cparata | 0:dff8803aace7 | 1187 | * |
cparata | 2:a94816b14e3d | 1188 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1189 | * @param val Get the values of sim in reg CTRL2 |
cparata | 2:a94816b14e3d | 1190 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1191 | * |
cparata | 0:dff8803aace7 | 1192 | */ |
cparata | 0:dff8803aace7 | 1193 | int32_t lis2dw12_spi_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_sim_t *val) |
cparata | 0:dff8803aace7 | 1194 | { |
cparata | 2:a94816b14e3d | 1195 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 1196 | int32_t ret; |
cparata | 2:a94816b14e3d | 1197 | |
cparata | 2:a94816b14e3d | 1198 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 1199 | |
cparata | 2:a94816b14e3d | 1200 | switch (reg.sim) { |
cparata | 2:a94816b14e3d | 1201 | case LIS2DW12_SPI_4_WIRE: |
cparata | 2:a94816b14e3d | 1202 | *val = LIS2DW12_SPI_4_WIRE; |
cparata | 2:a94816b14e3d | 1203 | break; |
cparata | 2:a94816b14e3d | 1204 | case LIS2DW12_SPI_3_WIRE: |
cparata | 2:a94816b14e3d | 1205 | *val = LIS2DW12_SPI_3_WIRE; |
cparata | 2:a94816b14e3d | 1206 | break; |
cparata | 2:a94816b14e3d | 1207 | default: |
cparata | 2:a94816b14e3d | 1208 | *val = LIS2DW12_SPI_4_WIRE; |
cparata | 2:a94816b14e3d | 1209 | break; |
cparata | 2:a94816b14e3d | 1210 | } |
cparata | 2:a94816b14e3d | 1211 | return ret; |
cparata | 0:dff8803aace7 | 1212 | } |
cparata | 0:dff8803aace7 | 1213 | |
cparata | 0:dff8803aace7 | 1214 | /** |
cparata | 2:a94816b14e3d | 1215 | * @brief Disable / Enable I2C interface.[set] |
cparata | 0:dff8803aace7 | 1216 | * |
cparata | 2:a94816b14e3d | 1217 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1218 | * @param val change the values of i2c_disable in |
cparata | 0:dff8803aace7 | 1219 | * reg CTRL2 |
cparata | 2:a94816b14e3d | 1220 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1221 | * |
cparata | 0:dff8803aace7 | 1222 | */ |
cparata | 0:dff8803aace7 | 1223 | int32_t lis2dw12_i2c_interface_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1224 | lis2dw12_i2c_disable_t val) |
cparata | 0:dff8803aace7 | 1225 | { |
cparata | 2:a94816b14e3d | 1226 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 1227 | int32_t ret; |
cparata | 0:dff8803aace7 | 1228 | |
cparata | 2:a94816b14e3d | 1229 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1230 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1231 | reg.i2c_disable = (uint8_t) val; |
cparata | 2:a94816b14e3d | 1232 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1233 | } |
cparata | 2:a94816b14e3d | 1234 | return ret; |
cparata | 0:dff8803aace7 | 1235 | } |
cparata | 0:dff8803aace7 | 1236 | |
cparata | 0:dff8803aace7 | 1237 | /** |
cparata | 2:a94816b14e3d | 1238 | * @brief Disable / Enable I2C interface.[get] |
cparata | 0:dff8803aace7 | 1239 | * |
cparata | 2:a94816b14e3d | 1240 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1241 | * @param val Get the values of i2c_disable in reg CTRL2 |
cparata | 2:a94816b14e3d | 1242 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1243 | * |
cparata | 0:dff8803aace7 | 1244 | */ |
cparata | 0:dff8803aace7 | 1245 | int32_t lis2dw12_i2c_interface_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1246 | lis2dw12_i2c_disable_t *val) |
cparata | 0:dff8803aace7 | 1247 | { |
cparata | 2:a94816b14e3d | 1248 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 1249 | int32_t ret; |
cparata | 2:a94816b14e3d | 1250 | |
cparata | 2:a94816b14e3d | 1251 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 1252 | |
cparata | 2:a94816b14e3d | 1253 | switch (reg.i2c_disable) { |
cparata | 2:a94816b14e3d | 1254 | case LIS2DW12_I2C_ENABLE: |
cparata | 2:a94816b14e3d | 1255 | *val = LIS2DW12_I2C_ENABLE; |
cparata | 2:a94816b14e3d | 1256 | break; |
cparata | 2:a94816b14e3d | 1257 | case LIS2DW12_I2C_DISABLE: |
cparata | 2:a94816b14e3d | 1258 | *val = LIS2DW12_I2C_DISABLE; |
cparata | 2:a94816b14e3d | 1259 | break; |
cparata | 2:a94816b14e3d | 1260 | default: |
cparata | 2:a94816b14e3d | 1261 | *val = LIS2DW12_I2C_ENABLE; |
cparata | 2:a94816b14e3d | 1262 | break; |
cparata | 2:a94816b14e3d | 1263 | } |
cparata | 2:a94816b14e3d | 1264 | return ret; |
cparata | 0:dff8803aace7 | 1265 | } |
cparata | 0:dff8803aace7 | 1266 | |
cparata | 0:dff8803aace7 | 1267 | /** |
cparata | 2:a94816b14e3d | 1268 | * @brief Disconnect CS pull-up.[set] |
cparata | 0:dff8803aace7 | 1269 | * |
cparata | 2:a94816b14e3d | 1270 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1271 | * @param val change the values of cs_pu_disc in reg CTRL2 |
cparata | 2:a94816b14e3d | 1272 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1273 | * |
cparata | 0:dff8803aace7 | 1274 | */ |
cparata | 0:dff8803aace7 | 1275 | int32_t lis2dw12_cs_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_cs_pu_disc_t val) |
cparata | 0:dff8803aace7 | 1276 | { |
cparata | 2:a94816b14e3d | 1277 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 1278 | int32_t ret; |
cparata | 0:dff8803aace7 | 1279 | |
cparata | 2:a94816b14e3d | 1280 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1281 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1282 | reg.cs_pu_disc = (uint8_t) val; |
cparata | 2:a94816b14e3d | 1283 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1284 | } |
cparata | 2:a94816b14e3d | 1285 | return ret; |
cparata | 0:dff8803aace7 | 1286 | } |
cparata | 0:dff8803aace7 | 1287 | |
cparata | 0:dff8803aace7 | 1288 | /** |
cparata | 2:a94816b14e3d | 1289 | * @brief Disconnect CS pull-up.[get] |
cparata | 0:dff8803aace7 | 1290 | * |
cparata | 2:a94816b14e3d | 1291 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1292 | * @param val Get the values of cs_pu_disc in reg CTRL2 |
cparata | 2:a94816b14e3d | 1293 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1294 | * |
cparata | 0:dff8803aace7 | 1295 | */ |
cparata | 0:dff8803aace7 | 1296 | int32_t lis2dw12_cs_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_cs_pu_disc_t *val) |
cparata | 0:dff8803aace7 | 1297 | { |
cparata | 2:a94816b14e3d | 1298 | lis2dw12_ctrl2_t reg; |
cparata | 2:a94816b14e3d | 1299 | int32_t ret; |
cparata | 2:a94816b14e3d | 1300 | |
cparata | 2:a94816b14e3d | 1301 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 1302 | |
cparata | 2:a94816b14e3d | 1303 | switch (reg.cs_pu_disc) { |
cparata | 2:a94816b14e3d | 1304 | case LIS2DW12_PULL_UP_CONNECT: |
cparata | 2:a94816b14e3d | 1305 | *val = LIS2DW12_PULL_UP_CONNECT; |
cparata | 2:a94816b14e3d | 1306 | break; |
cparata | 2:a94816b14e3d | 1307 | case LIS2DW12_PULL_UP_DISCONNECT: |
cparata | 2:a94816b14e3d | 1308 | *val = LIS2DW12_PULL_UP_DISCONNECT; |
cparata | 2:a94816b14e3d | 1309 | break; |
cparata | 2:a94816b14e3d | 1310 | default: |
cparata | 2:a94816b14e3d | 1311 | *val = LIS2DW12_PULL_UP_CONNECT; |
cparata | 2:a94816b14e3d | 1312 | break; |
cparata | 2:a94816b14e3d | 1313 | } |
cparata | 2:a94816b14e3d | 1314 | return ret; |
cparata | 0:dff8803aace7 | 1315 | } |
cparata | 0:dff8803aace7 | 1316 | |
cparata | 0:dff8803aace7 | 1317 | /** |
cparata | 0:dff8803aace7 | 1318 | * @} |
cparata | 2:a94816b14e3d | 1319 | * |
cparata | 0:dff8803aace7 | 1320 | */ |
cparata | 0:dff8803aace7 | 1321 | |
cparata | 0:dff8803aace7 | 1322 | /** |
cparata | 2:a94816b14e3d | 1323 | * @defgroup LIS2DW12_Interrupt_Pins |
cparata | 2:a94816b14e3d | 1324 | * @brief This section groups all the functions that manage interrupt pins |
cparata | 0:dff8803aace7 | 1325 | * @{ |
cparata | 2:a94816b14e3d | 1326 | * |
cparata | 0:dff8803aace7 | 1327 | */ |
cparata | 0:dff8803aace7 | 1328 | |
cparata | 0:dff8803aace7 | 1329 | /** |
cparata | 2:a94816b14e3d | 1330 | * @brief Interrupt active-high/low.[set] |
cparata | 0:dff8803aace7 | 1331 | * |
cparata | 2:a94816b14e3d | 1332 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1333 | * @param val change the values of h_lactive in reg CTRL3 |
cparata | 2:a94816b14e3d | 1334 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1335 | * |
cparata | 0:dff8803aace7 | 1336 | */ |
cparata | 0:dff8803aace7 | 1337 | int32_t lis2dw12_pin_polarity_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1338 | lis2dw12_h_lactive_t val) |
cparata | 0:dff8803aace7 | 1339 | { |
cparata | 2:a94816b14e3d | 1340 | lis2dw12_ctrl3_t reg; |
cparata | 2:a94816b14e3d | 1341 | int32_t ret; |
cparata | 0:dff8803aace7 | 1342 | |
cparata | 2:a94816b14e3d | 1343 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1344 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1345 | reg.h_lactive = (uint8_t) val; |
cparata | 2:a94816b14e3d | 1346 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1347 | } |
cparata | 2:a94816b14e3d | 1348 | return ret; |
cparata | 0:dff8803aace7 | 1349 | } |
cparata | 0:dff8803aace7 | 1350 | |
cparata | 0:dff8803aace7 | 1351 | /** |
cparata | 2:a94816b14e3d | 1352 | * @brief Interrupt active-high/low.[get] |
cparata | 0:dff8803aace7 | 1353 | * |
cparata | 2:a94816b14e3d | 1354 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1355 | * @param val Get the values of h_lactive in reg CTRL3 |
cparata | 2:a94816b14e3d | 1356 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1357 | * |
cparata | 0:dff8803aace7 | 1358 | */ |
cparata | 0:dff8803aace7 | 1359 | int32_t lis2dw12_pin_polarity_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1360 | lis2dw12_h_lactive_t *val) |
cparata | 0:dff8803aace7 | 1361 | { |
cparata | 2:a94816b14e3d | 1362 | lis2dw12_ctrl3_t reg; |
cparata | 2:a94816b14e3d | 1363 | int32_t ret; |
cparata | 2:a94816b14e3d | 1364 | |
cparata | 2:a94816b14e3d | 1365 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 1366 | |
cparata | 2:a94816b14e3d | 1367 | switch (reg.h_lactive) { |
cparata | 2:a94816b14e3d | 1368 | case LIS2DW12_ACTIVE_HIGH: |
cparata | 2:a94816b14e3d | 1369 | *val = LIS2DW12_ACTIVE_HIGH; |
cparata | 2:a94816b14e3d | 1370 | break; |
cparata | 2:a94816b14e3d | 1371 | case LIS2DW12_ACTIVE_LOW: |
cparata | 2:a94816b14e3d | 1372 | *val = LIS2DW12_ACTIVE_LOW; |
cparata | 2:a94816b14e3d | 1373 | break; |
cparata | 2:a94816b14e3d | 1374 | default: |
cparata | 2:a94816b14e3d | 1375 | *val = LIS2DW12_ACTIVE_HIGH; |
cparata | 2:a94816b14e3d | 1376 | break; |
cparata | 2:a94816b14e3d | 1377 | } |
cparata | 2:a94816b14e3d | 1378 | return ret; |
cparata | 0:dff8803aace7 | 1379 | } |
cparata | 0:dff8803aace7 | 1380 | |
cparata | 0:dff8803aace7 | 1381 | /** |
cparata | 2:a94816b14e3d | 1382 | * @brief Latched/pulsed interrupt.[set] |
cparata | 0:dff8803aace7 | 1383 | * |
cparata | 2:a94816b14e3d | 1384 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1385 | * @param val change the values of lir in reg CTRL3 |
cparata | 2:a94816b14e3d | 1386 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1387 | * |
cparata | 0:dff8803aace7 | 1388 | */ |
cparata | 0:dff8803aace7 | 1389 | int32_t lis2dw12_int_notification_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1390 | lis2dw12_lir_t val) |
cparata | 0:dff8803aace7 | 1391 | { |
cparata | 2:a94816b14e3d | 1392 | lis2dw12_ctrl3_t reg; |
cparata | 2:a94816b14e3d | 1393 | int32_t ret; |
cparata | 0:dff8803aace7 | 1394 | |
cparata | 2:a94816b14e3d | 1395 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1396 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1397 | reg.lir = (uint8_t) val; |
cparata | 2:a94816b14e3d | 1398 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1399 | } |
cparata | 2:a94816b14e3d | 1400 | return ret; |
cparata | 0:dff8803aace7 | 1401 | } |
cparata | 0:dff8803aace7 | 1402 | |
cparata | 0:dff8803aace7 | 1403 | /** |
cparata | 2:a94816b14e3d | 1404 | * @brief Latched/pulsed interrupt.[get] |
cparata | 0:dff8803aace7 | 1405 | * |
cparata | 2:a94816b14e3d | 1406 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1407 | * @param val Get the values of lir in reg CTRL3 |
cparata | 2:a94816b14e3d | 1408 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1409 | * |
cparata | 0:dff8803aace7 | 1410 | */ |
cparata | 0:dff8803aace7 | 1411 | int32_t lis2dw12_int_notification_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1412 | lis2dw12_lir_t *val) |
cparata | 0:dff8803aace7 | 1413 | { |
cparata | 2:a94816b14e3d | 1414 | lis2dw12_ctrl3_t reg; |
cparata | 2:a94816b14e3d | 1415 | int32_t ret; |
cparata | 2:a94816b14e3d | 1416 | |
cparata | 2:a94816b14e3d | 1417 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 1418 | |
cparata | 2:a94816b14e3d | 1419 | switch (reg.lir) { |
cparata | 2:a94816b14e3d | 1420 | case LIS2DW12_INT_PULSED: |
cparata | 2:a94816b14e3d | 1421 | *val = LIS2DW12_INT_PULSED; |
cparata | 2:a94816b14e3d | 1422 | break; |
cparata | 2:a94816b14e3d | 1423 | case LIS2DW12_INT_LATCHED: |
cparata | 2:a94816b14e3d | 1424 | *val = LIS2DW12_INT_LATCHED; |
cparata | 2:a94816b14e3d | 1425 | break; |
cparata | 2:a94816b14e3d | 1426 | default: |
cparata | 2:a94816b14e3d | 1427 | *val = LIS2DW12_INT_PULSED; |
cparata | 2:a94816b14e3d | 1428 | break; |
cparata | 2:a94816b14e3d | 1429 | } |
cparata | 2:a94816b14e3d | 1430 | return ret; |
cparata | 0:dff8803aace7 | 1431 | } |
cparata | 0:dff8803aace7 | 1432 | |
cparata | 0:dff8803aace7 | 1433 | /** |
cparata | 2:a94816b14e3d | 1434 | * @brief Push-pull/open drain selection on interrupt pads.[set] |
cparata | 0:dff8803aace7 | 1435 | * |
cparata | 2:a94816b14e3d | 1436 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1437 | * @param val change the values of pp_od in reg CTRL3 |
cparata | 2:a94816b14e3d | 1438 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1439 | * |
cparata | 0:dff8803aace7 | 1440 | */ |
cparata | 0:dff8803aace7 | 1441 | int32_t lis2dw12_pin_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_pp_od_t val) |
cparata | 0:dff8803aace7 | 1442 | { |
cparata | 2:a94816b14e3d | 1443 | lis2dw12_ctrl3_t reg; |
cparata | 2:a94816b14e3d | 1444 | int32_t ret; |
cparata | 0:dff8803aace7 | 1445 | |
cparata | 2:a94816b14e3d | 1446 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1447 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1448 | reg.pp_od = (uint8_t) val; |
cparata | 2:a94816b14e3d | 1449 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1450 | } |
cparata | 2:a94816b14e3d | 1451 | return ret; |
cparata | 0:dff8803aace7 | 1452 | } |
cparata | 0:dff8803aace7 | 1453 | |
cparata | 0:dff8803aace7 | 1454 | /** |
cparata | 2:a94816b14e3d | 1455 | * @brief Push-pull/open drain selection on interrupt pads.[get] |
cparata | 0:dff8803aace7 | 1456 | * |
cparata | 2:a94816b14e3d | 1457 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1458 | * @param val Get the values of pp_od in reg CTRL3 |
cparata | 2:a94816b14e3d | 1459 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1460 | * |
cparata | 0:dff8803aace7 | 1461 | */ |
cparata | 0:dff8803aace7 | 1462 | int32_t lis2dw12_pin_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_pp_od_t *val) |
cparata | 0:dff8803aace7 | 1463 | { |
cparata | 2:a94816b14e3d | 1464 | lis2dw12_ctrl3_t reg; |
cparata | 2:a94816b14e3d | 1465 | int32_t ret; |
cparata | 2:a94816b14e3d | 1466 | |
cparata | 2:a94816b14e3d | 1467 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 1468 | |
cparata | 2:a94816b14e3d | 1469 | switch (reg.pp_od) { |
cparata | 2:a94816b14e3d | 1470 | case LIS2DW12_PUSH_PULL: |
cparata | 2:a94816b14e3d | 1471 | *val = LIS2DW12_PUSH_PULL; |
cparata | 2:a94816b14e3d | 1472 | break; |
cparata | 2:a94816b14e3d | 1473 | case LIS2DW12_OPEN_DRAIN: |
cparata | 2:a94816b14e3d | 1474 | *val = LIS2DW12_OPEN_DRAIN; |
cparata | 2:a94816b14e3d | 1475 | break; |
cparata | 2:a94816b14e3d | 1476 | default: |
cparata | 2:a94816b14e3d | 1477 | *val = LIS2DW12_PUSH_PULL; |
cparata | 2:a94816b14e3d | 1478 | break; |
cparata | 2:a94816b14e3d | 1479 | } |
cparata | 2:a94816b14e3d | 1480 | return ret; |
cparata | 0:dff8803aace7 | 1481 | } |
cparata | 0:dff8803aace7 | 1482 | |
cparata | 0:dff8803aace7 | 1483 | /** |
cparata | 2:a94816b14e3d | 1484 | * @brief Select the signal that need to route on int1 pad.[set] |
cparata | 0:dff8803aace7 | 1485 | * |
cparata | 2:a94816b14e3d | 1486 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1487 | * @param val register CTRL4_INT1_PAD_CTRL. |
cparata | 2:a94816b14e3d | 1488 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1489 | * |
cparata | 0:dff8803aace7 | 1490 | */ |
cparata | 0:dff8803aace7 | 1491 | int32_t lis2dw12_pin_int1_route_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1492 | lis2dw12_ctrl4_int1_pad_ctrl_t *val) |
cparata | 0:dff8803aace7 | 1493 | { |
cparata | 2:a94816b14e3d | 1494 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 1495 | int32_t ret; |
cparata | 0:dff8803aace7 | 1496 | |
cparata | 2:a94816b14e3d | 1497 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1498 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1499 | if ((val->int1_tap | val->int1_ff | val->int1_wu | val->int1_single_tap | |
cparata | 2:a94816b14e3d | 1500 | val->int1_6d) != PROPERTY_DISABLE){ |
cparata | 2:a94816b14e3d | 1501 | reg.interrupts_enable = PROPERTY_ENABLE; |
cparata | 2:a94816b14e3d | 1502 | } |
cparata | 2:a94816b14e3d | 1503 | else{ |
cparata | 2:a94816b14e3d | 1504 | reg.interrupts_enable = PROPERTY_DISABLE; |
cparata | 2:a94816b14e3d | 1505 | } |
cparata | 2:a94816b14e3d | 1506 | |
cparata | 2:a94816b14e3d | 1507 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL, |
cparata | 0:dff8803aace7 | 1508 | (uint8_t*) val, 1); |
cparata | 2:a94816b14e3d | 1509 | } if (ret == 0) { |
cparata | 2:a94816b14e3d | 1510 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1511 | } |
cparata | 2:a94816b14e3d | 1512 | return ret; |
cparata | 0:dff8803aace7 | 1513 | } |
cparata | 0:dff8803aace7 | 1514 | |
cparata | 0:dff8803aace7 | 1515 | /** |
cparata | 2:a94816b14e3d | 1516 | * @brief Select the signal that need to route on int1 pad.[get] |
cparata | 0:dff8803aace7 | 1517 | * |
cparata | 2:a94816b14e3d | 1518 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1519 | * @param val register CTRL4_INT1_PAD_CTRL. |
cparata | 2:a94816b14e3d | 1520 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1521 | * |
cparata | 0:dff8803aace7 | 1522 | */ |
cparata | 0:dff8803aace7 | 1523 | int32_t lis2dw12_pin_int1_route_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1524 | lis2dw12_ctrl4_int1_pad_ctrl_t *val) |
cparata | 0:dff8803aace7 | 1525 | { |
cparata | 2:a94816b14e3d | 1526 | int32_t ret; |
cparata | 2:a94816b14e3d | 1527 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL, |
cparata | 2:a94816b14e3d | 1528 | (uint8_t*) val, 1); |
cparata | 2:a94816b14e3d | 1529 | return ret; |
cparata | 0:dff8803aace7 | 1530 | } |
cparata | 2:a94816b14e3d | 1531 | |
cparata | 0:dff8803aace7 | 1532 | /** |
cparata | 2:a94816b14e3d | 1533 | * @brief Select the signal that need to route on int2 pad.[set] |
cparata | 0:dff8803aace7 | 1534 | * |
cparata | 2:a94816b14e3d | 1535 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1536 | * @param val register CTRL5_INT2_PAD_CTRL. |
cparata | 2:a94816b14e3d | 1537 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1538 | * |
cparata | 0:dff8803aace7 | 1539 | */ |
cparata | 0:dff8803aace7 | 1540 | int32_t lis2dw12_pin_int2_route_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1541 | lis2dw12_ctrl5_int2_pad_ctrl_t *val) |
cparata | 0:dff8803aace7 | 1542 | { |
cparata | 2:a94816b14e3d | 1543 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 1544 | int32_t ret; |
cparata | 0:dff8803aace7 | 1545 | |
cparata | 2:a94816b14e3d | 1546 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1547 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1548 | if ((val->int2_sleep_state | val->int2_sleep_chg ) != PROPERTY_DISABLE) { |
cparata | 2:a94816b14e3d | 1549 | reg.interrupts_enable = PROPERTY_ENABLE; |
cparata | 2:a94816b14e3d | 1550 | } |
cparata | 2:a94816b14e3d | 1551 | else{ |
cparata | 2:a94816b14e3d | 1552 | reg.interrupts_enable = PROPERTY_DISABLE; |
cparata | 2:a94816b14e3d | 1553 | } |
cparata | 2:a94816b14e3d | 1554 | |
cparata | 2:a94816b14e3d | 1555 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL, |
cparata | 2:a94816b14e3d | 1556 | (uint8_t*) val, 1); |
cparata | 0:dff8803aace7 | 1557 | } |
cparata | 2:a94816b14e3d | 1558 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1559 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1560 | } |
cparata | 2:a94816b14e3d | 1561 | |
cparata | 2:a94816b14e3d | 1562 | return ret; |
cparata | 0:dff8803aace7 | 1563 | } |
cparata | 0:dff8803aace7 | 1564 | |
cparata | 0:dff8803aace7 | 1565 | /** |
cparata | 2:a94816b14e3d | 1566 | * @brief Select the signal that need to route on int2 pad.[get] |
cparata | 0:dff8803aace7 | 1567 | * |
cparata | 2:a94816b14e3d | 1568 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1569 | * @param val register CTRL5_INT2_PAD_CTRL |
cparata | 2:a94816b14e3d | 1570 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1571 | * |
cparata | 0:dff8803aace7 | 1572 | */ |
cparata | 0:dff8803aace7 | 1573 | int32_t lis2dw12_pin_int2_route_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1574 | lis2dw12_ctrl5_int2_pad_ctrl_t *val) |
cparata | 0:dff8803aace7 | 1575 | { |
cparata | 2:a94816b14e3d | 1576 | int32_t ret; |
cparata | 2:a94816b14e3d | 1577 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL, |
cparata | 2:a94816b14e3d | 1578 | (uint8_t*) val, 1); |
cparata | 2:a94816b14e3d | 1579 | return ret; |
cparata | 0:dff8803aace7 | 1580 | } |
cparata | 0:dff8803aace7 | 1581 | /** |
cparata | 2:a94816b14e3d | 1582 | * @brief All interrupt signals become available on INT1 pin.[set] |
cparata | 0:dff8803aace7 | 1583 | * |
cparata | 2:a94816b14e3d | 1584 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1585 | * @param val change the values of int2_on_int1 in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1586 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1587 | * |
cparata | 0:dff8803aace7 | 1588 | */ |
cparata | 0:dff8803aace7 | 1589 | int32_t lis2dw12_all_on_int1_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1590 | { |
cparata | 2:a94816b14e3d | 1591 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 1592 | int32_t ret; |
cparata | 0:dff8803aace7 | 1593 | |
cparata | 2:a94816b14e3d | 1594 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1595 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1596 | reg.int2_on_int1 = val; |
cparata | 2:a94816b14e3d | 1597 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1598 | } |
cparata | 2:a94816b14e3d | 1599 | return ret; |
cparata | 0:dff8803aace7 | 1600 | } |
cparata | 0:dff8803aace7 | 1601 | |
cparata | 0:dff8803aace7 | 1602 | /** |
cparata | 2:a94816b14e3d | 1603 | * @brief All interrupt signals become available on INT1 pin.[get] |
cparata | 0:dff8803aace7 | 1604 | * |
cparata | 2:a94816b14e3d | 1605 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1606 | * @param val change the values of int2_on_int1 in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1607 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1608 | * |
cparata | 0:dff8803aace7 | 1609 | */ |
cparata | 0:dff8803aace7 | 1610 | int32_t lis2dw12_all_on_int1_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1611 | { |
cparata | 2:a94816b14e3d | 1612 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 1613 | int32_t ret; |
cparata | 0:dff8803aace7 | 1614 | |
cparata | 2:a94816b14e3d | 1615 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1616 | *val = reg.int2_on_int1; |
cparata | 0:dff8803aace7 | 1617 | |
cparata | 2:a94816b14e3d | 1618 | return ret; |
cparata | 0:dff8803aace7 | 1619 | } |
cparata | 0:dff8803aace7 | 1620 | |
cparata | 0:dff8803aace7 | 1621 | /** |
cparata | 0:dff8803aace7 | 1622 | * @} |
cparata | 2:a94816b14e3d | 1623 | * |
cparata | 0:dff8803aace7 | 1624 | */ |
cparata | 0:dff8803aace7 | 1625 | |
cparata | 0:dff8803aace7 | 1626 | /** |
cparata | 2:a94816b14e3d | 1627 | * @defgroup LIS2DW12_Wake_Up_Event |
cparata | 2:a94816b14e3d | 1628 | * @brief This section groups all the functions that manage the Wake |
cparata | 2:a94816b14e3d | 1629 | * Up event generation. |
cparata | 0:dff8803aace7 | 1630 | * @{ |
cparata | 2:a94816b14e3d | 1631 | * |
cparata | 0:dff8803aace7 | 1632 | */ |
cparata | 0:dff8803aace7 | 1633 | |
cparata | 0:dff8803aace7 | 1634 | /** |
cparata | 2:a94816b14e3d | 1635 | * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set] |
cparata | 0:dff8803aace7 | 1636 | * |
cparata | 2:a94816b14e3d | 1637 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1638 | * @param val change the values of wk_ths in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 1639 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1640 | * |
cparata | 0:dff8803aace7 | 1641 | */ |
cparata | 0:dff8803aace7 | 1642 | int32_t lis2dw12_wkup_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1643 | { |
cparata | 2:a94816b14e3d | 1644 | lis2dw12_wake_up_ths_t reg; |
cparata | 2:a94816b14e3d | 1645 | int32_t ret; |
cparata | 0:dff8803aace7 | 1646 | |
cparata | 2:a94816b14e3d | 1647 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1648 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1649 | reg.wk_ths = val; |
cparata | 2:a94816b14e3d | 1650 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1651 | } |
cparata | 2:a94816b14e3d | 1652 | return ret; |
cparata | 0:dff8803aace7 | 1653 | } |
cparata | 0:dff8803aace7 | 1654 | |
cparata | 0:dff8803aace7 | 1655 | /** |
cparata | 2:a94816b14e3d | 1656 | * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get] |
cparata | 0:dff8803aace7 | 1657 | * |
cparata | 2:a94816b14e3d | 1658 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1659 | * @param val change the values of wk_ths in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 1660 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1661 | * |
cparata | 0:dff8803aace7 | 1662 | */ |
cparata | 0:dff8803aace7 | 1663 | int32_t lis2dw12_wkup_threshold_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1664 | { |
cparata | 2:a94816b14e3d | 1665 | lis2dw12_wake_up_ths_t reg; |
cparata | 2:a94816b14e3d | 1666 | int32_t ret; |
cparata | 0:dff8803aace7 | 1667 | |
cparata | 2:a94816b14e3d | 1668 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1669 | *val = reg.wk_ths; |
cparata | 0:dff8803aace7 | 1670 | |
cparata | 2:a94816b14e3d | 1671 | return ret; |
cparata | 0:dff8803aace7 | 1672 | } |
cparata | 0:dff8803aace7 | 1673 | |
cparata | 0:dff8803aace7 | 1674 | /** |
cparata | 2:a94816b14e3d | 1675 | * @brief Wake up duration event.1LSb = 1 / ODR.[set] |
cparata | 0:dff8803aace7 | 1676 | * |
cparata | 2:a94816b14e3d | 1677 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1678 | * @param val change the values of wake_dur in reg WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1679 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1680 | * |
cparata | 0:dff8803aace7 | 1681 | */ |
cparata | 0:dff8803aace7 | 1682 | int32_t lis2dw12_wkup_dur_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1683 | { |
cparata | 2:a94816b14e3d | 1684 | lis2dw12_wake_up_dur_t reg; |
cparata | 2:a94816b14e3d | 1685 | int32_t ret; |
cparata | 0:dff8803aace7 | 1686 | |
cparata | 2:a94816b14e3d | 1687 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1688 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1689 | reg.wake_dur = val; |
cparata | 2:a94816b14e3d | 1690 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1691 | } |
cparata | 2:a94816b14e3d | 1692 | return ret; |
cparata | 0:dff8803aace7 | 1693 | } |
cparata | 0:dff8803aace7 | 1694 | |
cparata | 0:dff8803aace7 | 1695 | /** |
cparata | 2:a94816b14e3d | 1696 | * @brief Wake up duration event.1LSb = 1 / ODR.[get] |
cparata | 0:dff8803aace7 | 1697 | * |
cparata | 2:a94816b14e3d | 1698 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1699 | * @param val change the values of wake_dur in reg WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1700 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1701 | * |
cparata | 0:dff8803aace7 | 1702 | */ |
cparata | 0:dff8803aace7 | 1703 | int32_t lis2dw12_wkup_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1704 | { |
cparata | 2:a94816b14e3d | 1705 | lis2dw12_wake_up_dur_t reg; |
cparata | 2:a94816b14e3d | 1706 | int32_t ret; |
cparata | 0:dff8803aace7 | 1707 | |
cparata | 2:a94816b14e3d | 1708 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1709 | *val = reg.wake_dur; |
cparata | 0:dff8803aace7 | 1710 | |
cparata | 2:a94816b14e3d | 1711 | return ret; |
cparata | 0:dff8803aace7 | 1712 | } |
cparata | 0:dff8803aace7 | 1713 | |
cparata | 0:dff8803aace7 | 1714 | /** |
cparata | 2:a94816b14e3d | 1715 | * @brief Data sent to wake-up interrupt function.[set] |
cparata | 0:dff8803aace7 | 1716 | * |
cparata | 2:a94816b14e3d | 1717 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1718 | * @param val change the values of usr_off_on_wu in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1719 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1720 | * |
cparata | 0:dff8803aace7 | 1721 | */ |
cparata | 0:dff8803aace7 | 1722 | int32_t lis2dw12_wkup_feed_data_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1723 | lis2dw12_usr_off_on_wu_t val) |
cparata | 0:dff8803aace7 | 1724 | { |
cparata | 2:a94816b14e3d | 1725 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 1726 | int32_t ret; |
cparata | 0:dff8803aace7 | 1727 | |
cparata | 2:a94816b14e3d | 1728 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1729 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1730 | reg.usr_off_on_wu = (uint8_t) val; |
cparata | 2:a94816b14e3d | 1731 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1732 | } |
cparata | 2:a94816b14e3d | 1733 | return ret; |
cparata | 0:dff8803aace7 | 1734 | } |
cparata | 0:dff8803aace7 | 1735 | |
cparata | 0:dff8803aace7 | 1736 | /** |
cparata | 2:a94816b14e3d | 1737 | * @brief Data sent to wake-up interrupt function.[get] |
cparata | 0:dff8803aace7 | 1738 | * |
cparata | 2:a94816b14e3d | 1739 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1740 | * @param val Get the values of usr_off_on_wu in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 1741 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1742 | * |
cparata | 0:dff8803aace7 | 1743 | */ |
cparata | 0:dff8803aace7 | 1744 | int32_t lis2dw12_wkup_feed_data_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1745 | lis2dw12_usr_off_on_wu_t *val) |
cparata | 0:dff8803aace7 | 1746 | { |
cparata | 2:a94816b14e3d | 1747 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 1748 | int32_t ret; |
cparata | 2:a94816b14e3d | 1749 | |
cparata | 2:a94816b14e3d | 1750 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 1751 | |
cparata | 2:a94816b14e3d | 1752 | switch (reg.usr_off_on_wu) { |
cparata | 2:a94816b14e3d | 1753 | case LIS2DW12_HP_FEED: |
cparata | 2:a94816b14e3d | 1754 | *val = LIS2DW12_HP_FEED; |
cparata | 2:a94816b14e3d | 1755 | break; |
cparata | 2:a94816b14e3d | 1756 | case LIS2DW12_USER_OFFSET_FEED: |
cparata | 2:a94816b14e3d | 1757 | *val = LIS2DW12_USER_OFFSET_FEED; |
cparata | 2:a94816b14e3d | 1758 | break; |
cparata | 2:a94816b14e3d | 1759 | default: |
cparata | 2:a94816b14e3d | 1760 | *val = LIS2DW12_HP_FEED; |
cparata | 2:a94816b14e3d | 1761 | break; |
cparata | 2:a94816b14e3d | 1762 | } |
cparata | 2:a94816b14e3d | 1763 | return ret; |
cparata | 0:dff8803aace7 | 1764 | } |
cparata | 0:dff8803aace7 | 1765 | |
cparata | 0:dff8803aace7 | 1766 | /** |
cparata | 0:dff8803aace7 | 1767 | * @} |
cparata | 2:a94816b14e3d | 1768 | * |
cparata | 0:dff8803aace7 | 1769 | */ |
cparata | 0:dff8803aace7 | 1770 | |
cparata | 0:dff8803aace7 | 1771 | /** |
cparata | 2:a94816b14e3d | 1772 | * @defgroup LIS2DW12_Activity/Inactivity_Detection |
cparata | 2:a94816b14e3d | 1773 | * @brief This section groups all the functions concerning |
cparata | 2:a94816b14e3d | 1774 | * activity/inactivity detection. |
cparata | 0:dff8803aace7 | 1775 | * @{ |
cparata | 2:a94816b14e3d | 1776 | * |
cparata | 0:dff8803aace7 | 1777 | */ |
cparata | 0:dff8803aace7 | 1778 | |
cparata | 0:dff8803aace7 | 1779 | /** |
cparata | 2:a94816b14e3d | 1780 | * @brief Config activity / inactivity or |
cparata | 2:a94816b14e3d | 1781 | * stationary / motion detection.[set] |
cparata | 0:dff8803aace7 | 1782 | * |
cparata | 2:a94816b14e3d | 1783 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1784 | * @param val change the values of sleep_on / stationary in |
cparata | 2:a94816b14e3d | 1785 | * reg WAKE_UP_THS / WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1786 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1787 | * |
cparata | 0:dff8803aace7 | 1788 | */ |
cparata | 0:dff8803aace7 | 1789 | int32_t lis2dw12_act_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sleep_on_t val) |
cparata | 0:dff8803aace7 | 1790 | { |
cparata | 2:a94816b14e3d | 1791 | lis2dw12_wake_up_ths_t wake_up_ths; |
cparata | 2:a94816b14e3d | 1792 | lis2dw12_wake_up_dur_t wake_up_dur; |
cparata | 2:a94816b14e3d | 1793 | int32_t ret; |
cparata | 2:a94816b14e3d | 1794 | |
cparata | 2:a94816b14e3d | 1795 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1); |
cparata | 2:a94816b14e3d | 1796 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1797 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); |
cparata | 2:a94816b14e3d | 1798 | } |
cparata | 2:a94816b14e3d | 1799 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1800 | wake_up_ths.sleep_on = (uint8_t) val & 0x01U; |
cparata | 2:a94816b14e3d | 1801 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1); |
cparata | 2:a94816b14e3d | 1802 | } |
cparata | 2:a94816b14e3d | 1803 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1804 | wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1; |
cparata | 2:a94816b14e3d | 1805 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); |
cparata | 2:a94816b14e3d | 1806 | } |
cparata | 2:a94816b14e3d | 1807 | |
cparata | 2:a94816b14e3d | 1808 | return ret; |
cparata | 0:dff8803aace7 | 1809 | } |
cparata | 0:dff8803aace7 | 1810 | |
cparata | 0:dff8803aace7 | 1811 | /** |
cparata | 2:a94816b14e3d | 1812 | * @brief Config activity / inactivity or |
cparata | 2:a94816b14e3d | 1813 | * stationary / motion detection. [get] |
cparata | 0:dff8803aace7 | 1814 | * |
cparata | 2:a94816b14e3d | 1815 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1816 | * @param val Get the values of sleep_on in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 1817 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1818 | * |
cparata | 0:dff8803aace7 | 1819 | */ |
cparata | 0:dff8803aace7 | 1820 | int32_t lis2dw12_act_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_sleep_on_t *val) |
cparata | 0:dff8803aace7 | 1821 | { |
cparata | 2:a94816b14e3d | 1822 | lis2dw12_wake_up_ths_t wake_up_ths; |
cparata | 2:a94816b14e3d | 1823 | lis2dw12_wake_up_dur_t wake_up_dur;; |
cparata | 2:a94816b14e3d | 1824 | int32_t ret; |
cparata | 2:a94816b14e3d | 1825 | |
cparata | 2:a94816b14e3d | 1826 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1); |
cparata | 2:a94816b14e3d | 1827 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1828 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); |
cparata | 0:dff8803aace7 | 1829 | |
cparata | 2:a94816b14e3d | 1830 | switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on){ |
cparata | 2:a94816b14e3d | 1831 | case LIS2DW12_NO_DETECTION: |
cparata | 2:a94816b14e3d | 1832 | *val = LIS2DW12_NO_DETECTION; |
cparata | 2:a94816b14e3d | 1833 | break; |
cparata | 2:a94816b14e3d | 1834 | case LIS2DW12_DETECT_ACT_INACT: |
cparata | 2:a94816b14e3d | 1835 | *val = LIS2DW12_DETECT_ACT_INACT; |
cparata | 2:a94816b14e3d | 1836 | break; |
cparata | 2:a94816b14e3d | 1837 | case LIS2DW12_DETECT_STAT_MOTION: |
cparata | 2:a94816b14e3d | 1838 | *val = LIS2DW12_DETECT_STAT_MOTION; |
cparata | 2:a94816b14e3d | 1839 | break; |
cparata | 2:a94816b14e3d | 1840 | default: |
cparata | 2:a94816b14e3d | 1841 | *val = LIS2DW12_NO_DETECTION; |
cparata | 2:a94816b14e3d | 1842 | break; |
cparata | 2:a94816b14e3d | 1843 | } |
cparata | 2:a94816b14e3d | 1844 | } |
cparata | 2:a94816b14e3d | 1845 | return ret; |
cparata | 0:dff8803aace7 | 1846 | } |
cparata | 0:dff8803aace7 | 1847 | |
cparata | 0:dff8803aace7 | 1848 | /** |
cparata | 2:a94816b14e3d | 1849 | * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set] |
cparata | 0:dff8803aace7 | 1850 | * |
cparata | 2:a94816b14e3d | 1851 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1852 | * @param val change the values of sleep_dur in reg WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1853 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1854 | * |
cparata | 0:dff8803aace7 | 1855 | */ |
cparata | 0:dff8803aace7 | 1856 | int32_t lis2dw12_act_sleep_dur_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1857 | { |
cparata | 2:a94816b14e3d | 1858 | lis2dw12_wake_up_dur_t reg; |
cparata | 2:a94816b14e3d | 1859 | int32_t ret; |
cparata | 0:dff8803aace7 | 1860 | |
cparata | 2:a94816b14e3d | 1861 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1862 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1863 | reg.sleep_dur = val; |
cparata | 2:a94816b14e3d | 1864 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1865 | } |
cparata | 2:a94816b14e3d | 1866 | return ret; |
cparata | 0:dff8803aace7 | 1867 | } |
cparata | 0:dff8803aace7 | 1868 | |
cparata | 0:dff8803aace7 | 1869 | /** |
cparata | 2:a94816b14e3d | 1870 | * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get] |
cparata | 0:dff8803aace7 | 1871 | * |
cparata | 2:a94816b14e3d | 1872 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1873 | * @param val change the values of sleep_dur in reg WAKE_UP_DUR |
cparata | 2:a94816b14e3d | 1874 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1875 | * |
cparata | 0:dff8803aace7 | 1876 | */ |
cparata | 0:dff8803aace7 | 1877 | int32_t lis2dw12_act_sleep_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1878 | { |
cparata | 2:a94816b14e3d | 1879 | lis2dw12_wake_up_dur_t reg; |
cparata | 2:a94816b14e3d | 1880 | int32_t ret; |
cparata | 0:dff8803aace7 | 1881 | |
cparata | 2:a94816b14e3d | 1882 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1883 | *val = reg.sleep_dur; |
cparata | 0:dff8803aace7 | 1884 | |
cparata | 2:a94816b14e3d | 1885 | return ret; |
cparata | 0:dff8803aace7 | 1886 | } |
cparata | 0:dff8803aace7 | 1887 | |
cparata | 0:dff8803aace7 | 1888 | /** |
cparata | 0:dff8803aace7 | 1889 | * @} |
cparata | 2:a94816b14e3d | 1890 | * |
cparata | 0:dff8803aace7 | 1891 | */ |
cparata | 0:dff8803aace7 | 1892 | |
cparata | 0:dff8803aace7 | 1893 | /** |
cparata | 2:a94816b14e3d | 1894 | * @defgroup LIS2DW12_Tap_Generator |
cparata | 2:a94816b14e3d | 1895 | * @brief This section groups all the functions that manage the tap |
cparata | 2:a94816b14e3d | 1896 | * and double tap event generation. |
cparata | 0:dff8803aace7 | 1897 | * @{ |
cparata | 2:a94816b14e3d | 1898 | * |
cparata | 0:dff8803aace7 | 1899 | */ |
cparata | 0:dff8803aace7 | 1900 | |
cparata | 0:dff8803aace7 | 1901 | /** |
cparata | 2:a94816b14e3d | 1902 | * @brief Threshold for tap recognition.[set] |
cparata | 0:dff8803aace7 | 1903 | * |
cparata | 2:a94816b14e3d | 1904 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1905 | * @param val change the values of tap_thsx in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 1906 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1907 | * |
cparata | 0:dff8803aace7 | 1908 | */ |
cparata | 0:dff8803aace7 | 1909 | int32_t lis2dw12_tap_threshold_x_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1910 | { |
cparata | 2:a94816b14e3d | 1911 | lis2dw12_tap_ths_x_t reg; |
cparata | 2:a94816b14e3d | 1912 | int32_t ret; |
cparata | 0:dff8803aace7 | 1913 | |
cparata | 2:a94816b14e3d | 1914 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1915 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1916 | reg.tap_thsx = val; |
cparata | 2:a94816b14e3d | 1917 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1918 | } |
cparata | 2:a94816b14e3d | 1919 | return ret; |
cparata | 0:dff8803aace7 | 1920 | } |
cparata | 0:dff8803aace7 | 1921 | |
cparata | 0:dff8803aace7 | 1922 | /** |
cparata | 2:a94816b14e3d | 1923 | * @brief Threshold for tap recognition.[get] |
cparata | 0:dff8803aace7 | 1924 | * |
cparata | 2:a94816b14e3d | 1925 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1926 | * @param val change the values of tap_thsx in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 1927 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1928 | * |
cparata | 0:dff8803aace7 | 1929 | */ |
cparata | 0:dff8803aace7 | 1930 | int32_t lis2dw12_tap_threshold_x_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1931 | { |
cparata | 2:a94816b14e3d | 1932 | lis2dw12_tap_ths_x_t reg; |
cparata | 2:a94816b14e3d | 1933 | int32_t ret; |
cparata | 0:dff8803aace7 | 1934 | |
cparata | 2:a94816b14e3d | 1935 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1936 | *val = reg.tap_thsx; |
cparata | 0:dff8803aace7 | 1937 | |
cparata | 2:a94816b14e3d | 1938 | return ret; |
cparata | 0:dff8803aace7 | 1939 | } |
cparata | 0:dff8803aace7 | 1940 | |
cparata | 0:dff8803aace7 | 1941 | /** |
cparata | 2:a94816b14e3d | 1942 | * @brief Threshold for tap recognition.[set] |
cparata | 0:dff8803aace7 | 1943 | * |
cparata | 2:a94816b14e3d | 1944 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1945 | * @param val change the values of tap_thsy in reg TAP_THS_Y |
cparata | 2:a94816b14e3d | 1946 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1947 | * |
cparata | 0:dff8803aace7 | 1948 | */ |
cparata | 0:dff8803aace7 | 1949 | int32_t lis2dw12_tap_threshold_y_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 1950 | { |
cparata | 2:a94816b14e3d | 1951 | lis2dw12_tap_ths_y_t reg; |
cparata | 2:a94816b14e3d | 1952 | int32_t ret; |
cparata | 0:dff8803aace7 | 1953 | |
cparata | 2:a94816b14e3d | 1954 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1955 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1956 | reg.tap_thsy = val; |
cparata | 2:a94816b14e3d | 1957 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1958 | } |
cparata | 2:a94816b14e3d | 1959 | return ret; |
cparata | 0:dff8803aace7 | 1960 | } |
cparata | 0:dff8803aace7 | 1961 | |
cparata | 0:dff8803aace7 | 1962 | /** |
cparata | 2:a94816b14e3d | 1963 | * @brief Threshold for tap recognition.[get] |
cparata | 0:dff8803aace7 | 1964 | * |
cparata | 2:a94816b14e3d | 1965 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1966 | * @param val change the values of tap_thsy in reg TAP_THS_Y |
cparata | 2:a94816b14e3d | 1967 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1968 | * |
cparata | 0:dff8803aace7 | 1969 | */ |
cparata | 0:dff8803aace7 | 1970 | int32_t lis2dw12_tap_threshold_y_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 1971 | { |
cparata | 2:a94816b14e3d | 1972 | lis2dw12_tap_ths_y_t reg; |
cparata | 2:a94816b14e3d | 1973 | int32_t ret; |
cparata | 0:dff8803aace7 | 1974 | |
cparata | 2:a94816b14e3d | 1975 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1976 | *val = reg.tap_thsy; |
cparata | 0:dff8803aace7 | 1977 | |
cparata | 2:a94816b14e3d | 1978 | return ret; |
cparata | 0:dff8803aace7 | 1979 | } |
cparata | 0:dff8803aace7 | 1980 | |
cparata | 0:dff8803aace7 | 1981 | /** |
cparata | 2:a94816b14e3d | 1982 | * @brief Selection of axis priority for TAP detection.[set] |
cparata | 0:dff8803aace7 | 1983 | * |
cparata | 2:a94816b14e3d | 1984 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 1985 | * @param val change the values of tap_prior in reg TAP_THS_Y |
cparata | 2:a94816b14e3d | 1986 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 1987 | * |
cparata | 0:dff8803aace7 | 1988 | */ |
cparata | 0:dff8803aace7 | 1989 | int32_t lis2dw12_tap_axis_priority_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 1990 | lis2dw12_tap_prior_t val) |
cparata | 0:dff8803aace7 | 1991 | { |
cparata | 2:a94816b14e3d | 1992 | lis2dw12_tap_ths_y_t reg; |
cparata | 2:a94816b14e3d | 1993 | int32_t ret; |
cparata | 0:dff8803aace7 | 1994 | |
cparata | 2:a94816b14e3d | 1995 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1996 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 1997 | reg.tap_prior = (uint8_t) val; |
cparata | 2:a94816b14e3d | 1998 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 1999 | } |
cparata | 2:a94816b14e3d | 2000 | return ret; |
cparata | 0:dff8803aace7 | 2001 | } |
cparata | 0:dff8803aace7 | 2002 | |
cparata | 0:dff8803aace7 | 2003 | /** |
cparata | 2:a94816b14e3d | 2004 | * @brief Selection of axis priority for TAP detection.[get] |
cparata | 0:dff8803aace7 | 2005 | * |
cparata | 2:a94816b14e3d | 2006 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2007 | * @param val Get the values of tap_prior in reg TAP_THS_Y |
cparata | 2:a94816b14e3d | 2008 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2009 | * |
cparata | 0:dff8803aace7 | 2010 | */ |
cparata | 0:dff8803aace7 | 2011 | int32_t lis2dw12_tap_axis_priority_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2012 | lis2dw12_tap_prior_t *val) |
cparata | 0:dff8803aace7 | 2013 | { |
cparata | 2:a94816b14e3d | 2014 | lis2dw12_tap_ths_y_t reg; |
cparata | 2:a94816b14e3d | 2015 | int32_t ret; |
cparata | 2:a94816b14e3d | 2016 | |
cparata | 2:a94816b14e3d | 2017 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 2018 | |
cparata | 2:a94816b14e3d | 2019 | switch (reg.tap_prior) { |
cparata | 2:a94816b14e3d | 2020 | case LIS2DW12_XYZ: |
cparata | 2:a94816b14e3d | 2021 | *val = LIS2DW12_XYZ; |
cparata | 2:a94816b14e3d | 2022 | break; |
cparata | 2:a94816b14e3d | 2023 | case LIS2DW12_YXZ: |
cparata | 2:a94816b14e3d | 2024 | *val = LIS2DW12_YXZ; |
cparata | 2:a94816b14e3d | 2025 | break; |
cparata | 2:a94816b14e3d | 2026 | case LIS2DW12_XZY: |
cparata | 2:a94816b14e3d | 2027 | *val = LIS2DW12_XZY; |
cparata | 2:a94816b14e3d | 2028 | break; |
cparata | 2:a94816b14e3d | 2029 | case LIS2DW12_ZYX: |
cparata | 2:a94816b14e3d | 2030 | *val = LIS2DW12_ZYX; |
cparata | 2:a94816b14e3d | 2031 | break; |
cparata | 2:a94816b14e3d | 2032 | case LIS2DW12_YZX: |
cparata | 2:a94816b14e3d | 2033 | *val = LIS2DW12_YZX; |
cparata | 2:a94816b14e3d | 2034 | break; |
cparata | 2:a94816b14e3d | 2035 | case LIS2DW12_ZXY: |
cparata | 2:a94816b14e3d | 2036 | *val = LIS2DW12_ZXY; |
cparata | 2:a94816b14e3d | 2037 | break; |
cparata | 2:a94816b14e3d | 2038 | default: |
cparata | 2:a94816b14e3d | 2039 | *val = LIS2DW12_XYZ; |
cparata | 2:a94816b14e3d | 2040 | break; |
cparata | 2:a94816b14e3d | 2041 | } |
cparata | 2:a94816b14e3d | 2042 | return ret; |
cparata | 0:dff8803aace7 | 2043 | } |
cparata | 0:dff8803aace7 | 2044 | |
cparata | 0:dff8803aace7 | 2045 | /** |
cparata | 2:a94816b14e3d | 2046 | * @brief Threshold for tap recognition.[set] |
cparata | 0:dff8803aace7 | 2047 | * |
cparata | 2:a94816b14e3d | 2048 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2049 | * @param val change the values of tap_thsz in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2050 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2051 | * |
cparata | 0:dff8803aace7 | 2052 | */ |
cparata | 0:dff8803aace7 | 2053 | int32_t lis2dw12_tap_threshold_z_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2054 | { |
cparata | 2:a94816b14e3d | 2055 | lis2dw12_tap_ths_z_t reg; |
cparata | 2:a94816b14e3d | 2056 | int32_t ret; |
cparata | 0:dff8803aace7 | 2057 | |
cparata | 2:a94816b14e3d | 2058 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2059 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2060 | reg.tap_thsz = val; |
cparata | 2:a94816b14e3d | 2061 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2062 | } |
cparata | 0:dff8803aace7 | 2063 | |
cparata | 2:a94816b14e3d | 2064 | return ret; |
cparata | 0:dff8803aace7 | 2065 | } |
cparata | 0:dff8803aace7 | 2066 | |
cparata | 0:dff8803aace7 | 2067 | /** |
cparata | 2:a94816b14e3d | 2068 | * @brief Threshold for tap recognition.[get] |
cparata | 0:dff8803aace7 | 2069 | * |
cparata | 2:a94816b14e3d | 2070 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2071 | * @param val change the values of tap_thsz in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2072 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2073 | * |
cparata | 0:dff8803aace7 | 2074 | */ |
cparata | 0:dff8803aace7 | 2075 | int32_t lis2dw12_tap_threshold_z_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2076 | { |
cparata | 2:a94816b14e3d | 2077 | lis2dw12_tap_ths_z_t reg; |
cparata | 2:a94816b14e3d | 2078 | int32_t ret; |
cparata | 0:dff8803aace7 | 2079 | |
cparata | 2:a94816b14e3d | 2080 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2081 | *val = reg.tap_thsz; |
cparata | 0:dff8803aace7 | 2082 | |
cparata | 2:a94816b14e3d | 2083 | return ret; |
cparata | 0:dff8803aace7 | 2084 | } |
cparata | 0:dff8803aace7 | 2085 | |
cparata | 0:dff8803aace7 | 2086 | /** |
cparata | 2:a94816b14e3d | 2087 | * @brief Enable Z direction in tap recognition.[set] |
cparata | 0:dff8803aace7 | 2088 | * |
cparata | 2:a94816b14e3d | 2089 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2090 | * @param val change the values of tap_z_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2091 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2092 | * |
cparata | 0:dff8803aace7 | 2093 | */ |
cparata | 0:dff8803aace7 | 2094 | int32_t lis2dw12_tap_detection_on_z_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2095 | { |
cparata | 2:a94816b14e3d | 2096 | lis2dw12_tap_ths_z_t reg; |
cparata | 2:a94816b14e3d | 2097 | int32_t ret; |
cparata | 0:dff8803aace7 | 2098 | |
cparata | 2:a94816b14e3d | 2099 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2100 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2101 | reg.tap_z_en = val; |
cparata | 2:a94816b14e3d | 2102 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2103 | } |
cparata | 2:a94816b14e3d | 2104 | return ret; |
cparata | 0:dff8803aace7 | 2105 | } |
cparata | 0:dff8803aace7 | 2106 | |
cparata | 0:dff8803aace7 | 2107 | /** |
cparata | 2:a94816b14e3d | 2108 | * @brief Enable Z direction in tap recognition.[get] |
cparata | 0:dff8803aace7 | 2109 | * |
cparata | 2:a94816b14e3d | 2110 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2111 | * @param val change the values of tap_z_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2112 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2113 | * |
cparata | 0:dff8803aace7 | 2114 | */ |
cparata | 0:dff8803aace7 | 2115 | int32_t lis2dw12_tap_detection_on_z_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2116 | { |
cparata | 2:a94816b14e3d | 2117 | lis2dw12_tap_ths_z_t reg; |
cparata | 2:a94816b14e3d | 2118 | int32_t ret; |
cparata | 0:dff8803aace7 | 2119 | |
cparata | 2:a94816b14e3d | 2120 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2121 | *val = reg.tap_z_en; |
cparata | 0:dff8803aace7 | 2122 | |
cparata | 2:a94816b14e3d | 2123 | return ret; |
cparata | 0:dff8803aace7 | 2124 | } |
cparata | 0:dff8803aace7 | 2125 | |
cparata | 0:dff8803aace7 | 2126 | /** |
cparata | 2:a94816b14e3d | 2127 | * @brief Enable Y direction in tap recognition.[set] |
cparata | 0:dff8803aace7 | 2128 | * |
cparata | 2:a94816b14e3d | 2129 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2130 | * @param val change the values of tap_y_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2131 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2132 | * |
cparata | 0:dff8803aace7 | 2133 | */ |
cparata | 0:dff8803aace7 | 2134 | int32_t lis2dw12_tap_detection_on_y_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2135 | { |
cparata | 2:a94816b14e3d | 2136 | lis2dw12_tap_ths_z_t reg; |
cparata | 2:a94816b14e3d | 2137 | int32_t ret; |
cparata | 0:dff8803aace7 | 2138 | |
cparata | 2:a94816b14e3d | 2139 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2140 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2141 | reg.tap_y_en = val; |
cparata | 2:a94816b14e3d | 2142 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2143 | } |
cparata | 2:a94816b14e3d | 2144 | return ret; |
cparata | 0:dff8803aace7 | 2145 | } |
cparata | 0:dff8803aace7 | 2146 | |
cparata | 0:dff8803aace7 | 2147 | /** |
cparata | 2:a94816b14e3d | 2148 | * @brief Enable Y direction in tap recognition.[get] |
cparata | 0:dff8803aace7 | 2149 | * |
cparata | 2:a94816b14e3d | 2150 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2151 | * @param val change the values of tap_y_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2152 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2153 | * |
cparata | 0:dff8803aace7 | 2154 | */ |
cparata | 0:dff8803aace7 | 2155 | int32_t lis2dw12_tap_detection_on_y_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2156 | { |
cparata | 2:a94816b14e3d | 2157 | lis2dw12_tap_ths_z_t reg; |
cparata | 2:a94816b14e3d | 2158 | int32_t ret; |
cparata | 0:dff8803aace7 | 2159 | |
cparata | 2:a94816b14e3d | 2160 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2161 | *val = reg.tap_y_en; |
cparata | 0:dff8803aace7 | 2162 | |
cparata | 2:a94816b14e3d | 2163 | return ret; |
cparata | 0:dff8803aace7 | 2164 | } |
cparata | 0:dff8803aace7 | 2165 | |
cparata | 0:dff8803aace7 | 2166 | /** |
cparata | 2:a94816b14e3d | 2167 | * @brief Enable X direction in tap recognition.[set] |
cparata | 0:dff8803aace7 | 2168 | * |
cparata | 2:a94816b14e3d | 2169 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2170 | * @param val change the values of tap_x_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2171 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2172 | * |
cparata | 0:dff8803aace7 | 2173 | */ |
cparata | 0:dff8803aace7 | 2174 | int32_t lis2dw12_tap_detection_on_x_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2175 | { |
cparata | 2:a94816b14e3d | 2176 | lis2dw12_tap_ths_z_t reg; |
cparata | 2:a94816b14e3d | 2177 | int32_t ret; |
cparata | 0:dff8803aace7 | 2178 | |
cparata | 2:a94816b14e3d | 2179 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2180 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2181 | reg.tap_x_en = val; |
cparata | 2:a94816b14e3d | 2182 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2183 | } |
cparata | 2:a94816b14e3d | 2184 | return ret; |
cparata | 0:dff8803aace7 | 2185 | } |
cparata | 0:dff8803aace7 | 2186 | |
cparata | 0:dff8803aace7 | 2187 | /** |
cparata | 2:a94816b14e3d | 2188 | * @brief Enable X direction in tap recognition.[get] |
cparata | 0:dff8803aace7 | 2189 | * |
cparata | 2:a94816b14e3d | 2190 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2191 | * @param val change the values of tap_x_en in reg TAP_THS_Z |
cparata | 2:a94816b14e3d | 2192 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2193 | * |
cparata | 0:dff8803aace7 | 2194 | */ |
cparata | 0:dff8803aace7 | 2195 | int32_t lis2dw12_tap_detection_on_x_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2196 | { |
cparata | 2:a94816b14e3d | 2197 | lis2dw12_tap_ths_z_t reg; |
cparata | 2:a94816b14e3d | 2198 | int32_t ret; |
cparata | 0:dff8803aace7 | 2199 | |
cparata | 2:a94816b14e3d | 2200 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2201 | *val = reg.tap_x_en; |
cparata | 0:dff8803aace7 | 2202 | |
cparata | 2:a94816b14e3d | 2203 | return ret; |
cparata | 0:dff8803aace7 | 2204 | } |
cparata | 0:dff8803aace7 | 2205 | |
cparata | 0:dff8803aace7 | 2206 | /** |
cparata | 2:a94816b14e3d | 2207 | * @brief Maximum duration is the maximum time of an overthreshold signal |
cparata | 2:a94816b14e3d | 2208 | * detection to be recognized as a tap event. The default value |
cparata | 2:a94816b14e3d | 2209 | * of these bits is 00b which corresponds to 4*ODR_XL time. |
cparata | 2:a94816b14e3d | 2210 | * If the SHOCK[1:0] bits are set to a different value, 1LSB |
cparata | 2:a94816b14e3d | 2211 | * corresponds to 8*ODR_XL time.[set] |
cparata | 0:dff8803aace7 | 2212 | * |
cparata | 2:a94816b14e3d | 2213 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2214 | * @param val change the values of shock in reg INT_DUR |
cparata | 2:a94816b14e3d | 2215 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2216 | * |
cparata | 0:dff8803aace7 | 2217 | */ |
cparata | 0:dff8803aace7 | 2218 | int32_t lis2dw12_tap_shock_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2219 | { |
cparata | 2:a94816b14e3d | 2220 | lis2dw12_int_dur_t reg; |
cparata | 2:a94816b14e3d | 2221 | int32_t ret; |
cparata | 0:dff8803aace7 | 2222 | |
cparata | 2:a94816b14e3d | 2223 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2224 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2225 | reg.shock = val; |
cparata | 2:a94816b14e3d | 2226 | ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2227 | } |
cparata | 0:dff8803aace7 | 2228 | |
cparata | 2:a94816b14e3d | 2229 | return ret; |
cparata | 0:dff8803aace7 | 2230 | } |
cparata | 0:dff8803aace7 | 2231 | |
cparata | 0:dff8803aace7 | 2232 | /** |
cparata | 2:a94816b14e3d | 2233 | * @brief Maximum duration is the maximum time of an overthreshold signal |
cparata | 2:a94816b14e3d | 2234 | * detection to be recognized as a tap event. The default value |
cparata | 2:a94816b14e3d | 2235 | * of these bits is 00b which corresponds to 4*ODR_XL time. |
cparata | 2:a94816b14e3d | 2236 | * If the SHOCK[1:0] bits are set to a different value, 1LSB |
cparata | 2:a94816b14e3d | 2237 | * corresponds to 8*ODR_XL time.[get] |
cparata | 0:dff8803aace7 | 2238 | * |
cparata | 2:a94816b14e3d | 2239 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2240 | * @param val change the values of shock in reg INT_DUR |
cparata | 2:a94816b14e3d | 2241 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2242 | * |
cparata | 0:dff8803aace7 | 2243 | */ |
cparata | 0:dff8803aace7 | 2244 | int32_t lis2dw12_tap_shock_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2245 | { |
cparata | 2:a94816b14e3d | 2246 | lis2dw12_int_dur_t reg; |
cparata | 2:a94816b14e3d | 2247 | int32_t ret; |
cparata | 0:dff8803aace7 | 2248 | |
cparata | 2:a94816b14e3d | 2249 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2250 | *val = reg.shock; |
cparata | 0:dff8803aace7 | 2251 | |
cparata | 2:a94816b14e3d | 2252 | return ret; |
cparata | 0:dff8803aace7 | 2253 | } |
cparata | 0:dff8803aace7 | 2254 | |
cparata | 0:dff8803aace7 | 2255 | /** |
cparata | 2:a94816b14e3d | 2256 | * @brief Quiet time is the time after the first detected tap in which |
cparata | 2:a94816b14e3d | 2257 | * there must not be any overthreshold event. |
cparata | 2:a94816b14e3d | 2258 | * The default value of these bits is 00b which corresponds |
cparata | 2:a94816b14e3d | 2259 | * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different |
cparata | 2:a94816b14e3d | 2260 | * value, 1LSB corresponds to 4*ODR_XL time.[set] |
cparata | 0:dff8803aace7 | 2261 | * |
cparata | 2:a94816b14e3d | 2262 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2263 | * @param val change the values of quiet in reg INT_DUR |
cparata | 2:a94816b14e3d | 2264 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2265 | * |
cparata | 0:dff8803aace7 | 2266 | */ |
cparata | 0:dff8803aace7 | 2267 | int32_t lis2dw12_tap_quiet_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2268 | { |
cparata | 2:a94816b14e3d | 2269 | lis2dw12_int_dur_t reg; |
cparata | 2:a94816b14e3d | 2270 | int32_t ret; |
cparata | 0:dff8803aace7 | 2271 | |
cparata | 2:a94816b14e3d | 2272 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2273 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2274 | reg.quiet = val; |
cparata | 2:a94816b14e3d | 2275 | ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2276 | } |
cparata | 2:a94816b14e3d | 2277 | return ret; |
cparata | 0:dff8803aace7 | 2278 | } |
cparata | 0:dff8803aace7 | 2279 | |
cparata | 0:dff8803aace7 | 2280 | /** |
cparata | 2:a94816b14e3d | 2281 | * @brief Quiet time is the time after the first detected tap in which |
cparata | 2:a94816b14e3d | 2282 | * there must not be any overthreshold event. |
cparata | 2:a94816b14e3d | 2283 | * The default value of these bits is 00b which corresponds |
cparata | 2:a94816b14e3d | 2284 | * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different |
cparata | 2:a94816b14e3d | 2285 | * value, 1LSB corresponds to 4*ODR_XL time.[get] |
cparata | 0:dff8803aace7 | 2286 | * |
cparata | 2:a94816b14e3d | 2287 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2288 | * @param val change the values of quiet in reg INT_DUR |
cparata | 2:a94816b14e3d | 2289 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2290 | * |
cparata | 0:dff8803aace7 | 2291 | */ |
cparata | 0:dff8803aace7 | 2292 | int32_t lis2dw12_tap_quiet_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2293 | { |
cparata | 2:a94816b14e3d | 2294 | lis2dw12_int_dur_t reg; |
cparata | 2:a94816b14e3d | 2295 | int32_t ret; |
cparata | 0:dff8803aace7 | 2296 | |
cparata | 2:a94816b14e3d | 2297 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2298 | *val = reg.quiet; |
cparata | 0:dff8803aace7 | 2299 | |
cparata | 2:a94816b14e3d | 2300 | return ret; |
cparata | 0:dff8803aace7 | 2301 | } |
cparata | 0:dff8803aace7 | 2302 | |
cparata | 0:dff8803aace7 | 2303 | /** |
cparata | 2:a94816b14e3d | 2304 | * @brief When double tap recognition is enabled, this register expresses |
cparata | 2:a94816b14e3d | 2305 | * the maximum time between two consecutive detected taps to |
cparata | 2:a94816b14e3d | 2306 | * determine a double tap event. |
cparata | 2:a94816b14e3d | 2307 | * The default value of these bits is 0000b which corresponds |
cparata | 2:a94816b14e3d | 2308 | * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different |
cparata | 2:a94816b14e3d | 2309 | * value, 1LSB corresponds to 32*ODR_XL time.[set] |
cparata | 0:dff8803aace7 | 2310 | * |
cparata | 2:a94816b14e3d | 2311 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2312 | * @param val change the values of latency in reg INT_DUR |
cparata | 2:a94816b14e3d | 2313 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2314 | * |
cparata | 0:dff8803aace7 | 2315 | */ |
cparata | 0:dff8803aace7 | 2316 | int32_t lis2dw12_tap_dur_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2317 | { |
cparata | 2:a94816b14e3d | 2318 | lis2dw12_int_dur_t reg; |
cparata | 2:a94816b14e3d | 2319 | int32_t ret; |
cparata | 0:dff8803aace7 | 2320 | |
cparata | 2:a94816b14e3d | 2321 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2322 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2323 | reg.latency = val; |
cparata | 2:a94816b14e3d | 2324 | ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2325 | } |
cparata | 2:a94816b14e3d | 2326 | return ret; |
cparata | 0:dff8803aace7 | 2327 | } |
cparata | 0:dff8803aace7 | 2328 | |
cparata | 0:dff8803aace7 | 2329 | /** |
cparata | 2:a94816b14e3d | 2330 | * @brief When double tap recognition is enabled, this register expresses |
cparata | 2:a94816b14e3d | 2331 | * the maximum time between two consecutive detected taps to |
cparata | 2:a94816b14e3d | 2332 | * determine a double tap event. |
cparata | 2:a94816b14e3d | 2333 | * The default value of these bits is 0000b which corresponds |
cparata | 2:a94816b14e3d | 2334 | * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different |
cparata | 2:a94816b14e3d | 2335 | * value, 1LSB corresponds to 32*ODR_XL time.[get] |
cparata | 0:dff8803aace7 | 2336 | * |
cparata | 2:a94816b14e3d | 2337 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2338 | * @param val change the values of latency in reg INT_DUR |
cparata | 2:a94816b14e3d | 2339 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2340 | * |
cparata | 0:dff8803aace7 | 2341 | */ |
cparata | 0:dff8803aace7 | 2342 | int32_t lis2dw12_tap_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2343 | { |
cparata | 2:a94816b14e3d | 2344 | lis2dw12_int_dur_t reg; |
cparata | 2:a94816b14e3d | 2345 | int32_t ret; |
cparata | 0:dff8803aace7 | 2346 | |
cparata | 2:a94816b14e3d | 2347 | ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2348 | *val = reg.latency; |
cparata | 0:dff8803aace7 | 2349 | |
cparata | 2:a94816b14e3d | 2350 | return ret; |
cparata | 0:dff8803aace7 | 2351 | } |
cparata | 0:dff8803aace7 | 2352 | |
cparata | 0:dff8803aace7 | 2353 | /** |
cparata | 2:a94816b14e3d | 2354 | * @brief Single/double-tap event enable.[set] |
cparata | 0:dff8803aace7 | 2355 | * |
cparata | 2:a94816b14e3d | 2356 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2357 | * @param val change the values of single_double_tap in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 2358 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2359 | * |
cparata | 0:dff8803aace7 | 2360 | */ |
cparata | 0:dff8803aace7 | 2361 | int32_t lis2dw12_tap_mode_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2362 | lis2dw12_single_double_tap_t val) |
cparata | 0:dff8803aace7 | 2363 | { |
cparata | 2:a94816b14e3d | 2364 | lis2dw12_wake_up_ths_t reg; |
cparata | 2:a94816b14e3d | 2365 | int32_t ret; |
cparata | 0:dff8803aace7 | 2366 | |
cparata | 2:a94816b14e3d | 2367 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2368 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2369 | reg.single_double_tap = (uint8_t) val; |
cparata | 2:a94816b14e3d | 2370 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2371 | } |
cparata | 2:a94816b14e3d | 2372 | return ret; |
cparata | 0:dff8803aace7 | 2373 | } |
cparata | 0:dff8803aace7 | 2374 | |
cparata | 0:dff8803aace7 | 2375 | /** |
cparata | 2:a94816b14e3d | 2376 | * @brief Single/double-tap event enable.[get] |
cparata | 0:dff8803aace7 | 2377 | * |
cparata | 2:a94816b14e3d | 2378 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2379 | * @param val Get the values of single_double_tap in reg WAKE_UP_THS |
cparata | 2:a94816b14e3d | 2380 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2381 | * |
cparata | 0:dff8803aace7 | 2382 | */ |
cparata | 0:dff8803aace7 | 2383 | int32_t lis2dw12_tap_mode_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2384 | lis2dw12_single_double_tap_t *val) |
cparata | 0:dff8803aace7 | 2385 | { |
cparata | 2:a94816b14e3d | 2386 | lis2dw12_wake_up_ths_t reg; |
cparata | 2:a94816b14e3d | 2387 | int32_t ret; |
cparata | 2:a94816b14e3d | 2388 | |
cparata | 2:a94816b14e3d | 2389 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 2390 | |
cparata | 2:a94816b14e3d | 2391 | switch (reg.single_double_tap) { |
cparata | 2:a94816b14e3d | 2392 | case LIS2DW12_ONLY_SINGLE: |
cparata | 2:a94816b14e3d | 2393 | *val = LIS2DW12_ONLY_SINGLE; |
cparata | 2:a94816b14e3d | 2394 | break; |
cparata | 2:a94816b14e3d | 2395 | case LIS2DW12_BOTH_SINGLE_DOUBLE: |
cparata | 2:a94816b14e3d | 2396 | *val = LIS2DW12_BOTH_SINGLE_DOUBLE; |
cparata | 2:a94816b14e3d | 2397 | break; |
cparata | 2:a94816b14e3d | 2398 | default: |
cparata | 2:a94816b14e3d | 2399 | *val = LIS2DW12_ONLY_SINGLE; |
cparata | 2:a94816b14e3d | 2400 | break; |
cparata | 2:a94816b14e3d | 2401 | } |
cparata | 0:dff8803aace7 | 2402 | |
cparata | 2:a94816b14e3d | 2403 | return ret; |
cparata | 0:dff8803aace7 | 2404 | } |
cparata | 0:dff8803aace7 | 2405 | |
cparata | 0:dff8803aace7 | 2406 | /** |
cparata | 2:a94816b14e3d | 2407 | * @brief Read the tap / double tap source register.[get] |
cparata | 0:dff8803aace7 | 2408 | * |
cparata | 2:a94816b14e3d | 2409 | * @param ctx read / write interface definitions |
cparata | 0:dff8803aace7 | 2410 | * @param lis2dw12_tap_src: union of registers from TAP_SRC to |
cparata | 2:a94816b14e3d | 2411 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2412 | * |
cparata | 0:dff8803aace7 | 2413 | */ |
cparata | 0:dff8803aace7 | 2414 | int32_t lis2dw12_tap_src_get(lis2dw12_ctx_t *ctx, lis2dw12_tap_src_t *val) |
cparata | 0:dff8803aace7 | 2415 | { |
cparata | 2:a94816b14e3d | 2416 | int32_t ret; |
cparata | 2:a94816b14e3d | 2417 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_SRC, (uint8_t*) val, 1); |
cparata | 2:a94816b14e3d | 2418 | return ret; |
cparata | 0:dff8803aace7 | 2419 | } |
cparata | 2:a94816b14e3d | 2420 | |
cparata | 0:dff8803aace7 | 2421 | /** |
cparata | 0:dff8803aace7 | 2422 | * @} |
cparata | 2:a94816b14e3d | 2423 | * |
cparata | 0:dff8803aace7 | 2424 | */ |
cparata | 0:dff8803aace7 | 2425 | |
cparata | 0:dff8803aace7 | 2426 | /** |
cparata | 2:a94816b14e3d | 2427 | * @defgroup LIS2DW12_Six_Position_Detection(6D/4D) |
cparata | 2:a94816b14e3d | 2428 | * @brief This section groups all the functions concerning six |
cparata | 2:a94816b14e3d | 2429 | * position detection (6D). |
cparata | 0:dff8803aace7 | 2430 | * @{ |
cparata | 2:a94816b14e3d | 2431 | * |
cparata | 0:dff8803aace7 | 2432 | */ |
cparata | 0:dff8803aace7 | 2433 | |
cparata | 0:dff8803aace7 | 2434 | /** |
cparata | 2:a94816b14e3d | 2435 | * @brief Threshold for 4D/6D function.[set] |
cparata | 0:dff8803aace7 | 2436 | * |
cparata | 2:a94816b14e3d | 2437 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2438 | * @param val change the values of 6d_ths in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 2439 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2440 | * |
cparata | 0:dff8803aace7 | 2441 | */ |
cparata | 0:dff8803aace7 | 2442 | int32_t lis2dw12_6d_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2443 | { |
cparata | 2:a94816b14e3d | 2444 | lis2dw12_tap_ths_x_t reg; |
cparata | 2:a94816b14e3d | 2445 | int32_t ret; |
cparata | 0:dff8803aace7 | 2446 | |
cparata | 2:a94816b14e3d | 2447 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2448 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2449 | reg._6d_ths = val; |
cparata | 2:a94816b14e3d | 2450 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2451 | } |
cparata | 2:a94816b14e3d | 2452 | return ret; |
cparata | 0:dff8803aace7 | 2453 | } |
cparata | 0:dff8803aace7 | 2454 | |
cparata | 0:dff8803aace7 | 2455 | /** |
cparata | 2:a94816b14e3d | 2456 | * @brief Threshold for 4D/6D function.[get] |
cparata | 0:dff8803aace7 | 2457 | * |
cparata | 2:a94816b14e3d | 2458 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2459 | * @param val change the values of 6d_ths in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 2460 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2461 | * |
cparata | 0:dff8803aace7 | 2462 | */ |
cparata | 0:dff8803aace7 | 2463 | int32_t lis2dw12_6d_threshold_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2464 | { |
cparata | 2:a94816b14e3d | 2465 | lis2dw12_tap_ths_x_t reg; |
cparata | 2:a94816b14e3d | 2466 | int32_t ret; |
cparata | 0:dff8803aace7 | 2467 | |
cparata | 2:a94816b14e3d | 2468 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2469 | *val = reg._6d_ths; |
cparata | 0:dff8803aace7 | 2470 | |
cparata | 2:a94816b14e3d | 2471 | return ret; |
cparata | 0:dff8803aace7 | 2472 | } |
cparata | 0:dff8803aace7 | 2473 | |
cparata | 0:dff8803aace7 | 2474 | /** |
cparata | 2:a94816b14e3d | 2475 | * @brief 4D orientation detection enable.[set] |
cparata | 0:dff8803aace7 | 2476 | * |
cparata | 2:a94816b14e3d | 2477 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2478 | * @param val change the values of 4d_en in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 2479 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2480 | * |
cparata | 0:dff8803aace7 | 2481 | */ |
cparata | 0:dff8803aace7 | 2482 | int32_t lis2dw12_4d_mode_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2483 | { |
cparata | 2:a94816b14e3d | 2484 | lis2dw12_tap_ths_x_t reg; |
cparata | 2:a94816b14e3d | 2485 | int32_t ret; |
cparata | 0:dff8803aace7 | 2486 | |
cparata | 2:a94816b14e3d | 2487 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2488 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2489 | reg._4d_en = val; |
cparata | 2:a94816b14e3d | 2490 | ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2491 | } |
cparata | 0:dff8803aace7 | 2492 | |
cparata | 2:a94816b14e3d | 2493 | return ret; |
cparata | 0:dff8803aace7 | 2494 | } |
cparata | 0:dff8803aace7 | 2495 | |
cparata | 0:dff8803aace7 | 2496 | /** |
cparata | 2:a94816b14e3d | 2497 | * @brief 4D orientation detection enable.[get] |
cparata | 0:dff8803aace7 | 2498 | * |
cparata | 2:a94816b14e3d | 2499 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2500 | * @param val change the values of 4d_en in reg TAP_THS_X |
cparata | 2:a94816b14e3d | 2501 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2502 | * |
cparata | 0:dff8803aace7 | 2503 | */ |
cparata | 0:dff8803aace7 | 2504 | int32_t lis2dw12_4d_mode_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2505 | { |
cparata | 2:a94816b14e3d | 2506 | lis2dw12_tap_ths_x_t reg; |
cparata | 2:a94816b14e3d | 2507 | int32_t ret; |
cparata | 0:dff8803aace7 | 2508 | |
cparata | 2:a94816b14e3d | 2509 | ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2510 | *val = reg._4d_en; |
cparata | 0:dff8803aace7 | 2511 | |
cparata | 2:a94816b14e3d | 2512 | return ret; |
cparata | 0:dff8803aace7 | 2513 | } |
cparata | 0:dff8803aace7 | 2514 | |
cparata | 0:dff8803aace7 | 2515 | /** |
cparata | 2:a94816b14e3d | 2516 | * @brief Read the 6D tap source register.[get] |
cparata | 0:dff8803aace7 | 2517 | * |
cparata | 2:a94816b14e3d | 2518 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2519 | * @param val union of registers from SIXD_SRC |
cparata | 2:a94816b14e3d | 2520 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2521 | * |
cparata | 0:dff8803aace7 | 2522 | */ |
cparata | 0:dff8803aace7 | 2523 | int32_t lis2dw12_6d_src_get(lis2dw12_ctx_t *ctx, lis2dw12_sixd_src_t *val) |
cparata | 0:dff8803aace7 | 2524 | { |
cparata | 2:a94816b14e3d | 2525 | int32_t ret; |
cparata | 2:a94816b14e3d | 2526 | ret = lis2dw12_read_reg(ctx, LIS2DW12_SIXD_SRC, (uint8_t*) val, 1); |
cparata | 2:a94816b14e3d | 2527 | return ret; |
cparata | 0:dff8803aace7 | 2528 | } |
cparata | 0:dff8803aace7 | 2529 | /** |
cparata | 2:a94816b14e3d | 2530 | * @brief Data sent to 6D interrupt function.[set] |
cparata | 0:dff8803aace7 | 2531 | * |
cparata | 2:a94816b14e3d | 2532 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2533 | * @param val change the values of lpass_on6d in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 2534 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2535 | * |
cparata | 0:dff8803aace7 | 2536 | */ |
cparata | 0:dff8803aace7 | 2537 | int32_t lis2dw12_6d_feed_data_set(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2538 | lis2dw12_lpass_on6d_t val) |
cparata | 0:dff8803aace7 | 2539 | { |
cparata | 2:a94816b14e3d | 2540 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 2541 | int32_t ret; |
cparata | 0:dff8803aace7 | 2542 | |
cparata | 2:a94816b14e3d | 2543 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2544 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2545 | reg.lpass_on6d = (uint8_t) val; |
cparata | 2:a94816b14e3d | 2546 | ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2547 | } |
cparata | 2:a94816b14e3d | 2548 | return ret; |
cparata | 0:dff8803aace7 | 2549 | } |
cparata | 0:dff8803aace7 | 2550 | |
cparata | 0:dff8803aace7 | 2551 | /** |
cparata | 2:a94816b14e3d | 2552 | * @brief Data sent to 6D interrupt function.[get] |
cparata | 0:dff8803aace7 | 2553 | * |
cparata | 2:a94816b14e3d | 2554 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2555 | * @param val Get the values of lpass_on6d in reg CTRL_REG7 |
cparata | 2:a94816b14e3d | 2556 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2557 | * |
cparata | 0:dff8803aace7 | 2558 | */ |
cparata | 0:dff8803aace7 | 2559 | int32_t lis2dw12_6d_feed_data_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2560 | lis2dw12_lpass_on6d_t *val) |
cparata | 0:dff8803aace7 | 2561 | { |
cparata | 2:a94816b14e3d | 2562 | lis2dw12_ctrl_reg7_t reg; |
cparata | 2:a94816b14e3d | 2563 | int32_t ret; |
cparata | 2:a94816b14e3d | 2564 | |
cparata | 2:a94816b14e3d | 2565 | ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 2566 | |
cparata | 2:a94816b14e3d | 2567 | switch (reg.lpass_on6d) { |
cparata | 2:a94816b14e3d | 2568 | case LIS2DW12_ODR_DIV_2_FEED: |
cparata | 2:a94816b14e3d | 2569 | *val = LIS2DW12_ODR_DIV_2_FEED; |
cparata | 2:a94816b14e3d | 2570 | break; |
cparata | 2:a94816b14e3d | 2571 | case LIS2DW12_LPF2_FEED: |
cparata | 2:a94816b14e3d | 2572 | *val = LIS2DW12_LPF2_FEED; |
cparata | 2:a94816b14e3d | 2573 | break; |
cparata | 2:a94816b14e3d | 2574 | default: |
cparata | 2:a94816b14e3d | 2575 | *val = LIS2DW12_ODR_DIV_2_FEED; |
cparata | 2:a94816b14e3d | 2576 | break; |
cparata | 2:a94816b14e3d | 2577 | } |
cparata | 2:a94816b14e3d | 2578 | return ret; |
cparata | 0:dff8803aace7 | 2579 | } |
cparata | 0:dff8803aace7 | 2580 | |
cparata | 0:dff8803aace7 | 2581 | /** |
cparata | 0:dff8803aace7 | 2582 | * @} |
cparata | 2:a94816b14e3d | 2583 | * |
cparata | 0:dff8803aace7 | 2584 | */ |
cparata | 0:dff8803aace7 | 2585 | |
cparata | 0:dff8803aace7 | 2586 | /** |
cparata | 2:a94816b14e3d | 2587 | * @defgroup LIS2DW12_Free_Fall |
cparata | 2:a94816b14e3d | 2588 | * @brief This section group all the functions concerning |
cparata | 2:a94816b14e3d | 2589 | * the free fall detection. |
cparata | 0:dff8803aace7 | 2590 | * @{ |
cparata | 2:a94816b14e3d | 2591 | * |
cparata | 0:dff8803aace7 | 2592 | */ |
cparata | 0:dff8803aace7 | 2593 | |
cparata | 0:dff8803aace7 | 2594 | /** |
cparata | 2:a94816b14e3d | 2595 | * @brief Wake up duration event(1LSb = 1 / ODR).[set] |
cparata | 0:dff8803aace7 | 2596 | * |
cparata | 2:a94816b14e3d | 2597 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2598 | * @param val change the values of ff_dur in reg |
cparata | 2:a94816b14e3d | 2599 | * WAKE_UP_DUR /F REE_FALL |
cparata | 2:a94816b14e3d | 2600 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2601 | * |
cparata | 0:dff8803aace7 | 2602 | */ |
cparata | 0:dff8803aace7 | 2603 | int32_t lis2dw12_ff_dur_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2604 | { |
cparata | 2:a94816b14e3d | 2605 | lis2dw12_wake_up_dur_t wake_up_dur; |
cparata | 2:a94816b14e3d | 2606 | lis2dw12_free_fall_t free_fall; |
cparata | 2:a94816b14e3d | 2607 | int32_t ret; |
cparata | 0:dff8803aace7 | 2608 | |
cparata | 2:a94816b14e3d | 2609 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); |
cparata | 2:a94816b14e3d | 2610 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2611 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1); |
cparata | 2:a94816b14e3d | 2612 | } |
cparata | 2:a94816b14e3d | 2613 | if(ret == 0) { |
cparata | 2:a94816b14e3d | 2614 | wake_up_dur.ff_dur = ( (uint8_t) val & 0x20U) >> 5; |
cparata | 2:a94816b14e3d | 2615 | free_fall.ff_dur = (uint8_t) val & 0x1FU; |
cparata | 2:a94816b14e3d | 2616 | ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); |
cparata | 2:a94816b14e3d | 2617 | } |
cparata | 2:a94816b14e3d | 2618 | if(ret == 0) { |
cparata | 2:a94816b14e3d | 2619 | ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1); |
cparata | 2:a94816b14e3d | 2620 | } |
cparata | 2:a94816b14e3d | 2621 | |
cparata | 2:a94816b14e3d | 2622 | return ret; |
cparata | 0:dff8803aace7 | 2623 | } |
cparata | 0:dff8803aace7 | 2624 | |
cparata | 0:dff8803aace7 | 2625 | /** |
cparata | 2:a94816b14e3d | 2626 | * @brief Wake up duration event(1LSb = 1 / ODR).[get] |
cparata | 0:dff8803aace7 | 2627 | * |
cparata | 2:a94816b14e3d | 2628 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2629 | * @param val change the values of ff_dur in |
cparata | 0:dff8803aace7 | 2630 | * reg WAKE_UP_DUR /F REE_FALL |
cparata | 2:a94816b14e3d | 2631 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2632 | * |
cparata | 0:dff8803aace7 | 2633 | */ |
cparata | 0:dff8803aace7 | 2634 | int32_t lis2dw12_ff_dur_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2635 | { |
cparata | 2:a94816b14e3d | 2636 | lis2dw12_wake_up_dur_t wake_up_dur; |
cparata | 2:a94816b14e3d | 2637 | lis2dw12_free_fall_t free_fall; |
cparata | 2:a94816b14e3d | 2638 | int32_t ret; |
cparata | 2:a94816b14e3d | 2639 | |
cparata | 2:a94816b14e3d | 2640 | ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1); |
cparata | 2:a94816b14e3d | 2641 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2642 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) &free_fall, 1); |
cparata | 2:a94816b14e3d | 2643 | *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; |
cparata | 2:a94816b14e3d | 2644 | } |
cparata | 2:a94816b14e3d | 2645 | return ret; |
cparata | 0:dff8803aace7 | 2646 | } |
cparata | 0:dff8803aace7 | 2647 | |
cparata | 0:dff8803aace7 | 2648 | /** |
cparata | 2:a94816b14e3d | 2649 | * @brief Free fall threshold setting.[set] |
cparata | 0:dff8803aace7 | 2650 | * |
cparata | 2:a94816b14e3d | 2651 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2652 | * @param val change the values of ff_ths in reg FREE_FALL |
cparata | 2:a94816b14e3d | 2653 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2654 | * |
cparata | 0:dff8803aace7 | 2655 | */ |
cparata | 0:dff8803aace7 | 2656 | int32_t lis2dw12_ff_threshold_set(lis2dw12_ctx_t *ctx, lis2dw12_ff_ths_t val) |
cparata | 0:dff8803aace7 | 2657 | { |
cparata | 2:a94816b14e3d | 2658 | lis2dw12_free_fall_t reg; |
cparata | 2:a94816b14e3d | 2659 | int32_t ret; |
cparata | 0:dff8803aace7 | 2660 | |
cparata | 2:a94816b14e3d | 2661 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2662 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2663 | reg.ff_ths = (uint8_t) val; |
cparata | 2:a94816b14e3d | 2664 | ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2665 | } |
cparata | 0:dff8803aace7 | 2666 | |
cparata | 2:a94816b14e3d | 2667 | return ret; |
cparata | 0:dff8803aace7 | 2668 | } |
cparata | 0:dff8803aace7 | 2669 | |
cparata | 0:dff8803aace7 | 2670 | /** |
cparata | 2:a94816b14e3d | 2671 | * @brief Free fall threshold setting.[get] |
cparata | 0:dff8803aace7 | 2672 | * |
cparata | 2:a94816b14e3d | 2673 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2674 | * @param val Get the values of ff_ths in reg FREE_FALL |
cparata | 2:a94816b14e3d | 2675 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2676 | * |
cparata | 0:dff8803aace7 | 2677 | */ |
cparata | 0:dff8803aace7 | 2678 | int32_t lis2dw12_ff_threshold_get(lis2dw12_ctx_t *ctx, |
cparata | 0:dff8803aace7 | 2679 | lis2dw12_ff_ths_t *val) |
cparata | 0:dff8803aace7 | 2680 | { |
cparata | 2:a94816b14e3d | 2681 | lis2dw12_free_fall_t reg; |
cparata | 2:a94816b14e3d | 2682 | int32_t ret; |
cparata | 2:a94816b14e3d | 2683 | |
cparata | 2:a94816b14e3d | 2684 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 2685 | |
cparata | 2:a94816b14e3d | 2686 | switch (reg.ff_ths) { |
cparata | 2:a94816b14e3d | 2687 | case LIS2DW12_FF_TSH_5LSb_FS2g: |
cparata | 2:a94816b14e3d | 2688 | *val = LIS2DW12_FF_TSH_5LSb_FS2g; |
cparata | 2:a94816b14e3d | 2689 | break; |
cparata | 2:a94816b14e3d | 2690 | case LIS2DW12_FF_TSH_7LSb_FS2g: |
cparata | 2:a94816b14e3d | 2691 | *val = LIS2DW12_FF_TSH_7LSb_FS2g; |
cparata | 2:a94816b14e3d | 2692 | break; |
cparata | 2:a94816b14e3d | 2693 | case LIS2DW12_FF_TSH_8LSb_FS2g: |
cparata | 2:a94816b14e3d | 2694 | *val = LIS2DW12_FF_TSH_8LSb_FS2g; |
cparata | 2:a94816b14e3d | 2695 | break; |
cparata | 2:a94816b14e3d | 2696 | case LIS2DW12_FF_TSH_10LSb_FS2g: |
cparata | 2:a94816b14e3d | 2697 | *val = LIS2DW12_FF_TSH_10LSb_FS2g; |
cparata | 2:a94816b14e3d | 2698 | break; |
cparata | 2:a94816b14e3d | 2699 | case LIS2DW12_FF_TSH_11LSb_FS2g: |
cparata | 2:a94816b14e3d | 2700 | *val = LIS2DW12_FF_TSH_11LSb_FS2g; |
cparata | 2:a94816b14e3d | 2701 | break; |
cparata | 2:a94816b14e3d | 2702 | case LIS2DW12_FF_TSH_13LSb_FS2g: |
cparata | 2:a94816b14e3d | 2703 | *val = LIS2DW12_FF_TSH_13LSb_FS2g; |
cparata | 2:a94816b14e3d | 2704 | break; |
cparata | 2:a94816b14e3d | 2705 | case LIS2DW12_FF_TSH_15LSb_FS2g: |
cparata | 2:a94816b14e3d | 2706 | *val = LIS2DW12_FF_TSH_15LSb_FS2g; |
cparata | 2:a94816b14e3d | 2707 | break; |
cparata | 2:a94816b14e3d | 2708 | case LIS2DW12_FF_TSH_16LSb_FS2g: |
cparata | 2:a94816b14e3d | 2709 | *val = LIS2DW12_FF_TSH_16LSb_FS2g; |
cparata | 2:a94816b14e3d | 2710 | break; |
cparata | 2:a94816b14e3d | 2711 | default: |
cparata | 2:a94816b14e3d | 2712 | *val = LIS2DW12_FF_TSH_5LSb_FS2g; |
cparata | 2:a94816b14e3d | 2713 | break; |
cparata | 2:a94816b14e3d | 2714 | } |
cparata | 2:a94816b14e3d | 2715 | return ret; |
cparata | 0:dff8803aace7 | 2716 | } |
cparata | 0:dff8803aace7 | 2717 | |
cparata | 0:dff8803aace7 | 2718 | /** |
cparata | 0:dff8803aace7 | 2719 | * @} |
cparata | 2:a94816b14e3d | 2720 | * |
cparata | 0:dff8803aace7 | 2721 | */ |
cparata | 0:dff8803aace7 | 2722 | |
cparata | 0:dff8803aace7 | 2723 | /** |
cparata | 2:a94816b14e3d | 2724 | * @defgroup LIS2DW12_Fifo |
cparata | 2:a94816b14e3d | 2725 | * @brief This section group all the functions concerning the fifo usage |
cparata | 0:dff8803aace7 | 2726 | * @{ |
cparata | 2:a94816b14e3d | 2727 | * |
cparata | 0:dff8803aace7 | 2728 | */ |
cparata | 0:dff8803aace7 | 2729 | |
cparata | 0:dff8803aace7 | 2730 | /** |
cparata | 2:a94816b14e3d | 2731 | * @brief FIFO watermark level selection.[set] |
cparata | 0:dff8803aace7 | 2732 | * |
cparata | 2:a94816b14e3d | 2733 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2734 | * @param val change the values of fth in reg FIFO_CTRL |
cparata | 2:a94816b14e3d | 2735 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2736 | * |
cparata | 0:dff8803aace7 | 2737 | */ |
cparata | 0:dff8803aace7 | 2738 | int32_t lis2dw12_fifo_watermark_set(lis2dw12_ctx_t *ctx, uint8_t val) |
cparata | 0:dff8803aace7 | 2739 | { |
cparata | 2:a94816b14e3d | 2740 | lis2dw12_fifo_ctrl_t reg; |
cparata | 2:a94816b14e3d | 2741 | int32_t ret; |
cparata | 0:dff8803aace7 | 2742 | |
cparata | 2:a94816b14e3d | 2743 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2744 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2745 | reg.fth = val; |
cparata | 2:a94816b14e3d | 2746 | ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2747 | } |
cparata | 0:dff8803aace7 | 2748 | |
cparata | 2:a94816b14e3d | 2749 | return ret; |
cparata | 0:dff8803aace7 | 2750 | } |
cparata | 0:dff8803aace7 | 2751 | |
cparata | 0:dff8803aace7 | 2752 | /** |
cparata | 2:a94816b14e3d | 2753 | * @brief FIFO watermark level selection.[get] |
cparata | 0:dff8803aace7 | 2754 | * |
cparata | 2:a94816b14e3d | 2755 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2756 | * @param val change the values of fth in reg FIFO_CTRL |
cparata | 2:a94816b14e3d | 2757 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2758 | * |
cparata | 0:dff8803aace7 | 2759 | */ |
cparata | 0:dff8803aace7 | 2760 | int32_t lis2dw12_fifo_watermark_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2761 | { |
cparata | 2:a94816b14e3d | 2762 | lis2dw12_fifo_ctrl_t reg; |
cparata | 2:a94816b14e3d | 2763 | int32_t ret; |
cparata | 0:dff8803aace7 | 2764 | |
cparata | 2:a94816b14e3d | 2765 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2766 | *val = reg.fth; |
cparata | 0:dff8803aace7 | 2767 | |
cparata | 2:a94816b14e3d | 2768 | return ret; |
cparata | 0:dff8803aace7 | 2769 | } |
cparata | 0:dff8803aace7 | 2770 | |
cparata | 0:dff8803aace7 | 2771 | /** |
cparata | 2:a94816b14e3d | 2772 | * @brief FIFO mode selection.[set] |
cparata | 0:dff8803aace7 | 2773 | * |
cparata | 2:a94816b14e3d | 2774 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2775 | * @param val change the values of fmode in reg FIFO_CTRL |
cparata | 2:a94816b14e3d | 2776 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2777 | * |
cparata | 0:dff8803aace7 | 2778 | */ |
cparata | 0:dff8803aace7 | 2779 | int32_t lis2dw12_fifo_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_fmode_t val) |
cparata | 0:dff8803aace7 | 2780 | { |
cparata | 2:a94816b14e3d | 2781 | lis2dw12_fifo_ctrl_t reg; |
cparata | 2:a94816b14e3d | 2782 | int32_t ret; |
cparata | 0:dff8803aace7 | 2783 | |
cparata | 2:a94816b14e3d | 2784 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2785 | if (ret == 0) { |
cparata | 2:a94816b14e3d | 2786 | reg.fmode = (uint8_t) val; |
cparata | 2:a94816b14e3d | 2787 | ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2788 | } |
cparata | 2:a94816b14e3d | 2789 | return ret; |
cparata | 0:dff8803aace7 | 2790 | } |
cparata | 0:dff8803aace7 | 2791 | |
cparata | 0:dff8803aace7 | 2792 | /** |
cparata | 2:a94816b14e3d | 2793 | * @brief FIFO mode selection.[get] |
cparata | 0:dff8803aace7 | 2794 | * |
cparata | 2:a94816b14e3d | 2795 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2796 | * @param val Get the values of fmode in reg FIFO_CTRL |
cparata | 2:a94816b14e3d | 2797 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2798 | * |
cparata | 0:dff8803aace7 | 2799 | */ |
cparata | 0:dff8803aace7 | 2800 | int32_t lis2dw12_fifo_mode_get(lis2dw12_ctx_t *ctx, lis2dw12_fmode_t *val) |
cparata | 0:dff8803aace7 | 2801 | { |
cparata | 2:a94816b14e3d | 2802 | lis2dw12_fifo_ctrl_t reg; |
cparata | 2:a94816b14e3d | 2803 | int32_t ret; |
cparata | 2:a94816b14e3d | 2804 | |
cparata | 2:a94816b14e3d | 2805 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL,(uint8_t*) ®, 1); |
cparata | 0:dff8803aace7 | 2806 | |
cparata | 2:a94816b14e3d | 2807 | switch (reg.fmode) { |
cparata | 2:a94816b14e3d | 2808 | case LIS2DW12_BYPASS_MODE: |
cparata | 2:a94816b14e3d | 2809 | *val = LIS2DW12_BYPASS_MODE; |
cparata | 2:a94816b14e3d | 2810 | break; |
cparata | 2:a94816b14e3d | 2811 | case LIS2DW12_FIFO_MODE: |
cparata | 2:a94816b14e3d | 2812 | *val = LIS2DW12_FIFO_MODE; |
cparata | 2:a94816b14e3d | 2813 | break; |
cparata | 2:a94816b14e3d | 2814 | case LIS2DW12_STREAM_TO_FIFO_MODE: |
cparata | 2:a94816b14e3d | 2815 | *val = LIS2DW12_STREAM_TO_FIFO_MODE; |
cparata | 2:a94816b14e3d | 2816 | break; |
cparata | 2:a94816b14e3d | 2817 | case LIS2DW12_BYPASS_TO_STREAM_MODE: |
cparata | 2:a94816b14e3d | 2818 | *val = LIS2DW12_BYPASS_TO_STREAM_MODE; |
cparata | 2:a94816b14e3d | 2819 | break; |
cparata | 2:a94816b14e3d | 2820 | case LIS2DW12_STREAM_MODE: |
cparata | 2:a94816b14e3d | 2821 | *val = LIS2DW12_STREAM_MODE; |
cparata | 2:a94816b14e3d | 2822 | break; |
cparata | 2:a94816b14e3d | 2823 | default: |
cparata | 2:a94816b14e3d | 2824 | *val = LIS2DW12_BYPASS_MODE; |
cparata | 2:a94816b14e3d | 2825 | break; |
cparata | 2:a94816b14e3d | 2826 | } |
cparata | 2:a94816b14e3d | 2827 | return ret; |
cparata | 0:dff8803aace7 | 2828 | } |
cparata | 0:dff8803aace7 | 2829 | |
cparata | 0:dff8803aace7 | 2830 | /** |
cparata | 2:a94816b14e3d | 2831 | * @brief Number of unread samples stored in FIFO.[get] |
cparata | 0:dff8803aace7 | 2832 | * |
cparata | 2:a94816b14e3d | 2833 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2834 | * @param val change the values of diff in reg FIFO_SAMPLES |
cparata | 2:a94816b14e3d | 2835 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2836 | * |
cparata | 0:dff8803aace7 | 2837 | */ |
cparata | 0:dff8803aace7 | 2838 | int32_t lis2dw12_fifo_data_level_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2839 | { |
cparata | 2:a94816b14e3d | 2840 | lis2dw12_fifo_samples_t reg; |
cparata | 2:a94816b14e3d | 2841 | int32_t ret; |
cparata | 0:dff8803aace7 | 2842 | |
cparata | 2:a94816b14e3d | 2843 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2844 | *val = reg.diff; |
cparata | 0:dff8803aace7 | 2845 | |
cparata | 2:a94816b14e3d | 2846 | return ret; |
cparata | 0:dff8803aace7 | 2847 | } |
cparata | 0:dff8803aace7 | 2848 | /** |
cparata | 2:a94816b14e3d | 2849 | * @brief FIFO overrun status.[get] |
cparata | 0:dff8803aace7 | 2850 | * |
cparata | 2:a94816b14e3d | 2851 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2852 | * @param val change the values of fifo_ovr in reg FIFO_SAMPLES |
cparata | 2:a94816b14e3d | 2853 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2854 | * |
cparata | 0:dff8803aace7 | 2855 | */ |
cparata | 0:dff8803aace7 | 2856 | int32_t lis2dw12_fifo_ovr_flag_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2857 | { |
cparata | 2:a94816b14e3d | 2858 | lis2dw12_fifo_samples_t reg; |
cparata | 2:a94816b14e3d | 2859 | int32_t ret; |
cparata | 0:dff8803aace7 | 2860 | |
cparata | 2:a94816b14e3d | 2861 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2862 | *val = reg.fifo_ovr; |
cparata | 0:dff8803aace7 | 2863 | |
cparata | 2:a94816b14e3d | 2864 | return ret; |
cparata | 0:dff8803aace7 | 2865 | } |
cparata | 0:dff8803aace7 | 2866 | /** |
cparata | 2:a94816b14e3d | 2867 | * @brief FIFO threshold status flag.[get] |
cparata | 0:dff8803aace7 | 2868 | * |
cparata | 2:a94816b14e3d | 2869 | * @param ctx read / write interface definitions |
cparata | 2:a94816b14e3d | 2870 | * @param val change the values of fifo_fth in reg FIFO_SAMPLES |
cparata | 2:a94816b14e3d | 2871 | * @retval interface status (MANDATORY: return 0 -> no Error) |
cparata | 0:dff8803aace7 | 2872 | * |
cparata | 0:dff8803aace7 | 2873 | */ |
cparata | 0:dff8803aace7 | 2874 | int32_t lis2dw12_fifo_wtm_flag_get(lis2dw12_ctx_t *ctx, uint8_t *val) |
cparata | 0:dff8803aace7 | 2875 | { |
cparata | 2:a94816b14e3d | 2876 | lis2dw12_fifo_samples_t reg; |
cparata | 2:a94816b14e3d | 2877 | int32_t ret; |
cparata | 0:dff8803aace7 | 2878 | |
cparata | 2:a94816b14e3d | 2879 | ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES,(uint8_t*) ®, 1); |
cparata | 2:a94816b14e3d | 2880 | *val = reg.fifo_fth; |
cparata | 0:dff8803aace7 | 2881 | |
cparata | 2:a94816b14e3d | 2882 | return ret; |
cparata | 0:dff8803aace7 | 2883 | } |
cparata | 0:dff8803aace7 | 2884 | /** |
cparata | 0:dff8803aace7 | 2885 | * @} |
cparata | 2:a94816b14e3d | 2886 | * |
cparata | 0:dff8803aace7 | 2887 | */ |
cparata | 0:dff8803aace7 | 2888 | |
cparata | 0:dff8803aace7 | 2889 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |