LIS2DW12 - 3-axis MEMS ultra low power accelerometer

ST » Code » LIS2DW12

3-axis MEMS ultra low power accelerometer

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3

lis2dw12_reg.c@0:dff8803aace7, 2018-11-19 (annotated)

Committer:: cparata
Date:: Mon Nov 19 13:20:07 2018 +0000
Revision:: 0:dff8803aace7
Child:: 1:94e908301953

First release of LIS2DW12 driver

Who changed what in which revision?

User	Revision	Line number	New contents of line
cparata	0:dff8803aace7	1	/*
cparata	0:dff8803aace7	2	******************************************************************************
cparata	0:dff8803aace7	3	* @file lis2dw12_reg.c
cparata	0:dff8803aace7	4	* @author MEMS Software Solution Team
cparata	0:dff8803aace7	5	* @date 25-January-2018
cparata	0:dff8803aace7	6	* @brief LIS2DW12 driver file
cparata	0:dff8803aace7	7	******************************************************************************
cparata	0:dff8803aace7	8	* @attention
cparata	0:dff8803aace7	9	*
cparata	0:dff8803aace7	10	* <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
cparata	0:dff8803aace7	11	*
cparata	0:dff8803aace7	12	* Redistribution and use in source and binary forms, with or without modification,
cparata	0:dff8803aace7	13	* are permitted provided that the following conditions are met:
cparata	0:dff8803aace7	14	* 1. Redistributions of source code must retain the above copyright notice,
cparata	0:dff8803aace7	15	* this list of conditions and the following disclaimer.
cparata	0:dff8803aace7	16	* 2. Redistributions in binary form must reproduce the above copyright notice,
cparata	0:dff8803aace7	17	* this list of conditions and the following disclaimer in the documentation
cparata	0:dff8803aace7	18	* and/or other materials provided with the distribution.
cparata	0:dff8803aace7	19	* 3. Neither the name of STMicroelectronics nor the names of its contributors
cparata	0:dff8803aace7	20	* may be used to endorse or promote products derived from this software
cparata	0:dff8803aace7	21	* without specific prior written permission.
cparata	0:dff8803aace7	22	*
cparata	0:dff8803aace7	23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
cparata	0:dff8803aace7	24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
cparata	0:dff8803aace7	25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
cparata	0:dff8803aace7	26	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
cparata	0:dff8803aace7	27	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
cparata	0:dff8803aace7	28	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
cparata	0:dff8803aace7	29	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
cparata	0:dff8803aace7	30	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
cparata	0:dff8803aace7	31	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
cparata	0:dff8803aace7	32	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
cparata	0:dff8803aace7	33	*
cparata	0:dff8803aace7	34	*/
cparata	0:dff8803aace7	35
cparata	0:dff8803aace7	36	#include "lis2dw12_reg.h"
cparata	0:dff8803aace7	37
cparata	0:dff8803aace7	38	/**
cparata	0:dff8803aace7	39	* @addtogroup lis2dw12
cparata	0:dff8803aace7	40	* @brief This file provides a set of functions needed to drive the
cparata	0:dff8803aace7	41	* lis2dw12 enanced inertial module.
cparata	0:dff8803aace7	42	* @{
cparata	0:dff8803aace7	43	*/
cparata	0:dff8803aace7	44
cparata	0:dff8803aace7	45	/**
cparata	0:dff8803aace7	46	* @addtogroup interfaces_functions
cparata	0:dff8803aace7	47	* @brief This section provide a set of functions used to read and write
cparata	0:dff8803aace7	48	* a generic register of the device.
cparata	0:dff8803aace7	49	* @{
cparata	0:dff8803aace7	50	*/
cparata	0:dff8803aace7	51
cparata	0:dff8803aace7	52	/**
cparata	0:dff8803aace7	53	* @brief Read generic device register
cparata	0:dff8803aace7	54	*
cparata	0:dff8803aace7	55	* @param lis2dw12_ctx_t* ctx: read / write interface definitions
cparata	0:dff8803aace7	56	* @param uint8_t reg: register to read
cparata	0:dff8803aace7	57	* @param uint8_t* data: pointer to buffer that store the data read
cparata	0:dff8803aace7	58	* @param uint16_t len: number of consecutive register to read
cparata	0:dff8803aace7	59	*
cparata	0:dff8803aace7	60	*/
cparata	0:dff8803aace7	61	int32_t lis2dw12_read_reg(lis2dw12_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:dff8803aace7	62	uint16_t len)
cparata	0:dff8803aace7	63	{
cparata	0:dff8803aace7	64	return ctx->read_reg(ctx->handle, reg, data, len);
cparata	0:dff8803aace7	65	}
cparata	0:dff8803aace7	66
cparata	0:dff8803aace7	67	/**
cparata	0:dff8803aace7	68	* @brief Write generic device register
cparata	0:dff8803aace7	69	*
cparata	0:dff8803aace7	70	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	71	* @param uint8_t reg: register to write
cparata	0:dff8803aace7	72	* @param uint8_t* data: pointer to data to write in register reg
cparata	0:dff8803aace7	73	* @param uint16_t len: number of consecutive register to write
cparata	0:dff8803aace7	74	*
cparata	0:dff8803aace7	75	*/
cparata	0:dff8803aace7	76	int32_t lis2dw12_write_reg(lis2dw12_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:dff8803aace7	77	uint16_t len)
cparata	0:dff8803aace7	78	{
cparata	0:dff8803aace7	79	return ctx->write_reg(ctx->handle, reg, data, len);
cparata	0:dff8803aace7	80	}
cparata	0:dff8803aace7	81
cparata	0:dff8803aace7	82	/**
cparata	0:dff8803aace7	83	* @}
cparata	0:dff8803aace7	84	*/
cparata	0:dff8803aace7	85
cparata	0:dff8803aace7	86	/**
cparata	0:dff8803aace7	87	* @addtogroup data_generation_c
cparata	0:dff8803aace7	88	* @brief This section groups all the functions concerning data generation
cparata	0:dff8803aace7	89	* @{
cparata	0:dff8803aace7	90	*/
cparata	0:dff8803aace7	91
cparata	0:dff8803aace7	92	/**
cparata	0:dff8803aace7	93	* @brief power_mode: [set] Select accelerometer operating modes.
cparata	0:dff8803aace7	94	*
cparata	0:dff8803aace7	95	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	96	* @param lis2dw12_mode_t: change the values of mode / lp_mode in reg CTRL1
cparata	0:dff8803aace7	97	* and low_noise in reg CTRL6
cparata	0:dff8803aace7	98	*
cparata	0:dff8803aace7	99	*/
cparata	0:dff8803aace7	100	int32_t lis2dw12_power_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_mode_t val)
cparata	0:dff8803aace7	101	{
cparata	0:dff8803aace7	102	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	103	int32_t mm_error;
cparata	0:dff8803aace7	104
cparata	0:dff8803aace7	105	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, &reg.byte, 1);
cparata	0:dff8803aace7	106	reg.ctrl1.mode = ( val & 0x0C ) >> 2;
cparata	0:dff8803aace7	107	reg.ctrl1.lp_mode = val & 0x03 ;
cparata	0:dff8803aace7	108	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, &reg.byte, 1);
cparata	0:dff8803aace7	109
cparata	0:dff8803aace7	110	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	111	reg.ctrl6.low_noise = ( val & 0x10 ) >> 4;
cparata	0:dff8803aace7	112	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	113
cparata	0:dff8803aace7	114	return mm_error;
cparata	0:dff8803aace7	115	}
cparata	0:dff8803aace7	116
cparata	0:dff8803aace7	117	/**
cparata	0:dff8803aace7	118	* @brief power_mode: [get] Select accelerometer operating modes.
cparata	0:dff8803aace7	119	*
cparata	0:dff8803aace7	120	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	121	* @param lis2dw12_mode_t: change the values of mode / lp_mode in reg CTRL1
cparata	0:dff8803aace7	122	* and low_noise in reg CTRL6
cparata	0:dff8803aace7	123	*
cparata	0:dff8803aace7	124	*/
cparata	0:dff8803aace7	125	int32_t lis2dw12_power_mode_get(lis2dw12_ctx_t ctx, lis2dw12_mode_t val)
cparata	0:dff8803aace7	126	{
cparata	0:dff8803aace7	127	lis2dw12_reg_t reg[2];
cparata	0:dff8803aace7	128	int32_t mm_error;
cparata	0:dff8803aace7	129
cparata	0:dff8803aace7	130	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, &reg[0].byte, 1);
cparata	0:dff8803aace7	131	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, &reg[1].byte, 1);
cparata	0:dff8803aace7	132	*val = (lis2dw12_mode_t) ((reg[1].ctrl6.low_noise << 4) +
cparata	0:dff8803aace7	133	(reg[0].ctrl1.mode << 2) + reg[0].ctrl1.lp_mode);
cparata	0:dff8803aace7	134
cparata	0:dff8803aace7	135	return mm_error;
cparata	0:dff8803aace7	136	}
cparata	0:dff8803aace7	137
cparata	0:dff8803aace7	138	/**
cparata	0:dff8803aace7	139	* @brief data_rate: [set] Accelerometer data rate selection.
cparata	0:dff8803aace7	140	*
cparata	0:dff8803aace7	141	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	142	* @param lis2dw12_odr_t: change the values of odr in reg CTRL1
cparata	0:dff8803aace7	143	*
cparata	0:dff8803aace7	144	*/
cparata	0:dff8803aace7	145	int32_t lis2dw12_data_rate_set(lis2dw12_ctx_t *ctx, lis2dw12_odr_t val)
cparata	0:dff8803aace7	146	{
cparata	0:dff8803aace7	147	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	148	int32_t mm_error;
cparata	0:dff8803aace7	149
cparata	0:dff8803aace7	150	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, &reg.byte, 1);
cparata	0:dff8803aace7	151	reg.ctrl1.odr = val;
cparata	0:dff8803aace7	152	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, &reg.byte, 1);
cparata	0:dff8803aace7	153
cparata	0:dff8803aace7	154	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	155	reg.ctrl3.slp_mode = ( val & 0x30 ) >> 4;
cparata	0:dff8803aace7	156	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	157
cparata	0:dff8803aace7	158	return mm_error;
cparata	0:dff8803aace7	159	}
cparata	0:dff8803aace7	160
cparata	0:dff8803aace7	161	/**
cparata	0:dff8803aace7	162	* @brief data_rate: [get] Accelerometer data rate selection.
cparata	0:dff8803aace7	163	*
cparata	0:dff8803aace7	164	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	165	* @param lis2dw12_odr_t: Get the values of odr in reg CTRL1
cparata	0:dff8803aace7	166	*
cparata	0:dff8803aace7	167	*/
cparata	0:dff8803aace7	168	int32_t lis2dw12_data_rate_get(lis2dw12_ctx_t ctx, lis2dw12_odr_t val)
cparata	0:dff8803aace7	169	{
cparata	0:dff8803aace7	170	lis2dw12_reg_t reg[2];
cparata	0:dff8803aace7	171	int32_t mm_error;
cparata	0:dff8803aace7	172
cparata	0:dff8803aace7	173	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, &reg[0].byte, 1);
cparata	0:dff8803aace7	174	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg[1].byte, 1);
cparata	0:dff8803aace7	175	*val = (lis2dw12_odr_t) ((reg[1].ctrl3.slp_mode << 4) + reg[0].ctrl1.odr);
cparata	0:dff8803aace7	176
cparata	0:dff8803aace7	177	return mm_error;
cparata	0:dff8803aace7	178	}
cparata	0:dff8803aace7	179
cparata	0:dff8803aace7	180	/**
cparata	0:dff8803aace7	181	* @brief block_data_update: [set] Blockdataupdate.
cparata	0:dff8803aace7	182	*
cparata	0:dff8803aace7	183	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	184	* @param uint8_t val: change the values of bdu in reg CTRL2
cparata	0:dff8803aace7	185	*
cparata	0:dff8803aace7	186	*/
cparata	0:dff8803aace7	187	int32_t lis2dw12_block_data_update_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	188	{
cparata	0:dff8803aace7	189	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	190	int32_t mm_error;
cparata	0:dff8803aace7	191
cparata	0:dff8803aace7	192	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	193	reg.ctrl2.bdu = val;
cparata	0:dff8803aace7	194	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	195
cparata	0:dff8803aace7	196	return mm_error;
cparata	0:dff8803aace7	197	}
cparata	0:dff8803aace7	198
cparata	0:dff8803aace7	199	/**
cparata	0:dff8803aace7	200	* @brief block_data_update: [get] Blockdataupdate.
cparata	0:dff8803aace7	201	*
cparata	0:dff8803aace7	202	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	203	* @param uint8_t: change the values of bdu in reg CTRL2
cparata	0:dff8803aace7	204	*
cparata	0:dff8803aace7	205	*/
cparata	0:dff8803aace7	206	int32_t lis2dw12_block_data_update_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	207	{
cparata	0:dff8803aace7	208	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	209	int32_t mm_error;
cparata	0:dff8803aace7	210
cparata	0:dff8803aace7	211	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	212	*val = reg.ctrl2.bdu;
cparata	0:dff8803aace7	213
cparata	0:dff8803aace7	214	return mm_error;
cparata	0:dff8803aace7	215	}
cparata	0:dff8803aace7	216
cparata	0:dff8803aace7	217	/**
cparata	0:dff8803aace7	218	* @brief full_scale: [set] Accelerometer full-scale selection.
cparata	0:dff8803aace7	219	*
cparata	0:dff8803aace7	220	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	221	* @param lis2dw12_fs_t: change the values of fs in reg CTRL6
cparata	0:dff8803aace7	222	*
cparata	0:dff8803aace7	223	*/
cparata	0:dff8803aace7	224	int32_t lis2dw12_full_scale_set(lis2dw12_ctx_t *ctx, lis2dw12_fs_t val)
cparata	0:dff8803aace7	225	{
cparata	0:dff8803aace7	226	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	227	int32_t mm_error;
cparata	0:dff8803aace7	228
cparata	0:dff8803aace7	229	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	230	reg.ctrl6.fs = val;
cparata	0:dff8803aace7	231	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	232
cparata	0:dff8803aace7	233	return mm_error;
cparata	0:dff8803aace7	234	}
cparata	0:dff8803aace7	235
cparata	0:dff8803aace7	236	/**
cparata	0:dff8803aace7	237	* @brief full_scale: [get] Accelerometer full-scale selection.
cparata	0:dff8803aace7	238	*
cparata	0:dff8803aace7	239	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	240	* @param lis2dw12_fs_t: Get the values of fs in reg CTRL6
cparata	0:dff8803aace7	241	*
cparata	0:dff8803aace7	242	*/
cparata	0:dff8803aace7	243	int32_t lis2dw12_full_scale_get(lis2dw12_ctx_t ctx, lis2dw12_fs_t val)
cparata	0:dff8803aace7	244	{
cparata	0:dff8803aace7	245	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	246	int32_t mm_error;
cparata	0:dff8803aace7	247
cparata	0:dff8803aace7	248	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	249	*val = (lis2dw12_fs_t) reg.ctrl6.fs;
cparata	0:dff8803aace7	250
cparata	0:dff8803aace7	251	return mm_error;
cparata	0:dff8803aace7	252	}
cparata	0:dff8803aace7	253
cparata	0:dff8803aace7	254	/**
cparata	0:dff8803aace7	255	* @brief status_reg: [get] The STATUS_REG register of the device.
cparata	0:dff8803aace7	256	*
cparata	0:dff8803aace7	257	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	258	* @param lis2dw12_: union of registers from STATUS to
cparata	0:dff8803aace7	259	*
cparata	0:dff8803aace7	260	*/
cparata	0:dff8803aace7	261	int32_t lis2dw12_status_reg_get(lis2dw12_ctx_t ctx, lis2dw12_status_t val)
cparata	0:dff8803aace7	262	{
cparata	0:dff8803aace7	263	return lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t*) val, 1);
cparata	0:dff8803aace7	264	}
cparata	0:dff8803aace7	265	/**
cparata	0:dff8803aace7	266	* @brief flag_data_ready: [get] Accelerometer new data available.
cparata	0:dff8803aace7	267	*
cparata	0:dff8803aace7	268	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	269	* @param uint8_t: change the values of drdy in reg STATUS
cparata	0:dff8803aace7	270	*
cparata	0:dff8803aace7	271	*/
cparata	0:dff8803aace7	272	int32_t lis2dw12_flag_data_ready_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	273	{
cparata	0:dff8803aace7	274	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	275	int32_t mm_error;
cparata	0:dff8803aace7	276
cparata	0:dff8803aace7	277	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, &reg.byte, 1);
cparata	0:dff8803aace7	278	*val = reg.status.drdy;
cparata	0:dff8803aace7	279
cparata	0:dff8803aace7	280	return mm_error;
cparata	0:dff8803aace7	281	}
cparata	0:dff8803aace7	282	/**
cparata	0:dff8803aace7	283	* @brief all_sources: [get] Read all the interrupt/status flag of
cparata	0:dff8803aace7	284	* the device.
cparata	0:dff8803aace7	285	*
cparata	0:dff8803aace7	286	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	287	* @param lis2dw12_all_sources: registers STATUS_DUP, WAKE_UP_SRC,
cparata	0:dff8803aace7	288	* TAP_SRC, SIXD_SRC, ALL_INT_SRC
cparata	0:dff8803aace7	289	*
cparata	0:dff8803aace7	290	*/
cparata	0:dff8803aace7	291	int32_t lis2dw12_all_sources_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	292	lis2dw12_all_sources_t *val)
cparata	0:dff8803aace7	293	{
cparata	0:dff8803aace7	294	return lis2dw12_read_reg(ctx, LIS2DW12_STATUS_DUP, (uint8_t*) val, 5);
cparata	0:dff8803aace7	295	}
cparata	0:dff8803aace7	296	/**
cparata	0:dff8803aace7	297	* @brief usr_offset_x: [set] Accelerometer X-axis user offset correction
cparata	0:dff8803aace7	298	* expressed in two’s complement, weight
cparata	0:dff8803aace7	299	* depends on bit USR_OFF_W. The value must be
cparata	0:dff8803aace7	300	* in the range [-127 127].
cparata	0:dff8803aace7	301	*
cparata	0:dff8803aace7	302	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	303	* @param uint8_t * : buffer that contains data to write
cparata	0:dff8803aace7	304	*
cparata	0:dff8803aace7	305	*/
cparata	0:dff8803aace7	306	int32_t lis2dw12_usr_offset_x_set(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	307	{
cparata	0:dff8803aace7	308	return lis2dw12_write_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
cparata	0:dff8803aace7	309	}
cparata	0:dff8803aace7	310
cparata	0:dff8803aace7	311	/**
cparata	0:dff8803aace7	312	* @brief usr_offset_x: [get] Accelerometer X-axis user offset
cparata	0:dff8803aace7	313	* correction expressed in two’s complement,
cparata	0:dff8803aace7	314	* weight depends on bit USR_OFF_W.
cparata	0:dff8803aace7	315	* The value must be in the range [-127 127].
cparata	0:dff8803aace7	316	*
cparata	0:dff8803aace7	317	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	318	* @param uint8_t * : buffer that stores data read
cparata	0:dff8803aace7	319	*
cparata	0:dff8803aace7	320	*/
cparata	0:dff8803aace7	321	int32_t lis2dw12_usr_offset_x_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	322	{
cparata	0:dff8803aace7	323	return lis2dw12_read_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
cparata	0:dff8803aace7	324	}
cparata	0:dff8803aace7	325	/**
cparata	0:dff8803aace7	326	* @brief usr_offset_y: [set] Accelerometer Y-axis user offset
cparata	0:dff8803aace7	327	* correction expressed in two’s complement,
cparata	0:dff8803aace7	328	* weight depends on bit USR_OFF_W.
cparata	0:dff8803aace7	329	* The value must be in the range [-127 127].
cparata	0:dff8803aace7	330	*
cparata	0:dff8803aace7	331	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	332	* @param uint8_t * : buffer that contains data to write
cparata	0:dff8803aace7	333	*
cparata	0:dff8803aace7	334	*/
cparata	0:dff8803aace7	335	int32_t lis2dw12_usr_offset_y_set(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	336	{
cparata	0:dff8803aace7	337	return lis2dw12_write_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
cparata	0:dff8803aace7	338	}
cparata	0:dff8803aace7	339
cparata	0:dff8803aace7	340	/**
cparata	0:dff8803aace7	341	* @brief usr_offset_y: [get] Accelerometer Y-axis user offset
cparata	0:dff8803aace7	342	* correction expressed in two’s complement,
cparata	0:dff8803aace7	343	* weight depends on bit USR_OFF_W.
cparata	0:dff8803aace7	344	* The value must be in the range [-127 127].
cparata	0:dff8803aace7	345	*
cparata	0:dff8803aace7	346	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	347	* @param uint8_t * : buffer that stores data read
cparata	0:dff8803aace7	348	*
cparata	0:dff8803aace7	349	*/
cparata	0:dff8803aace7	350	int32_t lis2dw12_usr_offset_y_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	351	{
cparata	0:dff8803aace7	352	return lis2dw12_read_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
cparata	0:dff8803aace7	353	}
cparata	0:dff8803aace7	354	/**
cparata	0:dff8803aace7	355	* @brief usr_offset_z: [set] Accelerometer Z-axis user offset
cparata	0:dff8803aace7	356	* correction expressed in two’s complement,
cparata	0:dff8803aace7	357	* weight depends on bit USR_OFF_W.
cparata	0:dff8803aace7	358	* The value must be in the range [-127 127].
cparata	0:dff8803aace7	359	*
cparata	0:dff8803aace7	360	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	361	* @param uint8_t * : buffer that contains data to write
cparata	0:dff8803aace7	362	*
cparata	0:dff8803aace7	363	*/
cparata	0:dff8803aace7	364	int32_t lis2dw12_usr_offset_z_set(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	365	{
cparata	0:dff8803aace7	366	return lis2dw12_write_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
cparata	0:dff8803aace7	367	}
cparata	0:dff8803aace7	368
cparata	0:dff8803aace7	369	/**
cparata	0:dff8803aace7	370	* @brief usr_offset_z: [get] Accelerometer Z-axis user offset
cparata	0:dff8803aace7	371	* correction expressed in two’s complement,
cparata	0:dff8803aace7	372	* weight depends on bit USR_OFF_W.
cparata	0:dff8803aace7	373	* The value must be in the range [-127 127].
cparata	0:dff8803aace7	374	*
cparata	0:dff8803aace7	375	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	376	* @param uint8_t * : buffer that stores data read
cparata	0:dff8803aace7	377	*
cparata	0:dff8803aace7	378	*/
cparata	0:dff8803aace7	379	int32_t lis2dw12_usr_offset_z_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	380	{
cparata	0:dff8803aace7	381	return lis2dw12_read_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
cparata	0:dff8803aace7	382	}
cparata	0:dff8803aace7	383	/**
cparata	0:dff8803aace7	384	* @brief offset_weight: [set] Weight of XL user offset bits of
cparata	0:dff8803aace7	385	* registers X_OFS_USR, Y_OFS_USR, Z_OFS_USR.
cparata	0:dff8803aace7	386	*
cparata	0:dff8803aace7	387	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	388	* @param lis2dw12_usr_off_w_t: change the values of usr_off_w in
cparata	0:dff8803aace7	389	* reg CTRL_REG7
cparata	0:dff8803aace7	390	*
cparata	0:dff8803aace7	391	*/
cparata	0:dff8803aace7	392	int32_t lis2dw12_offset_weight_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	393	lis2dw12_usr_off_w_t val)
cparata	0:dff8803aace7	394	{
cparata	0:dff8803aace7	395	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	396	int32_t mm_error;
cparata	0:dff8803aace7	397
cparata	0:dff8803aace7	398	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	399	reg.ctrl_reg7.usr_off_w = val;
cparata	0:dff8803aace7	400	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	401
cparata	0:dff8803aace7	402	return mm_error;
cparata	0:dff8803aace7	403	}
cparata	0:dff8803aace7	404
cparata	0:dff8803aace7	405	/**
cparata	0:dff8803aace7	406	* @brief offset_weight: [get] Weight of XL user offset bits of
cparata	0:dff8803aace7	407	* registers X_OFS_USR, Y_OFS_USR, Z_OFS_USR.
cparata	0:dff8803aace7	408	*
cparata	0:dff8803aace7	409	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	410	* @param lis2dw12_usr_off_w_t: Get the values of usr_off_w in reg CTRL_REG7
cparata	0:dff8803aace7	411	*
cparata	0:dff8803aace7	412	*/
cparata	0:dff8803aace7	413	int32_t lis2dw12_offset_weight_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	414	lis2dw12_usr_off_w_t *val)
cparata	0:dff8803aace7	415	{
cparata	0:dff8803aace7	416	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	417	int32_t mm_error;
cparata	0:dff8803aace7	418
cparata	0:dff8803aace7	419	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	420	*val = (lis2dw12_usr_off_w_t) reg.ctrl_reg7.usr_off_w;
cparata	0:dff8803aace7	421
cparata	0:dff8803aace7	422	return mm_error;
cparata	0:dff8803aace7	423	}
cparata	0:dff8803aace7	424
cparata	0:dff8803aace7	425	/**
cparata	0:dff8803aace7	426	* @}
cparata	0:dff8803aace7	427	*/
cparata	0:dff8803aace7	428
cparata	0:dff8803aace7	429	/**
cparata	0:dff8803aace7	430	* @addtogroup Dataoutput
cparata	0:dff8803aace7	431	* @brief This section groups all the data output functions.
cparata	0:dff8803aace7	432	* @{
cparata	0:dff8803aace7	433	*/
cparata	0:dff8803aace7	434
cparata	0:dff8803aace7	435	/**
cparata	0:dff8803aace7	436	* @brief temperature_raw: [get] Temperature data output register (r).
cparata	0:dff8803aace7	437	* L and H registers together express a
cparata	0:dff8803aace7	438	* 16-bit word in two’s complement.
cparata	0:dff8803aace7	439	*
cparata	0:dff8803aace7	440	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	441	* @param uint8_t * : buffer that stores data read
cparata	0:dff8803aace7	442	*
cparata	0:dff8803aace7	443	*/
cparata	0:dff8803aace7	444	int32_t lis2dw12_temperature_raw_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	445	{
cparata	0:dff8803aace7	446	return lis2dw12_read_reg(ctx, LIS2DW12_OUT_T_L, buff, 2);
cparata	0:dff8803aace7	447	}
cparata	0:dff8803aace7	448
cparata	0:dff8803aace7	449	/**
cparata	0:dff8803aace7	450	* @brief acceleration_raw: [get] Linear acceleration output register.
cparata	0:dff8803aace7	451	* The value is expressed as a 16-bit word
cparata	0:dff8803aace7	452	* in two’s complement.
cparata	0:dff8803aace7	453	*
cparata	0:dff8803aace7	454	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	455	* @param uint8_t * : buffer that stores data read
cparata	0:dff8803aace7	456	*
cparata	0:dff8803aace7	457	*/
cparata	0:dff8803aace7	458	int32_t lis2dw12_acceleration_raw_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	459	{
cparata	0:dff8803aace7	460	return lis2dw12_read_reg(ctx, LIS2DW12_OUT_X_L, buff, 6);
cparata	0:dff8803aace7	461	}
cparata	0:dff8803aace7	462
cparata	0:dff8803aace7	463	/**
cparata	0:dff8803aace7	464	* @}
cparata	0:dff8803aace7	465	*/
cparata	0:dff8803aace7	466
cparata	0:dff8803aace7	467	/**
cparata	0:dff8803aace7	468	* @addtogroup common
cparata	0:dff8803aace7	469	* @brief This section groups common usefull functions.
cparata	0:dff8803aace7	470	* @{
cparata	0:dff8803aace7	471	*/
cparata	0:dff8803aace7	472
cparata	0:dff8803aace7	473	/**
cparata	0:dff8803aace7	474	* @brief device_id: [get] DeviceWhoamI.
cparata	0:dff8803aace7	475	*
cparata	0:dff8803aace7	476	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	477	* @param uint8_t * : buffer that stores data read
cparata	0:dff8803aace7	478	*
cparata	0:dff8803aace7	479	*/
cparata	0:dff8803aace7	480	int32_t lis2dw12_device_id_get(lis2dw12_ctx_t ctx, uint8_t buff)
cparata	0:dff8803aace7	481	{
cparata	0:dff8803aace7	482	return lis2dw12_read_reg(ctx, LIS2DW12_WHO_AM_I, buff, 1);
cparata	0:dff8803aace7	483	}
cparata	0:dff8803aace7	484
cparata	0:dff8803aace7	485	/**
cparata	0:dff8803aace7	486	* @brief auto_increment: [set] Register address automatically incremented
cparata	0:dff8803aace7	487	* during multiple byte access with a
cparata	0:dff8803aace7	488	* serial interface.
cparata	0:dff8803aace7	489	*
cparata	0:dff8803aace7	490	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	491	* @param uint8_t val: change the values of if_add_inc in reg CTRL2
cparata	0:dff8803aace7	492	*
cparata	0:dff8803aace7	493	*/
cparata	0:dff8803aace7	494	int32_t lis2dw12_auto_increment_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	495	{
cparata	0:dff8803aace7	496	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	497	int32_t mm_error;
cparata	0:dff8803aace7	498
cparata	0:dff8803aace7	499	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	500	reg.ctrl2.if_add_inc = val;
cparata	0:dff8803aace7	501	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	502
cparata	0:dff8803aace7	503	return mm_error;
cparata	0:dff8803aace7	504	}
cparata	0:dff8803aace7	505
cparata	0:dff8803aace7	506	/**
cparata	0:dff8803aace7	507	* @brief auto_increment: [get] Register address automatically
cparata	0:dff8803aace7	508	* incremented during multiple byte access
cparata	0:dff8803aace7	509	* with a serial interface.
cparata	0:dff8803aace7	510	*
cparata	0:dff8803aace7	511	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	512	* @param uint8_t: change the values of if_add_inc in reg CTRL2
cparata	0:dff8803aace7	513	*
cparata	0:dff8803aace7	514	*/
cparata	0:dff8803aace7	515	int32_t lis2dw12_auto_increment_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	516	{
cparata	0:dff8803aace7	517	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	518	int32_t mm_error;
cparata	0:dff8803aace7	519
cparata	0:dff8803aace7	520	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	521	*val = reg.ctrl2.if_add_inc;
cparata	0:dff8803aace7	522
cparata	0:dff8803aace7	523	return mm_error;
cparata	0:dff8803aace7	524	}
cparata	0:dff8803aace7	525
cparata	0:dff8803aace7	526	/**
cparata	0:dff8803aace7	527	* @brief reset: [set] Software reset. Restore the default values in
cparata	0:dff8803aace7	528	* user registers.
cparata	0:dff8803aace7	529	*
cparata	0:dff8803aace7	530	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	531	* @param uint8_t val: change the values of soft_reset in reg CTRL2
cparata	0:dff8803aace7	532	*
cparata	0:dff8803aace7	533	*/
cparata	0:dff8803aace7	534	int32_t lis2dw12_reset_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	535	{
cparata	0:dff8803aace7	536	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	537	int32_t mm_error;
cparata	0:dff8803aace7	538
cparata	0:dff8803aace7	539	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	540	reg.ctrl2.soft_reset = val;
cparata	0:dff8803aace7	541	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	542
cparata	0:dff8803aace7	543	return mm_error;
cparata	0:dff8803aace7	544	}
cparata	0:dff8803aace7	545
cparata	0:dff8803aace7	546	/**
cparata	0:dff8803aace7	547	* @brief reset: [get] Software reset. Restore the default values in
cparata	0:dff8803aace7	548	* user registers.
cparata	0:dff8803aace7	549	*
cparata	0:dff8803aace7	550	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	551	* @param uint8_t: change the values of soft_reset in reg CTRL2
cparata	0:dff8803aace7	552	*
cparata	0:dff8803aace7	553	*/
cparata	0:dff8803aace7	554	int32_t lis2dw12_reset_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	555	{
cparata	0:dff8803aace7	556	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	557	int32_t mm_error;
cparata	0:dff8803aace7	558
cparata	0:dff8803aace7	559	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	560	*val = reg.ctrl2.soft_reset;
cparata	0:dff8803aace7	561
cparata	0:dff8803aace7	562	return mm_error;
cparata	0:dff8803aace7	563	}
cparata	0:dff8803aace7	564
cparata	0:dff8803aace7	565	/**
cparata	0:dff8803aace7	566	* @brief boot: [set] Reboot memory content. Reload the calibration
cparata	0:dff8803aace7	567	* parameters.
cparata	0:dff8803aace7	568	*
cparata	0:dff8803aace7	569	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	570	* @param uint8_t val: change the values of boot in reg CTRL2
cparata	0:dff8803aace7	571	*
cparata	0:dff8803aace7	572	*/
cparata	0:dff8803aace7	573	int32_t lis2dw12_boot_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	574	{
cparata	0:dff8803aace7	575	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	576	int32_t mm_error;
cparata	0:dff8803aace7	577
cparata	0:dff8803aace7	578	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	579	reg.ctrl2.boot = val;
cparata	0:dff8803aace7	580	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	581
cparata	0:dff8803aace7	582	return mm_error;
cparata	0:dff8803aace7	583	}
cparata	0:dff8803aace7	584
cparata	0:dff8803aace7	585	/**
cparata	0:dff8803aace7	586	* @brief boot: [get] Reboot memory content. Reload the calibration
cparata	0:dff8803aace7	587	* parameters.
cparata	0:dff8803aace7	588	*
cparata	0:dff8803aace7	589	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	590	* @param uint8_t: change the values of boot in reg CTRL2
cparata	0:dff8803aace7	591	*
cparata	0:dff8803aace7	592	*/
cparata	0:dff8803aace7	593	int32_t lis2dw12_boot_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	594	{
cparata	0:dff8803aace7	595	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	596	int32_t mm_error;
cparata	0:dff8803aace7	597
cparata	0:dff8803aace7	598	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	599	*val = reg.ctrl2.boot;
cparata	0:dff8803aace7	600
cparata	0:dff8803aace7	601	return mm_error;
cparata	0:dff8803aace7	602	}
cparata	0:dff8803aace7	603
cparata	0:dff8803aace7	604	/**
cparata	0:dff8803aace7	605	* @brief self_test: [set] Sensor self-test enable.
cparata	0:dff8803aace7	606	*
cparata	0:dff8803aace7	607	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	608	* @param lis2dw12_st_t: change the values of st in reg CTRL3
cparata	0:dff8803aace7	609	*
cparata	0:dff8803aace7	610	*/
cparata	0:dff8803aace7	611	int32_t lis2dw12_self_test_set(lis2dw12_ctx_t *ctx, lis2dw12_st_t val)
cparata	0:dff8803aace7	612	{
cparata	0:dff8803aace7	613	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	614	int32_t mm_error;
cparata	0:dff8803aace7	615
cparata	0:dff8803aace7	616	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	617	reg.ctrl3.st = val;
cparata	0:dff8803aace7	618	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	619
cparata	0:dff8803aace7	620	return mm_error;
cparata	0:dff8803aace7	621	}
cparata	0:dff8803aace7	622
cparata	0:dff8803aace7	623	/**
cparata	0:dff8803aace7	624	* @brief self_test: [get] Sensor self-test enable.
cparata	0:dff8803aace7	625	*
cparata	0:dff8803aace7	626	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	627	* @param lis2dw12_st_t: Get the values of st in reg CTRL3
cparata	0:dff8803aace7	628	*
cparata	0:dff8803aace7	629	*/
cparata	0:dff8803aace7	630	int32_t lis2dw12_self_test_get(lis2dw12_ctx_t ctx, lis2dw12_st_t val)
cparata	0:dff8803aace7	631	{
cparata	0:dff8803aace7	632	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	633	int32_t mm_error;
cparata	0:dff8803aace7	634
cparata	0:dff8803aace7	635	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	636	*val = (lis2dw12_st_t) reg.ctrl3.st;
cparata	0:dff8803aace7	637
cparata	0:dff8803aace7	638	return mm_error;
cparata	0:dff8803aace7	639	}
cparata	0:dff8803aace7	640
cparata	0:dff8803aace7	641	/**
cparata	0:dff8803aace7	642	* @brief data_ready_mode: [set] Data-ready pulsed / letched mode.
cparata	0:dff8803aace7	643	*
cparata	0:dff8803aace7	644	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	645	* @param lis2dw12_drdy_pulsed_t: change the values of drdy_pulsed in
cparata	0:dff8803aace7	646	* reg CTRL_REG7
cparata	0:dff8803aace7	647	*
cparata	0:dff8803aace7	648	*/
cparata	0:dff8803aace7	649	int32_t lis2dw12_data_ready_mode_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	650	lis2dw12_drdy_pulsed_t val)
cparata	0:dff8803aace7	651	{
cparata	0:dff8803aace7	652	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	653	int32_t mm_error;
cparata	0:dff8803aace7	654
cparata	0:dff8803aace7	655	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	656	reg.ctrl_reg7.drdy_pulsed = val;
cparata	0:dff8803aace7	657	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	658
cparata	0:dff8803aace7	659	return mm_error;
cparata	0:dff8803aace7	660	}
cparata	0:dff8803aace7	661
cparata	0:dff8803aace7	662	/**
cparata	0:dff8803aace7	663	* @brief data_ready_mode: [get] Data-ready pulsed / letched mode.
cparata	0:dff8803aace7	664	*
cparata	0:dff8803aace7	665	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	666	* @param lis2dw12_drdy_pulsed_t: Get the values of drdy_pulsed in
cparata	0:dff8803aace7	667	* reg CTRL_REG7
cparata	0:dff8803aace7	668	*
cparata	0:dff8803aace7	669	*/
cparata	0:dff8803aace7	670	int32_t lis2dw12_data_ready_mode_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	671	lis2dw12_drdy_pulsed_t *val)
cparata	0:dff8803aace7	672	{
cparata	0:dff8803aace7	673	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	674	int32_t mm_error;
cparata	0:dff8803aace7	675
cparata	0:dff8803aace7	676	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	677	*val = (lis2dw12_drdy_pulsed_t) reg.ctrl_reg7.drdy_pulsed;
cparata	0:dff8803aace7	678
cparata	0:dff8803aace7	679	return mm_error;
cparata	0:dff8803aace7	680	}
cparata	0:dff8803aace7	681
cparata	0:dff8803aace7	682	/**
cparata	0:dff8803aace7	683	* @}
cparata	0:dff8803aace7	684	*/
cparata	0:dff8803aace7	685
cparata	0:dff8803aace7	686	/**
cparata	0:dff8803aace7	687	* @addtogroup filters
cparata	0:dff8803aace7	688	* @brief This section group all the functions concerning the filters
cparata	0:dff8803aace7	689	* configuration.
cparata	0:dff8803aace7	690	* @{
cparata	0:dff8803aace7	691	*/
cparata	0:dff8803aace7	692
cparata	0:dff8803aace7	693	/**
cparata	0:dff8803aace7	694	* @brief filter_path: [set] Accelerometer filtering path for outputs.
cparata	0:dff8803aace7	695	*
cparata	0:dff8803aace7	696	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	697	* @param lis2dw12_fds_t: change the values of fds in reg CTRL6
cparata	0:dff8803aace7	698	*
cparata	0:dff8803aace7	699	*/
cparata	0:dff8803aace7	700	int32_t lis2dw12_filter_path_set(lis2dw12_ctx_t *ctx, lis2dw12_fds_t val)
cparata	0:dff8803aace7	701	{
cparata	0:dff8803aace7	702	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	703	int32_t mm_error;
cparata	0:dff8803aace7	704
cparata	0:dff8803aace7	705	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	706	reg.ctrl6.fds = ( val & 0x10 ) >> 4;
cparata	0:dff8803aace7	707	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	708
cparata	0:dff8803aace7	709	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	710	reg.ctrl_reg7.usr_off_on_out = val & 0x01;
cparata	0:dff8803aace7	711	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	712
cparata	0:dff8803aace7	713	return mm_error;
cparata	0:dff8803aace7	714	}
cparata	0:dff8803aace7	715
cparata	0:dff8803aace7	716	/**
cparata	0:dff8803aace7	717	* @brief filter_path: [get] Accelerometer filtering path for outputs.
cparata	0:dff8803aace7	718	*
cparata	0:dff8803aace7	719	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	720	* @param lis2dw12_fds_t: Get the values of fds in reg CTRL6
cparata	0:dff8803aace7	721	*
cparata	0:dff8803aace7	722	*/
cparata	0:dff8803aace7	723	int32_t lis2dw12_filter_path_get(lis2dw12_ctx_t ctx, lis2dw12_fds_t val)
cparata	0:dff8803aace7	724	{
cparata	0:dff8803aace7	725	lis2dw12_reg_t reg[2];
cparata	0:dff8803aace7	726	int32_t mm_error;
cparata	0:dff8803aace7	727
cparata	0:dff8803aace7	728	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, &reg[0].byte, 1);
cparata	0:dff8803aace7	729	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg[1].byte, 1);
cparata	0:dff8803aace7	730
cparata	0:dff8803aace7	731	*val = (lis2dw12_fds_t) ((reg[0].ctrl6.fds << 4 ) + reg[1].ctrl_reg7.usr_off_on_out);
cparata	0:dff8803aace7	732
cparata	0:dff8803aace7	733	return mm_error;
cparata	0:dff8803aace7	734	}
cparata	0:dff8803aace7	735
cparata	0:dff8803aace7	736	/**
cparata	0:dff8803aace7	737	* @brief filter_bandwidth: [set] Accelerometer cutoff filter frequency.
cparata	0:dff8803aace7	738	* Valid for low and high pass filter.
cparata	0:dff8803aace7	739	*
cparata	0:dff8803aace7	740	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	741	* @param lis2dw12_bw_filt_t: change the values of bw_filt in reg CTRL6
cparata	0:dff8803aace7	742	*
cparata	0:dff8803aace7	743	*/
cparata	0:dff8803aace7	744	int32_t lis2dw12_filter_bandwidth_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	745	lis2dw12_bw_filt_t val)
cparata	0:dff8803aace7	746	{
cparata	0:dff8803aace7	747	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	748	int32_t mm_error;
cparata	0:dff8803aace7	749
cparata	0:dff8803aace7	750	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	751	reg.ctrl6.bw_filt = val;
cparata	0:dff8803aace7	752	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	753
cparata	0:dff8803aace7	754	return mm_error;
cparata	0:dff8803aace7	755	}
cparata	0:dff8803aace7	756
cparata	0:dff8803aace7	757	/**
cparata	0:dff8803aace7	758	* @brief filter_bandwidth: [get] Accelerometer cutoff filter frequency.
cparata	0:dff8803aace7	759	* Valid for low and high pass filter.
cparata	0:dff8803aace7	760	*
cparata	0:dff8803aace7	761	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	762	* @param lis2dw12_bw_filt_t: Get the values of bw_filt in reg CTRL6
cparata	0:dff8803aace7	763	*
cparata	0:dff8803aace7	764	*/
cparata	0:dff8803aace7	765	int32_t lis2dw12_filter_bandwidth_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	766	lis2dw12_bw_filt_t *val)
cparata	0:dff8803aace7	767	{
cparata	0:dff8803aace7	768	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	769	int32_t mm_error;
cparata	0:dff8803aace7	770
cparata	0:dff8803aace7	771	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, &reg.byte, 1);
cparata	0:dff8803aace7	772	*val = (lis2dw12_bw_filt_t) reg.ctrl6.bw_filt;
cparata	0:dff8803aace7	773
cparata	0:dff8803aace7	774	return mm_error;
cparata	0:dff8803aace7	775	}
cparata	0:dff8803aace7	776
cparata	0:dff8803aace7	777	/**
cparata	0:dff8803aace7	778	* @brief reference_mode: [set] Enable HP filter reference mode.
cparata	0:dff8803aace7	779	*
cparata	0:dff8803aace7	780	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	781	* @param uint8_t val: change the values of hp_ref_mode in reg CTRL_REG7
cparata	0:dff8803aace7	782	*
cparata	0:dff8803aace7	783	*/
cparata	0:dff8803aace7	784	int32_t lis2dw12_reference_mode_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	785	{
cparata	0:dff8803aace7	786	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	787	int32_t mm_error;
cparata	0:dff8803aace7	788
cparata	0:dff8803aace7	789	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	790	reg.ctrl_reg7.hp_ref_mode = val;
cparata	0:dff8803aace7	791	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	792
cparata	0:dff8803aace7	793	return mm_error;
cparata	0:dff8803aace7	794	}
cparata	0:dff8803aace7	795
cparata	0:dff8803aace7	796	/**
cparata	0:dff8803aace7	797	* @brief reference_mode: [get] Enable HP filter reference mode.
cparata	0:dff8803aace7	798	*
cparata	0:dff8803aace7	799	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	800	* @param uint8_t: change the values of hp_ref_mode in reg CTRL_REG7
cparata	0:dff8803aace7	801	*
cparata	0:dff8803aace7	802	*/
cparata	0:dff8803aace7	803	int32_t lis2dw12_reference_mode_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	804	{
cparata	0:dff8803aace7	805	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	806	int32_t mm_error;
cparata	0:dff8803aace7	807
cparata	0:dff8803aace7	808	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	809	*val = reg.ctrl_reg7.hp_ref_mode;
cparata	0:dff8803aace7	810
cparata	0:dff8803aace7	811	return mm_error;
cparata	0:dff8803aace7	812	}
cparata	0:dff8803aace7	813
cparata	0:dff8803aace7	814	/**
cparata	0:dff8803aace7	815	* @}
cparata	0:dff8803aace7	816	*/
cparata	0:dff8803aace7	817
cparata	0:dff8803aace7	818	/**
cparata	0:dff8803aace7	819	* @addtogroup main_serial_interface
cparata	0:dff8803aace7	820	* @brief This section groups all the functions concerning main serial
cparata	0:dff8803aace7	821	* interface management (not auxiliary)
cparata	0:dff8803aace7	822	* @{
cparata	0:dff8803aace7	823	*/
cparata	0:dff8803aace7	824
cparata	0:dff8803aace7	825	/**
cparata	0:dff8803aace7	826	* @brief spi_mode: [set] SPI Serial Interface Mode selection.
cparata	0:dff8803aace7	827	*
cparata	0:dff8803aace7	828	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	829	* @param lis2dw12_sim_t: change the values of sim in reg CTRL2
cparata	0:dff8803aace7	830	*
cparata	0:dff8803aace7	831	*/
cparata	0:dff8803aace7	832	int32_t lis2dw12_spi_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sim_t val)
cparata	0:dff8803aace7	833	{
cparata	0:dff8803aace7	834	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	835	int32_t mm_error;
cparata	0:dff8803aace7	836
cparata	0:dff8803aace7	837	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	838	reg.ctrl2.sim = val;
cparata	0:dff8803aace7	839	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	840
cparata	0:dff8803aace7	841	return mm_error;
cparata	0:dff8803aace7	842	}
cparata	0:dff8803aace7	843
cparata	0:dff8803aace7	844	/**
cparata	0:dff8803aace7	845	* @brief spi_mode: [get] SPI Serial Interface Mode selection.
cparata	0:dff8803aace7	846	*
cparata	0:dff8803aace7	847	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	848	* @param lis2dw12_sim_t: Get the values of sim in reg CTRL2
cparata	0:dff8803aace7	849	*
cparata	0:dff8803aace7	850	*/
cparata	0:dff8803aace7	851	int32_t lis2dw12_spi_mode_get(lis2dw12_ctx_t ctx, lis2dw12_sim_t val)
cparata	0:dff8803aace7	852	{
cparata	0:dff8803aace7	853	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	854	int32_t mm_error;
cparata	0:dff8803aace7	855
cparata	0:dff8803aace7	856	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	857	*val = (lis2dw12_sim_t) reg.ctrl2.sim;
cparata	0:dff8803aace7	858
cparata	0:dff8803aace7	859	return mm_error;
cparata	0:dff8803aace7	860	}
cparata	0:dff8803aace7	861
cparata	0:dff8803aace7	862	/**
cparata	0:dff8803aace7	863	* @brief i2c_interface: [set] Disable / Enable I2C interface.
cparata	0:dff8803aace7	864	*
cparata	0:dff8803aace7	865	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	866	* @param lis2dw12_i2c_disable_t: change the values of i2c_disable in
cparata	0:dff8803aace7	867	* reg CTRL2
cparata	0:dff8803aace7	868	*
cparata	0:dff8803aace7	869	*/
cparata	0:dff8803aace7	870	int32_t lis2dw12_i2c_interface_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	871	lis2dw12_i2c_disable_t val)
cparata	0:dff8803aace7	872	{
cparata	0:dff8803aace7	873	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	874	int32_t mm_error;
cparata	0:dff8803aace7	875
cparata	0:dff8803aace7	876	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	877	reg.ctrl2.i2c_disable = val;
cparata	0:dff8803aace7	878	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	879
cparata	0:dff8803aace7	880	return mm_error;
cparata	0:dff8803aace7	881	}
cparata	0:dff8803aace7	882
cparata	0:dff8803aace7	883	/**
cparata	0:dff8803aace7	884	* @brief i2c_interface: [get] Disable / Enable I2C interface.
cparata	0:dff8803aace7	885	*
cparata	0:dff8803aace7	886	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	887	* @param lis2dw12_i2c_disable_t: Get the values of i2c_disable in reg CTRL2
cparata	0:dff8803aace7	888	*
cparata	0:dff8803aace7	889	*/
cparata	0:dff8803aace7	890	int32_t lis2dw12_i2c_interface_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	891	lis2dw12_i2c_disable_t *val)
cparata	0:dff8803aace7	892	{
cparata	0:dff8803aace7	893	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	894	int32_t mm_error;
cparata	0:dff8803aace7	895
cparata	0:dff8803aace7	896	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	897	*val = (lis2dw12_i2c_disable_t) reg.ctrl2.i2c_disable;
cparata	0:dff8803aace7	898
cparata	0:dff8803aace7	899	return mm_error;
cparata	0:dff8803aace7	900	}
cparata	0:dff8803aace7	901
cparata	0:dff8803aace7	902	/**
cparata	0:dff8803aace7	903	* @brief cs_mode: [set] Disconnect CS pull-up.
cparata	0:dff8803aace7	904	*
cparata	0:dff8803aace7	905	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	906	* @param lis2dw12_cs_pu_disc_t: change the values of cs_pu_disc in reg CTRL2
cparata	0:dff8803aace7	907	*
cparata	0:dff8803aace7	908	*/
cparata	0:dff8803aace7	909	int32_t lis2dw12_cs_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_cs_pu_disc_t val)
cparata	0:dff8803aace7	910	{
cparata	0:dff8803aace7	911	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	912	int32_t mm_error;
cparata	0:dff8803aace7	913
cparata	0:dff8803aace7	914	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	915	reg.ctrl2.cs_pu_disc = val;
cparata	0:dff8803aace7	916	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	917
cparata	0:dff8803aace7	918	return mm_error;
cparata	0:dff8803aace7	919	}
cparata	0:dff8803aace7	920
cparata	0:dff8803aace7	921	/**
cparata	0:dff8803aace7	922	* @brief cs_mode: [get] Disconnect CS pull-up.
cparata	0:dff8803aace7	923	*
cparata	0:dff8803aace7	924	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	925	* @param lis2dw12_cs_pu_disc_t: Get the values of cs_pu_disc in reg CTRL2
cparata	0:dff8803aace7	926	*
cparata	0:dff8803aace7	927	*/
cparata	0:dff8803aace7	928	int32_t lis2dw12_cs_mode_get(lis2dw12_ctx_t ctx, lis2dw12_cs_pu_disc_t val)
cparata	0:dff8803aace7	929	{
cparata	0:dff8803aace7	930	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	931	int32_t mm_error;
cparata	0:dff8803aace7	932
cparata	0:dff8803aace7	933	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, &reg.byte, 1);
cparata	0:dff8803aace7	934	*val = (lis2dw12_cs_pu_disc_t) reg.ctrl2.cs_pu_disc;
cparata	0:dff8803aace7	935
cparata	0:dff8803aace7	936	return mm_error;
cparata	0:dff8803aace7	937	}
cparata	0:dff8803aace7	938
cparata	0:dff8803aace7	939	/**
cparata	0:dff8803aace7	940	* @}
cparata	0:dff8803aace7	941	*/
cparata	0:dff8803aace7	942
cparata	0:dff8803aace7	943	/**
cparata	0:dff8803aace7	944	* @addtogroup interrupt_pins
cparata	0:dff8803aace7	945	* @brief This section groups all the functions that manage interrup pins
cparata	0:dff8803aace7	946	* @{
cparata	0:dff8803aace7	947	*/
cparata	0:dff8803aace7	948
cparata	0:dff8803aace7	949	/**
cparata	0:dff8803aace7	950	* @brief pin_polarity: [set] Interrupt active-high/low.
cparata	0:dff8803aace7	951	*
cparata	0:dff8803aace7	952	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	953	* @param lis2dw12_h_lactive_t: change the values of h_lactive in reg CTRL3
cparata	0:dff8803aace7	954	*
cparata	0:dff8803aace7	955	*/
cparata	0:dff8803aace7	956	int32_t lis2dw12_pin_polarity_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	957	lis2dw12_h_lactive_t val)
cparata	0:dff8803aace7	958	{
cparata	0:dff8803aace7	959	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	960	int32_t mm_error;
cparata	0:dff8803aace7	961
cparata	0:dff8803aace7	962	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	963	reg.ctrl3.h_lactive = val;
cparata	0:dff8803aace7	964	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	965
cparata	0:dff8803aace7	966	return mm_error;
cparata	0:dff8803aace7	967	}
cparata	0:dff8803aace7	968
cparata	0:dff8803aace7	969	/**
cparata	0:dff8803aace7	970	* @brief pin_polarity: [get] Interrupt active-high/low.
cparata	0:dff8803aace7	971	*
cparata	0:dff8803aace7	972	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	973	* @param lis2dw12_h_lactive_t: Get the values of h_lactive in reg CTRL3
cparata	0:dff8803aace7	974	*
cparata	0:dff8803aace7	975	*/
cparata	0:dff8803aace7	976	int32_t lis2dw12_pin_polarity_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	977	lis2dw12_h_lactive_t *val)
cparata	0:dff8803aace7	978	{
cparata	0:dff8803aace7	979	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	980	int32_t mm_error;
cparata	0:dff8803aace7	981
cparata	0:dff8803aace7	982	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	983	*val = (lis2dw12_h_lactive_t) reg.ctrl3.h_lactive;
cparata	0:dff8803aace7	984
cparata	0:dff8803aace7	985	return mm_error;
cparata	0:dff8803aace7	986	}
cparata	0:dff8803aace7	987
cparata	0:dff8803aace7	988	/**
cparata	0:dff8803aace7	989	* @brief int_notification: [set] Latched/pulsed interrupt.
cparata	0:dff8803aace7	990	*
cparata	0:dff8803aace7	991	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	992	* @param lis2dw12_lir_t: change the values of lir in reg CTRL3
cparata	0:dff8803aace7	993	*
cparata	0:dff8803aace7	994	*/
cparata	0:dff8803aace7	995	int32_t lis2dw12_int_notification_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	996	lis2dw12_lir_t val)
cparata	0:dff8803aace7	997	{
cparata	0:dff8803aace7	998	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	999	int32_t mm_error;
cparata	0:dff8803aace7	1000
cparata	0:dff8803aace7	1001	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	1002	reg.ctrl3.lir = val;
cparata	0:dff8803aace7	1003	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	1004
cparata	0:dff8803aace7	1005	return mm_error;
cparata	0:dff8803aace7	1006	}
cparata	0:dff8803aace7	1007
cparata	0:dff8803aace7	1008	/**
cparata	0:dff8803aace7	1009	* @brief int_notification: [get] Latched/pulsed interrupt.
cparata	0:dff8803aace7	1010	*
cparata	0:dff8803aace7	1011	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1012	* @param lis2dw12_lir_t: Get the values of lir in reg CTRL3
cparata	0:dff8803aace7	1013	*
cparata	0:dff8803aace7	1014	*/
cparata	0:dff8803aace7	1015	int32_t lis2dw12_int_notification_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1016	lis2dw12_lir_t *val)
cparata	0:dff8803aace7	1017	{
cparata	0:dff8803aace7	1018	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1019	int32_t mm_error;
cparata	0:dff8803aace7	1020
cparata	0:dff8803aace7	1021	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	1022	*val = (lis2dw12_lir_t) reg.ctrl3.lir;
cparata	0:dff8803aace7	1023
cparata	0:dff8803aace7	1024	return mm_error;
cparata	0:dff8803aace7	1025	}
cparata	0:dff8803aace7	1026
cparata	0:dff8803aace7	1027	/**
cparata	0:dff8803aace7	1028	* @brief pin_mode: [set] Push-pull/open drain selection on interrupt pads.
cparata	0:dff8803aace7	1029	*
cparata	0:dff8803aace7	1030	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1031	* @param lis2dw12_pp_od_t: change the values of pp_od in reg CTRL3
cparata	0:dff8803aace7	1032	*
cparata	0:dff8803aace7	1033	*/
cparata	0:dff8803aace7	1034	int32_t lis2dw12_pin_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_pp_od_t val)
cparata	0:dff8803aace7	1035	{
cparata	0:dff8803aace7	1036	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1037	int32_t mm_error;
cparata	0:dff8803aace7	1038
cparata	0:dff8803aace7	1039	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	1040	reg.ctrl3.pp_od = val;
cparata	0:dff8803aace7	1041	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	1042
cparata	0:dff8803aace7	1043	return mm_error;
cparata	0:dff8803aace7	1044	}
cparata	0:dff8803aace7	1045
cparata	0:dff8803aace7	1046	/**
cparata	0:dff8803aace7	1047	* @brief pin_mode: [get] Push-pull/open drain selection on interrupt pads.
cparata	0:dff8803aace7	1048	*
cparata	0:dff8803aace7	1049	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1050	* @param lis2dw12_pp_od_t: Get the values of pp_od in reg CTRL3
cparata	0:dff8803aace7	1051	*
cparata	0:dff8803aace7	1052	*/
cparata	0:dff8803aace7	1053	int32_t lis2dw12_pin_mode_get(lis2dw12_ctx_t ctx, lis2dw12_pp_od_t val)
cparata	0:dff8803aace7	1054	{
cparata	0:dff8803aace7	1055	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1056	int32_t mm_error;
cparata	0:dff8803aace7	1057
cparata	0:dff8803aace7	1058	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, &reg.byte, 1);
cparata	0:dff8803aace7	1059	*val = (lis2dw12_pp_od_t) reg.ctrl3.pp_od;
cparata	0:dff8803aace7	1060
cparata	0:dff8803aace7	1061	return mm_error;
cparata	0:dff8803aace7	1062	}
cparata	0:dff8803aace7	1063
cparata	0:dff8803aace7	1064	/**
cparata	0:dff8803aace7	1065	* @brief pin_int1_route: [set] Select the signal that need to
cparata	0:dff8803aace7	1066	* route on int1 pad.
cparata	0:dff8803aace7	1067	*
cparata	0:dff8803aace7	1068	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1069	* @param lis2dw12_: register CTRL4_INT1_PAD_CTRL.
cparata	0:dff8803aace7	1070	*
cparata	0:dff8803aace7	1071	*/
cparata	0:dff8803aace7	1072	int32_t lis2dw12_pin_int1_route_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1073	lis2dw12_ctrl4_int1_pad_ctrl_t *val)
cparata	0:dff8803aace7	1074	{
cparata	0:dff8803aace7	1075	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1076	int32_t mm_error;
cparata	0:dff8803aace7	1077
cparata	0:dff8803aace7	1078	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1079
cparata	0:dff8803aace7	1080	if (val->int1_tap \|\| val->int1_ff \|\| val->int1_wu \|\| val->int1_single_tap \|\|
cparata	0:dff8803aace7	1081	val->int1_6d){
cparata	0:dff8803aace7	1082	reg.ctrl_reg7.interrupts_enable = PROPERTY_ENABLE;
cparata	0:dff8803aace7	1083	}
cparata	0:dff8803aace7	1084	else{
cparata	0:dff8803aace7	1085	reg.ctrl_reg7.interrupts_enable = PROPERTY_DISABLE;
cparata	0:dff8803aace7	1086	}
cparata	0:dff8803aace7	1087
cparata	0:dff8803aace7	1088	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
cparata	0:dff8803aace7	1089	(uint8_t*) val, 1);
cparata	0:dff8803aace7	1090
cparata	0:dff8803aace7	1091	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1092
cparata	0:dff8803aace7	1093	return mm_error;
cparata	0:dff8803aace7	1094	}
cparata	0:dff8803aace7	1095
cparata	0:dff8803aace7	1096	/**
cparata	0:dff8803aace7	1097	* @brief pin_int1_route: [get] Select the signal that need to route on
cparata	0:dff8803aace7	1098	* int1 pad.
cparata	0:dff8803aace7	1099	*
cparata	0:dff8803aace7	1100	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1101	* @param lis2dw12_: register CTRL4_INT1_PAD_CTRL.
cparata	0:dff8803aace7	1102	*
cparata	0:dff8803aace7	1103	*/
cparata	0:dff8803aace7	1104	int32_t lis2dw12_pin_int1_route_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1105	lis2dw12_ctrl4_int1_pad_ctrl_t *val)
cparata	0:dff8803aace7	1106	{
cparata	0:dff8803aace7	1107	return lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
cparata	0:dff8803aace7	1108	(uint8_t*) val, 1);
cparata	0:dff8803aace7	1109	}
cparata	0:dff8803aace7	1110	/**
cparata	0:dff8803aace7	1111	* @brief pin_int2_route: [set] Select the signal that need to route on
cparata	0:dff8803aace7	1112	* int2 pad.
cparata	0:dff8803aace7	1113	*
cparata	0:dff8803aace7	1114	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1115	* @param lis2dw12_: register CTRL5_INT2_PAD_CTRL.
cparata	0:dff8803aace7	1116	*
cparata	0:dff8803aace7	1117	*/
cparata	0:dff8803aace7	1118	int32_t lis2dw12_pin_int2_route_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1119	lis2dw12_ctrl5_int2_pad_ctrl_t *val)
cparata	0:dff8803aace7	1120	{
cparata	0:dff8803aace7	1121	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1122	int32_t mm_error;
cparata	0:dff8803aace7	1123
cparata	0:dff8803aace7	1124	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1125
cparata	0:dff8803aace7	1126	if ( val->int2_sleep_state \|\| val->int2_sleep_chg ){
cparata	0:dff8803aace7	1127	reg.ctrl_reg7.interrupts_enable = PROPERTY_ENABLE;
cparata	0:dff8803aace7	1128	}
cparata	0:dff8803aace7	1129	else{
cparata	0:dff8803aace7	1130	reg.ctrl_reg7.interrupts_enable = PROPERTY_DISABLE;
cparata	0:dff8803aace7	1131	}
cparata	0:dff8803aace7	1132
cparata	0:dff8803aace7	1133	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
cparata	0:dff8803aace7	1134	(uint8_t*) val, 1);
cparata	0:dff8803aace7	1135
cparata	0:dff8803aace7	1136	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1137
cparata	0:dff8803aace7	1138	return mm_error;
cparata	0:dff8803aace7	1139	}
cparata	0:dff8803aace7	1140
cparata	0:dff8803aace7	1141	/**
cparata	0:dff8803aace7	1142	* @brief pin_int2_route: [get] Select the signal that need to route on
cparata	0:dff8803aace7	1143	* int2 pad.
cparata	0:dff8803aace7	1144	*
cparata	0:dff8803aace7	1145	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1146	* @param lis2dw12_: register CTRL5_INT2_PAD_CTRL
cparata	0:dff8803aace7	1147	*
cparata	0:dff8803aace7	1148	*/
cparata	0:dff8803aace7	1149	int32_t lis2dw12_pin_int2_route_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1150	lis2dw12_ctrl5_int2_pad_ctrl_t *val)
cparata	0:dff8803aace7	1151	{
cparata	0:dff8803aace7	1152	return lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
cparata	0:dff8803aace7	1153	(uint8_t*) val, 1);
cparata	0:dff8803aace7	1154	}
cparata	0:dff8803aace7	1155	/**
cparata	0:dff8803aace7	1156	* @brief all_on_int1: [set] All interrupt signals become available
cparata	0:dff8803aace7	1157	* on INT1 pin.
cparata	0:dff8803aace7	1158	*
cparata	0:dff8803aace7	1159	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1160	* @param uint8_t val: change the values of int2_on_int1 in reg CTRL_REG7
cparata	0:dff8803aace7	1161	*
cparata	0:dff8803aace7	1162	*/
cparata	0:dff8803aace7	1163	int32_t lis2dw12_all_on_int1_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1164	{
cparata	0:dff8803aace7	1165	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1166	int32_t mm_error;
cparata	0:dff8803aace7	1167
cparata	0:dff8803aace7	1168	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1169	reg.ctrl_reg7.int2_on_int1 = val;
cparata	0:dff8803aace7	1170	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1171
cparata	0:dff8803aace7	1172	return mm_error;
cparata	0:dff8803aace7	1173	}
cparata	0:dff8803aace7	1174
cparata	0:dff8803aace7	1175	/**
cparata	0:dff8803aace7	1176	* @brief all_on_int1: [get] All interrupt signals become available
cparata	0:dff8803aace7	1177	* on INT1 pin.
cparata	0:dff8803aace7	1178	*
cparata	0:dff8803aace7	1179	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1180	* @param uint8_t: change the values of int2_on_int1 in reg CTRL_REG7
cparata	0:dff8803aace7	1181	*
cparata	0:dff8803aace7	1182	*/
cparata	0:dff8803aace7	1183	int32_t lis2dw12_all_on_int1_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1184	{
cparata	0:dff8803aace7	1185	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1186	int32_t mm_error;
cparata	0:dff8803aace7	1187
cparata	0:dff8803aace7	1188	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1189	*val = reg.ctrl_reg7.int2_on_int1;
cparata	0:dff8803aace7	1190
cparata	0:dff8803aace7	1191	return mm_error;
cparata	0:dff8803aace7	1192	}
cparata	0:dff8803aace7	1193
cparata	0:dff8803aace7	1194	/**
cparata	0:dff8803aace7	1195	* @}
cparata	0:dff8803aace7	1196	*/
cparata	0:dff8803aace7	1197
cparata	0:dff8803aace7	1198	/**
cparata	0:dff8803aace7	1199	* @addtogroup Wake_Up_event
cparata	0:dff8803aace7	1200	* @brief This section groups all the functions that manage the Wake
cparata	0:dff8803aace7	1201	* Up event generation.
cparata	0:dff8803aace7	1202	* @{
cparata	0:dff8803aace7	1203	*/
cparata	0:dff8803aace7	1204
cparata	0:dff8803aace7	1205	/**
cparata	0:dff8803aace7	1206	* @brief wkup_threshold: [set] Threshold for wakeup.1 LSB = FS_XL / 64.
cparata	0:dff8803aace7	1207	*
cparata	0:dff8803aace7	1208	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1209	* @param uint8_t val: change the values of wk_ths in reg WAKE_UP_THS
cparata	0:dff8803aace7	1210	*
cparata	0:dff8803aace7	1211	*/
cparata	0:dff8803aace7	1212	int32_t lis2dw12_wkup_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1213	{
cparata	0:dff8803aace7	1214	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1215	int32_t mm_error;
cparata	0:dff8803aace7	1216
cparata	0:dff8803aace7	1217	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, &reg.byte, 1);
cparata	0:dff8803aace7	1218	reg.wake_up_ths.wk_ths = val;
cparata	0:dff8803aace7	1219	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, &reg.byte, 1);
cparata	0:dff8803aace7	1220
cparata	0:dff8803aace7	1221	return mm_error;
cparata	0:dff8803aace7	1222	}
cparata	0:dff8803aace7	1223
cparata	0:dff8803aace7	1224	/**
cparata	0:dff8803aace7	1225	* @brief wkup_threshold: [get] Threshold for wakeup.1 LSB = FS_XL / 64.
cparata	0:dff8803aace7	1226	*
cparata	0:dff8803aace7	1227	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1228	* @param uint8_t: change the values of wk_ths in reg WAKE_UP_THS
cparata	0:dff8803aace7	1229	*
cparata	0:dff8803aace7	1230	*/
cparata	0:dff8803aace7	1231	int32_t lis2dw12_wkup_threshold_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1232	{
cparata	0:dff8803aace7	1233	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1234	int32_t mm_error;
cparata	0:dff8803aace7	1235
cparata	0:dff8803aace7	1236	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, &reg.byte, 1);
cparata	0:dff8803aace7	1237	*val = reg.wake_up_ths.wk_ths;
cparata	0:dff8803aace7	1238
cparata	0:dff8803aace7	1239	return mm_error;
cparata	0:dff8803aace7	1240	}
cparata	0:dff8803aace7	1241
cparata	0:dff8803aace7	1242	/**
cparata	0:dff8803aace7	1243	* @brief wkup_dur: [set] Wake up duration event.1LSb = 1 / ODR.
cparata	0:dff8803aace7	1244	*
cparata	0:dff8803aace7	1245	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1246	* @param uint8_t val: change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:dff8803aace7	1247	*
cparata	0:dff8803aace7	1248	*/
cparata	0:dff8803aace7	1249	int32_t lis2dw12_wkup_dur_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1250	{
cparata	0:dff8803aace7	1251	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1252	int32_t mm_error;
cparata	0:dff8803aace7	1253
cparata	0:dff8803aace7	1254	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1255	reg.wake_up_dur.wake_dur = val;
cparata	0:dff8803aace7	1256	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1257
cparata	0:dff8803aace7	1258	return mm_error;
cparata	0:dff8803aace7	1259	}
cparata	0:dff8803aace7	1260
cparata	0:dff8803aace7	1261	/**
cparata	0:dff8803aace7	1262	* @brief wkup_dur: [get] Wake up duration event.1LSb = 1 / ODR.
cparata	0:dff8803aace7	1263	*
cparata	0:dff8803aace7	1264	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1265	* @param uint8_t: change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:dff8803aace7	1266	*
cparata	0:dff8803aace7	1267	*/
cparata	0:dff8803aace7	1268	int32_t lis2dw12_wkup_dur_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1269	{
cparata	0:dff8803aace7	1270	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1271	int32_t mm_error;
cparata	0:dff8803aace7	1272
cparata	0:dff8803aace7	1273	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1274	*val = reg.wake_up_dur.wake_dur;
cparata	0:dff8803aace7	1275
cparata	0:dff8803aace7	1276	return mm_error;
cparata	0:dff8803aace7	1277	}
cparata	0:dff8803aace7	1278
cparata	0:dff8803aace7	1279	/**
cparata	0:dff8803aace7	1280	* @brief wkup_feed_data: [set] Data sent to wake-up interrupt function.
cparata	0:dff8803aace7	1281	*
cparata	0:dff8803aace7	1282	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1283	* @param lis2dw12_usr_off_on_wu_t: change the values of usr_off_on_wu in
cparata	0:dff8803aace7	1284	* reg CTRL_REG7
cparata	0:dff8803aace7	1285	*
cparata	0:dff8803aace7	1286	*/
cparata	0:dff8803aace7	1287	int32_t lis2dw12_wkup_feed_data_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1288	lis2dw12_usr_off_on_wu_t val)
cparata	0:dff8803aace7	1289	{
cparata	0:dff8803aace7	1290	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1291	int32_t mm_error;
cparata	0:dff8803aace7	1292
cparata	0:dff8803aace7	1293	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1294	reg.ctrl_reg7.usr_off_on_wu = val;
cparata	0:dff8803aace7	1295	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1296
cparata	0:dff8803aace7	1297	return mm_error;
cparata	0:dff8803aace7	1298	}
cparata	0:dff8803aace7	1299
cparata	0:dff8803aace7	1300	/**
cparata	0:dff8803aace7	1301	* @brief wkup_feed_data: [get] Data sent to wake-up interrupt function.
cparata	0:dff8803aace7	1302	*
cparata	0:dff8803aace7	1303	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1304	* @param lis2dw12_usr_off_on_wu_t: Get the values of usr_off_on_wu in
cparata	0:dff8803aace7	1305	* reg CTRL_REG7
cparata	0:dff8803aace7	1306	*
cparata	0:dff8803aace7	1307	*/
cparata	0:dff8803aace7	1308	int32_t lis2dw12_wkup_feed_data_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1309	lis2dw12_usr_off_on_wu_t *val)
cparata	0:dff8803aace7	1310	{
cparata	0:dff8803aace7	1311	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1312	int32_t mm_error;
cparata	0:dff8803aace7	1313
cparata	0:dff8803aace7	1314	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1315	*val = (lis2dw12_usr_off_on_wu_t) reg.ctrl_reg7.usr_off_on_wu;
cparata	0:dff8803aace7	1316
cparata	0:dff8803aace7	1317	return mm_error;
cparata	0:dff8803aace7	1318	}
cparata	0:dff8803aace7	1319
cparata	0:dff8803aace7	1320	/**
cparata	0:dff8803aace7	1321	* @}
cparata	0:dff8803aace7	1322	*/
cparata	0:dff8803aace7	1323
cparata	0:dff8803aace7	1324	/**
cparata	0:dff8803aace7	1325	* @addtogroup Activity/Inactivity_detection
cparata	0:dff8803aace7	1326	* @brief This section groups all the functions concerning
cparata	0:dff8803aace7	1327	* activity/inactivity detection.
cparata	0:dff8803aace7	1328	* @{
cparata	0:dff8803aace7	1329	*/
cparata	0:dff8803aace7	1330
cparata	0:dff8803aace7	1331	/**
cparata	0:dff8803aace7	1332	* @brief act_mode: [set] Config activity / inactivity or
cparata	0:dff8803aace7	1333	* stationary / motion detection.
cparata	0:dff8803aace7	1334	*
cparata	0:dff8803aace7	1335	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1336	* @param lis2dw12_sleep_on_t: change the values of sleep_on / stationary in
cparata	0:dff8803aace7	1337	* reg WAKE_UP_THS / WAKE_UP_DUR
cparata	0:dff8803aace7	1338	*
cparata	0:dff8803aace7	1339	*/
cparata	0:dff8803aace7	1340	int32_t lis2dw12_act_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_sleep_on_t val)
cparata	0:dff8803aace7	1341	{
cparata	0:dff8803aace7	1342	lis2dw12_reg_t reg[2];
cparata	0:dff8803aace7	1343	int32_t mm_error;
cparata	0:dff8803aace7	1344
cparata	0:dff8803aace7	1345	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, &reg[0].byte, 2);
cparata	0:dff8803aace7	1346	reg[0].wake_up_ths.sleep_on = val & 0x01;
cparata	0:dff8803aace7	1347	reg[1].wake_up_dur.stationary = (val & 0x02) >> 1;
cparata	0:dff8803aace7	1348	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, &reg[0].byte, 2);
cparata	0:dff8803aace7	1349
cparata	0:dff8803aace7	1350	return mm_error;
cparata	0:dff8803aace7	1351	}
cparata	0:dff8803aace7	1352
cparata	0:dff8803aace7	1353	/**
cparata	0:dff8803aace7	1354	* @brief act_mode: [get] Config activity / inactivity or
cparata	0:dff8803aace7	1355	* stationary / motion detection.
cparata	0:dff8803aace7	1356	*
cparata	0:dff8803aace7	1357	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1358	* @param lis2dw12_sleep_on_t: Get the values of sleep_on in reg WAKE_UP_THS
cparata	0:dff8803aace7	1359	*
cparata	0:dff8803aace7	1360	*/
cparata	0:dff8803aace7	1361	int32_t lis2dw12_act_mode_get(lis2dw12_ctx_t ctx, lis2dw12_sleep_on_t val)
cparata	0:dff8803aace7	1362	{
cparata	0:dff8803aace7	1363	lis2dw12_reg_t reg[2];
cparata	0:dff8803aace7	1364	int32_t mm_error;
cparata	0:dff8803aace7	1365
cparata	0:dff8803aace7	1366	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, &reg[0].byte, 2);
cparata	0:dff8803aace7	1367	*val = (lis2dw12_sleep_on_t) ((reg[1].wake_up_dur.stationary << 1)
cparata	0:dff8803aace7	1368	+ reg[0].wake_up_ths.sleep_on);
cparata	0:dff8803aace7	1369
cparata	0:dff8803aace7	1370	return mm_error;
cparata	0:dff8803aace7	1371	}
cparata	0:dff8803aace7	1372
cparata	0:dff8803aace7	1373	/**
cparata	0:dff8803aace7	1374	* @brief act_sleep_dur: [set] Duration to go in sleep mode.
cparata	0:dff8803aace7	1375	* 1 LSb = 512 / ODR.
cparata	0:dff8803aace7	1376	*
cparata	0:dff8803aace7	1377	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1378	* @param uint8_t val: change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:dff8803aace7	1379	*
cparata	0:dff8803aace7	1380	*/
cparata	0:dff8803aace7	1381	int32_t lis2dw12_act_sleep_dur_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1382	{
cparata	0:dff8803aace7	1383	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1384	int32_t mm_error;
cparata	0:dff8803aace7	1385
cparata	0:dff8803aace7	1386	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1387	reg.wake_up_dur.sleep_dur = val;
cparata	0:dff8803aace7	1388	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1389
cparata	0:dff8803aace7	1390	return mm_error;
cparata	0:dff8803aace7	1391	}
cparata	0:dff8803aace7	1392
cparata	0:dff8803aace7	1393	/**
cparata	0:dff8803aace7	1394	* @brief act_sleep_dur: [get] Duration to go in sleep mode.
cparata	0:dff8803aace7	1395	* 1 LSb = 512 / ODR.
cparata	0:dff8803aace7	1396	*
cparata	0:dff8803aace7	1397	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1398	* @param uint8_t: change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:dff8803aace7	1399	*
cparata	0:dff8803aace7	1400	*/
cparata	0:dff8803aace7	1401	int32_t lis2dw12_act_sleep_dur_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1402	{
cparata	0:dff8803aace7	1403	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1404	int32_t mm_error;
cparata	0:dff8803aace7	1405
cparata	0:dff8803aace7	1406	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1407	*val = reg.wake_up_dur.sleep_dur;
cparata	0:dff8803aace7	1408
cparata	0:dff8803aace7	1409	return mm_error;
cparata	0:dff8803aace7	1410	}
cparata	0:dff8803aace7	1411
cparata	0:dff8803aace7	1412	/**
cparata	0:dff8803aace7	1413	* @}
cparata	0:dff8803aace7	1414	*/
cparata	0:dff8803aace7	1415
cparata	0:dff8803aace7	1416	/**
cparata	0:dff8803aace7	1417	* @addtogroup tap_generator
cparata	0:dff8803aace7	1418	* @brief This section groups all the functions that manage the tap
cparata	0:dff8803aace7	1419	* and double tap event generation.
cparata	0:dff8803aace7	1420	* @{
cparata	0:dff8803aace7	1421	*/
cparata	0:dff8803aace7	1422
cparata	0:dff8803aace7	1423	/**
cparata	0:dff8803aace7	1424	* @brief tap_threshold_x: [set] Threshold for tap recognition.
cparata	0:dff8803aace7	1425	*
cparata	0:dff8803aace7	1426	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1427	* @param uint8_t val: change the values of tap_thsx in reg TAP_THS_X
cparata	0:dff8803aace7	1428	*
cparata	0:dff8803aace7	1429	*/
cparata	0:dff8803aace7	1430	int32_t lis2dw12_tap_threshold_x_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1431	{
cparata	0:dff8803aace7	1432	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1433	int32_t mm_error;
cparata	0:dff8803aace7	1434
cparata	0:dff8803aace7	1435	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, &reg.byte, 1);
cparata	0:dff8803aace7	1436	reg.tap_ths_x.tap_thsx = val;
cparata	0:dff8803aace7	1437	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, &reg.byte, 1);
cparata	0:dff8803aace7	1438
cparata	0:dff8803aace7	1439	return mm_error;
cparata	0:dff8803aace7	1440	}
cparata	0:dff8803aace7	1441
cparata	0:dff8803aace7	1442	/**
cparata	0:dff8803aace7	1443	* @brief tap_threshold_x: [get] Threshold for tap recognition.
cparata	0:dff8803aace7	1444	*
cparata	0:dff8803aace7	1445	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1446	* @param uint8_t: change the values of tap_thsx in reg TAP_THS_X
cparata	0:dff8803aace7	1447	*
cparata	0:dff8803aace7	1448	*/
cparata	0:dff8803aace7	1449	int32_t lis2dw12_tap_threshold_x_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1450	{
cparata	0:dff8803aace7	1451	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1452	int32_t mm_error;
cparata	0:dff8803aace7	1453
cparata	0:dff8803aace7	1454	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, &reg.byte, 1);
cparata	0:dff8803aace7	1455	*val = reg.tap_ths_x.tap_thsx;
cparata	0:dff8803aace7	1456
cparata	0:dff8803aace7	1457	return mm_error;
cparata	0:dff8803aace7	1458	}
cparata	0:dff8803aace7	1459
cparata	0:dff8803aace7	1460	/**
cparata	0:dff8803aace7	1461	* @brief tap_threshold_y: [set] Threshold for tap recognition.
cparata	0:dff8803aace7	1462	*
cparata	0:dff8803aace7	1463	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1464	* @param uint8_t val: change the values of tap_thsy in reg TAP_THS_Y
cparata	0:dff8803aace7	1465	*
cparata	0:dff8803aace7	1466	*/
cparata	0:dff8803aace7	1467	int32_t lis2dw12_tap_threshold_y_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1468	{
cparata	0:dff8803aace7	1469	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1470	int32_t mm_error;
cparata	0:dff8803aace7	1471
cparata	0:dff8803aace7	1472	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, &reg.byte, 1);
cparata	0:dff8803aace7	1473	reg.tap_ths_y.tap_thsy = val;
cparata	0:dff8803aace7	1474	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, &reg.byte, 1);
cparata	0:dff8803aace7	1475
cparata	0:dff8803aace7	1476	return mm_error;
cparata	0:dff8803aace7	1477	}
cparata	0:dff8803aace7	1478
cparata	0:dff8803aace7	1479	/**
cparata	0:dff8803aace7	1480	* @brief tap_threshold_y: [get] Threshold for tap recognition.
cparata	0:dff8803aace7	1481	*
cparata	0:dff8803aace7	1482	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1483	* @param uint8_t: change the values of tap_thsy in reg TAP_THS_Y
cparata	0:dff8803aace7	1484	*
cparata	0:dff8803aace7	1485	*/
cparata	0:dff8803aace7	1486	int32_t lis2dw12_tap_threshold_y_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1487	{
cparata	0:dff8803aace7	1488	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1489	int32_t mm_error;
cparata	0:dff8803aace7	1490
cparata	0:dff8803aace7	1491	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, &reg.byte, 1);
cparata	0:dff8803aace7	1492	*val = reg.tap_ths_y.tap_thsy;
cparata	0:dff8803aace7	1493
cparata	0:dff8803aace7	1494	return mm_error;
cparata	0:dff8803aace7	1495	}
cparata	0:dff8803aace7	1496
cparata	0:dff8803aace7	1497	/**
cparata	0:dff8803aace7	1498	* @brief tap_axis_priority: [set] Selection of axis priority for
cparata	0:dff8803aace7	1499	* TAP detection.
cparata	0:dff8803aace7	1500	*
cparata	0:dff8803aace7	1501	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1502	* @param lis2dw12_tap_prior_t: change the values of tap_prior in
cparata	0:dff8803aace7	1503	* reg TAP_THS_Y
cparata	0:dff8803aace7	1504	*
cparata	0:dff8803aace7	1505	*/
cparata	0:dff8803aace7	1506	int32_t lis2dw12_tap_axis_priority_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1507	lis2dw12_tap_prior_t val)
cparata	0:dff8803aace7	1508	{
cparata	0:dff8803aace7	1509	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1510	int32_t mm_error;
cparata	0:dff8803aace7	1511
cparata	0:dff8803aace7	1512	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, &reg.byte, 1);
cparata	0:dff8803aace7	1513	reg.tap_ths_y.tap_prior = val;
cparata	0:dff8803aace7	1514	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, &reg.byte, 1);
cparata	0:dff8803aace7	1515
cparata	0:dff8803aace7	1516	return mm_error;
cparata	0:dff8803aace7	1517	}
cparata	0:dff8803aace7	1518
cparata	0:dff8803aace7	1519	/**
cparata	0:dff8803aace7	1520	* @brief tap_axis_priority: [get] Selection of axis priority for
cparata	0:dff8803aace7	1521	* TAP detection.
cparata	0:dff8803aace7	1522	*
cparata	0:dff8803aace7	1523	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1524	* @param lis2dw12_tap_prior_t: Get the values of tap_prior in reg TAP_THS_Y
cparata	0:dff8803aace7	1525	*
cparata	0:dff8803aace7	1526	*/
cparata	0:dff8803aace7	1527	int32_t lis2dw12_tap_axis_priority_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1528	lis2dw12_tap_prior_t *val)
cparata	0:dff8803aace7	1529	{
cparata	0:dff8803aace7	1530	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1531	int32_t mm_error;
cparata	0:dff8803aace7	1532
cparata	0:dff8803aace7	1533	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, &reg.byte, 1);
cparata	0:dff8803aace7	1534	*val = (lis2dw12_tap_prior_t) reg.tap_ths_y.tap_prior;
cparata	0:dff8803aace7	1535
cparata	0:dff8803aace7	1536	return mm_error;
cparata	0:dff8803aace7	1537	}
cparata	0:dff8803aace7	1538
cparata	0:dff8803aace7	1539	/**
cparata	0:dff8803aace7	1540	* @brief tap_threshold_z: [set] Threshold for tap recognition.
cparata	0:dff8803aace7	1541	*
cparata	0:dff8803aace7	1542	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1543	* @param uint8_t val: change the values of tap_thsz in reg TAP_THS_Z
cparata	0:dff8803aace7	1544	*
cparata	0:dff8803aace7	1545	*/
cparata	0:dff8803aace7	1546	int32_t lis2dw12_tap_threshold_z_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1547	{
cparata	0:dff8803aace7	1548	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1549	int32_t mm_error;
cparata	0:dff8803aace7	1550
cparata	0:dff8803aace7	1551	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1552	reg.tap_ths_z.tap_thsz = val;
cparata	0:dff8803aace7	1553	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1554
cparata	0:dff8803aace7	1555	return mm_error;
cparata	0:dff8803aace7	1556	}
cparata	0:dff8803aace7	1557
cparata	0:dff8803aace7	1558	/**
cparata	0:dff8803aace7	1559	* @brief tap_threshold_z: [get] Threshold for tap recognition.
cparata	0:dff8803aace7	1560	*
cparata	0:dff8803aace7	1561	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1562	* @param uint8_t: change the values of tap_thsz in reg TAP_THS_Z
cparata	0:dff8803aace7	1563	*
cparata	0:dff8803aace7	1564	*/
cparata	0:dff8803aace7	1565	int32_t lis2dw12_tap_threshold_z_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1566	{
cparata	0:dff8803aace7	1567	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1568	int32_t mm_error;
cparata	0:dff8803aace7	1569
cparata	0:dff8803aace7	1570	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1571	*val = reg.tap_ths_z.tap_thsz;
cparata	0:dff8803aace7	1572
cparata	0:dff8803aace7	1573	return mm_error;
cparata	0:dff8803aace7	1574	}
cparata	0:dff8803aace7	1575
cparata	0:dff8803aace7	1576	/**
cparata	0:dff8803aace7	1577	* @brief tap_detection_on_z: [set] Enable Z direction in tap recognition.
cparata	0:dff8803aace7	1578	*
cparata	0:dff8803aace7	1579	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1580	* @param uint8_t val: change the values of tap_z_en in reg TAP_THS_Z
cparata	0:dff8803aace7	1581	*
cparata	0:dff8803aace7	1582	*/
cparata	0:dff8803aace7	1583	int32_t lis2dw12_tap_detection_on_z_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1584	{
cparata	0:dff8803aace7	1585	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1586	int32_t mm_error;
cparata	0:dff8803aace7	1587
cparata	0:dff8803aace7	1588	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1589	reg.tap_ths_z.tap_z_en = val;
cparata	0:dff8803aace7	1590	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1591
cparata	0:dff8803aace7	1592	return mm_error;
cparata	0:dff8803aace7	1593	}
cparata	0:dff8803aace7	1594
cparata	0:dff8803aace7	1595	/**
cparata	0:dff8803aace7	1596	* @brief tap_detection_on_z: [get] Enable Z direction in tap recognition.
cparata	0:dff8803aace7	1597	*
cparata	0:dff8803aace7	1598	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1599	* @param uint8_t: change the values of tap_z_en in reg TAP_THS_Z
cparata	0:dff8803aace7	1600	*
cparata	0:dff8803aace7	1601	*/
cparata	0:dff8803aace7	1602	int32_t lis2dw12_tap_detection_on_z_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1603	{
cparata	0:dff8803aace7	1604	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1605	int32_t mm_error;
cparata	0:dff8803aace7	1606
cparata	0:dff8803aace7	1607	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1608	*val = reg.tap_ths_z.tap_z_en;
cparata	0:dff8803aace7	1609
cparata	0:dff8803aace7	1610	return mm_error;
cparata	0:dff8803aace7	1611	}
cparata	0:dff8803aace7	1612
cparata	0:dff8803aace7	1613	/**
cparata	0:dff8803aace7	1614	* @brief tap_detection_on_y: [set] Enable Y direction in tap recognition.
cparata	0:dff8803aace7	1615	*
cparata	0:dff8803aace7	1616	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1617	* @param uint8_t val: change the values of tap_y_en in reg TAP_THS_Z
cparata	0:dff8803aace7	1618	*
cparata	0:dff8803aace7	1619	*/
cparata	0:dff8803aace7	1620	int32_t lis2dw12_tap_detection_on_y_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1621	{
cparata	0:dff8803aace7	1622	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1623	int32_t mm_error;
cparata	0:dff8803aace7	1624
cparata	0:dff8803aace7	1625	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1626	reg.tap_ths_z.tap_y_en = val;
cparata	0:dff8803aace7	1627	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1628
cparata	0:dff8803aace7	1629	return mm_error;
cparata	0:dff8803aace7	1630	}
cparata	0:dff8803aace7	1631
cparata	0:dff8803aace7	1632	/**
cparata	0:dff8803aace7	1633	* @brief tap_detection_on_y: [get] Enable Y direction in tap recognition.
cparata	0:dff8803aace7	1634	*
cparata	0:dff8803aace7	1635	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1636	* @param uint8_t: change the values of tap_y_en in reg TAP_THS_Z
cparata	0:dff8803aace7	1637	*
cparata	0:dff8803aace7	1638	*/
cparata	0:dff8803aace7	1639	int32_t lis2dw12_tap_detection_on_y_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1640	{
cparata	0:dff8803aace7	1641	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1642	int32_t mm_error;
cparata	0:dff8803aace7	1643
cparata	0:dff8803aace7	1644	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1645	*val = reg.tap_ths_z.tap_y_en;
cparata	0:dff8803aace7	1646
cparata	0:dff8803aace7	1647	return mm_error;
cparata	0:dff8803aace7	1648	}
cparata	0:dff8803aace7	1649
cparata	0:dff8803aace7	1650	/**
cparata	0:dff8803aace7	1651	* @brief tap_detection_on_x: [set] Enable X direction in tap recognition.
cparata	0:dff8803aace7	1652	*
cparata	0:dff8803aace7	1653	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1654	* @param uint8_t val: change the values of tap_x_en in reg TAP_THS_Z
cparata	0:dff8803aace7	1655	*
cparata	0:dff8803aace7	1656	*/
cparata	0:dff8803aace7	1657	int32_t lis2dw12_tap_detection_on_x_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1658	{
cparata	0:dff8803aace7	1659	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1660	int32_t mm_error;
cparata	0:dff8803aace7	1661
cparata	0:dff8803aace7	1662	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1663	reg.tap_ths_z.tap_x_en = val;
cparata	0:dff8803aace7	1664	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1665
cparata	0:dff8803aace7	1666	return mm_error;
cparata	0:dff8803aace7	1667	}
cparata	0:dff8803aace7	1668
cparata	0:dff8803aace7	1669	/**
cparata	0:dff8803aace7	1670	* @brief tap_detection_on_x: [get] Enable X direction in tap recognition.
cparata	0:dff8803aace7	1671	*
cparata	0:dff8803aace7	1672	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1673	* @param uint8_t: change the values of tap_x_en in reg TAP_THS_Z
cparata	0:dff8803aace7	1674	*
cparata	0:dff8803aace7	1675	*/
cparata	0:dff8803aace7	1676	int32_t lis2dw12_tap_detection_on_x_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1677	{
cparata	0:dff8803aace7	1678	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1679	int32_t mm_error;
cparata	0:dff8803aace7	1680
cparata	0:dff8803aace7	1681	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, &reg.byte, 1);
cparata	0:dff8803aace7	1682	*val = reg.tap_ths_z.tap_x_en;
cparata	0:dff8803aace7	1683
cparata	0:dff8803aace7	1684	return mm_error;
cparata	0:dff8803aace7	1685	}
cparata	0:dff8803aace7	1686
cparata	0:dff8803aace7	1687	/**
cparata	0:dff8803aace7	1688	* @brief tap_shock: [set] Maximum duration is the maximum time of an
cparata	0:dff8803aace7	1689	* overthreshold signal detection to be recognized
cparata	0:dff8803aace7	1690	* as a tap event. The default value of these bits
cparata	0:dff8803aace7	1691	* is 00b which corresponds to 4*ODR_XL time.
cparata	0:dff8803aace7	1692	* If the SHOCK[1:0] bits are set to a different
cparata	0:dff8803aace7	1693	* value, 1LSB corresponds to 8*ODR_XL time.
cparata	0:dff8803aace7	1694	*
cparata	0:dff8803aace7	1695	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1696	* @param uint8_t val: change the values of shock in reg INT_DUR
cparata	0:dff8803aace7	1697	*
cparata	0:dff8803aace7	1698	*/
cparata	0:dff8803aace7	1699	int32_t lis2dw12_tap_shock_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1700	{
cparata	0:dff8803aace7	1701	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1702	int32_t mm_error;
cparata	0:dff8803aace7	1703
cparata	0:dff8803aace7	1704	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1705	reg.int_dur.shock = val;
cparata	0:dff8803aace7	1706	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1707
cparata	0:dff8803aace7	1708	return mm_error;
cparata	0:dff8803aace7	1709	}
cparata	0:dff8803aace7	1710
cparata	0:dff8803aace7	1711	/**
cparata	0:dff8803aace7	1712	* @brief tap_shock: [get] Maximum duration is the maximum time of an
cparata	0:dff8803aace7	1713	* overthreshold signal detection to be
cparata	0:dff8803aace7	1714	* recognized as a tap event.
cparata	0:dff8803aace7	1715	* The default value of these bits is 00b which
cparata	0:dff8803aace7	1716	* corresponds to 4*ODR_XL time.
cparata	0:dff8803aace7	1717	* If the SHOCK[1:0] bits are set to a different
cparata	0:dff8803aace7	1718	* value, 1LSB corresponds to 8*ODR_XL time.
cparata	0:dff8803aace7	1719	*
cparata	0:dff8803aace7	1720	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1721	* @param uint8_t: change the values of shock in reg INT_DUR
cparata	0:dff8803aace7	1722	*
cparata	0:dff8803aace7	1723	*/
cparata	0:dff8803aace7	1724	int32_t lis2dw12_tap_shock_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1725	{
cparata	0:dff8803aace7	1726	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1727	int32_t mm_error;
cparata	0:dff8803aace7	1728
cparata	0:dff8803aace7	1729	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1730	*val = reg.int_dur.shock;
cparata	0:dff8803aace7	1731
cparata	0:dff8803aace7	1732	return mm_error;
cparata	0:dff8803aace7	1733	}
cparata	0:dff8803aace7	1734
cparata	0:dff8803aace7	1735	/**
cparata	0:dff8803aace7	1736	* @brief tap_quiet: [set] Quiet time is the time after the first
cparata	0:dff8803aace7	1737	* detected tap in which there must not be any
cparata	0:dff8803aace7	1738	* overthreshold event.
cparata	0:dff8803aace7	1739	* The default value of these bits is 00b which
cparata	0:dff8803aace7	1740	* corresponds to 2*ODR_XL time.
cparata	0:dff8803aace7	1741	* If the QUIET[1:0] bits are set to a different
cparata	0:dff8803aace7	1742	* value, 1LSB corresponds to 4*ODR_XL time.
cparata	0:dff8803aace7	1743	*
cparata	0:dff8803aace7	1744	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1745	* @param uint8_t val: change the values of quiet in reg INT_DUR
cparata	0:dff8803aace7	1746	*
cparata	0:dff8803aace7	1747	*/
cparata	0:dff8803aace7	1748	int32_t lis2dw12_tap_quiet_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1749	{
cparata	0:dff8803aace7	1750	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1751	int32_t mm_error;
cparata	0:dff8803aace7	1752
cparata	0:dff8803aace7	1753	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1754	reg.int_dur.quiet = val;
cparata	0:dff8803aace7	1755	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1756
cparata	0:dff8803aace7	1757	return mm_error;
cparata	0:dff8803aace7	1758	}
cparata	0:dff8803aace7	1759
cparata	0:dff8803aace7	1760	/**
cparata	0:dff8803aace7	1761	* @brief tap_quiet: [get] Quiet time is the time after the first
cparata	0:dff8803aace7	1762	* detected tap in which there must not be
cparata	0:dff8803aace7	1763	* any overthreshold event.
cparata	0:dff8803aace7	1764	* The default value of these bits is 00b which
cparata	0:dff8803aace7	1765	* corresponds to 2*ODR_XL time.
cparata	0:dff8803aace7	1766	* If the QUIET[1:0] bits are set to a different
cparata	0:dff8803aace7	1767	* value, 1LSB corresponds to 4*ODR_XL time.
cparata	0:dff8803aace7	1768	*
cparata	0:dff8803aace7	1769	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1770	* @param uint8_t: change the values of quiet in reg INT_DUR
cparata	0:dff8803aace7	1771	*
cparata	0:dff8803aace7	1772	*/
cparata	0:dff8803aace7	1773	int32_t lis2dw12_tap_quiet_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1774	{
cparata	0:dff8803aace7	1775	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1776	int32_t mm_error;
cparata	0:dff8803aace7	1777
cparata	0:dff8803aace7	1778	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1779	*val = reg.int_dur.quiet;
cparata	0:dff8803aace7	1780
cparata	0:dff8803aace7	1781	return mm_error;
cparata	0:dff8803aace7	1782	}
cparata	0:dff8803aace7	1783
cparata	0:dff8803aace7	1784	/**
cparata	0:dff8803aace7	1785	* @brief tap_dur: [set] When double tap recognition is enabled,
cparata	0:dff8803aace7	1786	* this register expresses the maximum time
cparata	0:dff8803aace7	1787	* between two consecutive detected taps to
cparata	0:dff8803aace7	1788	* determine a double tap event.
cparata	0:dff8803aace7	1789	* The default value of these bits is 0000b
cparata	0:dff8803aace7	1790	* which corresponds to 16*ODR_XL time.
cparata	0:dff8803aace7	1791	* If the DUR[3:0] bits are set to a different value,
cparata	0:dff8803aace7	1792	* 1LSB corresponds to 32*ODR_XL time.
cparata	0:dff8803aace7	1793	*
cparata	0:dff8803aace7	1794	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1795	* @param uint8_t val: change the values of latency in reg INT_DUR
cparata	0:dff8803aace7	1796	*
cparata	0:dff8803aace7	1797	*/
cparata	0:dff8803aace7	1798	int32_t lis2dw12_tap_dur_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1799	{
cparata	0:dff8803aace7	1800	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1801	int32_t mm_error;
cparata	0:dff8803aace7	1802
cparata	0:dff8803aace7	1803	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1804	reg.int_dur.latency = val;
cparata	0:dff8803aace7	1805	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1806
cparata	0:dff8803aace7	1807	return mm_error;
cparata	0:dff8803aace7	1808	}
cparata	0:dff8803aace7	1809
cparata	0:dff8803aace7	1810	/**
cparata	0:dff8803aace7	1811	* @brief tap_dur: [get] When double tap recognition is enabled,
cparata	0:dff8803aace7	1812	* this register expresses the maximum time
cparata	0:dff8803aace7	1813	* between two consecutive detected taps to
cparata	0:dff8803aace7	1814	* determine a double tap event.
cparata	0:dff8803aace7	1815	* The default value of these bits is 0000b
cparata	0:dff8803aace7	1816	* which corresponds to 16*ODR_XL time.
cparata	0:dff8803aace7	1817	* If the DUR[3:0] bits are set to a different
cparata	0:dff8803aace7	1818	* value, 1LSB corresponds to 32*ODR_XL time.
cparata	0:dff8803aace7	1819	*
cparata	0:dff8803aace7	1820	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1821	* @param uint8_t: change the values of latency in reg INT_DUR
cparata	0:dff8803aace7	1822	*
cparata	0:dff8803aace7	1823	*/
cparata	0:dff8803aace7	1824	int32_t lis2dw12_tap_dur_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1825	{
cparata	0:dff8803aace7	1826	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1827	int32_t mm_error;
cparata	0:dff8803aace7	1828
cparata	0:dff8803aace7	1829	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, &reg.byte, 1);
cparata	0:dff8803aace7	1830	*val = reg.int_dur.latency;
cparata	0:dff8803aace7	1831
cparata	0:dff8803aace7	1832	return mm_error;
cparata	0:dff8803aace7	1833	}
cparata	0:dff8803aace7	1834
cparata	0:dff8803aace7	1835	/**
cparata	0:dff8803aace7	1836	* @brief tap_mode: [set] Single/double-tap event enable.
cparata	0:dff8803aace7	1837	*
cparata	0:dff8803aace7	1838	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1839	* @param lis2dw12_single_double_tap_t: change the values of
cparata	0:dff8803aace7	1840	* single_double_tap in reg WAKE_UP_THS
cparata	0:dff8803aace7	1841	*
cparata	0:dff8803aace7	1842	*/
cparata	0:dff8803aace7	1843	int32_t lis2dw12_tap_mode_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1844	lis2dw12_single_double_tap_t val)
cparata	0:dff8803aace7	1845	{
cparata	0:dff8803aace7	1846	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1847	int32_t mm_error;
cparata	0:dff8803aace7	1848
cparata	0:dff8803aace7	1849	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, &reg.byte, 1);
cparata	0:dff8803aace7	1850	reg.wake_up_ths.single_double_tap = val;
cparata	0:dff8803aace7	1851	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, &reg.byte, 1);
cparata	0:dff8803aace7	1852
cparata	0:dff8803aace7	1853	return mm_error;
cparata	0:dff8803aace7	1854	}
cparata	0:dff8803aace7	1855
cparata	0:dff8803aace7	1856	/**
cparata	0:dff8803aace7	1857	* @brief tap_mode: [get] Single/double-tap event enable.
cparata	0:dff8803aace7	1858	*
cparata	0:dff8803aace7	1859	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1860	* @param lis2dw12_single_double_tap_t: Get the values of single_double_tap
cparata	0:dff8803aace7	1861	* in reg WAKE_UP_THS
cparata	0:dff8803aace7	1862	*
cparata	0:dff8803aace7	1863	*/
cparata	0:dff8803aace7	1864	int32_t lis2dw12_tap_mode_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1865	lis2dw12_single_double_tap_t *val)
cparata	0:dff8803aace7	1866	{
cparata	0:dff8803aace7	1867	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1868	int32_t mm_error;
cparata	0:dff8803aace7	1869
cparata	0:dff8803aace7	1870	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, &reg.byte, 1);
cparata	0:dff8803aace7	1871	*val = (lis2dw12_single_double_tap_t) reg.wake_up_ths.single_double_tap;
cparata	0:dff8803aace7	1872
cparata	0:dff8803aace7	1873	return mm_error;
cparata	0:dff8803aace7	1874	}
cparata	0:dff8803aace7	1875
cparata	0:dff8803aace7	1876	/**
cparata	0:dff8803aace7	1877	* @brief tap_src: [get] Read the tap / double tap source register.
cparata	0:dff8803aace7	1878	*
cparata	0:dff8803aace7	1879	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1880	* @param lis2dw12_tap_src: union of registers from TAP_SRC to
cparata	0:dff8803aace7	1881	*
cparata	0:dff8803aace7	1882	*/
cparata	0:dff8803aace7	1883	int32_t lis2dw12_tap_src_get(lis2dw12_ctx_t ctx, lis2dw12_tap_src_t val)
cparata	0:dff8803aace7	1884	{
cparata	0:dff8803aace7	1885	return lis2dw12_read_reg(ctx, LIS2DW12_TAP_SRC, (uint8_t*) val, 1);
cparata	0:dff8803aace7	1886	}
cparata	0:dff8803aace7	1887	/**
cparata	0:dff8803aace7	1888	* @}
cparata	0:dff8803aace7	1889	*/
cparata	0:dff8803aace7	1890
cparata	0:dff8803aace7	1891	/**
cparata	0:dff8803aace7	1892	* @addtogroup Six_position_detection(6D/4D)
cparata	0:dff8803aace7	1893	* @brief This section groups all the functions concerning six
cparata	0:dff8803aace7	1894	* position detection (6D).
cparata	0:dff8803aace7	1895	* @{
cparata	0:dff8803aace7	1896	*/
cparata	0:dff8803aace7	1897
cparata	0:dff8803aace7	1898	/**
cparata	0:dff8803aace7	1899	* @brief 6d_threshold: [set] Threshold for 4D/6D function.
cparata	0:dff8803aace7	1900	*
cparata	0:dff8803aace7	1901	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1902	* @param uint8_t val: change the values of 6d_ths in reg TAP_THS_X
cparata	0:dff8803aace7	1903	*
cparata	0:dff8803aace7	1904	*/
cparata	0:dff8803aace7	1905	int32_t lis2dw12_6d_threshold_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1906	{
cparata	0:dff8803aace7	1907	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1908	int32_t mm_error;
cparata	0:dff8803aace7	1909
cparata	0:dff8803aace7	1910	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, &reg.byte, 1);
cparata	0:dff8803aace7	1911	reg.tap_ths_x._6d_ths = val;
cparata	0:dff8803aace7	1912	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, &reg.byte, 1);
cparata	0:dff8803aace7	1913
cparata	0:dff8803aace7	1914	return mm_error;
cparata	0:dff8803aace7	1915	}
cparata	0:dff8803aace7	1916
cparata	0:dff8803aace7	1917	/**
cparata	0:dff8803aace7	1918	* @brief 6d_threshold: [get] Threshold for 4D/6D function.
cparata	0:dff8803aace7	1919	*
cparata	0:dff8803aace7	1920	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1921	* @param uint8_t: change the values of 6d_ths in reg TAP_THS_X
cparata	0:dff8803aace7	1922	*
cparata	0:dff8803aace7	1923	*/
cparata	0:dff8803aace7	1924	int32_t lis2dw12_6d_threshold_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1925	{
cparata	0:dff8803aace7	1926	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1927	int32_t mm_error;
cparata	0:dff8803aace7	1928
cparata	0:dff8803aace7	1929	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, &reg.byte, 1);
cparata	0:dff8803aace7	1930	*val = reg.tap_ths_x._6d_ths;
cparata	0:dff8803aace7	1931
cparata	0:dff8803aace7	1932	return mm_error;
cparata	0:dff8803aace7	1933	}
cparata	0:dff8803aace7	1934
cparata	0:dff8803aace7	1935	/**
cparata	0:dff8803aace7	1936	* @brief 4d_mode: [set] 4D orientation detection enable.
cparata	0:dff8803aace7	1937	*
cparata	0:dff8803aace7	1938	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1939	* @param uint8_t val: change the values of 4d_en in reg TAP_THS_X
cparata	0:dff8803aace7	1940	*
cparata	0:dff8803aace7	1941	*/
cparata	0:dff8803aace7	1942	int32_t lis2dw12_4d_mode_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	1943	{
cparata	0:dff8803aace7	1944	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1945	int32_t mm_error;
cparata	0:dff8803aace7	1946
cparata	0:dff8803aace7	1947	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, &reg.byte, 1);
cparata	0:dff8803aace7	1948	reg.tap_ths_x._4d_en = val;
cparata	0:dff8803aace7	1949	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, &reg.byte, 1);
cparata	0:dff8803aace7	1950
cparata	0:dff8803aace7	1951	return mm_error;
cparata	0:dff8803aace7	1952	}
cparata	0:dff8803aace7	1953
cparata	0:dff8803aace7	1954	/**
cparata	0:dff8803aace7	1955	* @brief 4d_mode: [get] 4D orientation detection enable.
cparata	0:dff8803aace7	1956	*
cparata	0:dff8803aace7	1957	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1958	* @param uint8_t: change the values of 4d_en in reg TAP_THS_X
cparata	0:dff8803aace7	1959	*
cparata	0:dff8803aace7	1960	*/
cparata	0:dff8803aace7	1961	int32_t lis2dw12_4d_mode_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	1962	{
cparata	0:dff8803aace7	1963	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1964	int32_t mm_error;
cparata	0:dff8803aace7	1965
cparata	0:dff8803aace7	1966	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, &reg.byte, 1);
cparata	0:dff8803aace7	1967	*val = reg.tap_ths_x._4d_en;
cparata	0:dff8803aace7	1968
cparata	0:dff8803aace7	1969	return mm_error;
cparata	0:dff8803aace7	1970	}
cparata	0:dff8803aace7	1971
cparata	0:dff8803aace7	1972	/**
cparata	0:dff8803aace7	1973	* @brief 6d_src: [get] Read the 6D tap source register.
cparata	0:dff8803aace7	1974	*
cparata	0:dff8803aace7	1975	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1976	* @param lis2dw12_6d_src: union of registers from SIXD_SRC to
cparata	0:dff8803aace7	1977	*
cparata	0:dff8803aace7	1978	*/
cparata	0:dff8803aace7	1979	int32_t lis2dw12_6d_src_get(lis2dw12_ctx_t ctx, lis2dw12_sixd_src_t val)
cparata	0:dff8803aace7	1980	{
cparata	0:dff8803aace7	1981	return lis2dw12_read_reg(ctx, LIS2DW12_SIXD_SRC, (uint8_t*) val, 1);
cparata	0:dff8803aace7	1982	}
cparata	0:dff8803aace7	1983	/**
cparata	0:dff8803aace7	1984	* @brief 6d_feed_data: [set] Data sent to 6D interrupt function.
cparata	0:dff8803aace7	1985	*
cparata	0:dff8803aace7	1986	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	1987	* @param lis2dw12_lpass_on6d_t: change the values of lpass_on6d in
cparata	0:dff8803aace7	1988	* reg CTRL_REG7
cparata	0:dff8803aace7	1989	*
cparata	0:dff8803aace7	1990	*/
cparata	0:dff8803aace7	1991	int32_t lis2dw12_6d_feed_data_set(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	1992	lis2dw12_lpass_on6d_t val)
cparata	0:dff8803aace7	1993	{
cparata	0:dff8803aace7	1994	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	1995	int32_t mm_error;
cparata	0:dff8803aace7	1996
cparata	0:dff8803aace7	1997	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	1998	reg.ctrl_reg7.lpass_on6d = val;
cparata	0:dff8803aace7	1999	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	2000
cparata	0:dff8803aace7	2001	return mm_error;
cparata	0:dff8803aace7	2002	}
cparata	0:dff8803aace7	2003
cparata	0:dff8803aace7	2004	/**
cparata	0:dff8803aace7	2005	* @brief 6d_feed_data: [get] Data sent to 6D interrupt function.
cparata	0:dff8803aace7	2006	*
cparata	0:dff8803aace7	2007	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2008	* @param lis2dw12_lpass_on6d_t: Get the values of lpass_on6d in
cparata	0:dff8803aace7	2009	* reg CTRL_REG7
cparata	0:dff8803aace7	2010	*
cparata	0:dff8803aace7	2011	*/
cparata	0:dff8803aace7	2012	int32_t lis2dw12_6d_feed_data_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	2013	lis2dw12_lpass_on6d_t *val)
cparata	0:dff8803aace7	2014	{
cparata	0:dff8803aace7	2015	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2016	int32_t mm_error;
cparata	0:dff8803aace7	2017
cparata	0:dff8803aace7	2018	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, &reg.byte, 1);
cparata	0:dff8803aace7	2019	*val = (lis2dw12_lpass_on6d_t) reg.ctrl_reg7.lpass_on6d;
cparata	0:dff8803aace7	2020
cparata	0:dff8803aace7	2021	return mm_error;
cparata	0:dff8803aace7	2022	}
cparata	0:dff8803aace7	2023
cparata	0:dff8803aace7	2024	/**
cparata	0:dff8803aace7	2025	* @}
cparata	0:dff8803aace7	2026	*/
cparata	0:dff8803aace7	2027
cparata	0:dff8803aace7	2028	/**
cparata	0:dff8803aace7	2029	* @addtogroup free_fall
cparata	0:dff8803aace7	2030	* @brief This section group all the functions concerning
cparata	0:dff8803aace7	2031	* the free fall detection.
cparata	0:dff8803aace7	2032	* @{
cparata	0:dff8803aace7	2033	*/
cparata	0:dff8803aace7	2034
cparata	0:dff8803aace7	2035	/**
cparata	0:dff8803aace7	2036	* @brief ff_dur: [set] Wake up duration event.1LSb = 1 / ODR.
cparata	0:dff8803aace7	2037	*
cparata	0:dff8803aace7	2038	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2039	* @param uint8_t val: change the values of ff_dur in
cparata	0:dff8803aace7	2040	* reg WAKE_UP_DUR /F REE_FALL
cparata	0:dff8803aace7	2041	*
cparata	0:dff8803aace7	2042	*/
cparata	0:dff8803aace7	2043	int32_t lis2dw12_ff_dur_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2044	{
cparata	0:dff8803aace7	2045	lis2dw12_reg_t reg[2];
cparata	0:dff8803aace7	2046	int32_t mm_error;
cparata	0:dff8803aace7	2047
cparata	0:dff8803aace7	2048	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, &reg[0].byte, 2);
cparata	0:dff8803aace7	2049	reg[0].wake_up_dur.ff_dur = (val & 0x20) >> 5;
cparata	0:dff8803aace7	2050	reg[1].free_fall.ff_dur = val & 0x1F;
cparata	0:dff8803aace7	2051	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, &reg[0].byte, 2);
cparata	0:dff8803aace7	2052
cparata	0:dff8803aace7	2053	return mm_error;
cparata	0:dff8803aace7	2054	}
cparata	0:dff8803aace7	2055
cparata	0:dff8803aace7	2056	/**
cparata	0:dff8803aace7	2057	* @brief ff_dur: [get] Wake up duration event.1LSb = 1 / ODR.
cparata	0:dff8803aace7	2058	*
cparata	0:dff8803aace7	2059	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2060	* @param uint8_t: change the values of ff_dur in
cparata	0:dff8803aace7	2061	* reg WAKE_UP_DUR /F REE_FALL
cparata	0:dff8803aace7	2062	*
cparata	0:dff8803aace7	2063	*/
cparata	0:dff8803aace7	2064	int32_t lis2dw12_ff_dur_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2065	{
cparata	0:dff8803aace7	2066	lis2dw12_reg_t reg[2];
cparata	0:dff8803aace7	2067	int32_t mm_error;
cparata	0:dff8803aace7	2068
cparata	0:dff8803aace7	2069	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, &reg[0].byte, 2);
cparata	0:dff8803aace7	2070	*val = (reg[0].wake_up_dur.ff_dur << 5) + reg[1].free_fall.ff_dur;
cparata	0:dff8803aace7	2071
cparata	0:dff8803aace7	2072	return mm_error;
cparata	0:dff8803aace7	2073	}
cparata	0:dff8803aace7	2074
cparata	0:dff8803aace7	2075	/**
cparata	0:dff8803aace7	2076	* @brief ff_threshold: [set] Free fall threshold setting.
cparata	0:dff8803aace7	2077	*
cparata	0:dff8803aace7	2078	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2079	* @param lis2dw12_ff_ths_t: change the values of ff_ths in reg FREE_FALL
cparata	0:dff8803aace7	2080	*
cparata	0:dff8803aace7	2081	*/
cparata	0:dff8803aace7	2082	int32_t lis2dw12_ff_threshold_set(lis2dw12_ctx_t *ctx, lis2dw12_ff_ths_t val)
cparata	0:dff8803aace7	2083	{
cparata	0:dff8803aace7	2084	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2085	int32_t mm_error;
cparata	0:dff8803aace7	2086
cparata	0:dff8803aace7	2087	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, &reg.byte, 1);
cparata	0:dff8803aace7	2088	reg.free_fall.ff_ths = val;
cparata	0:dff8803aace7	2089	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL, &reg.byte, 1);
cparata	0:dff8803aace7	2090
cparata	0:dff8803aace7	2091	return mm_error;
cparata	0:dff8803aace7	2092	}
cparata	0:dff8803aace7	2093
cparata	0:dff8803aace7	2094	/**
cparata	0:dff8803aace7	2095	* @brief ff_threshold: [get] Free fall threshold setting.
cparata	0:dff8803aace7	2096	*
cparata	0:dff8803aace7	2097	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2098	* @param lis2dw12_ff_ths_t: Get the values of ff_ths in reg FREE_FALL
cparata	0:dff8803aace7	2099	*
cparata	0:dff8803aace7	2100	*/
cparata	0:dff8803aace7	2101	int32_t lis2dw12_ff_threshold_get(lis2dw12_ctx_t *ctx,
cparata	0:dff8803aace7	2102	lis2dw12_ff_ths_t *val)
cparata	0:dff8803aace7	2103	{
cparata	0:dff8803aace7	2104	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2105	int32_t mm_error;
cparata	0:dff8803aace7	2106
cparata	0:dff8803aace7	2107	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, &reg.byte, 1);
cparata	0:dff8803aace7	2108	*val = (lis2dw12_ff_ths_t) reg.free_fall.ff_ths;
cparata	0:dff8803aace7	2109
cparata	0:dff8803aace7	2110	return mm_error;
cparata	0:dff8803aace7	2111	}
cparata	0:dff8803aace7	2112
cparata	0:dff8803aace7	2113	/**
cparata	0:dff8803aace7	2114	* @}
cparata	0:dff8803aace7	2115	*/
cparata	0:dff8803aace7	2116
cparata	0:dff8803aace7	2117	/**
cparata	0:dff8803aace7	2118	* @addtogroup fifo
cparata	0:dff8803aace7	2119	* @brief This section group all the functions concerning the fifo usage
cparata	0:dff8803aace7	2120	* @{
cparata	0:dff8803aace7	2121	*/
cparata	0:dff8803aace7	2122
cparata	0:dff8803aace7	2123	/**
cparata	0:dff8803aace7	2124	* @brief fifo_watermark: [set] FIFO watermark level selection.
cparata	0:dff8803aace7	2125	*
cparata	0:dff8803aace7	2126	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2127	* @param uint8_t val: change the values of fth in reg FIFO_CTRL
cparata	0:dff8803aace7	2128	*
cparata	0:dff8803aace7	2129	*/
cparata	0:dff8803aace7	2130	int32_t lis2dw12_fifo_watermark_set(lis2dw12_ctx_t *ctx, uint8_t val)
cparata	0:dff8803aace7	2131	{
cparata	0:dff8803aace7	2132	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2133	int32_t mm_error;
cparata	0:dff8803aace7	2134
cparata	0:dff8803aace7	2135	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, &reg.byte, 1);
cparata	0:dff8803aace7	2136	reg.fifo_ctrl.fth = val;
cparata	0:dff8803aace7	2137	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, &reg.byte, 1);
cparata	0:dff8803aace7	2138
cparata	0:dff8803aace7	2139	return mm_error;
cparata	0:dff8803aace7	2140	}
cparata	0:dff8803aace7	2141
cparata	0:dff8803aace7	2142	/**
cparata	0:dff8803aace7	2143	* @brief fifo_watermark: [get] FIFO watermark level selection.
cparata	0:dff8803aace7	2144	*
cparata	0:dff8803aace7	2145	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2146	* @param uint8_t: change the values of fth in reg FIFO_CTRL
cparata	0:dff8803aace7	2147	*
cparata	0:dff8803aace7	2148	*/
cparata	0:dff8803aace7	2149	int32_t lis2dw12_fifo_watermark_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2150	{
cparata	0:dff8803aace7	2151	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2152	int32_t mm_error;
cparata	0:dff8803aace7	2153
cparata	0:dff8803aace7	2154	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, &reg.byte, 1);
cparata	0:dff8803aace7	2155	*val = reg.fifo_ctrl.fth;
cparata	0:dff8803aace7	2156
cparata	0:dff8803aace7	2157	return mm_error;
cparata	0:dff8803aace7	2158	}
cparata	0:dff8803aace7	2159
cparata	0:dff8803aace7	2160	/**
cparata	0:dff8803aace7	2161	* @brief fifo_mode: [set] FIFO mode selection.
cparata	0:dff8803aace7	2162	*
cparata	0:dff8803aace7	2163	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2164	* @param lis2dw12_fmode_t: change the values of fmode in reg FIFO_CTRL
cparata	0:dff8803aace7	2165	*
cparata	0:dff8803aace7	2166	*/
cparata	0:dff8803aace7	2167	int32_t lis2dw12_fifo_mode_set(lis2dw12_ctx_t *ctx, lis2dw12_fmode_t val)
cparata	0:dff8803aace7	2168	{
cparata	0:dff8803aace7	2169	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2170	int32_t mm_error;
cparata	0:dff8803aace7	2171
cparata	0:dff8803aace7	2172	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, &reg.byte, 1);
cparata	0:dff8803aace7	2173	reg.fifo_ctrl.fmode = val;
cparata	0:dff8803aace7	2174	mm_error = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, &reg.byte, 1);
cparata	0:dff8803aace7	2175
cparata	0:dff8803aace7	2176	return mm_error;
cparata	0:dff8803aace7	2177	}
cparata	0:dff8803aace7	2178
cparata	0:dff8803aace7	2179	/**
cparata	0:dff8803aace7	2180	* @brief fifo_mode: [get] FIFO mode selection.
cparata	0:dff8803aace7	2181	*
cparata	0:dff8803aace7	2182	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2183	* @param lis2dw12_fmode_t: Get the values of fmode in reg FIFO_CTRL
cparata	0:dff8803aace7	2184	*
cparata	0:dff8803aace7	2185	*/
cparata	0:dff8803aace7	2186	int32_t lis2dw12_fifo_mode_get(lis2dw12_ctx_t ctx, lis2dw12_fmode_t val)
cparata	0:dff8803aace7	2187	{
cparata	0:dff8803aace7	2188	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2189	int32_t mm_error;
cparata	0:dff8803aace7	2190
cparata	0:dff8803aace7	2191	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, &reg.byte, 1);
cparata	0:dff8803aace7	2192	*val = (lis2dw12_fmode_t) reg.fifo_ctrl.fmode;
cparata	0:dff8803aace7	2193
cparata	0:dff8803aace7	2194	return mm_error;
cparata	0:dff8803aace7	2195	}
cparata	0:dff8803aace7	2196
cparata	0:dff8803aace7	2197	/**
cparata	0:dff8803aace7	2198	* @brief fifo_data_level: [get] Number of unread samples stored in FIFO.
cparata	0:dff8803aace7	2199	*
cparata	0:dff8803aace7	2200	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2201	* @param uint8_t: change the values of diff in reg FIFO_SAMPLES
cparata	0:dff8803aace7	2202	*
cparata	0:dff8803aace7	2203	*/
cparata	0:dff8803aace7	2204	int32_t lis2dw12_fifo_data_level_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2205	{
cparata	0:dff8803aace7	2206	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2207	int32_t mm_error;
cparata	0:dff8803aace7	2208
cparata	0:dff8803aace7	2209	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, &reg.byte, 1);
cparata	0:dff8803aace7	2210	*val = reg.fifo_samples.diff;
cparata	0:dff8803aace7	2211
cparata	0:dff8803aace7	2212	return mm_error;
cparata	0:dff8803aace7	2213	}
cparata	0:dff8803aace7	2214	/**
cparata	0:dff8803aace7	2215	* @brief fifo_ovr_flag: [get] FIFO overrun status.
cparata	0:dff8803aace7	2216	*
cparata	0:dff8803aace7	2217	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2218	* @param uint8_t: change the values of fifo_ovr in reg FIFO_SAMPLES
cparata	0:dff8803aace7	2219	*
cparata	0:dff8803aace7	2220	*/
cparata	0:dff8803aace7	2221	int32_t lis2dw12_fifo_ovr_flag_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2222	{
cparata	0:dff8803aace7	2223	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2224	int32_t mm_error;
cparata	0:dff8803aace7	2225
cparata	0:dff8803aace7	2226	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, &reg.byte, 1);
cparata	0:dff8803aace7	2227	*val = reg.fifo_samples.fifo_ovr;
cparata	0:dff8803aace7	2228
cparata	0:dff8803aace7	2229	return mm_error;
cparata	0:dff8803aace7	2230	}
cparata	0:dff8803aace7	2231	/**
cparata	0:dff8803aace7	2232	* @brief fifo_wtm_flag: [get] FIFO threshold status flag.
cparata	0:dff8803aace7	2233	*
cparata	0:dff8803aace7	2234	* @param lis2dw12_ctx_t *ctx: read / write interface definitions
cparata	0:dff8803aace7	2235	* @param uint8_t: change the values of fifo_fth in reg FIFO_SAMPLES
cparata	0:dff8803aace7	2236	*
cparata	0:dff8803aace7	2237	*/
cparata	0:dff8803aace7	2238	int32_t lis2dw12_fifo_wtm_flag_get(lis2dw12_ctx_t ctx, uint8_t val)
cparata	0:dff8803aace7	2239	{
cparata	0:dff8803aace7	2240	lis2dw12_reg_t reg;
cparata	0:dff8803aace7	2241	int32_t mm_error;
cparata	0:dff8803aace7	2242
cparata	0:dff8803aace7	2243	mm_error = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, &reg.byte, 1);
cparata	0:dff8803aace7	2244	*val = reg.fifo_samples.fifo_fth;
cparata	0:dff8803aace7	2245
cparata	0:dff8803aace7	2246	return mm_error;
cparata	0:dff8803aace7	2247	}
cparata	0:dff8803aace7	2248	/**
cparata	0:dff8803aace7	2249	* @}
cparata	0:dff8803aace7	2250	*/
cparata	0:dff8803aace7	2251
cparata	0:dff8803aace7	2252	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	19 Nov 2018
Imports:	30
Forks:	0
Commits:	5
Dependents:	2
Dependencies:	2
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The code in this repository is Apache licensed.

lis2dw12_reg.c@0:dff8803aace7, 2018-11-19 (annotated)

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