ST / IIS2DLPC

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

iis2dlpc_reg.c@1:7b1fcb1bb23d, 2018-11-19 (annotated)

Committer:
cparata
Date:
Mon Nov 19 14:28:06 2018 +0000
Revision:
1:7b1fcb1bb23d
Parent:
0:13631b50eae6
Child:
2:28ad92a16a36
Fix header file

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cparata 1:7b1fcb1bb23d 1 /**
cparata 0:13631b50eae6 2 ******************************************************************************
cparata 0:13631b50eae6 3 * @file iis2dlpc_reg.c
cparata 0:13631b50eae6 4 * @author Sensors Software Solution Team
cparata 0:13631b50eae6 5 * @brief IIS2DLPC driver file
cparata 0:13631b50eae6 6 ******************************************************************************
cparata 0:13631b50eae6 7 * @attention
cparata 0:13631b50eae6 8 *
cparata 0:13631b50eae6 9 * <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
cparata 0:13631b50eae6 10 *
cparata 0:13631b50eae6 11 * Redistribution and use in source and binary forms, with or without
cparata 0:13631b50eae6 12 * modification, are permitted provided that the following conditions
cparata 0:13631b50eae6 13 * are met:
cparata 0:13631b50eae6 14 * 1. Redistributions of source code must retain the above copyright notice,
cparata 0:13631b50eae6 15 * this list of conditions and the following disclaimer.
cparata 0:13631b50eae6 16 * 2. Redistributions in binary form must reproduce the above copyright
cparata 0:13631b50eae6 17 * notice, this list of conditions and the following disclaimer in the
cparata 0:13631b50eae6 18 * documentation and/or other materials provided with the distribution.
cparata 0:13631b50eae6 19 * 3. Neither the name of STMicroelectronics nor the names of its
cparata 0:13631b50eae6 20 * contributors may be used to endorse or promote products derived from
cparata 0:13631b50eae6 21 * this software without specific prior written permission.
cparata 0:13631b50eae6 22 *
cparata 0:13631b50eae6 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
cparata 0:13631b50eae6 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
cparata 0:13631b50eae6 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
cparata 0:13631b50eae6 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
cparata 0:13631b50eae6 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
cparata 0:13631b50eae6 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
cparata 0:13631b50eae6 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
cparata 0:13631b50eae6 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
cparata 0:13631b50eae6 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
cparata 0:13631b50eae6 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
cparata 0:13631b50eae6 33 * POSSIBILITY OF SUCH DAMAGE.
cparata 0:13631b50eae6 34 *
cparata 0:13631b50eae6 35 */
cparata 0:13631b50eae6 36
cparata 0:13631b50eae6 37 #include "iis2dlpc_reg.h"
cparata 0:13631b50eae6 38
cparata 0:13631b50eae6 39 /**
cparata 0:13631b50eae6 40 * @defgroup IIS2DLPC
cparata 0:13631b50eae6 41 * @brief This file provides a set of functions needed to drive the
cparata 0:13631b50eae6 42 * iis2dlpc enanced inertial module.
cparata 0:13631b50eae6 43 * @{
cparata 0:13631b50eae6 44 *
cparata 0:13631b50eae6 45 */
cparata 0:13631b50eae6 46
cparata 0:13631b50eae6 47 /**
cparata 0:13631b50eae6 48 * @defgroup IIS2DLPC_Interfaces_Functions
cparata 0:13631b50eae6 49 * @brief This section provide a set of functions used to read and
cparata 0:13631b50eae6 50 * write a generic register of the device.
cparata 0:13631b50eae6 51 * MANDATORY: return 0 -> no Error.
cparata 0:13631b50eae6 52 * @{
cparata 0:13631b50eae6 53 *
cparata 0:13631b50eae6 54 */
cparata 0:13631b50eae6 55
cparata 0:13631b50eae6 56 /**
cparata 0:13631b50eae6 57 * @brief Read generic device register
cparata 0:13631b50eae6 58 *
cparata 0:13631b50eae6 59 * @param ctx read / write interface definitions(ptr)
cparata 0:13631b50eae6 60 * @param reg register to read
cparata 0:13631b50eae6 61 * @param data pointer to buffer that store the data read(ptr)
cparata 0:13631b50eae6 62 * @param len number of consecutive register to read
cparata 0:13631b50eae6 63 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 64 *
cparata 0:13631b50eae6 65 */
cparata 0:13631b50eae6 66 int32_t iis2dlpc_read_reg(iis2dlpc_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata 0:13631b50eae6 67 uint16_t len)
cparata 0:13631b50eae6 68 {
cparata 0:13631b50eae6 69 int32_t ret;
cparata 0:13631b50eae6 70 ret = ctx->read_reg(ctx->handle, reg, data, len);
cparata 0:13631b50eae6 71 return ret;
cparata 0:13631b50eae6 72 }
cparata 0:13631b50eae6 73
cparata 0:13631b50eae6 74 /**
cparata 0:13631b50eae6 75 * @brief Write generic device register
cparata 0:13631b50eae6 76 *
cparata 0:13631b50eae6 77 * @param ctx read / write interface definitions(ptr)
cparata 0:13631b50eae6 78 * @param reg register to write
cparata 0:13631b50eae6 79 * @param data pointer to data to write in register reg(ptr)
cparata 0:13631b50eae6 80 * @param len number of consecutive register to write
cparata 0:13631b50eae6 81 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 82 *
cparata 0:13631b50eae6 83 */
cparata 0:13631b50eae6 84 int32_t iis2dlpc_write_reg(iis2dlpc_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata 0:13631b50eae6 85 uint16_t len)
cparata 0:13631b50eae6 86 {
cparata 0:13631b50eae6 87 int32_t ret;
cparata 0:13631b50eae6 88 ret = ctx->write_reg(ctx->handle, reg, data, len);
cparata 0:13631b50eae6 89 return ret;
cparata 0:13631b50eae6 90 }
cparata 0:13631b50eae6 91
cparata 0:13631b50eae6 92 /**
cparata 0:13631b50eae6 93 * @}
cparata 0:13631b50eae6 94 *
cparata 0:13631b50eae6 95 */
cparata 0:13631b50eae6 96
cparata 0:13631b50eae6 97 /**
cparata 0:13631b50eae6 98 * @defgroup IIS2DLPC_Sensitivity
cparata 0:13631b50eae6 99 * @brief These functions convert raw-data into engineering units.
cparata 0:13631b50eae6 100 * @{
cparata 0:13631b50eae6 101 *
cparata 0:13631b50eae6 102 */
cparata 0:13631b50eae6 103
cparata 0:13631b50eae6 104 float iis2dlpc_from_fs2_to_mg(int16_t lsb)
cparata 0:13631b50eae6 105 {
cparata 0:13631b50eae6 106 return ((float)lsb) * 0.061f;
cparata 0:13631b50eae6 107 }
cparata 0:13631b50eae6 108
cparata 0:13631b50eae6 109 float iis2dlpc_from_fs4_to_mg(int16_t lsb)
cparata 0:13631b50eae6 110 {
cparata 0:13631b50eae6 111 return ((float)lsb) * 0.122f;
cparata 0:13631b50eae6 112 }
cparata 0:13631b50eae6 113
cparata 0:13631b50eae6 114 float iis2dlpc_from_fs8_to_mg(int16_t lsb)
cparata 0:13631b50eae6 115 {
cparata 0:13631b50eae6 116 return ((float)lsb) * 0.244f;
cparata 0:13631b50eae6 117 }
cparata 0:13631b50eae6 118
cparata 0:13631b50eae6 119 float iis2dlpc_from_fs16_to_mg(int16_t lsb)
cparata 0:13631b50eae6 120 {
cparata 0:13631b50eae6 121 return ((float)lsb) *0.488f;
cparata 0:13631b50eae6 122 }
cparata 0:13631b50eae6 123
cparata 0:13631b50eae6 124 float iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb)
cparata 0:13631b50eae6 125 {
cparata 0:13631b50eae6 126 return ((float)lsb) * 0.061f;
cparata 0:13631b50eae6 127 }
cparata 0:13631b50eae6 128
cparata 0:13631b50eae6 129 float iis2dlpc_from_fs4_lp1_to_mg(int16_t lsb)
cparata 0:13631b50eae6 130 {
cparata 0:13631b50eae6 131 return ((float)lsb) * 0.122f;
cparata 0:13631b50eae6 132 }
cparata 0:13631b50eae6 133
cparata 0:13631b50eae6 134 float iis2dlpc_from_fs8_lp1_to_mg(int16_t lsb)
cparata 0:13631b50eae6 135 {
cparata 0:13631b50eae6 136 return ((float)lsb) * 0.244f;
cparata 0:13631b50eae6 137 }
cparata 0:13631b50eae6 138
cparata 0:13631b50eae6 139 float iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb)
cparata 0:13631b50eae6 140 {
cparata 0:13631b50eae6 141 return ((float)lsb) * 0.488f;
cparata 0:13631b50eae6 142 }
cparata 0:13631b50eae6 143
cparata 0:13631b50eae6 144 float iis2dlpc_from_lsb_to_celsius(int16_t lsb)
cparata 0:13631b50eae6 145 {
cparata 0:13631b50eae6 146 return (((float)lsb / 16.0f) + 25.0f);
cparata 0:13631b50eae6 147 }
cparata 0:13631b50eae6 148
cparata 0:13631b50eae6 149 /**
cparata 0:13631b50eae6 150 * @}
cparata 0:13631b50eae6 151 *
cparata 0:13631b50eae6 152 */
cparata 0:13631b50eae6 153
cparata 0:13631b50eae6 154 /**
cparata 0:13631b50eae6 155 * @defgroup IIS2DLPC_Data_Generation
cparata 0:13631b50eae6 156 * @brief This section groups all the functions concerning
cparata 0:13631b50eae6 157 * data generation
cparata 0:13631b50eae6 158 * @{
cparata 0:13631b50eae6 159 *
cparata 0:13631b50eae6 160 */
cparata 0:13631b50eae6 161
cparata 0:13631b50eae6 162 /**
cparata 0:13631b50eae6 163 * @brief Select accelerometer operating modes.[set]
cparata 0:13631b50eae6 164 *
cparata 0:13631b50eae6 165 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 166 * @param val change the values of mode / lp_mode in reg CTRL1
cparata 0:13631b50eae6 167 * and low_noise in reg CTRL6
cparata 0:13631b50eae6 168 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 169 *
cparata 0:13631b50eae6 170 */
cparata 0:13631b50eae6 171 int32_t iis2dlpc_power_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_mode_t val)
cparata 0:13631b50eae6 172 {
cparata 0:13631b50eae6 173 iis2dlpc_ctrl1_t ctrl1;
cparata 0:13631b50eae6 174 iis2dlpc_ctrl6_t ctrl6;
cparata 0:13631b50eae6 175 int32_t ret;
cparata 0:13631b50eae6 176
cparata 0:13631b50eae6 177 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata 0:13631b50eae6 178 if (ret == 0) {
cparata 0:13631b50eae6 179 ctrl1.mode = ( (uint8_t) val & 0x0CU ) >> 2;
cparata 0:13631b50eae6 180 ctrl1.lp_mode = (uint8_t) val & 0x03U ;
cparata 0:13631b50eae6 181 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata 0:13631b50eae6 182 }
cparata 0:13631b50eae6 183 if (ret == 0) {
cparata 0:13631b50eae6 184 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata 0:13631b50eae6 185 }
cparata 0:13631b50eae6 186 if (ret == 0) {
cparata 0:13631b50eae6 187 ctrl6.low_noise = ( (uint8_t) val & 0x10U ) >> 4;
cparata 0:13631b50eae6 188 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata 0:13631b50eae6 189 } else {
cparata 0:13631b50eae6 190 ret = ret;
cparata 0:13631b50eae6 191 }
cparata 0:13631b50eae6 192 return ret;
cparata 0:13631b50eae6 193 }
cparata 0:13631b50eae6 194
cparata 0:13631b50eae6 195 /**
cparata 0:13631b50eae6 196 * @brief Select accelerometer operating modes.[get]
cparata 0:13631b50eae6 197 *
cparata 0:13631b50eae6 198 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 199 * @param val change the values of mode / lp_mode in reg CTRL1
cparata 0:13631b50eae6 200 * and low_noise in reg CTRL6
cparata 0:13631b50eae6 201 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 202 *
cparata 0:13631b50eae6 203 */
cparata 0:13631b50eae6 204 int32_t iis2dlpc_power_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_mode_t *val)
cparata 0:13631b50eae6 205 {
cparata 0:13631b50eae6 206 iis2dlpc_ctrl1_t ctrl1;
cparata 0:13631b50eae6 207 iis2dlpc_ctrl6_t ctrl6;
cparata 0:13631b50eae6 208 int32_t ret;
cparata 0:13631b50eae6 209
cparata 0:13631b50eae6 210 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata 0:13631b50eae6 211 if (ret == 0) {
cparata 0:13631b50eae6 212 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata 0:13631b50eae6 213
cparata 0:13631b50eae6 214 switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
cparata 0:13631b50eae6 215 ctrl1.lp_mode)) {
cparata 0:13631b50eae6 216 case IIS2DLPC_HIGH_PERFORMANCE:
cparata 0:13631b50eae6 217 *val = IIS2DLPC_HIGH_PERFORMANCE;
cparata 0:13631b50eae6 218 break;
cparata 0:13631b50eae6 219 case IIS2DLPC_CONT_LOW_PWR_4:
cparata 0:13631b50eae6 220 *val = IIS2DLPC_CONT_LOW_PWR_4;
cparata 0:13631b50eae6 221 break;
cparata 0:13631b50eae6 222 case IIS2DLPC_CONT_LOW_PWR_3:
cparata 0:13631b50eae6 223 *val = IIS2DLPC_CONT_LOW_PWR_3;
cparata 0:13631b50eae6 224 break;
cparata 0:13631b50eae6 225 case IIS2DLPC_CONT_LOW_PWR_2:
cparata 0:13631b50eae6 226 *val = IIS2DLPC_CONT_LOW_PWR_2;
cparata 0:13631b50eae6 227 break;
cparata 0:13631b50eae6 228 case IIS2DLPC_CONT_LOW_PWR_12bit:
cparata 0:13631b50eae6 229 *val = IIS2DLPC_CONT_LOW_PWR_12bit;
cparata 0:13631b50eae6 230 break;
cparata 0:13631b50eae6 231 case IIS2DLPC_SINGLE_LOW_PWR_4:
cparata 0:13631b50eae6 232 *val = IIS2DLPC_SINGLE_LOW_PWR_4;
cparata 0:13631b50eae6 233 break;
cparata 0:13631b50eae6 234 case IIS2DLPC_SINGLE_LOW_PWR_3:
cparata 0:13631b50eae6 235 *val = IIS2DLPC_SINGLE_LOW_PWR_3;
cparata 0:13631b50eae6 236 break;
cparata 0:13631b50eae6 237 case IIS2DLPC_SINGLE_LOW_PWR_2:
cparata 0:13631b50eae6 238 *val = IIS2DLPC_SINGLE_LOW_PWR_2;
cparata 0:13631b50eae6 239 break;
cparata 0:13631b50eae6 240 case IIS2DLPC_SINGLE_LOW_PWR_12bit:
cparata 0:13631b50eae6 241 *val = IIS2DLPC_SINGLE_LOW_PWR_12bit;
cparata 0:13631b50eae6 242 break;
cparata 0:13631b50eae6 243 case IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE:
cparata 0:13631b50eae6 244 *val = IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE;
cparata 0:13631b50eae6 245 break;
cparata 0:13631b50eae6 246 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4:
cparata 0:13631b50eae6 247 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4;
cparata 0:13631b50eae6 248 break;
cparata 0:13631b50eae6 249 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3:
cparata 0:13631b50eae6 250 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3;
cparata 0:13631b50eae6 251 break;
cparata 0:13631b50eae6 252 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2:
cparata 0:13631b50eae6 253 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2;
cparata 0:13631b50eae6 254 break;
cparata 0:13631b50eae6 255 case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit:
cparata 0:13631b50eae6 256 *val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit;
cparata 0:13631b50eae6 257 break;
cparata 0:13631b50eae6 258 case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4:
cparata 0:13631b50eae6 259 *val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4;
cparata 0:13631b50eae6 260 break;
cparata 0:13631b50eae6 261 case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3:
cparata 0:13631b50eae6 262 *val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3;
cparata 0:13631b50eae6 263 break;
cparata 0:13631b50eae6 264 case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2:
cparata 0:13631b50eae6 265 *val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2;
cparata 0:13631b50eae6 266 break;
cparata 0:13631b50eae6 267 case IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit:
cparata 0:13631b50eae6 268 *val = IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit;
cparata 0:13631b50eae6 269 break;
cparata 0:13631b50eae6 270 default:
cparata 0:13631b50eae6 271 *val = IIS2DLPC_HIGH_PERFORMANCE;
cparata 0:13631b50eae6 272 break;
cparata 0:13631b50eae6 273 }
cparata 0:13631b50eae6 274 }
cparata 0:13631b50eae6 275 return ret;
cparata 0:13631b50eae6 276 }
cparata 0:13631b50eae6 277
cparata 0:13631b50eae6 278 /**
cparata 0:13631b50eae6 279 * @brief Accelerometer data rate selection.[set]
cparata 0:13631b50eae6 280 *
cparata 0:13631b50eae6 281 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 282 * @param val change the values of odr in reg CTRL1
cparata 0:13631b50eae6 283 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 284 *
cparata 0:13631b50eae6 285 */
cparata 0:13631b50eae6 286 int32_t iis2dlpc_data_rate_set(iis2dlpc_ctx_t *ctx, iis2dlpc_odr_t val)
cparata 0:13631b50eae6 287 {
cparata 0:13631b50eae6 288 iis2dlpc_ctrl1_t ctrl1;
cparata 0:13631b50eae6 289 iis2dlpc_ctrl3_t ctrl3;
cparata 0:13631b50eae6 290 int32_t ret;
cparata 0:13631b50eae6 291
cparata 0:13631b50eae6 292 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata 0:13631b50eae6 293 if (ret == 0) {
cparata 0:13631b50eae6 294 ctrl1.odr = (uint8_t) val;
cparata 0:13631b50eae6 295 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata 0:13631b50eae6 296 }
cparata 0:13631b50eae6 297 if (ret == 0) {
cparata 0:13631b50eae6 298 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1);
cparata 0:13631b50eae6 299 }
cparata 0:13631b50eae6 300 if (ret == 0) {
cparata 0:13631b50eae6 301 ctrl3.slp_mode = ( (uint8_t) val & 0x30U ) >> 4;
cparata 0:13631b50eae6 302 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1);
cparata 0:13631b50eae6 303 } else {
cparata 0:13631b50eae6 304 ret = ret;
cparata 0:13631b50eae6 305 }
cparata 0:13631b50eae6 306 return ret;
cparata 0:13631b50eae6 307 }
cparata 0:13631b50eae6 308
cparata 0:13631b50eae6 309 /**
cparata 0:13631b50eae6 310 * @brief Accelerometer data rate selection.[get]
cparata 0:13631b50eae6 311 *
cparata 0:13631b50eae6 312 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 313 * @param val Get the values of odr in reg CTRL1
cparata 0:13631b50eae6 314 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 315 *
cparata 0:13631b50eae6 316 */
cparata 0:13631b50eae6 317 int32_t iis2dlpc_data_rate_get(iis2dlpc_ctx_t *ctx, iis2dlpc_odr_t *val)
cparata 0:13631b50eae6 318 {
cparata 0:13631b50eae6 319 iis2dlpc_ctrl1_t ctrl1;
cparata 0:13631b50eae6 320 iis2dlpc_ctrl3_t ctrl3;
cparata 0:13631b50eae6 321 int32_t ret;
cparata 0:13631b50eae6 322
cparata 0:13631b50eae6 323 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata 0:13631b50eae6 324 if (ret == 0) {
cparata 0:13631b50eae6 325 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1);
cparata 0:13631b50eae6 326
cparata 0:13631b50eae6 327 switch ((ctrl3.slp_mode << 4) + ctrl1.odr) {
cparata 0:13631b50eae6 328 case IIS2DLPC_XL_ODR_OFF:
cparata 0:13631b50eae6 329 *val = IIS2DLPC_XL_ODR_OFF;
cparata 0:13631b50eae6 330 break;
cparata 0:13631b50eae6 331 case IIS2DLPC_XL_ODR_1Hz6_LP_ONLY:
cparata 0:13631b50eae6 332 *val = IIS2DLPC_XL_ODR_1Hz6_LP_ONLY;
cparata 0:13631b50eae6 333 break;
cparata 0:13631b50eae6 334 case IIS2DLPC_XL_ODR_12Hz5:
cparata 0:13631b50eae6 335 *val = IIS2DLPC_XL_ODR_12Hz5;
cparata 0:13631b50eae6 336 break;
cparata 0:13631b50eae6 337 case IIS2DLPC_XL_ODR_25Hz:
cparata 0:13631b50eae6 338 *val = IIS2DLPC_XL_ODR_25Hz;
cparata 0:13631b50eae6 339 break;
cparata 0:13631b50eae6 340 case IIS2DLPC_XL_ODR_50Hz:
cparata 0:13631b50eae6 341 *val = IIS2DLPC_XL_ODR_50Hz;
cparata 0:13631b50eae6 342 break;
cparata 0:13631b50eae6 343 case IIS2DLPC_XL_ODR_100Hz:
cparata 0:13631b50eae6 344 *val = IIS2DLPC_XL_ODR_100Hz;
cparata 0:13631b50eae6 345 break;
cparata 0:13631b50eae6 346 case IIS2DLPC_XL_ODR_200Hz:
cparata 0:13631b50eae6 347 *val = IIS2DLPC_XL_ODR_200Hz;
cparata 0:13631b50eae6 348 break;
cparata 0:13631b50eae6 349 case IIS2DLPC_XL_ODR_400Hz:
cparata 0:13631b50eae6 350 *val = IIS2DLPC_XL_ODR_400Hz;
cparata 0:13631b50eae6 351 break;
cparata 0:13631b50eae6 352 case IIS2DLPC_XL_ODR_800Hz:
cparata 0:13631b50eae6 353 *val = IIS2DLPC_XL_ODR_800Hz;
cparata 0:13631b50eae6 354 break;
cparata 0:13631b50eae6 355 case IIS2DLPC_XL_ODR_1k6Hz:
cparata 0:13631b50eae6 356 *val = IIS2DLPC_XL_ODR_1k6Hz;
cparata 0:13631b50eae6 357 break;
cparata 0:13631b50eae6 358 case IIS2DLPC_XL_SET_SW_TRIG:
cparata 0:13631b50eae6 359 *val = IIS2DLPC_XL_SET_SW_TRIG;
cparata 0:13631b50eae6 360 break;
cparata 0:13631b50eae6 361 case IIS2DLPC_XL_SET_PIN_TRIG:
cparata 0:13631b50eae6 362 *val = IIS2DLPC_XL_SET_PIN_TRIG;
cparata 0:13631b50eae6 363 break;
cparata 0:13631b50eae6 364 default:
cparata 0:13631b50eae6 365 *val = IIS2DLPC_XL_ODR_OFF;
cparata 0:13631b50eae6 366 break;
cparata 0:13631b50eae6 367 }
cparata 0:13631b50eae6 368 }
cparata 0:13631b50eae6 369 return ret;
cparata 0:13631b50eae6 370 }
cparata 0:13631b50eae6 371
cparata 0:13631b50eae6 372 /**
cparata 0:13631b50eae6 373 * @brief Block data update.[set]
cparata 0:13631b50eae6 374 *
cparata 0:13631b50eae6 375 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 376 * @param val change the values of bdu in reg CTRL2
cparata 0:13631b50eae6 377 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 378 *
cparata 0:13631b50eae6 379 */
cparata 0:13631b50eae6 380 int32_t iis2dlpc_block_data_update_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 381 {
cparata 0:13631b50eae6 382 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 383 int32_t ret;
cparata 0:13631b50eae6 384
cparata 0:13631b50eae6 385 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 386 if (ret == 0) {
cparata 0:13631b50eae6 387 reg.bdu = val;
cparata 0:13631b50eae6 388 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 389 }
cparata 0:13631b50eae6 390 return ret;
cparata 0:13631b50eae6 391 }
cparata 0:13631b50eae6 392
cparata 0:13631b50eae6 393 /**
cparata 0:13631b50eae6 394 * @brief Block data update.[get]
cparata 0:13631b50eae6 395 *
cparata 0:13631b50eae6 396 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 397 * @param val change the values of bdu in reg CTRL2
cparata 0:13631b50eae6 398 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 399 *
cparata 0:13631b50eae6 400 */
cparata 0:13631b50eae6 401 int32_t iis2dlpc_block_data_update_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 402 {
cparata 0:13631b50eae6 403 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 404 int32_t ret;
cparata 0:13631b50eae6 405
cparata 0:13631b50eae6 406 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 407 *val = reg.bdu;
cparata 0:13631b50eae6 408
cparata 0:13631b50eae6 409 return ret;
cparata 0:13631b50eae6 410 }
cparata 0:13631b50eae6 411
cparata 0:13631b50eae6 412 /**
cparata 0:13631b50eae6 413 * @brief Accelerometer full-scale selection.[set]
cparata 0:13631b50eae6 414 *
cparata 0:13631b50eae6 415 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 416 * @param val change the values of fs in reg CTRL6
cparata 0:13631b50eae6 417 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 418 *
cparata 0:13631b50eae6 419 */
cparata 0:13631b50eae6 420 int32_t iis2dlpc_full_scale_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fs_t val)
cparata 0:13631b50eae6 421 {
cparata 0:13631b50eae6 422 iis2dlpc_ctrl6_t reg;
cparata 0:13631b50eae6 423 int32_t ret;
cparata 0:13631b50eae6 424
cparata 0:13631b50eae6 425 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 426 if (ret == 0) {
cparata 0:13631b50eae6 427 reg.fs = (uint8_t) val;
cparata 0:13631b50eae6 428 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 429 }
cparata 0:13631b50eae6 430 return ret;
cparata 0:13631b50eae6 431 }
cparata 0:13631b50eae6 432
cparata 0:13631b50eae6 433 /**
cparata 0:13631b50eae6 434 * @brief Accelerometer full-scale selection.[get]
cparata 0:13631b50eae6 435 *
cparata 0:13631b50eae6 436 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 437 * @param val Get the values of fs in reg CTRL6
cparata 0:13631b50eae6 438 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 439 *
cparata 0:13631b50eae6 440 */
cparata 0:13631b50eae6 441 int32_t iis2dlpc_full_scale_get(iis2dlpc_ctx_t *ctx, iis2dlpc_fs_t *val)
cparata 0:13631b50eae6 442 {
cparata 0:13631b50eae6 443 iis2dlpc_ctrl6_t reg;
cparata 0:13631b50eae6 444 int32_t ret;
cparata 0:13631b50eae6 445
cparata 0:13631b50eae6 446 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 447
cparata 0:13631b50eae6 448 switch (reg.fs) {
cparata 0:13631b50eae6 449 case IIS2DLPC_2g:
cparata 0:13631b50eae6 450 *val = IIS2DLPC_2g;
cparata 0:13631b50eae6 451 break;
cparata 0:13631b50eae6 452 case IIS2DLPC_4g:
cparata 0:13631b50eae6 453 *val = IIS2DLPC_4g;
cparata 0:13631b50eae6 454 break;
cparata 0:13631b50eae6 455 case IIS2DLPC_8g:
cparata 0:13631b50eae6 456 *val = IIS2DLPC_8g;
cparata 0:13631b50eae6 457 break;
cparata 0:13631b50eae6 458 case IIS2DLPC_16g:
cparata 0:13631b50eae6 459 *val = IIS2DLPC_16g;
cparata 0:13631b50eae6 460 break;
cparata 0:13631b50eae6 461 default:
cparata 0:13631b50eae6 462 *val = IIS2DLPC_2g;
cparata 0:13631b50eae6 463 break;
cparata 0:13631b50eae6 464 }
cparata 0:13631b50eae6 465 return ret;
cparata 0:13631b50eae6 466 }
cparata 0:13631b50eae6 467
cparata 0:13631b50eae6 468 /**
cparata 0:13631b50eae6 469 * @brief The STATUS_REG register of the device.[get]
cparata 0:13631b50eae6 470 *
cparata 0:13631b50eae6 471 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 472 * @param val union of registers from STATUS to
cparata 0:13631b50eae6 473 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 474 *
cparata 0:13631b50eae6 475 */
cparata 0:13631b50eae6 476 int32_t iis2dlpc_status_reg_get(iis2dlpc_ctx_t *ctx, iis2dlpc_status_t *val)
cparata 0:13631b50eae6 477 {
cparata 0:13631b50eae6 478 int32_t ret;
cparata 0:13631b50eae6 479 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS, (uint8_t*) val, 1);
cparata 0:13631b50eae6 480 return ret;
cparata 0:13631b50eae6 481 }
cparata 0:13631b50eae6 482
cparata 0:13631b50eae6 483 /**
cparata 0:13631b50eae6 484 * @brief Accelerometer new data available.[get]
cparata 0:13631b50eae6 485 *
cparata 0:13631b50eae6 486 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 487 * @param val change the values of drdy in reg STATUS
cparata 0:13631b50eae6 488 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 489 *
cparata 0:13631b50eae6 490 */
cparata 0:13631b50eae6 491 int32_t iis2dlpc_flag_data_ready_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 492 {
cparata 0:13631b50eae6 493 iis2dlpc_status_t reg;
cparata 0:13631b50eae6 494 int32_t ret;
cparata 0:13631b50eae6 495
cparata 0:13631b50eae6 496 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 497 *val = reg.drdy;
cparata 0:13631b50eae6 498
cparata 0:13631b50eae6 499 return ret;
cparata 0:13631b50eae6 500 }
cparata 0:13631b50eae6 501 /**
cparata 0:13631b50eae6 502 * @brief Read all the interrupt/status flag of the device.[get]
cparata 0:13631b50eae6 503 *
cparata 0:13631b50eae6 504 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 505 * @param val registers STATUS_DUP, WAKE_UP_SRC,
cparata 0:13631b50eae6 506 * TAP_SRC, SIXD_SRC, ALL_INT_SRC
cparata 0:13631b50eae6 507 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 508 *
cparata 0:13631b50eae6 509 */
cparata 0:13631b50eae6 510 int32_t iis2dlpc_all_sources_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 511 iis2dlpc_all_sources_t *val)
cparata 0:13631b50eae6 512 {
cparata 0:13631b50eae6 513 int32_t ret;
cparata 0:13631b50eae6 514 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS_DUP, (uint8_t*) val, 5);
cparata 0:13631b50eae6 515 return ret;
cparata 0:13631b50eae6 516 }
cparata 0:13631b50eae6 517
cparata 0:13631b50eae6 518 /**
cparata 0:13631b50eae6 519 * @brief Accelerometer X-axis user offset correction expressed in two’s
cparata 0:13631b50eae6 520 * complement, weight depends on bit USR_OFF_W. The value must be
cparata 0:13631b50eae6 521 * in the range [-127 127].[set]
cparata 0:13631b50eae6 522 *
cparata 0:13631b50eae6 523 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 524 * @param buff buffer that contains data to write
cparata 0:13631b50eae6 525 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 526 *
cparata 0:13631b50eae6 527 */
cparata 0:13631b50eae6 528 int32_t iis2dlpc_usr_offset_x_set(iis2dlpc_ctx_t *ctx, uint8_t *buff)
cparata 0:13631b50eae6 529 {
cparata 0:13631b50eae6 530 int32_t ret;
cparata 0:13631b50eae6 531 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1);
cparata 0:13631b50eae6 532 return ret;
cparata 0:13631b50eae6 533 }
cparata 0:13631b50eae6 534
cparata 0:13631b50eae6 535 /**
cparata 0:13631b50eae6 536 * @brief Accelerometer X-axis user offset correction expressed in two’s
cparata 0:13631b50eae6 537 * complement, weight depends on bit USR_OFF_W. The value must be
cparata 0:13631b50eae6 538 * in the range [-127 127].[get]
cparata 0:13631b50eae6 539 *
cparata 0:13631b50eae6 540 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 541 * @param buff buffer that stores data read
cparata 0:13631b50eae6 542 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 543 *
cparata 0:13631b50eae6 544 */
cparata 0:13631b50eae6 545 int32_t iis2dlpc_usr_offset_x_get(iis2dlpc_ctx_t *ctx, uint8_t *buff)
cparata 0:13631b50eae6 546 {
cparata 0:13631b50eae6 547 int32_t ret;
cparata 0:13631b50eae6 548 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1);
cparata 0:13631b50eae6 549 return ret;
cparata 0:13631b50eae6 550 }
cparata 0:13631b50eae6 551
cparata 0:13631b50eae6 552 /**
cparata 0:13631b50eae6 553 * @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata 0:13631b50eae6 554 * complement, weight depends on bit USR_OFF_W. The value must be
cparata 0:13631b50eae6 555 * in the range [-127 127].[set]
cparata 0:13631b50eae6 556 *
cparata 0:13631b50eae6 557 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 558 * @param buff buffer that contains data to write
cparata 0:13631b50eae6 559 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 560 *
cparata 0:13631b50eae6 561 */
cparata 0:13631b50eae6 562 int32_t iis2dlpc_usr_offset_y_set(iis2dlpc_ctx_t *ctx, uint8_t *buff)
cparata 0:13631b50eae6 563 {
cparata 0:13631b50eae6 564 int32_t ret;
cparata 0:13631b50eae6 565 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1);
cparata 0:13631b50eae6 566 return ret;
cparata 0:13631b50eae6 567 }
cparata 0:13631b50eae6 568
cparata 0:13631b50eae6 569 /**
cparata 0:13631b50eae6 570 * @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata 0:13631b50eae6 571 * complement, weight depends on bit USR_OFF_W. The value must be
cparata 0:13631b50eae6 572 * in the range [-127 127].[get]
cparata 0:13631b50eae6 573 *
cparata 0:13631b50eae6 574 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 575 * @param buff buffer that stores data read
cparata 0:13631b50eae6 576 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 577 *
cparata 0:13631b50eae6 578 */
cparata 0:13631b50eae6 579 int32_t iis2dlpc_usr_offset_y_get(iis2dlpc_ctx_t *ctx, uint8_t *buff)
cparata 0:13631b50eae6 580 {
cparata 0:13631b50eae6 581 int32_t ret;
cparata 0:13631b50eae6 582 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1);
cparata 0:13631b50eae6 583 return ret;
cparata 0:13631b50eae6 584 }
cparata 0:13631b50eae6 585
cparata 0:13631b50eae6 586 /**
cparata 0:13631b50eae6 587 * @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata 0:13631b50eae6 588 * complement, weight depends on bit USR_OFF_W. The value must be
cparata 0:13631b50eae6 589 * in the range [-127 127].[set]
cparata 0:13631b50eae6 590 *
cparata 0:13631b50eae6 591 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 592 * @param buff buffer that contains data to write
cparata 0:13631b50eae6 593 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 594 *
cparata 0:13631b50eae6 595 */
cparata 0:13631b50eae6 596 int32_t iis2dlpc_usr_offset_z_set(iis2dlpc_ctx_t *ctx, uint8_t *buff)
cparata 0:13631b50eae6 597 {
cparata 0:13631b50eae6 598 int32_t ret;
cparata 0:13631b50eae6 599 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1);
cparata 0:13631b50eae6 600 return ret;
cparata 0:13631b50eae6 601 }
cparata 0:13631b50eae6 602
cparata 0:13631b50eae6 603 /**
cparata 0:13631b50eae6 604 * @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata 0:13631b50eae6 605 * complement, weight depends on bit USR_OFF_W. The value must be
cparata 0:13631b50eae6 606 * in the range [-127 127].[get]
cparata 0:13631b50eae6 607 *
cparata 0:13631b50eae6 608 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 609 * @param buff buffer that stores data read
cparata 0:13631b50eae6 610 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 611 *
cparata 0:13631b50eae6 612 */
cparata 0:13631b50eae6 613 int32_t iis2dlpc_usr_offset_z_get(iis2dlpc_ctx_t *ctx, uint8_t *buff)
cparata 0:13631b50eae6 614 {
cparata 0:13631b50eae6 615 int32_t ret;
cparata 0:13631b50eae6 616 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1);
cparata 0:13631b50eae6 617 return ret;
cparata 0:13631b50eae6 618 }
cparata 0:13631b50eae6 619
cparata 0:13631b50eae6 620 /**
cparata 0:13631b50eae6 621 * @brief Weight of XL user offset bits of registers X_OFS_USR,
cparata 0:13631b50eae6 622 * Y_OFS_USR, Z_OFS_USR.[set]
cparata 0:13631b50eae6 623 *
cparata 0:13631b50eae6 624 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 625 * @param val change the values of usr_off_w in
cparata 0:13631b50eae6 626 * reg CTRL_REG7
cparata 0:13631b50eae6 627 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 628 *
cparata 0:13631b50eae6 629 */
cparata 0:13631b50eae6 630 int32_t iis2dlpc_offset_weight_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 631 iis2dlpc_usr_off_w_t val)
cparata 0:13631b50eae6 632 {
cparata 0:13631b50eae6 633 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 634 int32_t ret;
cparata 0:13631b50eae6 635
cparata 0:13631b50eae6 636 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 637 if (ret == 0) {
cparata 0:13631b50eae6 638 reg.usr_off_w = (uint8_t) val;
cparata 0:13631b50eae6 639 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 640 }
cparata 0:13631b50eae6 641 return ret;
cparata 0:13631b50eae6 642 }
cparata 0:13631b50eae6 643
cparata 0:13631b50eae6 644 /**
cparata 0:13631b50eae6 645 * @brief Weight of XL user offset bits of registers X_OFS_USR,
cparata 0:13631b50eae6 646 * Y_OFS_USR, Z_OFS_USR.[get]
cparata 0:13631b50eae6 647 *
cparata 0:13631b50eae6 648 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 649 * @param val Get the values of usr_off_w in reg CTRL_REG7
cparata 0:13631b50eae6 650 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 651 *
cparata 0:13631b50eae6 652 */
cparata 0:13631b50eae6 653 int32_t iis2dlpc_offset_weight_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 654 iis2dlpc_usr_off_w_t *val)
cparata 0:13631b50eae6 655 {
cparata 0:13631b50eae6 656 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 657 int32_t ret;
cparata 0:13631b50eae6 658
cparata 0:13631b50eae6 659 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 660 switch (reg.usr_off_w) {
cparata 0:13631b50eae6 661 case IIS2DLPC_LSb_977ug:
cparata 0:13631b50eae6 662 *val = IIS2DLPC_LSb_977ug;
cparata 0:13631b50eae6 663 break;
cparata 0:13631b50eae6 664 case IIS2DLPC_LSb_15mg6:
cparata 0:13631b50eae6 665 *val = IIS2DLPC_LSb_15mg6;
cparata 0:13631b50eae6 666 break;
cparata 0:13631b50eae6 667 default:
cparata 0:13631b50eae6 668 *val = IIS2DLPC_LSb_977ug;
cparata 0:13631b50eae6 669 break;
cparata 0:13631b50eae6 670 }
cparata 0:13631b50eae6 671 return ret;
cparata 0:13631b50eae6 672 }
cparata 0:13631b50eae6 673
cparata 0:13631b50eae6 674 /**
cparata 0:13631b50eae6 675 * @}
cparata 0:13631b50eae6 676 *
cparata 0:13631b50eae6 677 */
cparata 0:13631b50eae6 678
cparata 0:13631b50eae6 679 /**
cparata 0:13631b50eae6 680 * @defgroup IIS2DLPC_Data_Output
cparata 0:13631b50eae6 681 * @brief This section groups all the data output functions.
cparata 0:13631b50eae6 682 * @{
cparata 0:13631b50eae6 683 *
cparata 0:13631b50eae6 684 */
cparata 0:13631b50eae6 685
cparata 0:13631b50eae6 686 /**
cparata 0:13631b50eae6 687 * @brief Temperature data output register (r). L and H registers
cparata 0:13631b50eae6 688 * together express a 16-bit word in two’s complement.[get]
cparata 0:13631b50eae6 689 *
cparata 0:13631b50eae6 690 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 691 * @param buff buffer that stores data read
cparata 0:13631b50eae6 692 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 693 *
cparata 0:13631b50eae6 694 */
cparata 0:13631b50eae6 695 int32_t iis2dlpc_temperature_raw_get(iis2dlpc_ctx_t *ctx, uint8_t *buff)
cparata 0:13631b50eae6 696 {
cparata 0:13631b50eae6 697 int32_t ret;
cparata 0:13631b50eae6 698 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_T_L, buff, 2);
cparata 0:13631b50eae6 699 return ret;
cparata 0:13631b50eae6 700 }
cparata 0:13631b50eae6 701
cparata 0:13631b50eae6 702 /**
cparata 0:13631b50eae6 703 * @brief Linear acceleration output register. The value is expressed as
cparata 0:13631b50eae6 704 * a 16-bit word in two’s complement.[get]
cparata 0:13631b50eae6 705 *
cparata 0:13631b50eae6 706 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 707 * @param buff buffer that stores data read
cparata 0:13631b50eae6 708 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 709 *
cparata 0:13631b50eae6 710 */
cparata 0:13631b50eae6 711 int32_t iis2dlpc_acceleration_raw_get(iis2dlpc_ctx_t *ctx, uint8_t *buff)
cparata 0:13631b50eae6 712 {
cparata 0:13631b50eae6 713 int32_t ret;
cparata 0:13631b50eae6 714 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_X_L, buff, 6);
cparata 0:13631b50eae6 715 return ret;
cparata 0:13631b50eae6 716 }
cparata 0:13631b50eae6 717
cparata 0:13631b50eae6 718 /**
cparata 0:13631b50eae6 719 * @}
cparata 0:13631b50eae6 720 *
cparata 0:13631b50eae6 721 */
cparata 0:13631b50eae6 722
cparata 0:13631b50eae6 723 /**
cparata 0:13631b50eae6 724 * @defgroup IIS2DLPC_Common
cparata 0:13631b50eae6 725 * @brief This section groups common useful functions.
cparata 0:13631b50eae6 726 * @{
cparata 0:13631b50eae6 727 *
cparata 0:13631b50eae6 728 */
cparata 0:13631b50eae6 729
cparata 0:13631b50eae6 730 /**
cparata 0:13631b50eae6 731 * @brief Device Who am I.[get]
cparata 0:13631b50eae6 732 *
cparata 0:13631b50eae6 733 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 734 * @param buff buffer that stores data read
cparata 0:13631b50eae6 735 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 736 *
cparata 0:13631b50eae6 737 */
cparata 0:13631b50eae6 738 int32_t iis2dlpc_device_id_get(iis2dlpc_ctx_t *ctx, uint8_t *buff)
cparata 0:13631b50eae6 739 {
cparata 0:13631b50eae6 740 int32_t ret;
cparata 0:13631b50eae6 741 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WHO_AM_I, buff, 1);
cparata 0:13631b50eae6 742 return ret;
cparata 0:13631b50eae6 743 }
cparata 0:13631b50eae6 744
cparata 0:13631b50eae6 745 /**
cparata 0:13631b50eae6 746 * @brief Register address automatically incremented during multiple byte
cparata 0:13631b50eae6 747 * access with a serial interface.[set]
cparata 0:13631b50eae6 748 *
cparata 0:13631b50eae6 749 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 750 * @param val change the values of if_add_inc in reg CTRL2
cparata 0:13631b50eae6 751 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 752 *
cparata 0:13631b50eae6 753 */
cparata 0:13631b50eae6 754 int32_t iis2dlpc_auto_increment_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 755 {
cparata 0:13631b50eae6 756 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 757 int32_t ret;
cparata 0:13631b50eae6 758
cparata 0:13631b50eae6 759 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 760 if (ret == 0) {
cparata 0:13631b50eae6 761 reg.if_add_inc = val;
cparata 0:13631b50eae6 762 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 763 }
cparata 0:13631b50eae6 764 return ret;
cparata 0:13631b50eae6 765 }
cparata 0:13631b50eae6 766
cparata 0:13631b50eae6 767 /**
cparata 0:13631b50eae6 768 * @brief Register address automatically incremented during multiple
cparata 0:13631b50eae6 769 * byte access with a serial interface.[get]
cparata 0:13631b50eae6 770 *
cparata 0:13631b50eae6 771 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 772 * @param val change the values of if_add_inc in reg CTRL2
cparata 0:13631b50eae6 773 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 774 *
cparata 0:13631b50eae6 775 */
cparata 0:13631b50eae6 776 int32_t iis2dlpc_auto_increment_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 777 {
cparata 0:13631b50eae6 778 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 779 int32_t ret;
cparata 0:13631b50eae6 780
cparata 0:13631b50eae6 781 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 782 *val = reg.if_add_inc;
cparata 0:13631b50eae6 783
cparata 0:13631b50eae6 784 return ret;
cparata 0:13631b50eae6 785 }
cparata 0:13631b50eae6 786
cparata 0:13631b50eae6 787 /**
cparata 0:13631b50eae6 788 * @brief Software reset. Restore the default values in user registers.[set]
cparata 0:13631b50eae6 789 *
cparata 0:13631b50eae6 790 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 791 * @param val change the values of soft_reset in reg CTRL2
cparata 0:13631b50eae6 792 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 793 *
cparata 0:13631b50eae6 794 */
cparata 0:13631b50eae6 795 int32_t iis2dlpc_reset_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 796 {
cparata 0:13631b50eae6 797 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 798 int32_t ret;
cparata 0:13631b50eae6 799
cparata 0:13631b50eae6 800 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 801 if (ret == 0) {
cparata 0:13631b50eae6 802 reg.soft_reset = val;
cparata 0:13631b50eae6 803 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 804 }
cparata 0:13631b50eae6 805
cparata 0:13631b50eae6 806 return ret;
cparata 0:13631b50eae6 807 }
cparata 0:13631b50eae6 808
cparata 0:13631b50eae6 809 /**
cparata 0:13631b50eae6 810 * @brief Software reset. Restore the default values in user registers.[get]
cparata 0:13631b50eae6 811 *
cparata 0:13631b50eae6 812 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 813 * @param val change the values of soft_reset in reg CTRL2
cparata 0:13631b50eae6 814 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 815 *
cparata 0:13631b50eae6 816 */
cparata 0:13631b50eae6 817 int32_t iis2dlpc_reset_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 818 {
cparata 0:13631b50eae6 819 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 820 int32_t ret;
cparata 0:13631b50eae6 821
cparata 0:13631b50eae6 822 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 823 *val = reg.soft_reset;
cparata 0:13631b50eae6 824
cparata 0:13631b50eae6 825 return ret;
cparata 0:13631b50eae6 826 }
cparata 0:13631b50eae6 827
cparata 0:13631b50eae6 828 /**
cparata 0:13631b50eae6 829 * @brief Reboot memory content. Reload the calibration parameters.[set]
cparata 0:13631b50eae6 830 *
cparata 0:13631b50eae6 831 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 832 * @param val change the values of boot in reg CTRL2
cparata 0:13631b50eae6 833 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 834 *
cparata 0:13631b50eae6 835 */
cparata 0:13631b50eae6 836 int32_t iis2dlpc_boot_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 837 {
cparata 0:13631b50eae6 838 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 839 int32_t ret;
cparata 0:13631b50eae6 840
cparata 0:13631b50eae6 841 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 842 if (ret == 0) {
cparata 0:13631b50eae6 843 reg.boot = val;
cparata 0:13631b50eae6 844 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 845 }
cparata 0:13631b50eae6 846 return ret;
cparata 0:13631b50eae6 847 }
cparata 0:13631b50eae6 848
cparata 0:13631b50eae6 849 /**
cparata 0:13631b50eae6 850 * @brief Reboot memory content. Reload the calibration parameters.[get]
cparata 0:13631b50eae6 851 *
cparata 0:13631b50eae6 852 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 853 * @param val change the values of boot in reg CTRL2
cparata 0:13631b50eae6 854 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 855 *
cparata 0:13631b50eae6 856 */
cparata 0:13631b50eae6 857 int32_t iis2dlpc_boot_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 858 {
cparata 0:13631b50eae6 859 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 860 int32_t ret;
cparata 0:13631b50eae6 861
cparata 0:13631b50eae6 862 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 863 *val = reg.boot;
cparata 0:13631b50eae6 864
cparata 0:13631b50eae6 865 return ret;
cparata 0:13631b50eae6 866 }
cparata 0:13631b50eae6 867
cparata 0:13631b50eae6 868 /**
cparata 0:13631b50eae6 869 * @brief Sensor self-test enable.[set]
cparata 0:13631b50eae6 870 *
cparata 0:13631b50eae6 871 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 872 * @param val change the values of st in reg CTRL3
cparata 0:13631b50eae6 873 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 874 *
cparata 0:13631b50eae6 875 */
cparata 0:13631b50eae6 876 int32_t iis2dlpc_self_test_set(iis2dlpc_ctx_t *ctx, iis2dlpc_st_t val)
cparata 0:13631b50eae6 877 {
cparata 0:13631b50eae6 878 iis2dlpc_ctrl3_t reg;
cparata 0:13631b50eae6 879 int32_t ret;
cparata 0:13631b50eae6 880
cparata 0:13631b50eae6 881 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 882 if (ret == 0) {
cparata 0:13631b50eae6 883 reg.st = (uint8_t) val;
cparata 0:13631b50eae6 884 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 885 }
cparata 0:13631b50eae6 886
cparata 0:13631b50eae6 887 return ret;
cparata 0:13631b50eae6 888 }
cparata 0:13631b50eae6 889
cparata 0:13631b50eae6 890 /**
cparata 0:13631b50eae6 891 * @brief Sensor self-test enable.[get]
cparata 0:13631b50eae6 892 *
cparata 0:13631b50eae6 893 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 894 * @param val Get the values of st in reg CTRL3
cparata 0:13631b50eae6 895 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 896 *
cparata 0:13631b50eae6 897 */
cparata 0:13631b50eae6 898 int32_t iis2dlpc_self_test_get(iis2dlpc_ctx_t *ctx, iis2dlpc_st_t *val)
cparata 0:13631b50eae6 899 {
cparata 0:13631b50eae6 900 iis2dlpc_ctrl3_t reg;
cparata 0:13631b50eae6 901 int32_t ret;
cparata 0:13631b50eae6 902
cparata 0:13631b50eae6 903 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 904
cparata 0:13631b50eae6 905 switch (reg.st) {
cparata 0:13631b50eae6 906 case IIS2DLPC_XL_ST_DISABLE:
cparata 0:13631b50eae6 907 *val = IIS2DLPC_XL_ST_DISABLE;
cparata 0:13631b50eae6 908 break;
cparata 0:13631b50eae6 909 case IIS2DLPC_XL_ST_POSITIVE:
cparata 0:13631b50eae6 910 *val = IIS2DLPC_XL_ST_POSITIVE;
cparata 0:13631b50eae6 911 break;
cparata 0:13631b50eae6 912 case IIS2DLPC_XL_ST_NEGATIVE:
cparata 0:13631b50eae6 913 *val = IIS2DLPC_XL_ST_NEGATIVE;
cparata 0:13631b50eae6 914 break;
cparata 0:13631b50eae6 915 default:
cparata 0:13631b50eae6 916 *val = IIS2DLPC_XL_ST_DISABLE;
cparata 0:13631b50eae6 917 break;
cparata 0:13631b50eae6 918 }
cparata 0:13631b50eae6 919 return ret;
cparata 0:13631b50eae6 920 }
cparata 0:13631b50eae6 921
cparata 0:13631b50eae6 922 /**
cparata 0:13631b50eae6 923 * @brief Data-ready pulsed / letched mode.[set]
cparata 0:13631b50eae6 924 *
cparata 0:13631b50eae6 925 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 926 * @param val change the values of drdy_pulsed in reg CTRL_REG7
cparata 0:13631b50eae6 927 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 928 *
cparata 0:13631b50eae6 929 */
cparata 0:13631b50eae6 930 int32_t iis2dlpc_data_ready_mode_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 931 iis2dlpc_drdy_pulsed_t val)
cparata 0:13631b50eae6 932 {
cparata 0:13631b50eae6 933 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 934 int32_t ret;
cparata 0:13631b50eae6 935
cparata 0:13631b50eae6 936 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 937 if (ret == 0) {
cparata 0:13631b50eae6 938 reg.drdy_pulsed = (uint8_t) val;
cparata 0:13631b50eae6 939 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 940 }
cparata 0:13631b50eae6 941
cparata 0:13631b50eae6 942 return ret;
cparata 0:13631b50eae6 943 }
cparata 0:13631b50eae6 944
cparata 0:13631b50eae6 945 /**
cparata 0:13631b50eae6 946 * @brief Data-ready pulsed / letched mode.[get]
cparata 0:13631b50eae6 947 *
cparata 0:13631b50eae6 948 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 949 * @param val Get the values of drdy_pulsed in reg CTRL_REG7
cparata 0:13631b50eae6 950 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 951 *
cparata 0:13631b50eae6 952 */
cparata 0:13631b50eae6 953 int32_t iis2dlpc_data_ready_mode_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 954 iis2dlpc_drdy_pulsed_t *val)
cparata 0:13631b50eae6 955 {
cparata 0:13631b50eae6 956 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 957 int32_t ret;
cparata 0:13631b50eae6 958
cparata 0:13631b50eae6 959 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 960
cparata 0:13631b50eae6 961 switch (reg.drdy_pulsed) {
cparata 0:13631b50eae6 962 case IIS2DLPC_DRDY_LATCHED:
cparata 0:13631b50eae6 963 *val = IIS2DLPC_DRDY_LATCHED;
cparata 0:13631b50eae6 964 break;
cparata 0:13631b50eae6 965 case IIS2DLPC_DRDY_PULSED:
cparata 0:13631b50eae6 966 *val = IIS2DLPC_DRDY_PULSED;
cparata 0:13631b50eae6 967 break;
cparata 0:13631b50eae6 968 default:
cparata 0:13631b50eae6 969 *val = IIS2DLPC_DRDY_LATCHED;
cparata 0:13631b50eae6 970 break;
cparata 0:13631b50eae6 971 }
cparata 0:13631b50eae6 972 return ret;
cparata 0:13631b50eae6 973 }
cparata 0:13631b50eae6 974
cparata 0:13631b50eae6 975 /**
cparata 0:13631b50eae6 976 * @}
cparata 0:13631b50eae6 977 *
cparata 0:13631b50eae6 978 */
cparata 0:13631b50eae6 979
cparata 0:13631b50eae6 980 /**
cparata 0:13631b50eae6 981 * @defgroup IIS2DLPC_Filters
cparata 0:13631b50eae6 982 * @brief This section group all the functions concerning the filters
cparata 0:13631b50eae6 983 * configuration.
cparata 0:13631b50eae6 984 * @{
cparata 0:13631b50eae6 985 *
cparata 0:13631b50eae6 986 */
cparata 0:13631b50eae6 987
cparata 0:13631b50eae6 988 /**
cparata 0:13631b50eae6 989 * @brief Accelerometer filtering path for outputs.[set]
cparata 0:13631b50eae6 990 *
cparata 0:13631b50eae6 991 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 992 * @param val change the values of fds in reg CTRL6
cparata 0:13631b50eae6 993 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 994 *
cparata 0:13631b50eae6 995 */
cparata 0:13631b50eae6 996 int32_t iis2dlpc_filter_path_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fds_t val)
cparata 0:13631b50eae6 997 {
cparata 0:13631b50eae6 998 iis2dlpc_ctrl6_t ctrl6;
cparata 0:13631b50eae6 999 iis2dlpc_ctrl_reg7_t ctrl_reg7;
cparata 0:13631b50eae6 1000 int32_t ret;
cparata 0:13631b50eae6 1001
cparata 0:13631b50eae6 1002 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata 0:13631b50eae6 1003 if (ret == 0) {
cparata 0:13631b50eae6 1004 ctrl6.fds = ( (uint8_t) val & 0x10U ) >> 4;
cparata 0:13631b50eae6 1005 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata 0:13631b50eae6 1006 }
cparata 0:13631b50eae6 1007 if (ret == 0) {
cparata 0:13631b50eae6 1008 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
cparata 0:13631b50eae6 1009 }
cparata 0:13631b50eae6 1010 if (ret == 0) {
cparata 0:13631b50eae6 1011 ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
cparata 0:13631b50eae6 1012 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
cparata 0:13631b50eae6 1013 } else {
cparata 0:13631b50eae6 1014 ret = ret;
cparata 0:13631b50eae6 1015 }
cparata 0:13631b50eae6 1016 return ret;
cparata 0:13631b50eae6 1017 }
cparata 0:13631b50eae6 1018
cparata 0:13631b50eae6 1019 /**
cparata 0:13631b50eae6 1020 * @brief Accelerometer filtering path for outputs.[get]
cparata 0:13631b50eae6 1021 *
cparata 0:13631b50eae6 1022 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1023 * @param val Get the values of fds in reg CTRL6
cparata 0:13631b50eae6 1024 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1025 *
cparata 0:13631b50eae6 1026 */
cparata 0:13631b50eae6 1027 int32_t iis2dlpc_filter_path_get(iis2dlpc_ctx_t *ctx, iis2dlpc_fds_t *val)
cparata 0:13631b50eae6 1028 {
cparata 0:13631b50eae6 1029 iis2dlpc_ctrl6_t ctrl6;
cparata 0:13631b50eae6 1030 iis2dlpc_ctrl_reg7_t ctrl_reg7;
cparata 0:13631b50eae6 1031 int32_t ret;
cparata 0:13631b50eae6 1032
cparata 0:13631b50eae6 1033 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata 0:13631b50eae6 1034 if (ret == 0) {
cparata 0:13631b50eae6 1035 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
cparata 0:13631b50eae6 1036
cparata 0:13631b50eae6 1037 switch ((ctrl6.fds << 4 ) + ctrl_reg7.usr_off_on_out) {
cparata 0:13631b50eae6 1038 case IIS2DLPC_LPF_ON_OUT:
cparata 0:13631b50eae6 1039 *val = IIS2DLPC_LPF_ON_OUT;
cparata 0:13631b50eae6 1040 break;
cparata 0:13631b50eae6 1041 case IIS2DLPC_USER_OFFSET_ON_OUT:
cparata 0:13631b50eae6 1042 *val = IIS2DLPC_USER_OFFSET_ON_OUT;
cparata 0:13631b50eae6 1043 break;
cparata 0:13631b50eae6 1044 case IIS2DLPC_HIGH_PASS_ON_OUT:
cparata 0:13631b50eae6 1045 *val = IIS2DLPC_HIGH_PASS_ON_OUT;
cparata 0:13631b50eae6 1046 break;
cparata 0:13631b50eae6 1047 default:
cparata 0:13631b50eae6 1048 *val = IIS2DLPC_LPF_ON_OUT;
cparata 0:13631b50eae6 1049 break;
cparata 0:13631b50eae6 1050 }
cparata 0:13631b50eae6 1051 }
cparata 0:13631b50eae6 1052 return ret;
cparata 0:13631b50eae6 1053 }
cparata 0:13631b50eae6 1054
cparata 0:13631b50eae6 1055 /**
cparata 0:13631b50eae6 1056 * @brief Accelerometer cutoff filter frequency. Valid for low and high
cparata 0:13631b50eae6 1057 * pass filter.[set]
cparata 0:13631b50eae6 1058 *
cparata 0:13631b50eae6 1059 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1060 * @param val change the values of bw_filt in reg CTRL6
cparata 0:13631b50eae6 1061 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1062 *
cparata 0:13631b50eae6 1063 */
cparata 0:13631b50eae6 1064 int32_t iis2dlpc_filter_bandwidth_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1065 iis2dlpc_bw_filt_t val)
cparata 0:13631b50eae6 1066 {
cparata 0:13631b50eae6 1067 iis2dlpc_ctrl6_t reg;
cparata 0:13631b50eae6 1068 int32_t ret;
cparata 0:13631b50eae6 1069
cparata 0:13631b50eae6 1070 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1071 if (ret == 0) {
cparata 0:13631b50eae6 1072 reg.bw_filt = (uint8_t) val;
cparata 0:13631b50eae6 1073 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1074 }
cparata 0:13631b50eae6 1075
cparata 0:13631b50eae6 1076 return ret;
cparata 0:13631b50eae6 1077 }
cparata 0:13631b50eae6 1078
cparata 0:13631b50eae6 1079 /**
cparata 0:13631b50eae6 1080 * @brief Accelerometer cutoff filter frequency. Valid for low and
cparata 0:13631b50eae6 1081 * high pass filter.[get]
cparata 0:13631b50eae6 1082 *
cparata 0:13631b50eae6 1083 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1084 * @param val Get the values of bw_filt in reg CTRL6
cparata 0:13631b50eae6 1085 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1086 *
cparata 0:13631b50eae6 1087 */
cparata 0:13631b50eae6 1088 int32_t iis2dlpc_filter_bandwidth_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1089 iis2dlpc_bw_filt_t *val)
cparata 0:13631b50eae6 1090 {
cparata 0:13631b50eae6 1091 iis2dlpc_ctrl6_t reg;
cparata 0:13631b50eae6 1092 int32_t ret;
cparata 0:13631b50eae6 1093
cparata 0:13631b50eae6 1094 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1095
cparata 0:13631b50eae6 1096 switch (reg.bw_filt) {
cparata 0:13631b50eae6 1097 case IIS2DLPC_ODR_DIV_2:
cparata 0:13631b50eae6 1098 *val = IIS2DLPC_ODR_DIV_2;
cparata 0:13631b50eae6 1099 break;
cparata 0:13631b50eae6 1100 case IIS2DLPC_ODR_DIV_4:
cparata 0:13631b50eae6 1101 *val = IIS2DLPC_ODR_DIV_4;
cparata 0:13631b50eae6 1102 break;
cparata 0:13631b50eae6 1103 case IIS2DLPC_ODR_DIV_10:
cparata 0:13631b50eae6 1104 *val = IIS2DLPC_ODR_DIV_10;
cparata 0:13631b50eae6 1105 break;
cparata 0:13631b50eae6 1106 case IIS2DLPC_ODR_DIV_20:
cparata 0:13631b50eae6 1107 *val = IIS2DLPC_ODR_DIV_20;
cparata 0:13631b50eae6 1108 break;
cparata 0:13631b50eae6 1109 default:
cparata 0:13631b50eae6 1110 *val = IIS2DLPC_ODR_DIV_2;
cparata 0:13631b50eae6 1111 break;
cparata 0:13631b50eae6 1112 }
cparata 0:13631b50eae6 1113 return ret;
cparata 0:13631b50eae6 1114 }
cparata 0:13631b50eae6 1115
cparata 0:13631b50eae6 1116 /**
cparata 0:13631b50eae6 1117 * @brief Enable HP filter reference mode.[set]
cparata 0:13631b50eae6 1118 *
cparata 0:13631b50eae6 1119 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1120 * @param val change the values of hp_ref_mode in reg CTRL_REG7
cparata 0:13631b50eae6 1121 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1122 *
cparata 0:13631b50eae6 1123 */
cparata 0:13631b50eae6 1124 int32_t iis2dlpc_reference_mode_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 1125 {
cparata 0:13631b50eae6 1126 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 1127 int32_t ret;
cparata 0:13631b50eae6 1128
cparata 0:13631b50eae6 1129 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1130 if (ret == 0) {
cparata 0:13631b50eae6 1131 reg.hp_ref_mode = val;
cparata 0:13631b50eae6 1132 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1133 }
cparata 0:13631b50eae6 1134 return ret;
cparata 0:13631b50eae6 1135 }
cparata 0:13631b50eae6 1136
cparata 0:13631b50eae6 1137 /**
cparata 0:13631b50eae6 1138 * @brief Enable HP filter reference mode.[get]
cparata 0:13631b50eae6 1139 *
cparata 0:13631b50eae6 1140 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1141 * @param val change the values of hp_ref_mode in reg CTRL_REG7
cparata 0:13631b50eae6 1142 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1143 *
cparata 0:13631b50eae6 1144 */
cparata 0:13631b50eae6 1145 int32_t iis2dlpc_reference_mode_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 1146 {
cparata 0:13631b50eae6 1147 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 1148 int32_t ret;
cparata 0:13631b50eae6 1149
cparata 0:13631b50eae6 1150 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1151 *val = reg.hp_ref_mode;
cparata 0:13631b50eae6 1152
cparata 0:13631b50eae6 1153 return ret;
cparata 0:13631b50eae6 1154 }
cparata 0:13631b50eae6 1155
cparata 0:13631b50eae6 1156 /**
cparata 0:13631b50eae6 1157 * @}
cparata 0:13631b50eae6 1158 *
cparata 0:13631b50eae6 1159 */
cparata 0:13631b50eae6 1160
cparata 0:13631b50eae6 1161 /**
cparata 0:13631b50eae6 1162 * @defgroup IIS2DLPC_Serial_Interface
cparata 0:13631b50eae6 1163 * @brief This section groups all the functions concerning main serial
cparata 0:13631b50eae6 1164 * interface management (not auxiliary)
cparata 0:13631b50eae6 1165 * @{
cparata 0:13631b50eae6 1166 *
cparata 0:13631b50eae6 1167 */
cparata 0:13631b50eae6 1168
cparata 0:13631b50eae6 1169 /**
cparata 0:13631b50eae6 1170 * @brief SPI Serial Interface Mode selection.[set]
cparata 0:13631b50eae6 1171 *
cparata 0:13631b50eae6 1172 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1173 * @param val change the values of sim in reg CTRL2
cparata 0:13631b50eae6 1174 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1175 *
cparata 0:13631b50eae6 1176 */
cparata 0:13631b50eae6 1177 int32_t iis2dlpc_spi_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_sim_t val)
cparata 0:13631b50eae6 1178 {
cparata 0:13631b50eae6 1179 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 1180 int32_t ret;
cparata 0:13631b50eae6 1181
cparata 0:13631b50eae6 1182 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1183 if (ret == 0) {
cparata 0:13631b50eae6 1184 reg.sim = (uint8_t) val;
cparata 0:13631b50eae6 1185 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1186 }
cparata 0:13631b50eae6 1187 return ret;
cparata 0:13631b50eae6 1188 }
cparata 0:13631b50eae6 1189
cparata 0:13631b50eae6 1190 /**
cparata 0:13631b50eae6 1191 * @brief SPI Serial Interface Mode selection.[get]
cparata 0:13631b50eae6 1192 *
cparata 0:13631b50eae6 1193 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1194 * @param val Get the values of sim in reg CTRL2
cparata 0:13631b50eae6 1195 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1196 *
cparata 0:13631b50eae6 1197 */
cparata 0:13631b50eae6 1198 int32_t iis2dlpc_spi_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_sim_t *val)
cparata 0:13631b50eae6 1199 {
cparata 0:13631b50eae6 1200 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 1201 int32_t ret;
cparata 0:13631b50eae6 1202
cparata 0:13631b50eae6 1203 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1204
cparata 0:13631b50eae6 1205 switch (reg.sim) {
cparata 0:13631b50eae6 1206 case IIS2DLPC_SPI_4_WIRE:
cparata 0:13631b50eae6 1207 *val = IIS2DLPC_SPI_4_WIRE;
cparata 0:13631b50eae6 1208 break;
cparata 0:13631b50eae6 1209 case IIS2DLPC_SPI_3_WIRE:
cparata 0:13631b50eae6 1210 *val = IIS2DLPC_SPI_3_WIRE;
cparata 0:13631b50eae6 1211 break;
cparata 0:13631b50eae6 1212 default:
cparata 0:13631b50eae6 1213 *val = IIS2DLPC_SPI_4_WIRE;
cparata 0:13631b50eae6 1214 break;
cparata 0:13631b50eae6 1215 }
cparata 0:13631b50eae6 1216 return ret;
cparata 0:13631b50eae6 1217 }
cparata 0:13631b50eae6 1218
cparata 0:13631b50eae6 1219 /**
cparata 0:13631b50eae6 1220 * @brief Disable / Enable I2C interface.[set]
cparata 0:13631b50eae6 1221 *
cparata 0:13631b50eae6 1222 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1223 * @param val change the values of i2c_disable in
cparata 0:13631b50eae6 1224 * reg CTRL2
cparata 0:13631b50eae6 1225 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1226 *
cparata 0:13631b50eae6 1227 */
cparata 0:13631b50eae6 1228 int32_t iis2dlpc_i2c_interface_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1229 iis2dlpc_i2c_disable_t val)
cparata 0:13631b50eae6 1230 {
cparata 0:13631b50eae6 1231 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 1232 int32_t ret;
cparata 0:13631b50eae6 1233
cparata 0:13631b50eae6 1234 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1235 if (ret == 0) {
cparata 0:13631b50eae6 1236 reg.i2c_disable = (uint8_t) val;
cparata 0:13631b50eae6 1237 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1238 }
cparata 0:13631b50eae6 1239 return ret;
cparata 0:13631b50eae6 1240 }
cparata 0:13631b50eae6 1241
cparata 0:13631b50eae6 1242 /**
cparata 0:13631b50eae6 1243 * @brief Disable / Enable I2C interface.[get]
cparata 0:13631b50eae6 1244 *
cparata 0:13631b50eae6 1245 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1246 * @param val Get the values of i2c_disable in reg CTRL2
cparata 0:13631b50eae6 1247 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1248 *
cparata 0:13631b50eae6 1249 */
cparata 0:13631b50eae6 1250 int32_t iis2dlpc_i2c_interface_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1251 iis2dlpc_i2c_disable_t *val)
cparata 0:13631b50eae6 1252 {
cparata 0:13631b50eae6 1253 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 1254 int32_t ret;
cparata 0:13631b50eae6 1255
cparata 0:13631b50eae6 1256 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1257
cparata 0:13631b50eae6 1258 switch (reg.i2c_disable) {
cparata 0:13631b50eae6 1259 case IIS2DLPC_I2C_ENABLE:
cparata 0:13631b50eae6 1260 *val = IIS2DLPC_I2C_ENABLE;
cparata 0:13631b50eae6 1261 break;
cparata 0:13631b50eae6 1262 case IIS2DLPC_I2C_DISABLE:
cparata 0:13631b50eae6 1263 *val = IIS2DLPC_I2C_DISABLE;
cparata 0:13631b50eae6 1264 break;
cparata 0:13631b50eae6 1265 default:
cparata 0:13631b50eae6 1266 *val = IIS2DLPC_I2C_ENABLE;
cparata 0:13631b50eae6 1267 break;
cparata 0:13631b50eae6 1268 }
cparata 0:13631b50eae6 1269 return ret;
cparata 0:13631b50eae6 1270 }
cparata 0:13631b50eae6 1271
cparata 0:13631b50eae6 1272 /**
cparata 0:13631b50eae6 1273 * @brief Disconnect CS pull-up.[set]
cparata 0:13631b50eae6 1274 *
cparata 0:13631b50eae6 1275 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1276 * @param val change the values of cs_pu_disc in reg CTRL2
cparata 0:13631b50eae6 1277 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1278 *
cparata 0:13631b50eae6 1279 */
cparata 0:13631b50eae6 1280 int32_t iis2dlpc_cs_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_cs_pu_disc_t val)
cparata 0:13631b50eae6 1281 {
cparata 0:13631b50eae6 1282 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 1283 int32_t ret;
cparata 0:13631b50eae6 1284
cparata 0:13631b50eae6 1285 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1286 if (ret == 0) {
cparata 0:13631b50eae6 1287 reg.cs_pu_disc = (uint8_t) val;
cparata 0:13631b50eae6 1288 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1289 }
cparata 0:13631b50eae6 1290 return ret;
cparata 0:13631b50eae6 1291 }
cparata 0:13631b50eae6 1292
cparata 0:13631b50eae6 1293 /**
cparata 0:13631b50eae6 1294 * @brief Disconnect CS pull-up.[get]
cparata 0:13631b50eae6 1295 *
cparata 0:13631b50eae6 1296 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1297 * @param val Get the values of cs_pu_disc in reg CTRL2
cparata 0:13631b50eae6 1298 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1299 *
cparata 0:13631b50eae6 1300 */
cparata 0:13631b50eae6 1301 int32_t iis2dlpc_cs_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_cs_pu_disc_t *val)
cparata 0:13631b50eae6 1302 {
cparata 0:13631b50eae6 1303 iis2dlpc_ctrl2_t reg;
cparata 0:13631b50eae6 1304 int32_t ret;
cparata 0:13631b50eae6 1305
cparata 0:13631b50eae6 1306 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1307
cparata 0:13631b50eae6 1308 switch (reg.cs_pu_disc) {
cparata 0:13631b50eae6 1309 case IIS2DLPC_PULL_UP_CONNECT:
cparata 0:13631b50eae6 1310 *val = IIS2DLPC_PULL_UP_CONNECT;
cparata 0:13631b50eae6 1311 break;
cparata 0:13631b50eae6 1312 case IIS2DLPC_PULL_UP_DISCONNECT:
cparata 0:13631b50eae6 1313 *val = IIS2DLPC_PULL_UP_DISCONNECT;
cparata 0:13631b50eae6 1314 break;
cparata 0:13631b50eae6 1315 default:
cparata 0:13631b50eae6 1316 *val = IIS2DLPC_PULL_UP_CONNECT;
cparata 0:13631b50eae6 1317 break;
cparata 0:13631b50eae6 1318 }
cparata 0:13631b50eae6 1319 return ret;
cparata 0:13631b50eae6 1320 }
cparata 0:13631b50eae6 1321
cparata 0:13631b50eae6 1322 /**
cparata 0:13631b50eae6 1323 * @}
cparata 0:13631b50eae6 1324 *
cparata 0:13631b50eae6 1325 */
cparata 0:13631b50eae6 1326
cparata 0:13631b50eae6 1327 /**
cparata 0:13631b50eae6 1328 * @defgroup IIS2DLPC_Interrupt_Pins
cparata 0:13631b50eae6 1329 * @brief This section groups all the functions that manage interrupt pins
cparata 0:13631b50eae6 1330 * @{
cparata 0:13631b50eae6 1331 *
cparata 0:13631b50eae6 1332 */
cparata 0:13631b50eae6 1333
cparata 0:13631b50eae6 1334 /**
cparata 0:13631b50eae6 1335 * @brief Interrupt active-high/low.[set]
cparata 0:13631b50eae6 1336 *
cparata 0:13631b50eae6 1337 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1338 * @param val change the values of h_lactive in reg CTRL3
cparata 0:13631b50eae6 1339 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1340 *
cparata 0:13631b50eae6 1341 */
cparata 0:13631b50eae6 1342 int32_t iis2dlpc_pin_polarity_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1343 iis2dlpc_h_lactive_t val)
cparata 0:13631b50eae6 1344 {
cparata 0:13631b50eae6 1345 iis2dlpc_ctrl3_t reg;
cparata 0:13631b50eae6 1346 int32_t ret;
cparata 0:13631b50eae6 1347
cparata 0:13631b50eae6 1348 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1349 if (ret == 0) {
cparata 0:13631b50eae6 1350 reg.h_lactive = (uint8_t) val;
cparata 0:13631b50eae6 1351 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1352 }
cparata 0:13631b50eae6 1353 return ret;
cparata 0:13631b50eae6 1354 }
cparata 0:13631b50eae6 1355
cparata 0:13631b50eae6 1356 /**
cparata 0:13631b50eae6 1357 * @brief Interrupt active-high/low.[get]
cparata 0:13631b50eae6 1358 *
cparata 0:13631b50eae6 1359 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1360 * @param val Get the values of h_lactive in reg CTRL3
cparata 0:13631b50eae6 1361 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1362 *
cparata 0:13631b50eae6 1363 */
cparata 0:13631b50eae6 1364 int32_t iis2dlpc_pin_polarity_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1365 iis2dlpc_h_lactive_t *val)
cparata 0:13631b50eae6 1366 {
cparata 0:13631b50eae6 1367 iis2dlpc_ctrl3_t reg;
cparata 0:13631b50eae6 1368 int32_t ret;
cparata 0:13631b50eae6 1369
cparata 0:13631b50eae6 1370 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1371
cparata 0:13631b50eae6 1372 switch (reg.h_lactive) {
cparata 0:13631b50eae6 1373 case IIS2DLPC_ACTIVE_HIGH:
cparata 0:13631b50eae6 1374 *val = IIS2DLPC_ACTIVE_HIGH;
cparata 0:13631b50eae6 1375 break;
cparata 0:13631b50eae6 1376 case IIS2DLPC_ACTIVE_LOW:
cparata 0:13631b50eae6 1377 *val = IIS2DLPC_ACTIVE_LOW;
cparata 0:13631b50eae6 1378 break;
cparata 0:13631b50eae6 1379 default:
cparata 0:13631b50eae6 1380 *val = IIS2DLPC_ACTIVE_HIGH;
cparata 0:13631b50eae6 1381 break;
cparata 0:13631b50eae6 1382 }
cparata 0:13631b50eae6 1383 return ret;
cparata 0:13631b50eae6 1384 }
cparata 0:13631b50eae6 1385
cparata 0:13631b50eae6 1386 /**
cparata 0:13631b50eae6 1387 * @brief Latched/pulsed interrupt.[set]
cparata 0:13631b50eae6 1388 *
cparata 0:13631b50eae6 1389 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1390 * @param val change the values of lir in reg CTRL3
cparata 0:13631b50eae6 1391 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1392 *
cparata 0:13631b50eae6 1393 */
cparata 0:13631b50eae6 1394 int32_t iis2dlpc_int_notification_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1395 iis2dlpc_lir_t val)
cparata 0:13631b50eae6 1396 {
cparata 0:13631b50eae6 1397 iis2dlpc_ctrl3_t reg;
cparata 0:13631b50eae6 1398 int32_t ret;
cparata 0:13631b50eae6 1399
cparata 0:13631b50eae6 1400 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1401 if (ret == 0) {
cparata 0:13631b50eae6 1402 reg.lir = (uint8_t) val;
cparata 0:13631b50eae6 1403 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1404 }
cparata 0:13631b50eae6 1405 return ret;
cparata 0:13631b50eae6 1406 }
cparata 0:13631b50eae6 1407
cparata 0:13631b50eae6 1408 /**
cparata 0:13631b50eae6 1409 * @brief Latched/pulsed interrupt.[get]
cparata 0:13631b50eae6 1410 *
cparata 0:13631b50eae6 1411 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1412 * @param val Get the values of lir in reg CTRL3
cparata 0:13631b50eae6 1413 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1414 *
cparata 0:13631b50eae6 1415 */
cparata 0:13631b50eae6 1416 int32_t iis2dlpc_int_notification_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1417 iis2dlpc_lir_t *val)
cparata 0:13631b50eae6 1418 {
cparata 0:13631b50eae6 1419 iis2dlpc_ctrl3_t reg;
cparata 0:13631b50eae6 1420 int32_t ret;
cparata 0:13631b50eae6 1421
cparata 0:13631b50eae6 1422 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1423
cparata 0:13631b50eae6 1424 switch (reg.lir) {
cparata 0:13631b50eae6 1425 case IIS2DLPC_INT_PULSED:
cparata 0:13631b50eae6 1426 *val = IIS2DLPC_INT_PULSED;
cparata 0:13631b50eae6 1427 break;
cparata 0:13631b50eae6 1428 case IIS2DLPC_INT_LATCHED:
cparata 0:13631b50eae6 1429 *val = IIS2DLPC_INT_LATCHED;
cparata 0:13631b50eae6 1430 break;
cparata 0:13631b50eae6 1431 default:
cparata 0:13631b50eae6 1432 *val = IIS2DLPC_INT_PULSED;
cparata 0:13631b50eae6 1433 break;
cparata 0:13631b50eae6 1434 }
cparata 0:13631b50eae6 1435 return ret;
cparata 0:13631b50eae6 1436 }
cparata 0:13631b50eae6 1437
cparata 0:13631b50eae6 1438 /**
cparata 0:13631b50eae6 1439 * @brief Push-pull/open drain selection on interrupt pads.[set]
cparata 0:13631b50eae6 1440 *
cparata 0:13631b50eae6 1441 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1442 * @param val change the values of pp_od in reg CTRL3
cparata 0:13631b50eae6 1443 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1444 *
cparata 0:13631b50eae6 1445 */
cparata 0:13631b50eae6 1446 int32_t iis2dlpc_pin_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_pp_od_t val)
cparata 0:13631b50eae6 1447 {
cparata 0:13631b50eae6 1448 iis2dlpc_ctrl3_t reg;
cparata 0:13631b50eae6 1449 int32_t ret;
cparata 0:13631b50eae6 1450
cparata 0:13631b50eae6 1451 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1452 if (ret == 0) {
cparata 0:13631b50eae6 1453 reg.pp_od = (uint8_t) val;
cparata 0:13631b50eae6 1454 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1455 }
cparata 0:13631b50eae6 1456 return ret;
cparata 0:13631b50eae6 1457 }
cparata 0:13631b50eae6 1458
cparata 0:13631b50eae6 1459 /**
cparata 0:13631b50eae6 1460 * @brief Push-pull/open drain selection on interrupt pads.[get]
cparata 0:13631b50eae6 1461 *
cparata 0:13631b50eae6 1462 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1463 * @param val Get the values of pp_od in reg CTRL3
cparata 0:13631b50eae6 1464 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1465 *
cparata 0:13631b50eae6 1466 */
cparata 0:13631b50eae6 1467 int32_t iis2dlpc_pin_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_pp_od_t *val)
cparata 0:13631b50eae6 1468 {
cparata 0:13631b50eae6 1469 iis2dlpc_ctrl3_t reg;
cparata 0:13631b50eae6 1470 int32_t ret;
cparata 0:13631b50eae6 1471
cparata 0:13631b50eae6 1472 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1473
cparata 0:13631b50eae6 1474 switch (reg.pp_od) {
cparata 0:13631b50eae6 1475 case IIS2DLPC_PUSH_PULL:
cparata 0:13631b50eae6 1476 *val = IIS2DLPC_PUSH_PULL;
cparata 0:13631b50eae6 1477 break;
cparata 0:13631b50eae6 1478 case IIS2DLPC_OPEN_DRAIN:
cparata 0:13631b50eae6 1479 *val = IIS2DLPC_OPEN_DRAIN;
cparata 0:13631b50eae6 1480 break;
cparata 0:13631b50eae6 1481 default:
cparata 0:13631b50eae6 1482 *val = IIS2DLPC_PUSH_PULL;
cparata 0:13631b50eae6 1483 break;
cparata 0:13631b50eae6 1484 }
cparata 0:13631b50eae6 1485 return ret;
cparata 0:13631b50eae6 1486 }
cparata 0:13631b50eae6 1487
cparata 0:13631b50eae6 1488 /**
cparata 0:13631b50eae6 1489 * @brief Select the signal that need to route on int1 pad.[set]
cparata 0:13631b50eae6 1490 *
cparata 0:13631b50eae6 1491 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1492 * @param val register CTRL4_INT1_PAD_CTRL.
cparata 0:13631b50eae6 1493 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1494 *
cparata 0:13631b50eae6 1495 */
cparata 0:13631b50eae6 1496 int32_t iis2dlpc_pin_int1_route_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1497 iis2dlpc_ctrl4_int1_pad_ctrl_t *val)
cparata 0:13631b50eae6 1498 {
cparata 0:13631b50eae6 1499 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 1500 int32_t ret;
cparata 0:13631b50eae6 1501
cparata 0:13631b50eae6 1502 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1503 if (ret == 0) {
cparata 0:13631b50eae6 1504 if ((val->int1_tap | val->int1_ff | val->int1_wu | val->int1_single_tap |
cparata 0:13631b50eae6 1505 val->int1_6d) != PROPERTY_DISABLE){
cparata 0:13631b50eae6 1506 reg.interrupts_enable = PROPERTY_ENABLE;
cparata 0:13631b50eae6 1507 }
cparata 0:13631b50eae6 1508 else{
cparata 0:13631b50eae6 1509 reg.interrupts_enable = PROPERTY_DISABLE;
cparata 0:13631b50eae6 1510 }
cparata 0:13631b50eae6 1511
cparata 0:13631b50eae6 1512 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
cparata 0:13631b50eae6 1513 (uint8_t*) val, 1);
cparata 0:13631b50eae6 1514 }
cparata 0:13631b50eae6 1515 if (ret == 0) {
cparata 0:13631b50eae6 1516 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1517 } else {
cparata 0:13631b50eae6 1518 ret = ret;
cparata 0:13631b50eae6 1519 }
cparata 0:13631b50eae6 1520 return ret;
cparata 0:13631b50eae6 1521 }
cparata 0:13631b50eae6 1522
cparata 0:13631b50eae6 1523 /**
cparata 0:13631b50eae6 1524 * @brief Select the signal that need to route on int1 pad.[get]
cparata 0:13631b50eae6 1525 *
cparata 0:13631b50eae6 1526 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1527 * @param val register CTRL4_INT1_PAD_CTRL.
cparata 0:13631b50eae6 1528 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1529 *
cparata 0:13631b50eae6 1530 */
cparata 0:13631b50eae6 1531 int32_t iis2dlpc_pin_int1_route_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1532 iis2dlpc_ctrl4_int1_pad_ctrl_t *val)
cparata 0:13631b50eae6 1533 {
cparata 0:13631b50eae6 1534 int32_t ret;
cparata 0:13631b50eae6 1535 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
cparata 0:13631b50eae6 1536 (uint8_t*) val, 1);
cparata 0:13631b50eae6 1537 return ret;
cparata 0:13631b50eae6 1538 }
cparata 0:13631b50eae6 1539
cparata 0:13631b50eae6 1540 /**
cparata 0:13631b50eae6 1541 * @brief Select the signal that need to route on int2 pad.[set]
cparata 0:13631b50eae6 1542 *
cparata 0:13631b50eae6 1543 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1544 * @param val register CTRL5_INT2_PAD_CTRL.
cparata 0:13631b50eae6 1545 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1546 *
cparata 0:13631b50eae6 1547 */
cparata 0:13631b50eae6 1548 int32_t iis2dlpc_pin_int2_route_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1549 iis2dlpc_ctrl5_int2_pad_ctrl_t *val)
cparata 0:13631b50eae6 1550 {
cparata 0:13631b50eae6 1551 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 1552 int32_t ret;
cparata 0:13631b50eae6 1553
cparata 0:13631b50eae6 1554 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1555 if (ret == 0) {
cparata 0:13631b50eae6 1556 if ((val->int2_sleep_state | val->int2_sleep_chg ) != PROPERTY_DISABLE) {
cparata 0:13631b50eae6 1557 reg.interrupts_enable = PROPERTY_ENABLE;
cparata 0:13631b50eae6 1558 }
cparata 0:13631b50eae6 1559 else{
cparata 0:13631b50eae6 1560 reg.interrupts_enable = PROPERTY_DISABLE;
cparata 0:13631b50eae6 1561 }
cparata 0:13631b50eae6 1562
cparata 0:13631b50eae6 1563 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
cparata 0:13631b50eae6 1564 (uint8_t*) val, 1);
cparata 0:13631b50eae6 1565 }
cparata 0:13631b50eae6 1566 if (ret == 0) {
cparata 0:13631b50eae6 1567 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1568 } else {
cparata 0:13631b50eae6 1569 ret = ret;
cparata 0:13631b50eae6 1570 }
cparata 0:13631b50eae6 1571 return ret;
cparata 0:13631b50eae6 1572 }
cparata 0:13631b50eae6 1573
cparata 0:13631b50eae6 1574 /**
cparata 0:13631b50eae6 1575 * @brief Select the signal that need to route on int2 pad.[get]
cparata 0:13631b50eae6 1576 *
cparata 0:13631b50eae6 1577 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1578 * @param val register CTRL5_INT2_PAD_CTRL
cparata 0:13631b50eae6 1579 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1580 *
cparata 0:13631b50eae6 1581 */
cparata 0:13631b50eae6 1582 int32_t iis2dlpc_pin_int2_route_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1583 iis2dlpc_ctrl5_int2_pad_ctrl_t *val)
cparata 0:13631b50eae6 1584 {
cparata 0:13631b50eae6 1585 int32_t ret;
cparata 0:13631b50eae6 1586 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
cparata 0:13631b50eae6 1587 (uint8_t*) val, 1);
cparata 0:13631b50eae6 1588 return ret;
cparata 0:13631b50eae6 1589 }
cparata 0:13631b50eae6 1590 /**
cparata 0:13631b50eae6 1591 * @brief All interrupt signals become available on INT1 pin.[set]
cparata 0:13631b50eae6 1592 *
cparata 0:13631b50eae6 1593 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1594 * @param val change the values of int2_on_int1 in reg CTRL_REG7
cparata 0:13631b50eae6 1595 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1596 *
cparata 0:13631b50eae6 1597 */
cparata 0:13631b50eae6 1598 int32_t iis2dlpc_all_on_int1_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 1599 {
cparata 0:13631b50eae6 1600 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 1601 int32_t ret;
cparata 0:13631b50eae6 1602
cparata 0:13631b50eae6 1603 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1604 if (ret == 0) {
cparata 0:13631b50eae6 1605 reg.int2_on_int1 = val;
cparata 0:13631b50eae6 1606 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1607 }
cparata 0:13631b50eae6 1608 return ret;
cparata 0:13631b50eae6 1609 }
cparata 0:13631b50eae6 1610
cparata 0:13631b50eae6 1611 /**
cparata 0:13631b50eae6 1612 * @brief All interrupt signals become available on INT1 pin.[get]
cparata 0:13631b50eae6 1613 *
cparata 0:13631b50eae6 1614 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1615 * @param val change the values of int2_on_int1 in reg CTRL_REG7
cparata 0:13631b50eae6 1616 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1617 *
cparata 0:13631b50eae6 1618 */
cparata 0:13631b50eae6 1619 int32_t iis2dlpc_all_on_int1_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 1620 {
cparata 0:13631b50eae6 1621 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 1622 int32_t ret;
cparata 0:13631b50eae6 1623
cparata 0:13631b50eae6 1624 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1625 *val = reg.int2_on_int1;
cparata 0:13631b50eae6 1626
cparata 0:13631b50eae6 1627 return ret;
cparata 0:13631b50eae6 1628 }
cparata 0:13631b50eae6 1629
cparata 0:13631b50eae6 1630 /**
cparata 0:13631b50eae6 1631 * @}
cparata 0:13631b50eae6 1632 *
cparata 0:13631b50eae6 1633 */
cparata 0:13631b50eae6 1634
cparata 0:13631b50eae6 1635 /**
cparata 0:13631b50eae6 1636 * @defgroup IIS2DLPC_Wake_Up_Event
cparata 0:13631b50eae6 1637 * @brief This section groups all the functions that manage the Wake
cparata 0:13631b50eae6 1638 * Up event generation.
cparata 0:13631b50eae6 1639 * @{
cparata 0:13631b50eae6 1640 *
cparata 0:13631b50eae6 1641 */
cparata 0:13631b50eae6 1642
cparata 0:13631b50eae6 1643 /**
cparata 0:13631b50eae6 1644 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
cparata 0:13631b50eae6 1645 *
cparata 0:13631b50eae6 1646 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1647 * @param val change the values of wk_ths in reg WAKE_UP_THS
cparata 0:13631b50eae6 1648 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1649 *
cparata 0:13631b50eae6 1650 */
cparata 0:13631b50eae6 1651 int32_t iis2dlpc_wkup_threshold_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 1652 {
cparata 0:13631b50eae6 1653 iis2dlpc_wake_up_ths_t reg;
cparata 0:13631b50eae6 1654 int32_t ret;
cparata 0:13631b50eae6 1655
cparata 0:13631b50eae6 1656 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1657 if (ret == 0) {
cparata 0:13631b50eae6 1658 reg.wk_ths = val;
cparata 0:13631b50eae6 1659 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1660 }
cparata 0:13631b50eae6 1661 return ret;
cparata 0:13631b50eae6 1662 }
cparata 0:13631b50eae6 1663
cparata 0:13631b50eae6 1664 /**
cparata 0:13631b50eae6 1665 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
cparata 0:13631b50eae6 1666 *
cparata 0:13631b50eae6 1667 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1668 * @param val change the values of wk_ths in reg WAKE_UP_THS
cparata 0:13631b50eae6 1669 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1670 *
cparata 0:13631b50eae6 1671 */
cparata 0:13631b50eae6 1672 int32_t iis2dlpc_wkup_threshold_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 1673 {
cparata 0:13631b50eae6 1674 iis2dlpc_wake_up_ths_t reg;
cparata 0:13631b50eae6 1675 int32_t ret;
cparata 0:13631b50eae6 1676
cparata 0:13631b50eae6 1677 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1678 *val = reg.wk_ths;
cparata 0:13631b50eae6 1679
cparata 0:13631b50eae6 1680 return ret;
cparata 0:13631b50eae6 1681 }
cparata 0:13631b50eae6 1682
cparata 0:13631b50eae6 1683 /**
cparata 0:13631b50eae6 1684 * @brief Wake up duration event.1LSb = 1 / ODR.[set]
cparata 0:13631b50eae6 1685 *
cparata 0:13631b50eae6 1686 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1687 * @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata 0:13631b50eae6 1688 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1689 *
cparata 0:13631b50eae6 1690 */
cparata 0:13631b50eae6 1691 int32_t iis2dlpc_wkup_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 1692 {
cparata 0:13631b50eae6 1693 iis2dlpc_wake_up_dur_t reg;
cparata 0:13631b50eae6 1694 int32_t ret;
cparata 0:13631b50eae6 1695
cparata 0:13631b50eae6 1696 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1697 if (ret == 0) {
cparata 0:13631b50eae6 1698 reg.wake_dur = val;
cparata 0:13631b50eae6 1699 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1700 }
cparata 0:13631b50eae6 1701 return ret;
cparata 0:13631b50eae6 1702 }
cparata 0:13631b50eae6 1703
cparata 0:13631b50eae6 1704 /**
cparata 0:13631b50eae6 1705 * @brief Wake up duration event.1LSb = 1 / ODR.[get]
cparata 0:13631b50eae6 1706 *
cparata 0:13631b50eae6 1707 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1708 * @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata 0:13631b50eae6 1709 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1710 *
cparata 0:13631b50eae6 1711 */
cparata 0:13631b50eae6 1712 int32_t iis2dlpc_wkup_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 1713 {
cparata 0:13631b50eae6 1714 iis2dlpc_wake_up_dur_t reg;
cparata 0:13631b50eae6 1715 int32_t ret;
cparata 0:13631b50eae6 1716
cparata 0:13631b50eae6 1717 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1718 *val = reg.wake_dur;
cparata 0:13631b50eae6 1719
cparata 0:13631b50eae6 1720 return ret;
cparata 0:13631b50eae6 1721 }
cparata 0:13631b50eae6 1722
cparata 0:13631b50eae6 1723 /**
cparata 0:13631b50eae6 1724 * @brief Data sent to wake-up interrupt function.[set]
cparata 0:13631b50eae6 1725 *
cparata 0:13631b50eae6 1726 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1727 * @param val change the values of usr_off_on_wu in reg CTRL_REG7
cparata 0:13631b50eae6 1728 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1729 *
cparata 0:13631b50eae6 1730 */
cparata 0:13631b50eae6 1731 int32_t iis2dlpc_wkup_feed_data_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1732 iis2dlpc_usr_off_on_wu_t val)
cparata 0:13631b50eae6 1733 {
cparata 0:13631b50eae6 1734 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 1735 int32_t ret;
cparata 0:13631b50eae6 1736
cparata 0:13631b50eae6 1737 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1738 if (ret == 0) {
cparata 0:13631b50eae6 1739 reg.usr_off_on_wu = (uint8_t) val;
cparata 0:13631b50eae6 1740 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1741 }
cparata 0:13631b50eae6 1742 return ret;
cparata 0:13631b50eae6 1743 }
cparata 0:13631b50eae6 1744
cparata 0:13631b50eae6 1745 /**
cparata 0:13631b50eae6 1746 * @brief Data sent to wake-up interrupt function.[get]
cparata 0:13631b50eae6 1747 *
cparata 0:13631b50eae6 1748 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1749 * @param val Get the values of usr_off_on_wu in reg CTRL_REG7
cparata 0:13631b50eae6 1750 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1751 *
cparata 0:13631b50eae6 1752 */
cparata 0:13631b50eae6 1753 int32_t iis2dlpc_wkup_feed_data_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1754 iis2dlpc_usr_off_on_wu_t *val)
cparata 0:13631b50eae6 1755 {
cparata 0:13631b50eae6 1756 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 1757 int32_t ret;
cparata 0:13631b50eae6 1758
cparata 0:13631b50eae6 1759 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1760
cparata 0:13631b50eae6 1761 switch (reg.usr_off_on_wu) {
cparata 0:13631b50eae6 1762 case IIS2DLPC_HP_FEED:
cparata 0:13631b50eae6 1763 *val = IIS2DLPC_HP_FEED;
cparata 0:13631b50eae6 1764 break;
cparata 0:13631b50eae6 1765 case IIS2DLPC_USER_OFFSET_FEED:
cparata 0:13631b50eae6 1766 *val = IIS2DLPC_USER_OFFSET_FEED;
cparata 0:13631b50eae6 1767 break;
cparata 0:13631b50eae6 1768 default:
cparata 0:13631b50eae6 1769 *val = IIS2DLPC_HP_FEED;
cparata 0:13631b50eae6 1770 break;
cparata 0:13631b50eae6 1771 }
cparata 0:13631b50eae6 1772 return ret;
cparata 0:13631b50eae6 1773 }
cparata 0:13631b50eae6 1774
cparata 0:13631b50eae6 1775 /**
cparata 0:13631b50eae6 1776 * @}
cparata 0:13631b50eae6 1777 *
cparata 0:13631b50eae6 1778 */
cparata 0:13631b50eae6 1779
cparata 0:13631b50eae6 1780 /**
cparata 0:13631b50eae6 1781 * @defgroup IIS2DLPC_Activity/Inactivity_Detection
cparata 0:13631b50eae6 1782 * @brief This section groups all the functions concerning
cparata 0:13631b50eae6 1783 * activity/inactivity detection.
cparata 0:13631b50eae6 1784 * @{
cparata 0:13631b50eae6 1785 *
cparata 0:13631b50eae6 1786 */
cparata 0:13631b50eae6 1787
cparata 0:13631b50eae6 1788 /**
cparata 0:13631b50eae6 1789 * @brief Config activity / inactivity or
cparata 0:13631b50eae6 1790 * stationary / motion detection.[set]
cparata 0:13631b50eae6 1791 *
cparata 0:13631b50eae6 1792 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1793 * @param val change the values of sleep_on / stationary in
cparata 0:13631b50eae6 1794 * reg WAKE_UP_THS / WAKE_UP_DUR
cparata 0:13631b50eae6 1795 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1796 *
cparata 0:13631b50eae6 1797 */
cparata 0:13631b50eae6 1798 int32_t iis2dlpc_act_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_sleep_on_t val)
cparata 0:13631b50eae6 1799 {
cparata 0:13631b50eae6 1800 iis2dlpc_wake_up_ths_t wake_up_ths;
cparata 0:13631b50eae6 1801 iis2dlpc_wake_up_dur_t wake_up_dur;
cparata 0:13631b50eae6 1802 int32_t ret;
cparata 0:13631b50eae6 1803
cparata 0:13631b50eae6 1804 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
cparata 0:13631b50eae6 1805 if (ret == 0) {
cparata 0:13631b50eae6 1806 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata 0:13631b50eae6 1807 }
cparata 0:13631b50eae6 1808 if (ret == 0) {
cparata 0:13631b50eae6 1809 wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
cparata 0:13631b50eae6 1810 wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
cparata 0:13631b50eae6 1811 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 2);
cparata 0:13631b50eae6 1812 } else {
cparata 0:13631b50eae6 1813 ret = ret;
cparata 0:13631b50eae6 1814 }
cparata 0:13631b50eae6 1815
cparata 0:13631b50eae6 1816 return ret;
cparata 0:13631b50eae6 1817 }
cparata 0:13631b50eae6 1818
cparata 0:13631b50eae6 1819 /**
cparata 0:13631b50eae6 1820 * @brief Config activity / inactivity or
cparata 0:13631b50eae6 1821 * stationary / motion detection. [get]
cparata 0:13631b50eae6 1822 *
cparata 0:13631b50eae6 1823 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1824 * @param val Get the values of sleep_on in reg WAKE_UP_THS
cparata 0:13631b50eae6 1825 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1826 *
cparata 0:13631b50eae6 1827 */
cparata 0:13631b50eae6 1828 int32_t iis2dlpc_act_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_sleep_on_t *val)
cparata 0:13631b50eae6 1829 {
cparata 0:13631b50eae6 1830 iis2dlpc_wake_up_ths_t wake_up_ths;
cparata 0:13631b50eae6 1831 iis2dlpc_wake_up_dur_t wake_up_dur;;
cparata 0:13631b50eae6 1832 int32_t ret;
cparata 0:13631b50eae6 1833
cparata 0:13631b50eae6 1834 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
cparata 0:13631b50eae6 1835 if (ret == 0) {
cparata 0:13631b50eae6 1836 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata 0:13631b50eae6 1837
cparata 0:13631b50eae6 1838 switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on){
cparata 0:13631b50eae6 1839 case IIS2DLPC_NO_DETECTION:
cparata 0:13631b50eae6 1840 *val = IIS2DLPC_NO_DETECTION;
cparata 0:13631b50eae6 1841 break;
cparata 0:13631b50eae6 1842 case IIS2DLPC_DETECT_ACT_INACT:
cparata 0:13631b50eae6 1843 *val = IIS2DLPC_DETECT_ACT_INACT;
cparata 0:13631b50eae6 1844 break;
cparata 0:13631b50eae6 1845 case IIS2DLPC_DETECT_STAT_MOTION:
cparata 0:13631b50eae6 1846 *val = IIS2DLPC_DETECT_STAT_MOTION;
cparata 0:13631b50eae6 1847 break;
cparata 0:13631b50eae6 1848 default:
cparata 0:13631b50eae6 1849 *val = IIS2DLPC_NO_DETECTION;
cparata 0:13631b50eae6 1850 break;
cparata 0:13631b50eae6 1851 }
cparata 0:13631b50eae6 1852 }
cparata 0:13631b50eae6 1853 return ret;
cparata 0:13631b50eae6 1854 }
cparata 0:13631b50eae6 1855
cparata 0:13631b50eae6 1856 /**
cparata 0:13631b50eae6 1857 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
cparata 0:13631b50eae6 1858 *
cparata 0:13631b50eae6 1859 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1860 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata 0:13631b50eae6 1861 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1862 *
cparata 0:13631b50eae6 1863 */
cparata 0:13631b50eae6 1864 int32_t iis2dlpc_act_sleep_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 1865 {
cparata 0:13631b50eae6 1866 iis2dlpc_wake_up_dur_t reg;
cparata 0:13631b50eae6 1867 int32_t ret;
cparata 0:13631b50eae6 1868
cparata 0:13631b50eae6 1869 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1870 if (ret == 0) {
cparata 0:13631b50eae6 1871 reg.sleep_dur = val;
cparata 0:13631b50eae6 1872 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1873 }
cparata 0:13631b50eae6 1874 return ret;
cparata 0:13631b50eae6 1875 }
cparata 0:13631b50eae6 1876
cparata 0:13631b50eae6 1877 /**
cparata 0:13631b50eae6 1878 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
cparata 0:13631b50eae6 1879 *
cparata 0:13631b50eae6 1880 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1881 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata 0:13631b50eae6 1882 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1883 *
cparata 0:13631b50eae6 1884 */
cparata 0:13631b50eae6 1885 int32_t iis2dlpc_act_sleep_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 1886 {
cparata 0:13631b50eae6 1887 iis2dlpc_wake_up_dur_t reg;
cparata 0:13631b50eae6 1888 int32_t ret;
cparata 0:13631b50eae6 1889
cparata 0:13631b50eae6 1890 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1891 *val = reg.sleep_dur;
cparata 0:13631b50eae6 1892
cparata 0:13631b50eae6 1893 return ret;
cparata 0:13631b50eae6 1894 }
cparata 0:13631b50eae6 1895
cparata 0:13631b50eae6 1896 /**
cparata 0:13631b50eae6 1897 * @}
cparata 0:13631b50eae6 1898 *
cparata 0:13631b50eae6 1899 */
cparata 0:13631b50eae6 1900
cparata 0:13631b50eae6 1901 /**
cparata 0:13631b50eae6 1902 * @defgroup IIS2DLPC_Tap_Generator
cparata 0:13631b50eae6 1903 * @brief This section groups all the functions that manage the tap
cparata 0:13631b50eae6 1904 * and double tap event generation.
cparata 0:13631b50eae6 1905 * @{
cparata 0:13631b50eae6 1906 *
cparata 0:13631b50eae6 1907 */
cparata 0:13631b50eae6 1908
cparata 0:13631b50eae6 1909 /**
cparata 0:13631b50eae6 1910 * @brief Threshold for tap recognition.[set]
cparata 0:13631b50eae6 1911 *
cparata 0:13631b50eae6 1912 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1913 * @param val change the values of tap_thsx in reg TAP_THS_X
cparata 0:13631b50eae6 1914 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1915 *
cparata 0:13631b50eae6 1916 */
cparata 0:13631b50eae6 1917 int32_t iis2dlpc_tap_threshold_x_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 1918 {
cparata 0:13631b50eae6 1919 iis2dlpc_tap_ths_x_t reg;
cparata 0:13631b50eae6 1920 int32_t ret;
cparata 0:13631b50eae6 1921
cparata 0:13631b50eae6 1922 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1923 if (ret == 0) {
cparata 0:13631b50eae6 1924 reg.tap_thsx = val;
cparata 0:13631b50eae6 1925 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1926 }
cparata 0:13631b50eae6 1927 return ret;
cparata 0:13631b50eae6 1928 }
cparata 0:13631b50eae6 1929
cparata 0:13631b50eae6 1930 /**
cparata 0:13631b50eae6 1931 * @brief Threshold for tap recognition.[get]
cparata 0:13631b50eae6 1932 *
cparata 0:13631b50eae6 1933 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1934 * @param val change the values of tap_thsx in reg TAP_THS_X
cparata 0:13631b50eae6 1935 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1936 *
cparata 0:13631b50eae6 1937 */
cparata 0:13631b50eae6 1938 int32_t iis2dlpc_tap_threshold_x_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 1939 {
cparata 0:13631b50eae6 1940 iis2dlpc_tap_ths_x_t reg;
cparata 0:13631b50eae6 1941 int32_t ret;
cparata 0:13631b50eae6 1942
cparata 0:13631b50eae6 1943 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1944 *val = reg.tap_thsx;
cparata 0:13631b50eae6 1945
cparata 0:13631b50eae6 1946 return ret;
cparata 0:13631b50eae6 1947 }
cparata 0:13631b50eae6 1948
cparata 0:13631b50eae6 1949 /**
cparata 0:13631b50eae6 1950 * @brief Threshold for tap recognition.[set]
cparata 0:13631b50eae6 1951 *
cparata 0:13631b50eae6 1952 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1953 * @param val change the values of tap_thsy in reg TAP_THS_Y
cparata 0:13631b50eae6 1954 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1955 *
cparata 0:13631b50eae6 1956 */
cparata 0:13631b50eae6 1957 int32_t iis2dlpc_tap_threshold_y_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 1958 {
cparata 0:13631b50eae6 1959 iis2dlpc_tap_ths_y_t reg;
cparata 0:13631b50eae6 1960 int32_t ret;
cparata 0:13631b50eae6 1961
cparata 0:13631b50eae6 1962 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1963 if (ret == 0) {
cparata 0:13631b50eae6 1964 reg.tap_thsy = val;
cparata 0:13631b50eae6 1965 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1966 }
cparata 0:13631b50eae6 1967 return ret;
cparata 0:13631b50eae6 1968 }
cparata 0:13631b50eae6 1969
cparata 0:13631b50eae6 1970 /**
cparata 0:13631b50eae6 1971 * @brief Threshold for tap recognition.[get]
cparata 0:13631b50eae6 1972 *
cparata 0:13631b50eae6 1973 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1974 * @param val change the values of tap_thsy in reg TAP_THS_Y
cparata 0:13631b50eae6 1975 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1976 *
cparata 0:13631b50eae6 1977 */
cparata 0:13631b50eae6 1978 int32_t iis2dlpc_tap_threshold_y_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 1979 {
cparata 0:13631b50eae6 1980 iis2dlpc_tap_ths_y_t reg;
cparata 0:13631b50eae6 1981 int32_t ret;
cparata 0:13631b50eae6 1982
cparata 0:13631b50eae6 1983 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 1984 *val = reg.tap_thsy;
cparata 0:13631b50eae6 1985
cparata 0:13631b50eae6 1986 return ret;
cparata 0:13631b50eae6 1987 }
cparata 0:13631b50eae6 1988
cparata 0:13631b50eae6 1989 /**
cparata 0:13631b50eae6 1990 * @brief Selection of axis priority for TAP detection.[set]
cparata 0:13631b50eae6 1991 *
cparata 0:13631b50eae6 1992 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 1993 * @param val change the values of tap_prior in reg TAP_THS_Y
cparata 0:13631b50eae6 1994 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 1995 *
cparata 0:13631b50eae6 1996 */
cparata 0:13631b50eae6 1997 int32_t iis2dlpc_tap_axis_priority_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 1998 iis2dlpc_tap_prior_t val)
cparata 0:13631b50eae6 1999 {
cparata 0:13631b50eae6 2000 iis2dlpc_tap_ths_y_t reg;
cparata 0:13631b50eae6 2001 int32_t ret;
cparata 0:13631b50eae6 2002
cparata 0:13631b50eae6 2003 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2004 if (ret == 0) {
cparata 0:13631b50eae6 2005 reg.tap_prior = (uint8_t) val;
cparata 0:13631b50eae6 2006 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2007 }
cparata 0:13631b50eae6 2008 return ret;
cparata 0:13631b50eae6 2009 }
cparata 0:13631b50eae6 2010
cparata 0:13631b50eae6 2011 /**
cparata 0:13631b50eae6 2012 * @brief Selection of axis priority for TAP detection.[get]
cparata 0:13631b50eae6 2013 *
cparata 0:13631b50eae6 2014 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2015 * @param val Get the values of tap_prior in reg TAP_THS_Y
cparata 0:13631b50eae6 2016 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2017 *
cparata 0:13631b50eae6 2018 */
cparata 0:13631b50eae6 2019 int32_t iis2dlpc_tap_axis_priority_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 2020 iis2dlpc_tap_prior_t *val)
cparata 0:13631b50eae6 2021 {
cparata 0:13631b50eae6 2022 iis2dlpc_tap_ths_y_t reg;
cparata 0:13631b50eae6 2023 int32_t ret;
cparata 0:13631b50eae6 2024
cparata 0:13631b50eae6 2025 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2026
cparata 0:13631b50eae6 2027 switch (reg.tap_prior) {
cparata 0:13631b50eae6 2028 case IIS2DLPC_XYZ:
cparata 0:13631b50eae6 2029 *val = IIS2DLPC_XYZ;
cparata 0:13631b50eae6 2030 break;
cparata 0:13631b50eae6 2031 case IIS2DLPC_YXZ:
cparata 0:13631b50eae6 2032 *val = IIS2DLPC_YXZ;
cparata 0:13631b50eae6 2033 break;
cparata 0:13631b50eae6 2034 case IIS2DLPC_XZY:
cparata 0:13631b50eae6 2035 *val = IIS2DLPC_XZY;
cparata 0:13631b50eae6 2036 break;
cparata 0:13631b50eae6 2037 case IIS2DLPC_ZYX:
cparata 0:13631b50eae6 2038 *val = IIS2DLPC_ZYX;
cparata 0:13631b50eae6 2039 break;
cparata 0:13631b50eae6 2040 case IIS2DLPC_YZX:
cparata 0:13631b50eae6 2041 *val = IIS2DLPC_YZX;
cparata 0:13631b50eae6 2042 break;
cparata 0:13631b50eae6 2043 case IIS2DLPC_ZXY:
cparata 0:13631b50eae6 2044 *val = IIS2DLPC_ZXY;
cparata 0:13631b50eae6 2045 break;
cparata 0:13631b50eae6 2046 default:
cparata 0:13631b50eae6 2047 *val = IIS2DLPC_XYZ;
cparata 0:13631b50eae6 2048 break;
cparata 0:13631b50eae6 2049 }
cparata 0:13631b50eae6 2050 return ret;
cparata 0:13631b50eae6 2051 }
cparata 0:13631b50eae6 2052
cparata 0:13631b50eae6 2053 /**
cparata 0:13631b50eae6 2054 * @brief Threshold for tap recognition.[set]
cparata 0:13631b50eae6 2055 *
cparata 0:13631b50eae6 2056 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2057 * @param val change the values of tap_thsz in reg TAP_THS_Z
cparata 0:13631b50eae6 2058 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2059 *
cparata 0:13631b50eae6 2060 */
cparata 0:13631b50eae6 2061 int32_t iis2dlpc_tap_threshold_z_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2062 {
cparata 0:13631b50eae6 2063 iis2dlpc_tap_ths_z_t reg;
cparata 0:13631b50eae6 2064 int32_t ret;
cparata 0:13631b50eae6 2065
cparata 0:13631b50eae6 2066 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2067 if (ret == 0) {
cparata 0:13631b50eae6 2068 reg.tap_thsz = val;
cparata 0:13631b50eae6 2069 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2070 }
cparata 0:13631b50eae6 2071
cparata 0:13631b50eae6 2072 return ret;
cparata 0:13631b50eae6 2073 }
cparata 0:13631b50eae6 2074
cparata 0:13631b50eae6 2075 /**
cparata 0:13631b50eae6 2076 * @brief Threshold for tap recognition.[get]
cparata 0:13631b50eae6 2077 *
cparata 0:13631b50eae6 2078 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2079 * @param val change the values of tap_thsz in reg TAP_THS_Z
cparata 0:13631b50eae6 2080 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2081 *
cparata 0:13631b50eae6 2082 */
cparata 0:13631b50eae6 2083 int32_t iis2dlpc_tap_threshold_z_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2084 {
cparata 0:13631b50eae6 2085 iis2dlpc_tap_ths_z_t reg;
cparata 0:13631b50eae6 2086 int32_t ret;
cparata 0:13631b50eae6 2087
cparata 0:13631b50eae6 2088 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2089 *val = reg.tap_thsz;
cparata 0:13631b50eae6 2090
cparata 0:13631b50eae6 2091 return ret;
cparata 0:13631b50eae6 2092 }
cparata 0:13631b50eae6 2093
cparata 0:13631b50eae6 2094 /**
cparata 0:13631b50eae6 2095 * @brief Enable Z direction in tap recognition.[set]
cparata 0:13631b50eae6 2096 *
cparata 0:13631b50eae6 2097 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2098 * @param val change the values of tap_z_en in reg TAP_THS_Z
cparata 0:13631b50eae6 2099 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2100 *
cparata 0:13631b50eae6 2101 */
cparata 0:13631b50eae6 2102 int32_t iis2dlpc_tap_detection_on_z_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2103 {
cparata 0:13631b50eae6 2104 iis2dlpc_tap_ths_z_t reg;
cparata 0:13631b50eae6 2105 int32_t ret;
cparata 0:13631b50eae6 2106
cparata 0:13631b50eae6 2107 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2108 if (ret == 0) {
cparata 0:13631b50eae6 2109 reg.tap_z_en = val;
cparata 0:13631b50eae6 2110 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2111 }
cparata 0:13631b50eae6 2112 return ret;
cparata 0:13631b50eae6 2113 }
cparata 0:13631b50eae6 2114
cparata 0:13631b50eae6 2115 /**
cparata 0:13631b50eae6 2116 * @brief Enable Z direction in tap recognition.[get]
cparata 0:13631b50eae6 2117 *
cparata 0:13631b50eae6 2118 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2119 * @param val change the values of tap_z_en in reg TAP_THS_Z
cparata 0:13631b50eae6 2120 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2121 *
cparata 0:13631b50eae6 2122 */
cparata 0:13631b50eae6 2123 int32_t iis2dlpc_tap_detection_on_z_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2124 {
cparata 0:13631b50eae6 2125 iis2dlpc_tap_ths_z_t reg;
cparata 0:13631b50eae6 2126 int32_t ret;
cparata 0:13631b50eae6 2127
cparata 0:13631b50eae6 2128 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2129 *val = reg.tap_z_en;
cparata 0:13631b50eae6 2130
cparata 0:13631b50eae6 2131 return ret;
cparata 0:13631b50eae6 2132 }
cparata 0:13631b50eae6 2133
cparata 0:13631b50eae6 2134 /**
cparata 0:13631b50eae6 2135 * @brief Enable Y direction in tap recognition.[set]
cparata 0:13631b50eae6 2136 *
cparata 0:13631b50eae6 2137 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2138 * @param val change the values of tap_y_en in reg TAP_THS_Z
cparata 0:13631b50eae6 2139 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2140 *
cparata 0:13631b50eae6 2141 */
cparata 0:13631b50eae6 2142 int32_t iis2dlpc_tap_detection_on_y_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2143 {
cparata 0:13631b50eae6 2144 iis2dlpc_tap_ths_z_t reg;
cparata 0:13631b50eae6 2145 int32_t ret;
cparata 0:13631b50eae6 2146
cparata 0:13631b50eae6 2147 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2148 if (ret == 0) {
cparata 0:13631b50eae6 2149 reg.tap_y_en = val;
cparata 0:13631b50eae6 2150 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2151 }
cparata 0:13631b50eae6 2152 return ret;
cparata 0:13631b50eae6 2153 }
cparata 0:13631b50eae6 2154
cparata 0:13631b50eae6 2155 /**
cparata 0:13631b50eae6 2156 * @brief Enable Y direction in tap recognition.[get]
cparata 0:13631b50eae6 2157 *
cparata 0:13631b50eae6 2158 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2159 * @param val change the values of tap_y_en in reg TAP_THS_Z
cparata 0:13631b50eae6 2160 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2161 *
cparata 0:13631b50eae6 2162 */
cparata 0:13631b50eae6 2163 int32_t iis2dlpc_tap_detection_on_y_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2164 {
cparata 0:13631b50eae6 2165 iis2dlpc_tap_ths_z_t reg;
cparata 0:13631b50eae6 2166 int32_t ret;
cparata 0:13631b50eae6 2167
cparata 0:13631b50eae6 2168 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2169 *val = reg.tap_y_en;
cparata 0:13631b50eae6 2170
cparata 0:13631b50eae6 2171 return ret;
cparata 0:13631b50eae6 2172 }
cparata 0:13631b50eae6 2173
cparata 0:13631b50eae6 2174 /**
cparata 0:13631b50eae6 2175 * @brief Enable X direction in tap recognition.[set]
cparata 0:13631b50eae6 2176 *
cparata 0:13631b50eae6 2177 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2178 * @param val change the values of tap_x_en in reg TAP_THS_Z
cparata 0:13631b50eae6 2179 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2180 *
cparata 0:13631b50eae6 2181 */
cparata 0:13631b50eae6 2182 int32_t iis2dlpc_tap_detection_on_x_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2183 {
cparata 0:13631b50eae6 2184 iis2dlpc_tap_ths_z_t reg;
cparata 0:13631b50eae6 2185 int32_t ret;
cparata 0:13631b50eae6 2186
cparata 0:13631b50eae6 2187 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2188 if (ret == 0) {
cparata 0:13631b50eae6 2189 reg.tap_x_en = val;
cparata 0:13631b50eae6 2190 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2191 }
cparata 0:13631b50eae6 2192 return ret;
cparata 0:13631b50eae6 2193 }
cparata 0:13631b50eae6 2194
cparata 0:13631b50eae6 2195 /**
cparata 0:13631b50eae6 2196 * @brief Enable X direction in tap recognition.[get]
cparata 0:13631b50eae6 2197 *
cparata 0:13631b50eae6 2198 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2199 * @param val change the values of tap_x_en in reg TAP_THS_Z
cparata 0:13631b50eae6 2200 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2201 *
cparata 0:13631b50eae6 2202 */
cparata 0:13631b50eae6 2203 int32_t iis2dlpc_tap_detection_on_x_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2204 {
cparata 0:13631b50eae6 2205 iis2dlpc_tap_ths_z_t reg;
cparata 0:13631b50eae6 2206 int32_t ret;
cparata 0:13631b50eae6 2207
cparata 0:13631b50eae6 2208 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2209 *val = reg.tap_x_en;
cparata 0:13631b50eae6 2210
cparata 0:13631b50eae6 2211 return ret;
cparata 0:13631b50eae6 2212 }
cparata 0:13631b50eae6 2213
cparata 0:13631b50eae6 2214 /**
cparata 0:13631b50eae6 2215 * @brief Maximum duration is the maximum time of an overthreshold signal
cparata 0:13631b50eae6 2216 * detection to be recognized as a tap event. The default value
cparata 0:13631b50eae6 2217 * of these bits is 00b which corresponds to 4*ODR_XL time.
cparata 0:13631b50eae6 2218 * If the SHOCK[1:0] bits are set to a different value, 1LSB
cparata 0:13631b50eae6 2219 * corresponds to 8*ODR_XL time.[set]
cparata 0:13631b50eae6 2220 *
cparata 0:13631b50eae6 2221 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2222 * @param val change the values of shock in reg INT_DUR
cparata 0:13631b50eae6 2223 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2224 *
cparata 0:13631b50eae6 2225 */
cparata 0:13631b50eae6 2226 int32_t iis2dlpc_tap_shock_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2227 {
cparata 0:13631b50eae6 2228 iis2dlpc_int_dur_t reg;
cparata 0:13631b50eae6 2229 int32_t ret;
cparata 0:13631b50eae6 2230
cparata 0:13631b50eae6 2231 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2232 if (ret == 0) {
cparata 0:13631b50eae6 2233 reg.shock = val;
cparata 0:13631b50eae6 2234 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2235 }
cparata 0:13631b50eae6 2236
cparata 0:13631b50eae6 2237 return ret;
cparata 0:13631b50eae6 2238 }
cparata 0:13631b50eae6 2239
cparata 0:13631b50eae6 2240 /**
cparata 0:13631b50eae6 2241 * @brief Maximum duration is the maximum time of an overthreshold signal
cparata 0:13631b50eae6 2242 * detection to be recognized as a tap event. The default value
cparata 0:13631b50eae6 2243 * of these bits is 00b which corresponds to 4*ODR_XL time.
cparata 0:13631b50eae6 2244 * If the SHOCK[1:0] bits are set to a different value, 1LSB
cparata 0:13631b50eae6 2245 * corresponds to 8*ODR_XL time.[get]
cparata 0:13631b50eae6 2246 *
cparata 0:13631b50eae6 2247 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2248 * @param val change the values of shock in reg INT_DUR
cparata 0:13631b50eae6 2249 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2250 *
cparata 0:13631b50eae6 2251 */
cparata 0:13631b50eae6 2252 int32_t iis2dlpc_tap_shock_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2253 {
cparata 0:13631b50eae6 2254 iis2dlpc_int_dur_t reg;
cparata 0:13631b50eae6 2255 int32_t ret;
cparata 0:13631b50eae6 2256
cparata 0:13631b50eae6 2257 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2258 *val = reg.shock;
cparata 0:13631b50eae6 2259
cparata 0:13631b50eae6 2260 return ret;
cparata 0:13631b50eae6 2261 }
cparata 0:13631b50eae6 2262
cparata 0:13631b50eae6 2263 /**
cparata 0:13631b50eae6 2264 * @brief Quiet time is the time after the first detected tap in which
cparata 0:13631b50eae6 2265 * there must not be any overthreshold event.
cparata 0:13631b50eae6 2266 * The default value of these bits is 00b which corresponds
cparata 0:13631b50eae6 2267 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
cparata 0:13631b50eae6 2268 * value, 1LSB corresponds to 4*ODR_XL time.[set]
cparata 0:13631b50eae6 2269 *
cparata 0:13631b50eae6 2270 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2271 * @param val change the values of quiet in reg INT_DUR
cparata 0:13631b50eae6 2272 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2273 *
cparata 0:13631b50eae6 2274 */
cparata 0:13631b50eae6 2275 int32_t iis2dlpc_tap_quiet_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2276 {
cparata 0:13631b50eae6 2277 iis2dlpc_int_dur_t reg;
cparata 0:13631b50eae6 2278 int32_t ret;
cparata 0:13631b50eae6 2279
cparata 0:13631b50eae6 2280 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2281 if (ret == 0) {
cparata 0:13631b50eae6 2282 reg.quiet = val;
cparata 0:13631b50eae6 2283 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2284 }
cparata 0:13631b50eae6 2285 return ret;
cparata 0:13631b50eae6 2286 }
cparata 0:13631b50eae6 2287
cparata 0:13631b50eae6 2288 /**
cparata 0:13631b50eae6 2289 * @brief Quiet time is the time after the first detected tap in which
cparata 0:13631b50eae6 2290 * there must not be any overthreshold event.
cparata 0:13631b50eae6 2291 * The default value of these bits is 00b which corresponds
cparata 0:13631b50eae6 2292 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
cparata 0:13631b50eae6 2293 * value, 1LSB corresponds to 4*ODR_XL time.[get]
cparata 0:13631b50eae6 2294 *
cparata 0:13631b50eae6 2295 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2296 * @param val change the values of quiet in reg INT_DUR
cparata 0:13631b50eae6 2297 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2298 *
cparata 0:13631b50eae6 2299 */
cparata 0:13631b50eae6 2300 int32_t iis2dlpc_tap_quiet_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2301 {
cparata 0:13631b50eae6 2302 iis2dlpc_int_dur_t reg;
cparata 0:13631b50eae6 2303 int32_t ret;
cparata 0:13631b50eae6 2304
cparata 0:13631b50eae6 2305 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2306 *val = reg.quiet;
cparata 0:13631b50eae6 2307
cparata 0:13631b50eae6 2308 return ret;
cparata 0:13631b50eae6 2309 }
cparata 0:13631b50eae6 2310
cparata 0:13631b50eae6 2311 /**
cparata 0:13631b50eae6 2312 * @brief When double tap recognition is enabled, this register expresses
cparata 0:13631b50eae6 2313 * the maximum time between two consecutive detected taps to
cparata 0:13631b50eae6 2314 * determine a double tap event.
cparata 0:13631b50eae6 2315 * The default value of these bits is 0000b which corresponds
cparata 0:13631b50eae6 2316 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
cparata 0:13631b50eae6 2317 * value, 1LSB corresponds to 32*ODR_XL time.[set]
cparata 0:13631b50eae6 2318 *
cparata 0:13631b50eae6 2319 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2320 * @param val change the values of latency in reg INT_DUR
cparata 0:13631b50eae6 2321 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2322 *
cparata 0:13631b50eae6 2323 */
cparata 0:13631b50eae6 2324 int32_t iis2dlpc_tap_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2325 {
cparata 0:13631b50eae6 2326 iis2dlpc_int_dur_t reg;
cparata 0:13631b50eae6 2327 int32_t ret;
cparata 0:13631b50eae6 2328
cparata 0:13631b50eae6 2329 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2330 if (ret == 0) {
cparata 0:13631b50eae6 2331 reg.latency = val;
cparata 0:13631b50eae6 2332 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2333 }
cparata 0:13631b50eae6 2334 return ret;
cparata 0:13631b50eae6 2335 }
cparata 0:13631b50eae6 2336
cparata 0:13631b50eae6 2337 /**
cparata 0:13631b50eae6 2338 * @brief When double tap recognition is enabled, this register expresses
cparata 0:13631b50eae6 2339 * the maximum time between two consecutive detected taps to
cparata 0:13631b50eae6 2340 * determine a double tap event.
cparata 0:13631b50eae6 2341 * The default value of these bits is 0000b which corresponds
cparata 0:13631b50eae6 2342 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
cparata 0:13631b50eae6 2343 * value, 1LSB corresponds to 32*ODR_XL time.[get]
cparata 0:13631b50eae6 2344 *
cparata 0:13631b50eae6 2345 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2346 * @param val change the values of latency in reg INT_DUR
cparata 0:13631b50eae6 2347 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2348 *
cparata 0:13631b50eae6 2349 */
cparata 0:13631b50eae6 2350 int32_t iis2dlpc_tap_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2351 {
cparata 0:13631b50eae6 2352 iis2dlpc_int_dur_t reg;
cparata 0:13631b50eae6 2353 int32_t ret;
cparata 0:13631b50eae6 2354
cparata 0:13631b50eae6 2355 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2356 *val = reg.latency;
cparata 0:13631b50eae6 2357
cparata 0:13631b50eae6 2358 return ret;
cparata 0:13631b50eae6 2359 }
cparata 0:13631b50eae6 2360
cparata 0:13631b50eae6 2361 /**
cparata 0:13631b50eae6 2362 * @brief Single/double-tap event enable.[set]
cparata 0:13631b50eae6 2363 *
cparata 0:13631b50eae6 2364 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2365 * @param val change the values of single_double_tap in reg WAKE_UP_THS
cparata 0:13631b50eae6 2366 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2367 *
cparata 0:13631b50eae6 2368 */
cparata 0:13631b50eae6 2369 int32_t iis2dlpc_tap_mode_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 2370 iis2dlpc_single_double_tap_t val)
cparata 0:13631b50eae6 2371 {
cparata 0:13631b50eae6 2372 iis2dlpc_wake_up_ths_t reg;
cparata 0:13631b50eae6 2373 int32_t ret;
cparata 0:13631b50eae6 2374
cparata 0:13631b50eae6 2375 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2376 if (ret == 0) {
cparata 0:13631b50eae6 2377 reg.single_double_tap = (uint8_t) val;
cparata 0:13631b50eae6 2378 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2379 }
cparata 0:13631b50eae6 2380 return ret;
cparata 0:13631b50eae6 2381 }
cparata 0:13631b50eae6 2382
cparata 0:13631b50eae6 2383 /**
cparata 0:13631b50eae6 2384 * @brief Single/double-tap event enable.[get]
cparata 0:13631b50eae6 2385 *
cparata 0:13631b50eae6 2386 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2387 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
cparata 0:13631b50eae6 2388 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2389 *
cparata 0:13631b50eae6 2390 */
cparata 0:13631b50eae6 2391 int32_t iis2dlpc_tap_mode_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 2392 iis2dlpc_single_double_tap_t *val)
cparata 0:13631b50eae6 2393 {
cparata 0:13631b50eae6 2394 iis2dlpc_wake_up_ths_t reg;
cparata 0:13631b50eae6 2395 int32_t ret;
cparata 0:13631b50eae6 2396
cparata 0:13631b50eae6 2397 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2398
cparata 0:13631b50eae6 2399 switch (reg.single_double_tap) {
cparata 0:13631b50eae6 2400 case IIS2DLPC_ONLY_SINGLE:
cparata 0:13631b50eae6 2401 *val = IIS2DLPC_ONLY_SINGLE;
cparata 0:13631b50eae6 2402 break;
cparata 0:13631b50eae6 2403 case IIS2DLPC_BOTH_SINGLE_DOUBLE:
cparata 0:13631b50eae6 2404 *val = IIS2DLPC_BOTH_SINGLE_DOUBLE;
cparata 0:13631b50eae6 2405 break;
cparata 0:13631b50eae6 2406 default:
cparata 0:13631b50eae6 2407 *val = IIS2DLPC_ONLY_SINGLE;
cparata 0:13631b50eae6 2408 break;
cparata 0:13631b50eae6 2409 }
cparata 0:13631b50eae6 2410
cparata 0:13631b50eae6 2411 return ret;
cparata 0:13631b50eae6 2412 }
cparata 0:13631b50eae6 2413
cparata 0:13631b50eae6 2414 /**
cparata 0:13631b50eae6 2415 * @brief Read the tap / double tap source register.[get]
cparata 0:13631b50eae6 2416 *
cparata 0:13631b50eae6 2417 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2418 * @param iis2dlpc_tap_src: union of registers from TAP_SRC to
cparata 0:13631b50eae6 2419 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2420 *
cparata 0:13631b50eae6 2421 */
cparata 0:13631b50eae6 2422 int32_t iis2dlpc_tap_src_get(iis2dlpc_ctx_t *ctx, iis2dlpc_tap_src_t *val)
cparata 0:13631b50eae6 2423 {
cparata 0:13631b50eae6 2424 int32_t ret;
cparata 0:13631b50eae6 2425 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_SRC, (uint8_t*) val, 1);
cparata 0:13631b50eae6 2426 return ret;
cparata 0:13631b50eae6 2427 }
cparata 0:13631b50eae6 2428
cparata 0:13631b50eae6 2429 /**
cparata 0:13631b50eae6 2430 * @}
cparata 0:13631b50eae6 2431 *
cparata 0:13631b50eae6 2432 */
cparata 0:13631b50eae6 2433
cparata 0:13631b50eae6 2434 /**
cparata 0:13631b50eae6 2435 * @defgroup IIS2DLPC_Six_Position_Detection(6D/4D)
cparata 0:13631b50eae6 2436 * @brief This section groups all the functions concerning six
cparata 0:13631b50eae6 2437 * position detection (6D).
cparata 0:13631b50eae6 2438 * @{
cparata 0:13631b50eae6 2439 *
cparata 0:13631b50eae6 2440 */
cparata 0:13631b50eae6 2441
cparata 0:13631b50eae6 2442 /**
cparata 0:13631b50eae6 2443 * @brief Threshold for 4D/6D function.[set]
cparata 0:13631b50eae6 2444 *
cparata 0:13631b50eae6 2445 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2446 * @param val change the values of 6d_ths in reg TAP_THS_X
cparata 0:13631b50eae6 2447 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2448 *
cparata 0:13631b50eae6 2449 */
cparata 0:13631b50eae6 2450 int32_t iis2dlpc_6d_threshold_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2451 {
cparata 0:13631b50eae6 2452 iis2dlpc_tap_ths_x_t reg;
cparata 0:13631b50eae6 2453 int32_t ret;
cparata 0:13631b50eae6 2454
cparata 0:13631b50eae6 2455 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2456 if (ret == 0) {
cparata 0:13631b50eae6 2457 reg._6d_ths = val;
cparata 0:13631b50eae6 2458 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2459 }
cparata 0:13631b50eae6 2460 return ret;
cparata 0:13631b50eae6 2461 }
cparata 0:13631b50eae6 2462
cparata 0:13631b50eae6 2463 /**
cparata 0:13631b50eae6 2464 * @brief Threshold for 4D/6D function.[get]
cparata 0:13631b50eae6 2465 *
cparata 0:13631b50eae6 2466 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2467 * @param val change the values of 6d_ths in reg TAP_THS_X
cparata 0:13631b50eae6 2468 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2469 *
cparata 0:13631b50eae6 2470 */
cparata 0:13631b50eae6 2471 int32_t iis2dlpc_6d_threshold_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2472 {
cparata 0:13631b50eae6 2473 iis2dlpc_tap_ths_x_t reg;
cparata 0:13631b50eae6 2474 int32_t ret;
cparata 0:13631b50eae6 2475
cparata 0:13631b50eae6 2476 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2477 *val = reg._6d_ths;
cparata 0:13631b50eae6 2478
cparata 0:13631b50eae6 2479 return ret;
cparata 0:13631b50eae6 2480 }
cparata 0:13631b50eae6 2481
cparata 0:13631b50eae6 2482 /**
cparata 0:13631b50eae6 2483 * @brief 4D orientation detection enable.[set]
cparata 0:13631b50eae6 2484 *
cparata 0:13631b50eae6 2485 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2486 * @param val change the values of 4d_en in reg TAP_THS_X
cparata 0:13631b50eae6 2487 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2488 *
cparata 0:13631b50eae6 2489 */
cparata 0:13631b50eae6 2490 int32_t iis2dlpc_4d_mode_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2491 {
cparata 0:13631b50eae6 2492 iis2dlpc_tap_ths_x_t reg;
cparata 0:13631b50eae6 2493 int32_t ret;
cparata 0:13631b50eae6 2494
cparata 0:13631b50eae6 2495 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2496 if (ret == 0) {
cparata 0:13631b50eae6 2497 reg._4d_en = val;
cparata 0:13631b50eae6 2498 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2499 }
cparata 0:13631b50eae6 2500
cparata 0:13631b50eae6 2501 return ret;
cparata 0:13631b50eae6 2502 }
cparata 0:13631b50eae6 2503
cparata 0:13631b50eae6 2504 /**
cparata 0:13631b50eae6 2505 * @brief 4D orientation detection enable.[get]
cparata 0:13631b50eae6 2506 *
cparata 0:13631b50eae6 2507 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2508 * @param val change the values of 4d_en in reg TAP_THS_X
cparata 0:13631b50eae6 2509 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2510 *
cparata 0:13631b50eae6 2511 */
cparata 0:13631b50eae6 2512 int32_t iis2dlpc_4d_mode_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2513 {
cparata 0:13631b50eae6 2514 iis2dlpc_tap_ths_x_t reg;
cparata 0:13631b50eae6 2515 int32_t ret;
cparata 0:13631b50eae6 2516
cparata 0:13631b50eae6 2517 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2518 *val = reg._4d_en;
cparata 0:13631b50eae6 2519
cparata 0:13631b50eae6 2520 return ret;
cparata 0:13631b50eae6 2521 }
cparata 0:13631b50eae6 2522
cparata 0:13631b50eae6 2523 /**
cparata 0:13631b50eae6 2524 * @brief Read the 6D tap source register.[get]
cparata 0:13631b50eae6 2525 *
cparata 0:13631b50eae6 2526 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2527 * @param val union of registers from SIXD_SRC
cparata 0:13631b50eae6 2528 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2529 *
cparata 0:13631b50eae6 2530 */
cparata 0:13631b50eae6 2531 int32_t iis2dlpc_6d_src_get(iis2dlpc_ctx_t *ctx, iis2dlpc_sixd_src_t *val)
cparata 0:13631b50eae6 2532 {
cparata 0:13631b50eae6 2533 int32_t ret;
cparata 0:13631b50eae6 2534 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_SIXD_SRC, (uint8_t*) val, 1);
cparata 0:13631b50eae6 2535 return ret;
cparata 0:13631b50eae6 2536 }
cparata 0:13631b50eae6 2537 /**
cparata 0:13631b50eae6 2538 * @brief Data sent to 6D interrupt function.[set]
cparata 0:13631b50eae6 2539 *
cparata 0:13631b50eae6 2540 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2541 * @param val change the values of lpass_on6d in reg CTRL_REG7
cparata 0:13631b50eae6 2542 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2543 *
cparata 0:13631b50eae6 2544 */
cparata 0:13631b50eae6 2545 int32_t iis2dlpc_6d_feed_data_set(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 2546 iis2dlpc_lpass_on6d_t val)
cparata 0:13631b50eae6 2547 {
cparata 0:13631b50eae6 2548 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 2549 int32_t ret;
cparata 0:13631b50eae6 2550
cparata 0:13631b50eae6 2551 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2552 if (ret == 0) {
cparata 0:13631b50eae6 2553 reg.lpass_on6d = (uint8_t) val;
cparata 0:13631b50eae6 2554 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2555 }
cparata 0:13631b50eae6 2556 return ret;
cparata 0:13631b50eae6 2557 }
cparata 0:13631b50eae6 2558
cparata 0:13631b50eae6 2559 /**
cparata 0:13631b50eae6 2560 * @brief Data sent to 6D interrupt function.[get]
cparata 0:13631b50eae6 2561 *
cparata 0:13631b50eae6 2562 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2563 * @param val Get the values of lpass_on6d in reg CTRL_REG7
cparata 0:13631b50eae6 2564 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2565 *
cparata 0:13631b50eae6 2566 */
cparata 0:13631b50eae6 2567 int32_t iis2dlpc_6d_feed_data_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 2568 iis2dlpc_lpass_on6d_t *val)
cparata 0:13631b50eae6 2569 {
cparata 0:13631b50eae6 2570 iis2dlpc_ctrl_reg7_t reg;
cparata 0:13631b50eae6 2571 int32_t ret;
cparata 0:13631b50eae6 2572
cparata 0:13631b50eae6 2573 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2574
cparata 0:13631b50eae6 2575 switch (reg.lpass_on6d) {
cparata 0:13631b50eae6 2576 case IIS2DLPC_ODR_DIV_2_FEED:
cparata 0:13631b50eae6 2577 *val = IIS2DLPC_ODR_DIV_2_FEED;
cparata 0:13631b50eae6 2578 break;
cparata 0:13631b50eae6 2579 case IIS2DLPC_LPF2_FEED:
cparata 0:13631b50eae6 2580 *val = IIS2DLPC_LPF2_FEED;
cparata 0:13631b50eae6 2581 break;
cparata 0:13631b50eae6 2582 default:
cparata 0:13631b50eae6 2583 *val = IIS2DLPC_ODR_DIV_2_FEED;
cparata 0:13631b50eae6 2584 break;
cparata 0:13631b50eae6 2585 }
cparata 0:13631b50eae6 2586 return ret;
cparata 0:13631b50eae6 2587 }
cparata 0:13631b50eae6 2588
cparata 0:13631b50eae6 2589 /**
cparata 0:13631b50eae6 2590 * @}
cparata 0:13631b50eae6 2591 *
cparata 0:13631b50eae6 2592 */
cparata 0:13631b50eae6 2593
cparata 0:13631b50eae6 2594 /**
cparata 0:13631b50eae6 2595 * @defgroup IIS2DLPC_Free_Fall
cparata 0:13631b50eae6 2596 * @brief This section group all the functions concerning
cparata 0:13631b50eae6 2597 * the free fall detection.
cparata 0:13631b50eae6 2598 * @{
cparata 0:13631b50eae6 2599 *
cparata 0:13631b50eae6 2600 */
cparata 0:13631b50eae6 2601
cparata 0:13631b50eae6 2602 /**
cparata 0:13631b50eae6 2603 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
cparata 0:13631b50eae6 2604 *
cparata 0:13631b50eae6 2605 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2606 * @param val change the values of ff_dur in reg
cparata 0:13631b50eae6 2607 * WAKE_UP_DUR /F REE_FALL
cparata 0:13631b50eae6 2608 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2609 *
cparata 0:13631b50eae6 2610 */
cparata 0:13631b50eae6 2611 int32_t iis2dlpc_ff_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2612 {
cparata 0:13631b50eae6 2613 iis2dlpc_wake_up_dur_t wake_up_dur;
cparata 0:13631b50eae6 2614 iis2dlpc_free_fall_t free_fall;
cparata 0:13631b50eae6 2615 int32_t ret;
cparata 0:13631b50eae6 2616
cparata 0:13631b50eae6 2617 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata 0:13631b50eae6 2618 if (ret == 0) {
cparata 0:13631b50eae6 2619 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1);
cparata 0:13631b50eae6 2620 }
cparata 0:13631b50eae6 2621 if(ret == 0) {
cparata 0:13631b50eae6 2622 wake_up_dur.ff_dur = ( (uint8_t) val & 0x20U) >> 5;
cparata 0:13631b50eae6 2623 free_fall.ff_dur = (uint8_t) val & 0x1FU;
cparata 0:13631b50eae6 2624 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata 0:13631b50eae6 2625 }
cparata 0:13631b50eae6 2626 if(ret == 0) {
cparata 0:13631b50eae6 2627 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1);
cparata 0:13631b50eae6 2628 }
cparata 0:13631b50eae6 2629
cparata 0:13631b50eae6 2630 return ret;
cparata 0:13631b50eae6 2631 }
cparata 0:13631b50eae6 2632
cparata 0:13631b50eae6 2633 /**
cparata 0:13631b50eae6 2634 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
cparata 0:13631b50eae6 2635 *
cparata 0:13631b50eae6 2636 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2637 * @param val change the values of ff_dur in
cparata 0:13631b50eae6 2638 * reg WAKE_UP_DUR /F REE_FALL
cparata 0:13631b50eae6 2639 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2640 *
cparata 0:13631b50eae6 2641 */
cparata 0:13631b50eae6 2642 int32_t iis2dlpc_ff_dur_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2643 {
cparata 0:13631b50eae6 2644 iis2dlpc_wake_up_dur_t wake_up_dur;
cparata 0:13631b50eae6 2645 iis2dlpc_free_fall_t free_fall;
cparata 0:13631b50eae6 2646 int32_t ret;
cparata 0:13631b50eae6 2647
cparata 0:13631b50eae6 2648 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata 0:13631b50eae6 2649 if (ret == 0) {
cparata 0:13631b50eae6 2650 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1);
cparata 0:13631b50eae6 2651 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
cparata 0:13631b50eae6 2652 }
cparata 0:13631b50eae6 2653 return ret;
cparata 0:13631b50eae6 2654 }
cparata 0:13631b50eae6 2655
cparata 0:13631b50eae6 2656 /**
cparata 0:13631b50eae6 2657 * @brief Free fall threshold setting.[set]
cparata 0:13631b50eae6 2658 *
cparata 0:13631b50eae6 2659 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2660 * @param val change the values of ff_ths in reg FREE_FALL
cparata 0:13631b50eae6 2661 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2662 *
cparata 0:13631b50eae6 2663 */
cparata 0:13631b50eae6 2664 int32_t iis2dlpc_ff_threshold_set(iis2dlpc_ctx_t *ctx, iis2dlpc_ff_ths_t val)
cparata 0:13631b50eae6 2665 {
cparata 0:13631b50eae6 2666 iis2dlpc_free_fall_t reg;
cparata 0:13631b50eae6 2667 int32_t ret;
cparata 0:13631b50eae6 2668
cparata 0:13631b50eae6 2669 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2670 if (ret == 0) {
cparata 0:13631b50eae6 2671 reg.ff_ths = (uint8_t) val;
cparata 0:13631b50eae6 2672 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2673 }
cparata 0:13631b50eae6 2674
cparata 0:13631b50eae6 2675 return ret;
cparata 0:13631b50eae6 2676 }
cparata 0:13631b50eae6 2677
cparata 0:13631b50eae6 2678 /**
cparata 0:13631b50eae6 2679 * @brief Free fall threshold setting.[get]
cparata 0:13631b50eae6 2680 *
cparata 0:13631b50eae6 2681 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2682 * @param val Get the values of ff_ths in reg FREE_FALL
cparata 0:13631b50eae6 2683 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2684 *
cparata 0:13631b50eae6 2685 */
cparata 0:13631b50eae6 2686 int32_t iis2dlpc_ff_threshold_get(iis2dlpc_ctx_t *ctx,
cparata 0:13631b50eae6 2687 iis2dlpc_ff_ths_t *val)
cparata 0:13631b50eae6 2688 {
cparata 0:13631b50eae6 2689 iis2dlpc_free_fall_t reg;
cparata 0:13631b50eae6 2690 int32_t ret;
cparata 0:13631b50eae6 2691
cparata 0:13631b50eae6 2692 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2693
cparata 0:13631b50eae6 2694 switch (reg.ff_ths) {
cparata 0:13631b50eae6 2695 case IIS2DLPC_FF_TSH_5LSb_FS2g:
cparata 0:13631b50eae6 2696 *val = IIS2DLPC_FF_TSH_5LSb_FS2g;
cparata 0:13631b50eae6 2697 break;
cparata 0:13631b50eae6 2698 case IIS2DLPC_FF_TSH_7LSb_FS2g:
cparata 0:13631b50eae6 2699 *val = IIS2DLPC_FF_TSH_7LSb_FS2g;
cparata 0:13631b50eae6 2700 break;
cparata 0:13631b50eae6 2701 case IIS2DLPC_FF_TSH_8LSb_FS2g:
cparata 0:13631b50eae6 2702 *val = IIS2DLPC_FF_TSH_8LSb_FS2g;
cparata 0:13631b50eae6 2703 break;
cparata 0:13631b50eae6 2704 case IIS2DLPC_FF_TSH_10LSb_FS2g:
cparata 0:13631b50eae6 2705 *val = IIS2DLPC_FF_TSH_10LSb_FS2g;
cparata 0:13631b50eae6 2706 break;
cparata 0:13631b50eae6 2707 case IIS2DLPC_FF_TSH_11LSb_FS2g:
cparata 0:13631b50eae6 2708 *val = IIS2DLPC_FF_TSH_11LSb_FS2g;
cparata 0:13631b50eae6 2709 break;
cparata 0:13631b50eae6 2710 case IIS2DLPC_FF_TSH_13LSb_FS2g:
cparata 0:13631b50eae6 2711 *val = IIS2DLPC_FF_TSH_13LSb_FS2g;
cparata 0:13631b50eae6 2712 break;
cparata 0:13631b50eae6 2713 case IIS2DLPC_FF_TSH_15LSb_FS2g:
cparata 0:13631b50eae6 2714 *val = IIS2DLPC_FF_TSH_15LSb_FS2g;
cparata 0:13631b50eae6 2715 break;
cparata 0:13631b50eae6 2716 case IIS2DLPC_FF_TSH_16LSb_FS2g:
cparata 0:13631b50eae6 2717 *val = IIS2DLPC_FF_TSH_16LSb_FS2g;
cparata 0:13631b50eae6 2718 break;
cparata 0:13631b50eae6 2719 default:
cparata 0:13631b50eae6 2720 *val = IIS2DLPC_FF_TSH_5LSb_FS2g;
cparata 0:13631b50eae6 2721 break;
cparata 0:13631b50eae6 2722 }
cparata 0:13631b50eae6 2723 return ret;
cparata 0:13631b50eae6 2724 }
cparata 0:13631b50eae6 2725
cparata 0:13631b50eae6 2726 /**
cparata 0:13631b50eae6 2727 * @}
cparata 0:13631b50eae6 2728 *
cparata 0:13631b50eae6 2729 */
cparata 0:13631b50eae6 2730
cparata 0:13631b50eae6 2731 /**
cparata 0:13631b50eae6 2732 * @defgroup IIS2DLPC_Fifo
cparata 0:13631b50eae6 2733 * @brief This section group all the functions concerning the fifo usage
cparata 0:13631b50eae6 2734 * @{
cparata 0:13631b50eae6 2735 *
cparata 0:13631b50eae6 2736 */
cparata 0:13631b50eae6 2737
cparata 0:13631b50eae6 2738 /**
cparata 0:13631b50eae6 2739 * @brief FIFO watermark level selection.[set]
cparata 0:13631b50eae6 2740 *
cparata 0:13631b50eae6 2741 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2742 * @param val change the values of fth in reg FIFO_CTRL
cparata 0:13631b50eae6 2743 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2744 *
cparata 0:13631b50eae6 2745 */
cparata 0:13631b50eae6 2746 int32_t iis2dlpc_fifo_watermark_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata 0:13631b50eae6 2747 {
cparata 0:13631b50eae6 2748 iis2dlpc_fifo_ctrl_t reg;
cparata 0:13631b50eae6 2749 int32_t ret;
cparata 0:13631b50eae6 2750
cparata 0:13631b50eae6 2751 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2752 if (ret == 0) {
cparata 0:13631b50eae6 2753 reg.fth = val;
cparata 0:13631b50eae6 2754 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2755 }
cparata 0:13631b50eae6 2756
cparata 0:13631b50eae6 2757 return ret;
cparata 0:13631b50eae6 2758 }
cparata 0:13631b50eae6 2759
cparata 0:13631b50eae6 2760 /**
cparata 0:13631b50eae6 2761 * @brief FIFO watermark level selection.[get]
cparata 0:13631b50eae6 2762 *
cparata 0:13631b50eae6 2763 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2764 * @param val change the values of fth in reg FIFO_CTRL
cparata 0:13631b50eae6 2765 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2766 *
cparata 0:13631b50eae6 2767 */
cparata 0:13631b50eae6 2768 int32_t iis2dlpc_fifo_watermark_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2769 {
cparata 0:13631b50eae6 2770 iis2dlpc_fifo_ctrl_t reg;
cparata 0:13631b50eae6 2771 int32_t ret;
cparata 0:13631b50eae6 2772
cparata 0:13631b50eae6 2773 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2774 *val = reg.fth;
cparata 0:13631b50eae6 2775
cparata 0:13631b50eae6 2776 return ret;
cparata 0:13631b50eae6 2777 }
cparata 0:13631b50eae6 2778
cparata 0:13631b50eae6 2779 /**
cparata 0:13631b50eae6 2780 * @brief FIFO mode selection.[set]
cparata 0:13631b50eae6 2781 *
cparata 0:13631b50eae6 2782 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2783 * @param val change the values of fmode in reg FIFO_CTRL
cparata 0:13631b50eae6 2784 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2785 *
cparata 0:13631b50eae6 2786 */
cparata 0:13631b50eae6 2787 int32_t iis2dlpc_fifo_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fmode_t val)
cparata 0:13631b50eae6 2788 {
cparata 0:13631b50eae6 2789 iis2dlpc_fifo_ctrl_t reg;
cparata 0:13631b50eae6 2790 int32_t ret;
cparata 0:13631b50eae6 2791
cparata 0:13631b50eae6 2792 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2793 if (ret == 0) {
cparata 0:13631b50eae6 2794 reg.fmode = (uint8_t) val;
cparata 0:13631b50eae6 2795 ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2796 }
cparata 0:13631b50eae6 2797 return ret;
cparata 0:13631b50eae6 2798 }
cparata 0:13631b50eae6 2799
cparata 0:13631b50eae6 2800 /**
cparata 0:13631b50eae6 2801 * @brief FIFO mode selection.[get]
cparata 0:13631b50eae6 2802 *
cparata 0:13631b50eae6 2803 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2804 * @param val Get the values of fmode in reg FIFO_CTRL
cparata 0:13631b50eae6 2805 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2806 *
cparata 0:13631b50eae6 2807 */
cparata 0:13631b50eae6 2808 int32_t iis2dlpc_fifo_mode_get(iis2dlpc_ctx_t *ctx, iis2dlpc_fmode_t *val)
cparata 0:13631b50eae6 2809 {
cparata 0:13631b50eae6 2810 iis2dlpc_fifo_ctrl_t reg;
cparata 0:13631b50eae6 2811 int32_t ret;
cparata 0:13631b50eae6 2812
cparata 0:13631b50eae6 2813 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2814
cparata 0:13631b50eae6 2815 switch (reg.fmode) {
cparata 0:13631b50eae6 2816 case IIS2DLPC_BYPASS_MODE:
cparata 0:13631b50eae6 2817 *val = IIS2DLPC_BYPASS_MODE;
cparata 0:13631b50eae6 2818 break;
cparata 0:13631b50eae6 2819 case IIS2DLPC_FIFO_MODE:
cparata 0:13631b50eae6 2820 *val = IIS2DLPC_FIFO_MODE;
cparata 0:13631b50eae6 2821 break;
cparata 0:13631b50eae6 2822 case IIS2DLPC_STREAM_TO_FIFO_MODE:
cparata 0:13631b50eae6 2823 *val = IIS2DLPC_STREAM_TO_FIFO_MODE;
cparata 0:13631b50eae6 2824 break;
cparata 0:13631b50eae6 2825 case IIS2DLPC_BYPASS_TO_STREAM_MODE:
cparata 0:13631b50eae6 2826 *val = IIS2DLPC_BYPASS_TO_STREAM_MODE;
cparata 0:13631b50eae6 2827 break;
cparata 0:13631b50eae6 2828 case IIS2DLPC_STREAM_MODE:
cparata 0:13631b50eae6 2829 *val = IIS2DLPC_STREAM_MODE;
cparata 0:13631b50eae6 2830 break;
cparata 0:13631b50eae6 2831 default:
cparata 0:13631b50eae6 2832 *val = IIS2DLPC_BYPASS_MODE;
cparata 0:13631b50eae6 2833 break;
cparata 0:13631b50eae6 2834 }
cparata 0:13631b50eae6 2835 return ret;
cparata 0:13631b50eae6 2836 }
cparata 0:13631b50eae6 2837
cparata 0:13631b50eae6 2838 /**
cparata 0:13631b50eae6 2839 * @brief Number of unread samples stored in FIFO.[get]
cparata 0:13631b50eae6 2840 *
cparata 0:13631b50eae6 2841 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2842 * @param val change the values of diff in reg FIFO_SAMPLES
cparata 0:13631b50eae6 2843 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2844 *
cparata 0:13631b50eae6 2845 */
cparata 0:13631b50eae6 2846 int32_t iis2dlpc_fifo_data_level_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2847 {
cparata 0:13631b50eae6 2848 iis2dlpc_fifo_samples_t reg;
cparata 0:13631b50eae6 2849 int32_t ret;
cparata 0:13631b50eae6 2850
cparata 0:13631b50eae6 2851 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2852 *val = reg.diff;
cparata 0:13631b50eae6 2853
cparata 0:13631b50eae6 2854 return ret;
cparata 0:13631b50eae6 2855 }
cparata 0:13631b50eae6 2856 /**
cparata 0:13631b50eae6 2857 * @brief FIFO overrun status.[get]
cparata 0:13631b50eae6 2858 *
cparata 0:13631b50eae6 2859 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2860 * @param val change the values of fifo_ovr in reg FIFO_SAMPLES
cparata 0:13631b50eae6 2861 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2862 *
cparata 0:13631b50eae6 2863 */
cparata 0:13631b50eae6 2864 int32_t iis2dlpc_fifo_ovr_flag_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2865 {
cparata 0:13631b50eae6 2866 iis2dlpc_fifo_samples_t reg;
cparata 0:13631b50eae6 2867 int32_t ret;
cparata 0:13631b50eae6 2868
cparata 0:13631b50eae6 2869 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2870 *val = reg.fifo_ovr;
cparata 0:13631b50eae6 2871
cparata 0:13631b50eae6 2872 return ret;
cparata 0:13631b50eae6 2873 }
cparata 0:13631b50eae6 2874 /**
cparata 0:13631b50eae6 2875 * @brief FIFO threshold status flag.[get]
cparata 0:13631b50eae6 2876 *
cparata 0:13631b50eae6 2877 * @param ctx read / write interface definitions
cparata 0:13631b50eae6 2878 * @param val change the values of fifo_fth in reg FIFO_SAMPLES
cparata 0:13631b50eae6 2879 * @retval interface status (MANDATORY: return 0 -> no Error)
cparata 0:13631b50eae6 2880 *
cparata 0:13631b50eae6 2881 */
cparata 0:13631b50eae6 2882 int32_t iis2dlpc_fifo_wtm_flag_get(iis2dlpc_ctx_t *ctx, uint8_t *val)
cparata 0:13631b50eae6 2883 {
cparata 0:13631b50eae6 2884 iis2dlpc_fifo_samples_t reg;
cparata 0:13631b50eae6 2885 int32_t ret;
cparata 0:13631b50eae6 2886
cparata 0:13631b50eae6 2887 ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) &reg, 1);
cparata 0:13631b50eae6 2888 *val = reg.fifo_fth;
cparata 0:13631b50eae6 2889
cparata 0:13631b50eae6 2890 return ret;
cparata 0:13631b50eae6 2891 }
cparata 0:13631b50eae6 2892 /**
cparata 0:13631b50eae6 2893 * @}
cparata 0:13631b50eae6 2894 *
cparata 0:13631b50eae6 2895 */
cparata 0:13631b50eae6 2896
cparata 0:13631b50eae6 2897 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/