IIS2DLPC - MEMS digital output motion sensor: high-performan…

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MEMS digital output motion sensor: high-performance ultra-low-power 3-axis accelerometer for industrial applications

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

iis2dlpc_reg.c@2:28ad92a16a36, 2018-11-21 (annotated)

Committer:: cparata
Date:: Wed Nov 21 15:51:50 2018 +0000
Revision:: 2:28ad92a16a36
Parent:: 1:7b1fcb1bb23d

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cparata	1:7b1fcb1bb23d	1	/**
cparata	0:13631b50eae6	2	******************************************************************************
cparata	0:13631b50eae6	3	* @file iis2dlpc_reg.c
cparata	0:13631b50eae6	4	* @author Sensors Software Solution Team
cparata	0:13631b50eae6	5	* @brief IIS2DLPC driver file
cparata	0:13631b50eae6	6	******************************************************************************
cparata	0:13631b50eae6	7	* @attention
cparata	0:13631b50eae6	8	*
cparata	0:13631b50eae6	9	* <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
cparata	0:13631b50eae6	10	*
cparata	0:13631b50eae6	11	* Redistribution and use in source and binary forms, with or without
cparata	0:13631b50eae6	12	* modification, are permitted provided that the following conditions
cparata	0:13631b50eae6	13	* are met:
cparata	0:13631b50eae6	14	* 1. Redistributions of source code must retain the above copyright notice,
cparata	0:13631b50eae6	15	* this list of conditions and the following disclaimer.
cparata	0:13631b50eae6	16	* 2. Redistributions in binary form must reproduce the above copyright
cparata	0:13631b50eae6	17	* notice, this list of conditions and the following disclaimer in the
cparata	0:13631b50eae6	18	* documentation and/or other materials provided with the distribution.
cparata	0:13631b50eae6	19	* 3. Neither the name of STMicroelectronics nor the names of its
cparata	0:13631b50eae6	20	* contributors may be used to endorse or promote products derived from
cparata	0:13631b50eae6	21	* this software without specific prior written permission.
cparata	0:13631b50eae6	22	*
cparata	0:13631b50eae6	23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
cparata	0:13631b50eae6	24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
cparata	0:13631b50eae6	25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
cparata	0:13631b50eae6	26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
cparata	0:13631b50eae6	27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
cparata	0:13631b50eae6	28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
cparata	0:13631b50eae6	29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
cparata	0:13631b50eae6	30	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
cparata	0:13631b50eae6	31	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
cparata	0:13631b50eae6	32	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
cparata	0:13631b50eae6	33	* POSSIBILITY OF SUCH DAMAGE.
cparata	0:13631b50eae6	34	*
cparata	2:28ad92a16a36	35	******************************************************************************
cparata	0:13631b50eae6	36	*/
cparata	0:13631b50eae6	37
cparata	0:13631b50eae6	38	#include "iis2dlpc_reg.h"
cparata	0:13631b50eae6	39
cparata	0:13631b50eae6	40	/**
cparata	0:13631b50eae6	41	* @defgroup IIS2DLPC
cparata	0:13631b50eae6	42	* @brief This file provides a set of functions needed to drive the
cparata	0:13631b50eae6	43	* iis2dlpc enanced inertial module.
cparata	0:13631b50eae6	44	* @{
cparata	0:13631b50eae6	45	*
cparata	0:13631b50eae6	46	*/
cparata	0:13631b50eae6	47
cparata	0:13631b50eae6	48	/**
cparata	0:13631b50eae6	49	* @defgroup IIS2DLPC_Interfaces_Functions
cparata	0:13631b50eae6	50	* @brief This section provide a set of functions used to read and
cparata	0:13631b50eae6	51	* write a generic register of the device.
cparata	0:13631b50eae6	52	* MANDATORY: return 0 -> no Error.
cparata	0:13631b50eae6	53	* @{
cparata	0:13631b50eae6	54	*
cparata	0:13631b50eae6	55	*/
cparata	0:13631b50eae6	56
cparata	0:13631b50eae6	57	/**
cparata	0:13631b50eae6	58	* @brief Read generic device register
cparata	0:13631b50eae6	59	*
cparata	0:13631b50eae6	60	* @param ctx read / write interface definitions(ptr)
cparata	0:13631b50eae6	61	* @param reg register to read
cparata	0:13631b50eae6	62	* @param data pointer to buffer that store the data read(ptr)
cparata	0:13631b50eae6	63	* @param len number of consecutive register to read
cparata	0:13631b50eae6	64	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	65	*
cparata	0:13631b50eae6	66	*/
cparata	0:13631b50eae6	67	int32_t iis2dlpc_read_reg(iis2dlpc_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:13631b50eae6	68	uint16_t len)
cparata	0:13631b50eae6	69	{
cparata	0:13631b50eae6	70	int32_t ret;
cparata	0:13631b50eae6	71	ret = ctx->read_reg(ctx->handle, reg, data, len);
cparata	0:13631b50eae6	72	return ret;
cparata	0:13631b50eae6	73	}
cparata	0:13631b50eae6	74
cparata	0:13631b50eae6	75	/**
cparata	0:13631b50eae6	76	* @brief Write generic device register
cparata	0:13631b50eae6	77	*
cparata	0:13631b50eae6	78	* @param ctx read / write interface definitions(ptr)
cparata	0:13631b50eae6	79	* @param reg register to write
cparata	0:13631b50eae6	80	* @param data pointer to data to write in register reg(ptr)
cparata	0:13631b50eae6	81	* @param len number of consecutive register to write
cparata	0:13631b50eae6	82	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	83	*
cparata	0:13631b50eae6	84	*/
cparata	0:13631b50eae6	85	int32_t iis2dlpc_write_reg(iis2dlpc_ctx_t* ctx, uint8_t reg, uint8_t* data,
cparata	0:13631b50eae6	86	uint16_t len)
cparata	0:13631b50eae6	87	{
cparata	0:13631b50eae6	88	int32_t ret;
cparata	0:13631b50eae6	89	ret = ctx->write_reg(ctx->handle, reg, data, len);
cparata	0:13631b50eae6	90	return ret;
cparata	0:13631b50eae6	91	}
cparata	0:13631b50eae6	92
cparata	0:13631b50eae6	93	/**
cparata	0:13631b50eae6	94	* @}
cparata	0:13631b50eae6	95	*
cparata	0:13631b50eae6	96	*/
cparata	0:13631b50eae6	97
cparata	0:13631b50eae6	98	/**
cparata	0:13631b50eae6	99	* @defgroup IIS2DLPC_Sensitivity
cparata	0:13631b50eae6	100	* @brief These functions convert raw-data into engineering units.
cparata	0:13631b50eae6	101	* @{
cparata	0:13631b50eae6	102	*
cparata	0:13631b50eae6	103	*/
cparata	0:13631b50eae6	104
cparata	0:13631b50eae6	105	float iis2dlpc_from_fs2_to_mg(int16_t lsb)
cparata	0:13631b50eae6	106	{
cparata	0:13631b50eae6	107	return ((float)lsb) * 0.061f;
cparata	0:13631b50eae6	108	}
cparata	0:13631b50eae6	109
cparata	0:13631b50eae6	110	float iis2dlpc_from_fs4_to_mg(int16_t lsb)
cparata	0:13631b50eae6	111	{
cparata	0:13631b50eae6	112	return ((float)lsb) * 0.122f;
cparata	0:13631b50eae6	113	}
cparata	0:13631b50eae6	114
cparata	0:13631b50eae6	115	float iis2dlpc_from_fs8_to_mg(int16_t lsb)
cparata	0:13631b50eae6	116	{
cparata	0:13631b50eae6	117	return ((float)lsb) * 0.244f;
cparata	0:13631b50eae6	118	}
cparata	0:13631b50eae6	119
cparata	0:13631b50eae6	120	float iis2dlpc_from_fs16_to_mg(int16_t lsb)
cparata	0:13631b50eae6	121	{
cparata	0:13631b50eae6	122	return ((float)lsb) *0.488f;
cparata	0:13631b50eae6	123	}
cparata	0:13631b50eae6	124
cparata	0:13631b50eae6	125	float iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb)
cparata	0:13631b50eae6	126	{
cparata	0:13631b50eae6	127	return ((float)lsb) * 0.061f;
cparata	0:13631b50eae6	128	}
cparata	0:13631b50eae6	129
cparata	0:13631b50eae6	130	float iis2dlpc_from_fs4_lp1_to_mg(int16_t lsb)
cparata	0:13631b50eae6	131	{
cparata	0:13631b50eae6	132	return ((float)lsb) * 0.122f;
cparata	0:13631b50eae6	133	}
cparata	0:13631b50eae6	134
cparata	0:13631b50eae6	135	float iis2dlpc_from_fs8_lp1_to_mg(int16_t lsb)
cparata	0:13631b50eae6	136	{
cparata	0:13631b50eae6	137	return ((float)lsb) * 0.244f;
cparata	0:13631b50eae6	138	}
cparata	0:13631b50eae6	139
cparata	0:13631b50eae6	140	float iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb)
cparata	0:13631b50eae6	141	{
cparata	0:13631b50eae6	142	return ((float)lsb) * 0.488f;
cparata	0:13631b50eae6	143	}
cparata	0:13631b50eae6	144
cparata	0:13631b50eae6	145	float iis2dlpc_from_lsb_to_celsius(int16_t lsb)
cparata	0:13631b50eae6	146	{
cparata	0:13631b50eae6	147	return (((float)lsb / 16.0f) + 25.0f);
cparata	0:13631b50eae6	148	}
cparata	0:13631b50eae6	149
cparata	0:13631b50eae6	150	/**
cparata	0:13631b50eae6	151	* @}
cparata	0:13631b50eae6	152	*
cparata	0:13631b50eae6	153	*/
cparata	0:13631b50eae6	154
cparata	0:13631b50eae6	155	/**
cparata	0:13631b50eae6	156	* @defgroup IIS2DLPC_Data_Generation
cparata	0:13631b50eae6	157	* @brief This section groups all the functions concerning
cparata	0:13631b50eae6	158	* data generation
cparata	0:13631b50eae6	159	* @{
cparata	0:13631b50eae6	160	*
cparata	0:13631b50eae6	161	*/
cparata	0:13631b50eae6	162
cparata	0:13631b50eae6	163	/**
cparata	0:13631b50eae6	164	* @brief Select accelerometer operating modes.[set]
cparata	0:13631b50eae6	165	*
cparata	0:13631b50eae6	166	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	167	* @param val change the values of mode / lp_mode in reg CTRL1
cparata	0:13631b50eae6	168	* and low_noise in reg CTRL6
cparata	0:13631b50eae6	169	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	170	*
cparata	0:13631b50eae6	171	*/
cparata	0:13631b50eae6	172	int32_t iis2dlpc_power_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_mode_t val)
cparata	0:13631b50eae6	173	{
cparata	0:13631b50eae6	174	iis2dlpc_ctrl1_t ctrl1;
cparata	0:13631b50eae6	175	iis2dlpc_ctrl6_t ctrl6;
cparata	0:13631b50eae6	176	int32_t ret;
cparata	0:13631b50eae6	177
cparata	0:13631b50eae6	178	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	0:13631b50eae6	179	if (ret == 0) {
cparata	0:13631b50eae6	180	ctrl1.mode = ( (uint8_t) val & 0x0CU ) >> 2;
cparata	0:13631b50eae6	181	ctrl1.lp_mode = (uint8_t) val & 0x03U ;
cparata	0:13631b50eae6	182	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	0:13631b50eae6	183	}
cparata	0:13631b50eae6	184	if (ret == 0) {
cparata	0:13631b50eae6	185	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	0:13631b50eae6	186	}
cparata	0:13631b50eae6	187	if (ret == 0) {
cparata	0:13631b50eae6	188	ctrl6.low_noise = ( (uint8_t) val & 0x10U ) >> 4;
cparata	0:13631b50eae6	189	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	0:13631b50eae6	190	} else {
cparata	0:13631b50eae6	191	ret = ret;
cparata	0:13631b50eae6	192	}
cparata	0:13631b50eae6	193	return ret;
cparata	0:13631b50eae6	194	}
cparata	0:13631b50eae6	195
cparata	0:13631b50eae6	196	/**
cparata	0:13631b50eae6	197	* @brief Select accelerometer operating modes.[get]
cparata	0:13631b50eae6	198	*
cparata	0:13631b50eae6	199	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	200	* @param val change the values of mode / lp_mode in reg CTRL1
cparata	0:13631b50eae6	201	* and low_noise in reg CTRL6
cparata	0:13631b50eae6	202	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	203	*
cparata	0:13631b50eae6	204	*/
cparata	0:13631b50eae6	205	int32_t iis2dlpc_power_mode_get(iis2dlpc_ctx_t ctx, iis2dlpc_mode_t val)
cparata	0:13631b50eae6	206	{
cparata	0:13631b50eae6	207	iis2dlpc_ctrl1_t ctrl1;
cparata	0:13631b50eae6	208	iis2dlpc_ctrl6_t ctrl6;
cparata	0:13631b50eae6	209	int32_t ret;
cparata	0:13631b50eae6	210
cparata	0:13631b50eae6	211	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	0:13631b50eae6	212	if (ret == 0) {
cparata	0:13631b50eae6	213	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	0:13631b50eae6	214
cparata	0:13631b50eae6	215	switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
cparata	0:13631b50eae6	216	ctrl1.lp_mode)) {
cparata	0:13631b50eae6	217	case IIS2DLPC_HIGH_PERFORMANCE:
cparata	0:13631b50eae6	218	*val = IIS2DLPC_HIGH_PERFORMANCE;
cparata	0:13631b50eae6	219	break;
cparata	0:13631b50eae6	220	case IIS2DLPC_CONT_LOW_PWR_4:
cparata	0:13631b50eae6	221	*val = IIS2DLPC_CONT_LOW_PWR_4;
cparata	0:13631b50eae6	222	break;
cparata	0:13631b50eae6	223	case IIS2DLPC_CONT_LOW_PWR_3:
cparata	0:13631b50eae6	224	*val = IIS2DLPC_CONT_LOW_PWR_3;
cparata	0:13631b50eae6	225	break;
cparata	0:13631b50eae6	226	case IIS2DLPC_CONT_LOW_PWR_2:
cparata	0:13631b50eae6	227	*val = IIS2DLPC_CONT_LOW_PWR_2;
cparata	0:13631b50eae6	228	break;
cparata	0:13631b50eae6	229	case IIS2DLPC_CONT_LOW_PWR_12bit:
cparata	0:13631b50eae6	230	*val = IIS2DLPC_CONT_LOW_PWR_12bit;
cparata	0:13631b50eae6	231	break;
cparata	0:13631b50eae6	232	case IIS2DLPC_SINGLE_LOW_PWR_4:
cparata	0:13631b50eae6	233	*val = IIS2DLPC_SINGLE_LOW_PWR_4;
cparata	0:13631b50eae6	234	break;
cparata	0:13631b50eae6	235	case IIS2DLPC_SINGLE_LOW_PWR_3:
cparata	0:13631b50eae6	236	*val = IIS2DLPC_SINGLE_LOW_PWR_3;
cparata	0:13631b50eae6	237	break;
cparata	0:13631b50eae6	238	case IIS2DLPC_SINGLE_LOW_PWR_2:
cparata	0:13631b50eae6	239	*val = IIS2DLPC_SINGLE_LOW_PWR_2;
cparata	0:13631b50eae6	240	break;
cparata	0:13631b50eae6	241	case IIS2DLPC_SINGLE_LOW_PWR_12bit:
cparata	0:13631b50eae6	242	*val = IIS2DLPC_SINGLE_LOW_PWR_12bit;
cparata	0:13631b50eae6	243	break;
cparata	0:13631b50eae6	244	case IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE:
cparata	0:13631b50eae6	245	*val = IIS2DLPC_HIGH_PERFORMANCE_LOW_NOISE;
cparata	0:13631b50eae6	246	break;
cparata	0:13631b50eae6	247	case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4:
cparata	0:13631b50eae6	248	*val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_4;
cparata	0:13631b50eae6	249	break;
cparata	0:13631b50eae6	250	case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3:
cparata	0:13631b50eae6	251	*val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_3;
cparata	0:13631b50eae6	252	break;
cparata	0:13631b50eae6	253	case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2:
cparata	0:13631b50eae6	254	*val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_2;
cparata	0:13631b50eae6	255	break;
cparata	0:13631b50eae6	256	case IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit:
cparata	0:13631b50eae6	257	*val = IIS2DLPC_CONT_LOW_PWR_LOW_NOISE_12bit;
cparata	0:13631b50eae6	258	break;
cparata	0:13631b50eae6	259	case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4:
cparata	0:13631b50eae6	260	*val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_4;
cparata	0:13631b50eae6	261	break;
cparata	0:13631b50eae6	262	case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3:
cparata	0:13631b50eae6	263	*val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_3;
cparata	0:13631b50eae6	264	break;
cparata	0:13631b50eae6	265	case IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2:
cparata	0:13631b50eae6	266	*val = IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2;
cparata	0:13631b50eae6	267	break;
cparata	0:13631b50eae6	268	case IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit:
cparata	0:13631b50eae6	269	*val = IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit;
cparata	0:13631b50eae6	270	break;
cparata	0:13631b50eae6	271	default:
cparata	0:13631b50eae6	272	*val = IIS2DLPC_HIGH_PERFORMANCE;
cparata	0:13631b50eae6	273	break;
cparata	0:13631b50eae6	274	}
cparata	0:13631b50eae6	275	}
cparata	0:13631b50eae6	276	return ret;
cparata	0:13631b50eae6	277	}
cparata	0:13631b50eae6	278
cparata	0:13631b50eae6	279	/**
cparata	0:13631b50eae6	280	* @brief Accelerometer data rate selection.[set]
cparata	0:13631b50eae6	281	*
cparata	0:13631b50eae6	282	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	283	* @param val change the values of odr in reg CTRL1
cparata	0:13631b50eae6	284	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	285	*
cparata	0:13631b50eae6	286	*/
cparata	0:13631b50eae6	287	int32_t iis2dlpc_data_rate_set(iis2dlpc_ctx_t *ctx, iis2dlpc_odr_t val)
cparata	0:13631b50eae6	288	{
cparata	0:13631b50eae6	289	iis2dlpc_ctrl1_t ctrl1;
cparata	0:13631b50eae6	290	iis2dlpc_ctrl3_t ctrl3;
cparata	0:13631b50eae6	291	int32_t ret;
cparata	0:13631b50eae6	292
cparata	0:13631b50eae6	293	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	0:13631b50eae6	294	if (ret == 0) {
cparata	0:13631b50eae6	295	ctrl1.odr = (uint8_t) val;
cparata	0:13631b50eae6	296	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	0:13631b50eae6	297	}
cparata	0:13631b50eae6	298	if (ret == 0) {
cparata	0:13631b50eae6	299	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1);
cparata	0:13631b50eae6	300	}
cparata	0:13631b50eae6	301	if (ret == 0) {
cparata	0:13631b50eae6	302	ctrl3.slp_mode = ( (uint8_t) val & 0x30U ) >> 4;
cparata	0:13631b50eae6	303	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1);
cparata	0:13631b50eae6	304	} else {
cparata	0:13631b50eae6	305	ret = ret;
cparata	0:13631b50eae6	306	}
cparata	0:13631b50eae6	307	return ret;
cparata	0:13631b50eae6	308	}
cparata	0:13631b50eae6	309
cparata	0:13631b50eae6	310	/**
cparata	0:13631b50eae6	311	* @brief Accelerometer data rate selection.[get]
cparata	0:13631b50eae6	312	*
cparata	0:13631b50eae6	313	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	314	* @param val Get the values of odr in reg CTRL1
cparata	0:13631b50eae6	315	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	316	*
cparata	0:13631b50eae6	317	*/
cparata	0:13631b50eae6	318	int32_t iis2dlpc_data_rate_get(iis2dlpc_ctx_t ctx, iis2dlpc_odr_t val)
cparata	0:13631b50eae6	319	{
cparata	0:13631b50eae6	320	iis2dlpc_ctrl1_t ctrl1;
cparata	0:13631b50eae6	321	iis2dlpc_ctrl3_t ctrl3;
cparata	0:13631b50eae6	322	int32_t ret;
cparata	0:13631b50eae6	323
cparata	0:13631b50eae6	324	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1,(uint8_t*) &ctrl1, 1);
cparata	0:13631b50eae6	325	if (ret == 0) {
cparata	0:13631b50eae6	326	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &ctrl3, 1);
cparata	0:13631b50eae6	327
cparata	0:13631b50eae6	328	switch ((ctrl3.slp_mode << 4) + ctrl1.odr) {
cparata	0:13631b50eae6	329	case IIS2DLPC_XL_ODR_OFF:
cparata	0:13631b50eae6	330	*val = IIS2DLPC_XL_ODR_OFF;
cparata	0:13631b50eae6	331	break;
cparata	0:13631b50eae6	332	case IIS2DLPC_XL_ODR_1Hz6_LP_ONLY:
cparata	0:13631b50eae6	333	*val = IIS2DLPC_XL_ODR_1Hz6_LP_ONLY;
cparata	0:13631b50eae6	334	break;
cparata	0:13631b50eae6	335	case IIS2DLPC_XL_ODR_12Hz5:
cparata	0:13631b50eae6	336	*val = IIS2DLPC_XL_ODR_12Hz5;
cparata	0:13631b50eae6	337	break;
cparata	0:13631b50eae6	338	case IIS2DLPC_XL_ODR_25Hz:
cparata	0:13631b50eae6	339	*val = IIS2DLPC_XL_ODR_25Hz;
cparata	0:13631b50eae6	340	break;
cparata	0:13631b50eae6	341	case IIS2DLPC_XL_ODR_50Hz:
cparata	0:13631b50eae6	342	*val = IIS2DLPC_XL_ODR_50Hz;
cparata	0:13631b50eae6	343	break;
cparata	0:13631b50eae6	344	case IIS2DLPC_XL_ODR_100Hz:
cparata	0:13631b50eae6	345	*val = IIS2DLPC_XL_ODR_100Hz;
cparata	0:13631b50eae6	346	break;
cparata	0:13631b50eae6	347	case IIS2DLPC_XL_ODR_200Hz:
cparata	0:13631b50eae6	348	*val = IIS2DLPC_XL_ODR_200Hz;
cparata	0:13631b50eae6	349	break;
cparata	0:13631b50eae6	350	case IIS2DLPC_XL_ODR_400Hz:
cparata	0:13631b50eae6	351	*val = IIS2DLPC_XL_ODR_400Hz;
cparata	0:13631b50eae6	352	break;
cparata	0:13631b50eae6	353	case IIS2DLPC_XL_ODR_800Hz:
cparata	0:13631b50eae6	354	*val = IIS2DLPC_XL_ODR_800Hz;
cparata	0:13631b50eae6	355	break;
cparata	0:13631b50eae6	356	case IIS2DLPC_XL_ODR_1k6Hz:
cparata	0:13631b50eae6	357	*val = IIS2DLPC_XL_ODR_1k6Hz;
cparata	0:13631b50eae6	358	break;
cparata	0:13631b50eae6	359	case IIS2DLPC_XL_SET_SW_TRIG:
cparata	0:13631b50eae6	360	*val = IIS2DLPC_XL_SET_SW_TRIG;
cparata	0:13631b50eae6	361	break;
cparata	0:13631b50eae6	362	case IIS2DLPC_XL_SET_PIN_TRIG:
cparata	0:13631b50eae6	363	*val = IIS2DLPC_XL_SET_PIN_TRIG;
cparata	0:13631b50eae6	364	break;
cparata	0:13631b50eae6	365	default:
cparata	0:13631b50eae6	366	*val = IIS2DLPC_XL_ODR_OFF;
cparata	0:13631b50eae6	367	break;
cparata	0:13631b50eae6	368	}
cparata	0:13631b50eae6	369	}
cparata	0:13631b50eae6	370	return ret;
cparata	0:13631b50eae6	371	}
cparata	0:13631b50eae6	372
cparata	0:13631b50eae6	373	/**
cparata	0:13631b50eae6	374	* @brief Block data update.[set]
cparata	0:13631b50eae6	375	*
cparata	0:13631b50eae6	376	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	377	* @param val change the values of bdu in reg CTRL2
cparata	0:13631b50eae6	378	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	379	*
cparata	0:13631b50eae6	380	*/
cparata	0:13631b50eae6	381	int32_t iis2dlpc_block_data_update_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	382	{
cparata	0:13631b50eae6	383	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	384	int32_t ret;
cparata	0:13631b50eae6	385
cparata	0:13631b50eae6	386	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	387	if (ret == 0) {
cparata	0:13631b50eae6	388	reg.bdu = val;
cparata	0:13631b50eae6	389	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	390	}
cparata	0:13631b50eae6	391	return ret;
cparata	0:13631b50eae6	392	}
cparata	0:13631b50eae6	393
cparata	0:13631b50eae6	394	/**
cparata	0:13631b50eae6	395	* @brief Block data update.[get]
cparata	0:13631b50eae6	396	*
cparata	0:13631b50eae6	397	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	398	* @param val change the values of bdu in reg CTRL2
cparata	0:13631b50eae6	399	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	400	*
cparata	0:13631b50eae6	401	*/
cparata	0:13631b50eae6	402	int32_t iis2dlpc_block_data_update_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	403	{
cparata	0:13631b50eae6	404	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	405	int32_t ret;
cparata	0:13631b50eae6	406
cparata	0:13631b50eae6	407	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	408	*val = reg.bdu;
cparata	0:13631b50eae6	409
cparata	0:13631b50eae6	410	return ret;
cparata	0:13631b50eae6	411	}
cparata	0:13631b50eae6	412
cparata	0:13631b50eae6	413	/**
cparata	0:13631b50eae6	414	* @brief Accelerometer full-scale selection.[set]
cparata	0:13631b50eae6	415	*
cparata	0:13631b50eae6	416	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	417	* @param val change the values of fs in reg CTRL6
cparata	0:13631b50eae6	418	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	419	*
cparata	0:13631b50eae6	420	*/
cparata	0:13631b50eae6	421	int32_t iis2dlpc_full_scale_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fs_t val)
cparata	0:13631b50eae6	422	{
cparata	0:13631b50eae6	423	iis2dlpc_ctrl6_t reg;
cparata	0:13631b50eae6	424	int32_t ret;
cparata	0:13631b50eae6	425
cparata	0:13631b50eae6	426	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	427	if (ret == 0) {
cparata	0:13631b50eae6	428	reg.fs = (uint8_t) val;
cparata	0:13631b50eae6	429	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	430	}
cparata	0:13631b50eae6	431	return ret;
cparata	0:13631b50eae6	432	}
cparata	0:13631b50eae6	433
cparata	0:13631b50eae6	434	/**
cparata	0:13631b50eae6	435	* @brief Accelerometer full-scale selection.[get]
cparata	0:13631b50eae6	436	*
cparata	0:13631b50eae6	437	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	438	* @param val Get the values of fs in reg CTRL6
cparata	0:13631b50eae6	439	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	440	*
cparata	0:13631b50eae6	441	*/
cparata	0:13631b50eae6	442	int32_t iis2dlpc_full_scale_get(iis2dlpc_ctx_t ctx, iis2dlpc_fs_t val)
cparata	0:13631b50eae6	443	{
cparata	0:13631b50eae6	444	iis2dlpc_ctrl6_t reg;
cparata	0:13631b50eae6	445	int32_t ret;
cparata	0:13631b50eae6	446
cparata	0:13631b50eae6	447	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	448
cparata	0:13631b50eae6	449	switch (reg.fs) {
cparata	0:13631b50eae6	450	case IIS2DLPC_2g:
cparata	0:13631b50eae6	451	*val = IIS2DLPC_2g;
cparata	0:13631b50eae6	452	break;
cparata	0:13631b50eae6	453	case IIS2DLPC_4g:
cparata	0:13631b50eae6	454	*val = IIS2DLPC_4g;
cparata	0:13631b50eae6	455	break;
cparata	0:13631b50eae6	456	case IIS2DLPC_8g:
cparata	0:13631b50eae6	457	*val = IIS2DLPC_8g;
cparata	0:13631b50eae6	458	break;
cparata	0:13631b50eae6	459	case IIS2DLPC_16g:
cparata	0:13631b50eae6	460	*val = IIS2DLPC_16g;
cparata	0:13631b50eae6	461	break;
cparata	0:13631b50eae6	462	default:
cparata	0:13631b50eae6	463	*val = IIS2DLPC_2g;
cparata	0:13631b50eae6	464	break;
cparata	0:13631b50eae6	465	}
cparata	0:13631b50eae6	466	return ret;
cparata	0:13631b50eae6	467	}
cparata	0:13631b50eae6	468
cparata	0:13631b50eae6	469	/**
cparata	0:13631b50eae6	470	* @brief The STATUS_REG register of the device.[get]
cparata	0:13631b50eae6	471	*
cparata	0:13631b50eae6	472	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	473	* @param val union of registers from STATUS to
cparata	0:13631b50eae6	474	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	475	*
cparata	0:13631b50eae6	476	*/
cparata	0:13631b50eae6	477	int32_t iis2dlpc_status_reg_get(iis2dlpc_ctx_t ctx, iis2dlpc_status_t val)
cparata	0:13631b50eae6	478	{
cparata	0:13631b50eae6	479	int32_t ret;
cparata	0:13631b50eae6	480	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS, (uint8_t*) val, 1);
cparata	0:13631b50eae6	481	return ret;
cparata	0:13631b50eae6	482	}
cparata	0:13631b50eae6	483
cparata	0:13631b50eae6	484	/**
cparata	0:13631b50eae6	485	* @brief Accelerometer new data available.[get]
cparata	0:13631b50eae6	486	*
cparata	0:13631b50eae6	487	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	488	* @param val change the values of drdy in reg STATUS
cparata	0:13631b50eae6	489	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	490	*
cparata	0:13631b50eae6	491	*/
cparata	0:13631b50eae6	492	int32_t iis2dlpc_flag_data_ready_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	493	{
cparata	0:13631b50eae6	494	iis2dlpc_status_t reg;
cparata	0:13631b50eae6	495	int32_t ret;
cparata	0:13631b50eae6	496
cparata	0:13631b50eae6	497	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	498	*val = reg.drdy;
cparata	0:13631b50eae6	499
cparata	0:13631b50eae6	500	return ret;
cparata	0:13631b50eae6	501	}
cparata	0:13631b50eae6	502	/**
cparata	0:13631b50eae6	503	* @brief Read all the interrupt/status flag of the device.[get]
cparata	0:13631b50eae6	504	*
cparata	0:13631b50eae6	505	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	506	* @param val registers STATUS_DUP, WAKE_UP_SRC,
cparata	0:13631b50eae6	507	* TAP_SRC, SIXD_SRC, ALL_INT_SRC
cparata	0:13631b50eae6	508	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	509	*
cparata	0:13631b50eae6	510	*/
cparata	0:13631b50eae6	511	int32_t iis2dlpc_all_sources_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	512	iis2dlpc_all_sources_t *val)
cparata	0:13631b50eae6	513	{
cparata	0:13631b50eae6	514	int32_t ret;
cparata	0:13631b50eae6	515	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS_DUP, (uint8_t*) val, 5);
cparata	0:13631b50eae6	516	return ret;
cparata	0:13631b50eae6	517	}
cparata	0:13631b50eae6	518
cparata	0:13631b50eae6	519	/**
cparata	0:13631b50eae6	520	* @brief Accelerometer X-axis user offset correction expressed in two’s
cparata	0:13631b50eae6	521	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	0:13631b50eae6	522	* in the range [-127 127].[set]
cparata	0:13631b50eae6	523	*
cparata	0:13631b50eae6	524	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	525	* @param buff buffer that contains data to write
cparata	0:13631b50eae6	526	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	527	*
cparata	0:13631b50eae6	528	*/
cparata	0:13631b50eae6	529	int32_t iis2dlpc_usr_offset_x_set(iis2dlpc_ctx_t ctx, uint8_t buff)
cparata	0:13631b50eae6	530	{
cparata	0:13631b50eae6	531	int32_t ret;
cparata	0:13631b50eae6	532	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1);
cparata	0:13631b50eae6	533	return ret;
cparata	0:13631b50eae6	534	}
cparata	0:13631b50eae6	535
cparata	0:13631b50eae6	536	/**
cparata	0:13631b50eae6	537	* @brief Accelerometer X-axis user offset correction expressed in two’s
cparata	0:13631b50eae6	538	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	0:13631b50eae6	539	* in the range [-127 127].[get]
cparata	0:13631b50eae6	540	*
cparata	0:13631b50eae6	541	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	542	* @param buff buffer that stores data read
cparata	0:13631b50eae6	543	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	544	*
cparata	0:13631b50eae6	545	*/
cparata	0:13631b50eae6	546	int32_t iis2dlpc_usr_offset_x_get(iis2dlpc_ctx_t ctx, uint8_t buff)
cparata	0:13631b50eae6	547	{
cparata	0:13631b50eae6	548	int32_t ret;
cparata	0:13631b50eae6	549	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_X_OFS_USR, buff, 1);
cparata	0:13631b50eae6	550	return ret;
cparata	0:13631b50eae6	551	}
cparata	0:13631b50eae6	552
cparata	0:13631b50eae6	553	/**
cparata	0:13631b50eae6	554	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:13631b50eae6	555	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	0:13631b50eae6	556	* in the range [-127 127].[set]
cparata	0:13631b50eae6	557	*
cparata	0:13631b50eae6	558	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	559	* @param buff buffer that contains data to write
cparata	0:13631b50eae6	560	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	561	*
cparata	0:13631b50eae6	562	*/
cparata	0:13631b50eae6	563	int32_t iis2dlpc_usr_offset_y_set(iis2dlpc_ctx_t ctx, uint8_t buff)
cparata	0:13631b50eae6	564	{
cparata	0:13631b50eae6	565	int32_t ret;
cparata	0:13631b50eae6	566	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1);
cparata	0:13631b50eae6	567	return ret;
cparata	0:13631b50eae6	568	}
cparata	0:13631b50eae6	569
cparata	0:13631b50eae6	570	/**
cparata	0:13631b50eae6	571	* @brief Accelerometer Y-axis user offset correction expressed in two’s
cparata	0:13631b50eae6	572	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	0:13631b50eae6	573	* in the range [-127 127].[get]
cparata	0:13631b50eae6	574	*
cparata	0:13631b50eae6	575	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	576	* @param buff buffer that stores data read
cparata	0:13631b50eae6	577	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	578	*
cparata	0:13631b50eae6	579	*/
cparata	0:13631b50eae6	580	int32_t iis2dlpc_usr_offset_y_get(iis2dlpc_ctx_t ctx, uint8_t buff)
cparata	0:13631b50eae6	581	{
cparata	0:13631b50eae6	582	int32_t ret;
cparata	0:13631b50eae6	583	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Y_OFS_USR, buff, 1);
cparata	0:13631b50eae6	584	return ret;
cparata	0:13631b50eae6	585	}
cparata	0:13631b50eae6	586
cparata	0:13631b50eae6	587	/**
cparata	0:13631b50eae6	588	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:13631b50eae6	589	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	0:13631b50eae6	590	* in the range [-127 127].[set]
cparata	0:13631b50eae6	591	*
cparata	0:13631b50eae6	592	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	593	* @param buff buffer that contains data to write
cparata	0:13631b50eae6	594	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	595	*
cparata	0:13631b50eae6	596	*/
cparata	0:13631b50eae6	597	int32_t iis2dlpc_usr_offset_z_set(iis2dlpc_ctx_t ctx, uint8_t buff)
cparata	0:13631b50eae6	598	{
cparata	0:13631b50eae6	599	int32_t ret;
cparata	0:13631b50eae6	600	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1);
cparata	0:13631b50eae6	601	return ret;
cparata	0:13631b50eae6	602	}
cparata	0:13631b50eae6	603
cparata	0:13631b50eae6	604	/**
cparata	0:13631b50eae6	605	* @brief Accelerometer Z-axis user offset correction expressed in two’s
cparata	0:13631b50eae6	606	* complement, weight depends on bit USR_OFF_W. The value must be
cparata	0:13631b50eae6	607	* in the range [-127 127].[get]
cparata	0:13631b50eae6	608	*
cparata	0:13631b50eae6	609	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	610	* @param buff buffer that stores data read
cparata	0:13631b50eae6	611	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	612	*
cparata	0:13631b50eae6	613	*/
cparata	0:13631b50eae6	614	int32_t iis2dlpc_usr_offset_z_get(iis2dlpc_ctx_t ctx, uint8_t buff)
cparata	0:13631b50eae6	615	{
cparata	0:13631b50eae6	616	int32_t ret;
cparata	0:13631b50eae6	617	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_Z_OFS_USR, buff, 1);
cparata	0:13631b50eae6	618	return ret;
cparata	0:13631b50eae6	619	}
cparata	0:13631b50eae6	620
cparata	0:13631b50eae6	621	/**
cparata	0:13631b50eae6	622	* @brief Weight of XL user offset bits of registers X_OFS_USR,
cparata	0:13631b50eae6	623	* Y_OFS_USR, Z_OFS_USR.[set]
cparata	0:13631b50eae6	624	*
cparata	0:13631b50eae6	625	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	626	* @param val change the values of usr_off_w in
cparata	0:13631b50eae6	627	* reg CTRL_REG7
cparata	0:13631b50eae6	628	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	629	*
cparata	0:13631b50eae6	630	*/
cparata	0:13631b50eae6	631	int32_t iis2dlpc_offset_weight_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	632	iis2dlpc_usr_off_w_t val)
cparata	0:13631b50eae6	633	{
cparata	0:13631b50eae6	634	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	635	int32_t ret;
cparata	0:13631b50eae6	636
cparata	0:13631b50eae6	637	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	638	if (ret == 0) {
cparata	0:13631b50eae6	639	reg.usr_off_w = (uint8_t) val;
cparata	0:13631b50eae6	640	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	641	}
cparata	0:13631b50eae6	642	return ret;
cparata	0:13631b50eae6	643	}
cparata	0:13631b50eae6	644
cparata	0:13631b50eae6	645	/**
cparata	0:13631b50eae6	646	* @brief Weight of XL user offset bits of registers X_OFS_USR,
cparata	0:13631b50eae6	647	* Y_OFS_USR, Z_OFS_USR.[get]
cparata	0:13631b50eae6	648	*
cparata	0:13631b50eae6	649	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	650	* @param val Get the values of usr_off_w in reg CTRL_REG7
cparata	0:13631b50eae6	651	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	652	*
cparata	0:13631b50eae6	653	*/
cparata	0:13631b50eae6	654	int32_t iis2dlpc_offset_weight_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	655	iis2dlpc_usr_off_w_t *val)
cparata	0:13631b50eae6	656	{
cparata	0:13631b50eae6	657	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	658	int32_t ret;
cparata	0:13631b50eae6	659
cparata	0:13631b50eae6	660	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	661	switch (reg.usr_off_w) {
cparata	0:13631b50eae6	662	case IIS2DLPC_LSb_977ug:
cparata	0:13631b50eae6	663	*val = IIS2DLPC_LSb_977ug;
cparata	0:13631b50eae6	664	break;
cparata	0:13631b50eae6	665	case IIS2DLPC_LSb_15mg6:
cparata	0:13631b50eae6	666	*val = IIS2DLPC_LSb_15mg6;
cparata	0:13631b50eae6	667	break;
cparata	0:13631b50eae6	668	default:
cparata	0:13631b50eae6	669	*val = IIS2DLPC_LSb_977ug;
cparata	0:13631b50eae6	670	break;
cparata	0:13631b50eae6	671	}
cparata	0:13631b50eae6	672	return ret;
cparata	0:13631b50eae6	673	}
cparata	0:13631b50eae6	674
cparata	0:13631b50eae6	675	/**
cparata	0:13631b50eae6	676	* @}
cparata	0:13631b50eae6	677	*
cparata	0:13631b50eae6	678	*/
cparata	0:13631b50eae6	679
cparata	0:13631b50eae6	680	/**
cparata	0:13631b50eae6	681	* @defgroup IIS2DLPC_Data_Output
cparata	0:13631b50eae6	682	* @brief This section groups all the data output functions.
cparata	0:13631b50eae6	683	* @{
cparata	0:13631b50eae6	684	*
cparata	0:13631b50eae6	685	*/
cparata	0:13631b50eae6	686
cparata	0:13631b50eae6	687	/**
cparata	0:13631b50eae6	688	* @brief Temperature data output register (r). L and H registers
cparata	0:13631b50eae6	689	* together express a 16-bit word in two’s complement.[get]
cparata	0:13631b50eae6	690	*
cparata	0:13631b50eae6	691	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	692	* @param buff buffer that stores data read
cparata	0:13631b50eae6	693	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	694	*
cparata	0:13631b50eae6	695	*/
cparata	0:13631b50eae6	696	int32_t iis2dlpc_temperature_raw_get(iis2dlpc_ctx_t ctx, uint8_t buff)
cparata	0:13631b50eae6	697	{
cparata	0:13631b50eae6	698	int32_t ret;
cparata	0:13631b50eae6	699	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_T_L, buff, 2);
cparata	0:13631b50eae6	700	return ret;
cparata	0:13631b50eae6	701	}
cparata	0:13631b50eae6	702
cparata	0:13631b50eae6	703	/**
cparata	0:13631b50eae6	704	* @brief Linear acceleration output register. The value is expressed as
cparata	0:13631b50eae6	705	* a 16-bit word in two’s complement.[get]
cparata	0:13631b50eae6	706	*
cparata	0:13631b50eae6	707	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	708	* @param buff buffer that stores data read
cparata	0:13631b50eae6	709	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	710	*
cparata	0:13631b50eae6	711	*/
cparata	0:13631b50eae6	712	int32_t iis2dlpc_acceleration_raw_get(iis2dlpc_ctx_t ctx, uint8_t buff)
cparata	0:13631b50eae6	713	{
cparata	0:13631b50eae6	714	int32_t ret;
cparata	0:13631b50eae6	715	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_X_L, buff, 6);
cparata	0:13631b50eae6	716	return ret;
cparata	0:13631b50eae6	717	}
cparata	0:13631b50eae6	718
cparata	0:13631b50eae6	719	/**
cparata	0:13631b50eae6	720	* @}
cparata	0:13631b50eae6	721	*
cparata	0:13631b50eae6	722	*/
cparata	0:13631b50eae6	723
cparata	0:13631b50eae6	724	/**
cparata	0:13631b50eae6	725	* @defgroup IIS2DLPC_Common
cparata	0:13631b50eae6	726	* @brief This section groups common useful functions.
cparata	0:13631b50eae6	727	* @{
cparata	0:13631b50eae6	728	*
cparata	0:13631b50eae6	729	*/
cparata	0:13631b50eae6	730
cparata	0:13631b50eae6	731	/**
cparata	0:13631b50eae6	732	* @brief Device Who am I.[get]
cparata	0:13631b50eae6	733	*
cparata	0:13631b50eae6	734	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	735	* @param buff buffer that stores data read
cparata	0:13631b50eae6	736	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	737	*
cparata	0:13631b50eae6	738	*/
cparata	0:13631b50eae6	739	int32_t iis2dlpc_device_id_get(iis2dlpc_ctx_t ctx, uint8_t buff)
cparata	0:13631b50eae6	740	{
cparata	0:13631b50eae6	741	int32_t ret;
cparata	0:13631b50eae6	742	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WHO_AM_I, buff, 1);
cparata	0:13631b50eae6	743	return ret;
cparata	0:13631b50eae6	744	}
cparata	0:13631b50eae6	745
cparata	0:13631b50eae6	746	/**
cparata	0:13631b50eae6	747	* @brief Register address automatically incremented during multiple byte
cparata	0:13631b50eae6	748	* access with a serial interface.[set]
cparata	0:13631b50eae6	749	*
cparata	0:13631b50eae6	750	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	751	* @param val change the values of if_add_inc in reg CTRL2
cparata	0:13631b50eae6	752	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	753	*
cparata	0:13631b50eae6	754	*/
cparata	0:13631b50eae6	755	int32_t iis2dlpc_auto_increment_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	756	{
cparata	0:13631b50eae6	757	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	758	int32_t ret;
cparata	0:13631b50eae6	759
cparata	0:13631b50eae6	760	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	761	if (ret == 0) {
cparata	0:13631b50eae6	762	reg.if_add_inc = val;
cparata	0:13631b50eae6	763	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	764	}
cparata	0:13631b50eae6	765	return ret;
cparata	0:13631b50eae6	766	}
cparata	0:13631b50eae6	767
cparata	0:13631b50eae6	768	/**
cparata	0:13631b50eae6	769	* @brief Register address automatically incremented during multiple
cparata	0:13631b50eae6	770	* byte access with a serial interface.[get]
cparata	0:13631b50eae6	771	*
cparata	0:13631b50eae6	772	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	773	* @param val change the values of if_add_inc in reg CTRL2
cparata	0:13631b50eae6	774	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	775	*
cparata	0:13631b50eae6	776	*/
cparata	0:13631b50eae6	777	int32_t iis2dlpc_auto_increment_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	778	{
cparata	0:13631b50eae6	779	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	780	int32_t ret;
cparata	0:13631b50eae6	781
cparata	0:13631b50eae6	782	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	783	*val = reg.if_add_inc;
cparata	0:13631b50eae6	784
cparata	0:13631b50eae6	785	return ret;
cparata	0:13631b50eae6	786	}
cparata	0:13631b50eae6	787
cparata	0:13631b50eae6	788	/**
cparata	0:13631b50eae6	789	* @brief Software reset. Restore the default values in user registers.[set]
cparata	0:13631b50eae6	790	*
cparata	0:13631b50eae6	791	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	792	* @param val change the values of soft_reset in reg CTRL2
cparata	0:13631b50eae6	793	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	794	*
cparata	0:13631b50eae6	795	*/
cparata	0:13631b50eae6	796	int32_t iis2dlpc_reset_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	797	{
cparata	0:13631b50eae6	798	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	799	int32_t ret;
cparata	0:13631b50eae6	800
cparata	0:13631b50eae6	801	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	802	if (ret == 0) {
cparata	0:13631b50eae6	803	reg.soft_reset = val;
cparata	0:13631b50eae6	804	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	805	}
cparata	0:13631b50eae6	806
cparata	0:13631b50eae6	807	return ret;
cparata	0:13631b50eae6	808	}
cparata	0:13631b50eae6	809
cparata	0:13631b50eae6	810	/**
cparata	0:13631b50eae6	811	* @brief Software reset. Restore the default values in user registers.[get]
cparata	0:13631b50eae6	812	*
cparata	0:13631b50eae6	813	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	814	* @param val change the values of soft_reset in reg CTRL2
cparata	0:13631b50eae6	815	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	816	*
cparata	0:13631b50eae6	817	*/
cparata	0:13631b50eae6	818	int32_t iis2dlpc_reset_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	819	{
cparata	0:13631b50eae6	820	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	821	int32_t ret;
cparata	0:13631b50eae6	822
cparata	0:13631b50eae6	823	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	824	*val = reg.soft_reset;
cparata	0:13631b50eae6	825
cparata	0:13631b50eae6	826	return ret;
cparata	0:13631b50eae6	827	}
cparata	0:13631b50eae6	828
cparata	0:13631b50eae6	829	/**
cparata	0:13631b50eae6	830	* @brief Reboot memory content. Reload the calibration parameters.[set]
cparata	0:13631b50eae6	831	*
cparata	0:13631b50eae6	832	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	833	* @param val change the values of boot in reg CTRL2
cparata	0:13631b50eae6	834	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	835	*
cparata	0:13631b50eae6	836	*/
cparata	0:13631b50eae6	837	int32_t iis2dlpc_boot_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	838	{
cparata	0:13631b50eae6	839	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	840	int32_t ret;
cparata	0:13631b50eae6	841
cparata	0:13631b50eae6	842	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	843	if (ret == 0) {
cparata	0:13631b50eae6	844	reg.boot = val;
cparata	0:13631b50eae6	845	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	846	}
cparata	0:13631b50eae6	847	return ret;
cparata	0:13631b50eae6	848	}
cparata	0:13631b50eae6	849
cparata	0:13631b50eae6	850	/**
cparata	0:13631b50eae6	851	* @brief Reboot memory content. Reload the calibration parameters.[get]
cparata	0:13631b50eae6	852	*
cparata	0:13631b50eae6	853	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	854	* @param val change the values of boot in reg CTRL2
cparata	0:13631b50eae6	855	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	856	*
cparata	0:13631b50eae6	857	*/
cparata	0:13631b50eae6	858	int32_t iis2dlpc_boot_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	859	{
cparata	0:13631b50eae6	860	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	861	int32_t ret;
cparata	0:13631b50eae6	862
cparata	0:13631b50eae6	863	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	864	*val = reg.boot;
cparata	0:13631b50eae6	865
cparata	0:13631b50eae6	866	return ret;
cparata	0:13631b50eae6	867	}
cparata	0:13631b50eae6	868
cparata	0:13631b50eae6	869	/**
cparata	0:13631b50eae6	870	* @brief Sensor self-test enable.[set]
cparata	0:13631b50eae6	871	*
cparata	0:13631b50eae6	872	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	873	* @param val change the values of st in reg CTRL3
cparata	0:13631b50eae6	874	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	875	*
cparata	0:13631b50eae6	876	*/
cparata	0:13631b50eae6	877	int32_t iis2dlpc_self_test_set(iis2dlpc_ctx_t *ctx, iis2dlpc_st_t val)
cparata	0:13631b50eae6	878	{
cparata	0:13631b50eae6	879	iis2dlpc_ctrl3_t reg;
cparata	0:13631b50eae6	880	int32_t ret;
cparata	0:13631b50eae6	881
cparata	0:13631b50eae6	882	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	883	if (ret == 0) {
cparata	0:13631b50eae6	884	reg.st = (uint8_t) val;
cparata	0:13631b50eae6	885	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	886	}
cparata	0:13631b50eae6	887
cparata	0:13631b50eae6	888	return ret;
cparata	0:13631b50eae6	889	}
cparata	0:13631b50eae6	890
cparata	0:13631b50eae6	891	/**
cparata	0:13631b50eae6	892	* @brief Sensor self-test enable.[get]
cparata	0:13631b50eae6	893	*
cparata	0:13631b50eae6	894	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	895	* @param val Get the values of st in reg CTRL3
cparata	0:13631b50eae6	896	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	897	*
cparata	0:13631b50eae6	898	*/
cparata	0:13631b50eae6	899	int32_t iis2dlpc_self_test_get(iis2dlpc_ctx_t ctx, iis2dlpc_st_t val)
cparata	0:13631b50eae6	900	{
cparata	0:13631b50eae6	901	iis2dlpc_ctrl3_t reg;
cparata	0:13631b50eae6	902	int32_t ret;
cparata	0:13631b50eae6	903
cparata	0:13631b50eae6	904	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	905
cparata	0:13631b50eae6	906	switch (reg.st) {
cparata	0:13631b50eae6	907	case IIS2DLPC_XL_ST_DISABLE:
cparata	0:13631b50eae6	908	*val = IIS2DLPC_XL_ST_DISABLE;
cparata	0:13631b50eae6	909	break;
cparata	0:13631b50eae6	910	case IIS2DLPC_XL_ST_POSITIVE:
cparata	0:13631b50eae6	911	*val = IIS2DLPC_XL_ST_POSITIVE;
cparata	0:13631b50eae6	912	break;
cparata	0:13631b50eae6	913	case IIS2DLPC_XL_ST_NEGATIVE:
cparata	0:13631b50eae6	914	*val = IIS2DLPC_XL_ST_NEGATIVE;
cparata	0:13631b50eae6	915	break;
cparata	0:13631b50eae6	916	default:
cparata	0:13631b50eae6	917	*val = IIS2DLPC_XL_ST_DISABLE;
cparata	0:13631b50eae6	918	break;
cparata	0:13631b50eae6	919	}
cparata	0:13631b50eae6	920	return ret;
cparata	0:13631b50eae6	921	}
cparata	0:13631b50eae6	922
cparata	0:13631b50eae6	923	/**
cparata	0:13631b50eae6	924	* @brief Data-ready pulsed / letched mode.[set]
cparata	0:13631b50eae6	925	*
cparata	0:13631b50eae6	926	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	927	* @param val change the values of drdy_pulsed in reg CTRL_REG7
cparata	0:13631b50eae6	928	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	929	*
cparata	0:13631b50eae6	930	*/
cparata	0:13631b50eae6	931	int32_t iis2dlpc_data_ready_mode_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	932	iis2dlpc_drdy_pulsed_t val)
cparata	0:13631b50eae6	933	{
cparata	0:13631b50eae6	934	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	935	int32_t ret;
cparata	0:13631b50eae6	936
cparata	0:13631b50eae6	937	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	938	if (ret == 0) {
cparata	0:13631b50eae6	939	reg.drdy_pulsed = (uint8_t) val;
cparata	0:13631b50eae6	940	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	941	}
cparata	0:13631b50eae6	942
cparata	0:13631b50eae6	943	return ret;
cparata	0:13631b50eae6	944	}
cparata	0:13631b50eae6	945
cparata	0:13631b50eae6	946	/**
cparata	0:13631b50eae6	947	* @brief Data-ready pulsed / letched mode.[get]
cparata	0:13631b50eae6	948	*
cparata	0:13631b50eae6	949	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	950	* @param val Get the values of drdy_pulsed in reg CTRL_REG7
cparata	0:13631b50eae6	951	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	952	*
cparata	0:13631b50eae6	953	*/
cparata	0:13631b50eae6	954	int32_t iis2dlpc_data_ready_mode_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	955	iis2dlpc_drdy_pulsed_t *val)
cparata	0:13631b50eae6	956	{
cparata	0:13631b50eae6	957	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	958	int32_t ret;
cparata	0:13631b50eae6	959
cparata	0:13631b50eae6	960	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	961
cparata	0:13631b50eae6	962	switch (reg.drdy_pulsed) {
cparata	0:13631b50eae6	963	case IIS2DLPC_DRDY_LATCHED:
cparata	0:13631b50eae6	964	*val = IIS2DLPC_DRDY_LATCHED;
cparata	0:13631b50eae6	965	break;
cparata	0:13631b50eae6	966	case IIS2DLPC_DRDY_PULSED:
cparata	0:13631b50eae6	967	*val = IIS2DLPC_DRDY_PULSED;
cparata	0:13631b50eae6	968	break;
cparata	0:13631b50eae6	969	default:
cparata	0:13631b50eae6	970	*val = IIS2DLPC_DRDY_LATCHED;
cparata	0:13631b50eae6	971	break;
cparata	0:13631b50eae6	972	}
cparata	0:13631b50eae6	973	return ret;
cparata	0:13631b50eae6	974	}
cparata	0:13631b50eae6	975
cparata	0:13631b50eae6	976	/**
cparata	0:13631b50eae6	977	* @}
cparata	0:13631b50eae6	978	*
cparata	0:13631b50eae6	979	*/
cparata	0:13631b50eae6	980
cparata	0:13631b50eae6	981	/**
cparata	0:13631b50eae6	982	* @defgroup IIS2DLPC_Filters
cparata	0:13631b50eae6	983	* @brief This section group all the functions concerning the filters
cparata	0:13631b50eae6	984	* configuration.
cparata	0:13631b50eae6	985	* @{
cparata	0:13631b50eae6	986	*
cparata	0:13631b50eae6	987	*/
cparata	0:13631b50eae6	988
cparata	0:13631b50eae6	989	/**
cparata	0:13631b50eae6	990	* @brief Accelerometer filtering path for outputs.[set]
cparata	0:13631b50eae6	991	*
cparata	0:13631b50eae6	992	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	993	* @param val change the values of fds in reg CTRL6
cparata	0:13631b50eae6	994	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	995	*
cparata	0:13631b50eae6	996	*/
cparata	0:13631b50eae6	997	int32_t iis2dlpc_filter_path_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fds_t val)
cparata	0:13631b50eae6	998	{
cparata	0:13631b50eae6	999	iis2dlpc_ctrl6_t ctrl6;
cparata	0:13631b50eae6	1000	iis2dlpc_ctrl_reg7_t ctrl_reg7;
cparata	0:13631b50eae6	1001	int32_t ret;
cparata	0:13631b50eae6	1002
cparata	0:13631b50eae6	1003	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	0:13631b50eae6	1004	if (ret == 0) {
cparata	0:13631b50eae6	1005	ctrl6.fds = ( (uint8_t) val & 0x10U ) >> 4;
cparata	0:13631b50eae6	1006	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	0:13631b50eae6	1007	}
cparata	0:13631b50eae6	1008	if (ret == 0) {
cparata	0:13631b50eae6	1009	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
cparata	0:13631b50eae6	1010	}
cparata	0:13631b50eae6	1011	if (ret == 0) {
cparata	0:13631b50eae6	1012	ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
cparata	0:13631b50eae6	1013	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
cparata	0:13631b50eae6	1014	} else {
cparata	0:13631b50eae6	1015	ret = ret;
cparata	0:13631b50eae6	1016	}
cparata	0:13631b50eae6	1017	return ret;
cparata	0:13631b50eae6	1018	}
cparata	0:13631b50eae6	1019
cparata	0:13631b50eae6	1020	/**
cparata	0:13631b50eae6	1021	* @brief Accelerometer filtering path for outputs.[get]
cparata	0:13631b50eae6	1022	*
cparata	0:13631b50eae6	1023	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1024	* @param val Get the values of fds in reg CTRL6
cparata	0:13631b50eae6	1025	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1026	*
cparata	0:13631b50eae6	1027	*/
cparata	0:13631b50eae6	1028	int32_t iis2dlpc_filter_path_get(iis2dlpc_ctx_t ctx, iis2dlpc_fds_t val)
cparata	0:13631b50eae6	1029	{
cparata	0:13631b50eae6	1030	iis2dlpc_ctrl6_t ctrl6;
cparata	0:13631b50eae6	1031	iis2dlpc_ctrl_reg7_t ctrl_reg7;
cparata	0:13631b50eae6	1032	int32_t ret;
cparata	0:13631b50eae6	1033
cparata	0:13631b50eae6	1034	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &ctrl6, 1);
cparata	0:13631b50eae6	1035	if (ret == 0) {
cparata	0:13631b50eae6	1036	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &ctrl_reg7, 1);
cparata	0:13631b50eae6	1037
cparata	0:13631b50eae6	1038	switch ((ctrl6.fds << 4 ) + ctrl_reg7.usr_off_on_out) {
cparata	0:13631b50eae6	1039	case IIS2DLPC_LPF_ON_OUT:
cparata	0:13631b50eae6	1040	*val = IIS2DLPC_LPF_ON_OUT;
cparata	0:13631b50eae6	1041	break;
cparata	0:13631b50eae6	1042	case IIS2DLPC_USER_OFFSET_ON_OUT:
cparata	0:13631b50eae6	1043	*val = IIS2DLPC_USER_OFFSET_ON_OUT;
cparata	0:13631b50eae6	1044	break;
cparata	0:13631b50eae6	1045	case IIS2DLPC_HIGH_PASS_ON_OUT:
cparata	0:13631b50eae6	1046	*val = IIS2DLPC_HIGH_PASS_ON_OUT;
cparata	0:13631b50eae6	1047	break;
cparata	0:13631b50eae6	1048	default:
cparata	0:13631b50eae6	1049	*val = IIS2DLPC_LPF_ON_OUT;
cparata	0:13631b50eae6	1050	break;
cparata	0:13631b50eae6	1051	}
cparata	0:13631b50eae6	1052	}
cparata	0:13631b50eae6	1053	return ret;
cparata	0:13631b50eae6	1054	}
cparata	0:13631b50eae6	1055
cparata	0:13631b50eae6	1056	/**
cparata	0:13631b50eae6	1057	* @brief Accelerometer cutoff filter frequency. Valid for low and high
cparata	0:13631b50eae6	1058	* pass filter.[set]
cparata	0:13631b50eae6	1059	*
cparata	0:13631b50eae6	1060	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1061	* @param val change the values of bw_filt in reg CTRL6
cparata	0:13631b50eae6	1062	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1063	*
cparata	0:13631b50eae6	1064	*/
cparata	0:13631b50eae6	1065	int32_t iis2dlpc_filter_bandwidth_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1066	iis2dlpc_bw_filt_t val)
cparata	0:13631b50eae6	1067	{
cparata	0:13631b50eae6	1068	iis2dlpc_ctrl6_t reg;
cparata	0:13631b50eae6	1069	int32_t ret;
cparata	0:13631b50eae6	1070
cparata	0:13631b50eae6	1071	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1072	if (ret == 0) {
cparata	0:13631b50eae6	1073	reg.bw_filt = (uint8_t) val;
cparata	0:13631b50eae6	1074	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1075	}
cparata	0:13631b50eae6	1076
cparata	0:13631b50eae6	1077	return ret;
cparata	0:13631b50eae6	1078	}
cparata	0:13631b50eae6	1079
cparata	0:13631b50eae6	1080	/**
cparata	0:13631b50eae6	1081	* @brief Accelerometer cutoff filter frequency. Valid for low and
cparata	0:13631b50eae6	1082	* high pass filter.[get]
cparata	0:13631b50eae6	1083	*
cparata	0:13631b50eae6	1084	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1085	* @param val Get the values of bw_filt in reg CTRL6
cparata	0:13631b50eae6	1086	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1087	*
cparata	0:13631b50eae6	1088	*/
cparata	0:13631b50eae6	1089	int32_t iis2dlpc_filter_bandwidth_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1090	iis2dlpc_bw_filt_t *val)
cparata	0:13631b50eae6	1091	{
cparata	0:13631b50eae6	1092	iis2dlpc_ctrl6_t reg;
cparata	0:13631b50eae6	1093	int32_t ret;
cparata	0:13631b50eae6	1094
cparata	0:13631b50eae6	1095	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1096
cparata	0:13631b50eae6	1097	switch (reg.bw_filt) {
cparata	0:13631b50eae6	1098	case IIS2DLPC_ODR_DIV_2:
cparata	0:13631b50eae6	1099	*val = IIS2DLPC_ODR_DIV_2;
cparata	0:13631b50eae6	1100	break;
cparata	0:13631b50eae6	1101	case IIS2DLPC_ODR_DIV_4:
cparata	0:13631b50eae6	1102	*val = IIS2DLPC_ODR_DIV_4;
cparata	0:13631b50eae6	1103	break;
cparata	0:13631b50eae6	1104	case IIS2DLPC_ODR_DIV_10:
cparata	0:13631b50eae6	1105	*val = IIS2DLPC_ODR_DIV_10;
cparata	0:13631b50eae6	1106	break;
cparata	0:13631b50eae6	1107	case IIS2DLPC_ODR_DIV_20:
cparata	0:13631b50eae6	1108	*val = IIS2DLPC_ODR_DIV_20;
cparata	0:13631b50eae6	1109	break;
cparata	0:13631b50eae6	1110	default:
cparata	0:13631b50eae6	1111	*val = IIS2DLPC_ODR_DIV_2;
cparata	0:13631b50eae6	1112	break;
cparata	0:13631b50eae6	1113	}
cparata	0:13631b50eae6	1114	return ret;
cparata	0:13631b50eae6	1115	}
cparata	0:13631b50eae6	1116
cparata	0:13631b50eae6	1117	/**
cparata	0:13631b50eae6	1118	* @brief Enable HP filter reference mode.[set]
cparata	0:13631b50eae6	1119	*
cparata	0:13631b50eae6	1120	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1121	* @param val change the values of hp_ref_mode in reg CTRL_REG7
cparata	0:13631b50eae6	1122	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1123	*
cparata	0:13631b50eae6	1124	*/
cparata	0:13631b50eae6	1125	int32_t iis2dlpc_reference_mode_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	1126	{
cparata	0:13631b50eae6	1127	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	1128	int32_t ret;
cparata	0:13631b50eae6	1129
cparata	0:13631b50eae6	1130	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1131	if (ret == 0) {
cparata	0:13631b50eae6	1132	reg.hp_ref_mode = val;
cparata	0:13631b50eae6	1133	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1134	}
cparata	0:13631b50eae6	1135	return ret;
cparata	0:13631b50eae6	1136	}
cparata	0:13631b50eae6	1137
cparata	0:13631b50eae6	1138	/**
cparata	0:13631b50eae6	1139	* @brief Enable HP filter reference mode.[get]
cparata	0:13631b50eae6	1140	*
cparata	0:13631b50eae6	1141	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1142	* @param val change the values of hp_ref_mode in reg CTRL_REG7
cparata	0:13631b50eae6	1143	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1144	*
cparata	0:13631b50eae6	1145	*/
cparata	0:13631b50eae6	1146	int32_t iis2dlpc_reference_mode_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	1147	{
cparata	0:13631b50eae6	1148	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	1149	int32_t ret;
cparata	0:13631b50eae6	1150
cparata	0:13631b50eae6	1151	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1152	*val = reg.hp_ref_mode;
cparata	0:13631b50eae6	1153
cparata	0:13631b50eae6	1154	return ret;
cparata	0:13631b50eae6	1155	}
cparata	0:13631b50eae6	1156
cparata	0:13631b50eae6	1157	/**
cparata	0:13631b50eae6	1158	* @}
cparata	0:13631b50eae6	1159	*
cparata	0:13631b50eae6	1160	*/
cparata	0:13631b50eae6	1161
cparata	0:13631b50eae6	1162	/**
cparata	0:13631b50eae6	1163	* @defgroup IIS2DLPC_Serial_Interface
cparata	0:13631b50eae6	1164	* @brief This section groups all the functions concerning main serial
cparata	0:13631b50eae6	1165	* interface management (not auxiliary)
cparata	0:13631b50eae6	1166	* @{
cparata	0:13631b50eae6	1167	*
cparata	0:13631b50eae6	1168	*/
cparata	0:13631b50eae6	1169
cparata	0:13631b50eae6	1170	/**
cparata	0:13631b50eae6	1171	* @brief SPI Serial Interface Mode selection.[set]
cparata	0:13631b50eae6	1172	*
cparata	0:13631b50eae6	1173	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1174	* @param val change the values of sim in reg CTRL2
cparata	0:13631b50eae6	1175	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1176	*
cparata	0:13631b50eae6	1177	*/
cparata	0:13631b50eae6	1178	int32_t iis2dlpc_spi_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_sim_t val)
cparata	0:13631b50eae6	1179	{
cparata	0:13631b50eae6	1180	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	1181	int32_t ret;
cparata	0:13631b50eae6	1182
cparata	0:13631b50eae6	1183	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1184	if (ret == 0) {
cparata	0:13631b50eae6	1185	reg.sim = (uint8_t) val;
cparata	0:13631b50eae6	1186	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1187	}
cparata	0:13631b50eae6	1188	return ret;
cparata	0:13631b50eae6	1189	}
cparata	0:13631b50eae6	1190
cparata	0:13631b50eae6	1191	/**
cparata	0:13631b50eae6	1192	* @brief SPI Serial Interface Mode selection.[get]
cparata	0:13631b50eae6	1193	*
cparata	0:13631b50eae6	1194	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1195	* @param val Get the values of sim in reg CTRL2
cparata	0:13631b50eae6	1196	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1197	*
cparata	0:13631b50eae6	1198	*/
cparata	0:13631b50eae6	1199	int32_t iis2dlpc_spi_mode_get(iis2dlpc_ctx_t ctx, iis2dlpc_sim_t val)
cparata	0:13631b50eae6	1200	{
cparata	0:13631b50eae6	1201	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	1202	int32_t ret;
cparata	0:13631b50eae6	1203
cparata	0:13631b50eae6	1204	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1205
cparata	0:13631b50eae6	1206	switch (reg.sim) {
cparata	0:13631b50eae6	1207	case IIS2DLPC_SPI_4_WIRE:
cparata	0:13631b50eae6	1208	*val = IIS2DLPC_SPI_4_WIRE;
cparata	0:13631b50eae6	1209	break;
cparata	0:13631b50eae6	1210	case IIS2DLPC_SPI_3_WIRE:
cparata	0:13631b50eae6	1211	*val = IIS2DLPC_SPI_3_WIRE;
cparata	0:13631b50eae6	1212	break;
cparata	0:13631b50eae6	1213	default:
cparata	0:13631b50eae6	1214	*val = IIS2DLPC_SPI_4_WIRE;
cparata	0:13631b50eae6	1215	break;
cparata	0:13631b50eae6	1216	}
cparata	0:13631b50eae6	1217	return ret;
cparata	0:13631b50eae6	1218	}
cparata	0:13631b50eae6	1219
cparata	0:13631b50eae6	1220	/**
cparata	0:13631b50eae6	1221	* @brief Disable / Enable I2C interface.[set]
cparata	0:13631b50eae6	1222	*
cparata	0:13631b50eae6	1223	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1224	* @param val change the values of i2c_disable in
cparata	0:13631b50eae6	1225	* reg CTRL2
cparata	0:13631b50eae6	1226	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1227	*
cparata	0:13631b50eae6	1228	*/
cparata	0:13631b50eae6	1229	int32_t iis2dlpc_i2c_interface_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1230	iis2dlpc_i2c_disable_t val)
cparata	0:13631b50eae6	1231	{
cparata	0:13631b50eae6	1232	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	1233	int32_t ret;
cparata	0:13631b50eae6	1234
cparata	0:13631b50eae6	1235	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1236	if (ret == 0) {
cparata	0:13631b50eae6	1237	reg.i2c_disable = (uint8_t) val;
cparata	0:13631b50eae6	1238	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1239	}
cparata	0:13631b50eae6	1240	return ret;
cparata	0:13631b50eae6	1241	}
cparata	0:13631b50eae6	1242
cparata	0:13631b50eae6	1243	/**
cparata	0:13631b50eae6	1244	* @brief Disable / Enable I2C interface.[get]
cparata	0:13631b50eae6	1245	*
cparata	0:13631b50eae6	1246	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1247	* @param val Get the values of i2c_disable in reg CTRL2
cparata	0:13631b50eae6	1248	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1249	*
cparata	0:13631b50eae6	1250	*/
cparata	0:13631b50eae6	1251	int32_t iis2dlpc_i2c_interface_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1252	iis2dlpc_i2c_disable_t *val)
cparata	0:13631b50eae6	1253	{
cparata	0:13631b50eae6	1254	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	1255	int32_t ret;
cparata	0:13631b50eae6	1256
cparata	0:13631b50eae6	1257	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1258
cparata	0:13631b50eae6	1259	switch (reg.i2c_disable) {
cparata	0:13631b50eae6	1260	case IIS2DLPC_I2C_ENABLE:
cparata	0:13631b50eae6	1261	*val = IIS2DLPC_I2C_ENABLE;
cparata	0:13631b50eae6	1262	break;
cparata	0:13631b50eae6	1263	case IIS2DLPC_I2C_DISABLE:
cparata	0:13631b50eae6	1264	*val = IIS2DLPC_I2C_DISABLE;
cparata	0:13631b50eae6	1265	break;
cparata	0:13631b50eae6	1266	default:
cparata	0:13631b50eae6	1267	*val = IIS2DLPC_I2C_ENABLE;
cparata	0:13631b50eae6	1268	break;
cparata	0:13631b50eae6	1269	}
cparata	0:13631b50eae6	1270	return ret;
cparata	0:13631b50eae6	1271	}
cparata	0:13631b50eae6	1272
cparata	0:13631b50eae6	1273	/**
cparata	0:13631b50eae6	1274	* @brief Disconnect CS pull-up.[set]
cparata	0:13631b50eae6	1275	*
cparata	0:13631b50eae6	1276	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1277	* @param val change the values of cs_pu_disc in reg CTRL2
cparata	0:13631b50eae6	1278	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1279	*
cparata	0:13631b50eae6	1280	*/
cparata	0:13631b50eae6	1281	int32_t iis2dlpc_cs_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_cs_pu_disc_t val)
cparata	0:13631b50eae6	1282	{
cparata	0:13631b50eae6	1283	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	1284	int32_t ret;
cparata	0:13631b50eae6	1285
cparata	0:13631b50eae6	1286	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1287	if (ret == 0) {
cparata	0:13631b50eae6	1288	reg.cs_pu_disc = (uint8_t) val;
cparata	0:13631b50eae6	1289	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1290	}
cparata	0:13631b50eae6	1291	return ret;
cparata	0:13631b50eae6	1292	}
cparata	0:13631b50eae6	1293
cparata	0:13631b50eae6	1294	/**
cparata	0:13631b50eae6	1295	* @brief Disconnect CS pull-up.[get]
cparata	0:13631b50eae6	1296	*
cparata	0:13631b50eae6	1297	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1298	* @param val Get the values of cs_pu_disc in reg CTRL2
cparata	0:13631b50eae6	1299	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1300	*
cparata	0:13631b50eae6	1301	*/
cparata	0:13631b50eae6	1302	int32_t iis2dlpc_cs_mode_get(iis2dlpc_ctx_t ctx, iis2dlpc_cs_pu_disc_t val)
cparata	0:13631b50eae6	1303	{
cparata	0:13631b50eae6	1304	iis2dlpc_ctrl2_t reg;
cparata	0:13631b50eae6	1305	int32_t ret;
cparata	0:13631b50eae6	1306
cparata	0:13631b50eae6	1307	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1308
cparata	0:13631b50eae6	1309	switch (reg.cs_pu_disc) {
cparata	0:13631b50eae6	1310	case IIS2DLPC_PULL_UP_CONNECT:
cparata	0:13631b50eae6	1311	*val = IIS2DLPC_PULL_UP_CONNECT;
cparata	0:13631b50eae6	1312	break;
cparata	0:13631b50eae6	1313	case IIS2DLPC_PULL_UP_DISCONNECT:
cparata	0:13631b50eae6	1314	*val = IIS2DLPC_PULL_UP_DISCONNECT;
cparata	0:13631b50eae6	1315	break;
cparata	0:13631b50eae6	1316	default:
cparata	0:13631b50eae6	1317	*val = IIS2DLPC_PULL_UP_CONNECT;
cparata	0:13631b50eae6	1318	break;
cparata	0:13631b50eae6	1319	}
cparata	0:13631b50eae6	1320	return ret;
cparata	0:13631b50eae6	1321	}
cparata	0:13631b50eae6	1322
cparata	0:13631b50eae6	1323	/**
cparata	0:13631b50eae6	1324	* @}
cparata	0:13631b50eae6	1325	*
cparata	0:13631b50eae6	1326	*/
cparata	0:13631b50eae6	1327
cparata	0:13631b50eae6	1328	/**
cparata	0:13631b50eae6	1329	* @defgroup IIS2DLPC_Interrupt_Pins
cparata	0:13631b50eae6	1330	* @brief This section groups all the functions that manage interrupt pins
cparata	0:13631b50eae6	1331	* @{
cparata	0:13631b50eae6	1332	*
cparata	0:13631b50eae6	1333	*/
cparata	0:13631b50eae6	1334
cparata	0:13631b50eae6	1335	/**
cparata	0:13631b50eae6	1336	* @brief Interrupt active-high/low.[set]
cparata	0:13631b50eae6	1337	*
cparata	0:13631b50eae6	1338	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1339	* @param val change the values of h_lactive in reg CTRL3
cparata	0:13631b50eae6	1340	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1341	*
cparata	0:13631b50eae6	1342	*/
cparata	0:13631b50eae6	1343	int32_t iis2dlpc_pin_polarity_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1344	iis2dlpc_h_lactive_t val)
cparata	0:13631b50eae6	1345	{
cparata	0:13631b50eae6	1346	iis2dlpc_ctrl3_t reg;
cparata	0:13631b50eae6	1347	int32_t ret;
cparata	0:13631b50eae6	1348
cparata	0:13631b50eae6	1349	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1350	if (ret == 0) {
cparata	0:13631b50eae6	1351	reg.h_lactive = (uint8_t) val;
cparata	0:13631b50eae6	1352	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1353	}
cparata	0:13631b50eae6	1354	return ret;
cparata	0:13631b50eae6	1355	}
cparata	0:13631b50eae6	1356
cparata	0:13631b50eae6	1357	/**
cparata	0:13631b50eae6	1358	* @brief Interrupt active-high/low.[get]
cparata	0:13631b50eae6	1359	*
cparata	0:13631b50eae6	1360	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1361	* @param val Get the values of h_lactive in reg CTRL3
cparata	0:13631b50eae6	1362	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1363	*
cparata	0:13631b50eae6	1364	*/
cparata	0:13631b50eae6	1365	int32_t iis2dlpc_pin_polarity_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1366	iis2dlpc_h_lactive_t *val)
cparata	0:13631b50eae6	1367	{
cparata	0:13631b50eae6	1368	iis2dlpc_ctrl3_t reg;
cparata	0:13631b50eae6	1369	int32_t ret;
cparata	0:13631b50eae6	1370
cparata	0:13631b50eae6	1371	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1372
cparata	0:13631b50eae6	1373	switch (reg.h_lactive) {
cparata	0:13631b50eae6	1374	case IIS2DLPC_ACTIVE_HIGH:
cparata	0:13631b50eae6	1375	*val = IIS2DLPC_ACTIVE_HIGH;
cparata	0:13631b50eae6	1376	break;
cparata	0:13631b50eae6	1377	case IIS2DLPC_ACTIVE_LOW:
cparata	0:13631b50eae6	1378	*val = IIS2DLPC_ACTIVE_LOW;
cparata	0:13631b50eae6	1379	break;
cparata	0:13631b50eae6	1380	default:
cparata	0:13631b50eae6	1381	*val = IIS2DLPC_ACTIVE_HIGH;
cparata	0:13631b50eae6	1382	break;
cparata	0:13631b50eae6	1383	}
cparata	0:13631b50eae6	1384	return ret;
cparata	0:13631b50eae6	1385	}
cparata	0:13631b50eae6	1386
cparata	0:13631b50eae6	1387	/**
cparata	0:13631b50eae6	1388	* @brief Latched/pulsed interrupt.[set]
cparata	0:13631b50eae6	1389	*
cparata	0:13631b50eae6	1390	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1391	* @param val change the values of lir in reg CTRL3
cparata	0:13631b50eae6	1392	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1393	*
cparata	0:13631b50eae6	1394	*/
cparata	0:13631b50eae6	1395	int32_t iis2dlpc_int_notification_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1396	iis2dlpc_lir_t val)
cparata	0:13631b50eae6	1397	{
cparata	0:13631b50eae6	1398	iis2dlpc_ctrl3_t reg;
cparata	0:13631b50eae6	1399	int32_t ret;
cparata	0:13631b50eae6	1400
cparata	0:13631b50eae6	1401	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1402	if (ret == 0) {
cparata	0:13631b50eae6	1403	reg.lir = (uint8_t) val;
cparata	0:13631b50eae6	1404	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1405	}
cparata	0:13631b50eae6	1406	return ret;
cparata	0:13631b50eae6	1407	}
cparata	0:13631b50eae6	1408
cparata	0:13631b50eae6	1409	/**
cparata	0:13631b50eae6	1410	* @brief Latched/pulsed interrupt.[get]
cparata	0:13631b50eae6	1411	*
cparata	0:13631b50eae6	1412	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1413	* @param val Get the values of lir in reg CTRL3
cparata	0:13631b50eae6	1414	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1415	*
cparata	0:13631b50eae6	1416	*/
cparata	0:13631b50eae6	1417	int32_t iis2dlpc_int_notification_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1418	iis2dlpc_lir_t *val)
cparata	0:13631b50eae6	1419	{
cparata	0:13631b50eae6	1420	iis2dlpc_ctrl3_t reg;
cparata	0:13631b50eae6	1421	int32_t ret;
cparata	0:13631b50eae6	1422
cparata	0:13631b50eae6	1423	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1424
cparata	0:13631b50eae6	1425	switch (reg.lir) {
cparata	0:13631b50eae6	1426	case IIS2DLPC_INT_PULSED:
cparata	0:13631b50eae6	1427	*val = IIS2DLPC_INT_PULSED;
cparata	0:13631b50eae6	1428	break;
cparata	0:13631b50eae6	1429	case IIS2DLPC_INT_LATCHED:
cparata	0:13631b50eae6	1430	*val = IIS2DLPC_INT_LATCHED;
cparata	0:13631b50eae6	1431	break;
cparata	0:13631b50eae6	1432	default:
cparata	0:13631b50eae6	1433	*val = IIS2DLPC_INT_PULSED;
cparata	0:13631b50eae6	1434	break;
cparata	0:13631b50eae6	1435	}
cparata	0:13631b50eae6	1436	return ret;
cparata	0:13631b50eae6	1437	}
cparata	0:13631b50eae6	1438
cparata	0:13631b50eae6	1439	/**
cparata	0:13631b50eae6	1440	* @brief Push-pull/open drain selection on interrupt pads.[set]
cparata	0:13631b50eae6	1441	*
cparata	0:13631b50eae6	1442	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1443	* @param val change the values of pp_od in reg CTRL3
cparata	0:13631b50eae6	1444	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1445	*
cparata	0:13631b50eae6	1446	*/
cparata	0:13631b50eae6	1447	int32_t iis2dlpc_pin_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_pp_od_t val)
cparata	0:13631b50eae6	1448	{
cparata	0:13631b50eae6	1449	iis2dlpc_ctrl3_t reg;
cparata	0:13631b50eae6	1450	int32_t ret;
cparata	0:13631b50eae6	1451
cparata	0:13631b50eae6	1452	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1453	if (ret == 0) {
cparata	0:13631b50eae6	1454	reg.pp_od = (uint8_t) val;
cparata	0:13631b50eae6	1455	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1456	}
cparata	0:13631b50eae6	1457	return ret;
cparata	0:13631b50eae6	1458	}
cparata	0:13631b50eae6	1459
cparata	0:13631b50eae6	1460	/**
cparata	0:13631b50eae6	1461	* @brief Push-pull/open drain selection on interrupt pads.[get]
cparata	0:13631b50eae6	1462	*
cparata	0:13631b50eae6	1463	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1464	* @param val Get the values of pp_od in reg CTRL3
cparata	0:13631b50eae6	1465	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1466	*
cparata	0:13631b50eae6	1467	*/
cparata	0:13631b50eae6	1468	int32_t iis2dlpc_pin_mode_get(iis2dlpc_ctx_t ctx, iis2dlpc_pp_od_t val)
cparata	0:13631b50eae6	1469	{
cparata	0:13631b50eae6	1470	iis2dlpc_ctrl3_t reg;
cparata	0:13631b50eae6	1471	int32_t ret;
cparata	0:13631b50eae6	1472
cparata	0:13631b50eae6	1473	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1474
cparata	0:13631b50eae6	1475	switch (reg.pp_od) {
cparata	0:13631b50eae6	1476	case IIS2DLPC_PUSH_PULL:
cparata	0:13631b50eae6	1477	*val = IIS2DLPC_PUSH_PULL;
cparata	0:13631b50eae6	1478	break;
cparata	0:13631b50eae6	1479	case IIS2DLPC_OPEN_DRAIN:
cparata	0:13631b50eae6	1480	*val = IIS2DLPC_OPEN_DRAIN;
cparata	0:13631b50eae6	1481	break;
cparata	0:13631b50eae6	1482	default:
cparata	0:13631b50eae6	1483	*val = IIS2DLPC_PUSH_PULL;
cparata	0:13631b50eae6	1484	break;
cparata	0:13631b50eae6	1485	}
cparata	0:13631b50eae6	1486	return ret;
cparata	0:13631b50eae6	1487	}
cparata	0:13631b50eae6	1488
cparata	0:13631b50eae6	1489	/**
cparata	0:13631b50eae6	1490	* @brief Select the signal that need to route on int1 pad.[set]
cparata	0:13631b50eae6	1491	*
cparata	0:13631b50eae6	1492	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1493	* @param val register CTRL4_INT1_PAD_CTRL.
cparata	0:13631b50eae6	1494	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1495	*
cparata	0:13631b50eae6	1496	*/
cparata	0:13631b50eae6	1497	int32_t iis2dlpc_pin_int1_route_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1498	iis2dlpc_ctrl4_int1_pad_ctrl_t *val)
cparata	0:13631b50eae6	1499	{
cparata	0:13631b50eae6	1500	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	1501	int32_t ret;
cparata	0:13631b50eae6	1502
cparata	0:13631b50eae6	1503	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1504	if (ret == 0) {
cparata	0:13631b50eae6	1505	if ((val->int1_tap \| val->int1_ff \| val->int1_wu \| val->int1_single_tap \|
cparata	0:13631b50eae6	1506	val->int1_6d) != PROPERTY_DISABLE){
cparata	0:13631b50eae6	1507	reg.interrupts_enable = PROPERTY_ENABLE;
cparata	0:13631b50eae6	1508	}
cparata	0:13631b50eae6	1509	else{
cparata	0:13631b50eae6	1510	reg.interrupts_enable = PROPERTY_DISABLE;
cparata	0:13631b50eae6	1511	}
cparata	0:13631b50eae6	1512
cparata	0:13631b50eae6	1513	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
cparata	0:13631b50eae6	1514	(uint8_t*) val, 1);
cparata	0:13631b50eae6	1515	}
cparata	0:13631b50eae6	1516	if (ret == 0) {
cparata	0:13631b50eae6	1517	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1518	} else {
cparata	0:13631b50eae6	1519	ret = ret;
cparata	0:13631b50eae6	1520	}
cparata	0:13631b50eae6	1521	return ret;
cparata	0:13631b50eae6	1522	}
cparata	0:13631b50eae6	1523
cparata	0:13631b50eae6	1524	/**
cparata	0:13631b50eae6	1525	* @brief Select the signal that need to route on int1 pad.[get]
cparata	0:13631b50eae6	1526	*
cparata	0:13631b50eae6	1527	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1528	* @param val register CTRL4_INT1_PAD_CTRL.
cparata	0:13631b50eae6	1529	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1530	*
cparata	0:13631b50eae6	1531	*/
cparata	0:13631b50eae6	1532	int32_t iis2dlpc_pin_int1_route_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1533	iis2dlpc_ctrl4_int1_pad_ctrl_t *val)
cparata	0:13631b50eae6	1534	{
cparata	0:13631b50eae6	1535	int32_t ret;
cparata	0:13631b50eae6	1536	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL4_INT1_PAD_CTRL,
cparata	0:13631b50eae6	1537	(uint8_t*) val, 1);
cparata	0:13631b50eae6	1538	return ret;
cparata	0:13631b50eae6	1539	}
cparata	0:13631b50eae6	1540
cparata	0:13631b50eae6	1541	/**
cparata	0:13631b50eae6	1542	* @brief Select the signal that need to route on int2 pad.[set]
cparata	0:13631b50eae6	1543	*
cparata	0:13631b50eae6	1544	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1545	* @param val register CTRL5_INT2_PAD_CTRL.
cparata	0:13631b50eae6	1546	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1547	*
cparata	0:13631b50eae6	1548	*/
cparata	0:13631b50eae6	1549	int32_t iis2dlpc_pin_int2_route_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1550	iis2dlpc_ctrl5_int2_pad_ctrl_t *val)
cparata	0:13631b50eae6	1551	{
cparata	0:13631b50eae6	1552	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	1553	int32_t ret;
cparata	0:13631b50eae6	1554
cparata	0:13631b50eae6	1555	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1556	if (ret == 0) {
cparata	0:13631b50eae6	1557	if ((val->int2_sleep_state \| val->int2_sleep_chg ) != PROPERTY_DISABLE) {
cparata	0:13631b50eae6	1558	reg.interrupts_enable = PROPERTY_ENABLE;
cparata	0:13631b50eae6	1559	}
cparata	0:13631b50eae6	1560	else{
cparata	0:13631b50eae6	1561	reg.interrupts_enable = PROPERTY_DISABLE;
cparata	0:13631b50eae6	1562	}
cparata	0:13631b50eae6	1563
cparata	0:13631b50eae6	1564	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
cparata	0:13631b50eae6	1565	(uint8_t*) val, 1);
cparata	0:13631b50eae6	1566	}
cparata	0:13631b50eae6	1567	if (ret == 0) {
cparata	0:13631b50eae6	1568	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1569	} else {
cparata	0:13631b50eae6	1570	ret = ret;
cparata	0:13631b50eae6	1571	}
cparata	0:13631b50eae6	1572	return ret;
cparata	0:13631b50eae6	1573	}
cparata	0:13631b50eae6	1574
cparata	0:13631b50eae6	1575	/**
cparata	0:13631b50eae6	1576	* @brief Select the signal that need to route on int2 pad.[get]
cparata	0:13631b50eae6	1577	*
cparata	0:13631b50eae6	1578	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1579	* @param val register CTRL5_INT2_PAD_CTRL
cparata	0:13631b50eae6	1580	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1581	*
cparata	0:13631b50eae6	1582	*/
cparata	0:13631b50eae6	1583	int32_t iis2dlpc_pin_int2_route_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1584	iis2dlpc_ctrl5_int2_pad_ctrl_t *val)
cparata	0:13631b50eae6	1585	{
cparata	0:13631b50eae6	1586	int32_t ret;
cparata	0:13631b50eae6	1587	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL5_INT2_PAD_CTRL,
cparata	0:13631b50eae6	1588	(uint8_t*) val, 1);
cparata	0:13631b50eae6	1589	return ret;
cparata	0:13631b50eae6	1590	}
cparata	0:13631b50eae6	1591	/**
cparata	0:13631b50eae6	1592	* @brief All interrupt signals become available on INT1 pin.[set]
cparata	0:13631b50eae6	1593	*
cparata	0:13631b50eae6	1594	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1595	* @param val change the values of int2_on_int1 in reg CTRL_REG7
cparata	0:13631b50eae6	1596	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1597	*
cparata	0:13631b50eae6	1598	*/
cparata	0:13631b50eae6	1599	int32_t iis2dlpc_all_on_int1_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	1600	{
cparata	0:13631b50eae6	1601	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	1602	int32_t ret;
cparata	0:13631b50eae6	1603
cparata	0:13631b50eae6	1604	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1605	if (ret == 0) {
cparata	0:13631b50eae6	1606	reg.int2_on_int1 = val;
cparata	0:13631b50eae6	1607	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1608	}
cparata	0:13631b50eae6	1609	return ret;
cparata	0:13631b50eae6	1610	}
cparata	0:13631b50eae6	1611
cparata	0:13631b50eae6	1612	/**
cparata	0:13631b50eae6	1613	* @brief All interrupt signals become available on INT1 pin.[get]
cparata	0:13631b50eae6	1614	*
cparata	0:13631b50eae6	1615	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1616	* @param val change the values of int2_on_int1 in reg CTRL_REG7
cparata	0:13631b50eae6	1617	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1618	*
cparata	0:13631b50eae6	1619	*/
cparata	0:13631b50eae6	1620	int32_t iis2dlpc_all_on_int1_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	1621	{
cparata	0:13631b50eae6	1622	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	1623	int32_t ret;
cparata	0:13631b50eae6	1624
cparata	0:13631b50eae6	1625	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1626	*val = reg.int2_on_int1;
cparata	0:13631b50eae6	1627
cparata	0:13631b50eae6	1628	return ret;
cparata	0:13631b50eae6	1629	}
cparata	0:13631b50eae6	1630
cparata	0:13631b50eae6	1631	/**
cparata	0:13631b50eae6	1632	* @}
cparata	0:13631b50eae6	1633	*
cparata	0:13631b50eae6	1634	*/
cparata	0:13631b50eae6	1635
cparata	0:13631b50eae6	1636	/**
cparata	0:13631b50eae6	1637	* @defgroup IIS2DLPC_Wake_Up_Event
cparata	0:13631b50eae6	1638	* @brief This section groups all the functions that manage the Wake
cparata	0:13631b50eae6	1639	* Up event generation.
cparata	0:13631b50eae6	1640	* @{
cparata	0:13631b50eae6	1641	*
cparata	0:13631b50eae6	1642	*/
cparata	0:13631b50eae6	1643
cparata	0:13631b50eae6	1644	/**
cparata	0:13631b50eae6	1645	* @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
cparata	0:13631b50eae6	1646	*
cparata	0:13631b50eae6	1647	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1648	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:13631b50eae6	1649	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1650	*
cparata	0:13631b50eae6	1651	*/
cparata	0:13631b50eae6	1652	int32_t iis2dlpc_wkup_threshold_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	1653	{
cparata	0:13631b50eae6	1654	iis2dlpc_wake_up_ths_t reg;
cparata	0:13631b50eae6	1655	int32_t ret;
cparata	0:13631b50eae6	1656
cparata	0:13631b50eae6	1657	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1658	if (ret == 0) {
cparata	0:13631b50eae6	1659	reg.wk_ths = val;
cparata	0:13631b50eae6	1660	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1661	}
cparata	0:13631b50eae6	1662	return ret;
cparata	0:13631b50eae6	1663	}
cparata	0:13631b50eae6	1664
cparata	0:13631b50eae6	1665	/**
cparata	0:13631b50eae6	1666	* @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
cparata	0:13631b50eae6	1667	*
cparata	0:13631b50eae6	1668	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1669	* @param val change the values of wk_ths in reg WAKE_UP_THS
cparata	0:13631b50eae6	1670	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1671	*
cparata	0:13631b50eae6	1672	*/
cparata	0:13631b50eae6	1673	int32_t iis2dlpc_wkup_threshold_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	1674	{
cparata	0:13631b50eae6	1675	iis2dlpc_wake_up_ths_t reg;
cparata	0:13631b50eae6	1676	int32_t ret;
cparata	0:13631b50eae6	1677
cparata	0:13631b50eae6	1678	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1679	*val = reg.wk_ths;
cparata	0:13631b50eae6	1680
cparata	0:13631b50eae6	1681	return ret;
cparata	0:13631b50eae6	1682	}
cparata	0:13631b50eae6	1683
cparata	0:13631b50eae6	1684	/**
cparata	0:13631b50eae6	1685	* @brief Wake up duration event.1LSb = 1 / ODR.[set]
cparata	0:13631b50eae6	1686	*
cparata	0:13631b50eae6	1687	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1688	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:13631b50eae6	1689	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1690	*
cparata	0:13631b50eae6	1691	*/
cparata	0:13631b50eae6	1692	int32_t iis2dlpc_wkup_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	1693	{
cparata	0:13631b50eae6	1694	iis2dlpc_wake_up_dur_t reg;
cparata	0:13631b50eae6	1695	int32_t ret;
cparata	0:13631b50eae6	1696
cparata	0:13631b50eae6	1697	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1698	if (ret == 0) {
cparata	0:13631b50eae6	1699	reg.wake_dur = val;
cparata	0:13631b50eae6	1700	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1701	}
cparata	0:13631b50eae6	1702	return ret;
cparata	0:13631b50eae6	1703	}
cparata	0:13631b50eae6	1704
cparata	0:13631b50eae6	1705	/**
cparata	0:13631b50eae6	1706	* @brief Wake up duration event.1LSb = 1 / ODR.[get]
cparata	0:13631b50eae6	1707	*
cparata	0:13631b50eae6	1708	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1709	* @param val change the values of wake_dur in reg WAKE_UP_DUR
cparata	0:13631b50eae6	1710	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1711	*
cparata	0:13631b50eae6	1712	*/
cparata	0:13631b50eae6	1713	int32_t iis2dlpc_wkup_dur_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	1714	{
cparata	0:13631b50eae6	1715	iis2dlpc_wake_up_dur_t reg;
cparata	0:13631b50eae6	1716	int32_t ret;
cparata	0:13631b50eae6	1717
cparata	0:13631b50eae6	1718	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1719	*val = reg.wake_dur;
cparata	0:13631b50eae6	1720
cparata	0:13631b50eae6	1721	return ret;
cparata	0:13631b50eae6	1722	}
cparata	0:13631b50eae6	1723
cparata	0:13631b50eae6	1724	/**
cparata	0:13631b50eae6	1725	* @brief Data sent to wake-up interrupt function.[set]
cparata	0:13631b50eae6	1726	*
cparata	0:13631b50eae6	1727	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1728	* @param val change the values of usr_off_on_wu in reg CTRL_REG7
cparata	0:13631b50eae6	1729	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1730	*
cparata	0:13631b50eae6	1731	*/
cparata	0:13631b50eae6	1732	int32_t iis2dlpc_wkup_feed_data_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1733	iis2dlpc_usr_off_on_wu_t val)
cparata	0:13631b50eae6	1734	{
cparata	0:13631b50eae6	1735	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	1736	int32_t ret;
cparata	0:13631b50eae6	1737
cparata	0:13631b50eae6	1738	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1739	if (ret == 0) {
cparata	0:13631b50eae6	1740	reg.usr_off_on_wu = (uint8_t) val;
cparata	0:13631b50eae6	1741	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1742	}
cparata	0:13631b50eae6	1743	return ret;
cparata	0:13631b50eae6	1744	}
cparata	0:13631b50eae6	1745
cparata	0:13631b50eae6	1746	/**
cparata	0:13631b50eae6	1747	* @brief Data sent to wake-up interrupt function.[get]
cparata	0:13631b50eae6	1748	*
cparata	0:13631b50eae6	1749	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1750	* @param val Get the values of usr_off_on_wu in reg CTRL_REG7
cparata	0:13631b50eae6	1751	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1752	*
cparata	0:13631b50eae6	1753	*/
cparata	0:13631b50eae6	1754	int32_t iis2dlpc_wkup_feed_data_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1755	iis2dlpc_usr_off_on_wu_t *val)
cparata	0:13631b50eae6	1756	{
cparata	0:13631b50eae6	1757	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	1758	int32_t ret;
cparata	0:13631b50eae6	1759
cparata	0:13631b50eae6	1760	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1761
cparata	0:13631b50eae6	1762	switch (reg.usr_off_on_wu) {
cparata	0:13631b50eae6	1763	case IIS2DLPC_HP_FEED:
cparata	0:13631b50eae6	1764	*val = IIS2DLPC_HP_FEED;
cparata	0:13631b50eae6	1765	break;
cparata	0:13631b50eae6	1766	case IIS2DLPC_USER_OFFSET_FEED:
cparata	0:13631b50eae6	1767	*val = IIS2DLPC_USER_OFFSET_FEED;
cparata	0:13631b50eae6	1768	break;
cparata	0:13631b50eae6	1769	default:
cparata	0:13631b50eae6	1770	*val = IIS2DLPC_HP_FEED;
cparata	0:13631b50eae6	1771	break;
cparata	0:13631b50eae6	1772	}
cparata	0:13631b50eae6	1773	return ret;
cparata	0:13631b50eae6	1774	}
cparata	0:13631b50eae6	1775
cparata	0:13631b50eae6	1776	/**
cparata	0:13631b50eae6	1777	* @}
cparata	0:13631b50eae6	1778	*
cparata	0:13631b50eae6	1779	*/
cparata	0:13631b50eae6	1780
cparata	0:13631b50eae6	1781	/**
cparata	0:13631b50eae6	1782	* @defgroup IIS2DLPC_Activity/Inactivity_Detection
cparata	0:13631b50eae6	1783	* @brief This section groups all the functions concerning
cparata	0:13631b50eae6	1784	* activity/inactivity detection.
cparata	0:13631b50eae6	1785	* @{
cparata	0:13631b50eae6	1786	*
cparata	0:13631b50eae6	1787	*/
cparata	0:13631b50eae6	1788
cparata	0:13631b50eae6	1789	/**
cparata	0:13631b50eae6	1790	* @brief Config activity / inactivity or
cparata	0:13631b50eae6	1791	* stationary / motion detection.[set]
cparata	0:13631b50eae6	1792	*
cparata	0:13631b50eae6	1793	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1794	* @param val change the values of sleep_on / stationary in
cparata	0:13631b50eae6	1795	* reg WAKE_UP_THS / WAKE_UP_DUR
cparata	0:13631b50eae6	1796	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1797	*
cparata	0:13631b50eae6	1798	*/
cparata	0:13631b50eae6	1799	int32_t iis2dlpc_act_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_sleep_on_t val)
cparata	0:13631b50eae6	1800	{
cparata	0:13631b50eae6	1801	iis2dlpc_wake_up_ths_t wake_up_ths;
cparata	0:13631b50eae6	1802	iis2dlpc_wake_up_dur_t wake_up_dur;
cparata	0:13631b50eae6	1803	int32_t ret;
cparata	0:13631b50eae6	1804
cparata	0:13631b50eae6	1805	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
cparata	0:13631b50eae6	1806	if (ret == 0) {
cparata	0:13631b50eae6	1807	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	0:13631b50eae6	1808	}
cparata	0:13631b50eae6	1809	if (ret == 0) {
cparata	0:13631b50eae6	1810	wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
cparata	0:13631b50eae6	1811	wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
cparata	0:13631b50eae6	1812	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 2);
cparata	0:13631b50eae6	1813	} else {
cparata	0:13631b50eae6	1814	ret = ret;
cparata	0:13631b50eae6	1815	}
cparata	0:13631b50eae6	1816
cparata	0:13631b50eae6	1817	return ret;
cparata	0:13631b50eae6	1818	}
cparata	0:13631b50eae6	1819
cparata	0:13631b50eae6	1820	/**
cparata	0:13631b50eae6	1821	* @brief Config activity / inactivity or
cparata	0:13631b50eae6	1822	* stationary / motion detection. [get]
cparata	0:13631b50eae6	1823	*
cparata	0:13631b50eae6	1824	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1825	* @param val Get the values of sleep_on in reg WAKE_UP_THS
cparata	0:13631b50eae6	1826	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1827	*
cparata	0:13631b50eae6	1828	*/
cparata	0:13631b50eae6	1829	int32_t iis2dlpc_act_mode_get(iis2dlpc_ctx_t ctx, iis2dlpc_sleep_on_t val)
cparata	0:13631b50eae6	1830	{
cparata	0:13631b50eae6	1831	iis2dlpc_wake_up_ths_t wake_up_ths;
cparata	0:13631b50eae6	1832	iis2dlpc_wake_up_dur_t wake_up_dur;;
cparata	0:13631b50eae6	1833	int32_t ret;
cparata	0:13631b50eae6	1834
cparata	0:13631b50eae6	1835	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &wake_up_ths, 1);
cparata	0:13631b50eae6	1836	if (ret == 0) {
cparata	0:13631b50eae6	1837	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	0:13631b50eae6	1838
cparata	0:13631b50eae6	1839	switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on){
cparata	0:13631b50eae6	1840	case IIS2DLPC_NO_DETECTION:
cparata	0:13631b50eae6	1841	*val = IIS2DLPC_NO_DETECTION;
cparata	0:13631b50eae6	1842	break;
cparata	0:13631b50eae6	1843	case IIS2DLPC_DETECT_ACT_INACT:
cparata	0:13631b50eae6	1844	*val = IIS2DLPC_DETECT_ACT_INACT;
cparata	0:13631b50eae6	1845	break;
cparata	0:13631b50eae6	1846	case IIS2DLPC_DETECT_STAT_MOTION:
cparata	0:13631b50eae6	1847	*val = IIS2DLPC_DETECT_STAT_MOTION;
cparata	0:13631b50eae6	1848	break;
cparata	0:13631b50eae6	1849	default:
cparata	0:13631b50eae6	1850	*val = IIS2DLPC_NO_DETECTION;
cparata	0:13631b50eae6	1851	break;
cparata	0:13631b50eae6	1852	}
cparata	0:13631b50eae6	1853	}
cparata	0:13631b50eae6	1854	return ret;
cparata	0:13631b50eae6	1855	}
cparata	0:13631b50eae6	1856
cparata	0:13631b50eae6	1857	/**
cparata	0:13631b50eae6	1858	* @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
cparata	0:13631b50eae6	1859	*
cparata	0:13631b50eae6	1860	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1861	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:13631b50eae6	1862	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1863	*
cparata	0:13631b50eae6	1864	*/
cparata	0:13631b50eae6	1865	int32_t iis2dlpc_act_sleep_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	1866	{
cparata	0:13631b50eae6	1867	iis2dlpc_wake_up_dur_t reg;
cparata	0:13631b50eae6	1868	int32_t ret;
cparata	0:13631b50eae6	1869
cparata	0:13631b50eae6	1870	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1871	if (ret == 0) {
cparata	0:13631b50eae6	1872	reg.sleep_dur = val;
cparata	0:13631b50eae6	1873	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1874	}
cparata	0:13631b50eae6	1875	return ret;
cparata	0:13631b50eae6	1876	}
cparata	0:13631b50eae6	1877
cparata	0:13631b50eae6	1878	/**
cparata	0:13631b50eae6	1879	* @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
cparata	0:13631b50eae6	1880	*
cparata	0:13631b50eae6	1881	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1882	* @param val change the values of sleep_dur in reg WAKE_UP_DUR
cparata	0:13631b50eae6	1883	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1884	*
cparata	0:13631b50eae6	1885	*/
cparata	0:13631b50eae6	1886	int32_t iis2dlpc_act_sleep_dur_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	1887	{
cparata	0:13631b50eae6	1888	iis2dlpc_wake_up_dur_t reg;
cparata	0:13631b50eae6	1889	int32_t ret;
cparata	0:13631b50eae6	1890
cparata	0:13631b50eae6	1891	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1892	*val = reg.sleep_dur;
cparata	0:13631b50eae6	1893
cparata	0:13631b50eae6	1894	return ret;
cparata	0:13631b50eae6	1895	}
cparata	0:13631b50eae6	1896
cparata	0:13631b50eae6	1897	/**
cparata	0:13631b50eae6	1898	* @}
cparata	0:13631b50eae6	1899	*
cparata	0:13631b50eae6	1900	*/
cparata	0:13631b50eae6	1901
cparata	0:13631b50eae6	1902	/**
cparata	0:13631b50eae6	1903	* @defgroup IIS2DLPC_Tap_Generator
cparata	0:13631b50eae6	1904	* @brief This section groups all the functions that manage the tap
cparata	0:13631b50eae6	1905	* and double tap event generation.
cparata	0:13631b50eae6	1906	* @{
cparata	0:13631b50eae6	1907	*
cparata	0:13631b50eae6	1908	*/
cparata	0:13631b50eae6	1909
cparata	0:13631b50eae6	1910	/**
cparata	0:13631b50eae6	1911	* @brief Threshold for tap recognition.[set]
cparata	0:13631b50eae6	1912	*
cparata	0:13631b50eae6	1913	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1914	* @param val change the values of tap_thsx in reg TAP_THS_X
cparata	0:13631b50eae6	1915	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1916	*
cparata	0:13631b50eae6	1917	*/
cparata	0:13631b50eae6	1918	int32_t iis2dlpc_tap_threshold_x_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	1919	{
cparata	0:13631b50eae6	1920	iis2dlpc_tap_ths_x_t reg;
cparata	0:13631b50eae6	1921	int32_t ret;
cparata	0:13631b50eae6	1922
cparata	0:13631b50eae6	1923	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1924	if (ret == 0) {
cparata	0:13631b50eae6	1925	reg.tap_thsx = val;
cparata	0:13631b50eae6	1926	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1927	}
cparata	0:13631b50eae6	1928	return ret;
cparata	0:13631b50eae6	1929	}
cparata	0:13631b50eae6	1930
cparata	0:13631b50eae6	1931	/**
cparata	0:13631b50eae6	1932	* @brief Threshold for tap recognition.[get]
cparata	0:13631b50eae6	1933	*
cparata	0:13631b50eae6	1934	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1935	* @param val change the values of tap_thsx in reg TAP_THS_X
cparata	0:13631b50eae6	1936	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1937	*
cparata	0:13631b50eae6	1938	*/
cparata	0:13631b50eae6	1939	int32_t iis2dlpc_tap_threshold_x_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	1940	{
cparata	0:13631b50eae6	1941	iis2dlpc_tap_ths_x_t reg;
cparata	0:13631b50eae6	1942	int32_t ret;
cparata	0:13631b50eae6	1943
cparata	0:13631b50eae6	1944	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1945	*val = reg.tap_thsx;
cparata	0:13631b50eae6	1946
cparata	0:13631b50eae6	1947	return ret;
cparata	0:13631b50eae6	1948	}
cparata	0:13631b50eae6	1949
cparata	0:13631b50eae6	1950	/**
cparata	0:13631b50eae6	1951	* @brief Threshold for tap recognition.[set]
cparata	0:13631b50eae6	1952	*
cparata	0:13631b50eae6	1953	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1954	* @param val change the values of tap_thsy in reg TAP_THS_Y
cparata	0:13631b50eae6	1955	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1956	*
cparata	0:13631b50eae6	1957	*/
cparata	0:13631b50eae6	1958	int32_t iis2dlpc_tap_threshold_y_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	1959	{
cparata	0:13631b50eae6	1960	iis2dlpc_tap_ths_y_t reg;
cparata	0:13631b50eae6	1961	int32_t ret;
cparata	0:13631b50eae6	1962
cparata	0:13631b50eae6	1963	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1964	if (ret == 0) {
cparata	0:13631b50eae6	1965	reg.tap_thsy = val;
cparata	0:13631b50eae6	1966	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1967	}
cparata	0:13631b50eae6	1968	return ret;
cparata	0:13631b50eae6	1969	}
cparata	0:13631b50eae6	1970
cparata	0:13631b50eae6	1971	/**
cparata	0:13631b50eae6	1972	* @brief Threshold for tap recognition.[get]
cparata	0:13631b50eae6	1973	*
cparata	0:13631b50eae6	1974	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1975	* @param val change the values of tap_thsy in reg TAP_THS_Y
cparata	0:13631b50eae6	1976	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1977	*
cparata	0:13631b50eae6	1978	*/
cparata	0:13631b50eae6	1979	int32_t iis2dlpc_tap_threshold_y_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	1980	{
cparata	0:13631b50eae6	1981	iis2dlpc_tap_ths_y_t reg;
cparata	0:13631b50eae6	1982	int32_t ret;
cparata	0:13631b50eae6	1983
cparata	0:13631b50eae6	1984	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	1985	*val = reg.tap_thsy;
cparata	0:13631b50eae6	1986
cparata	0:13631b50eae6	1987	return ret;
cparata	0:13631b50eae6	1988	}
cparata	0:13631b50eae6	1989
cparata	0:13631b50eae6	1990	/**
cparata	0:13631b50eae6	1991	* @brief Selection of axis priority for TAP detection.[set]
cparata	0:13631b50eae6	1992	*
cparata	0:13631b50eae6	1993	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	1994	* @param val change the values of tap_prior in reg TAP_THS_Y
cparata	0:13631b50eae6	1995	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	1996	*
cparata	0:13631b50eae6	1997	*/
cparata	0:13631b50eae6	1998	int32_t iis2dlpc_tap_axis_priority_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	1999	iis2dlpc_tap_prior_t val)
cparata	0:13631b50eae6	2000	{
cparata	0:13631b50eae6	2001	iis2dlpc_tap_ths_y_t reg;
cparata	0:13631b50eae6	2002	int32_t ret;
cparata	0:13631b50eae6	2003
cparata	0:13631b50eae6	2004	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2005	if (ret == 0) {
cparata	0:13631b50eae6	2006	reg.tap_prior = (uint8_t) val;
cparata	0:13631b50eae6	2007	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2008	}
cparata	0:13631b50eae6	2009	return ret;
cparata	0:13631b50eae6	2010	}
cparata	0:13631b50eae6	2011
cparata	0:13631b50eae6	2012	/**
cparata	0:13631b50eae6	2013	* @brief Selection of axis priority for TAP detection.[get]
cparata	0:13631b50eae6	2014	*
cparata	0:13631b50eae6	2015	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2016	* @param val Get the values of tap_prior in reg TAP_THS_Y
cparata	0:13631b50eae6	2017	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2018	*
cparata	0:13631b50eae6	2019	*/
cparata	0:13631b50eae6	2020	int32_t iis2dlpc_tap_axis_priority_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	2021	iis2dlpc_tap_prior_t *val)
cparata	0:13631b50eae6	2022	{
cparata	0:13631b50eae6	2023	iis2dlpc_tap_ths_y_t reg;
cparata	0:13631b50eae6	2024	int32_t ret;
cparata	0:13631b50eae6	2025
cparata	0:13631b50eae6	2026	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2027
cparata	0:13631b50eae6	2028	switch (reg.tap_prior) {
cparata	0:13631b50eae6	2029	case IIS2DLPC_XYZ:
cparata	0:13631b50eae6	2030	*val = IIS2DLPC_XYZ;
cparata	0:13631b50eae6	2031	break;
cparata	0:13631b50eae6	2032	case IIS2DLPC_YXZ:
cparata	0:13631b50eae6	2033	*val = IIS2DLPC_YXZ;
cparata	0:13631b50eae6	2034	break;
cparata	0:13631b50eae6	2035	case IIS2DLPC_XZY:
cparata	0:13631b50eae6	2036	*val = IIS2DLPC_XZY;
cparata	0:13631b50eae6	2037	break;
cparata	0:13631b50eae6	2038	case IIS2DLPC_ZYX:
cparata	0:13631b50eae6	2039	*val = IIS2DLPC_ZYX;
cparata	0:13631b50eae6	2040	break;
cparata	0:13631b50eae6	2041	case IIS2DLPC_YZX:
cparata	0:13631b50eae6	2042	*val = IIS2DLPC_YZX;
cparata	0:13631b50eae6	2043	break;
cparata	0:13631b50eae6	2044	case IIS2DLPC_ZXY:
cparata	0:13631b50eae6	2045	*val = IIS2DLPC_ZXY;
cparata	0:13631b50eae6	2046	break;
cparata	0:13631b50eae6	2047	default:
cparata	0:13631b50eae6	2048	*val = IIS2DLPC_XYZ;
cparata	0:13631b50eae6	2049	break;
cparata	0:13631b50eae6	2050	}
cparata	0:13631b50eae6	2051	return ret;
cparata	0:13631b50eae6	2052	}
cparata	0:13631b50eae6	2053
cparata	0:13631b50eae6	2054	/**
cparata	0:13631b50eae6	2055	* @brief Threshold for tap recognition.[set]
cparata	0:13631b50eae6	2056	*
cparata	0:13631b50eae6	2057	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2058	* @param val change the values of tap_thsz in reg TAP_THS_Z
cparata	0:13631b50eae6	2059	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2060	*
cparata	0:13631b50eae6	2061	*/
cparata	0:13631b50eae6	2062	int32_t iis2dlpc_tap_threshold_z_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2063	{
cparata	0:13631b50eae6	2064	iis2dlpc_tap_ths_z_t reg;
cparata	0:13631b50eae6	2065	int32_t ret;
cparata	0:13631b50eae6	2066
cparata	0:13631b50eae6	2067	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2068	if (ret == 0) {
cparata	0:13631b50eae6	2069	reg.tap_thsz = val;
cparata	0:13631b50eae6	2070	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2071	}
cparata	0:13631b50eae6	2072
cparata	0:13631b50eae6	2073	return ret;
cparata	0:13631b50eae6	2074	}
cparata	0:13631b50eae6	2075
cparata	0:13631b50eae6	2076	/**
cparata	0:13631b50eae6	2077	* @brief Threshold for tap recognition.[get]
cparata	0:13631b50eae6	2078	*
cparata	0:13631b50eae6	2079	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2080	* @param val change the values of tap_thsz in reg TAP_THS_Z
cparata	0:13631b50eae6	2081	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2082	*
cparata	0:13631b50eae6	2083	*/
cparata	0:13631b50eae6	2084	int32_t iis2dlpc_tap_threshold_z_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2085	{
cparata	0:13631b50eae6	2086	iis2dlpc_tap_ths_z_t reg;
cparata	0:13631b50eae6	2087	int32_t ret;
cparata	0:13631b50eae6	2088
cparata	0:13631b50eae6	2089	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2090	*val = reg.tap_thsz;
cparata	0:13631b50eae6	2091
cparata	0:13631b50eae6	2092	return ret;
cparata	0:13631b50eae6	2093	}
cparata	0:13631b50eae6	2094
cparata	0:13631b50eae6	2095	/**
cparata	0:13631b50eae6	2096	* @brief Enable Z direction in tap recognition.[set]
cparata	0:13631b50eae6	2097	*
cparata	0:13631b50eae6	2098	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2099	* @param val change the values of tap_z_en in reg TAP_THS_Z
cparata	0:13631b50eae6	2100	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2101	*
cparata	0:13631b50eae6	2102	*/
cparata	0:13631b50eae6	2103	int32_t iis2dlpc_tap_detection_on_z_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2104	{
cparata	0:13631b50eae6	2105	iis2dlpc_tap_ths_z_t reg;
cparata	0:13631b50eae6	2106	int32_t ret;
cparata	0:13631b50eae6	2107
cparata	0:13631b50eae6	2108	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2109	if (ret == 0) {
cparata	0:13631b50eae6	2110	reg.tap_z_en = val;
cparata	0:13631b50eae6	2111	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2112	}
cparata	0:13631b50eae6	2113	return ret;
cparata	0:13631b50eae6	2114	}
cparata	0:13631b50eae6	2115
cparata	0:13631b50eae6	2116	/**
cparata	0:13631b50eae6	2117	* @brief Enable Z direction in tap recognition.[get]
cparata	0:13631b50eae6	2118	*
cparata	0:13631b50eae6	2119	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2120	* @param val change the values of tap_z_en in reg TAP_THS_Z
cparata	0:13631b50eae6	2121	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2122	*
cparata	0:13631b50eae6	2123	*/
cparata	0:13631b50eae6	2124	int32_t iis2dlpc_tap_detection_on_z_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2125	{
cparata	0:13631b50eae6	2126	iis2dlpc_tap_ths_z_t reg;
cparata	0:13631b50eae6	2127	int32_t ret;
cparata	0:13631b50eae6	2128
cparata	0:13631b50eae6	2129	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2130	*val = reg.tap_z_en;
cparata	0:13631b50eae6	2131
cparata	0:13631b50eae6	2132	return ret;
cparata	0:13631b50eae6	2133	}
cparata	0:13631b50eae6	2134
cparata	0:13631b50eae6	2135	/**
cparata	0:13631b50eae6	2136	* @brief Enable Y direction in tap recognition.[set]
cparata	0:13631b50eae6	2137	*
cparata	0:13631b50eae6	2138	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2139	* @param val change the values of tap_y_en in reg TAP_THS_Z
cparata	0:13631b50eae6	2140	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2141	*
cparata	0:13631b50eae6	2142	*/
cparata	0:13631b50eae6	2143	int32_t iis2dlpc_tap_detection_on_y_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2144	{
cparata	0:13631b50eae6	2145	iis2dlpc_tap_ths_z_t reg;
cparata	0:13631b50eae6	2146	int32_t ret;
cparata	0:13631b50eae6	2147
cparata	0:13631b50eae6	2148	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2149	if (ret == 0) {
cparata	0:13631b50eae6	2150	reg.tap_y_en = val;
cparata	0:13631b50eae6	2151	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2152	}
cparata	0:13631b50eae6	2153	return ret;
cparata	0:13631b50eae6	2154	}
cparata	0:13631b50eae6	2155
cparata	0:13631b50eae6	2156	/**
cparata	0:13631b50eae6	2157	* @brief Enable Y direction in tap recognition.[get]
cparata	0:13631b50eae6	2158	*
cparata	0:13631b50eae6	2159	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2160	* @param val change the values of tap_y_en in reg TAP_THS_Z
cparata	0:13631b50eae6	2161	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2162	*
cparata	0:13631b50eae6	2163	*/
cparata	0:13631b50eae6	2164	int32_t iis2dlpc_tap_detection_on_y_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2165	{
cparata	0:13631b50eae6	2166	iis2dlpc_tap_ths_z_t reg;
cparata	0:13631b50eae6	2167	int32_t ret;
cparata	0:13631b50eae6	2168
cparata	0:13631b50eae6	2169	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2170	*val = reg.tap_y_en;
cparata	0:13631b50eae6	2171
cparata	0:13631b50eae6	2172	return ret;
cparata	0:13631b50eae6	2173	}
cparata	0:13631b50eae6	2174
cparata	0:13631b50eae6	2175	/**
cparata	0:13631b50eae6	2176	* @brief Enable X direction in tap recognition.[set]
cparata	0:13631b50eae6	2177	*
cparata	0:13631b50eae6	2178	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2179	* @param val change the values of tap_x_en in reg TAP_THS_Z
cparata	0:13631b50eae6	2180	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2181	*
cparata	0:13631b50eae6	2182	*/
cparata	0:13631b50eae6	2183	int32_t iis2dlpc_tap_detection_on_x_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2184	{
cparata	0:13631b50eae6	2185	iis2dlpc_tap_ths_z_t reg;
cparata	0:13631b50eae6	2186	int32_t ret;
cparata	0:13631b50eae6	2187
cparata	0:13631b50eae6	2188	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2189	if (ret == 0) {
cparata	0:13631b50eae6	2190	reg.tap_x_en = val;
cparata	0:13631b50eae6	2191	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2192	}
cparata	0:13631b50eae6	2193	return ret;
cparata	0:13631b50eae6	2194	}
cparata	0:13631b50eae6	2195
cparata	0:13631b50eae6	2196	/**
cparata	0:13631b50eae6	2197	* @brief Enable X direction in tap recognition.[get]
cparata	0:13631b50eae6	2198	*
cparata	0:13631b50eae6	2199	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2200	* @param val change the values of tap_x_en in reg TAP_THS_Z
cparata	0:13631b50eae6	2201	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2202	*
cparata	0:13631b50eae6	2203	*/
cparata	0:13631b50eae6	2204	int32_t iis2dlpc_tap_detection_on_x_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2205	{
cparata	0:13631b50eae6	2206	iis2dlpc_tap_ths_z_t reg;
cparata	0:13631b50eae6	2207	int32_t ret;
cparata	0:13631b50eae6	2208
cparata	0:13631b50eae6	2209	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2210	*val = reg.tap_x_en;
cparata	0:13631b50eae6	2211
cparata	0:13631b50eae6	2212	return ret;
cparata	0:13631b50eae6	2213	}
cparata	0:13631b50eae6	2214
cparata	0:13631b50eae6	2215	/**
cparata	0:13631b50eae6	2216	* @brief Maximum duration is the maximum time of an overthreshold signal
cparata	0:13631b50eae6	2217	* detection to be recognized as a tap event. The default value
cparata	0:13631b50eae6	2218	* of these bits is 00b which corresponds to 4*ODR_XL time.
cparata	0:13631b50eae6	2219	* If the SHOCK[1:0] bits are set to a different value, 1LSB
cparata	0:13631b50eae6	2220	* corresponds to 8*ODR_XL time.[set]
cparata	0:13631b50eae6	2221	*
cparata	0:13631b50eae6	2222	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2223	* @param val change the values of shock in reg INT_DUR
cparata	0:13631b50eae6	2224	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2225	*
cparata	0:13631b50eae6	2226	*/
cparata	0:13631b50eae6	2227	int32_t iis2dlpc_tap_shock_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2228	{
cparata	0:13631b50eae6	2229	iis2dlpc_int_dur_t reg;
cparata	0:13631b50eae6	2230	int32_t ret;
cparata	0:13631b50eae6	2231
cparata	0:13631b50eae6	2232	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2233	if (ret == 0) {
cparata	0:13631b50eae6	2234	reg.shock = val;
cparata	0:13631b50eae6	2235	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2236	}
cparata	0:13631b50eae6	2237
cparata	0:13631b50eae6	2238	return ret;
cparata	0:13631b50eae6	2239	}
cparata	0:13631b50eae6	2240
cparata	0:13631b50eae6	2241	/**
cparata	0:13631b50eae6	2242	* @brief Maximum duration is the maximum time of an overthreshold signal
cparata	0:13631b50eae6	2243	* detection to be recognized as a tap event. The default value
cparata	0:13631b50eae6	2244	* of these bits is 00b which corresponds to 4*ODR_XL time.
cparata	0:13631b50eae6	2245	* If the SHOCK[1:0] bits are set to a different value, 1LSB
cparata	0:13631b50eae6	2246	* corresponds to 8*ODR_XL time.[get]
cparata	0:13631b50eae6	2247	*
cparata	0:13631b50eae6	2248	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2249	* @param val change the values of shock in reg INT_DUR
cparata	0:13631b50eae6	2250	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2251	*
cparata	0:13631b50eae6	2252	*/
cparata	0:13631b50eae6	2253	int32_t iis2dlpc_tap_shock_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2254	{
cparata	0:13631b50eae6	2255	iis2dlpc_int_dur_t reg;
cparata	0:13631b50eae6	2256	int32_t ret;
cparata	0:13631b50eae6	2257
cparata	0:13631b50eae6	2258	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2259	*val = reg.shock;
cparata	0:13631b50eae6	2260
cparata	0:13631b50eae6	2261	return ret;
cparata	0:13631b50eae6	2262	}
cparata	0:13631b50eae6	2263
cparata	0:13631b50eae6	2264	/**
cparata	0:13631b50eae6	2265	* @brief Quiet time is the time after the first detected tap in which
cparata	0:13631b50eae6	2266	* there must not be any overthreshold event.
cparata	0:13631b50eae6	2267	* The default value of these bits is 00b which corresponds
cparata	0:13631b50eae6	2268	* to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
cparata	0:13631b50eae6	2269	* value, 1LSB corresponds to 4*ODR_XL time.[set]
cparata	0:13631b50eae6	2270	*
cparata	0:13631b50eae6	2271	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2272	* @param val change the values of quiet in reg INT_DUR
cparata	0:13631b50eae6	2273	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2274	*
cparata	0:13631b50eae6	2275	*/
cparata	0:13631b50eae6	2276	int32_t iis2dlpc_tap_quiet_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2277	{
cparata	0:13631b50eae6	2278	iis2dlpc_int_dur_t reg;
cparata	0:13631b50eae6	2279	int32_t ret;
cparata	0:13631b50eae6	2280
cparata	0:13631b50eae6	2281	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2282	if (ret == 0) {
cparata	0:13631b50eae6	2283	reg.quiet = val;
cparata	0:13631b50eae6	2284	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2285	}
cparata	0:13631b50eae6	2286	return ret;
cparata	0:13631b50eae6	2287	}
cparata	0:13631b50eae6	2288
cparata	0:13631b50eae6	2289	/**
cparata	0:13631b50eae6	2290	* @brief Quiet time is the time after the first detected tap in which
cparata	0:13631b50eae6	2291	* there must not be any overthreshold event.
cparata	0:13631b50eae6	2292	* The default value of these bits is 00b which corresponds
cparata	0:13631b50eae6	2293	* to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
cparata	0:13631b50eae6	2294	* value, 1LSB corresponds to 4*ODR_XL time.[get]
cparata	0:13631b50eae6	2295	*
cparata	0:13631b50eae6	2296	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2297	* @param val change the values of quiet in reg INT_DUR
cparata	0:13631b50eae6	2298	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2299	*
cparata	0:13631b50eae6	2300	*/
cparata	0:13631b50eae6	2301	int32_t iis2dlpc_tap_quiet_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2302	{
cparata	0:13631b50eae6	2303	iis2dlpc_int_dur_t reg;
cparata	0:13631b50eae6	2304	int32_t ret;
cparata	0:13631b50eae6	2305
cparata	0:13631b50eae6	2306	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2307	*val = reg.quiet;
cparata	0:13631b50eae6	2308
cparata	0:13631b50eae6	2309	return ret;
cparata	0:13631b50eae6	2310	}
cparata	0:13631b50eae6	2311
cparata	0:13631b50eae6	2312	/**
cparata	0:13631b50eae6	2313	* @brief When double tap recognition is enabled, this register expresses
cparata	0:13631b50eae6	2314	* the maximum time between two consecutive detected taps to
cparata	0:13631b50eae6	2315	* determine a double tap event.
cparata	0:13631b50eae6	2316	* The default value of these bits is 0000b which corresponds
cparata	0:13631b50eae6	2317	* to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
cparata	0:13631b50eae6	2318	* value, 1LSB corresponds to 32*ODR_XL time.[set]
cparata	0:13631b50eae6	2319	*
cparata	0:13631b50eae6	2320	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2321	* @param val change the values of latency in reg INT_DUR
cparata	0:13631b50eae6	2322	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2323	*
cparata	0:13631b50eae6	2324	*/
cparata	0:13631b50eae6	2325	int32_t iis2dlpc_tap_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2326	{
cparata	0:13631b50eae6	2327	iis2dlpc_int_dur_t reg;
cparata	0:13631b50eae6	2328	int32_t ret;
cparata	0:13631b50eae6	2329
cparata	0:13631b50eae6	2330	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2331	if (ret == 0) {
cparata	0:13631b50eae6	2332	reg.latency = val;
cparata	0:13631b50eae6	2333	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2334	}
cparata	0:13631b50eae6	2335	return ret;
cparata	0:13631b50eae6	2336	}
cparata	0:13631b50eae6	2337
cparata	0:13631b50eae6	2338	/**
cparata	0:13631b50eae6	2339	* @brief When double tap recognition is enabled, this register expresses
cparata	0:13631b50eae6	2340	* the maximum time between two consecutive detected taps to
cparata	0:13631b50eae6	2341	* determine a double tap event.
cparata	0:13631b50eae6	2342	* The default value of these bits is 0000b which corresponds
cparata	0:13631b50eae6	2343	* to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
cparata	0:13631b50eae6	2344	* value, 1LSB corresponds to 32*ODR_XL time.[get]
cparata	0:13631b50eae6	2345	*
cparata	0:13631b50eae6	2346	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2347	* @param val change the values of latency in reg INT_DUR
cparata	0:13631b50eae6	2348	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2349	*
cparata	0:13631b50eae6	2350	*/
cparata	0:13631b50eae6	2351	int32_t iis2dlpc_tap_dur_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2352	{
cparata	0:13631b50eae6	2353	iis2dlpc_int_dur_t reg;
cparata	0:13631b50eae6	2354	int32_t ret;
cparata	0:13631b50eae6	2355
cparata	0:13631b50eae6	2356	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2357	*val = reg.latency;
cparata	0:13631b50eae6	2358
cparata	0:13631b50eae6	2359	return ret;
cparata	0:13631b50eae6	2360	}
cparata	0:13631b50eae6	2361
cparata	0:13631b50eae6	2362	/**
cparata	0:13631b50eae6	2363	* @brief Single/double-tap event enable.[set]
cparata	0:13631b50eae6	2364	*
cparata	0:13631b50eae6	2365	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2366	* @param val change the values of single_double_tap in reg WAKE_UP_THS
cparata	0:13631b50eae6	2367	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2368	*
cparata	0:13631b50eae6	2369	*/
cparata	0:13631b50eae6	2370	int32_t iis2dlpc_tap_mode_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	2371	iis2dlpc_single_double_tap_t val)
cparata	0:13631b50eae6	2372	{
cparata	0:13631b50eae6	2373	iis2dlpc_wake_up_ths_t reg;
cparata	0:13631b50eae6	2374	int32_t ret;
cparata	0:13631b50eae6	2375
cparata	0:13631b50eae6	2376	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2377	if (ret == 0) {
cparata	0:13631b50eae6	2378	reg.single_double_tap = (uint8_t) val;
cparata	0:13631b50eae6	2379	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2380	}
cparata	0:13631b50eae6	2381	return ret;
cparata	0:13631b50eae6	2382	}
cparata	0:13631b50eae6	2383
cparata	0:13631b50eae6	2384	/**
cparata	0:13631b50eae6	2385	* @brief Single/double-tap event enable.[get]
cparata	0:13631b50eae6	2386	*
cparata	0:13631b50eae6	2387	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2388	* @param val Get the values of single_double_tap in reg WAKE_UP_THS
cparata	0:13631b50eae6	2389	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2390	*
cparata	0:13631b50eae6	2391	*/
cparata	0:13631b50eae6	2392	int32_t iis2dlpc_tap_mode_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	2393	iis2dlpc_single_double_tap_t *val)
cparata	0:13631b50eae6	2394	{
cparata	0:13631b50eae6	2395	iis2dlpc_wake_up_ths_t reg;
cparata	0:13631b50eae6	2396	int32_t ret;
cparata	0:13631b50eae6	2397
cparata	0:13631b50eae6	2398	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2399
cparata	0:13631b50eae6	2400	switch (reg.single_double_tap) {
cparata	0:13631b50eae6	2401	case IIS2DLPC_ONLY_SINGLE:
cparata	0:13631b50eae6	2402	*val = IIS2DLPC_ONLY_SINGLE;
cparata	0:13631b50eae6	2403	break;
cparata	0:13631b50eae6	2404	case IIS2DLPC_BOTH_SINGLE_DOUBLE:
cparata	0:13631b50eae6	2405	*val = IIS2DLPC_BOTH_SINGLE_DOUBLE;
cparata	0:13631b50eae6	2406	break;
cparata	0:13631b50eae6	2407	default:
cparata	0:13631b50eae6	2408	*val = IIS2DLPC_ONLY_SINGLE;
cparata	0:13631b50eae6	2409	break;
cparata	0:13631b50eae6	2410	}
cparata	0:13631b50eae6	2411
cparata	0:13631b50eae6	2412	return ret;
cparata	0:13631b50eae6	2413	}
cparata	0:13631b50eae6	2414
cparata	0:13631b50eae6	2415	/**
cparata	0:13631b50eae6	2416	* @brief Read the tap / double tap source register.[get]
cparata	0:13631b50eae6	2417	*
cparata	0:13631b50eae6	2418	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2419	* @param iis2dlpc_tap_src: union of registers from TAP_SRC to
cparata	0:13631b50eae6	2420	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2421	*
cparata	0:13631b50eae6	2422	*/
cparata	0:13631b50eae6	2423	int32_t iis2dlpc_tap_src_get(iis2dlpc_ctx_t ctx, iis2dlpc_tap_src_t val)
cparata	0:13631b50eae6	2424	{
cparata	0:13631b50eae6	2425	int32_t ret;
cparata	0:13631b50eae6	2426	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_SRC, (uint8_t*) val, 1);
cparata	0:13631b50eae6	2427	return ret;
cparata	0:13631b50eae6	2428	}
cparata	0:13631b50eae6	2429
cparata	0:13631b50eae6	2430	/**
cparata	0:13631b50eae6	2431	* @}
cparata	0:13631b50eae6	2432	*
cparata	0:13631b50eae6	2433	*/
cparata	0:13631b50eae6	2434
cparata	0:13631b50eae6	2435	/**
cparata	0:13631b50eae6	2436	* @defgroup IIS2DLPC_Six_Position_Detection(6D/4D)
cparata	0:13631b50eae6	2437	* @brief This section groups all the functions concerning six
cparata	0:13631b50eae6	2438	* position detection (6D).
cparata	0:13631b50eae6	2439	* @{
cparata	0:13631b50eae6	2440	*
cparata	0:13631b50eae6	2441	*/
cparata	0:13631b50eae6	2442
cparata	0:13631b50eae6	2443	/**
cparata	0:13631b50eae6	2444	* @brief Threshold for 4D/6D function.[set]
cparata	0:13631b50eae6	2445	*
cparata	0:13631b50eae6	2446	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2447	* @param val change the values of 6d_ths in reg TAP_THS_X
cparata	0:13631b50eae6	2448	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2449	*
cparata	0:13631b50eae6	2450	*/
cparata	0:13631b50eae6	2451	int32_t iis2dlpc_6d_threshold_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2452	{
cparata	0:13631b50eae6	2453	iis2dlpc_tap_ths_x_t reg;
cparata	0:13631b50eae6	2454	int32_t ret;
cparata	0:13631b50eae6	2455
cparata	0:13631b50eae6	2456	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2457	if (ret == 0) {
cparata	0:13631b50eae6	2458	reg._6d_ths = val;
cparata	0:13631b50eae6	2459	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2460	}
cparata	0:13631b50eae6	2461	return ret;
cparata	0:13631b50eae6	2462	}
cparata	0:13631b50eae6	2463
cparata	0:13631b50eae6	2464	/**
cparata	0:13631b50eae6	2465	* @brief Threshold for 4D/6D function.[get]
cparata	0:13631b50eae6	2466	*
cparata	0:13631b50eae6	2467	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2468	* @param val change the values of 6d_ths in reg TAP_THS_X
cparata	0:13631b50eae6	2469	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2470	*
cparata	0:13631b50eae6	2471	*/
cparata	0:13631b50eae6	2472	int32_t iis2dlpc_6d_threshold_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2473	{
cparata	0:13631b50eae6	2474	iis2dlpc_tap_ths_x_t reg;
cparata	0:13631b50eae6	2475	int32_t ret;
cparata	0:13631b50eae6	2476
cparata	0:13631b50eae6	2477	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2478	*val = reg._6d_ths;
cparata	0:13631b50eae6	2479
cparata	0:13631b50eae6	2480	return ret;
cparata	0:13631b50eae6	2481	}
cparata	0:13631b50eae6	2482
cparata	0:13631b50eae6	2483	/**
cparata	0:13631b50eae6	2484	* @brief 4D orientation detection enable.[set]
cparata	0:13631b50eae6	2485	*
cparata	0:13631b50eae6	2486	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2487	* @param val change the values of 4d_en in reg TAP_THS_X
cparata	0:13631b50eae6	2488	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2489	*
cparata	0:13631b50eae6	2490	*/
cparata	0:13631b50eae6	2491	int32_t iis2dlpc_4d_mode_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2492	{
cparata	0:13631b50eae6	2493	iis2dlpc_tap_ths_x_t reg;
cparata	0:13631b50eae6	2494	int32_t ret;
cparata	0:13631b50eae6	2495
cparata	0:13631b50eae6	2496	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2497	if (ret == 0) {
cparata	0:13631b50eae6	2498	reg._4d_en = val;
cparata	0:13631b50eae6	2499	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2500	}
cparata	0:13631b50eae6	2501
cparata	0:13631b50eae6	2502	return ret;
cparata	0:13631b50eae6	2503	}
cparata	0:13631b50eae6	2504
cparata	0:13631b50eae6	2505	/**
cparata	0:13631b50eae6	2506	* @brief 4D orientation detection enable.[get]
cparata	0:13631b50eae6	2507	*
cparata	0:13631b50eae6	2508	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2509	* @param val change the values of 4d_en in reg TAP_THS_X
cparata	0:13631b50eae6	2510	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2511	*
cparata	0:13631b50eae6	2512	*/
cparata	0:13631b50eae6	2513	int32_t iis2dlpc_4d_mode_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2514	{
cparata	0:13631b50eae6	2515	iis2dlpc_tap_ths_x_t reg;
cparata	0:13631b50eae6	2516	int32_t ret;
cparata	0:13631b50eae6	2517
cparata	0:13631b50eae6	2518	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2519	*val = reg._4d_en;
cparata	0:13631b50eae6	2520
cparata	0:13631b50eae6	2521	return ret;
cparata	0:13631b50eae6	2522	}
cparata	0:13631b50eae6	2523
cparata	0:13631b50eae6	2524	/**
cparata	0:13631b50eae6	2525	* @brief Read the 6D tap source register.[get]
cparata	0:13631b50eae6	2526	*
cparata	0:13631b50eae6	2527	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2528	* @param val union of registers from SIXD_SRC
cparata	0:13631b50eae6	2529	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2530	*
cparata	0:13631b50eae6	2531	*/
cparata	0:13631b50eae6	2532	int32_t iis2dlpc_6d_src_get(iis2dlpc_ctx_t ctx, iis2dlpc_sixd_src_t val)
cparata	0:13631b50eae6	2533	{
cparata	0:13631b50eae6	2534	int32_t ret;
cparata	0:13631b50eae6	2535	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_SIXD_SRC, (uint8_t*) val, 1);
cparata	0:13631b50eae6	2536	return ret;
cparata	0:13631b50eae6	2537	}
cparata	0:13631b50eae6	2538	/**
cparata	0:13631b50eae6	2539	* @brief Data sent to 6D interrupt function.[set]
cparata	0:13631b50eae6	2540	*
cparata	0:13631b50eae6	2541	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2542	* @param val change the values of lpass_on6d in reg CTRL_REG7
cparata	0:13631b50eae6	2543	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2544	*
cparata	0:13631b50eae6	2545	*/
cparata	0:13631b50eae6	2546	int32_t iis2dlpc_6d_feed_data_set(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	2547	iis2dlpc_lpass_on6d_t val)
cparata	0:13631b50eae6	2548	{
cparata	0:13631b50eae6	2549	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	2550	int32_t ret;
cparata	0:13631b50eae6	2551
cparata	0:13631b50eae6	2552	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2553	if (ret == 0) {
cparata	0:13631b50eae6	2554	reg.lpass_on6d = (uint8_t) val;
cparata	0:13631b50eae6	2555	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2556	}
cparata	0:13631b50eae6	2557	return ret;
cparata	0:13631b50eae6	2558	}
cparata	0:13631b50eae6	2559
cparata	0:13631b50eae6	2560	/**
cparata	0:13631b50eae6	2561	* @brief Data sent to 6D interrupt function.[get]
cparata	0:13631b50eae6	2562	*
cparata	0:13631b50eae6	2563	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2564	* @param val Get the values of lpass_on6d in reg CTRL_REG7
cparata	0:13631b50eae6	2565	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2566	*
cparata	0:13631b50eae6	2567	*/
cparata	0:13631b50eae6	2568	int32_t iis2dlpc_6d_feed_data_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	2569	iis2dlpc_lpass_on6d_t *val)
cparata	0:13631b50eae6	2570	{
cparata	0:13631b50eae6	2571	iis2dlpc_ctrl_reg7_t reg;
cparata	0:13631b50eae6	2572	int32_t ret;
cparata	0:13631b50eae6	2573
cparata	0:13631b50eae6	2574	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL_REG7,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2575
cparata	0:13631b50eae6	2576	switch (reg.lpass_on6d) {
cparata	0:13631b50eae6	2577	case IIS2DLPC_ODR_DIV_2_FEED:
cparata	0:13631b50eae6	2578	*val = IIS2DLPC_ODR_DIV_2_FEED;
cparata	0:13631b50eae6	2579	break;
cparata	0:13631b50eae6	2580	case IIS2DLPC_LPF2_FEED:
cparata	0:13631b50eae6	2581	*val = IIS2DLPC_LPF2_FEED;
cparata	0:13631b50eae6	2582	break;
cparata	0:13631b50eae6	2583	default:
cparata	0:13631b50eae6	2584	*val = IIS2DLPC_ODR_DIV_2_FEED;
cparata	0:13631b50eae6	2585	break;
cparata	0:13631b50eae6	2586	}
cparata	0:13631b50eae6	2587	return ret;
cparata	0:13631b50eae6	2588	}
cparata	0:13631b50eae6	2589
cparata	0:13631b50eae6	2590	/**
cparata	0:13631b50eae6	2591	* @}
cparata	0:13631b50eae6	2592	*
cparata	0:13631b50eae6	2593	*/
cparata	0:13631b50eae6	2594
cparata	0:13631b50eae6	2595	/**
cparata	0:13631b50eae6	2596	* @defgroup IIS2DLPC_Free_Fall
cparata	0:13631b50eae6	2597	* @brief This section group all the functions concerning
cparata	0:13631b50eae6	2598	* the free fall detection.
cparata	0:13631b50eae6	2599	* @{
cparata	0:13631b50eae6	2600	*
cparata	0:13631b50eae6	2601	*/
cparata	0:13631b50eae6	2602
cparata	0:13631b50eae6	2603	/**
cparata	0:13631b50eae6	2604	* @brief Wake up duration event(1LSb = 1 / ODR).[set]
cparata	0:13631b50eae6	2605	*
cparata	0:13631b50eae6	2606	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2607	* @param val change the values of ff_dur in reg
cparata	0:13631b50eae6	2608	* WAKE_UP_DUR /F REE_FALL
cparata	0:13631b50eae6	2609	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2610	*
cparata	0:13631b50eae6	2611	*/
cparata	0:13631b50eae6	2612	int32_t iis2dlpc_ff_dur_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2613	{
cparata	0:13631b50eae6	2614	iis2dlpc_wake_up_dur_t wake_up_dur;
cparata	0:13631b50eae6	2615	iis2dlpc_free_fall_t free_fall;
cparata	0:13631b50eae6	2616	int32_t ret;
cparata	0:13631b50eae6	2617
cparata	0:13631b50eae6	2618	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	0:13631b50eae6	2619	if (ret == 0) {
cparata	0:13631b50eae6	2620	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1);
cparata	0:13631b50eae6	2621	}
cparata	0:13631b50eae6	2622	if(ret == 0) {
cparata	0:13631b50eae6	2623	wake_up_dur.ff_dur = ( (uint8_t) val & 0x20U) >> 5;
cparata	0:13631b50eae6	2624	free_fall.ff_dur = (uint8_t) val & 0x1FU;
cparata	0:13631b50eae6	2625	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	0:13631b50eae6	2626	}
cparata	0:13631b50eae6	2627	if(ret == 0) {
cparata	0:13631b50eae6	2628	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1);
cparata	0:13631b50eae6	2629	}
cparata	0:13631b50eae6	2630
cparata	0:13631b50eae6	2631	return ret;
cparata	0:13631b50eae6	2632	}
cparata	0:13631b50eae6	2633
cparata	0:13631b50eae6	2634	/**
cparata	0:13631b50eae6	2635	* @brief Wake up duration event(1LSb = 1 / ODR).[get]
cparata	0:13631b50eae6	2636	*
cparata	0:13631b50eae6	2637	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2638	* @param val change the values of ff_dur in
cparata	0:13631b50eae6	2639	* reg WAKE_UP_DUR /F REE_FALL
cparata	0:13631b50eae6	2640	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2641	*
cparata	0:13631b50eae6	2642	*/
cparata	0:13631b50eae6	2643	int32_t iis2dlpc_ff_dur_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2644	{
cparata	0:13631b50eae6	2645	iis2dlpc_wake_up_dur_t wake_up_dur;
cparata	0:13631b50eae6	2646	iis2dlpc_free_fall_t free_fall;
cparata	0:13631b50eae6	2647	int32_t ret;
cparata	0:13631b50eae6	2648
cparata	0:13631b50eae6	2649	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR,(uint8_t*) &wake_up_dur, 1);
cparata	0:13631b50eae6	2650	if (ret == 0) {
cparata	0:13631b50eae6	2651	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &free_fall, 1);
cparata	0:13631b50eae6	2652	*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
cparata	0:13631b50eae6	2653	}
cparata	0:13631b50eae6	2654	return ret;
cparata	0:13631b50eae6	2655	}
cparata	0:13631b50eae6	2656
cparata	0:13631b50eae6	2657	/**
cparata	0:13631b50eae6	2658	* @brief Free fall threshold setting.[set]
cparata	0:13631b50eae6	2659	*
cparata	0:13631b50eae6	2660	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2661	* @param val change the values of ff_ths in reg FREE_FALL
cparata	0:13631b50eae6	2662	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2663	*
cparata	0:13631b50eae6	2664	*/
cparata	0:13631b50eae6	2665	int32_t iis2dlpc_ff_threshold_set(iis2dlpc_ctx_t *ctx, iis2dlpc_ff_ths_t val)
cparata	0:13631b50eae6	2666	{
cparata	0:13631b50eae6	2667	iis2dlpc_free_fall_t reg;
cparata	0:13631b50eae6	2668	int32_t ret;
cparata	0:13631b50eae6	2669
cparata	0:13631b50eae6	2670	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2671	if (ret == 0) {
cparata	0:13631b50eae6	2672	reg.ff_ths = (uint8_t) val;
cparata	0:13631b50eae6	2673	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2674	}
cparata	0:13631b50eae6	2675
cparata	0:13631b50eae6	2676	return ret;
cparata	0:13631b50eae6	2677	}
cparata	0:13631b50eae6	2678
cparata	0:13631b50eae6	2679	/**
cparata	0:13631b50eae6	2680	* @brief Free fall threshold setting.[get]
cparata	0:13631b50eae6	2681	*
cparata	0:13631b50eae6	2682	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2683	* @param val Get the values of ff_ths in reg FREE_FALL
cparata	0:13631b50eae6	2684	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2685	*
cparata	0:13631b50eae6	2686	*/
cparata	0:13631b50eae6	2687	int32_t iis2dlpc_ff_threshold_get(iis2dlpc_ctx_t *ctx,
cparata	0:13631b50eae6	2688	iis2dlpc_ff_ths_t *val)
cparata	0:13631b50eae6	2689	{
cparata	0:13631b50eae6	2690	iis2dlpc_free_fall_t reg;
cparata	0:13631b50eae6	2691	int32_t ret;
cparata	0:13631b50eae6	2692
cparata	0:13631b50eae6	2693	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2694
cparata	0:13631b50eae6	2695	switch (reg.ff_ths) {
cparata	0:13631b50eae6	2696	case IIS2DLPC_FF_TSH_5LSb_FS2g:
cparata	0:13631b50eae6	2697	*val = IIS2DLPC_FF_TSH_5LSb_FS2g;
cparata	0:13631b50eae6	2698	break;
cparata	0:13631b50eae6	2699	case IIS2DLPC_FF_TSH_7LSb_FS2g:
cparata	0:13631b50eae6	2700	*val = IIS2DLPC_FF_TSH_7LSb_FS2g;
cparata	0:13631b50eae6	2701	break;
cparata	0:13631b50eae6	2702	case IIS2DLPC_FF_TSH_8LSb_FS2g:
cparata	0:13631b50eae6	2703	*val = IIS2DLPC_FF_TSH_8LSb_FS2g;
cparata	0:13631b50eae6	2704	break;
cparata	0:13631b50eae6	2705	case IIS2DLPC_FF_TSH_10LSb_FS2g:
cparata	0:13631b50eae6	2706	*val = IIS2DLPC_FF_TSH_10LSb_FS2g;
cparata	0:13631b50eae6	2707	break;
cparata	0:13631b50eae6	2708	case IIS2DLPC_FF_TSH_11LSb_FS2g:
cparata	0:13631b50eae6	2709	*val = IIS2DLPC_FF_TSH_11LSb_FS2g;
cparata	0:13631b50eae6	2710	break;
cparata	0:13631b50eae6	2711	case IIS2DLPC_FF_TSH_13LSb_FS2g:
cparata	0:13631b50eae6	2712	*val = IIS2DLPC_FF_TSH_13LSb_FS2g;
cparata	0:13631b50eae6	2713	break;
cparata	0:13631b50eae6	2714	case IIS2DLPC_FF_TSH_15LSb_FS2g:
cparata	0:13631b50eae6	2715	*val = IIS2DLPC_FF_TSH_15LSb_FS2g;
cparata	0:13631b50eae6	2716	break;
cparata	0:13631b50eae6	2717	case IIS2DLPC_FF_TSH_16LSb_FS2g:
cparata	0:13631b50eae6	2718	*val = IIS2DLPC_FF_TSH_16LSb_FS2g;
cparata	0:13631b50eae6	2719	break;
cparata	0:13631b50eae6	2720	default:
cparata	0:13631b50eae6	2721	*val = IIS2DLPC_FF_TSH_5LSb_FS2g;
cparata	0:13631b50eae6	2722	break;
cparata	0:13631b50eae6	2723	}
cparata	0:13631b50eae6	2724	return ret;
cparata	0:13631b50eae6	2725	}
cparata	0:13631b50eae6	2726
cparata	0:13631b50eae6	2727	/**
cparata	0:13631b50eae6	2728	* @}
cparata	0:13631b50eae6	2729	*
cparata	0:13631b50eae6	2730	*/
cparata	0:13631b50eae6	2731
cparata	0:13631b50eae6	2732	/**
cparata	0:13631b50eae6	2733	* @defgroup IIS2DLPC_Fifo
cparata	0:13631b50eae6	2734	* @brief This section group all the functions concerning the fifo usage
cparata	0:13631b50eae6	2735	* @{
cparata	0:13631b50eae6	2736	*
cparata	0:13631b50eae6	2737	*/
cparata	0:13631b50eae6	2738
cparata	0:13631b50eae6	2739	/**
cparata	0:13631b50eae6	2740	* @brief FIFO watermark level selection.[set]
cparata	0:13631b50eae6	2741	*
cparata	0:13631b50eae6	2742	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2743	* @param val change the values of fth in reg FIFO_CTRL
cparata	0:13631b50eae6	2744	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2745	*
cparata	0:13631b50eae6	2746	*/
cparata	0:13631b50eae6	2747	int32_t iis2dlpc_fifo_watermark_set(iis2dlpc_ctx_t *ctx, uint8_t val)
cparata	0:13631b50eae6	2748	{
cparata	0:13631b50eae6	2749	iis2dlpc_fifo_ctrl_t reg;
cparata	0:13631b50eae6	2750	int32_t ret;
cparata	0:13631b50eae6	2751
cparata	0:13631b50eae6	2752	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2753	if (ret == 0) {
cparata	0:13631b50eae6	2754	reg.fth = val;
cparata	0:13631b50eae6	2755	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2756	}
cparata	0:13631b50eae6	2757
cparata	0:13631b50eae6	2758	return ret;
cparata	0:13631b50eae6	2759	}
cparata	0:13631b50eae6	2760
cparata	0:13631b50eae6	2761	/**
cparata	0:13631b50eae6	2762	* @brief FIFO watermark level selection.[get]
cparata	0:13631b50eae6	2763	*
cparata	0:13631b50eae6	2764	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2765	* @param val change the values of fth in reg FIFO_CTRL
cparata	0:13631b50eae6	2766	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2767	*
cparata	0:13631b50eae6	2768	*/
cparata	0:13631b50eae6	2769	int32_t iis2dlpc_fifo_watermark_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2770	{
cparata	0:13631b50eae6	2771	iis2dlpc_fifo_ctrl_t reg;
cparata	0:13631b50eae6	2772	int32_t ret;
cparata	0:13631b50eae6	2773
cparata	0:13631b50eae6	2774	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2775	*val = reg.fth;
cparata	0:13631b50eae6	2776
cparata	0:13631b50eae6	2777	return ret;
cparata	0:13631b50eae6	2778	}
cparata	0:13631b50eae6	2779
cparata	0:13631b50eae6	2780	/**
cparata	0:13631b50eae6	2781	* @brief FIFO mode selection.[set]
cparata	0:13631b50eae6	2782	*
cparata	0:13631b50eae6	2783	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2784	* @param val change the values of fmode in reg FIFO_CTRL
cparata	0:13631b50eae6	2785	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2786	*
cparata	0:13631b50eae6	2787	*/
cparata	0:13631b50eae6	2788	int32_t iis2dlpc_fifo_mode_set(iis2dlpc_ctx_t *ctx, iis2dlpc_fmode_t val)
cparata	0:13631b50eae6	2789	{
cparata	0:13631b50eae6	2790	iis2dlpc_fifo_ctrl_t reg;
cparata	0:13631b50eae6	2791	int32_t ret;
cparata	0:13631b50eae6	2792
cparata	0:13631b50eae6	2793	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2794	if (ret == 0) {
cparata	0:13631b50eae6	2795	reg.fmode = (uint8_t) val;
cparata	0:13631b50eae6	2796	ret = iis2dlpc_write_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2797	}
cparata	0:13631b50eae6	2798	return ret;
cparata	0:13631b50eae6	2799	}
cparata	0:13631b50eae6	2800
cparata	0:13631b50eae6	2801	/**
cparata	0:13631b50eae6	2802	* @brief FIFO mode selection.[get]
cparata	0:13631b50eae6	2803	*
cparata	0:13631b50eae6	2804	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2805	* @param val Get the values of fmode in reg FIFO_CTRL
cparata	0:13631b50eae6	2806	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2807	*
cparata	0:13631b50eae6	2808	*/
cparata	0:13631b50eae6	2809	int32_t iis2dlpc_fifo_mode_get(iis2dlpc_ctx_t ctx, iis2dlpc_fmode_t val)
cparata	0:13631b50eae6	2810	{
cparata	0:13631b50eae6	2811	iis2dlpc_fifo_ctrl_t reg;
cparata	0:13631b50eae6	2812	int32_t ret;
cparata	0:13631b50eae6	2813
cparata	0:13631b50eae6	2814	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2815
cparata	0:13631b50eae6	2816	switch (reg.fmode) {
cparata	0:13631b50eae6	2817	case IIS2DLPC_BYPASS_MODE:
cparata	0:13631b50eae6	2818	*val = IIS2DLPC_BYPASS_MODE;
cparata	0:13631b50eae6	2819	break;
cparata	0:13631b50eae6	2820	case IIS2DLPC_FIFO_MODE:
cparata	0:13631b50eae6	2821	*val = IIS2DLPC_FIFO_MODE;
cparata	0:13631b50eae6	2822	break;
cparata	0:13631b50eae6	2823	case IIS2DLPC_STREAM_TO_FIFO_MODE:
cparata	0:13631b50eae6	2824	*val = IIS2DLPC_STREAM_TO_FIFO_MODE;
cparata	0:13631b50eae6	2825	break;
cparata	0:13631b50eae6	2826	case IIS2DLPC_BYPASS_TO_STREAM_MODE:
cparata	0:13631b50eae6	2827	*val = IIS2DLPC_BYPASS_TO_STREAM_MODE;
cparata	0:13631b50eae6	2828	break;
cparata	0:13631b50eae6	2829	case IIS2DLPC_STREAM_MODE:
cparata	0:13631b50eae6	2830	*val = IIS2DLPC_STREAM_MODE;
cparata	0:13631b50eae6	2831	break;
cparata	0:13631b50eae6	2832	default:
cparata	0:13631b50eae6	2833	*val = IIS2DLPC_BYPASS_MODE;
cparata	0:13631b50eae6	2834	break;
cparata	0:13631b50eae6	2835	}
cparata	0:13631b50eae6	2836	return ret;
cparata	0:13631b50eae6	2837	}
cparata	0:13631b50eae6	2838
cparata	0:13631b50eae6	2839	/**
cparata	0:13631b50eae6	2840	* @brief Number of unread samples stored in FIFO.[get]
cparata	0:13631b50eae6	2841	*
cparata	0:13631b50eae6	2842	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2843	* @param val change the values of diff in reg FIFO_SAMPLES
cparata	0:13631b50eae6	2844	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2845	*
cparata	0:13631b50eae6	2846	*/
cparata	0:13631b50eae6	2847	int32_t iis2dlpc_fifo_data_level_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2848	{
cparata	0:13631b50eae6	2849	iis2dlpc_fifo_samples_t reg;
cparata	0:13631b50eae6	2850	int32_t ret;
cparata	0:13631b50eae6	2851
cparata	0:13631b50eae6	2852	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2853	*val = reg.diff;
cparata	0:13631b50eae6	2854
cparata	0:13631b50eae6	2855	return ret;
cparata	0:13631b50eae6	2856	}
cparata	0:13631b50eae6	2857	/**
cparata	0:13631b50eae6	2858	* @brief FIFO overrun status.[get]
cparata	0:13631b50eae6	2859	*
cparata	0:13631b50eae6	2860	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2861	* @param val change the values of fifo_ovr in reg FIFO_SAMPLES
cparata	0:13631b50eae6	2862	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2863	*
cparata	0:13631b50eae6	2864	*/
cparata	0:13631b50eae6	2865	int32_t iis2dlpc_fifo_ovr_flag_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2866	{
cparata	0:13631b50eae6	2867	iis2dlpc_fifo_samples_t reg;
cparata	0:13631b50eae6	2868	int32_t ret;
cparata	0:13631b50eae6	2869
cparata	0:13631b50eae6	2870	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2871	*val = reg.fifo_ovr;
cparata	0:13631b50eae6	2872
cparata	0:13631b50eae6	2873	return ret;
cparata	0:13631b50eae6	2874	}
cparata	0:13631b50eae6	2875	/**
cparata	0:13631b50eae6	2876	* @brief FIFO threshold status flag.[get]
cparata	0:13631b50eae6	2877	*
cparata	0:13631b50eae6	2878	* @param ctx read / write interface definitions
cparata	0:13631b50eae6	2879	* @param val change the values of fifo_fth in reg FIFO_SAMPLES
cparata	0:13631b50eae6	2880	* @retval interface status (MANDATORY: return 0 -> no Error)
cparata	0:13631b50eae6	2881	*
cparata	0:13631b50eae6	2882	*/
cparata	0:13631b50eae6	2883	int32_t iis2dlpc_fifo_wtm_flag_get(iis2dlpc_ctx_t ctx, uint8_t val)
cparata	0:13631b50eae6	2884	{
cparata	0:13631b50eae6	2885	iis2dlpc_fifo_samples_t reg;
cparata	0:13631b50eae6	2886	int32_t ret;
cparata	0:13631b50eae6	2887
cparata	0:13631b50eae6	2888	ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES,(uint8_t*) &reg, 1);
cparata	0:13631b50eae6	2889	*val = reg.fifo_fth;
cparata	0:13631b50eae6	2890
cparata	0:13631b50eae6	2891	return ret;
cparata	0:13631b50eae6	2892	}
cparata	0:13631b50eae6	2893	/**
cparata	0:13631b50eae6	2894	* @}
cparata	0:13631b50eae6	2895	*
cparata	0:13631b50eae6	2896	*/
cparata	0:13631b50eae6	2897
cparata	0:13631b50eae6	2898	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	19 Nov 2018
Imports:	16
Forks:	0
Commits:	3
Dependents:	0
Dependencies:	2
Followers:	404

The code in this repository is Apache licensed.

iis2dlpc_reg.c@2:28ad92a16a36, 2018-11-21 (annotated)

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