ST / BSP_DISCO_L496AG

BSP driver for DISCO_L496AG

Dependents:   DISCO_L496AG-LCD-prova_1 DISCO_L496AG-LCD-prova_2 DISCO_L496AG-LCD-demo DISCO_L496AG-SRAM-demo

Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.c@0:d83f1c8ca282, 2018-03-26 (annotated)

Committer:
bcostm
Date:
Mon Mar 26 10:28:18 2018 +0200
Revision:
0:d83f1c8ca282
Child:
2:106c7b82e064
Add BSP files coming from CubeL4 V1.11.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 0:d83f1c8ca282 1 /**
bcostm 0:d83f1c8ca282 2 ******************************************************************************
bcostm 0:d83f1c8ca282 3 * @file mfxstm32l152.c
bcostm 0:d83f1c8ca282 4 * @author MCD Application Team
bcostm 0:d83f1c8ca282 5 * @version V2.0.0
bcostm 0:d83f1c8ca282 6 * @date 24-June-2015
bcostm 0:d83f1c8ca282 7 * @brief This file provides a set of functions needed to manage the MFXSTM32L152
bcostm 0:d83f1c8ca282 8 * IO Expander devices.
bcostm 0:d83f1c8ca282 9 ******************************************************************************
bcostm 0:d83f1c8ca282 10 * @attention
bcostm 0:d83f1c8ca282 11 *
bcostm 0:d83f1c8ca282 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bcostm 0:d83f1c8ca282 13 *
bcostm 0:d83f1c8ca282 14 * Redistribution and use in source and binary forms, with or without modification,
bcostm 0:d83f1c8ca282 15 * are permitted provided that the following conditions are met:
bcostm 0:d83f1c8ca282 16 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 0:d83f1c8ca282 17 * this list of conditions and the following disclaimer.
bcostm 0:d83f1c8ca282 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 0:d83f1c8ca282 19 * this list of conditions and the following disclaimer in the documentation
bcostm 0:d83f1c8ca282 20 * and/or other materials provided with the distribution.
bcostm 0:d83f1c8ca282 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 0:d83f1c8ca282 22 * may be used to endorse or promote products derived from this software
bcostm 0:d83f1c8ca282 23 * without specific prior written permission.
bcostm 0:d83f1c8ca282 24 *
bcostm 0:d83f1c8ca282 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 0:d83f1c8ca282 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 0:d83f1c8ca282 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 0:d83f1c8ca282 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 0:d83f1c8ca282 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 0:d83f1c8ca282 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 0:d83f1c8ca282 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 0:d83f1c8ca282 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 0:d83f1c8ca282 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 0:d83f1c8ca282 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 0:d83f1c8ca282 35 *
bcostm 0:d83f1c8ca282 36 ******************************************************************************
bcostm 0:d83f1c8ca282 37 */
bcostm 0:d83f1c8ca282 38
bcostm 0:d83f1c8ca282 39 /* Includes ------------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 40 #include "mfxstm32l152.h"
bcostm 0:d83f1c8ca282 41
bcostm 0:d83f1c8ca282 42 /** @addtogroup BSP
bcostm 0:d83f1c8ca282 43 * @{
bcostm 0:d83f1c8ca282 44 */
bcostm 0:d83f1c8ca282 45
bcostm 0:d83f1c8ca282 46 /** @addtogroup Component
bcostm 0:d83f1c8ca282 47 * @{
bcostm 0:d83f1c8ca282 48 */
bcostm 0:d83f1c8ca282 49
bcostm 0:d83f1c8ca282 50 /** @defgroup MFXSTM32L152
bcostm 0:d83f1c8ca282 51 * @{
bcostm 0:d83f1c8ca282 52 */
bcostm 0:d83f1c8ca282 53
bcostm 0:d83f1c8ca282 54 /* Private typedef -----------------------------------------------------------*/
bcostm 0:d83f1c8ca282 55
bcostm 0:d83f1c8ca282 56 /** @defgroup MFXSTM32L152_Private_Types_Definitions
bcostm 0:d83f1c8ca282 57 * @{
bcostm 0:d83f1c8ca282 58 */
bcostm 0:d83f1c8ca282 59
bcostm 0:d83f1c8ca282 60 /* Private define ------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 61
bcostm 0:d83f1c8ca282 62 /** @defgroup MFXSTM32L152_Private_Defines
bcostm 0:d83f1c8ca282 63 * @{
bcostm 0:d83f1c8ca282 64 */
bcostm 0:d83f1c8ca282 65 #define MFXSTM32L152_MAX_INSTANCE 3
bcostm 0:d83f1c8ca282 66
bcostm 0:d83f1c8ca282 67 /* Private macro -------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 68
bcostm 0:d83f1c8ca282 69 /** @defgroup MFXSTM32L152_Private_Macros
bcostm 0:d83f1c8ca282 70 * @{
bcostm 0:d83f1c8ca282 71 */
bcostm 0:d83f1c8ca282 72
bcostm 0:d83f1c8ca282 73 /* Private variables ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 74
bcostm 0:d83f1c8ca282 75 /** @defgroup MFXSTM32L152_Private_Variables
bcostm 0:d83f1c8ca282 76 * @{
bcostm 0:d83f1c8ca282 77 */
bcostm 0:d83f1c8ca282 78
bcostm 0:d83f1c8ca282 79 /* Touch screen driver structure initialization */
bcostm 0:d83f1c8ca282 80 TS_DrvTypeDef mfxstm32l152_ts_drv =
bcostm 0:d83f1c8ca282 81 {
bcostm 0:d83f1c8ca282 82 mfxstm32l152_Init,
bcostm 0:d83f1c8ca282 83 mfxstm32l152_ReadID,
bcostm 0:d83f1c8ca282 84 mfxstm32l152_Reset,
bcostm 0:d83f1c8ca282 85
bcostm 0:d83f1c8ca282 86 mfxstm32l152_TS_Start,
bcostm 0:d83f1c8ca282 87 mfxstm32l152_TS_DetectTouch,
bcostm 0:d83f1c8ca282 88 mfxstm32l152_TS_GetXY,
bcostm 0:d83f1c8ca282 89
bcostm 0:d83f1c8ca282 90 mfxstm32l152_TS_EnableIT,
bcostm 0:d83f1c8ca282 91 mfxstm32l152_TS_ClearIT,
bcostm 0:d83f1c8ca282 92 mfxstm32l152_TS_ITStatus,
bcostm 0:d83f1c8ca282 93 mfxstm32l152_TS_DisableIT,
bcostm 0:d83f1c8ca282 94 };
bcostm 0:d83f1c8ca282 95
bcostm 0:d83f1c8ca282 96 /* IO driver structure initialization */
bcostm 0:d83f1c8ca282 97 IO_DrvTypeDef mfxstm32l152_io_drv =
bcostm 0:d83f1c8ca282 98 {
bcostm 0:d83f1c8ca282 99 mfxstm32l152_Init,
bcostm 0:d83f1c8ca282 100 mfxstm32l152_ReadID,
bcostm 0:d83f1c8ca282 101 mfxstm32l152_Reset,
bcostm 0:d83f1c8ca282 102
bcostm 0:d83f1c8ca282 103 mfxstm32l152_IO_Start,
bcostm 0:d83f1c8ca282 104 mfxstm32l152_IO_Config,
bcostm 0:d83f1c8ca282 105 mfxstm32l152_IO_WritePin,
bcostm 0:d83f1c8ca282 106 mfxstm32l152_IO_ReadPin,
bcostm 0:d83f1c8ca282 107
bcostm 0:d83f1c8ca282 108 mfxstm32l152_IO_EnableIT,
bcostm 0:d83f1c8ca282 109 mfxstm32l152_IO_DisableIT,
bcostm 0:d83f1c8ca282 110 mfxstm32l152_IO_ITStatus,
bcostm 0:d83f1c8ca282 111 mfxstm32l152_IO_ClearIT,
bcostm 0:d83f1c8ca282 112 };
bcostm 0:d83f1c8ca282 113
bcostm 0:d83f1c8ca282 114 /* IDD driver structure initialization */
bcostm 0:d83f1c8ca282 115 IDD_DrvTypeDef mfxstm32l152_idd_drv =
bcostm 0:d83f1c8ca282 116 {
bcostm 0:d83f1c8ca282 117 mfxstm32l152_Init,
bcostm 0:d83f1c8ca282 118 mfxstm32l152_DeInit,
bcostm 0:d83f1c8ca282 119 mfxstm32l152_ReadID,
bcostm 0:d83f1c8ca282 120 mfxstm32l152_Reset,
bcostm 0:d83f1c8ca282 121 mfxstm32l152_LowPower,
bcostm 0:d83f1c8ca282 122 mfxstm32l152_WakeUp,
bcostm 0:d83f1c8ca282 123
bcostm 0:d83f1c8ca282 124 mfxstm32l152_IDD_Start,
bcostm 0:d83f1c8ca282 125 mfxstm32l152_IDD_Config,
bcostm 0:d83f1c8ca282 126 mfxstm32l152_IDD_GetValue,
bcostm 0:d83f1c8ca282 127
bcostm 0:d83f1c8ca282 128 mfxstm32l152_IDD_EnableIT,
bcostm 0:d83f1c8ca282 129 mfxstm32l152_IDD_ClearIT,
bcostm 0:d83f1c8ca282 130 mfxstm32l152_IDD_GetITStatus,
bcostm 0:d83f1c8ca282 131 mfxstm32l152_IDD_DisableIT,
bcostm 0:d83f1c8ca282 132
bcostm 0:d83f1c8ca282 133 mfxstm32l152_Error_EnableIT,
bcostm 0:d83f1c8ca282 134 mfxstm32l152_Error_ClearIT,
bcostm 0:d83f1c8ca282 135 mfxstm32l152_Error_GetITStatus,
bcostm 0:d83f1c8ca282 136 mfxstm32l152_Error_DisableIT,
bcostm 0:d83f1c8ca282 137 mfxstm32l152_Error_ReadSrc,
bcostm 0:d83f1c8ca282 138 mfxstm32l152_Error_ReadMsg
bcostm 0:d83f1c8ca282 139 };
bcostm 0:d83f1c8ca282 140
bcostm 0:d83f1c8ca282 141
bcostm 0:d83f1c8ca282 142 /* mfxstm32l152 instances by address */
bcostm 0:d83f1c8ca282 143 uint8_t mfxstm32l152[MFXSTM32L152_MAX_INSTANCE] = {0};
bcostm 0:d83f1c8ca282 144 /**
bcostm 0:d83f1c8ca282 145 * @}
bcostm 0:d83f1c8ca282 146 */
bcostm 0:d83f1c8ca282 147
bcostm 0:d83f1c8ca282 148 /* Private function prototypes -----------------------------------------------*/
bcostm 0:d83f1c8ca282 149
bcostm 0:d83f1c8ca282 150 /** @defgroup MFXSTM32L152_Private_Function_Prototypes
bcostm 0:d83f1c8ca282 151 * @{
bcostm 0:d83f1c8ca282 152 */
bcostm 0:d83f1c8ca282 153 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 154 static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 155 static void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue );
bcostm 0:d83f1c8ca282 156
bcostm 0:d83f1c8ca282 157 /* Private functions ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 158
bcostm 0:d83f1c8ca282 159 /** @defgroup MFXSTM32L152_Private_Functions
bcostm 0:d83f1c8ca282 160 * @{
bcostm 0:d83f1c8ca282 161 */
bcostm 0:d83f1c8ca282 162
bcostm 0:d83f1c8ca282 163 /**
bcostm 0:d83f1c8ca282 164 * @brief Initialize the mfxstm32l152 and configure the needed hardware resources
bcostm 0:d83f1c8ca282 165 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 166 * @retval None
bcostm 0:d83f1c8ca282 167 */
bcostm 0:d83f1c8ca282 168 void mfxstm32l152_Init(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 169 {
bcostm 0:d83f1c8ca282 170 uint8_t instance;
bcostm 0:d83f1c8ca282 171 uint8_t empty;
bcostm 0:d83f1c8ca282 172
bcostm 0:d83f1c8ca282 173 /* Check if device instance already exists */
bcostm 0:d83f1c8ca282 174 instance = mfxstm32l152_GetInstance(DeviceAddr);
bcostm 0:d83f1c8ca282 175
bcostm 0:d83f1c8ca282 176 /* To prevent double initialization */
bcostm 0:d83f1c8ca282 177 if(instance == 0xFF)
bcostm 0:d83f1c8ca282 178 {
bcostm 0:d83f1c8ca282 179 /* Look for empty instance */
bcostm 0:d83f1c8ca282 180 empty = mfxstm32l152_GetInstance(0);
bcostm 0:d83f1c8ca282 181
bcostm 0:d83f1c8ca282 182 if(empty < MFXSTM32L152_MAX_INSTANCE)
bcostm 0:d83f1c8ca282 183 {
bcostm 0:d83f1c8ca282 184 /* Register the current device instance */
bcostm 0:d83f1c8ca282 185 mfxstm32l152[empty] = DeviceAddr;
bcostm 0:d83f1c8ca282 186
bcostm 0:d83f1c8ca282 187 /* Initialize IO BUS layer */
bcostm 0:d83f1c8ca282 188 MFX_IO_Init();
bcostm 0:d83f1c8ca282 189 }
bcostm 0:d83f1c8ca282 190 }
bcostm 0:d83f1c8ca282 191
bcostm 0:d83f1c8ca282 192 mfxstm32l152_SetIrqOutPinPolarity(DeviceAddr, MFXSTM32L152_OUT_PIN_POLARITY_HIGH);
bcostm 0:d83f1c8ca282 193 mfxstm32l152_SetIrqOutPinType(DeviceAddr, MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL);
bcostm 0:d83f1c8ca282 194 }
bcostm 0:d83f1c8ca282 195
bcostm 0:d83f1c8ca282 196 /**
bcostm 0:d83f1c8ca282 197 * @brief DeInitialize the mfxstm32l152 and unconfigure the needed hardware resources
bcostm 0:d83f1c8ca282 198 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 199 * @retval None
bcostm 0:d83f1c8ca282 200 */
bcostm 0:d83f1c8ca282 201 void mfxstm32l152_DeInit(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 202 {
bcostm 0:d83f1c8ca282 203 uint8_t instance;
bcostm 0:d83f1c8ca282 204
bcostm 0:d83f1c8ca282 205 /* release existing instance */
bcostm 0:d83f1c8ca282 206 instance = mfxstm32l152_ReleaseInstance(DeviceAddr);
bcostm 0:d83f1c8ca282 207
bcostm 0:d83f1c8ca282 208 /* De-Init only if instance was previously registered */
bcostm 0:d83f1c8ca282 209 if(instance != 0xFF)
bcostm 0:d83f1c8ca282 210 {
bcostm 0:d83f1c8ca282 211 /* De-Initialize IO BUS layer */
bcostm 0:d83f1c8ca282 212 MFX_IO_DeInit();
bcostm 0:d83f1c8ca282 213 }
bcostm 0:d83f1c8ca282 214 }
bcostm 0:d83f1c8ca282 215
bcostm 0:d83f1c8ca282 216 /**
bcostm 0:d83f1c8ca282 217 * @brief Reset the mfxstm32l152 by Software.
bcostm 0:d83f1c8ca282 218 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 219 * @retval None
bcostm 0:d83f1c8ca282 220 */
bcostm 0:d83f1c8ca282 221 void mfxstm32l152_Reset(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 222 {
bcostm 0:d83f1c8ca282 223 /* Soft Reset */
bcostm 0:d83f1c8ca282 224 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST);
bcostm 0:d83f1c8ca282 225
bcostm 0:d83f1c8ca282 226 /* Wait for a delay to ensure registers erasing */
bcostm 0:d83f1c8ca282 227 MFX_IO_Delay(10);
bcostm 0:d83f1c8ca282 228 }
bcostm 0:d83f1c8ca282 229
bcostm 0:d83f1c8ca282 230 /**
bcostm 0:d83f1c8ca282 231 * @brief Put mfxstm32l152 Device in Low Power standby mode
bcostm 0:d83f1c8ca282 232 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 233 * @retval None
bcostm 0:d83f1c8ca282 234 */
bcostm 0:d83f1c8ca282 235 void mfxstm32l152_LowPower(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 236 {
bcostm 0:d83f1c8ca282 237 /* Enter standby mode */
bcostm 0:d83f1c8ca282 238 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY);
bcostm 0:d83f1c8ca282 239
bcostm 0:d83f1c8ca282 240 /* enable wakeup pin */
bcostm 0:d83f1c8ca282 241 MFX_IO_EnableWakeupPin();
bcostm 0:d83f1c8ca282 242 }
bcostm 0:d83f1c8ca282 243
bcostm 0:d83f1c8ca282 244 /**
bcostm 0:d83f1c8ca282 245 * @brief WakeUp mfxstm32l152 from standby mode
bcostm 0:d83f1c8ca282 246 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 247 * @retval None
bcostm 0:d83f1c8ca282 248 */
bcostm 0:d83f1c8ca282 249 void mfxstm32l152_WakeUp(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 250 {
bcostm 0:d83f1c8ca282 251 uint8_t instance;
bcostm 0:d83f1c8ca282 252
bcostm 0:d83f1c8ca282 253 /* Check if device instance already exists */
bcostm 0:d83f1c8ca282 254 instance = mfxstm32l152_GetInstance(DeviceAddr);
bcostm 0:d83f1c8ca282 255
bcostm 0:d83f1c8ca282 256 /* if instance does not exist, first initialize pins*/
bcostm 0:d83f1c8ca282 257 if(instance == 0xFF)
bcostm 0:d83f1c8ca282 258 {
bcostm 0:d83f1c8ca282 259 /* enable wakeup pin */
bcostm 0:d83f1c8ca282 260 MFX_IO_EnableWakeupPin();
bcostm 0:d83f1c8ca282 261 }
bcostm 0:d83f1c8ca282 262
bcostm 0:d83f1c8ca282 263 /* toggle wakeup pin */
bcostm 0:d83f1c8ca282 264 MFX_IO_Wakeup();
bcostm 0:d83f1c8ca282 265 }
bcostm 0:d83f1c8ca282 266
bcostm 0:d83f1c8ca282 267 /**
bcostm 0:d83f1c8ca282 268 * @brief Read the MFXSTM32L152 IO Expander device ID.
bcostm 0:d83f1c8ca282 269 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 270 * @retval The Device ID (two bytes).
bcostm 0:d83f1c8ca282 271 */
bcostm 0:d83f1c8ca282 272 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 273 {
bcostm 0:d83f1c8ca282 274 uint8_t id;
bcostm 0:d83f1c8ca282 275
bcostm 0:d83f1c8ca282 276 /* Wait for a delay to ensure the state of registers */
bcostm 0:d83f1c8ca282 277 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 278
bcostm 0:d83f1c8ca282 279 /* Initialize IO BUS layer */
bcostm 0:d83f1c8ca282 280 MFX_IO_Init();
bcostm 0:d83f1c8ca282 281
bcostm 0:d83f1c8ca282 282 id = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_ID);
bcostm 0:d83f1c8ca282 283
bcostm 0:d83f1c8ca282 284 /* Return the device ID value */
bcostm 0:d83f1c8ca282 285 return (id);
bcostm 0:d83f1c8ca282 286 }
bcostm 0:d83f1c8ca282 287
bcostm 0:d83f1c8ca282 288 /**
bcostm 0:d83f1c8ca282 289 * @brief Read the MFXSTM32L152 device firmware version.
bcostm 0:d83f1c8ca282 290 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 291 * @retval The Device FW version (two bytes).
bcostm 0:d83f1c8ca282 292 */
bcostm 0:d83f1c8ca282 293 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 294 {
bcostm 0:d83f1c8ca282 295 uint8_t data[2];
bcostm 0:d83f1c8ca282 296
bcostm 0:d83f1c8ca282 297 MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_FW_VERSION_MSB, data, sizeof(data)) ;
bcostm 0:d83f1c8ca282 298
bcostm 0:d83f1c8ca282 299 /* Recompose MFX firmware value */
bcostm 0:d83f1c8ca282 300 return ((data[0] << 8) | data[1]);
bcostm 0:d83f1c8ca282 301 }
bcostm 0:d83f1c8ca282 302
bcostm 0:d83f1c8ca282 303 /**
bcostm 0:d83f1c8ca282 304 * @brief Enable the interrupt mode for the selected IT source
bcostm 0:d83f1c8ca282 305 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 306 * @param Source: The interrupt source to be configured, could be:
bcostm 0:d83f1c8ca282 307 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
bcostm 0:d83f1c8ca282 308 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
bcostm 0:d83f1c8ca282 309 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
bcostm 0:d83f1c8ca282 310 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
bcostm 0:d83f1c8ca282 311 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
bcostm 0:d83f1c8ca282 312 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
bcostm 0:d83f1c8ca282 313 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
bcostm 0:d83f1c8ca282 314 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
bcostm 0:d83f1c8ca282 315 * @retval None
bcostm 0:d83f1c8ca282 316 */
bcostm 0:d83f1c8ca282 317 void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source)
bcostm 0:d83f1c8ca282 318 {
bcostm 0:d83f1c8ca282 319 uint8_t tmp = 0;
bcostm 0:d83f1c8ca282 320
bcostm 0:d83f1c8ca282 321 /* Get the current value of the INT_EN register */
bcostm 0:d83f1c8ca282 322 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
bcostm 0:d83f1c8ca282 323
bcostm 0:d83f1c8ca282 324 /* Set the interrupts to be Enabled */
bcostm 0:d83f1c8ca282 325 tmp |= Source;
bcostm 0:d83f1c8ca282 326
bcostm 0:d83f1c8ca282 327 /* Set the register */
bcostm 0:d83f1c8ca282 328 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
bcostm 0:d83f1c8ca282 329 }
bcostm 0:d83f1c8ca282 330
bcostm 0:d83f1c8ca282 331 /**
bcostm 0:d83f1c8ca282 332 * @brief Disable the interrupt mode for the selected IT source
bcostm 0:d83f1c8ca282 333 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 334 * @param Source: The interrupt source to be configured, could be:
bcostm 0:d83f1c8ca282 335 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
bcostm 0:d83f1c8ca282 336 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
bcostm 0:d83f1c8ca282 337 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
bcostm 0:d83f1c8ca282 338 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
bcostm 0:d83f1c8ca282 339 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
bcostm 0:d83f1c8ca282 340 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
bcostm 0:d83f1c8ca282 341 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
bcostm 0:d83f1c8ca282 342 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
bcostm 0:d83f1c8ca282 343 * @retval None
bcostm 0:d83f1c8ca282 344 */
bcostm 0:d83f1c8ca282 345 void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source)
bcostm 0:d83f1c8ca282 346 {
bcostm 0:d83f1c8ca282 347 uint8_t tmp = 0;
bcostm 0:d83f1c8ca282 348
bcostm 0:d83f1c8ca282 349 /* Get the current value of the INT_EN register */
bcostm 0:d83f1c8ca282 350 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
bcostm 0:d83f1c8ca282 351
bcostm 0:d83f1c8ca282 352 /* Set the interrupts to be Enabled */
bcostm 0:d83f1c8ca282 353 tmp &= ~Source;
bcostm 0:d83f1c8ca282 354
bcostm 0:d83f1c8ca282 355 /* Set the register */
bcostm 0:d83f1c8ca282 356 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
bcostm 0:d83f1c8ca282 357 }
bcostm 0:d83f1c8ca282 358
bcostm 0:d83f1c8ca282 359
bcostm 0:d83f1c8ca282 360 /**
bcostm 0:d83f1c8ca282 361 * @brief Returns the selected Global interrupt source pending bit value
bcostm 0:d83f1c8ca282 362 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 363 * @param Source: the Global interrupt source to be checked, could be:
bcostm 0:d83f1c8ca282 364 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
bcostm 0:d83f1c8ca282 365 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
bcostm 0:d83f1c8ca282 366 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
bcostm 0:d83f1c8ca282 367 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
bcostm 0:d83f1c8ca282 368 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
bcostm 0:d83f1c8ca282 369 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
bcostm 0:d83f1c8ca282 370 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
bcostm 0:d83f1c8ca282 371 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
bcostm 0:d83f1c8ca282 372 * @retval The value of the checked Global interrupt source status.
bcostm 0:d83f1c8ca282 373 */
bcostm 0:d83f1c8ca282 374 uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source)
bcostm 0:d83f1c8ca282 375 {
bcostm 0:d83f1c8ca282 376 /* Return the global IT source status (pending or not)*/
bcostm 0:d83f1c8ca282 377 return((MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_PENDING) & Source));
bcostm 0:d83f1c8ca282 378 }
bcostm 0:d83f1c8ca282 379
bcostm 0:d83f1c8ca282 380 /**
bcostm 0:d83f1c8ca282 381 * @brief Clear the selected Global interrupt pending bit(s)
bcostm 0:d83f1c8ca282 382 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 383 * @param Source: the Global interrupt source to be cleared, could be any combination
bcostm 0:d83f1c8ca282 384 * of the below values. The acknowledge signal for MFXSTM32L152_GPIOs configured in input
bcostm 0:d83f1c8ca282 385 * with interrupt is not on this register but in IRQ_GPI_ACK1, IRQ_GPI_ACK2 registers.
bcostm 0:d83f1c8ca282 386 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
bcostm 0:d83f1c8ca282 387 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
bcostm 0:d83f1c8ca282 388 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
bcostm 0:d83f1c8ca282 389 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
bcostm 0:d83f1c8ca282 390 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
bcostm 0:d83f1c8ca282 391 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
bcostm 0:d83f1c8ca282 392 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
bcostm 0:d83f1c8ca282 393 * /\/\ IMPORTANT NOTE /\/\ must not use MFXSTM32L152_IRQ_GPIO as argument, see IRQ_GPI_ACK1 and IRQ_GPI_ACK2 registers
bcostm 0:d83f1c8ca282 394 * @retval None
bcostm 0:d83f1c8ca282 395 */
bcostm 0:d83f1c8ca282 396 void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source)
bcostm 0:d83f1c8ca282 397 {
bcostm 0:d83f1c8ca282 398 /* Write 1 to the bits that have to be cleared */
bcostm 0:d83f1c8ca282 399 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source);
bcostm 0:d83f1c8ca282 400 }
bcostm 0:d83f1c8ca282 401
bcostm 0:d83f1c8ca282 402 /**
bcostm 0:d83f1c8ca282 403 * @brief Set the global interrupt Polarity of IRQ_OUT_PIN.
bcostm 0:d83f1c8ca282 404 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 405 * @param Polarity: the IT mode polarity, could be one of the following values:
bcostm 0:d83f1c8ca282 406 * @arg MFXSTM32L152_OUT_PIN_POLARITY_LOW: Interrupt output line is active Low edge
bcostm 0:d83f1c8ca282 407 * @arg MFXSTM32L152_OUT_PIN_POLARITY_HIGH: Interrupt line output is active High edge
bcostm 0:d83f1c8ca282 408 * @retval None
bcostm 0:d83f1c8ca282 409 */
bcostm 0:d83f1c8ca282 410 void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity)
bcostm 0:d83f1c8ca282 411 {
bcostm 0:d83f1c8ca282 412 uint8_t tmp = 0;
bcostm 0:d83f1c8ca282 413
bcostm 0:d83f1c8ca282 414 /* Get the current register value */
bcostm 0:d83f1c8ca282 415 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
bcostm 0:d83f1c8ca282 416
bcostm 0:d83f1c8ca282 417 /* Mask the polarity bits */
bcostm 0:d83f1c8ca282 418 tmp &= ~(uint8_t)0x02;
bcostm 0:d83f1c8ca282 419
bcostm 0:d83f1c8ca282 420 /* Modify the Interrupt Output line configuration */
bcostm 0:d83f1c8ca282 421 tmp |= Polarity;
bcostm 0:d83f1c8ca282 422
bcostm 0:d83f1c8ca282 423 /* Set the new register value */
bcostm 0:d83f1c8ca282 424 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
bcostm 0:d83f1c8ca282 425
bcostm 0:d83f1c8ca282 426 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
bcostm 0:d83f1c8ca282 427 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 428
bcostm 0:d83f1c8ca282 429 }
bcostm 0:d83f1c8ca282 430
bcostm 0:d83f1c8ca282 431 /**
bcostm 0:d83f1c8ca282 432 * @brief Set the global interrupt Type of IRQ_OUT_PIN.
bcostm 0:d83f1c8ca282 433 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 434 * @param Type: Interrupt line activity type, could be one of the following values:
bcostm 0:d83f1c8ca282 435 * @arg MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN: Open Drain output Interrupt line
bcostm 0:d83f1c8ca282 436 * @arg MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL: Push Pull output Interrupt line
bcostm 0:d83f1c8ca282 437 * @retval None
bcostm 0:d83f1c8ca282 438 */
bcostm 0:d83f1c8ca282 439 void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type)
bcostm 0:d83f1c8ca282 440 {
bcostm 0:d83f1c8ca282 441 uint8_t tmp = 0;
bcostm 0:d83f1c8ca282 442
bcostm 0:d83f1c8ca282 443 /* Get the current register value */
bcostm 0:d83f1c8ca282 444 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
bcostm 0:d83f1c8ca282 445
bcostm 0:d83f1c8ca282 446 /* Mask the type bits */
bcostm 0:d83f1c8ca282 447 tmp &= ~(uint8_t)0x01;
bcostm 0:d83f1c8ca282 448
bcostm 0:d83f1c8ca282 449 /* Modify the Interrupt Output line configuration */
bcostm 0:d83f1c8ca282 450 tmp |= Type;
bcostm 0:d83f1c8ca282 451
bcostm 0:d83f1c8ca282 452 /* Set the new register value */
bcostm 0:d83f1c8ca282 453 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
bcostm 0:d83f1c8ca282 454
bcostm 0:d83f1c8ca282 455 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
bcostm 0:d83f1c8ca282 456 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 457
bcostm 0:d83f1c8ca282 458 }
bcostm 0:d83f1c8ca282 459
bcostm 0:d83f1c8ca282 460
bcostm 0:d83f1c8ca282 461 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 462 /* ----------------------- GPIO ------------------------------------- */
bcostm 0:d83f1c8ca282 463 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 464
bcostm 0:d83f1c8ca282 465
bcostm 0:d83f1c8ca282 466 /**
bcostm 0:d83f1c8ca282 467 * @brief Start the IO functionality used and enable the AF for selected IO pin(s).
bcostm 0:d83f1c8ca282 468 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 469 * @param AF_en: 0 to disable, else enabled.
bcostm 0:d83f1c8ca282 470 * @retval None
bcostm 0:d83f1c8ca282 471 */
bcostm 0:d83f1c8ca282 472 void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 473 {
bcostm 0:d83f1c8ca282 474 uint8_t mode;
bcostm 0:d83f1c8ca282 475
bcostm 0:d83f1c8ca282 476 /* Get the current register value */
bcostm 0:d83f1c8ca282 477 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
bcostm 0:d83f1c8ca282 478
bcostm 0:d83f1c8ca282 479 /* Set the IO Functionalities to be Enabled */
bcostm 0:d83f1c8ca282 480 mode |= MFXSTM32L152_GPIO_EN;
bcostm 0:d83f1c8ca282 481
bcostm 0:d83f1c8ca282 482 /* Enable ALTERNATE functions */
bcostm 0:d83f1c8ca282 483 /* AGPIO[0..3] can be either IDD or GPIO */
bcostm 0:d83f1c8ca282 484 /* AGPIO[4..7] can be either TS or GPIO */
bcostm 0:d83f1c8ca282 485 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
bcostm 0:d83f1c8ca282 486 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
bcostm 0:d83f1c8ca282 487 /* so if IDD and TS are both active it is better to let ALTERNATE off (0) */
bcostm 0:d83f1c8ca282 488 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
bcostm 0:d83f1c8ca282 489 /* remind that AGPIO are less efficient then normal GPIO (They use pooling rather then EXTI */
bcostm 0:d83f1c8ca282 490 if (IO_Pin > 0xFFFF)
bcostm 0:d83f1c8ca282 491 {
bcostm 0:d83f1c8ca282 492 mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
bcostm 0:d83f1c8ca282 493 }
bcostm 0:d83f1c8ca282 494 else
bcostm 0:d83f1c8ca282 495 {
bcostm 0:d83f1c8ca282 496 mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
bcostm 0:d83f1c8ca282 497 }
bcostm 0:d83f1c8ca282 498
bcostm 0:d83f1c8ca282 499 /* Write the new register value */
bcostm 0:d83f1c8ca282 500 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
bcostm 0:d83f1c8ca282 501
bcostm 0:d83f1c8ca282 502 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
bcostm 0:d83f1c8ca282 503 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 504 }
bcostm 0:d83f1c8ca282 505
bcostm 0:d83f1c8ca282 506 /**
bcostm 0:d83f1c8ca282 507 * @brief Configures the IO pin(s) according to IO mode structure value.
bcostm 0:d83f1c8ca282 508 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 509 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
bcostm 0:d83f1c8ca282 510 * of the following values:
bcostm 0:d83f1c8ca282 511 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 512 * @param IO_Mode: The IO pin mode to configure, could be one of the following values:
bcostm 0:d83f1c8ca282 513 * @arg IO_MODE_INPUT
bcostm 0:d83f1c8ca282 514 * @arg IO_MODE_OUTPUT
bcostm 0:d83f1c8ca282 515 * @arg IO_MODE_IT_RISING_EDGE
bcostm 0:d83f1c8ca282 516 * @arg IO_MODE_IT_FALLING_EDGE
bcostm 0:d83f1c8ca282 517 * @arg IO_MODE_IT_LOW_LEVEL
bcostm 0:d83f1c8ca282 518 * @arg IO_MODE_IT_HIGH_LEVEL
bcostm 0:d83f1c8ca282 519 * @arg IO_MODE_INPUT_PU,
bcostm 0:d83f1c8ca282 520 * @arg IO_MODE_INPUT_PD,
bcostm 0:d83f1c8ca282 521 * @arg IO_MODE_OUTPUT_OD_PU,
bcostm 0:d83f1c8ca282 522 * @arg IO_MODE_OUTPUT_OD_PD,
bcostm 0:d83f1c8ca282 523 * @arg IO_MODE_OUTPUT_PP_PU,
bcostm 0:d83f1c8ca282 524 * @arg IO_MODE_OUTPUT_PP_PD,
bcostm 0:d83f1c8ca282 525 * @arg IO_MODE_IT_RISING_EDGE_PU
bcostm 0:d83f1c8ca282 526 * @arg IO_MODE_IT_FALLING_EDGE_PU
bcostm 0:d83f1c8ca282 527 * @arg IO_MODE_IT_LOW_LEVEL_PU
bcostm 0:d83f1c8ca282 528 * @arg IO_MODE_IT_HIGH_LEVEL_PU
bcostm 0:d83f1c8ca282 529 * @arg IO_MODE_IT_RISING_EDGE_PD
bcostm 0:d83f1c8ca282 530 * @arg IO_MODE_IT_FALLING_EDGE_PD
bcostm 0:d83f1c8ca282 531 * @arg IO_MODE_IT_LOW_LEVEL_PD
bcostm 0:d83f1c8ca282 532 * @arg IO_MODE_IT_HIGH_LEVEL_PD
bcostm 0:d83f1c8ca282 533 * @retval None
bcostm 0:d83f1c8ca282 534 */
bcostm 0:d83f1c8ca282 535 uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode)
bcostm 0:d83f1c8ca282 536 {
bcostm 0:d83f1c8ca282 537 uint8_t error_code = 0;
bcostm 0:d83f1c8ca282 538
bcostm 0:d83f1c8ca282 539 /* Configure IO pin according to selected IO mode */
bcostm 0:d83f1c8ca282 540 switch(IO_Mode)
bcostm 0:d83f1c8ca282 541 {
bcostm 0:d83f1c8ca282 542 case IO_MODE_OFF: /* Off or analog mode */
bcostm 0:d83f1c8ca282 543 case IO_MODE_ANALOG: /* Off or analog mode */
bcostm 0:d83f1c8ca282 544 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 545 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 546 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 547 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 548 break;
bcostm 0:d83f1c8ca282 549
bcostm 0:d83f1c8ca282 550 case IO_MODE_INPUT: /* Input mode */
bcostm 0:d83f1c8ca282 551 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 552 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 553 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 554 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 555 break;
bcostm 0:d83f1c8ca282 556
bcostm 0:d83f1c8ca282 557 case IO_MODE_INPUT_PU: /* Input mode */
bcostm 0:d83f1c8ca282 558 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 559 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 560 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 561 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 562 break;
bcostm 0:d83f1c8ca282 563
bcostm 0:d83f1c8ca282 564 case IO_MODE_INPUT_PD: /* Input mode */
bcostm 0:d83f1c8ca282 565 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 566 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 567 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 568 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 569 break;
bcostm 0:d83f1c8ca282 570
bcostm 0:d83f1c8ca282 571 case IO_MODE_OUTPUT: /* Output mode */
bcostm 0:d83f1c8ca282 572 case IO_MODE_OUTPUT_PP_PD: /* Output mode */
bcostm 0:d83f1c8ca282 573 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 574 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
bcostm 0:d83f1c8ca282 575 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
bcostm 0:d83f1c8ca282 576 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 577 break;
bcostm 0:d83f1c8ca282 578
bcostm 0:d83f1c8ca282 579 case IO_MODE_OUTPUT_PP_PU: /* Output mode */
bcostm 0:d83f1c8ca282 580 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 581 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
bcostm 0:d83f1c8ca282 582 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
bcostm 0:d83f1c8ca282 583 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 584 break;
bcostm 0:d83f1c8ca282 585
bcostm 0:d83f1c8ca282 586 case IO_MODE_OUTPUT_OD_PD: /* Output mode */
bcostm 0:d83f1c8ca282 587 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 588 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
bcostm 0:d83f1c8ca282 589 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
bcostm 0:d83f1c8ca282 590 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 591 break;
bcostm 0:d83f1c8ca282 592
bcostm 0:d83f1c8ca282 593 case IO_MODE_OUTPUT_OD_PU: /* Output mode */
bcostm 0:d83f1c8ca282 594 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 595 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
bcostm 0:d83f1c8ca282 596 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
bcostm 0:d83f1c8ca282 597 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 598 break;
bcostm 0:d83f1c8ca282 599
bcostm 0:d83f1c8ca282 600 case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */
bcostm 0:d83f1c8ca282 601 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 602 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 603 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 604 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 605 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 606 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 607 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 608 break;
bcostm 0:d83f1c8ca282 609
bcostm 0:d83f1c8ca282 610 case IO_MODE_IT_RISING_EDGE_PU: /* Interrupt rising edge mode */
bcostm 0:d83f1c8ca282 611 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 612 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 613 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 614 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 615 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 616 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 617 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 618 break;
bcostm 0:d83f1c8ca282 619
bcostm 0:d83f1c8ca282 620 case IO_MODE_IT_RISING_EDGE_PD: /* Interrupt rising edge mode */
bcostm 0:d83f1c8ca282 621 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 622 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 623 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 624 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 625 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 626 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 627 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 628 break;
bcostm 0:d83f1c8ca282 629
bcostm 0:d83f1c8ca282 630 case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */
bcostm 0:d83f1c8ca282 631 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 632 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 633 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 634 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 635 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 636 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 637 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 638 break;
bcostm 0:d83f1c8ca282 639
bcostm 0:d83f1c8ca282 640 case IO_MODE_IT_FALLING_EDGE_PU: /* Interrupt falling edge mode */
bcostm 0:d83f1c8ca282 641 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 642 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 643 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 644 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 645 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 646 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 647 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 648 break;
bcostm 0:d83f1c8ca282 649
bcostm 0:d83f1c8ca282 650 case IO_MODE_IT_FALLING_EDGE_PD: /* Interrupt falling edge mode */
bcostm 0:d83f1c8ca282 651 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 652 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 653 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 654 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 655 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 656 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 657 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 658 break;
bcostm 0:d83f1c8ca282 659
bcostm 0:d83f1c8ca282 660 case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */
bcostm 0:d83f1c8ca282 661 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 662 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 663 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 664 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 665 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 666 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 667 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 668 break;
bcostm 0:d83f1c8ca282 669
bcostm 0:d83f1c8ca282 670 case IO_MODE_IT_LOW_LEVEL_PU: /* Low level interrupt mode */
bcostm 0:d83f1c8ca282 671 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 672 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 673 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 674 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 675 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 676 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 677 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 678 break;
bcostm 0:d83f1c8ca282 679
bcostm 0:d83f1c8ca282 680 case IO_MODE_IT_LOW_LEVEL_PD: /* Low level interrupt mode */
bcostm 0:d83f1c8ca282 681 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 682 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 683 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 684 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 685 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 686 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 687 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 688 break;
bcostm 0:d83f1c8ca282 689
bcostm 0:d83f1c8ca282 690 case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */
bcostm 0:d83f1c8ca282 691 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 692 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 693 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 694 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 695 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 696 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 697 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 698 break;
bcostm 0:d83f1c8ca282 699
bcostm 0:d83f1c8ca282 700 case IO_MODE_IT_HIGH_LEVEL_PU: /* High level interrupt mode */
bcostm 0:d83f1c8ca282 701 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 702 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 703 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 704 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 705 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 706 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 707 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 708 break;
bcostm 0:d83f1c8ca282 709
bcostm 0:d83f1c8ca282 710 case IO_MODE_IT_HIGH_LEVEL_PD: /* High level interrupt mode */
bcostm 0:d83f1c8ca282 711 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 712 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 713 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 714 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 715 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 716 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 717 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 718 break;
bcostm 0:d83f1c8ca282 719
bcostm 0:d83f1c8ca282 720 default:
bcostm 0:d83f1c8ca282 721 error_code = (uint8_t) IO_Mode;
bcostm 0:d83f1c8ca282 722 break;
bcostm 0:d83f1c8ca282 723 }
bcostm 0:d83f1c8ca282 724
bcostm 0:d83f1c8ca282 725 return error_code;
bcostm 0:d83f1c8ca282 726 }
bcostm 0:d83f1c8ca282 727
bcostm 0:d83f1c8ca282 728 /**
bcostm 0:d83f1c8ca282 729 * @brief Initialize the selected IO pin direction.
bcostm 0:d83f1c8ca282 730 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 731 * @param IO_Pin: The IO pin to be configured. This parameter could be any
bcostm 0:d83f1c8ca282 732 * combination of the following values:
bcostm 0:d83f1c8ca282 733 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 734 * @param Direction: could be MFXSTM32L152_GPIO_DIR_IN or MFXSTM32L152_GPIO_DIR_OUT.
bcostm 0:d83f1c8ca282 735 * @retval None
bcostm 0:d83f1c8ca282 736 */
bcostm 0:d83f1c8ca282 737 void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction)
bcostm 0:d83f1c8ca282 738 {
bcostm 0:d83f1c8ca282 739 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_DIR1, IO_Pin, Direction);
bcostm 0:d83f1c8ca282 740 }
bcostm 0:d83f1c8ca282 741
bcostm 0:d83f1c8ca282 742 /**
bcostm 0:d83f1c8ca282 743 * @brief Set the global interrupt Type.
bcostm 0:d83f1c8ca282 744 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 745 * @param IO_Pin: The IO pin to be configured. This parameter could be any
bcostm 0:d83f1c8ca282 746 * combination of the following values:
bcostm 0:d83f1c8ca282 747 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 748 * @param Evt: Interrupt line activity type, could be one of the following values:
bcostm 0:d83f1c8ca282 749 * @arg MFXSTM32L152_IRQ_GPI_EVT_LEVEL: Interrupt line is active in level model
bcostm 0:d83f1c8ca282 750 * @arg MFXSTM32L152_IRQ_GPI_EVT_EDGE: Interrupt line is active in edge model
bcostm 0:d83f1c8ca282 751 * @retval None
bcostm 0:d83f1c8ca282 752 */
bcostm 0:d83f1c8ca282 753 void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt)
bcostm 0:d83f1c8ca282 754 {
bcostm 0:d83f1c8ca282 755 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1, IO_Pin, Evt);
bcostm 0:d83f1c8ca282 756 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 757 }
bcostm 0:d83f1c8ca282 758
bcostm 0:d83f1c8ca282 759 /**
bcostm 0:d83f1c8ca282 760 * @brief Configure the Edge for which a transition is detectable for the
bcostm 0:d83f1c8ca282 761 * selected pin.
bcostm 0:d83f1c8ca282 762 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 763 * @param IO_Pin: The IO pin to be configured. This parameter could be any
bcostm 0:d83f1c8ca282 764 * combination of the following values:
bcostm 0:d83f1c8ca282 765 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 766 * @param Evt: Interrupt line activity type, could be one of the following values:
bcostm 0:d83f1c8ca282 767 * @arg MFXSTM32L152_IRQ_GPI_TYPE_LLFE: Interrupt line is active in Low Level or Falling Edge
bcostm 0:d83f1c8ca282 768 * @arg MFXSTM32L152_IRQ_GPI_TYPE_HLRE: Interrupt line is active in High Level or Rising Edge
bcostm 0:d83f1c8ca282 769 * @retval None
bcostm 0:d83f1c8ca282 770 */
bcostm 0:d83f1c8ca282 771 void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type)
bcostm 0:d83f1c8ca282 772 {
bcostm 0:d83f1c8ca282 773 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1, IO_Pin, Type);
bcostm 0:d83f1c8ca282 774 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 775 }
bcostm 0:d83f1c8ca282 776
bcostm 0:d83f1c8ca282 777 /**
bcostm 0:d83f1c8ca282 778 * @brief When GPIO is in output mode, puts the corresponding GPO in High (1) or Low (0) level.
bcostm 0:d83f1c8ca282 779 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 780 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
bcostm 0:d83f1c8ca282 781 * of the following values:
bcostm 0:d83f1c8ca282 782 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 783 * @param PinState: The new IO pin state.
bcostm 0:d83f1c8ca282 784 * @retval None
bcostm 0:d83f1c8ca282 785 */
bcostm 0:d83f1c8ca282 786 void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState)
bcostm 0:d83f1c8ca282 787 {
bcostm 0:d83f1c8ca282 788 /* Apply the bit value to the selected pin */
bcostm 0:d83f1c8ca282 789 if (PinState != 0)
bcostm 0:d83f1c8ca282 790 {
bcostm 0:d83f1c8ca282 791 /* Set the SET register */
bcostm 0:d83f1c8ca282 792 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_SET1, IO_Pin, 1);
bcostm 0:d83f1c8ca282 793 }
bcostm 0:d83f1c8ca282 794 else
bcostm 0:d83f1c8ca282 795 {
bcostm 0:d83f1c8ca282 796 /* Set the CLEAR register */
bcostm 0:d83f1c8ca282 797 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_CLR1, IO_Pin, 1);
bcostm 0:d83f1c8ca282 798 }
bcostm 0:d83f1c8ca282 799 }
bcostm 0:d83f1c8ca282 800
bcostm 0:d83f1c8ca282 801 /**
bcostm 0:d83f1c8ca282 802 * @brief Return the state of the selected IO pin(s).
bcostm 0:d83f1c8ca282 803 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 804 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
bcostm 0:d83f1c8ca282 805 * of the following values:
bcostm 0:d83f1c8ca282 806 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 807 * @retval IO pin(s) state.
bcostm 0:d83f1c8ca282 808 */
bcostm 0:d83f1c8ca282 809 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 810 {
bcostm 0:d83f1c8ca282 811 uint8_t tmp1;
bcostm 0:d83f1c8ca282 812 uint16_t tmp2;
bcostm 0:d83f1c8ca282 813 uint32_t tmp3;
bcostm 0:d83f1c8ca282 814
bcostm 0:d83f1c8ca282 815 tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE1);
bcostm 0:d83f1c8ca282 816 tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE2);
bcostm 0:d83f1c8ca282 817 tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE3);
bcostm 0:d83f1c8ca282 818 tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
bcostm 0:d83f1c8ca282 819
bcostm 0:d83f1c8ca282 820 return(tmp3 & IO_Pin);
bcostm 0:d83f1c8ca282 821 }
bcostm 0:d83f1c8ca282 822
bcostm 0:d83f1c8ca282 823 /**
bcostm 0:d83f1c8ca282 824 * @brief Enable the global IO interrupt source.
bcostm 0:d83f1c8ca282 825 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 826 * @retval None
bcostm 0:d83f1c8ca282 827 */
bcostm 0:d83f1c8ca282 828 void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 829 {
bcostm 0:d83f1c8ca282 830 MFX_IO_ITConfig();
bcostm 0:d83f1c8ca282 831
bcostm 0:d83f1c8ca282 832 /* Enable global IO IT source */
bcostm 0:d83f1c8ca282 833 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
bcostm 0:d83f1c8ca282 834 }
bcostm 0:d83f1c8ca282 835
bcostm 0:d83f1c8ca282 836 /**
bcostm 0:d83f1c8ca282 837 * @brief Disable the global IO interrupt source.
bcostm 0:d83f1c8ca282 838 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 839 * @retval None
bcostm 0:d83f1c8ca282 840 */
bcostm 0:d83f1c8ca282 841 void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 842 {
bcostm 0:d83f1c8ca282 843 /* Disable global IO IT source */
bcostm 0:d83f1c8ca282 844 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
bcostm 0:d83f1c8ca282 845 }
bcostm 0:d83f1c8ca282 846
bcostm 0:d83f1c8ca282 847 /**
bcostm 0:d83f1c8ca282 848 * @brief Enable interrupt mode for the selected IO pin(s).
bcostm 0:d83f1c8ca282 849 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 850 * @param IO_Pin: The IO interrupt to be enabled. This parameter could be any
bcostm 0:d83f1c8ca282 851 * combination of the following values:
bcostm 0:d83f1c8ca282 852 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 853 * @retval None
bcostm 0:d83f1c8ca282 854 */
bcostm 0:d83f1c8ca282 855 void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 856 {
bcostm 0:d83f1c8ca282 857 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 1);
bcostm 0:d83f1c8ca282 858 }
bcostm 0:d83f1c8ca282 859
bcostm 0:d83f1c8ca282 860 /**
bcostm 0:d83f1c8ca282 861 * @brief Disable interrupt mode for the selected IO pin(s).
bcostm 0:d83f1c8ca282 862 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 863 * @param IO_Pin: The IO interrupt to be disabled. This parameter could be any
bcostm 0:d83f1c8ca282 864 * combination of the following values:
bcostm 0:d83f1c8ca282 865 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 866 * @retval None
bcostm 0:d83f1c8ca282 867 */
bcostm 0:d83f1c8ca282 868 void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 869 {
bcostm 0:d83f1c8ca282 870 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 0);
bcostm 0:d83f1c8ca282 871 }
bcostm 0:d83f1c8ca282 872
bcostm 0:d83f1c8ca282 873
bcostm 0:d83f1c8ca282 874 /**
bcostm 0:d83f1c8ca282 875 * @brief Check the status of the selected IO interrupt pending bit
bcostm 0:d83f1c8ca282 876 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 877 * @param IO_Pin: The IO interrupt to be checked could be:
bcostm 0:d83f1c8ca282 878 * @arg MFXSTM32L152_GPIO_PIN_x Where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 879 * @retval Status of the checked IO pin(s).
bcostm 0:d83f1c8ca282 880 */
bcostm 0:d83f1c8ca282 881 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 882 {
bcostm 0:d83f1c8ca282 883 /* Get the Interrupt status */
bcostm 0:d83f1c8ca282 884 uint8_t tmp1;
bcostm 0:d83f1c8ca282 885 uint16_t tmp2;
bcostm 0:d83f1c8ca282 886 uint32_t tmp3;
bcostm 0:d83f1c8ca282 887
bcostm 0:d83f1c8ca282 888 tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1);
bcostm 0:d83f1c8ca282 889 tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2);
bcostm 0:d83f1c8ca282 890 tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3);
bcostm 0:d83f1c8ca282 891 tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
bcostm 0:d83f1c8ca282 892
bcostm 0:d83f1c8ca282 893 return(tmp3 & IO_Pin);
bcostm 0:d83f1c8ca282 894 }
bcostm 0:d83f1c8ca282 895
bcostm 0:d83f1c8ca282 896 /**
bcostm 0:d83f1c8ca282 897 * @brief Clear the selected IO interrupt pending bit(s). It clear automatically also the general MFXSTM32L152_REG_ADR_IRQ_PENDING
bcostm 0:d83f1c8ca282 898 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 899 * @param IO_Pin: the IO interrupt to be cleared, could be:
bcostm 0:d83f1c8ca282 900 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 901 * @retval None
bcostm 0:d83f1c8ca282 902 */
bcostm 0:d83f1c8ca282 903 void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 904 {
bcostm 0:d83f1c8ca282 905 /* Clear the IO IT pending bit(s) by acknowledging */
bcostm 0:d83f1c8ca282 906 /* it cleans automatically also the Global IRQ_GPIO */
bcostm 0:d83f1c8ca282 907 /* normally this function is called under interrupt */
bcostm 0:d83f1c8ca282 908 uint8_t pin_0_7, pin_8_15, pin_16_23;
bcostm 0:d83f1c8ca282 909
bcostm 0:d83f1c8ca282 910 pin_0_7 = IO_Pin & 0x0000ff;
bcostm 0:d83f1c8ca282 911 pin_8_15 = IO_Pin >> 8;
bcostm 0:d83f1c8ca282 912 pin_8_15 = pin_8_15 & 0x00ff;
bcostm 0:d83f1c8ca282 913 pin_16_23 = IO_Pin >> 16;
bcostm 0:d83f1c8ca282 914
bcostm 0:d83f1c8ca282 915 if (pin_0_7)
bcostm 0:d83f1c8ca282 916 {
bcostm 0:d83f1c8ca282 917 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7);
bcostm 0:d83f1c8ca282 918 }
bcostm 0:d83f1c8ca282 919 if (pin_8_15)
bcostm 0:d83f1c8ca282 920 {
bcostm 0:d83f1c8ca282 921 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15);
bcostm 0:d83f1c8ca282 922 }
bcostm 0:d83f1c8ca282 923 if (pin_16_23)
bcostm 0:d83f1c8ca282 924 {
bcostm 0:d83f1c8ca282 925 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23);
bcostm 0:d83f1c8ca282 926 }
bcostm 0:d83f1c8ca282 927 }
bcostm 0:d83f1c8ca282 928
bcostm 0:d83f1c8ca282 929
bcostm 0:d83f1c8ca282 930 /**
bcostm 0:d83f1c8ca282 931 * @brief Enable the AF for aGPIO.
bcostm 0:d83f1c8ca282 932 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 933 * @retval None
bcostm 0:d83f1c8ca282 934 */
bcostm 0:d83f1c8ca282 935 void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 936 {
bcostm 0:d83f1c8ca282 937 uint8_t mode;
bcostm 0:d83f1c8ca282 938
bcostm 0:d83f1c8ca282 939 /* Get the current register value */
bcostm 0:d83f1c8ca282 940 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
bcostm 0:d83f1c8ca282 941
bcostm 0:d83f1c8ca282 942 /* Enable ALTERNATE functions */
bcostm 0:d83f1c8ca282 943 /* AGPIO[0..3] can be either IDD or GPIO */
bcostm 0:d83f1c8ca282 944 /* AGPIO[4..7] can be either TS or GPIO */
bcostm 0:d83f1c8ca282 945 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
bcostm 0:d83f1c8ca282 946 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
bcostm 0:d83f1c8ca282 947 /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
bcostm 0:d83f1c8ca282 948 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
bcostm 0:d83f1c8ca282 949 /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
bcostm 0:d83f1c8ca282 950 mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
bcostm 0:d83f1c8ca282 951
bcostm 0:d83f1c8ca282 952 /* Write the new register value */
bcostm 0:d83f1c8ca282 953 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
bcostm 0:d83f1c8ca282 954 }
bcostm 0:d83f1c8ca282 955
bcostm 0:d83f1c8ca282 956 /**
bcostm 0:d83f1c8ca282 957 * @brief Disable the AF for aGPIO.
bcostm 0:d83f1c8ca282 958 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 959 * @retval None
bcostm 0:d83f1c8ca282 960 */
bcostm 0:d83f1c8ca282 961 void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 962 {
bcostm 0:d83f1c8ca282 963 uint8_t mode;
bcostm 0:d83f1c8ca282 964
bcostm 0:d83f1c8ca282 965 /* Get the current register value */
bcostm 0:d83f1c8ca282 966 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
bcostm 0:d83f1c8ca282 967
bcostm 0:d83f1c8ca282 968 /* Enable ALTERNATE functions */
bcostm 0:d83f1c8ca282 969 /* AGPIO[0..3] can be either IDD or GPIO */
bcostm 0:d83f1c8ca282 970 /* AGPIO[4..7] can be either TS or GPIO */
bcostm 0:d83f1c8ca282 971 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
bcostm 0:d83f1c8ca282 972 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
bcostm 0:d83f1c8ca282 973 /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
bcostm 0:d83f1c8ca282 974 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
bcostm 0:d83f1c8ca282 975 /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
bcostm 0:d83f1c8ca282 976 mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
bcostm 0:d83f1c8ca282 977
bcostm 0:d83f1c8ca282 978 /* Write the new register value */
bcostm 0:d83f1c8ca282 979 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
bcostm 0:d83f1c8ca282 980
bcostm 0:d83f1c8ca282 981 }
bcostm 0:d83f1c8ca282 982
bcostm 0:d83f1c8ca282 983
bcostm 0:d83f1c8ca282 984 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 985 /* --------------------- TOUCH SCREEN ------------------------------- */
bcostm 0:d83f1c8ca282 986 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 987
bcostm 0:d83f1c8ca282 988 /**
bcostm 0:d83f1c8ca282 989 * @brief Configures the touch Screen Controller (Single point detection)
bcostm 0:d83f1c8ca282 990 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 991 * @retval None.
bcostm 0:d83f1c8ca282 992 */
bcostm 0:d83f1c8ca282 993 void mfxstm32l152_TS_Start(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 994 {
bcostm 0:d83f1c8ca282 995 uint8_t mode;
bcostm 0:d83f1c8ca282 996
bcostm 0:d83f1c8ca282 997 /* Get the current register value */
bcostm 0:d83f1c8ca282 998 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
bcostm 0:d83f1c8ca282 999
bcostm 0:d83f1c8ca282 1000 /* Set the Functionalities to be Enabled */
bcostm 0:d83f1c8ca282 1001 mode |= MFXSTM32L152_TS_EN;
bcostm 0:d83f1c8ca282 1002
bcostm 0:d83f1c8ca282 1003 /* Set the new register value */
bcostm 0:d83f1c8ca282 1004 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
bcostm 0:d83f1c8ca282 1005
bcostm 0:d83f1c8ca282 1006 /* Wait for 2 ms */
bcostm 0:d83f1c8ca282 1007 MFX_IO_Delay(2);
bcostm 0:d83f1c8ca282 1008
bcostm 0:d83f1c8ca282 1009 /* Select 2 nF filter capacitor */
bcostm 0:d83f1c8ca282 1010 /* Configuration:
bcostm 0:d83f1c8ca282 1011 - Touch average control : 4 samples
bcostm 0:d83f1c8ca282 1012 - Touch delay time : 500 uS
bcostm 0:d83f1c8ca282 1013 - Panel driver setting time: 500 uS
bcostm 0:d83f1c8ca282 1014 */
bcostm 0:d83f1c8ca282 1015 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32);
bcostm 0:d83f1c8ca282 1016 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5);
bcostm 0:d83f1c8ca282 1017 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04);
bcostm 0:d83f1c8ca282 1018
bcostm 0:d83f1c8ca282 1019 /* Configure the Touch FIFO threshold: single point reading */
bcostm 0:d83f1c8ca282 1020 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01);
bcostm 0:d83f1c8ca282 1021
bcostm 0:d83f1c8ca282 1022 /* Clear the FIFO memory content. */
bcostm 0:d83f1c8ca282 1023 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
bcostm 0:d83f1c8ca282 1024
bcostm 0:d83f1c8ca282 1025 /* Touch screen control configuration :
bcostm 0:d83f1c8ca282 1026 - No window tracking index
bcostm 0:d83f1c8ca282 1027 */
bcostm 0:d83f1c8ca282 1028 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00);
bcostm 0:d83f1c8ca282 1029
bcostm 0:d83f1c8ca282 1030
bcostm 0:d83f1c8ca282 1031 /* Clear all the IT status pending bits if any */
bcostm 0:d83f1c8ca282 1032 mfxstm32l152_IO_ClearIT(DeviceAddr, 0xFFFFFF);
bcostm 0:d83f1c8ca282 1033
bcostm 0:d83f1c8ca282 1034 /* Wait for 1 ms delay */
bcostm 0:d83f1c8ca282 1035 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 1036 }
bcostm 0:d83f1c8ca282 1037
bcostm 0:d83f1c8ca282 1038 /**
bcostm 0:d83f1c8ca282 1039 * @brief Return if there is touch detected or not.
bcostm 0:d83f1c8ca282 1040 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1041 * @retval Touch detected state.
bcostm 0:d83f1c8ca282 1042 */
bcostm 0:d83f1c8ca282 1043 uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1044 {
bcostm 0:d83f1c8ca282 1045 uint8_t state;
bcostm 0:d83f1c8ca282 1046 uint8_t ret = 0;
bcostm 0:d83f1c8ca282 1047
bcostm 0:d83f1c8ca282 1048 state = MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_STA);
bcostm 0:d83f1c8ca282 1049 state = ((state & (uint8_t)MFXSTM32L152_TS_CTRL_STATUS) == (uint8_t)MFXSTM32L152_TS_CTRL_STATUS);
bcostm 0:d83f1c8ca282 1050
bcostm 0:d83f1c8ca282 1051 if(state > 0)
bcostm 0:d83f1c8ca282 1052 {
bcostm 0:d83f1c8ca282 1053 if(MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_LEVEL) > 0)
bcostm 0:d83f1c8ca282 1054 {
bcostm 0:d83f1c8ca282 1055 ret = 1;
bcostm 0:d83f1c8ca282 1056 }
bcostm 0:d83f1c8ca282 1057 }
bcostm 0:d83f1c8ca282 1058
bcostm 0:d83f1c8ca282 1059 return ret;
bcostm 0:d83f1c8ca282 1060 }
bcostm 0:d83f1c8ca282 1061
bcostm 0:d83f1c8ca282 1062 /**
bcostm 0:d83f1c8ca282 1063 * @brief Get the touch screen X and Y positions values
bcostm 0:d83f1c8ca282 1064 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1065 * @param X: Pointer to X position value
bcostm 0:d83f1c8ca282 1066 * @param Y: Pointer to Y position value
bcostm 0:d83f1c8ca282 1067 * @retval None.
bcostm 0:d83f1c8ca282 1068 */
bcostm 0:d83f1c8ca282 1069 void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
bcostm 0:d83f1c8ca282 1070 {
bcostm 0:d83f1c8ca282 1071 uint8_t data_xy[3];
bcostm 0:d83f1c8ca282 1072
bcostm 0:d83f1c8ca282 1073 MFX_IO_ReadMultiple(DeviceAddr, MFXSTM32L152_TS_XY_DATA, data_xy, sizeof(data_xy)) ;
bcostm 0:d83f1c8ca282 1074
bcostm 0:d83f1c8ca282 1075 /* Calculate positions values */
bcostm 0:d83f1c8ca282 1076 *X = (data_xy[1]<<4) + (data_xy[0]>>4);
bcostm 0:d83f1c8ca282 1077 *Y = (data_xy[2]<<4) + (data_xy[0]&4);
bcostm 0:d83f1c8ca282 1078
bcostm 0:d83f1c8ca282 1079 /* Reset the FIFO memory content. */
bcostm 0:d83f1c8ca282 1080 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
bcostm 0:d83f1c8ca282 1081 }
bcostm 0:d83f1c8ca282 1082
bcostm 0:d83f1c8ca282 1083 /**
bcostm 0:d83f1c8ca282 1084 * @brief Configure the selected source to generate a global interrupt or not
bcostm 0:d83f1c8ca282 1085 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1086 * @retval None
bcostm 0:d83f1c8ca282 1087 */
bcostm 0:d83f1c8ca282 1088 void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1089 {
bcostm 0:d83f1c8ca282 1090 MFX_IO_ITConfig();
bcostm 0:d83f1c8ca282 1091
bcostm 0:d83f1c8ca282 1092 /* Enable global TS IT source */
bcostm 0:d83f1c8ca282 1093 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
bcostm 0:d83f1c8ca282 1094 }
bcostm 0:d83f1c8ca282 1095
bcostm 0:d83f1c8ca282 1096 /**
bcostm 0:d83f1c8ca282 1097 * @brief Configure the selected source to generate a global interrupt or not
bcostm 0:d83f1c8ca282 1098 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1099 * @retval None
bcostm 0:d83f1c8ca282 1100 */
bcostm 0:d83f1c8ca282 1101 void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1102 {
bcostm 0:d83f1c8ca282 1103 /* Disable global TS IT source */
bcostm 0:d83f1c8ca282 1104 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
bcostm 0:d83f1c8ca282 1105 }
bcostm 0:d83f1c8ca282 1106
bcostm 0:d83f1c8ca282 1107 /**
bcostm 0:d83f1c8ca282 1108 * @brief Configure the selected source to generate a global interrupt or not
bcostm 0:d83f1c8ca282 1109 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1110 * @retval TS interrupts status
bcostm 0:d83f1c8ca282 1111 */
bcostm 0:d83f1c8ca282 1112 uint8_t mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1113 {
bcostm 0:d83f1c8ca282 1114 /* Return TS interrupts status */
bcostm 0:d83f1c8ca282 1115 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_TS));
bcostm 0:d83f1c8ca282 1116 }
bcostm 0:d83f1c8ca282 1117
bcostm 0:d83f1c8ca282 1118 /**
bcostm 0:d83f1c8ca282 1119 * @brief Configure the selected source to generate a global interrupt or not
bcostm 0:d83f1c8ca282 1120 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1121 * @retval None
bcostm 0:d83f1c8ca282 1122 */
bcostm 0:d83f1c8ca282 1123 void mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1124 {
bcostm 0:d83f1c8ca282 1125 /* Clear the global TS IT source */
bcostm 0:d83f1c8ca282 1126 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_TS);
bcostm 0:d83f1c8ca282 1127 }
bcostm 0:d83f1c8ca282 1128
bcostm 0:d83f1c8ca282 1129 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1130 /* --------------------- IDD MEASUREMENT ---------------------------- */
bcostm 0:d83f1c8ca282 1131 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1132
bcostm 0:d83f1c8ca282 1133 /**
bcostm 0:d83f1c8ca282 1134 * @brief Launch IDD current measurement
bcostm 0:d83f1c8ca282 1135 * @param DeviceAddr: Device address on communication Bus
bcostm 0:d83f1c8ca282 1136 * @retval None.
bcostm 0:d83f1c8ca282 1137 */
bcostm 0:d83f1c8ca282 1138 void mfxstm32l152_IDD_Start(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1139 {
bcostm 0:d83f1c8ca282 1140 uint8_t mode = 0;
bcostm 0:d83f1c8ca282 1141
bcostm 0:d83f1c8ca282 1142 /* Get the current register value */
bcostm 0:d83f1c8ca282 1143 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
bcostm 0:d83f1c8ca282 1144
bcostm 0:d83f1c8ca282 1145 /* Set the Functionalities to be enabled */
bcostm 0:d83f1c8ca282 1146 mode |= MFXSTM32L152_IDD_CTRL_REQ;
bcostm 0:d83f1c8ca282 1147
bcostm 0:d83f1c8ca282 1148 /* Start measurement campaign */
bcostm 0:d83f1c8ca282 1149 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
bcostm 0:d83f1c8ca282 1150 }
bcostm 0:d83f1c8ca282 1151
bcostm 0:d83f1c8ca282 1152 /**
bcostm 0:d83f1c8ca282 1153 * @brief Configures the IDD current measurement
bcostm 0:d83f1c8ca282 1154 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1155 * @param MfxIddConfig: Parameters depending on hardware config.
bcostm 0:d83f1c8ca282 1156 * @retval None
bcostm 0:d83f1c8ca282 1157 */
bcostm 0:d83f1c8ca282 1158 void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig)
bcostm 0:d83f1c8ca282 1159 {
bcostm 0:d83f1c8ca282 1160 uint8_t value = 0;
bcostm 0:d83f1c8ca282 1161 uint8_t mode = 0;
bcostm 0:d83f1c8ca282 1162
bcostm 0:d83f1c8ca282 1163 /* Get the current register value */
bcostm 0:d83f1c8ca282 1164 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
bcostm 0:d83f1c8ca282 1165
bcostm 0:d83f1c8ca282 1166 if((mode & MFXSTM32L152_IDD_EN) != MFXSTM32L152_IDD_EN)
bcostm 0:d83f1c8ca282 1167 {
bcostm 0:d83f1c8ca282 1168 /* Set the Functionalities to be enabled */
bcostm 0:d83f1c8ca282 1169 mode |= MFXSTM32L152_IDD_EN;
bcostm 0:d83f1c8ca282 1170
bcostm 0:d83f1c8ca282 1171 /* Set the new register value */
bcostm 0:d83f1c8ca282 1172 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
bcostm 0:d83f1c8ca282 1173 }
bcostm 0:d83f1c8ca282 1174
bcostm 0:d83f1c8ca282 1175 /* Control register setting: number of shunts */
bcostm 0:d83f1c8ca282 1176 value = ((MfxIddConfig.ShuntNbUsed << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
bcostm 0:d83f1c8ca282 1177 value |= (MfxIddConfig.VrefMeasurement & MFXSTM32L152_IDD_CTRL_VREF_DIS);
bcostm 0:d83f1c8ca282 1178 value |= (MfxIddConfig.Calibration & MFXSTM32L152_IDD_CTRL_CAL_DIS);
bcostm 0:d83f1c8ca282 1179 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value);
bcostm 0:d83f1c8ca282 1180
bcostm 0:d83f1c8ca282 1181 /* Idd pre delay configuration: unit and value*/
bcostm 0:d83f1c8ca282 1182 value = (MfxIddConfig.PreDelayUnit & MFXSTM32L152_IDD_PREDELAY_UNIT) |
bcostm 0:d83f1c8ca282 1183 (MfxIddConfig.PreDelayValue & MFXSTM32L152_IDD_PREDELAY_VALUE);
bcostm 0:d83f1c8ca282 1184 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value);
bcostm 0:d83f1c8ca282 1185
bcostm 0:d83f1c8ca282 1186 /* Shunt 0 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1187 value = (uint8_t) (MfxIddConfig.Shunt0Value >> 8);
bcostm 0:d83f1c8ca282 1188 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value);
bcostm 0:d83f1c8ca282 1189 value = (uint8_t) (MfxIddConfig.Shunt0Value);
bcostm 0:d83f1c8ca282 1190 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value);
bcostm 0:d83f1c8ca282 1191
bcostm 0:d83f1c8ca282 1192 /* Shunt 1 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1193 value = (uint8_t) (MfxIddConfig.Shunt1Value >> 8);
bcostm 0:d83f1c8ca282 1194 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value);
bcostm 0:d83f1c8ca282 1195 value = (uint8_t) (MfxIddConfig.Shunt1Value);
bcostm 0:d83f1c8ca282 1196 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value);
bcostm 0:d83f1c8ca282 1197
bcostm 0:d83f1c8ca282 1198 /* Shunt 2 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1199 value = (uint8_t) (MfxIddConfig.Shunt2Value >> 8);
bcostm 0:d83f1c8ca282 1200 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value);
bcostm 0:d83f1c8ca282 1201 value = (uint8_t) (MfxIddConfig.Shunt2Value);
bcostm 0:d83f1c8ca282 1202 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value);
bcostm 0:d83f1c8ca282 1203
bcostm 0:d83f1c8ca282 1204 /* Shunt 3 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1205 value = (uint8_t) (MfxIddConfig.Shunt3Value >> 8);
bcostm 0:d83f1c8ca282 1206 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value);
bcostm 0:d83f1c8ca282 1207 value = (uint8_t) (MfxIddConfig.Shunt3Value);
bcostm 0:d83f1c8ca282 1208 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value);
bcostm 0:d83f1c8ca282 1209
bcostm 0:d83f1c8ca282 1210 /* Shunt 4 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1211 value = (uint8_t) (MfxIddConfig.Shunt4Value >> 8);
bcostm 0:d83f1c8ca282 1212 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value);
bcostm 0:d83f1c8ca282 1213 value = (uint8_t) (MfxIddConfig.Shunt4Value);
bcostm 0:d83f1c8ca282 1214 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value);
bcostm 0:d83f1c8ca282 1215
bcostm 0:d83f1c8ca282 1216 /* Shunt 0 stabilization delay */
bcostm 0:d83f1c8ca282 1217 value = MfxIddConfig.Shunt0StabDelay;
bcostm 0:d83f1c8ca282 1218 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1219
bcostm 0:d83f1c8ca282 1220 /* Shunt 1 stabilization delay */
bcostm 0:d83f1c8ca282 1221 value = MfxIddConfig.Shunt1StabDelay;
bcostm 0:d83f1c8ca282 1222 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1223
bcostm 0:d83f1c8ca282 1224 /* Shunt 2 stabilization delay */
bcostm 0:d83f1c8ca282 1225 value = MfxIddConfig.Shunt2StabDelay;
bcostm 0:d83f1c8ca282 1226 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1227
bcostm 0:d83f1c8ca282 1228 /* Shunt 3 stabilization delay */
bcostm 0:d83f1c8ca282 1229 value = MfxIddConfig.Shunt3StabDelay;
bcostm 0:d83f1c8ca282 1230 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1231
bcostm 0:d83f1c8ca282 1232 /* Shunt 4 stabilization delay */
bcostm 0:d83f1c8ca282 1233 value = MfxIddConfig.Shunt4StabDelay;
bcostm 0:d83f1c8ca282 1234 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1235
bcostm 0:d83f1c8ca282 1236 /* Idd ampli gain value: MSB then LSB */
bcostm 0:d83f1c8ca282 1237 value = (uint8_t) (MfxIddConfig.AmpliGain >> 8);
bcostm 0:d83f1c8ca282 1238 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value);
bcostm 0:d83f1c8ca282 1239 value = (uint8_t) (MfxIddConfig.AmpliGain);
bcostm 0:d83f1c8ca282 1240 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value);
bcostm 0:d83f1c8ca282 1241
bcostm 0:d83f1c8ca282 1242 /* Idd VDD min value: MSB then LSB */
bcostm 0:d83f1c8ca282 1243 value = (uint8_t) (MfxIddConfig.VddMin >> 8);
bcostm 0:d83f1c8ca282 1244 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value);
bcostm 0:d83f1c8ca282 1245 value = (uint8_t) (MfxIddConfig.VddMin);
bcostm 0:d83f1c8ca282 1246 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value);
bcostm 0:d83f1c8ca282 1247
bcostm 0:d83f1c8ca282 1248 /* Idd number of measurements */
bcostm 0:d83f1c8ca282 1249 value = MfxIddConfig.MeasureNb;
bcostm 0:d83f1c8ca282 1250 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value);
bcostm 0:d83f1c8ca282 1251
bcostm 0:d83f1c8ca282 1252 /* Idd delta delay configuration: unit and value */
bcostm 0:d83f1c8ca282 1253 value = (MfxIddConfig.DeltaDelayUnit & MFXSTM32L152_IDD_DELTADELAY_UNIT) |
bcostm 0:d83f1c8ca282 1254 (MfxIddConfig.DeltaDelayValue & MFXSTM32L152_IDD_DELTADELAY_VALUE);
bcostm 0:d83f1c8ca282 1255 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value);
bcostm 0:d83f1c8ca282 1256
bcostm 0:d83f1c8ca282 1257 /* Idd number of shut on board */
bcostm 0:d83f1c8ca282 1258 value = MfxIddConfig.ShuntNbOnBoard;
bcostm 0:d83f1c8ca282 1259 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value);
bcostm 0:d83f1c8ca282 1260 }
bcostm 0:d83f1c8ca282 1261
bcostm 0:d83f1c8ca282 1262 /**
bcostm 0:d83f1c8ca282 1263 * @brief This function allows to modify number of shunt used for a measurement
bcostm 0:d83f1c8ca282 1264 * @param DeviceAddr: Device address on communication Bus
bcostm 0:d83f1c8ca282 1265 * @retval None.
bcostm 0:d83f1c8ca282 1266 */
bcostm 0:d83f1c8ca282 1267 void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit)
bcostm 0:d83f1c8ca282 1268 {
bcostm 0:d83f1c8ca282 1269 uint8_t mode = 0;
bcostm 0:d83f1c8ca282 1270
bcostm 0:d83f1c8ca282 1271 /* Get the current register value */
bcostm 0:d83f1c8ca282 1272 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
bcostm 0:d83f1c8ca282 1273
bcostm 0:d83f1c8ca282 1274 /* Clear number of shunt limit */
bcostm 0:d83f1c8ca282 1275 mode &= ~(MFXSTM32L152_IDD_CTRL_SHUNT_NB);
bcostm 0:d83f1c8ca282 1276
bcostm 0:d83f1c8ca282 1277 /* Clear number of shunt limit */
bcostm 0:d83f1c8ca282 1278 mode |= ((ShuntNbLimit << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
bcostm 0:d83f1c8ca282 1279
bcostm 0:d83f1c8ca282 1280 /* Write noewx desired limit */
bcostm 0:d83f1c8ca282 1281 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
bcostm 0:d83f1c8ca282 1282 }
bcostm 0:d83f1c8ca282 1283
bcostm 0:d83f1c8ca282 1284 /**
bcostm 0:d83f1c8ca282 1285 * @brief Get Idd current value
bcostm 0:d83f1c8ca282 1286 * @param DeviceAddr: Device address on communication Bus
bcostm 0:d83f1c8ca282 1287 * @param ReadValue: Pointer on value to be read
bcostm 0:d83f1c8ca282 1288 * @retval Idd value in 10 nA.
bcostm 0:d83f1c8ca282 1289 */
bcostm 0:d83f1c8ca282 1290 void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue)
bcostm 0:d83f1c8ca282 1291 {
bcostm 0:d83f1c8ca282 1292 uint8_t data[3];
bcostm 0:d83f1c8ca282 1293
bcostm 0:d83f1c8ca282 1294 MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VALUE_MSB, data, sizeof(data)) ;
bcostm 0:d83f1c8ca282 1295
bcostm 0:d83f1c8ca282 1296 /* Recompose Idd current value */
bcostm 0:d83f1c8ca282 1297 *ReadValue = (data[0] << 16) | (data[1] << 8) | data[2];
bcostm 0:d83f1c8ca282 1298
bcostm 0:d83f1c8ca282 1299 }
bcostm 0:d83f1c8ca282 1300
bcostm 0:d83f1c8ca282 1301 /**
bcostm 0:d83f1c8ca282 1302 * @brief Get Last shunt used for measurement
bcostm 0:d83f1c8ca282 1303 * @param DeviceAddr: Device address on communication Bus
bcostm 0:d83f1c8ca282 1304 * @retval Last shunt used
bcostm 0:d83f1c8ca282 1305 */
bcostm 0:d83f1c8ca282 1306 uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1307 {
bcostm 0:d83f1c8ca282 1308 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT_USED));
bcostm 0:d83f1c8ca282 1309 }
bcostm 0:d83f1c8ca282 1310
bcostm 0:d83f1c8ca282 1311 /**
bcostm 0:d83f1c8ca282 1312 * @brief Configure mfx to enable Idd interrupt
bcostm 0:d83f1c8ca282 1313 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1314 * @retval None
bcostm 0:d83f1c8ca282 1315 */
bcostm 0:d83f1c8ca282 1316 void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1317 {
bcostm 0:d83f1c8ca282 1318 MFX_IO_ITConfig();
bcostm 0:d83f1c8ca282 1319
bcostm 0:d83f1c8ca282 1320 /* Enable global IDD interrupt source */
bcostm 0:d83f1c8ca282 1321 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
bcostm 0:d83f1c8ca282 1322 }
bcostm 0:d83f1c8ca282 1323
bcostm 0:d83f1c8ca282 1324 /**
bcostm 0:d83f1c8ca282 1325 * @brief Clear Idd global interrupt
bcostm 0:d83f1c8ca282 1326 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1327 * @retval None
bcostm 0:d83f1c8ca282 1328 */
bcostm 0:d83f1c8ca282 1329 void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1330 {
bcostm 0:d83f1c8ca282 1331 /* Clear the global IDD interrupt source */
bcostm 0:d83f1c8ca282 1332 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_IDD);
bcostm 0:d83f1c8ca282 1333 }
bcostm 0:d83f1c8ca282 1334
bcostm 0:d83f1c8ca282 1335 /**
bcostm 0:d83f1c8ca282 1336 * @brief get Idd interrupt status
bcostm 0:d83f1c8ca282 1337 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1338 * @retval IDD interrupts status
bcostm 0:d83f1c8ca282 1339 */
bcostm 0:d83f1c8ca282 1340 uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1341 {
bcostm 0:d83f1c8ca282 1342 /* Return IDD interrupt status */
bcostm 0:d83f1c8ca282 1343 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_IDD));
bcostm 0:d83f1c8ca282 1344 }
bcostm 0:d83f1c8ca282 1345
bcostm 0:d83f1c8ca282 1346 /**
bcostm 0:d83f1c8ca282 1347 * @brief disable Idd interrupt
bcostm 0:d83f1c8ca282 1348 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1349 * @retval None.
bcostm 0:d83f1c8ca282 1350 */
bcostm 0:d83f1c8ca282 1351 void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1352 {
bcostm 0:d83f1c8ca282 1353 /* Disable global IDD interrupt source */
bcostm 0:d83f1c8ca282 1354 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
bcostm 0:d83f1c8ca282 1355 }
bcostm 0:d83f1c8ca282 1356
bcostm 0:d83f1c8ca282 1357
bcostm 0:d83f1c8ca282 1358 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1359 /* --------------------- ERROR MANAGEMENT --------------------------- */
bcostm 0:d83f1c8ca282 1360 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1361
bcostm 0:d83f1c8ca282 1362 /**
bcostm 0:d83f1c8ca282 1363 * @brief Read Error Source.
bcostm 0:d83f1c8ca282 1364 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1365 * @retval Error message code with error source
bcostm 0:d83f1c8ca282 1366 */
bcostm 0:d83f1c8ca282 1367 uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1368 {
bcostm 0:d83f1c8ca282 1369 /* Get the current source register value */
bcostm 0:d83f1c8ca282 1370 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_SRC));
bcostm 0:d83f1c8ca282 1371 }
bcostm 0:d83f1c8ca282 1372
bcostm 0:d83f1c8ca282 1373 /**
bcostm 0:d83f1c8ca282 1374 * @brief Read Error Message
bcostm 0:d83f1c8ca282 1375 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1376 * @retval Error message code with error source
bcostm 0:d83f1c8ca282 1377 */
bcostm 0:d83f1c8ca282 1378 uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1379 {
bcostm 0:d83f1c8ca282 1380 /* Get the current message register value */
bcostm 0:d83f1c8ca282 1381 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_MSG));
bcostm 0:d83f1c8ca282 1382 }
bcostm 0:d83f1c8ca282 1383
bcostm 0:d83f1c8ca282 1384 /**
bcostm 0:d83f1c8ca282 1385 * @brief Enable Error global interrupt
bcostm 0:d83f1c8ca282 1386 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1387 * @retval None
bcostm 0:d83f1c8ca282 1388 */
bcostm 0:d83f1c8ca282 1389
bcostm 0:d83f1c8ca282 1390 void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1391 {
bcostm 0:d83f1c8ca282 1392 MFX_IO_ITConfig();
bcostm 0:d83f1c8ca282 1393
bcostm 0:d83f1c8ca282 1394 /* Enable global Error interrupt source */
bcostm 0:d83f1c8ca282 1395 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
bcostm 0:d83f1c8ca282 1396 }
bcostm 0:d83f1c8ca282 1397
bcostm 0:d83f1c8ca282 1398 /**
bcostm 0:d83f1c8ca282 1399 * @brief Clear Error global interrupt
bcostm 0:d83f1c8ca282 1400 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1401 * @retval None
bcostm 0:d83f1c8ca282 1402 */
bcostm 0:d83f1c8ca282 1403 void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1404 {
bcostm 0:d83f1c8ca282 1405 /* Clear the global Error interrupt source */
bcostm 0:d83f1c8ca282 1406 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
bcostm 0:d83f1c8ca282 1407 }
bcostm 0:d83f1c8ca282 1408
bcostm 0:d83f1c8ca282 1409 /**
bcostm 0:d83f1c8ca282 1410 * @brief get Error interrupt status
bcostm 0:d83f1c8ca282 1411 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1412 * @retval Error interrupts status
bcostm 0:d83f1c8ca282 1413 */
bcostm 0:d83f1c8ca282 1414 uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1415 {
bcostm 0:d83f1c8ca282 1416 /* Return Error interrupt status */
bcostm 0:d83f1c8ca282 1417 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_ERROR));
bcostm 0:d83f1c8ca282 1418 }
bcostm 0:d83f1c8ca282 1419
bcostm 0:d83f1c8ca282 1420 /**
bcostm 0:d83f1c8ca282 1421 * @brief disable Error interrupt
bcostm 0:d83f1c8ca282 1422 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1423 * @retval None.
bcostm 0:d83f1c8ca282 1424 */
bcostm 0:d83f1c8ca282 1425 void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1426 {
bcostm 0:d83f1c8ca282 1427 /* Disable global Error interrupt source */
bcostm 0:d83f1c8ca282 1428 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
bcostm 0:d83f1c8ca282 1429 }
bcostm 0:d83f1c8ca282 1430
bcostm 0:d83f1c8ca282 1431 /**
bcostm 0:d83f1c8ca282 1432 * @brief FOR DEBUG ONLY
bcostm 0:d83f1c8ca282 1433 */
bcostm 0:d83f1c8ca282 1434 uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr)
bcostm 0:d83f1c8ca282 1435 {
bcostm 0:d83f1c8ca282 1436 /* Get the current register value */
bcostm 0:d83f1c8ca282 1437 return(MFX_IO_Read((uint8_t) DeviceAddr, RegAddr));
bcostm 0:d83f1c8ca282 1438 }
bcostm 0:d83f1c8ca282 1439
bcostm 0:d83f1c8ca282 1440 void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value)
bcostm 0:d83f1c8ca282 1441 {
bcostm 0:d83f1c8ca282 1442 /* set the current register value */
bcostm 0:d83f1c8ca282 1443 MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value);
bcostm 0:d83f1c8ca282 1444 }
bcostm 0:d83f1c8ca282 1445
bcostm 0:d83f1c8ca282 1446 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1447 /* ----------------------- Private functions ------------------------ */
bcostm 0:d83f1c8ca282 1448 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1449 /**
bcostm 0:d83f1c8ca282 1450 * @brief Check if the device instance of the selected address is already registered
bcostm 0:d83f1c8ca282 1451 * and return its index
bcostm 0:d83f1c8ca282 1452 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1453 * @retval Index of the device instance if registered, 0xFF if not.
bcostm 0:d83f1c8ca282 1454 */
bcostm 0:d83f1c8ca282 1455 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1456 {
bcostm 0:d83f1c8ca282 1457 uint8_t idx = 0;
bcostm 0:d83f1c8ca282 1458
bcostm 0:d83f1c8ca282 1459 /* Check all the registered instances */
bcostm 0:d83f1c8ca282 1460 for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
bcostm 0:d83f1c8ca282 1461 {
bcostm 0:d83f1c8ca282 1462 if(mfxstm32l152[idx] == DeviceAddr)
bcostm 0:d83f1c8ca282 1463 {
bcostm 0:d83f1c8ca282 1464 return idx;
bcostm 0:d83f1c8ca282 1465 }
bcostm 0:d83f1c8ca282 1466 }
bcostm 0:d83f1c8ca282 1467
bcostm 0:d83f1c8ca282 1468 return 0xFF;
bcostm 0:d83f1c8ca282 1469 }
bcostm 0:d83f1c8ca282 1470
bcostm 0:d83f1c8ca282 1471 /**
bcostm 0:d83f1c8ca282 1472 * @brief Release registered device instance
bcostm 0:d83f1c8ca282 1473 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1474 * @retval Index of released device instance, 0xFF if not.
bcostm 0:d83f1c8ca282 1475 */
bcostm 0:d83f1c8ca282 1476 static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1477 {
bcostm 0:d83f1c8ca282 1478 uint8_t idx = 0;
bcostm 0:d83f1c8ca282 1479
bcostm 0:d83f1c8ca282 1480 /* Check for all the registered instances */
bcostm 0:d83f1c8ca282 1481 for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
bcostm 0:d83f1c8ca282 1482 {
bcostm 0:d83f1c8ca282 1483 if(mfxstm32l152[idx] == DeviceAddr)
bcostm 0:d83f1c8ca282 1484 {
bcostm 0:d83f1c8ca282 1485 mfxstm32l152[idx] = 0;
bcostm 0:d83f1c8ca282 1486 return idx;
bcostm 0:d83f1c8ca282 1487 }
bcostm 0:d83f1c8ca282 1488 }
bcostm 0:d83f1c8ca282 1489 return 0xFF;
bcostm 0:d83f1c8ca282 1490 }
bcostm 0:d83f1c8ca282 1491
bcostm 0:d83f1c8ca282 1492 /**
bcostm 0:d83f1c8ca282 1493 * @brief Internal routine
bcostm 0:d83f1c8ca282 1494 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1495 * @param RegisterAddr: Register Address
bcostm 0:d83f1c8ca282 1496 * @param PinPosition: Pin [0:23]
bcostm 0:d83f1c8ca282 1497 * @param PinValue: 0/1
bcostm 0:d83f1c8ca282 1498 * @retval None
bcostm 0:d83f1c8ca282 1499 */
bcostm 0:d83f1c8ca282 1500 void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue )
bcostm 0:d83f1c8ca282 1501 {
bcostm 0:d83f1c8ca282 1502 uint8_t tmp = 0;
bcostm 0:d83f1c8ca282 1503 uint8_t pin_0_7, pin_8_15, pin_16_23;
bcostm 0:d83f1c8ca282 1504
bcostm 0:d83f1c8ca282 1505 pin_0_7 = PinPosition & 0x0000ff;
bcostm 0:d83f1c8ca282 1506 pin_8_15 = PinPosition >> 8;
bcostm 0:d83f1c8ca282 1507 pin_8_15 = pin_8_15 & 0x00ff;
bcostm 0:d83f1c8ca282 1508 pin_16_23 = PinPosition >> 16;
bcostm 0:d83f1c8ca282 1509
bcostm 0:d83f1c8ca282 1510 if (pin_0_7)
bcostm 0:d83f1c8ca282 1511 {
bcostm 0:d83f1c8ca282 1512 /* Get the current register value */
bcostm 0:d83f1c8ca282 1513 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr);
bcostm 0:d83f1c8ca282 1514
bcostm 0:d83f1c8ca282 1515 /* Set the selected pin direction */
bcostm 0:d83f1c8ca282 1516 if (PinValue != 0)
bcostm 0:d83f1c8ca282 1517 {
bcostm 0:d83f1c8ca282 1518 tmp |= (uint8_t)pin_0_7;
bcostm 0:d83f1c8ca282 1519 }
bcostm 0:d83f1c8ca282 1520 else
bcostm 0:d83f1c8ca282 1521 {
bcostm 0:d83f1c8ca282 1522 tmp &= ~(uint8_t)pin_0_7;
bcostm 0:d83f1c8ca282 1523 }
bcostm 0:d83f1c8ca282 1524
bcostm 0:d83f1c8ca282 1525 /* Set the new register value */
bcostm 0:d83f1c8ca282 1526 MFX_IO_Write(DeviceAddr, RegisterAddr, tmp);
bcostm 0:d83f1c8ca282 1527 }
bcostm 0:d83f1c8ca282 1528
bcostm 0:d83f1c8ca282 1529 if (pin_8_15)
bcostm 0:d83f1c8ca282 1530 {
bcostm 0:d83f1c8ca282 1531 /* Get the current register value */
bcostm 0:d83f1c8ca282 1532 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+1);
bcostm 0:d83f1c8ca282 1533
bcostm 0:d83f1c8ca282 1534 /* Set the selected pin direction */
bcostm 0:d83f1c8ca282 1535 if (PinValue != 0)
bcostm 0:d83f1c8ca282 1536 {
bcostm 0:d83f1c8ca282 1537 tmp |= (uint8_t)pin_8_15;
bcostm 0:d83f1c8ca282 1538 }
bcostm 0:d83f1c8ca282 1539 else
bcostm 0:d83f1c8ca282 1540 {
bcostm 0:d83f1c8ca282 1541 tmp &= ~(uint8_t)pin_8_15;
bcostm 0:d83f1c8ca282 1542 }
bcostm 0:d83f1c8ca282 1543
bcostm 0:d83f1c8ca282 1544 /* Set the new register value */
bcostm 0:d83f1c8ca282 1545 MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp);
bcostm 0:d83f1c8ca282 1546 }
bcostm 0:d83f1c8ca282 1547
bcostm 0:d83f1c8ca282 1548 if (pin_16_23)
bcostm 0:d83f1c8ca282 1549 {
bcostm 0:d83f1c8ca282 1550 /* Get the current register value */
bcostm 0:d83f1c8ca282 1551 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+2);
bcostm 0:d83f1c8ca282 1552
bcostm 0:d83f1c8ca282 1553 /* Set the selected pin direction */
bcostm 0:d83f1c8ca282 1554 if (PinValue != 0)
bcostm 0:d83f1c8ca282 1555 {
bcostm 0:d83f1c8ca282 1556 tmp |= (uint8_t)pin_16_23;
bcostm 0:d83f1c8ca282 1557 }
bcostm 0:d83f1c8ca282 1558 else
bcostm 0:d83f1c8ca282 1559 {
bcostm 0:d83f1c8ca282 1560 tmp &= ~(uint8_t)pin_16_23;
bcostm 0:d83f1c8ca282 1561 }
bcostm 0:d83f1c8ca282 1562
bcostm 0:d83f1c8ca282 1563 /* Set the new register value */
bcostm 0:d83f1c8ca282 1564 MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp);
bcostm 0:d83f1c8ca282 1565 }
bcostm 0:d83f1c8ca282 1566 }
bcostm 0:d83f1c8ca282 1567
bcostm 0:d83f1c8ca282 1568
bcostm 0:d83f1c8ca282 1569 /**
bcostm 0:d83f1c8ca282 1570 * @}
bcostm 0:d83f1c8ca282 1571 */
bcostm 0:d83f1c8ca282 1572
bcostm 0:d83f1c8ca282 1573 /**
bcostm 0:d83f1c8ca282 1574 * @}
bcostm 0:d83f1c8ca282 1575 */
bcostm 0:d83f1c8ca282 1576
bcostm 0:d83f1c8ca282 1577 /**
bcostm 0:d83f1c8ca282 1578 * @}
bcostm 0:d83f1c8ca282 1579 */
bcostm 0:d83f1c8ca282 1580
bcostm 0:d83f1c8ca282 1581 /**
bcostm 0:d83f1c8ca282 1582 * @}
bcostm 0:d83f1c8ca282 1583 */
bcostm 0:d83f1c8ca282 1584 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/