ST / BSP_DISCO_L496AG

BSP driver for DISCO_L496AG

Dependents:   DISCO_L496AG-LCD-prova_1 DISCO_L496AG-LCD-prova_2 DISCO_L496AG-LCD-demo DISCO_L496AG-SRAM-demo

Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.c@2:106c7b82e064, 2019-11-20 (annotated)

Committer:
Jerome Coutant
Date:
Wed Nov 20 16:48:24 2019 +0100
Revision:
2:106c7b82e064
Parent:
0:d83f1c8ca282 
Update BSP files with CubeL4 V1.14.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jerome Coutant 2:106c7b82e064 1 /**
bcostm 0:d83f1c8ca282 2 ******************************************************************************
bcostm 0:d83f1c8ca282 3 * @file mfxstm32l152.c
bcostm 0:d83f1c8ca282 4 * @author MCD Application Team
bcostm 0:d83f1c8ca282 5 * @brief This file provides a set of functions needed to manage the MFXSTM32L152
bcostm 0:d83f1c8ca282 6 * IO Expander devices.
bcostm 0:d83f1c8ca282 7 ******************************************************************************
bcostm 0:d83f1c8ca282 8 * @attention
bcostm 0:d83f1c8ca282 9 *
Jerome Coutant 2:106c7b82e064 10 * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
Jerome Coutant 2:106c7b82e064 11 * All rights reserved.</center></h2>
bcostm 0:d83f1c8ca282 12 *
Jerome Coutant 2:106c7b82e064 13 * This software component is licensed by ST under BSD 3-Clause license,
Jerome Coutant 2:106c7b82e064 14 * the "License"; You may not use this file except in compliance with the
Jerome Coutant 2:106c7b82e064 15 * License. You may obtain a copy of the License at:
Jerome Coutant 2:106c7b82e064 16 * opensource.org/licenses/BSD-3-Clause
bcostm 0:d83f1c8ca282 17 *
bcostm 0:d83f1c8ca282 18 ******************************************************************************
Jerome Coutant 2:106c7b82e064 19 */
bcostm 0:d83f1c8ca282 20
bcostm 0:d83f1c8ca282 21 /* Includes ------------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 22 #include "mfxstm32l152.h"
bcostm 0:d83f1c8ca282 23
bcostm 0:d83f1c8ca282 24 /** @addtogroup BSP
bcostm 0:d83f1c8ca282 25 * @{
bcostm 0:d83f1c8ca282 26 */
bcostm 0:d83f1c8ca282 27
bcostm 0:d83f1c8ca282 28 /** @addtogroup Component
bcostm 0:d83f1c8ca282 29 * @{
Jerome Coutant 2:106c7b82e064 30 */
Jerome Coutant 2:106c7b82e064 31
bcostm 0:d83f1c8ca282 32 /** @defgroup MFXSTM32L152
bcostm 0:d83f1c8ca282 33 * @{
Jerome Coutant 2:106c7b82e064 34 */
Jerome Coutant 2:106c7b82e064 35
bcostm 0:d83f1c8ca282 36 /* Private typedef -----------------------------------------------------------*/
bcostm 0:d83f1c8ca282 37
bcostm 0:d83f1c8ca282 38 /** @defgroup MFXSTM32L152_Private_Types_Definitions
bcostm 0:d83f1c8ca282 39 * @{
Jerome Coutant 2:106c7b82e064 40 */
Jerome Coutant 2:106c7b82e064 41
bcostm 0:d83f1c8ca282 42 /* Private define ------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 43
bcostm 0:d83f1c8ca282 44 /** @defgroup MFXSTM32L152_Private_Defines
bcostm 0:d83f1c8ca282 45 * @{
Jerome Coutant 2:106c7b82e064 46 */
bcostm 0:d83f1c8ca282 47 #define MFXSTM32L152_MAX_INSTANCE 3
bcostm 0:d83f1c8ca282 48
bcostm 0:d83f1c8ca282 49 /* Private macro -------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 50
bcostm 0:d83f1c8ca282 51 /** @defgroup MFXSTM32L152_Private_Macros
bcostm 0:d83f1c8ca282 52 * @{
Jerome Coutant 2:106c7b82e064 53 */
Jerome Coutant 2:106c7b82e064 54
bcostm 0:d83f1c8ca282 55 /* Private variables ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 56
bcostm 0:d83f1c8ca282 57 /** @defgroup MFXSTM32L152_Private_Variables
bcostm 0:d83f1c8ca282 58 * @{
Jerome Coutant 2:106c7b82e064 59 */
bcostm 0:d83f1c8ca282 60
Jerome Coutant 2:106c7b82e064 61 /* Touch screen driver structure initialization */
Jerome Coutant 2:106c7b82e064 62 TS_DrvTypeDef mfxstm32l152_ts_drv =
bcostm 0:d83f1c8ca282 63 {
bcostm 0:d83f1c8ca282 64 mfxstm32l152_Init,
bcostm 0:d83f1c8ca282 65 mfxstm32l152_ReadID,
bcostm 0:d83f1c8ca282 66 mfxstm32l152_Reset,
Jerome Coutant 2:106c7b82e064 67
bcostm 0:d83f1c8ca282 68 mfxstm32l152_TS_Start,
bcostm 0:d83f1c8ca282 69 mfxstm32l152_TS_DetectTouch,
bcostm 0:d83f1c8ca282 70 mfxstm32l152_TS_GetXY,
Jerome Coutant 2:106c7b82e064 71
bcostm 0:d83f1c8ca282 72 mfxstm32l152_TS_EnableIT,
bcostm 0:d83f1c8ca282 73 mfxstm32l152_TS_ClearIT,
bcostm 0:d83f1c8ca282 74 mfxstm32l152_TS_ITStatus,
bcostm 0:d83f1c8ca282 75 mfxstm32l152_TS_DisableIT,
bcostm 0:d83f1c8ca282 76 };
bcostm 0:d83f1c8ca282 77
Jerome Coutant 2:106c7b82e064 78 /* IO driver structure initialization */
Jerome Coutant 2:106c7b82e064 79 IO_DrvTypeDef mfxstm32l152_io_drv =
bcostm 0:d83f1c8ca282 80 {
bcostm 0:d83f1c8ca282 81 mfxstm32l152_Init,
bcostm 0:d83f1c8ca282 82 mfxstm32l152_ReadID,
bcostm 0:d83f1c8ca282 83 mfxstm32l152_Reset,
Jerome Coutant 2:106c7b82e064 84
bcostm 0:d83f1c8ca282 85 mfxstm32l152_IO_Start,
bcostm 0:d83f1c8ca282 86 mfxstm32l152_IO_Config,
bcostm 0:d83f1c8ca282 87 mfxstm32l152_IO_WritePin,
bcostm 0:d83f1c8ca282 88 mfxstm32l152_IO_ReadPin,
Jerome Coutant 2:106c7b82e064 89
bcostm 0:d83f1c8ca282 90 mfxstm32l152_IO_EnableIT,
bcostm 0:d83f1c8ca282 91 mfxstm32l152_IO_DisableIT,
bcostm 0:d83f1c8ca282 92 mfxstm32l152_IO_ITStatus,
bcostm 0:d83f1c8ca282 93 mfxstm32l152_IO_ClearIT,
bcostm 0:d83f1c8ca282 94 };
bcostm 0:d83f1c8ca282 95
bcostm 0:d83f1c8ca282 96 /* IDD driver structure initialization */
bcostm 0:d83f1c8ca282 97 IDD_DrvTypeDef mfxstm32l152_idd_drv =
bcostm 0:d83f1c8ca282 98 {
bcostm 0:d83f1c8ca282 99 mfxstm32l152_Init,
bcostm 0:d83f1c8ca282 100 mfxstm32l152_DeInit,
bcostm 0:d83f1c8ca282 101 mfxstm32l152_ReadID,
bcostm 0:d83f1c8ca282 102 mfxstm32l152_Reset,
bcostm 0:d83f1c8ca282 103 mfxstm32l152_LowPower,
bcostm 0:d83f1c8ca282 104 mfxstm32l152_WakeUp,
bcostm 0:d83f1c8ca282 105
bcostm 0:d83f1c8ca282 106 mfxstm32l152_IDD_Start,
bcostm 0:d83f1c8ca282 107 mfxstm32l152_IDD_Config,
bcostm 0:d83f1c8ca282 108 mfxstm32l152_IDD_GetValue,
bcostm 0:d83f1c8ca282 109
bcostm 0:d83f1c8ca282 110 mfxstm32l152_IDD_EnableIT,
bcostm 0:d83f1c8ca282 111 mfxstm32l152_IDD_ClearIT,
bcostm 0:d83f1c8ca282 112 mfxstm32l152_IDD_GetITStatus,
bcostm 0:d83f1c8ca282 113 mfxstm32l152_IDD_DisableIT,
bcostm 0:d83f1c8ca282 114
bcostm 0:d83f1c8ca282 115 mfxstm32l152_Error_EnableIT,
bcostm 0:d83f1c8ca282 116 mfxstm32l152_Error_ClearIT,
bcostm 0:d83f1c8ca282 117 mfxstm32l152_Error_GetITStatus,
bcostm 0:d83f1c8ca282 118 mfxstm32l152_Error_DisableIT,
bcostm 0:d83f1c8ca282 119 mfxstm32l152_Error_ReadSrc,
bcostm 0:d83f1c8ca282 120 mfxstm32l152_Error_ReadMsg
bcostm 0:d83f1c8ca282 121 };
bcostm 0:d83f1c8ca282 122
bcostm 0:d83f1c8ca282 123
bcostm 0:d83f1c8ca282 124 /* mfxstm32l152 instances by address */
bcostm 0:d83f1c8ca282 125 uint8_t mfxstm32l152[MFXSTM32L152_MAX_INSTANCE] = {0};
bcostm 0:d83f1c8ca282 126 /**
bcostm 0:d83f1c8ca282 127 * @}
Jerome Coutant 2:106c7b82e064 128 */
Jerome Coutant 2:106c7b82e064 129
bcostm 0:d83f1c8ca282 130 /* Private function prototypes -----------------------------------------------*/
bcostm 0:d83f1c8ca282 131
bcostm 0:d83f1c8ca282 132 /** @defgroup MFXSTM32L152_Private_Function_Prototypes
bcostm 0:d83f1c8ca282 133 * @{
bcostm 0:d83f1c8ca282 134 */
Jerome Coutant 2:106c7b82e064 135 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 136 static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 137 static void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue );
bcostm 0:d83f1c8ca282 138
bcostm 0:d83f1c8ca282 139 /* Private functions ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 140
bcostm 0:d83f1c8ca282 141 /** @defgroup MFXSTM32L152_Private_Functions
bcostm 0:d83f1c8ca282 142 * @{
bcostm 0:d83f1c8ca282 143 */
bcostm 0:d83f1c8ca282 144
bcostm 0:d83f1c8ca282 145 /**
bcostm 0:d83f1c8ca282 146 * @brief Initialize the mfxstm32l152 and configure the needed hardware resources
bcostm 0:d83f1c8ca282 147 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 148 * @retval None
bcostm 0:d83f1c8ca282 149 */
bcostm 0:d83f1c8ca282 150 void mfxstm32l152_Init(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 151 {
bcostm 0:d83f1c8ca282 152 uint8_t instance;
bcostm 0:d83f1c8ca282 153 uint8_t empty;
Jerome Coutant 2:106c7b82e064 154
bcostm 0:d83f1c8ca282 155 /* Check if device instance already exists */
bcostm 0:d83f1c8ca282 156 instance = mfxstm32l152_GetInstance(DeviceAddr);
Jerome Coutant 2:106c7b82e064 157
bcostm 0:d83f1c8ca282 158 /* To prevent double initialization */
bcostm 0:d83f1c8ca282 159 if(instance == 0xFF)
bcostm 0:d83f1c8ca282 160 {
bcostm 0:d83f1c8ca282 161 /* Look for empty instance */
bcostm 0:d83f1c8ca282 162 empty = mfxstm32l152_GetInstance(0);
Jerome Coutant 2:106c7b82e064 163
bcostm 0:d83f1c8ca282 164 if(empty < MFXSTM32L152_MAX_INSTANCE)
bcostm 0:d83f1c8ca282 165 {
bcostm 0:d83f1c8ca282 166 /* Register the current device instance */
bcostm 0:d83f1c8ca282 167 mfxstm32l152[empty] = DeviceAddr;
Jerome Coutant 2:106c7b82e064 168
bcostm 0:d83f1c8ca282 169 /* Initialize IO BUS layer */
bcostm 0:d83f1c8ca282 170 MFX_IO_Init();
bcostm 0:d83f1c8ca282 171 }
bcostm 0:d83f1c8ca282 172 }
Jerome Coutant 2:106c7b82e064 173
bcostm 0:d83f1c8ca282 174 mfxstm32l152_SetIrqOutPinPolarity(DeviceAddr, MFXSTM32L152_OUT_PIN_POLARITY_HIGH);
bcostm 0:d83f1c8ca282 175 mfxstm32l152_SetIrqOutPinType(DeviceAddr, MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL);
bcostm 0:d83f1c8ca282 176 }
bcostm 0:d83f1c8ca282 177
bcostm 0:d83f1c8ca282 178 /**
bcostm 0:d83f1c8ca282 179 * @brief DeInitialize the mfxstm32l152 and unconfigure the needed hardware resources
bcostm 0:d83f1c8ca282 180 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 181 * @retval None
bcostm 0:d83f1c8ca282 182 */
bcostm 0:d83f1c8ca282 183 void mfxstm32l152_DeInit(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 184 {
bcostm 0:d83f1c8ca282 185 uint8_t instance;
Jerome Coutant 2:106c7b82e064 186
bcostm 0:d83f1c8ca282 187 /* release existing instance */
bcostm 0:d83f1c8ca282 188 instance = mfxstm32l152_ReleaseInstance(DeviceAddr);
Jerome Coutant 2:106c7b82e064 189
bcostm 0:d83f1c8ca282 190 /* De-Init only if instance was previously registered */
bcostm 0:d83f1c8ca282 191 if(instance != 0xFF)
bcostm 0:d83f1c8ca282 192 {
bcostm 0:d83f1c8ca282 193 /* De-Initialize IO BUS layer */
bcostm 0:d83f1c8ca282 194 MFX_IO_DeInit();
bcostm 0:d83f1c8ca282 195 }
bcostm 0:d83f1c8ca282 196 }
bcostm 0:d83f1c8ca282 197
bcostm 0:d83f1c8ca282 198 /**
bcostm 0:d83f1c8ca282 199 * @brief Reset the mfxstm32l152 by Software.
Jerome Coutant 2:106c7b82e064 200 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 201 * @retval None
bcostm 0:d83f1c8ca282 202 */
bcostm 0:d83f1c8ca282 203 void mfxstm32l152_Reset(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 204 {
Jerome Coutant 2:106c7b82e064 205 /* Soft Reset */
bcostm 0:d83f1c8ca282 206 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST);
bcostm 0:d83f1c8ca282 207
bcostm 0:d83f1c8ca282 208 /* Wait for a delay to ensure registers erasing */
bcostm 0:d83f1c8ca282 209 MFX_IO_Delay(10);
bcostm 0:d83f1c8ca282 210 }
bcostm 0:d83f1c8ca282 211
bcostm 0:d83f1c8ca282 212 /**
bcostm 0:d83f1c8ca282 213 * @brief Put mfxstm32l152 Device in Low Power standby mode
bcostm 0:d83f1c8ca282 214 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 215 * @retval None
bcostm 0:d83f1c8ca282 216 */
bcostm 0:d83f1c8ca282 217 void mfxstm32l152_LowPower(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 218 {
bcostm 0:d83f1c8ca282 219 /* Enter standby mode */
bcostm 0:d83f1c8ca282 220 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY);
bcostm 0:d83f1c8ca282 221
bcostm 0:d83f1c8ca282 222 /* enable wakeup pin */
bcostm 0:d83f1c8ca282 223 MFX_IO_EnableWakeupPin();
bcostm 0:d83f1c8ca282 224 }
bcostm 0:d83f1c8ca282 225
bcostm 0:d83f1c8ca282 226 /**
bcostm 0:d83f1c8ca282 227 * @brief WakeUp mfxstm32l152 from standby mode
bcostm 0:d83f1c8ca282 228 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 229 * @retval None
bcostm 0:d83f1c8ca282 230 */
bcostm 0:d83f1c8ca282 231 void mfxstm32l152_WakeUp(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 232 {
bcostm 0:d83f1c8ca282 233 uint8_t instance;
Jerome Coutant 2:106c7b82e064 234
bcostm 0:d83f1c8ca282 235 /* Check if device instance already exists */
bcostm 0:d83f1c8ca282 236 instance = mfxstm32l152_GetInstance(DeviceAddr);
Jerome Coutant 2:106c7b82e064 237
bcostm 0:d83f1c8ca282 238 /* if instance does not exist, first initialize pins*/
bcostm 0:d83f1c8ca282 239 if(instance == 0xFF)
bcostm 0:d83f1c8ca282 240 {
bcostm 0:d83f1c8ca282 241 /* enable wakeup pin */
bcostm 0:d83f1c8ca282 242 MFX_IO_EnableWakeupPin();
bcostm 0:d83f1c8ca282 243 }
bcostm 0:d83f1c8ca282 244
bcostm 0:d83f1c8ca282 245 /* toggle wakeup pin */
bcostm 0:d83f1c8ca282 246 MFX_IO_Wakeup();
bcostm 0:d83f1c8ca282 247 }
bcostm 0:d83f1c8ca282 248
bcostm 0:d83f1c8ca282 249 /**
bcostm 0:d83f1c8ca282 250 * @brief Read the MFXSTM32L152 IO Expander device ID.
Jerome Coutant 2:106c7b82e064 251 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 252 * @retval The Device ID (two bytes).
bcostm 0:d83f1c8ca282 253 */
bcostm 0:d83f1c8ca282 254 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 255 {
bcostm 0:d83f1c8ca282 256 uint8_t id;
Jerome Coutant 2:106c7b82e064 257
bcostm 0:d83f1c8ca282 258 /* Wait for a delay to ensure the state of registers */
bcostm 0:d83f1c8ca282 259 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 260
bcostm 0:d83f1c8ca282 261 /* Initialize IO BUS layer */
bcostm 0:d83f1c8ca282 262 MFX_IO_Init();
Jerome Coutant 2:106c7b82e064 263
bcostm 0:d83f1c8ca282 264 id = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_ID);
Jerome Coutant 2:106c7b82e064 265
bcostm 0:d83f1c8ca282 266 /* Return the device ID value */
bcostm 0:d83f1c8ca282 267 return (id);
bcostm 0:d83f1c8ca282 268 }
bcostm 0:d83f1c8ca282 269
bcostm 0:d83f1c8ca282 270 /**
bcostm 0:d83f1c8ca282 271 * @brief Read the MFXSTM32L152 device firmware version.
Jerome Coutant 2:106c7b82e064 272 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 273 * @retval The Device FW version (two bytes).
bcostm 0:d83f1c8ca282 274 */
bcostm 0:d83f1c8ca282 275 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 276 {
bcostm 0:d83f1c8ca282 277 uint8_t data[2];
bcostm 0:d83f1c8ca282 278
bcostm 0:d83f1c8ca282 279 MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_FW_VERSION_MSB, data, sizeof(data)) ;
bcostm 0:d83f1c8ca282 280
bcostm 0:d83f1c8ca282 281 /* Recompose MFX firmware value */
bcostm 0:d83f1c8ca282 282 return ((data[0] << 8) | data[1]);
bcostm 0:d83f1c8ca282 283 }
bcostm 0:d83f1c8ca282 284
bcostm 0:d83f1c8ca282 285 /**
bcostm 0:d83f1c8ca282 286 * @brief Enable the interrupt mode for the selected IT source
Jerome Coutant 2:106c7b82e064 287 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 288 * @param Source: The interrupt source to be configured, could be:
Jerome Coutant 2:106c7b82e064 289 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
Jerome Coutant 2:106c7b82e064 290 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
Jerome Coutant 2:106c7b82e064 291 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
Jerome Coutant 2:106c7b82e064 292 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
Jerome Coutant 2:106c7b82e064 293 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
Jerome Coutant 2:106c7b82e064 294 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
Jerome Coutant 2:106c7b82e064 295 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
Jerome Coutant 2:106c7b82e064 296 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
bcostm 0:d83f1c8ca282 297 * @retval None
Jerome Coutant 2:106c7b82e064 298 */
bcostm 0:d83f1c8ca282 299 void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source)
bcostm 0:d83f1c8ca282 300 {
bcostm 0:d83f1c8ca282 301 uint8_t tmp = 0;
Jerome Coutant 2:106c7b82e064 302
bcostm 0:d83f1c8ca282 303 /* Get the current value of the INT_EN register */
bcostm 0:d83f1c8ca282 304 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
bcostm 0:d83f1c8ca282 305
Jerome Coutant 2:106c7b82e064 306 /* Set the interrupts to be Enabled */
Jerome Coutant 2:106c7b82e064 307 tmp |= Source;
Jerome Coutant 2:106c7b82e064 308
bcostm 0:d83f1c8ca282 309 /* Set the register */
bcostm 0:d83f1c8ca282 310 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
bcostm 0:d83f1c8ca282 311 }
bcostm 0:d83f1c8ca282 312
bcostm 0:d83f1c8ca282 313 /**
bcostm 0:d83f1c8ca282 314 * @brief Disable the interrupt mode for the selected IT source
Jerome Coutant 2:106c7b82e064 315 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 316 * @param Source: The interrupt source to be configured, could be:
Jerome Coutant 2:106c7b82e064 317 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
Jerome Coutant 2:106c7b82e064 318 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
Jerome Coutant 2:106c7b82e064 319 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
Jerome Coutant 2:106c7b82e064 320 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
Jerome Coutant 2:106c7b82e064 321 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
Jerome Coutant 2:106c7b82e064 322 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
Jerome Coutant 2:106c7b82e064 323 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
Jerome Coutant 2:106c7b82e064 324 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
bcostm 0:d83f1c8ca282 325 * @retval None
bcostm 0:d83f1c8ca282 326 */
bcostm 0:d83f1c8ca282 327 void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source)
bcostm 0:d83f1c8ca282 328 {
bcostm 0:d83f1c8ca282 329 uint8_t tmp = 0;
Jerome Coutant 2:106c7b82e064 330
bcostm 0:d83f1c8ca282 331 /* Get the current value of the INT_EN register */
bcostm 0:d83f1c8ca282 332 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
bcostm 0:d83f1c8ca282 333
Jerome Coutant 2:106c7b82e064 334 /* Set the interrupts to be Enabled */
Jerome Coutant 2:106c7b82e064 335 tmp &= ~Source;
Jerome Coutant 2:106c7b82e064 336
bcostm 0:d83f1c8ca282 337 /* Set the register */
bcostm 0:d83f1c8ca282 338 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
bcostm 0:d83f1c8ca282 339 }
bcostm 0:d83f1c8ca282 340
bcostm 0:d83f1c8ca282 341
bcostm 0:d83f1c8ca282 342 /**
bcostm 0:d83f1c8ca282 343 * @brief Returns the selected Global interrupt source pending bit value
Jerome Coutant 2:106c7b82e064 344 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 345 * @param Source: the Global interrupt source to be checked, could be:
Jerome Coutant 2:106c7b82e064 346 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
Jerome Coutant 2:106c7b82e064 347 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
Jerome Coutant 2:106c7b82e064 348 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
Jerome Coutant 2:106c7b82e064 349 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
Jerome Coutant 2:106c7b82e064 350 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
Jerome Coutant 2:106c7b82e064 351 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
Jerome Coutant 2:106c7b82e064 352 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
Jerome Coutant 2:106c7b82e064 353 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
bcostm 0:d83f1c8ca282 354 * @retval The value of the checked Global interrupt source status.
bcostm 0:d83f1c8ca282 355 */
bcostm 0:d83f1c8ca282 356 uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source)
bcostm 0:d83f1c8ca282 357 {
bcostm 0:d83f1c8ca282 358 /* Return the global IT source status (pending or not)*/
bcostm 0:d83f1c8ca282 359 return((MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_PENDING) & Source));
bcostm 0:d83f1c8ca282 360 }
bcostm 0:d83f1c8ca282 361
bcostm 0:d83f1c8ca282 362 /**
bcostm 0:d83f1c8ca282 363 * @brief Clear the selected Global interrupt pending bit(s)
Jerome Coutant 2:106c7b82e064 364 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 365 * @param Source: the Global interrupt source to be cleared, could be any combination
Jerome Coutant 2:106c7b82e064 366 * of the below values. The acknowledge signal for MFXSTM32L152_GPIOs configured in input
Jerome Coutant 2:106c7b82e064 367 * with interrupt is not on this register but in IRQ_GPI_ACK1, IRQ_GPI_ACK2 registers.
Jerome Coutant 2:106c7b82e064 368 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
Jerome Coutant 2:106c7b82e064 369 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
Jerome Coutant 2:106c7b82e064 370 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
Jerome Coutant 2:106c7b82e064 371 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
Jerome Coutant 2:106c7b82e064 372 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
Jerome Coutant 2:106c7b82e064 373 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
Jerome Coutant 2:106c7b82e064 374 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
Jerome Coutant 2:106c7b82e064 375 * /\/\ IMPORTANT NOTE /\/\ must not use MFXSTM32L152_IRQ_GPIO as argument, see IRQ_GPI_ACK1 and IRQ_GPI_ACK2 registers
bcostm 0:d83f1c8ca282 376 * @retval None
bcostm 0:d83f1c8ca282 377 */
bcostm 0:d83f1c8ca282 378 void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source)
bcostm 0:d83f1c8ca282 379 {
bcostm 0:d83f1c8ca282 380 /* Write 1 to the bits that have to be cleared */
bcostm 0:d83f1c8ca282 381 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source);
bcostm 0:d83f1c8ca282 382 }
bcostm 0:d83f1c8ca282 383
bcostm 0:d83f1c8ca282 384 /**
bcostm 0:d83f1c8ca282 385 * @brief Set the global interrupt Polarity of IRQ_OUT_PIN.
Jerome Coutant 2:106c7b82e064 386 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 387 * @param Polarity: the IT mode polarity, could be one of the following values:
Jerome Coutant 2:106c7b82e064 388 * @arg MFXSTM32L152_OUT_PIN_POLARITY_LOW: Interrupt output line is active Low edge
Jerome Coutant 2:106c7b82e064 389 * @arg MFXSTM32L152_OUT_PIN_POLARITY_HIGH: Interrupt line output is active High edge
bcostm 0:d83f1c8ca282 390 * @retval None
bcostm 0:d83f1c8ca282 391 */
bcostm 0:d83f1c8ca282 392 void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity)
bcostm 0:d83f1c8ca282 393 {
bcostm 0:d83f1c8ca282 394 uint8_t tmp = 0;
Jerome Coutant 2:106c7b82e064 395
Jerome Coutant 2:106c7b82e064 396 /* Get the current register value */
bcostm 0:d83f1c8ca282 397 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
Jerome Coutant 2:106c7b82e064 398
bcostm 0:d83f1c8ca282 399 /* Mask the polarity bits */
bcostm 0:d83f1c8ca282 400 tmp &= ~(uint8_t)0x02;
Jerome Coutant 2:106c7b82e064 401
bcostm 0:d83f1c8ca282 402 /* Modify the Interrupt Output line configuration */
bcostm 0:d83f1c8ca282 403 tmp |= Polarity;
Jerome Coutant 2:106c7b82e064 404
bcostm 0:d83f1c8ca282 405 /* Set the new register value */
bcostm 0:d83f1c8ca282 406 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
bcostm 0:d83f1c8ca282 407
bcostm 0:d83f1c8ca282 408 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
bcostm 0:d83f1c8ca282 409 MFX_IO_Delay(1);
Jerome Coutant 2:106c7b82e064 410
bcostm 0:d83f1c8ca282 411 }
bcostm 0:d83f1c8ca282 412
bcostm 0:d83f1c8ca282 413 /**
Jerome Coutant 2:106c7b82e064 414 * @brief Set the global interrupt Type of IRQ_OUT_PIN.
Jerome Coutant 2:106c7b82e064 415 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 416 * @param Type: Interrupt line activity type, could be one of the following values:
Jerome Coutant 2:106c7b82e064 417 * @arg MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN: Open Drain output Interrupt line
Jerome Coutant 2:106c7b82e064 418 * @arg MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL: Push Pull output Interrupt line
bcostm 0:d83f1c8ca282 419 * @retval None
bcostm 0:d83f1c8ca282 420 */
bcostm 0:d83f1c8ca282 421 void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type)
bcostm 0:d83f1c8ca282 422 {
bcostm 0:d83f1c8ca282 423 uint8_t tmp = 0;
Jerome Coutant 2:106c7b82e064 424
Jerome Coutant 2:106c7b82e064 425 /* Get the current register value */
bcostm 0:d83f1c8ca282 426 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
Jerome Coutant 2:106c7b82e064 427
bcostm 0:d83f1c8ca282 428 /* Mask the type bits */
bcostm 0:d83f1c8ca282 429 tmp &= ~(uint8_t)0x01;
Jerome Coutant 2:106c7b82e064 430
bcostm 0:d83f1c8ca282 431 /* Modify the Interrupt Output line configuration */
bcostm 0:d83f1c8ca282 432 tmp |= Type;
Jerome Coutant 2:106c7b82e064 433
bcostm 0:d83f1c8ca282 434 /* Set the new register value */
bcostm 0:d83f1c8ca282 435 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
bcostm 0:d83f1c8ca282 436
bcostm 0:d83f1c8ca282 437 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
bcostm 0:d83f1c8ca282 438 MFX_IO_Delay(1);
Jerome Coutant 2:106c7b82e064 439
bcostm 0:d83f1c8ca282 440 }
bcostm 0:d83f1c8ca282 441
bcostm 0:d83f1c8ca282 442
bcostm 0:d83f1c8ca282 443 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 444 /* ----------------------- GPIO ------------------------------------- */
bcostm 0:d83f1c8ca282 445 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 446
bcostm 0:d83f1c8ca282 447
bcostm 0:d83f1c8ca282 448 /**
bcostm 0:d83f1c8ca282 449 * @brief Start the IO functionality used and enable the AF for selected IO pin(s).
Jerome Coutant 2:106c7b82e064 450 * @param DeviceAddr: Device address on communication Bus.
Jerome Coutant 2:106c7b82e064 451 * @param AF_en: 0 to disable, else enabled.
bcostm 0:d83f1c8ca282 452 * @retval None
bcostm 0:d83f1c8ca282 453 */
bcostm 0:d83f1c8ca282 454 void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 455 {
bcostm 0:d83f1c8ca282 456 uint8_t mode;
Jerome Coutant 2:106c7b82e064 457
bcostm 0:d83f1c8ca282 458 /* Get the current register value */
bcostm 0:d83f1c8ca282 459 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
Jerome Coutant 2:106c7b82e064 460
Jerome Coutant 2:106c7b82e064 461 /* Set the IO Functionalities to be Enabled */
Jerome Coutant 2:106c7b82e064 462 mode |= MFXSTM32L152_GPIO_EN;
Jerome Coutant 2:106c7b82e064 463
bcostm 0:d83f1c8ca282 464 /* Enable ALTERNATE functions */
Jerome Coutant 2:106c7b82e064 465 /* AGPIO[0..3] can be either IDD or GPIO */
Jerome Coutant 2:106c7b82e064 466 /* AGPIO[4..7] can be either TS or GPIO */
bcostm 0:d83f1c8ca282 467 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
Jerome Coutant 2:106c7b82e064 468 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
bcostm 0:d83f1c8ca282 469 /* so if IDD and TS are both active it is better to let ALTERNATE off (0) */
bcostm 0:d83f1c8ca282 470 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
bcostm 0:d83f1c8ca282 471 /* remind that AGPIO are less efficient then normal GPIO (They use pooling rather then EXTI */
bcostm 0:d83f1c8ca282 472 if (IO_Pin > 0xFFFF)
bcostm 0:d83f1c8ca282 473 {
Jerome Coutant 2:106c7b82e064 474 mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
bcostm 0:d83f1c8ca282 475 }
bcostm 0:d83f1c8ca282 476 else
bcostm 0:d83f1c8ca282 477 {
Jerome Coutant 2:106c7b82e064 478 mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
Jerome Coutant 2:106c7b82e064 479 }
bcostm 0:d83f1c8ca282 480
Jerome Coutant 2:106c7b82e064 481 /* Write the new register value */
bcostm 0:d83f1c8ca282 482 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
Jerome Coutant 2:106c7b82e064 483
bcostm 0:d83f1c8ca282 484 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
bcostm 0:d83f1c8ca282 485 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 486 }
bcostm 0:d83f1c8ca282 487
bcostm 0:d83f1c8ca282 488 /**
bcostm 0:d83f1c8ca282 489 * @brief Configures the IO pin(s) according to IO mode structure value.
Jerome Coutant 2:106c7b82e064 490 * @param DeviceAddr: Device address on communication Bus.
Jerome Coutant 2:106c7b82e064 491 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
Jerome Coutant 2:106c7b82e064 492 * of the following values:
bcostm 0:d83f1c8ca282 493 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 494 * @param IO_Mode: The IO pin mode to configure, could be one of the following values:
bcostm 0:d83f1c8ca282 495 * @arg IO_MODE_INPUT
bcostm 0:d83f1c8ca282 496 * @arg IO_MODE_OUTPUT
bcostm 0:d83f1c8ca282 497 * @arg IO_MODE_IT_RISING_EDGE
bcostm 0:d83f1c8ca282 498 * @arg IO_MODE_IT_FALLING_EDGE
bcostm 0:d83f1c8ca282 499 * @arg IO_MODE_IT_LOW_LEVEL
Jerome Coutant 2:106c7b82e064 500 * @arg IO_MODE_IT_HIGH_LEVEL
bcostm 0:d83f1c8ca282 501 * @arg IO_MODE_INPUT_PU,
bcostm 0:d83f1c8ca282 502 * @arg IO_MODE_INPUT_PD,
bcostm 0:d83f1c8ca282 503 * @arg IO_MODE_OUTPUT_OD_PU,
bcostm 0:d83f1c8ca282 504 * @arg IO_MODE_OUTPUT_OD_PD,
bcostm 0:d83f1c8ca282 505 * @arg IO_MODE_OUTPUT_PP_PU,
bcostm 0:d83f1c8ca282 506 * @arg IO_MODE_OUTPUT_PP_PD,
bcostm 0:d83f1c8ca282 507 * @arg IO_MODE_IT_RISING_EDGE_PU
bcostm 0:d83f1c8ca282 508 * @arg IO_MODE_IT_FALLING_EDGE_PU
bcostm 0:d83f1c8ca282 509 * @arg IO_MODE_IT_LOW_LEVEL_PU
bcostm 0:d83f1c8ca282 510 * @arg IO_MODE_IT_HIGH_LEVEL_PU
bcostm 0:d83f1c8ca282 511 * @arg IO_MODE_IT_RISING_EDGE_PD
bcostm 0:d83f1c8ca282 512 * @arg IO_MODE_IT_FALLING_EDGE_PD
bcostm 0:d83f1c8ca282 513 * @arg IO_MODE_IT_LOW_LEVEL_PD
bcostm 0:d83f1c8ca282 514 * @arg IO_MODE_IT_HIGH_LEVEL_PD
bcostm 0:d83f1c8ca282 515 * @retval None
bcostm 0:d83f1c8ca282 516 */
bcostm 0:d83f1c8ca282 517 uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode)
bcostm 0:d83f1c8ca282 518 {
bcostm 0:d83f1c8ca282 519 uint8_t error_code = 0;
bcostm 0:d83f1c8ca282 520
bcostm 0:d83f1c8ca282 521 /* Configure IO pin according to selected IO mode */
bcostm 0:d83f1c8ca282 522 switch(IO_Mode)
bcostm 0:d83f1c8ca282 523 {
bcostm 0:d83f1c8ca282 524 case IO_MODE_OFF: /* Off or analog mode */
bcostm 0:d83f1c8ca282 525 case IO_MODE_ANALOG: /* Off or analog mode */
bcostm 0:d83f1c8ca282 526 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 527 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 528 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 529 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 530 break;
bcostm 0:d83f1c8ca282 531
bcostm 0:d83f1c8ca282 532 case IO_MODE_INPUT: /* Input mode */
bcostm 0:d83f1c8ca282 533 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 534 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 535 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 536 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 537 break;
Jerome Coutant 2:106c7b82e064 538
bcostm 0:d83f1c8ca282 539 case IO_MODE_INPUT_PU: /* Input mode */
bcostm 0:d83f1c8ca282 540 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 541 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 542 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 543 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 544 break;
Jerome Coutant 2:106c7b82e064 545
bcostm 0:d83f1c8ca282 546 case IO_MODE_INPUT_PD: /* Input mode */
bcostm 0:d83f1c8ca282 547 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 548 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 549 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 550 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 551 break;
bcostm 0:d83f1c8ca282 552
bcostm 0:d83f1c8ca282 553 case IO_MODE_OUTPUT: /* Output mode */
bcostm 0:d83f1c8ca282 554 case IO_MODE_OUTPUT_PP_PD: /* Output mode */
bcostm 0:d83f1c8ca282 555 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 556 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
bcostm 0:d83f1c8ca282 557 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
bcostm 0:d83f1c8ca282 558 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 559 break;
bcostm 0:d83f1c8ca282 560
bcostm 0:d83f1c8ca282 561 case IO_MODE_OUTPUT_PP_PU: /* Output mode */
bcostm 0:d83f1c8ca282 562 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 563 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
bcostm 0:d83f1c8ca282 564 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
bcostm 0:d83f1c8ca282 565 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 566 break;
bcostm 0:d83f1c8ca282 567
bcostm 0:d83f1c8ca282 568 case IO_MODE_OUTPUT_OD_PD: /* Output mode */
bcostm 0:d83f1c8ca282 569 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 570 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
bcostm 0:d83f1c8ca282 571 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
bcostm 0:d83f1c8ca282 572 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 573 break;
bcostm 0:d83f1c8ca282 574
bcostm 0:d83f1c8ca282 575 case IO_MODE_OUTPUT_OD_PU: /* Output mode */
bcostm 0:d83f1c8ca282 576 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
bcostm 0:d83f1c8ca282 577 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
bcostm 0:d83f1c8ca282 578 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
bcostm 0:d83f1c8ca282 579 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 580 break;
bcostm 0:d83f1c8ca282 581
bcostm 0:d83f1c8ca282 582 case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */
bcostm 0:d83f1c8ca282 583 mfxstm32l152_IO_EnableIT(DeviceAddr);
Jerome Coutant 2:106c7b82e064 584 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 585 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 586 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 587 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 588 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 589 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 590 break;
bcostm 0:d83f1c8ca282 591
bcostm 0:d83f1c8ca282 592 case IO_MODE_IT_RISING_EDGE_PU: /* Interrupt rising edge mode */
bcostm 0:d83f1c8ca282 593 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 594 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 595 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 596 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 597 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 598 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 599 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 600 break;
bcostm 0:d83f1c8ca282 601
bcostm 0:d83f1c8ca282 602 case IO_MODE_IT_RISING_EDGE_PD: /* Interrupt rising edge mode */
bcostm 0:d83f1c8ca282 603 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 604 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 605 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 606 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
Jerome Coutant 2:106c7b82e064 607 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
Jerome Coutant 2:106c7b82e064 608 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 609 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 610 break;
bcostm 0:d83f1c8ca282 611
bcostm 0:d83f1c8ca282 612 case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */
bcostm 0:d83f1c8ca282 613 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 614 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 615 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 616 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 617 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 618 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 619 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 620 break;
bcostm 0:d83f1c8ca282 621
bcostm 0:d83f1c8ca282 622 case IO_MODE_IT_FALLING_EDGE_PU: /* Interrupt falling edge mode */
bcostm 0:d83f1c8ca282 623 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 624 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 625 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 626 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 627 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
bcostm 0:d83f1c8ca282 628 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 629 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 630 break;
bcostm 0:d83f1c8ca282 631
bcostm 0:d83f1c8ca282 632 case IO_MODE_IT_FALLING_EDGE_PD: /* Interrupt falling edge mode */
bcostm 0:d83f1c8ca282 633 mfxstm32l152_IO_EnableIT(DeviceAddr);
Jerome Coutant 2:106c7b82e064 634 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 635 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 636 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
Jerome Coutant 2:106c7b82e064 637 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
Jerome Coutant 2:106c7b82e064 638 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 639 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 640 break;
bcostm 0:d83f1c8ca282 641
bcostm 0:d83f1c8ca282 642 case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */
bcostm 0:d83f1c8ca282 643 mfxstm32l152_IO_EnableIT(DeviceAddr);
Jerome Coutant 2:106c7b82e064 644 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 645 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 646 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 647 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 648 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 649 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 650 break;
bcostm 0:d83f1c8ca282 651
bcostm 0:d83f1c8ca282 652 case IO_MODE_IT_LOW_LEVEL_PU: /* Low level interrupt mode */
bcostm 0:d83f1c8ca282 653 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 654 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 655 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 656 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 657 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 658 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 659 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 660 break;
bcostm 0:d83f1c8ca282 661
bcostm 0:d83f1c8ca282 662 case IO_MODE_IT_LOW_LEVEL_PD: /* Low level interrupt mode */
bcostm 0:d83f1c8ca282 663 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 664 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 665 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 666 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 667 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
Jerome Coutant 2:106c7b82e064 668 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
bcostm 0:d83f1c8ca282 669 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 670 break;
Jerome Coutant 2:106c7b82e064 671
bcostm 0:d83f1c8ca282 672 case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */
bcostm 0:d83f1c8ca282 673 mfxstm32l152_IO_EnableIT(DeviceAddr);
Jerome Coutant 2:106c7b82e064 674 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 675 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 676 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 677 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 678 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 679 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 680 break;
bcostm 0:d83f1c8ca282 681
bcostm 0:d83f1c8ca282 682 case IO_MODE_IT_HIGH_LEVEL_PU: /* High level interrupt mode */
bcostm 0:d83f1c8ca282 683 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 684 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 685 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 686 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
bcostm 0:d83f1c8ca282 687 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
bcostm 0:d83f1c8ca282 688 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 689 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
bcostm 0:d83f1c8ca282 690 break;
bcostm 0:d83f1c8ca282 691
bcostm 0:d83f1c8ca282 692 case IO_MODE_IT_HIGH_LEVEL_PD: /* High level interrupt mode */
bcostm 0:d83f1c8ca282 693 mfxstm32l152_IO_EnableIT(DeviceAddr);
bcostm 0:d83f1c8ca282 694 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
bcostm 0:d83f1c8ca282 695 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
bcostm 0:d83f1c8ca282 696 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
bcostm 0:d83f1c8ca282 697 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
Jerome Coutant 2:106c7b82e064 698 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
bcostm 0:d83f1c8ca282 699 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
Jerome Coutant 2:106c7b82e064 700 break;
Jerome Coutant 2:106c7b82e064 701
bcostm 0:d83f1c8ca282 702 default:
bcostm 0:d83f1c8ca282 703 error_code = (uint8_t) IO_Mode;
Jerome Coutant 2:106c7b82e064 704 break;
Jerome Coutant 2:106c7b82e064 705 }
bcostm 0:d83f1c8ca282 706
bcostm 0:d83f1c8ca282 707 return error_code;
bcostm 0:d83f1c8ca282 708 }
bcostm 0:d83f1c8ca282 709
bcostm 0:d83f1c8ca282 710 /**
bcostm 0:d83f1c8ca282 711 * @brief Initialize the selected IO pin direction.
bcostm 0:d83f1c8ca282 712 * @param DeviceAddr: Device address on communication Bus.
Jerome Coutant 2:106c7b82e064 713 * @param IO_Pin: The IO pin to be configured. This parameter could be any
bcostm 0:d83f1c8ca282 714 * combination of the following values:
Jerome Coutant 2:106c7b82e064 715 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
Jerome Coutant 2:106c7b82e064 716 * @param Direction: could be MFXSTM32L152_GPIO_DIR_IN or MFXSTM32L152_GPIO_DIR_OUT.
bcostm 0:d83f1c8ca282 717 * @retval None
bcostm 0:d83f1c8ca282 718 */
bcostm 0:d83f1c8ca282 719 void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction)
bcostm 0:d83f1c8ca282 720 {
bcostm 0:d83f1c8ca282 721 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_DIR1, IO_Pin, Direction);
bcostm 0:d83f1c8ca282 722 }
bcostm 0:d83f1c8ca282 723
bcostm 0:d83f1c8ca282 724 /**
Jerome Coutant 2:106c7b82e064 725 * @brief Set the global interrupt Type.
Jerome Coutant 2:106c7b82e064 726 * @param DeviceAddr: Device address on communication Bus.
Jerome Coutant 2:106c7b82e064 727 * @param IO_Pin: The IO pin to be configured. This parameter could be any
bcostm 0:d83f1c8ca282 728 * combination of the following values:
Jerome Coutant 2:106c7b82e064 729 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 730 * @param Evt: Interrupt line activity type, could be one of the following values:
Jerome Coutant 2:106c7b82e064 731 * @arg MFXSTM32L152_IRQ_GPI_EVT_LEVEL: Interrupt line is active in level model
Jerome Coutant 2:106c7b82e064 732 * @arg MFXSTM32L152_IRQ_GPI_EVT_EDGE: Interrupt line is active in edge model
bcostm 0:d83f1c8ca282 733 * @retval None
bcostm 0:d83f1c8ca282 734 */
bcostm 0:d83f1c8ca282 735 void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt)
bcostm 0:d83f1c8ca282 736 {
bcostm 0:d83f1c8ca282 737 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1, IO_Pin, Evt);
bcostm 0:d83f1c8ca282 738 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 739 }
bcostm 0:d83f1c8ca282 740
bcostm 0:d83f1c8ca282 741 /**
bcostm 0:d83f1c8ca282 742 * @brief Configure the Edge for which a transition is detectable for the
bcostm 0:d83f1c8ca282 743 * selected pin.
bcostm 0:d83f1c8ca282 744 * @param DeviceAddr: Device address on communication Bus.
Jerome Coutant 2:106c7b82e064 745 * @param IO_Pin: The IO pin to be configured. This parameter could be any
bcostm 0:d83f1c8ca282 746 * combination of the following values:
Jerome Coutant 2:106c7b82e064 747 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 748 * @param Evt: Interrupt line activity type, could be one of the following values:
Jerome Coutant 2:106c7b82e064 749 * @arg MFXSTM32L152_IRQ_GPI_TYPE_LLFE: Interrupt line is active in Low Level or Falling Edge
Jerome Coutant 2:106c7b82e064 750 * @arg MFXSTM32L152_IRQ_GPI_TYPE_HLRE: Interrupt line is active in High Level or Rising Edge
bcostm 0:d83f1c8ca282 751 * @retval None
bcostm 0:d83f1c8ca282 752 */
bcostm 0:d83f1c8ca282 753 void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type)
bcostm 0:d83f1c8ca282 754 {
bcostm 0:d83f1c8ca282 755 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1, IO_Pin, Type);
bcostm 0:d83f1c8ca282 756 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 757 }
bcostm 0:d83f1c8ca282 758
bcostm 0:d83f1c8ca282 759 /**
bcostm 0:d83f1c8ca282 760 * @brief When GPIO is in output mode, puts the corresponding GPO in High (1) or Low (0) level.
Jerome Coutant 2:106c7b82e064 761 * @param DeviceAddr: Device address on communication Bus.
Jerome Coutant 2:106c7b82e064 762 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
bcostm 0:d83f1c8ca282 763 * of the following values:
Jerome Coutant 2:106c7b82e064 764 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 765 * @param PinState: The new IO pin state.
bcostm 0:d83f1c8ca282 766 * @retval None
bcostm 0:d83f1c8ca282 767 */
bcostm 0:d83f1c8ca282 768 void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState)
bcostm 0:d83f1c8ca282 769 {
bcostm 0:d83f1c8ca282 770 /* Apply the bit value to the selected pin */
bcostm 0:d83f1c8ca282 771 if (PinState != 0)
bcostm 0:d83f1c8ca282 772 {
bcostm 0:d83f1c8ca282 773 /* Set the SET register */
bcostm 0:d83f1c8ca282 774 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_SET1, IO_Pin, 1);
bcostm 0:d83f1c8ca282 775 }
bcostm 0:d83f1c8ca282 776 else
bcostm 0:d83f1c8ca282 777 {
bcostm 0:d83f1c8ca282 778 /* Set the CLEAR register */
bcostm 0:d83f1c8ca282 779 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_CLR1, IO_Pin, 1);
Jerome Coutant 2:106c7b82e064 780 }
bcostm 0:d83f1c8ca282 781 }
bcostm 0:d83f1c8ca282 782
bcostm 0:d83f1c8ca282 783 /**
bcostm 0:d83f1c8ca282 784 * @brief Return the state of the selected IO pin(s).
Jerome Coutant 2:106c7b82e064 785 * @param DeviceAddr: Device address on communication Bus.
Jerome Coutant 2:106c7b82e064 786 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
bcostm 0:d83f1c8ca282 787 * of the following values:
Jerome Coutant 2:106c7b82e064 788 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 789 * @retval IO pin(s) state.
bcostm 0:d83f1c8ca282 790 */
bcostm 0:d83f1c8ca282 791 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 792 {
Jerome Coutant 2:106c7b82e064 793 uint32_t tmp1 = 0;
Jerome Coutant 2:106c7b82e064 794 uint32_t tmp2 = 0;
Jerome Coutant 2:106c7b82e064 795 uint32_t tmp3 = 0;
Jerome Coutant 2:106c7b82e064 796
Jerome Coutant 2:106c7b82e064 797 if(IO_Pin & 0x000000FF)
Jerome Coutant 2:106c7b82e064 798 {
Jerome Coutant 2:106c7b82e064 799 tmp1 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE1);
Jerome Coutant 2:106c7b82e064 800 }
Jerome Coutant 2:106c7b82e064 801 if(IO_Pin & 0x0000FF00)
Jerome Coutant 2:106c7b82e064 802 {
Jerome Coutant 2:106c7b82e064 803 tmp2 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE2);
Jerome Coutant 2:106c7b82e064 804 }
Jerome Coutant 2:106c7b82e064 805 if(IO_Pin & 0x00FF0000)
Jerome Coutant 2:106c7b82e064 806 {
Jerome Coutant 2:106c7b82e064 807 tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE3);
Jerome Coutant 2:106c7b82e064 808 }
Jerome Coutant 2:106c7b82e064 809
bcostm 0:d83f1c8ca282 810 tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
Jerome Coutant 2:106c7b82e064 811
bcostm 0:d83f1c8ca282 812 return(tmp3 & IO_Pin);
bcostm 0:d83f1c8ca282 813 }
bcostm 0:d83f1c8ca282 814
bcostm 0:d83f1c8ca282 815 /**
bcostm 0:d83f1c8ca282 816 * @brief Enable the global IO interrupt source.
Jerome Coutant 2:106c7b82e064 817 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 818 * @retval None
bcostm 0:d83f1c8ca282 819 */
bcostm 0:d83f1c8ca282 820 void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr)
Jerome Coutant 2:106c7b82e064 821 {
bcostm 0:d83f1c8ca282 822 MFX_IO_ITConfig();
Jerome Coutant 2:106c7b82e064 823
bcostm 0:d83f1c8ca282 824 /* Enable global IO IT source */
bcostm 0:d83f1c8ca282 825 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
bcostm 0:d83f1c8ca282 826 }
bcostm 0:d83f1c8ca282 827
bcostm 0:d83f1c8ca282 828 /**
bcostm 0:d83f1c8ca282 829 * @brief Disable the global IO interrupt source.
Jerome Coutant 2:106c7b82e064 830 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 831 * @retval None
bcostm 0:d83f1c8ca282 832 */
bcostm 0:d83f1c8ca282 833 void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 834 {
bcostm 0:d83f1c8ca282 835 /* Disable global IO IT source */
Jerome Coutant 2:106c7b82e064 836 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
bcostm 0:d83f1c8ca282 837 }
Jerome Coutant 2:106c7b82e064 838
bcostm 0:d83f1c8ca282 839 /**
bcostm 0:d83f1c8ca282 840 * @brief Enable interrupt mode for the selected IO pin(s).
bcostm 0:d83f1c8ca282 841 * @param DeviceAddr: Device address on communication Bus.
Jerome Coutant 2:106c7b82e064 842 * @param IO_Pin: The IO interrupt to be enabled. This parameter could be any
bcostm 0:d83f1c8ca282 843 * combination of the following values:
bcostm 0:d83f1c8ca282 844 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 845 * @retval None
bcostm 0:d83f1c8ca282 846 */
bcostm 0:d83f1c8ca282 847 void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 848 {
bcostm 0:d83f1c8ca282 849 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 1);
bcostm 0:d83f1c8ca282 850 }
bcostm 0:d83f1c8ca282 851
bcostm 0:d83f1c8ca282 852 /**
bcostm 0:d83f1c8ca282 853 * @brief Disable interrupt mode for the selected IO pin(s).
bcostm 0:d83f1c8ca282 854 * @param DeviceAddr: Device address on communication Bus.
Jerome Coutant 2:106c7b82e064 855 * @param IO_Pin: The IO interrupt to be disabled. This parameter could be any
bcostm 0:d83f1c8ca282 856 * combination of the following values:
bcostm 0:d83f1c8ca282 857 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 858 * @retval None
bcostm 0:d83f1c8ca282 859 */
bcostm 0:d83f1c8ca282 860 void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 861 {
bcostm 0:d83f1c8ca282 862 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 0);
bcostm 0:d83f1c8ca282 863 }
bcostm 0:d83f1c8ca282 864
bcostm 0:d83f1c8ca282 865
bcostm 0:d83f1c8ca282 866 /**
bcostm 0:d83f1c8ca282 867 * @brief Check the status of the selected IO interrupt pending bit
bcostm 0:d83f1c8ca282 868 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 869 * @param IO_Pin: The IO interrupt to be checked could be:
Jerome Coutant 2:106c7b82e064 870 * @arg MFXSTM32L152_GPIO_PIN_x Where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 871 * @retval Status of the checked IO pin(s).
bcostm 0:d83f1c8ca282 872 */
bcostm 0:d83f1c8ca282 873 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 874 {
bcostm 0:d83f1c8ca282 875 /* Get the Interrupt status */
Jerome Coutant 2:106c7b82e064 876 uint8_t tmp1 = 0;
Jerome Coutant 2:106c7b82e064 877 uint16_t tmp2 = 0;
Jerome Coutant 2:106c7b82e064 878 uint32_t tmp3 = 0;
bcostm 0:d83f1c8ca282 879
Jerome Coutant 2:106c7b82e064 880 if(IO_Pin & 0xFF)
Jerome Coutant 2:106c7b82e064 881 {
Jerome Coutant 2:106c7b82e064 882 tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1);
Jerome Coutant 2:106c7b82e064 883 }
Jerome Coutant 2:106c7b82e064 884 if(IO_Pin & 0xFFFF00)
Jerome Coutant 2:106c7b82e064 885 {
Jerome Coutant 2:106c7b82e064 886 tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2);
Jerome Coutant 2:106c7b82e064 887 }
Jerome Coutant 2:106c7b82e064 888 if(IO_Pin & 0xFFFF0000)
Jerome Coutant 2:106c7b82e064 889 {
Jerome Coutant 2:106c7b82e064 890 tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3);
Jerome Coutant 2:106c7b82e064 891 }
Jerome Coutant 2:106c7b82e064 892
bcostm 0:d83f1c8ca282 893 tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
Jerome Coutant 2:106c7b82e064 894
bcostm 0:d83f1c8ca282 895 return(tmp3 & IO_Pin);
bcostm 0:d83f1c8ca282 896 }
bcostm 0:d83f1c8ca282 897
bcostm 0:d83f1c8ca282 898 /**
bcostm 0:d83f1c8ca282 899 * @brief Clear the selected IO interrupt pending bit(s). It clear automatically also the general MFXSTM32L152_REG_ADR_IRQ_PENDING
bcostm 0:d83f1c8ca282 900 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 901 * @param IO_Pin: the IO interrupt to be cleared, could be:
Jerome Coutant 2:106c7b82e064 902 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
bcostm 0:d83f1c8ca282 903 * @retval None
bcostm 0:d83f1c8ca282 904 */
bcostm 0:d83f1c8ca282 905 void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin)
bcostm 0:d83f1c8ca282 906 {
bcostm 0:d83f1c8ca282 907 /* Clear the IO IT pending bit(s) by acknowledging */
bcostm 0:d83f1c8ca282 908 /* it cleans automatically also the Global IRQ_GPIO */
bcostm 0:d83f1c8ca282 909 /* normally this function is called under interrupt */
bcostm 0:d83f1c8ca282 910 uint8_t pin_0_7, pin_8_15, pin_16_23;
bcostm 0:d83f1c8ca282 911
bcostm 0:d83f1c8ca282 912 pin_0_7 = IO_Pin & 0x0000ff;
bcostm 0:d83f1c8ca282 913 pin_8_15 = IO_Pin >> 8;
bcostm 0:d83f1c8ca282 914 pin_8_15 = pin_8_15 & 0x00ff;
bcostm 0:d83f1c8ca282 915 pin_16_23 = IO_Pin >> 16;
bcostm 0:d83f1c8ca282 916
bcostm 0:d83f1c8ca282 917 if (pin_0_7)
bcostm 0:d83f1c8ca282 918 {
bcostm 0:d83f1c8ca282 919 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7);
bcostm 0:d83f1c8ca282 920 }
bcostm 0:d83f1c8ca282 921 if (pin_8_15)
bcostm 0:d83f1c8ca282 922 {
bcostm 0:d83f1c8ca282 923 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15);
bcostm 0:d83f1c8ca282 924 }
bcostm 0:d83f1c8ca282 925 if (pin_16_23)
bcostm 0:d83f1c8ca282 926 {
bcostm 0:d83f1c8ca282 927 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23);
bcostm 0:d83f1c8ca282 928 }
bcostm 0:d83f1c8ca282 929 }
bcostm 0:d83f1c8ca282 930
bcostm 0:d83f1c8ca282 931
bcostm 0:d83f1c8ca282 932 /**
bcostm 0:d83f1c8ca282 933 * @brief Enable the AF for aGPIO.
Jerome Coutant 2:106c7b82e064 934 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 935 * @retval None
bcostm 0:d83f1c8ca282 936 */
bcostm 0:d83f1c8ca282 937 void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 938 {
bcostm 0:d83f1c8ca282 939 uint8_t mode;
bcostm 0:d83f1c8ca282 940
bcostm 0:d83f1c8ca282 941 /* Get the current register value */
bcostm 0:d83f1c8ca282 942 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
Jerome Coutant 2:106c7b82e064 943
bcostm 0:d83f1c8ca282 944 /* Enable ALTERNATE functions */
Jerome Coutant 2:106c7b82e064 945 /* AGPIO[0..3] can be either IDD or GPIO */
Jerome Coutant 2:106c7b82e064 946 /* AGPIO[4..7] can be either TS or GPIO */
bcostm 0:d83f1c8ca282 947 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
Jerome Coutant 2:106c7b82e064 948 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
bcostm 0:d83f1c8ca282 949 /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
bcostm 0:d83f1c8ca282 950 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
bcostm 0:d83f1c8ca282 951 /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
Jerome Coutant 2:106c7b82e064 952 mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
Jerome Coutant 2:106c7b82e064 953
Jerome Coutant 2:106c7b82e064 954 /* Write the new register value */
bcostm 0:d83f1c8ca282 955 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
bcostm 0:d83f1c8ca282 956 }
bcostm 0:d83f1c8ca282 957
bcostm 0:d83f1c8ca282 958 /**
bcostm 0:d83f1c8ca282 959 * @brief Disable the AF for aGPIO.
Jerome Coutant 2:106c7b82e064 960 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 961 * @retval None
bcostm 0:d83f1c8ca282 962 */
bcostm 0:d83f1c8ca282 963 void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 964 {
bcostm 0:d83f1c8ca282 965 uint8_t mode;
bcostm 0:d83f1c8ca282 966
bcostm 0:d83f1c8ca282 967 /* Get the current register value */
bcostm 0:d83f1c8ca282 968 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
Jerome Coutant 2:106c7b82e064 969
bcostm 0:d83f1c8ca282 970 /* Enable ALTERNATE functions */
Jerome Coutant 2:106c7b82e064 971 /* AGPIO[0..3] can be either IDD or GPIO */
Jerome Coutant 2:106c7b82e064 972 /* AGPIO[4..7] can be either TS or GPIO */
bcostm 0:d83f1c8ca282 973 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
Jerome Coutant 2:106c7b82e064 974 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
bcostm 0:d83f1c8ca282 975 /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
bcostm 0:d83f1c8ca282 976 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
bcostm 0:d83f1c8ca282 977 /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
Jerome Coutant 2:106c7b82e064 978 mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
Jerome Coutant 2:106c7b82e064 979
Jerome Coutant 2:106c7b82e064 980 /* Write the new register value */
bcostm 0:d83f1c8ca282 981 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
Jerome Coutant 2:106c7b82e064 982
bcostm 0:d83f1c8ca282 983 }
bcostm 0:d83f1c8ca282 984
bcostm 0:d83f1c8ca282 985
bcostm 0:d83f1c8ca282 986 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 987 /* --------------------- TOUCH SCREEN ------------------------------- */
bcostm 0:d83f1c8ca282 988 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 989
bcostm 0:d83f1c8ca282 990 /**
bcostm 0:d83f1c8ca282 991 * @brief Configures the touch Screen Controller (Single point detection)
bcostm 0:d83f1c8ca282 992 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 993 * @retval None.
bcostm 0:d83f1c8ca282 994 */
bcostm 0:d83f1c8ca282 995 void mfxstm32l152_TS_Start(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 996 {
bcostm 0:d83f1c8ca282 997 uint8_t mode;
bcostm 0:d83f1c8ca282 998
bcostm 0:d83f1c8ca282 999 /* Get the current register value */
bcostm 0:d83f1c8ca282 1000 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
Jerome Coutant 2:106c7b82e064 1001
Jerome Coutant 2:106c7b82e064 1002 /* Set the Functionalities to be Enabled */
Jerome Coutant 2:106c7b82e064 1003 mode |= MFXSTM32L152_TS_EN;
Jerome Coutant 2:106c7b82e064 1004
Jerome Coutant 2:106c7b82e064 1005 /* Set the new register value */
bcostm 0:d83f1c8ca282 1006 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
Jerome Coutant 2:106c7b82e064 1007
bcostm 0:d83f1c8ca282 1008 /* Wait for 2 ms */
Jerome Coutant 2:106c7b82e064 1009 MFX_IO_Delay(2);
Jerome Coutant 2:106c7b82e064 1010
bcostm 0:d83f1c8ca282 1011 /* Select 2 nF filter capacitor */
Jerome Coutant 2:106c7b82e064 1012 /* Configuration:
bcostm 0:d83f1c8ca282 1013 - Touch average control : 4 samples
bcostm 0:d83f1c8ca282 1014 - Touch delay time : 500 uS
Jerome Coutant 2:106c7b82e064 1015 - Panel driver setting time: 500 uS
bcostm 0:d83f1c8ca282 1016 */
bcostm 0:d83f1c8ca282 1017 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32);
bcostm 0:d83f1c8ca282 1018 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5);
bcostm 0:d83f1c8ca282 1019 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04);
Jerome Coutant 2:106c7b82e064 1020
bcostm 0:d83f1c8ca282 1021 /* Configure the Touch FIFO threshold: single point reading */
bcostm 0:d83f1c8ca282 1022 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01);
Jerome Coutant 2:106c7b82e064 1023
bcostm 0:d83f1c8ca282 1024 /* Clear the FIFO memory content. */
bcostm 0:d83f1c8ca282 1025 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
bcostm 0:d83f1c8ca282 1026
bcostm 0:d83f1c8ca282 1027 /* Touch screen control configuration :
bcostm 0:d83f1c8ca282 1028 - No window tracking index
bcostm 0:d83f1c8ca282 1029 */
bcostm 0:d83f1c8ca282 1030 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00);
Jerome Coutant 2:106c7b82e064 1031
Jerome Coutant 2:106c7b82e064 1032
bcostm 0:d83f1c8ca282 1033 /* Clear all the IT status pending bits if any */
bcostm 0:d83f1c8ca282 1034 mfxstm32l152_IO_ClearIT(DeviceAddr, 0xFFFFFF);
bcostm 0:d83f1c8ca282 1035
bcostm 0:d83f1c8ca282 1036 /* Wait for 1 ms delay */
bcostm 0:d83f1c8ca282 1037 MFX_IO_Delay(1);
bcostm 0:d83f1c8ca282 1038 }
bcostm 0:d83f1c8ca282 1039
bcostm 0:d83f1c8ca282 1040 /**
bcostm 0:d83f1c8ca282 1041 * @brief Return if there is touch detected or not.
bcostm 0:d83f1c8ca282 1042 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1043 * @retval Touch detected state.
bcostm 0:d83f1c8ca282 1044 */
bcostm 0:d83f1c8ca282 1045 uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1046 {
bcostm 0:d83f1c8ca282 1047 uint8_t state;
bcostm 0:d83f1c8ca282 1048 uint8_t ret = 0;
Jerome Coutant 2:106c7b82e064 1049
bcostm 0:d83f1c8ca282 1050 state = MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_STA);
bcostm 0:d83f1c8ca282 1051 state = ((state & (uint8_t)MFXSTM32L152_TS_CTRL_STATUS) == (uint8_t)MFXSTM32L152_TS_CTRL_STATUS);
Jerome Coutant 2:106c7b82e064 1052
bcostm 0:d83f1c8ca282 1053 if(state > 0)
bcostm 0:d83f1c8ca282 1054 {
bcostm 0:d83f1c8ca282 1055 if(MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_LEVEL) > 0)
bcostm 0:d83f1c8ca282 1056 {
bcostm 0:d83f1c8ca282 1057 ret = 1;
bcostm 0:d83f1c8ca282 1058 }
bcostm 0:d83f1c8ca282 1059 }
Jerome Coutant 2:106c7b82e064 1060
bcostm 0:d83f1c8ca282 1061 return ret;
bcostm 0:d83f1c8ca282 1062 }
bcostm 0:d83f1c8ca282 1063
bcostm 0:d83f1c8ca282 1064 /**
bcostm 0:d83f1c8ca282 1065 * @brief Get the touch screen X and Y positions values
bcostm 0:d83f1c8ca282 1066 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1067 * @param X: Pointer to X position value
Jerome Coutant 2:106c7b82e064 1068 * @param Y: Pointer to Y position value
bcostm 0:d83f1c8ca282 1069 * @retval None.
bcostm 0:d83f1c8ca282 1070 */
bcostm 0:d83f1c8ca282 1071 void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
bcostm 0:d83f1c8ca282 1072 {
bcostm 0:d83f1c8ca282 1073 uint8_t data_xy[3];
bcostm 0:d83f1c8ca282 1074
bcostm 0:d83f1c8ca282 1075 MFX_IO_ReadMultiple(DeviceAddr, MFXSTM32L152_TS_XY_DATA, data_xy, sizeof(data_xy)) ;
Jerome Coutant 2:106c7b82e064 1076
bcostm 0:d83f1c8ca282 1077 /* Calculate positions values */
Jerome Coutant 2:106c7b82e064 1078 *X = (data_xy[1]<<4) + (data_xy[0]>>4);
Jerome Coutant 2:106c7b82e064 1079 *Y = (data_xy[2]<<4) + (data_xy[0]&4);
bcostm 0:d83f1c8ca282 1080
bcostm 0:d83f1c8ca282 1081 /* Reset the FIFO memory content. */
bcostm 0:d83f1c8ca282 1082 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
bcostm 0:d83f1c8ca282 1083 }
bcostm 0:d83f1c8ca282 1084
bcostm 0:d83f1c8ca282 1085 /**
bcostm 0:d83f1c8ca282 1086 * @brief Configure the selected source to generate a global interrupt or not
Jerome Coutant 2:106c7b82e064 1087 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1088 * @retval None
bcostm 0:d83f1c8ca282 1089 */
bcostm 0:d83f1c8ca282 1090 void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1091 {
bcostm 0:d83f1c8ca282 1092 MFX_IO_ITConfig();
Jerome Coutant 2:106c7b82e064 1093
bcostm 0:d83f1c8ca282 1094 /* Enable global TS IT source */
bcostm 0:d83f1c8ca282 1095 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
bcostm 0:d83f1c8ca282 1096 }
bcostm 0:d83f1c8ca282 1097
bcostm 0:d83f1c8ca282 1098 /**
bcostm 0:d83f1c8ca282 1099 * @brief Configure the selected source to generate a global interrupt or not
Jerome Coutant 2:106c7b82e064 1100 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1101 * @retval None
bcostm 0:d83f1c8ca282 1102 */
bcostm 0:d83f1c8ca282 1103 void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1104 {
bcostm 0:d83f1c8ca282 1105 /* Disable global TS IT source */
Jerome Coutant 2:106c7b82e064 1106 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
bcostm 0:d83f1c8ca282 1107 }
bcostm 0:d83f1c8ca282 1108
bcostm 0:d83f1c8ca282 1109 /**
bcostm 0:d83f1c8ca282 1110 * @brief Configure the selected source to generate a global interrupt or not
Jerome Coutant 2:106c7b82e064 1111 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1112 * @retval TS interrupts status
bcostm 0:d83f1c8ca282 1113 */
bcostm 0:d83f1c8ca282 1114 uint8_t mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1115 {
bcostm 0:d83f1c8ca282 1116 /* Return TS interrupts status */
bcostm 0:d83f1c8ca282 1117 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_TS));
bcostm 0:d83f1c8ca282 1118 }
bcostm 0:d83f1c8ca282 1119
bcostm 0:d83f1c8ca282 1120 /**
bcostm 0:d83f1c8ca282 1121 * @brief Configure the selected source to generate a global interrupt or not
Jerome Coutant 2:106c7b82e064 1122 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1123 * @retval None
bcostm 0:d83f1c8ca282 1124 */
bcostm 0:d83f1c8ca282 1125 void mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1126 {
bcostm 0:d83f1c8ca282 1127 /* Clear the global TS IT source */
bcostm 0:d83f1c8ca282 1128 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_TS);
bcostm 0:d83f1c8ca282 1129 }
bcostm 0:d83f1c8ca282 1130
bcostm 0:d83f1c8ca282 1131 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1132 /* --------------------- IDD MEASUREMENT ---------------------------- */
bcostm 0:d83f1c8ca282 1133 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1134
bcostm 0:d83f1c8ca282 1135 /**
bcostm 0:d83f1c8ca282 1136 * @brief Launch IDD current measurement
bcostm 0:d83f1c8ca282 1137 * @param DeviceAddr: Device address on communication Bus
bcostm 0:d83f1c8ca282 1138 * @retval None.
bcostm 0:d83f1c8ca282 1139 */
bcostm 0:d83f1c8ca282 1140 void mfxstm32l152_IDD_Start(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1141 {
bcostm 0:d83f1c8ca282 1142 uint8_t mode = 0;
bcostm 0:d83f1c8ca282 1143
bcostm 0:d83f1c8ca282 1144 /* Get the current register value */
bcostm 0:d83f1c8ca282 1145 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
bcostm 0:d83f1c8ca282 1146
bcostm 0:d83f1c8ca282 1147 /* Set the Functionalities to be enabled */
bcostm 0:d83f1c8ca282 1148 mode |= MFXSTM32L152_IDD_CTRL_REQ;
bcostm 0:d83f1c8ca282 1149
bcostm 0:d83f1c8ca282 1150 /* Start measurement campaign */
bcostm 0:d83f1c8ca282 1151 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
bcostm 0:d83f1c8ca282 1152 }
bcostm 0:d83f1c8ca282 1153
bcostm 0:d83f1c8ca282 1154 /**
bcostm 0:d83f1c8ca282 1155 * @brief Configures the IDD current measurement
bcostm 0:d83f1c8ca282 1156 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1157 * @param MfxIddConfig: Parameters depending on hardware config.
bcostm 0:d83f1c8ca282 1158 * @retval None
bcostm 0:d83f1c8ca282 1159 */
bcostm 0:d83f1c8ca282 1160 void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig)
bcostm 0:d83f1c8ca282 1161 {
bcostm 0:d83f1c8ca282 1162 uint8_t value = 0;
bcostm 0:d83f1c8ca282 1163 uint8_t mode = 0;
bcostm 0:d83f1c8ca282 1164
bcostm 0:d83f1c8ca282 1165 /* Get the current register value */
bcostm 0:d83f1c8ca282 1166 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
bcostm 0:d83f1c8ca282 1167
bcostm 0:d83f1c8ca282 1168 if((mode & MFXSTM32L152_IDD_EN) != MFXSTM32L152_IDD_EN)
bcostm 0:d83f1c8ca282 1169 {
bcostm 0:d83f1c8ca282 1170 /* Set the Functionalities to be enabled */
bcostm 0:d83f1c8ca282 1171 mode |= MFXSTM32L152_IDD_EN;
bcostm 0:d83f1c8ca282 1172
bcostm 0:d83f1c8ca282 1173 /* Set the new register value */
bcostm 0:d83f1c8ca282 1174 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
bcostm 0:d83f1c8ca282 1175 }
bcostm 0:d83f1c8ca282 1176
bcostm 0:d83f1c8ca282 1177 /* Control register setting: number of shunts */
bcostm 0:d83f1c8ca282 1178 value = ((MfxIddConfig.ShuntNbUsed << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
bcostm 0:d83f1c8ca282 1179 value |= (MfxIddConfig.VrefMeasurement & MFXSTM32L152_IDD_CTRL_VREF_DIS);
bcostm 0:d83f1c8ca282 1180 value |= (MfxIddConfig.Calibration & MFXSTM32L152_IDD_CTRL_CAL_DIS);
bcostm 0:d83f1c8ca282 1181 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value);
bcostm 0:d83f1c8ca282 1182
bcostm 0:d83f1c8ca282 1183 /* Idd pre delay configuration: unit and value*/
bcostm 0:d83f1c8ca282 1184 value = (MfxIddConfig.PreDelayUnit & MFXSTM32L152_IDD_PREDELAY_UNIT) |
bcostm 0:d83f1c8ca282 1185 (MfxIddConfig.PreDelayValue & MFXSTM32L152_IDD_PREDELAY_VALUE);
bcostm 0:d83f1c8ca282 1186 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value);
bcostm 0:d83f1c8ca282 1187
bcostm 0:d83f1c8ca282 1188 /* Shunt 0 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1189 value = (uint8_t) (MfxIddConfig.Shunt0Value >> 8);
bcostm 0:d83f1c8ca282 1190 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value);
bcostm 0:d83f1c8ca282 1191 value = (uint8_t) (MfxIddConfig.Shunt0Value);
bcostm 0:d83f1c8ca282 1192 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value);
bcostm 0:d83f1c8ca282 1193
bcostm 0:d83f1c8ca282 1194 /* Shunt 1 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1195 value = (uint8_t) (MfxIddConfig.Shunt1Value >> 8);
bcostm 0:d83f1c8ca282 1196 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value);
bcostm 0:d83f1c8ca282 1197 value = (uint8_t) (MfxIddConfig.Shunt1Value);
bcostm 0:d83f1c8ca282 1198 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value);
bcostm 0:d83f1c8ca282 1199
bcostm 0:d83f1c8ca282 1200 /* Shunt 2 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1201 value = (uint8_t) (MfxIddConfig.Shunt2Value >> 8);
bcostm 0:d83f1c8ca282 1202 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value);
bcostm 0:d83f1c8ca282 1203 value = (uint8_t) (MfxIddConfig.Shunt2Value);
bcostm 0:d83f1c8ca282 1204 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value);
bcostm 0:d83f1c8ca282 1205
bcostm 0:d83f1c8ca282 1206 /* Shunt 3 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1207 value = (uint8_t) (MfxIddConfig.Shunt3Value >> 8);
bcostm 0:d83f1c8ca282 1208 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value);
bcostm 0:d83f1c8ca282 1209 value = (uint8_t) (MfxIddConfig.Shunt3Value);
bcostm 0:d83f1c8ca282 1210 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value);
bcostm 0:d83f1c8ca282 1211
bcostm 0:d83f1c8ca282 1212 /* Shunt 4 register value: MSB then LSB */
bcostm 0:d83f1c8ca282 1213 value = (uint8_t) (MfxIddConfig.Shunt4Value >> 8);
bcostm 0:d83f1c8ca282 1214 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value);
bcostm 0:d83f1c8ca282 1215 value = (uint8_t) (MfxIddConfig.Shunt4Value);
bcostm 0:d83f1c8ca282 1216 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value);
bcostm 0:d83f1c8ca282 1217
bcostm 0:d83f1c8ca282 1218 /* Shunt 0 stabilization delay */
bcostm 0:d83f1c8ca282 1219 value = MfxIddConfig.Shunt0StabDelay;
bcostm 0:d83f1c8ca282 1220 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1221
bcostm 0:d83f1c8ca282 1222 /* Shunt 1 stabilization delay */
bcostm 0:d83f1c8ca282 1223 value = MfxIddConfig.Shunt1StabDelay;
bcostm 0:d83f1c8ca282 1224 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1225
bcostm 0:d83f1c8ca282 1226 /* Shunt 2 stabilization delay */
bcostm 0:d83f1c8ca282 1227 value = MfxIddConfig.Shunt2StabDelay;
bcostm 0:d83f1c8ca282 1228 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1229
bcostm 0:d83f1c8ca282 1230 /* Shunt 3 stabilization delay */
bcostm 0:d83f1c8ca282 1231 value = MfxIddConfig.Shunt3StabDelay;
bcostm 0:d83f1c8ca282 1232 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1233
bcostm 0:d83f1c8ca282 1234 /* Shunt 4 stabilization delay */
bcostm 0:d83f1c8ca282 1235 value = MfxIddConfig.Shunt4StabDelay;
bcostm 0:d83f1c8ca282 1236 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value);
bcostm 0:d83f1c8ca282 1237
bcostm 0:d83f1c8ca282 1238 /* Idd ampli gain value: MSB then LSB */
bcostm 0:d83f1c8ca282 1239 value = (uint8_t) (MfxIddConfig.AmpliGain >> 8);
bcostm 0:d83f1c8ca282 1240 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value);
bcostm 0:d83f1c8ca282 1241 value = (uint8_t) (MfxIddConfig.AmpliGain);
bcostm 0:d83f1c8ca282 1242 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value);
bcostm 0:d83f1c8ca282 1243
bcostm 0:d83f1c8ca282 1244 /* Idd VDD min value: MSB then LSB */
bcostm 0:d83f1c8ca282 1245 value = (uint8_t) (MfxIddConfig.VddMin >> 8);
bcostm 0:d83f1c8ca282 1246 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value);
bcostm 0:d83f1c8ca282 1247 value = (uint8_t) (MfxIddConfig.VddMin);
bcostm 0:d83f1c8ca282 1248 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value);
bcostm 0:d83f1c8ca282 1249
bcostm 0:d83f1c8ca282 1250 /* Idd number of measurements */
bcostm 0:d83f1c8ca282 1251 value = MfxIddConfig.MeasureNb;
bcostm 0:d83f1c8ca282 1252 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value);
bcostm 0:d83f1c8ca282 1253
bcostm 0:d83f1c8ca282 1254 /* Idd delta delay configuration: unit and value */
bcostm 0:d83f1c8ca282 1255 value = (MfxIddConfig.DeltaDelayUnit & MFXSTM32L152_IDD_DELTADELAY_UNIT) |
bcostm 0:d83f1c8ca282 1256 (MfxIddConfig.DeltaDelayValue & MFXSTM32L152_IDD_DELTADELAY_VALUE);
bcostm 0:d83f1c8ca282 1257 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value);
bcostm 0:d83f1c8ca282 1258
bcostm 0:d83f1c8ca282 1259 /* Idd number of shut on board */
bcostm 0:d83f1c8ca282 1260 value = MfxIddConfig.ShuntNbOnBoard;
bcostm 0:d83f1c8ca282 1261 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value);
bcostm 0:d83f1c8ca282 1262 }
bcostm 0:d83f1c8ca282 1263
bcostm 0:d83f1c8ca282 1264 /**
bcostm 0:d83f1c8ca282 1265 * @brief This function allows to modify number of shunt used for a measurement
bcostm 0:d83f1c8ca282 1266 * @param DeviceAddr: Device address on communication Bus
bcostm 0:d83f1c8ca282 1267 * @retval None.
bcostm 0:d83f1c8ca282 1268 */
bcostm 0:d83f1c8ca282 1269 void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit)
bcostm 0:d83f1c8ca282 1270 {
bcostm 0:d83f1c8ca282 1271 uint8_t mode = 0;
bcostm 0:d83f1c8ca282 1272
bcostm 0:d83f1c8ca282 1273 /* Get the current register value */
bcostm 0:d83f1c8ca282 1274 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
bcostm 0:d83f1c8ca282 1275
bcostm 0:d83f1c8ca282 1276 /* Clear number of shunt limit */
bcostm 0:d83f1c8ca282 1277 mode &= ~(MFXSTM32L152_IDD_CTRL_SHUNT_NB);
bcostm 0:d83f1c8ca282 1278
bcostm 0:d83f1c8ca282 1279 /* Clear number of shunt limit */
bcostm 0:d83f1c8ca282 1280 mode |= ((ShuntNbLimit << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
bcostm 0:d83f1c8ca282 1281
bcostm 0:d83f1c8ca282 1282 /* Write noewx desired limit */
bcostm 0:d83f1c8ca282 1283 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
bcostm 0:d83f1c8ca282 1284 }
bcostm 0:d83f1c8ca282 1285
bcostm 0:d83f1c8ca282 1286 /**
bcostm 0:d83f1c8ca282 1287 * @brief Get Idd current value
bcostm 0:d83f1c8ca282 1288 * @param DeviceAddr: Device address on communication Bus
bcostm 0:d83f1c8ca282 1289 * @param ReadValue: Pointer on value to be read
bcostm 0:d83f1c8ca282 1290 * @retval Idd value in 10 nA.
bcostm 0:d83f1c8ca282 1291 */
bcostm 0:d83f1c8ca282 1292 void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue)
bcostm 0:d83f1c8ca282 1293 {
bcostm 0:d83f1c8ca282 1294 uint8_t data[3];
bcostm 0:d83f1c8ca282 1295
bcostm 0:d83f1c8ca282 1296 MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VALUE_MSB, data, sizeof(data)) ;
bcostm 0:d83f1c8ca282 1297
bcostm 0:d83f1c8ca282 1298 /* Recompose Idd current value */
bcostm 0:d83f1c8ca282 1299 *ReadValue = (data[0] << 16) | (data[1] << 8) | data[2];
bcostm 0:d83f1c8ca282 1300
bcostm 0:d83f1c8ca282 1301 }
bcostm 0:d83f1c8ca282 1302
bcostm 0:d83f1c8ca282 1303 /**
bcostm 0:d83f1c8ca282 1304 * @brief Get Last shunt used for measurement
bcostm 0:d83f1c8ca282 1305 * @param DeviceAddr: Device address on communication Bus
Jerome Coutant 2:106c7b82e064 1306 * @retval Last shunt used
bcostm 0:d83f1c8ca282 1307 */
bcostm 0:d83f1c8ca282 1308 uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1309 {
bcostm 0:d83f1c8ca282 1310 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT_USED));
bcostm 0:d83f1c8ca282 1311 }
bcostm 0:d83f1c8ca282 1312
bcostm 0:d83f1c8ca282 1313 /**
bcostm 0:d83f1c8ca282 1314 * @brief Configure mfx to enable Idd interrupt
bcostm 0:d83f1c8ca282 1315 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1316 * @retval None
bcostm 0:d83f1c8ca282 1317 */
bcostm 0:d83f1c8ca282 1318 void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1319 {
bcostm 0:d83f1c8ca282 1320 MFX_IO_ITConfig();
bcostm 0:d83f1c8ca282 1321
bcostm 0:d83f1c8ca282 1322 /* Enable global IDD interrupt source */
bcostm 0:d83f1c8ca282 1323 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
bcostm 0:d83f1c8ca282 1324 }
bcostm 0:d83f1c8ca282 1325
bcostm 0:d83f1c8ca282 1326 /**
bcostm 0:d83f1c8ca282 1327 * @brief Clear Idd global interrupt
bcostm 0:d83f1c8ca282 1328 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1329 * @retval None
bcostm 0:d83f1c8ca282 1330 */
bcostm 0:d83f1c8ca282 1331 void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1332 {
bcostm 0:d83f1c8ca282 1333 /* Clear the global IDD interrupt source */
bcostm 0:d83f1c8ca282 1334 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_IDD);
bcostm 0:d83f1c8ca282 1335 }
bcostm 0:d83f1c8ca282 1336
bcostm 0:d83f1c8ca282 1337 /**
bcostm 0:d83f1c8ca282 1338 * @brief get Idd interrupt status
bcostm 0:d83f1c8ca282 1339 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1340 * @retval IDD interrupts status
bcostm 0:d83f1c8ca282 1341 */
bcostm 0:d83f1c8ca282 1342 uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1343 {
bcostm 0:d83f1c8ca282 1344 /* Return IDD interrupt status */
bcostm 0:d83f1c8ca282 1345 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_IDD));
bcostm 0:d83f1c8ca282 1346 }
bcostm 0:d83f1c8ca282 1347
bcostm 0:d83f1c8ca282 1348 /**
bcostm 0:d83f1c8ca282 1349 * @brief disable Idd interrupt
bcostm 0:d83f1c8ca282 1350 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1351 * @retval None.
bcostm 0:d83f1c8ca282 1352 */
bcostm 0:d83f1c8ca282 1353 void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1354 {
bcostm 0:d83f1c8ca282 1355 /* Disable global IDD interrupt source */
bcostm 0:d83f1c8ca282 1356 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
bcostm 0:d83f1c8ca282 1357 }
bcostm 0:d83f1c8ca282 1358
bcostm 0:d83f1c8ca282 1359
bcostm 0:d83f1c8ca282 1360 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1361 /* --------------------- ERROR MANAGEMENT --------------------------- */
bcostm 0:d83f1c8ca282 1362 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1363
bcostm 0:d83f1c8ca282 1364 /**
bcostm 0:d83f1c8ca282 1365 * @brief Read Error Source.
bcostm 0:d83f1c8ca282 1366 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1367 * @retval Error message code with error source
bcostm 0:d83f1c8ca282 1368 */
bcostm 0:d83f1c8ca282 1369 uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1370 {
bcostm 0:d83f1c8ca282 1371 /* Get the current source register value */
bcostm 0:d83f1c8ca282 1372 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_SRC));
bcostm 0:d83f1c8ca282 1373 }
bcostm 0:d83f1c8ca282 1374
bcostm 0:d83f1c8ca282 1375 /**
bcostm 0:d83f1c8ca282 1376 * @brief Read Error Message
bcostm 0:d83f1c8ca282 1377 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1378 * @retval Error message code with error source
bcostm 0:d83f1c8ca282 1379 */
bcostm 0:d83f1c8ca282 1380 uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1381 {
bcostm 0:d83f1c8ca282 1382 /* Get the current message register value */
bcostm 0:d83f1c8ca282 1383 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_MSG));
bcostm 0:d83f1c8ca282 1384 }
bcostm 0:d83f1c8ca282 1385
bcostm 0:d83f1c8ca282 1386 /**
bcostm 0:d83f1c8ca282 1387 * @brief Enable Error global interrupt
bcostm 0:d83f1c8ca282 1388 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1389 * @retval None
bcostm 0:d83f1c8ca282 1390 */
bcostm 0:d83f1c8ca282 1391
bcostm 0:d83f1c8ca282 1392 void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1393 {
bcostm 0:d83f1c8ca282 1394 MFX_IO_ITConfig();
bcostm 0:d83f1c8ca282 1395
bcostm 0:d83f1c8ca282 1396 /* Enable global Error interrupt source */
bcostm 0:d83f1c8ca282 1397 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
bcostm 0:d83f1c8ca282 1398 }
bcostm 0:d83f1c8ca282 1399
bcostm 0:d83f1c8ca282 1400 /**
bcostm 0:d83f1c8ca282 1401 * @brief Clear Error global interrupt
bcostm 0:d83f1c8ca282 1402 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1403 * @retval None
bcostm 0:d83f1c8ca282 1404 */
bcostm 0:d83f1c8ca282 1405 void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1406 {
bcostm 0:d83f1c8ca282 1407 /* Clear the global Error interrupt source */
bcostm 0:d83f1c8ca282 1408 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
bcostm 0:d83f1c8ca282 1409 }
bcostm 0:d83f1c8ca282 1410
bcostm 0:d83f1c8ca282 1411 /**
bcostm 0:d83f1c8ca282 1412 * @brief get Error interrupt status
bcostm 0:d83f1c8ca282 1413 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1414 * @retval Error interrupts status
bcostm 0:d83f1c8ca282 1415 */
bcostm 0:d83f1c8ca282 1416 uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1417 {
bcostm 0:d83f1c8ca282 1418 /* Return Error interrupt status */
bcostm 0:d83f1c8ca282 1419 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_ERROR));
bcostm 0:d83f1c8ca282 1420 }
bcostm 0:d83f1c8ca282 1421
bcostm 0:d83f1c8ca282 1422 /**
bcostm 0:d83f1c8ca282 1423 * @brief disable Error interrupt
bcostm 0:d83f1c8ca282 1424 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1425 * @retval None.
bcostm 0:d83f1c8ca282 1426 */
bcostm 0:d83f1c8ca282 1427 void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1428 {
bcostm 0:d83f1c8ca282 1429 /* Disable global Error interrupt source */
bcostm 0:d83f1c8ca282 1430 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
bcostm 0:d83f1c8ca282 1431 }
bcostm 0:d83f1c8ca282 1432
bcostm 0:d83f1c8ca282 1433 /**
bcostm 0:d83f1c8ca282 1434 * @brief FOR DEBUG ONLY
bcostm 0:d83f1c8ca282 1435 */
bcostm 0:d83f1c8ca282 1436 uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr)
bcostm 0:d83f1c8ca282 1437 {
Jerome Coutant 2:106c7b82e064 1438 /* Get the current register value */
bcostm 0:d83f1c8ca282 1439 return(MFX_IO_Read((uint8_t) DeviceAddr, RegAddr));
bcostm 0:d83f1c8ca282 1440 }
bcostm 0:d83f1c8ca282 1441
bcostm 0:d83f1c8ca282 1442 void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value)
bcostm 0:d83f1c8ca282 1443 {
Jerome Coutant 2:106c7b82e064 1444 /* set the current register value */
bcostm 0:d83f1c8ca282 1445 MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value);
bcostm 0:d83f1c8ca282 1446 }
bcostm 0:d83f1c8ca282 1447
bcostm 0:d83f1c8ca282 1448 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1449 /* ----------------------- Private functions ------------------------ */
bcostm 0:d83f1c8ca282 1450 /* ------------------------------------------------------------------ */
bcostm 0:d83f1c8ca282 1451 /**
bcostm 0:d83f1c8ca282 1452 * @brief Check if the device instance of the selected address is already registered
Jerome Coutant 2:106c7b82e064 1453 * and return its index
bcostm 0:d83f1c8ca282 1454 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1455 * @retval Index of the device instance if registered, 0xFF if not.
bcostm 0:d83f1c8ca282 1456 */
bcostm 0:d83f1c8ca282 1457 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1458 {
bcostm 0:d83f1c8ca282 1459 uint8_t idx = 0;
Jerome Coutant 2:106c7b82e064 1460
bcostm 0:d83f1c8ca282 1461 /* Check all the registered instances */
bcostm 0:d83f1c8ca282 1462 for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
bcostm 0:d83f1c8ca282 1463 {
bcostm 0:d83f1c8ca282 1464 if(mfxstm32l152[idx] == DeviceAddr)
bcostm 0:d83f1c8ca282 1465 {
Jerome Coutant 2:106c7b82e064 1466 return idx;
bcostm 0:d83f1c8ca282 1467 }
bcostm 0:d83f1c8ca282 1468 }
Jerome Coutant 2:106c7b82e064 1469
bcostm 0:d83f1c8ca282 1470 return 0xFF;
bcostm 0:d83f1c8ca282 1471 }
bcostm 0:d83f1c8ca282 1472
bcostm 0:d83f1c8ca282 1473 /**
bcostm 0:d83f1c8ca282 1474 * @brief Release registered device instance
bcostm 0:d83f1c8ca282 1475 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1476 * @retval Index of released device instance, 0xFF if not.
bcostm 0:d83f1c8ca282 1477 */
bcostm 0:d83f1c8ca282 1478 static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr)
bcostm 0:d83f1c8ca282 1479 {
bcostm 0:d83f1c8ca282 1480 uint8_t idx = 0;
Jerome Coutant 2:106c7b82e064 1481
bcostm 0:d83f1c8ca282 1482 /* Check for all the registered instances */
bcostm 0:d83f1c8ca282 1483 for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
bcostm 0:d83f1c8ca282 1484 {
bcostm 0:d83f1c8ca282 1485 if(mfxstm32l152[idx] == DeviceAddr)
bcostm 0:d83f1c8ca282 1486 {
bcostm 0:d83f1c8ca282 1487 mfxstm32l152[idx] = 0;
bcostm 0:d83f1c8ca282 1488 return idx;
bcostm 0:d83f1c8ca282 1489 }
bcostm 0:d83f1c8ca282 1490 }
bcostm 0:d83f1c8ca282 1491 return 0xFF;
bcostm 0:d83f1c8ca282 1492 }
bcostm 0:d83f1c8ca282 1493
bcostm 0:d83f1c8ca282 1494 /**
bcostm 0:d83f1c8ca282 1495 * @brief Internal routine
Jerome Coutant 2:106c7b82e064 1496 * @param DeviceAddr: Device address on communication Bus.
bcostm 0:d83f1c8ca282 1497 * @param RegisterAddr: Register Address
bcostm 0:d83f1c8ca282 1498 * @param PinPosition: Pin [0:23]
bcostm 0:d83f1c8ca282 1499 * @param PinValue: 0/1
bcostm 0:d83f1c8ca282 1500 * @retval None
bcostm 0:d83f1c8ca282 1501 */
bcostm 0:d83f1c8ca282 1502 void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue )
bcostm 0:d83f1c8ca282 1503 {
bcostm 0:d83f1c8ca282 1504 uint8_t tmp = 0;
bcostm 0:d83f1c8ca282 1505 uint8_t pin_0_7, pin_8_15, pin_16_23;
bcostm 0:d83f1c8ca282 1506
bcostm 0:d83f1c8ca282 1507 pin_0_7 = PinPosition & 0x0000ff;
bcostm 0:d83f1c8ca282 1508 pin_8_15 = PinPosition >> 8;
bcostm 0:d83f1c8ca282 1509 pin_8_15 = pin_8_15 & 0x00ff;
bcostm 0:d83f1c8ca282 1510 pin_16_23 = PinPosition >> 16;
Jerome Coutant 2:106c7b82e064 1511
bcostm 0:d83f1c8ca282 1512 if (pin_0_7)
Jerome Coutant 2:106c7b82e064 1513 {
Jerome Coutant 2:106c7b82e064 1514 /* Get the current register value */
bcostm 0:d83f1c8ca282 1515 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr);
Jerome Coutant 2:106c7b82e064 1516
bcostm 0:d83f1c8ca282 1517 /* Set the selected pin direction */
bcostm 0:d83f1c8ca282 1518 if (PinValue != 0)
bcostm 0:d83f1c8ca282 1519 {
bcostm 0:d83f1c8ca282 1520 tmp |= (uint8_t)pin_0_7;
Jerome Coutant 2:106c7b82e064 1521 }
Jerome Coutant 2:106c7b82e064 1522 else
bcostm 0:d83f1c8ca282 1523 {
bcostm 0:d83f1c8ca282 1524 tmp &= ~(uint8_t)pin_0_7;
bcostm 0:d83f1c8ca282 1525 }
Jerome Coutant 2:106c7b82e064 1526
bcostm 0:d83f1c8ca282 1527 /* Set the new register value */
bcostm 0:d83f1c8ca282 1528 MFX_IO_Write(DeviceAddr, RegisterAddr, tmp);
bcostm 0:d83f1c8ca282 1529 }
bcostm 0:d83f1c8ca282 1530
bcostm 0:d83f1c8ca282 1531 if (pin_8_15)
bcostm 0:d83f1c8ca282 1532 {
Jerome Coutant 2:106c7b82e064 1533 /* Get the current register value */
bcostm 0:d83f1c8ca282 1534 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+1);
Jerome Coutant 2:106c7b82e064 1535
bcostm 0:d83f1c8ca282 1536 /* Set the selected pin direction */
bcostm 0:d83f1c8ca282 1537 if (PinValue != 0)
bcostm 0:d83f1c8ca282 1538 {
bcostm 0:d83f1c8ca282 1539 tmp |= (uint8_t)pin_8_15;
Jerome Coutant 2:106c7b82e064 1540 }
Jerome Coutant 2:106c7b82e064 1541 else
bcostm 0:d83f1c8ca282 1542 {
bcostm 0:d83f1c8ca282 1543 tmp &= ~(uint8_t)pin_8_15;
bcostm 0:d83f1c8ca282 1544 }
Jerome Coutant 2:106c7b82e064 1545
bcostm 0:d83f1c8ca282 1546 /* Set the new register value */
bcostm 0:d83f1c8ca282 1547 MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp);
Jerome Coutant 2:106c7b82e064 1548 }
bcostm 0:d83f1c8ca282 1549
bcostm 0:d83f1c8ca282 1550 if (pin_16_23)
bcostm 0:d83f1c8ca282 1551 {
Jerome Coutant 2:106c7b82e064 1552 /* Get the current register value */
bcostm 0:d83f1c8ca282 1553 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+2);
Jerome Coutant 2:106c7b82e064 1554
bcostm 0:d83f1c8ca282 1555 /* Set the selected pin direction */
bcostm 0:d83f1c8ca282 1556 if (PinValue != 0)
bcostm 0:d83f1c8ca282 1557 {
bcostm 0:d83f1c8ca282 1558 tmp |= (uint8_t)pin_16_23;
Jerome Coutant 2:106c7b82e064 1559 }
Jerome Coutant 2:106c7b82e064 1560 else
bcostm 0:d83f1c8ca282 1561 {
bcostm 0:d83f1c8ca282 1562 tmp &= ~(uint8_t)pin_16_23;
bcostm 0:d83f1c8ca282 1563 }
Jerome Coutant 2:106c7b82e064 1564
bcostm 0:d83f1c8ca282 1565 /* Set the new register value */
bcostm 0:d83f1c8ca282 1566 MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp);
Jerome Coutant 2:106c7b82e064 1567 }
bcostm 0:d83f1c8ca282 1568 }
bcostm 0:d83f1c8ca282 1569
bcostm 0:d83f1c8ca282 1570
bcostm 0:d83f1c8ca282 1571 /**
bcostm 0:d83f1c8ca282 1572 * @}
Jerome Coutant 2:106c7b82e064 1573 */
bcostm 0:d83f1c8ca282 1574
bcostm 0:d83f1c8ca282 1575 /**
bcostm 0:d83f1c8ca282 1576 * @}
Jerome Coutant 2:106c7b82e064 1577 */
bcostm 0:d83f1c8ca282 1578
bcostm 0:d83f1c8ca282 1579 /**
bcostm 0:d83f1c8ca282 1580 * @}
Jerome Coutant 2:106c7b82e064 1581 */
bcostm 0:d83f1c8ca282 1582
bcostm 0:d83f1c8ca282 1583 /**
bcostm 0:d83f1c8ca282 1584 * @}
Jerome Coutant 2:106c7b82e064 1585 */
bcostm 0:d83f1c8ca282 1586 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/