Contains the BSP driver for the B-L475E-IOT01 board.
Dependents: mbed-os-example-ble-Thermometer DISCO_L475VG_IOT01-Telegram-BOT DISCO_L475VG_IOT01-sche_cheveux DISCO_L475VG_IOT01-QSPI_FLASH_FILE_SYSTEM ... more
https://os.mbed.com/platforms/ST-Discovery-L475E-IOT01A/
Drivers/BSP/B-L475E-IOT01/stm32l475e_iot01_qspi.c@7:bfe8272ced90, 2019-09-24 (annotated)
- Committer:
- jeromecoutant
- Date:
- Tue Sep 24 15:30:09 2019 +0200
- Revision:
- 7:bfe8272ced90
- Parent:
- 6:9dfa42666f03
Update BSP files with STM32Cube L4 V1.14.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bcostm | 3:c6b5944187d5 | 1 | /** |
bcostm | 3:c6b5944187d5 | 2 | ****************************************************************************** |
bcostm | 3:c6b5944187d5 | 3 | * @file stm32l475e_iot01_qspi.c |
bcostm | 3:c6b5944187d5 | 4 | * @author MCD Application Team |
bcostm | 3:c6b5944187d5 | 5 | * @brief This file includes a standard driver for the MX25R6435F QSPI |
bcostm | 3:c6b5944187d5 | 6 | * memory mounted on STM32L475E IOT01 board. |
bcostm | 3:c6b5944187d5 | 7 | @verbatim |
bcostm | 3:c6b5944187d5 | 8 | ============================================================================== |
bcostm | 3:c6b5944187d5 | 9 | ##### How to use this driver ##### |
bcostm | 3:c6b5944187d5 | 10 | ============================================================================== |
bcostm | 3:c6b5944187d5 | 11 | [..] |
bcostm | 3:c6b5944187d5 | 12 | (#) This driver is used to drive the MX25R6435F QSPI external |
bcostm | 3:c6b5944187d5 | 13 | memory mounted on STM32L475E IOT01 board. |
bcostm | 3:c6b5944187d5 | 14 | |
bcostm | 3:c6b5944187d5 | 15 | (#) This driver need a specific component driver (MX25R6435F) to be included with. |
bcostm | 3:c6b5944187d5 | 16 | |
bcostm | 3:c6b5944187d5 | 17 | (#) Initialization steps: |
bcostm | 3:c6b5944187d5 | 18 | (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This |
bcostm | 3:c6b5944187d5 | 19 | function includes the MSP layer hardware resources initialization and the |
bcostm | 3:c6b5944187d5 | 20 | QSPI interface with the external memory. The BSP_QSPI_DeInit() can be used |
bcostm | 3:c6b5944187d5 | 21 | to deactivate the QSPI interface. |
bcostm | 3:c6b5944187d5 | 22 | |
bcostm | 3:c6b5944187d5 | 23 | (#) QSPI memory operations |
bcostm | 3:c6b5944187d5 | 24 | (++) QSPI memory can be accessed with read/write operations once it is |
bcostm | 3:c6b5944187d5 | 25 | initialized. |
bcostm | 3:c6b5944187d5 | 26 | Read/write operation can be performed with AHB access using the functions |
bcostm | 3:c6b5944187d5 | 27 | BSP_QSPI_Read()/BSP_QSPI_Write(). |
bcostm | 3:c6b5944187d5 | 28 | (++) The function to the QSPI memory in memory-mapped mode is possible after |
bcostm | 3:c6b5944187d5 | 29 | the call of the function BSP_QSPI_EnableMemoryMappedMode(). |
bcostm | 3:c6b5944187d5 | 30 | (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 31 | (see the QSPI memory data sheet) |
bcostm | 3:c6b5944187d5 | 32 | (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by |
bcostm | 3:c6b5944187d5 | 33 | specifying the block address. You can perform an erase operation of the whole |
bcostm | 3:c6b5944187d5 | 34 | chip by calling the function BSP_QSPI_Erase_Chip(). |
bcostm | 3:c6b5944187d5 | 35 | (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 36 | (see the QSPI memory data sheet) |
bcostm | 3:c6b5944187d5 | 37 | (++) Perform erase sector operation using the function BSP_QSPI_Erase_Sector() |
bcostm | 3:c6b5944187d5 | 38 | which is not blocking. So the function BSP_QSPI_GetStatus() should be used |
bcostm | 3:c6b5944187d5 | 39 | to check if the memory is busy, and the functions BSP_QSPI_SuspendErase()/ |
bcostm | 3:c6b5944187d5 | 40 | BSP_QSPI_ResumeErase() can be used to perform other operations during the |
bcostm | 3:c6b5944187d5 | 41 | sector erase. |
bcostm | 3:c6b5944187d5 | 42 | (++) Deep power down of the QSPI memory is managed with the call of the functions |
bcostm | 3:c6b5944187d5 | 43 | BSP_QSPI_EnterDeepPowerDown()/BSP_QSPI_LeaveDeepPowerDown() |
bcostm | 3:c6b5944187d5 | 44 | @endverbatim |
bcostm | 3:c6b5944187d5 | 45 | ****************************************************************************** |
bcostm | 3:c6b5944187d5 | 46 | * @attention |
bcostm | 3:c6b5944187d5 | 47 | * |
jeromecoutant | 7:bfe8272ced90 | 48 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
jeromecoutant | 7:bfe8272ced90 | 49 | * All rights reserved.</center></h2> |
bcostm | 3:c6b5944187d5 | 50 | * |
jeromecoutant | 7:bfe8272ced90 | 51 | * This software component is licensed by ST under BSD 3-Clause license, |
jeromecoutant | 7:bfe8272ced90 | 52 | * the "License"; You may not use this file except in compliance with the |
jeromecoutant | 7:bfe8272ced90 | 53 | * License. You may obtain a copy of the License at: |
jeromecoutant | 7:bfe8272ced90 | 54 | * opensource.org/licenses/BSD-3-Clause |
bcostm | 3:c6b5944187d5 | 55 | * |
bcostm | 3:c6b5944187d5 | 56 | ****************************************************************************** |
bcostm | 3:c6b5944187d5 | 57 | */ |
bcostm | 3:c6b5944187d5 | 58 | |
bcostm | 3:c6b5944187d5 | 59 | /* Includes ------------------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 60 | #include "stm32l475e_iot01_qspi.h" |
bcostm | 3:c6b5944187d5 | 61 | |
bcostm | 3:c6b5944187d5 | 62 | /** @addtogroup BSP |
bcostm | 3:c6b5944187d5 | 63 | * @{ |
bcostm | 3:c6b5944187d5 | 64 | */ |
bcostm | 3:c6b5944187d5 | 65 | |
bcostm | 3:c6b5944187d5 | 66 | /** @addtogroup STM32L475E_IOT01 |
bcostm | 3:c6b5944187d5 | 67 | * @{ |
bcostm | 3:c6b5944187d5 | 68 | */ |
bcostm | 3:c6b5944187d5 | 69 | |
bcostm | 3:c6b5944187d5 | 70 | /** @defgroup STM32L475E_IOT01_QSPI QSPI |
bcostm | 3:c6b5944187d5 | 71 | * @{ |
bcostm | 3:c6b5944187d5 | 72 | */ |
bcostm | 3:c6b5944187d5 | 73 | |
bcostm | 3:c6b5944187d5 | 74 | /* Private constants --------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 75 | /** @defgroup STM32L475E_IOT01_QSPI_Private_Constants QSPI Private Constants |
bcostm | 3:c6b5944187d5 | 76 | * @{ |
bcostm | 3:c6b5944187d5 | 77 | */ |
bcostm | 3:c6b5944187d5 | 78 | #define QSPI_QUAD_DISABLE 0x0 |
bcostm | 3:c6b5944187d5 | 79 | #define QSPI_QUAD_ENABLE 0x1 |
bcostm | 3:c6b5944187d5 | 80 | |
bcostm | 3:c6b5944187d5 | 81 | #define QSPI_HIGH_PERF_DISABLE 0x0 |
bcostm | 3:c6b5944187d5 | 82 | #define QSPI_HIGH_PERF_ENABLE 0x1 |
bcostm | 3:c6b5944187d5 | 83 | /** |
bcostm | 3:c6b5944187d5 | 84 | * @} |
bcostm | 3:c6b5944187d5 | 85 | */ |
bcostm | 3:c6b5944187d5 | 86 | /* Private variables ---------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 87 | |
bcostm | 3:c6b5944187d5 | 88 | /** @defgroup STM32L475E_IOT01_QSPI_Private_Variables QSPI Private Variables |
bcostm | 3:c6b5944187d5 | 89 | * @{ |
bcostm | 3:c6b5944187d5 | 90 | */ |
bcostm | 3:c6b5944187d5 | 91 | QSPI_HandleTypeDef QSPIHandle; |
bcostm | 3:c6b5944187d5 | 92 | |
bcostm | 3:c6b5944187d5 | 93 | /** |
bcostm | 3:c6b5944187d5 | 94 | * @} |
bcostm | 3:c6b5944187d5 | 95 | */ |
bcostm | 3:c6b5944187d5 | 96 | |
bcostm | 3:c6b5944187d5 | 97 | |
bcostm | 3:c6b5944187d5 | 98 | /* Private functions ---------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 99 | |
bcostm | 3:c6b5944187d5 | 100 | /** @defgroup STM32L475E_IOT01_QSPI_Private_Functions QSPI Private Functions |
bcostm | 3:c6b5944187d5 | 101 | * @{ |
bcostm | 3:c6b5944187d5 | 102 | */ |
bcostm | 3:c6b5944187d5 | 103 | static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi); |
bcostm | 3:c6b5944187d5 | 104 | static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi); |
bcostm | 3:c6b5944187d5 | 105 | static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout); |
bcostm | 3:c6b5944187d5 | 106 | static uint8_t QSPI_QuadMode (QSPI_HandleTypeDef *hqspi, uint8_t Operation); |
bcostm | 3:c6b5944187d5 | 107 | static uint8_t QSPI_HighPerfMode (QSPI_HandleTypeDef *hqspi, uint8_t Operation); |
bcostm | 3:c6b5944187d5 | 108 | |
bcostm | 3:c6b5944187d5 | 109 | /** |
bcostm | 3:c6b5944187d5 | 110 | * @} |
bcostm | 3:c6b5944187d5 | 111 | */ |
bcostm | 3:c6b5944187d5 | 112 | |
bcostm | 3:c6b5944187d5 | 113 | /* Exported functions ---------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 114 | |
bcostm | 3:c6b5944187d5 | 115 | /** @addtogroup STM32L475E_IOT01_QSPI_Exported_Functions |
bcostm | 3:c6b5944187d5 | 116 | * @{ |
bcostm | 3:c6b5944187d5 | 117 | */ |
bcostm | 3:c6b5944187d5 | 118 | |
bcostm | 3:c6b5944187d5 | 119 | /** |
bcostm | 3:c6b5944187d5 | 120 | * @brief Initializes the QSPI interface. |
bcostm | 3:c6b5944187d5 | 121 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 122 | */ |
bcostm | 3:c6b5944187d5 | 123 | uint8_t BSP_QSPI_Init(void) |
bcostm | 3:c6b5944187d5 | 124 | { |
bcostm | 3:c6b5944187d5 | 125 | QSPIHandle.Instance = QUADSPI; |
bcostm | 3:c6b5944187d5 | 126 | |
bcostm | 3:c6b5944187d5 | 127 | /* Call the DeInit function to reset the driver */ |
bcostm | 3:c6b5944187d5 | 128 | if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 129 | { |
bcostm | 3:c6b5944187d5 | 130 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 131 | } |
bcostm | 3:c6b5944187d5 | 132 | |
bcostm | 3:c6b5944187d5 | 133 | /* System level initialization */ |
bcostm | 3:c6b5944187d5 | 134 | BSP_QSPI_MspInit(); |
bcostm | 3:c6b5944187d5 | 135 | |
bcostm | 3:c6b5944187d5 | 136 | /* QSPI initialization */ |
bcostm | 3:c6b5944187d5 | 137 | QSPIHandle.Init.ClockPrescaler = 2; /* QSPI clock = 80MHz / (ClockPrescaler+1) = 26.67MHz */ |
bcostm | 3:c6b5944187d5 | 138 | QSPIHandle.Init.FifoThreshold = 4; |
bcostm | 3:c6b5944187d5 | 139 | QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; |
bcostm | 3:c6b5944187d5 | 140 | QSPIHandle.Init.FlashSize = POSITION_VAL(MX25R6435F_FLASH_SIZE) - 1; |
bcostm | 3:c6b5944187d5 | 141 | QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE; |
bcostm | 3:c6b5944187d5 | 142 | QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0; |
bcostm | 3:c6b5944187d5 | 143 | |
bcostm | 3:c6b5944187d5 | 144 | if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 145 | { |
bcostm | 3:c6b5944187d5 | 146 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 147 | } |
bcostm | 3:c6b5944187d5 | 148 | |
bcostm | 3:c6b5944187d5 | 149 | /* QSPI memory reset */ |
bcostm | 3:c6b5944187d5 | 150 | if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 151 | { |
bcostm | 3:c6b5944187d5 | 152 | return QSPI_NOT_SUPPORTED; |
bcostm | 3:c6b5944187d5 | 153 | } |
bcostm | 3:c6b5944187d5 | 154 | |
bcostm | 3:c6b5944187d5 | 155 | /* QSPI quad enable */ |
bcostm | 3:c6b5944187d5 | 156 | if (QSPI_QuadMode(&QSPIHandle, QSPI_QUAD_ENABLE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 157 | { |
bcostm | 3:c6b5944187d5 | 158 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 159 | } |
bcostm | 3:c6b5944187d5 | 160 | |
bcostm | 3:c6b5944187d5 | 161 | /* High performance mode enable */ |
bcostm | 3:c6b5944187d5 | 162 | if (QSPI_HighPerfMode(&QSPIHandle, QSPI_HIGH_PERF_ENABLE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 163 | { |
bcostm | 3:c6b5944187d5 | 164 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 165 | } |
bcostm | 3:c6b5944187d5 | 166 | |
bcostm | 3:c6b5944187d5 | 167 | /* Re-configure the clock for the high performance mode */ |
bcostm | 3:c6b5944187d5 | 168 | QSPIHandle.Init.ClockPrescaler = 1; /* QSPI clock = 80MHz / (ClockPrescaler+1) = 40MHz */ |
bcostm | 3:c6b5944187d5 | 169 | |
bcostm | 3:c6b5944187d5 | 170 | if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 171 | { |
bcostm | 3:c6b5944187d5 | 172 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 173 | } |
bcostm | 3:c6b5944187d5 | 174 | |
bcostm | 3:c6b5944187d5 | 175 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 176 | } |
bcostm | 3:c6b5944187d5 | 177 | |
bcostm | 3:c6b5944187d5 | 178 | /** |
bcostm | 3:c6b5944187d5 | 179 | * @brief De-Initializes the QSPI interface. |
bcostm | 3:c6b5944187d5 | 180 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 181 | */ |
bcostm | 3:c6b5944187d5 | 182 | uint8_t BSP_QSPI_DeInit(void) |
bcostm | 3:c6b5944187d5 | 183 | { |
bcostm | 3:c6b5944187d5 | 184 | QSPIHandle.Instance = QUADSPI; |
bcostm | 3:c6b5944187d5 | 185 | |
bcostm | 3:c6b5944187d5 | 186 | /* Call the DeInit function to reset the driver */ |
bcostm | 3:c6b5944187d5 | 187 | if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 188 | { |
bcostm | 3:c6b5944187d5 | 189 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 190 | } |
bcostm | 3:c6b5944187d5 | 191 | |
bcostm | 3:c6b5944187d5 | 192 | /* System level De-initialization */ |
bcostm | 3:c6b5944187d5 | 193 | BSP_QSPI_MspDeInit(); |
bcostm | 3:c6b5944187d5 | 194 | |
bcostm | 3:c6b5944187d5 | 195 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 196 | } |
bcostm | 3:c6b5944187d5 | 197 | |
bcostm | 3:c6b5944187d5 | 198 | /** |
bcostm | 3:c6b5944187d5 | 199 | * @brief Reads an amount of data from the QSPI memory. |
bcostm | 3:c6b5944187d5 | 200 | * @param pData : Pointer to data to be read |
bcostm | 3:c6b5944187d5 | 201 | * @param ReadAddr : Read start address |
bcostm | 3:c6b5944187d5 | 202 | * @param Size : Size of data to read |
bcostm | 3:c6b5944187d5 | 203 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 204 | */ |
bcostm | 3:c6b5944187d5 | 205 | uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size) |
bcostm | 3:c6b5944187d5 | 206 | { |
bcostm | 3:c6b5944187d5 | 207 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 208 | |
bcostm | 3:c6b5944187d5 | 209 | /* Initialize the read command */ |
bcostm | 3:c6b5944187d5 | 210 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 211 | sCommand.Instruction = QUAD_INOUT_READ_CMD; |
bcostm | 3:c6b5944187d5 | 212 | sCommand.AddressMode = QSPI_ADDRESS_4_LINES; |
bcostm | 3:c6b5944187d5 | 213 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 214 | sCommand.Address = ReadAddr; |
bcostm | 3:c6b5944187d5 | 215 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; |
bcostm | 3:c6b5944187d5 | 216 | sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; |
bcostm | 3:c6b5944187d5 | 217 | sCommand.AlternateBytes = MX25R6435F_ALT_BYTES_NO_PE_MODE; |
bcostm | 3:c6b5944187d5 | 218 | sCommand.DataMode = QSPI_DATA_4_LINES; |
bcostm | 3:c6b5944187d5 | 219 | sCommand.DummyCycles = MX25R6435F_DUMMY_CYCLES_READ_QUAD; |
bcostm | 3:c6b5944187d5 | 220 | sCommand.NbData = Size; |
bcostm | 3:c6b5944187d5 | 221 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 222 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 223 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 224 | |
bcostm | 3:c6b5944187d5 | 225 | /* Configure the command */ |
bcostm | 3:c6b5944187d5 | 226 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 227 | { |
bcostm | 3:c6b5944187d5 | 228 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 229 | } |
bcostm | 3:c6b5944187d5 | 230 | |
bcostm | 3:c6b5944187d5 | 231 | /* Reception of the data */ |
bcostm | 3:c6b5944187d5 | 232 | if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 233 | { |
bcostm | 3:c6b5944187d5 | 234 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 235 | } |
bcostm | 3:c6b5944187d5 | 236 | |
bcostm | 3:c6b5944187d5 | 237 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 238 | } |
bcostm | 3:c6b5944187d5 | 239 | |
bcostm | 3:c6b5944187d5 | 240 | /** |
bcostm | 3:c6b5944187d5 | 241 | * @brief Writes an amount of data to the QSPI memory. |
bcostm | 3:c6b5944187d5 | 242 | * @param pData : Pointer to data to be written |
bcostm | 3:c6b5944187d5 | 243 | * @param WriteAddr : Write start address |
bcostm | 3:c6b5944187d5 | 244 | * @param Size : Size of data to write |
bcostm | 3:c6b5944187d5 | 245 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 246 | */ |
bcostm | 3:c6b5944187d5 | 247 | uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size) |
bcostm | 3:c6b5944187d5 | 248 | { |
bcostm | 3:c6b5944187d5 | 249 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 250 | uint32_t end_addr, current_size, current_addr; |
bcostm | 3:c6b5944187d5 | 251 | |
bcostm | 3:c6b5944187d5 | 252 | /* Calculation of the size between the write address and the end of the page */ |
bcostm | 3:c6b5944187d5 | 253 | current_size = MX25R6435F_PAGE_SIZE - (WriteAddr % MX25R6435F_PAGE_SIZE); |
bcostm | 3:c6b5944187d5 | 254 | |
bcostm | 3:c6b5944187d5 | 255 | /* Check if the size of the data is less than the remaining place in the page */ |
bcostm | 3:c6b5944187d5 | 256 | if (current_size > Size) |
bcostm | 3:c6b5944187d5 | 257 | { |
bcostm | 3:c6b5944187d5 | 258 | current_size = Size; |
bcostm | 3:c6b5944187d5 | 259 | } |
bcostm | 3:c6b5944187d5 | 260 | |
bcostm | 3:c6b5944187d5 | 261 | /* Initialize the adress variables */ |
bcostm | 3:c6b5944187d5 | 262 | current_addr = WriteAddr; |
bcostm | 3:c6b5944187d5 | 263 | end_addr = WriteAddr + Size; |
bcostm | 3:c6b5944187d5 | 264 | |
bcostm | 3:c6b5944187d5 | 265 | /* Initialize the program command */ |
bcostm | 3:c6b5944187d5 | 266 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 267 | sCommand.Instruction = QUAD_PAGE_PROG_CMD; |
bcostm | 3:c6b5944187d5 | 268 | sCommand.AddressMode = QSPI_ADDRESS_4_LINES; |
bcostm | 3:c6b5944187d5 | 269 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 270 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 271 | sCommand.DataMode = QSPI_DATA_4_LINES; |
bcostm | 3:c6b5944187d5 | 272 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 273 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 274 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 275 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 276 | |
bcostm | 3:c6b5944187d5 | 277 | /* Perform the write page by page */ |
bcostm | 3:c6b5944187d5 | 278 | do |
bcostm | 3:c6b5944187d5 | 279 | { |
bcostm | 3:c6b5944187d5 | 280 | sCommand.Address = current_addr; |
bcostm | 3:c6b5944187d5 | 281 | sCommand.NbData = current_size; |
bcostm | 3:c6b5944187d5 | 282 | |
bcostm | 3:c6b5944187d5 | 283 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 284 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 285 | { |
bcostm | 3:c6b5944187d5 | 286 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 287 | } |
bcostm | 3:c6b5944187d5 | 288 | |
bcostm | 3:c6b5944187d5 | 289 | /* Configure the command */ |
bcostm | 3:c6b5944187d5 | 290 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 291 | { |
bcostm | 3:c6b5944187d5 | 292 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 293 | } |
bcostm | 3:c6b5944187d5 | 294 | |
bcostm | 3:c6b5944187d5 | 295 | /* Transmission of the data */ |
bcostm | 3:c6b5944187d5 | 296 | if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 297 | { |
bcostm | 3:c6b5944187d5 | 298 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 299 | } |
bcostm | 3:c6b5944187d5 | 300 | |
bcostm | 3:c6b5944187d5 | 301 | /* Configure automatic polling mode to wait for end of program */ |
bcostm | 3:c6b5944187d5 | 302 | if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 303 | { |
bcostm | 3:c6b5944187d5 | 304 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 305 | } |
bcostm | 3:c6b5944187d5 | 306 | |
bcostm | 3:c6b5944187d5 | 307 | /* Update the address and size variables for next page programming */ |
bcostm | 3:c6b5944187d5 | 308 | current_addr += current_size; |
bcostm | 3:c6b5944187d5 | 309 | pData += current_size; |
bcostm | 3:c6b5944187d5 | 310 | current_size = ((current_addr + MX25R6435F_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MX25R6435F_PAGE_SIZE; |
bcostm | 3:c6b5944187d5 | 311 | } while (current_addr < end_addr); |
bcostm | 3:c6b5944187d5 | 312 | |
bcostm | 3:c6b5944187d5 | 313 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 314 | } |
bcostm | 3:c6b5944187d5 | 315 | |
bcostm | 3:c6b5944187d5 | 316 | /** |
bcostm | 3:c6b5944187d5 | 317 | * @brief Erases the specified block of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 318 | * @param BlockAddress : Block address to erase |
bcostm | 3:c6b5944187d5 | 319 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 320 | */ |
bcostm | 3:c6b5944187d5 | 321 | uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress) |
bcostm | 3:c6b5944187d5 | 322 | { |
bcostm | 3:c6b5944187d5 | 323 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 324 | |
bcostm | 3:c6b5944187d5 | 325 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 326 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 327 | sCommand.Instruction = BLOCK_ERASE_CMD; |
bcostm | 3:c6b5944187d5 | 328 | sCommand.AddressMode = QSPI_ADDRESS_1_LINE; |
bcostm | 3:c6b5944187d5 | 329 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 330 | sCommand.Address = BlockAddress; |
bcostm | 3:c6b5944187d5 | 331 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 332 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 333 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 334 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 335 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 336 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 337 | |
bcostm | 3:c6b5944187d5 | 338 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 339 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 340 | { |
bcostm | 3:c6b5944187d5 | 341 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 342 | } |
bcostm | 3:c6b5944187d5 | 343 | |
bcostm | 3:c6b5944187d5 | 344 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 345 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 346 | { |
bcostm | 3:c6b5944187d5 | 347 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 348 | } |
bcostm | 3:c6b5944187d5 | 349 | |
bcostm | 3:c6b5944187d5 | 350 | /* Configure automatic polling mode to wait for end of erase */ |
bcostm | 3:c6b5944187d5 | 351 | if (QSPI_AutoPollingMemReady(&QSPIHandle, MX25R6435F_BLOCK_ERASE_MAX_TIME) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 352 | { |
bcostm | 3:c6b5944187d5 | 353 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 354 | } |
bcostm | 3:c6b5944187d5 | 355 | |
bcostm | 3:c6b5944187d5 | 356 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 357 | } |
bcostm | 3:c6b5944187d5 | 358 | |
bcostm | 3:c6b5944187d5 | 359 | /** |
bcostm | 3:c6b5944187d5 | 360 | * @brief Erases the specified sector of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 361 | * @param Sector : Sector address to erase (0 to 255) |
bcostm | 3:c6b5944187d5 | 362 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 363 | * @note This function is non blocking meaning that sector erase |
bcostm | 3:c6b5944187d5 | 364 | * operation is started but not completed when the function |
bcostm | 3:c6b5944187d5 | 365 | * returns. Application has to call BSP_QSPI_GetStatus() |
bcostm | 3:c6b5944187d5 | 366 | * to know when the device is available again (i.e. erase operation |
bcostm | 3:c6b5944187d5 | 367 | * completed). |
bcostm | 3:c6b5944187d5 | 368 | */ |
bcostm | 3:c6b5944187d5 | 369 | uint8_t BSP_QSPI_Erase_Sector(uint32_t Sector) |
bcostm | 3:c6b5944187d5 | 370 | { |
bcostm | 3:c6b5944187d5 | 371 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 372 | |
bcostm | 3:c6b5944187d5 | 373 | if (Sector >= (uint32_t)(MX25R6435F_FLASH_SIZE/MX25R6435F_SECTOR_SIZE)) |
bcostm | 3:c6b5944187d5 | 374 | { |
bcostm | 3:c6b5944187d5 | 375 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 376 | } |
bcostm | 3:c6b5944187d5 | 377 | |
bcostm | 3:c6b5944187d5 | 378 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 379 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 380 | sCommand.Instruction = SECTOR_ERASE_CMD; |
bcostm | 3:c6b5944187d5 | 381 | sCommand.AddressMode = QSPI_ADDRESS_1_LINE; |
bcostm | 3:c6b5944187d5 | 382 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 383 | sCommand.Address = (Sector * MX25R6435F_SECTOR_SIZE); |
bcostm | 3:c6b5944187d5 | 384 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 385 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 386 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 387 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 388 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 389 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 390 | |
bcostm | 3:c6b5944187d5 | 391 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 392 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 393 | { |
bcostm | 3:c6b5944187d5 | 394 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 395 | } |
bcostm | 3:c6b5944187d5 | 396 | |
bcostm | 3:c6b5944187d5 | 397 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 398 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 399 | { |
bcostm | 3:c6b5944187d5 | 400 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 401 | } |
bcostm | 3:c6b5944187d5 | 402 | |
bcostm | 3:c6b5944187d5 | 403 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 404 | } |
bcostm | 3:c6b5944187d5 | 405 | |
bcostm | 3:c6b5944187d5 | 406 | /** |
bcostm | 3:c6b5944187d5 | 407 | * @brief Erases the entire QSPI memory. |
bcostm | 3:c6b5944187d5 | 408 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 409 | */ |
bcostm | 3:c6b5944187d5 | 410 | uint8_t BSP_QSPI_Erase_Chip(void) |
bcostm | 3:c6b5944187d5 | 411 | { |
bcostm | 3:c6b5944187d5 | 412 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 413 | |
bcostm | 3:c6b5944187d5 | 414 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 415 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 416 | sCommand.Instruction = CHIP_ERASE_CMD; |
bcostm | 3:c6b5944187d5 | 417 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 418 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 419 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 420 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 421 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 422 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 423 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 424 | |
bcostm | 3:c6b5944187d5 | 425 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 426 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 427 | { |
bcostm | 3:c6b5944187d5 | 428 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 429 | } |
bcostm | 3:c6b5944187d5 | 430 | |
bcostm | 3:c6b5944187d5 | 431 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 432 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 433 | { |
bcostm | 3:c6b5944187d5 | 434 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 435 | } |
bcostm | 3:c6b5944187d5 | 436 | |
bcostm | 3:c6b5944187d5 | 437 | /* Configure automatic polling mode to wait for end of erase */ |
bcostm | 3:c6b5944187d5 | 438 | if (QSPI_AutoPollingMemReady(&QSPIHandle, MX25R6435F_CHIP_ERASE_MAX_TIME) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 439 | { |
bcostm | 3:c6b5944187d5 | 440 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 441 | } |
bcostm | 3:c6b5944187d5 | 442 | |
bcostm | 3:c6b5944187d5 | 443 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 444 | } |
bcostm | 3:c6b5944187d5 | 445 | |
bcostm | 3:c6b5944187d5 | 446 | /** |
bcostm | 3:c6b5944187d5 | 447 | * @brief Reads current status of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 448 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 449 | */ |
bcostm | 3:c6b5944187d5 | 450 | uint8_t BSP_QSPI_GetStatus(void) |
bcostm | 3:c6b5944187d5 | 451 | { |
bcostm | 3:c6b5944187d5 | 452 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 453 | uint8_t reg; |
bcostm | 3:c6b5944187d5 | 454 | |
bcostm | 3:c6b5944187d5 | 455 | /* Initialize the read security register command */ |
bcostm | 3:c6b5944187d5 | 456 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 457 | sCommand.Instruction = READ_SEC_REG_CMD; |
bcostm | 3:c6b5944187d5 | 458 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 459 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 460 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 461 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 462 | sCommand.NbData = 1; |
bcostm | 3:c6b5944187d5 | 463 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 464 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 465 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 466 | |
bcostm | 3:c6b5944187d5 | 467 | /* Configure the command */ |
bcostm | 3:c6b5944187d5 | 468 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 469 | { |
bcostm | 3:c6b5944187d5 | 470 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 471 | } |
bcostm | 3:c6b5944187d5 | 472 | |
bcostm | 3:c6b5944187d5 | 473 | /* Reception of the data */ |
bcostm | 3:c6b5944187d5 | 474 | if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 475 | { |
bcostm | 3:c6b5944187d5 | 476 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 477 | } |
bcostm | 3:c6b5944187d5 | 478 | |
bcostm | 3:c6b5944187d5 | 479 | /* Check the value of the register */ |
bcostm | 3:c6b5944187d5 | 480 | if ((reg & (MX25R6435F_SECR_P_FAIL | MX25R6435F_SECR_E_FAIL)) != 0) |
bcostm | 3:c6b5944187d5 | 481 | { |
bcostm | 3:c6b5944187d5 | 482 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 483 | } |
bcostm | 3:c6b5944187d5 | 484 | else if ((reg & (MX25R6435F_SECR_PSB | MX25R6435F_SECR_ESB)) != 0) |
bcostm | 3:c6b5944187d5 | 485 | { |
bcostm | 3:c6b5944187d5 | 486 | return QSPI_SUSPENDED; |
bcostm | 3:c6b5944187d5 | 487 | } |
bcostm | 3:c6b5944187d5 | 488 | |
bcostm | 3:c6b5944187d5 | 489 | /* Initialize the read status register command */ |
bcostm | 3:c6b5944187d5 | 490 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 491 | |
bcostm | 3:c6b5944187d5 | 492 | /* Configure the command */ |
bcostm | 3:c6b5944187d5 | 493 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 494 | { |
bcostm | 3:c6b5944187d5 | 495 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 496 | } |
bcostm | 3:c6b5944187d5 | 497 | |
bcostm | 3:c6b5944187d5 | 498 | /* Reception of the data */ |
bcostm | 3:c6b5944187d5 | 499 | if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 500 | { |
bcostm | 3:c6b5944187d5 | 501 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 502 | } |
bcostm | 3:c6b5944187d5 | 503 | |
bcostm | 3:c6b5944187d5 | 504 | /* Check the value of the register */ |
bcostm | 3:c6b5944187d5 | 505 | if ((reg & MX25R6435F_SR_WIP) != 0) |
bcostm | 3:c6b5944187d5 | 506 | { |
bcostm | 3:c6b5944187d5 | 507 | return QSPI_BUSY; |
bcostm | 3:c6b5944187d5 | 508 | } |
bcostm | 3:c6b5944187d5 | 509 | else |
bcostm | 3:c6b5944187d5 | 510 | { |
bcostm | 3:c6b5944187d5 | 511 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 512 | } |
bcostm | 3:c6b5944187d5 | 513 | } |
bcostm | 3:c6b5944187d5 | 514 | |
bcostm | 3:c6b5944187d5 | 515 | /** |
bcostm | 3:c6b5944187d5 | 516 | * @brief Return the configuration of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 517 | * @param pInfo : pointer on the configuration structure |
bcostm | 3:c6b5944187d5 | 518 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 519 | */ |
bcostm | 3:c6b5944187d5 | 520 | uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo) |
bcostm | 3:c6b5944187d5 | 521 | { |
bcostm | 3:c6b5944187d5 | 522 | /* Configure the structure with the memory configuration */ |
bcostm | 3:c6b5944187d5 | 523 | pInfo->FlashSize = MX25R6435F_FLASH_SIZE; |
bcostm | 3:c6b5944187d5 | 524 | pInfo->EraseSectorSize = MX25R6435F_SECTOR_SIZE; |
bcostm | 3:c6b5944187d5 | 525 | pInfo->EraseSectorsNumber = (MX25R6435F_FLASH_SIZE/MX25R6435F_SECTOR_SIZE); |
bcostm | 3:c6b5944187d5 | 526 | pInfo->ProgPageSize = MX25R6435F_PAGE_SIZE; |
bcostm | 3:c6b5944187d5 | 527 | pInfo->ProgPagesNumber = (MX25R6435F_FLASH_SIZE/MX25R6435F_PAGE_SIZE); |
bcostm | 3:c6b5944187d5 | 528 | |
bcostm | 3:c6b5944187d5 | 529 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 530 | } |
bcostm | 3:c6b5944187d5 | 531 | |
bcostm | 3:c6b5944187d5 | 532 | /** |
bcostm | 3:c6b5944187d5 | 533 | * @brief Configure the QSPI in memory-mapped mode |
bcostm | 3:c6b5944187d5 | 534 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 535 | */ |
bcostm | 3:c6b5944187d5 | 536 | uint8_t BSP_QSPI_EnableMemoryMappedMode(void) |
bcostm | 3:c6b5944187d5 | 537 | { |
bcostm | 3:c6b5944187d5 | 538 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 539 | QSPI_MemoryMappedTypeDef sMemMappedCfg; |
bcostm | 3:c6b5944187d5 | 540 | |
bcostm | 3:c6b5944187d5 | 541 | /* Configure the command for the read instruction */ |
bcostm | 3:c6b5944187d5 | 542 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 543 | sCommand.Instruction = QUAD_INOUT_READ_CMD; |
bcostm | 3:c6b5944187d5 | 544 | sCommand.AddressMode = QSPI_ADDRESS_4_LINES; |
bcostm | 3:c6b5944187d5 | 545 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 546 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; |
bcostm | 3:c6b5944187d5 | 547 | sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; |
bcostm | 3:c6b5944187d5 | 548 | sCommand.AlternateBytes = MX25R6435F_ALT_BYTES_NO_PE_MODE; |
bcostm | 3:c6b5944187d5 | 549 | sCommand.DataMode = QSPI_DATA_4_LINES; |
bcostm | 3:c6b5944187d5 | 550 | sCommand.DummyCycles = MX25R6435F_DUMMY_CYCLES_READ_QUAD; |
bcostm | 3:c6b5944187d5 | 551 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 552 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 553 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 554 | |
bcostm | 3:c6b5944187d5 | 555 | /* Configure the memory mapped mode */ |
bcostm | 3:c6b5944187d5 | 556 | sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; |
bcostm | 3:c6b5944187d5 | 557 | |
bcostm | 3:c6b5944187d5 | 558 | if (HAL_QSPI_MemoryMapped(&QSPIHandle, &sCommand, &sMemMappedCfg) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 559 | { |
bcostm | 3:c6b5944187d5 | 560 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 561 | } |
bcostm | 3:c6b5944187d5 | 562 | |
bcostm | 3:c6b5944187d5 | 563 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 564 | } |
bcostm | 3:c6b5944187d5 | 565 | |
bcostm | 3:c6b5944187d5 | 566 | /** |
bcostm | 3:c6b5944187d5 | 567 | * @brief This function suspends an ongoing erase command. |
bcostm | 3:c6b5944187d5 | 568 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 569 | */ |
bcostm | 3:c6b5944187d5 | 570 | uint8_t BSP_QSPI_SuspendErase(void) |
bcostm | 3:c6b5944187d5 | 571 | { |
bcostm | 3:c6b5944187d5 | 572 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 573 | |
bcostm | 3:c6b5944187d5 | 574 | /* Check whether the device is busy (erase operation is |
bcostm | 3:c6b5944187d5 | 575 | in progress). |
bcostm | 3:c6b5944187d5 | 576 | */ |
bcostm | 3:c6b5944187d5 | 577 | if (BSP_QSPI_GetStatus() == QSPI_BUSY) |
bcostm | 3:c6b5944187d5 | 578 | { |
bcostm | 3:c6b5944187d5 | 579 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 580 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 581 | sCommand.Instruction = PROG_ERASE_SUSPEND_CMD; |
bcostm | 3:c6b5944187d5 | 582 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 583 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 584 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 585 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 586 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 587 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 588 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 589 | |
bcostm | 3:c6b5944187d5 | 590 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 591 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 592 | { |
bcostm | 3:c6b5944187d5 | 593 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 594 | } |
bcostm | 3:c6b5944187d5 | 595 | |
bcostm | 3:c6b5944187d5 | 596 | if (BSP_QSPI_GetStatus() == QSPI_SUSPENDED) |
bcostm | 3:c6b5944187d5 | 597 | { |
bcostm | 3:c6b5944187d5 | 598 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 599 | } |
bcostm | 3:c6b5944187d5 | 600 | |
bcostm | 3:c6b5944187d5 | 601 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 602 | } |
bcostm | 3:c6b5944187d5 | 603 | |
bcostm | 3:c6b5944187d5 | 604 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 605 | } |
bcostm | 3:c6b5944187d5 | 606 | |
bcostm | 3:c6b5944187d5 | 607 | /** |
bcostm | 3:c6b5944187d5 | 608 | * @brief This function resumes a paused erase command. |
bcostm | 3:c6b5944187d5 | 609 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 610 | */ |
bcostm | 3:c6b5944187d5 | 611 | uint8_t BSP_QSPI_ResumeErase(void) |
bcostm | 3:c6b5944187d5 | 612 | { |
bcostm | 3:c6b5944187d5 | 613 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 614 | |
bcostm | 3:c6b5944187d5 | 615 | /* Check whether the device is in suspended state */ |
bcostm | 3:c6b5944187d5 | 616 | if (BSP_QSPI_GetStatus() == QSPI_SUSPENDED) |
bcostm | 3:c6b5944187d5 | 617 | { |
bcostm | 3:c6b5944187d5 | 618 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 619 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 620 | sCommand.Instruction = PROG_ERASE_RESUME_CMD; |
bcostm | 3:c6b5944187d5 | 621 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 622 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 623 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 624 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 625 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 626 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 627 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 628 | |
bcostm | 3:c6b5944187d5 | 629 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 630 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 631 | { |
bcostm | 3:c6b5944187d5 | 632 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 633 | } |
bcostm | 3:c6b5944187d5 | 634 | |
bcostm | 3:c6b5944187d5 | 635 | /* |
bcostm | 3:c6b5944187d5 | 636 | When this command is executed, the status register write in progress bit is set to 1, and |
bcostm | 3:c6b5944187d5 | 637 | the flag status register program erase controller bit is set to 0. This command is ignored |
bcostm | 3:c6b5944187d5 | 638 | if the device is not in a suspended state. |
bcostm | 3:c6b5944187d5 | 639 | */ |
bcostm | 3:c6b5944187d5 | 640 | |
bcostm | 3:c6b5944187d5 | 641 | if (BSP_QSPI_GetStatus() == QSPI_BUSY) |
bcostm | 3:c6b5944187d5 | 642 | { |
bcostm | 3:c6b5944187d5 | 643 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 644 | } |
bcostm | 3:c6b5944187d5 | 645 | |
bcostm | 3:c6b5944187d5 | 646 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 647 | } |
bcostm | 3:c6b5944187d5 | 648 | |
bcostm | 3:c6b5944187d5 | 649 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 650 | } |
bcostm | 3:c6b5944187d5 | 651 | |
bcostm | 3:c6b5944187d5 | 652 | /** |
bcostm | 3:c6b5944187d5 | 653 | * @brief This function enter the QSPI memory in deep power down mode. |
bcostm | 3:c6b5944187d5 | 654 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 655 | */ |
bcostm | 3:c6b5944187d5 | 656 | uint8_t BSP_QSPI_EnterDeepPowerDown(void) |
bcostm | 3:c6b5944187d5 | 657 | { |
bcostm | 3:c6b5944187d5 | 658 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 659 | |
bcostm | 3:c6b5944187d5 | 660 | /* Initialize the deep power down command */ |
bcostm | 3:c6b5944187d5 | 661 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 662 | sCommand.Instruction = DEEP_POWER_DOWN_CMD; |
bcostm | 3:c6b5944187d5 | 663 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 664 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 665 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 666 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 667 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 668 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 669 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 670 | |
bcostm | 3:c6b5944187d5 | 671 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 672 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 673 | { |
bcostm | 3:c6b5944187d5 | 674 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 675 | } |
bcostm | 3:c6b5944187d5 | 676 | |
bcostm | 3:c6b5944187d5 | 677 | /* --- Memory takes 10us max to enter deep power down --- */ |
bcostm | 3:c6b5944187d5 | 678 | /* --- At least 30us should be respected before leaving deep power down --- */ |
bcostm | 3:c6b5944187d5 | 679 | |
bcostm | 3:c6b5944187d5 | 680 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 681 | } |
bcostm | 3:c6b5944187d5 | 682 | |
bcostm | 3:c6b5944187d5 | 683 | /** |
bcostm | 3:c6b5944187d5 | 684 | * @brief This function leave the QSPI memory from deep power down mode. |
bcostm | 3:c6b5944187d5 | 685 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 686 | */ |
bcostm | 3:c6b5944187d5 | 687 | uint8_t BSP_QSPI_LeaveDeepPowerDown(void) |
bcostm | 3:c6b5944187d5 | 688 | { |
bcostm | 3:c6b5944187d5 | 689 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 690 | |
bcostm | 3:c6b5944187d5 | 691 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 692 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 693 | sCommand.Instruction = NO_OPERATION_CMD; |
bcostm | 3:c6b5944187d5 | 694 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 695 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 696 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 697 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 698 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 699 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 700 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 701 | |
bcostm | 3:c6b5944187d5 | 702 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 703 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 704 | { |
bcostm | 3:c6b5944187d5 | 705 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 706 | } |
bcostm | 3:c6b5944187d5 | 707 | |
bcostm | 3:c6b5944187d5 | 708 | /* --- A NOP command is sent to the memory, as the nCS should be low for at least 20 ns --- */ |
bcostm | 3:c6b5944187d5 | 709 | /* --- Memory takes 35us min to leave deep power down --- */ |
bcostm | 3:c6b5944187d5 | 710 | |
bcostm | 3:c6b5944187d5 | 711 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 712 | } |
bcostm | 3:c6b5944187d5 | 713 | |
bcostm | 3:c6b5944187d5 | 714 | /** |
bcostm | 3:c6b5944187d5 | 715 | * @brief Initializes the QSPI MSP. |
bcostm | 3:c6b5944187d5 | 716 | * @retval None |
bcostm | 3:c6b5944187d5 | 717 | */ |
bcostm | 3:c6b5944187d5 | 718 | __weak void BSP_QSPI_MspInit(void) |
bcostm | 3:c6b5944187d5 | 719 | { |
bcostm | 3:c6b5944187d5 | 720 | GPIO_InitTypeDef GPIO_InitStruct; |
bcostm | 3:c6b5944187d5 | 721 | |
bcostm | 3:c6b5944187d5 | 722 | /* Enable the QuadSPI memory interface clock */ |
bcostm | 3:c6b5944187d5 | 723 | __HAL_RCC_QSPI_CLK_ENABLE(); |
bcostm | 3:c6b5944187d5 | 724 | |
bcostm | 3:c6b5944187d5 | 725 | /* Reset the QuadSPI memory interface */ |
bcostm | 3:c6b5944187d5 | 726 | __HAL_RCC_QSPI_FORCE_RESET(); |
bcostm | 3:c6b5944187d5 | 727 | __HAL_RCC_QSPI_RELEASE_RESET(); |
bcostm | 3:c6b5944187d5 | 728 | |
bcostm | 3:c6b5944187d5 | 729 | /* Enable GPIO clocks */ |
bcostm | 3:c6b5944187d5 | 730 | __HAL_RCC_GPIOE_CLK_ENABLE(); |
bcostm | 3:c6b5944187d5 | 731 | |
bcostm | 3:c6b5944187d5 | 732 | /* QSPI CLK, CS, D0, D1, D2 and D3 GPIO pins configuration */ |
bcostm | 3:c6b5944187d5 | 733 | GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\ |
bcostm | 3:c6b5944187d5 | 734 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; |
bcostm | 3:c6b5944187d5 | 735 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
bcostm | 3:c6b5944187d5 | 736 | GPIO_InitStruct.Pull = GPIO_NOPULL; |
bcostm | 3:c6b5944187d5 | 737 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
bcostm | 3:c6b5944187d5 | 738 | GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; |
bcostm | 3:c6b5944187d5 | 739 | HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); |
bcostm | 3:c6b5944187d5 | 740 | } |
bcostm | 3:c6b5944187d5 | 741 | |
bcostm | 3:c6b5944187d5 | 742 | /** |
bcostm | 3:c6b5944187d5 | 743 | * @brief De-Initializes the QSPI MSP. |
bcostm | 3:c6b5944187d5 | 744 | * @retval None |
bcostm | 3:c6b5944187d5 | 745 | */ |
bcostm | 3:c6b5944187d5 | 746 | __weak void BSP_QSPI_MspDeInit(void) |
bcostm | 3:c6b5944187d5 | 747 | { |
bcostm | 3:c6b5944187d5 | 748 | GPIO_InitTypeDef GPIO_InitStruct; |
bcostm | 3:c6b5944187d5 | 749 | |
bcostm | 3:c6b5944187d5 | 750 | /* QSPI CLK, CS, D0-D3 GPIO pins de-configuration */ |
bcostm | 3:c6b5944187d5 | 751 | __HAL_RCC_GPIOE_CLK_ENABLE(); |
bcostm | 3:c6b5944187d5 | 752 | GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\ |
bcostm | 3:c6b5944187d5 | 753 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; |
bcostm | 3:c6b5944187d5 | 754 | |
bcostm | 3:c6b5944187d5 | 755 | HAL_GPIO_DeInit(GPIOE, GPIO_InitStruct.Pin); |
bcostm | 3:c6b5944187d5 | 756 | |
bcostm | 3:c6b5944187d5 | 757 | /* Reset the QuadSPI memory interface */ |
bcostm | 3:c6b5944187d5 | 758 | __HAL_RCC_QSPI_FORCE_RESET(); |
bcostm | 3:c6b5944187d5 | 759 | __HAL_RCC_QSPI_RELEASE_RESET(); |
bcostm | 3:c6b5944187d5 | 760 | |
bcostm | 3:c6b5944187d5 | 761 | /* Disable the QuadSPI memory interface clock */ |
bcostm | 3:c6b5944187d5 | 762 | __HAL_RCC_QSPI_CLK_DISABLE(); |
bcostm | 3:c6b5944187d5 | 763 | } |
bcostm | 3:c6b5944187d5 | 764 | |
bcostm | 3:c6b5944187d5 | 765 | /** |
bcostm | 3:c6b5944187d5 | 766 | * @} |
bcostm | 3:c6b5944187d5 | 767 | */ |
bcostm | 3:c6b5944187d5 | 768 | |
bcostm | 3:c6b5944187d5 | 769 | /** @addtogroup STM32L475E_IOT01_QSPI_Private_Functions |
bcostm | 3:c6b5944187d5 | 770 | * @{ |
bcostm | 3:c6b5944187d5 | 771 | */ |
bcostm | 3:c6b5944187d5 | 772 | |
bcostm | 3:c6b5944187d5 | 773 | /** |
bcostm | 3:c6b5944187d5 | 774 | * @brief This function reset the QSPI memory. |
bcostm | 3:c6b5944187d5 | 775 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 776 | * @retval None |
bcostm | 3:c6b5944187d5 | 777 | */ |
bcostm | 3:c6b5944187d5 | 778 | static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi) |
bcostm | 3:c6b5944187d5 | 779 | { |
bcostm | 3:c6b5944187d5 | 780 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 781 | |
bcostm | 3:c6b5944187d5 | 782 | /* Initialize the reset enable command */ |
bcostm | 3:c6b5944187d5 | 783 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 784 | sCommand.Instruction = RESET_ENABLE_CMD; |
bcostm | 3:c6b5944187d5 | 785 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 786 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 787 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 788 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 789 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 790 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 791 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 792 | |
bcostm | 3:c6b5944187d5 | 793 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 794 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 795 | { |
bcostm | 3:c6b5944187d5 | 796 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 797 | } |
bcostm | 3:c6b5944187d5 | 798 | |
bcostm | 3:c6b5944187d5 | 799 | /* Send the reset memory command */ |
bcostm | 3:c6b5944187d5 | 800 | sCommand.Instruction = RESET_MEMORY_CMD; |
bcostm | 3:c6b5944187d5 | 801 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 802 | { |
bcostm | 3:c6b5944187d5 | 803 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 804 | } |
bcostm | 3:c6b5944187d5 | 805 | |
bcostm | 3:c6b5944187d5 | 806 | /* Configure automatic polling mode to wait the memory is ready */ |
bcostm | 3:c6b5944187d5 | 807 | if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 808 | { |
bcostm | 3:c6b5944187d5 | 809 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 810 | } |
bcostm | 3:c6b5944187d5 | 811 | |
bcostm | 3:c6b5944187d5 | 812 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 813 | } |
bcostm | 3:c6b5944187d5 | 814 | |
bcostm | 3:c6b5944187d5 | 815 | /** |
bcostm | 3:c6b5944187d5 | 816 | * @brief This function send a Write Enable and wait it is effective. |
bcostm | 3:c6b5944187d5 | 817 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 818 | * @retval None |
bcostm | 3:c6b5944187d5 | 819 | */ |
bcostm | 3:c6b5944187d5 | 820 | static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi) |
bcostm | 3:c6b5944187d5 | 821 | { |
bcostm | 3:c6b5944187d5 | 822 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 823 | QSPI_AutoPollingTypeDef sConfig; |
bcostm | 3:c6b5944187d5 | 824 | |
bcostm | 3:c6b5944187d5 | 825 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 826 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 827 | sCommand.Instruction = WRITE_ENABLE_CMD; |
bcostm | 3:c6b5944187d5 | 828 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 829 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 830 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 831 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 832 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 833 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 834 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 835 | |
bcostm | 3:c6b5944187d5 | 836 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 837 | { |
bcostm | 3:c6b5944187d5 | 838 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 839 | } |
bcostm | 3:c6b5944187d5 | 840 | |
bcostm | 3:c6b5944187d5 | 841 | /* Configure automatic polling mode to wait for write enabling */ |
bcostm | 3:c6b5944187d5 | 842 | sConfig.Match = MX25R6435F_SR_WEL; |
bcostm | 3:c6b5944187d5 | 843 | sConfig.Mask = MX25R6435F_SR_WEL; |
bcostm | 3:c6b5944187d5 | 844 | sConfig.MatchMode = QSPI_MATCH_MODE_AND; |
bcostm | 3:c6b5944187d5 | 845 | sConfig.StatusBytesSize = 1; |
bcostm | 3:c6b5944187d5 | 846 | sConfig.Interval = 0x10; |
bcostm | 3:c6b5944187d5 | 847 | sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; |
bcostm | 3:c6b5944187d5 | 848 | |
bcostm | 3:c6b5944187d5 | 849 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 850 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 851 | |
bcostm | 3:c6b5944187d5 | 852 | if (HAL_QSPI_AutoPolling(&QSPIHandle, &sCommand, &sConfig, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 853 | { |
bcostm | 3:c6b5944187d5 | 854 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 855 | } |
bcostm | 3:c6b5944187d5 | 856 | |
bcostm | 3:c6b5944187d5 | 857 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 858 | } |
bcostm | 3:c6b5944187d5 | 859 | |
bcostm | 3:c6b5944187d5 | 860 | /** |
bcostm | 3:c6b5944187d5 | 861 | * @brief This function read the SR of the memory and wait the EOP. |
bcostm | 3:c6b5944187d5 | 862 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 863 | * @param Timeout : Timeout for auto-polling |
bcostm | 3:c6b5944187d5 | 864 | * @retval None |
bcostm | 3:c6b5944187d5 | 865 | */ |
bcostm | 3:c6b5944187d5 | 866 | static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) |
bcostm | 3:c6b5944187d5 | 867 | { |
bcostm | 3:c6b5944187d5 | 868 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 869 | QSPI_AutoPollingTypeDef sConfig; |
bcostm | 3:c6b5944187d5 | 870 | |
bcostm | 3:c6b5944187d5 | 871 | /* Configure automatic polling mode to wait for memory ready */ |
bcostm | 3:c6b5944187d5 | 872 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 873 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 874 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 875 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 876 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 877 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 878 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 879 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 880 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 881 | |
bcostm | 3:c6b5944187d5 | 882 | sConfig.Match = 0; |
bcostm | 3:c6b5944187d5 | 883 | sConfig.Mask = MX25R6435F_SR_WIP; |
bcostm | 3:c6b5944187d5 | 884 | sConfig.MatchMode = QSPI_MATCH_MODE_AND; |
bcostm | 3:c6b5944187d5 | 885 | sConfig.StatusBytesSize = 1; |
bcostm | 3:c6b5944187d5 | 886 | sConfig.Interval = 0x10; |
bcostm | 3:c6b5944187d5 | 887 | sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; |
bcostm | 3:c6b5944187d5 | 888 | |
bcostm | 3:c6b5944187d5 | 889 | if (HAL_QSPI_AutoPolling(&QSPIHandle, &sCommand, &sConfig, Timeout) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 890 | { |
bcostm | 3:c6b5944187d5 | 891 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 892 | } |
bcostm | 3:c6b5944187d5 | 893 | |
bcostm | 3:c6b5944187d5 | 894 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 895 | } |
bcostm | 3:c6b5944187d5 | 896 | |
bcostm | 3:c6b5944187d5 | 897 | /** |
bcostm | 3:c6b5944187d5 | 898 | * @brief This function enables/disables the Quad mode of the memory. |
bcostm | 3:c6b5944187d5 | 899 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 900 | * @param Operation : QSPI_QUAD_ENABLE or QSPI_QUAD_DISABLE mode |
bcostm | 3:c6b5944187d5 | 901 | * @retval None |
bcostm | 3:c6b5944187d5 | 902 | */ |
bcostm | 3:c6b5944187d5 | 903 | static uint8_t QSPI_QuadMode(QSPI_HandleTypeDef *hqspi, uint8_t Operation) |
bcostm | 3:c6b5944187d5 | 904 | { |
bcostm | 3:c6b5944187d5 | 905 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 906 | uint8_t reg; |
bcostm | 3:c6b5944187d5 | 907 | |
bcostm | 3:c6b5944187d5 | 908 | /* Read status register */ |
bcostm | 3:c6b5944187d5 | 909 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 910 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 911 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 912 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 913 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 914 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 915 | sCommand.NbData = 1; |
bcostm | 3:c6b5944187d5 | 916 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 917 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 918 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 919 | |
bcostm | 3:c6b5944187d5 | 920 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 921 | { |
bcostm | 3:c6b5944187d5 | 922 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 923 | } |
bcostm | 3:c6b5944187d5 | 924 | |
bcostm | 3:c6b5944187d5 | 925 | if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 926 | { |
bcostm | 3:c6b5944187d5 | 927 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 928 | } |
bcostm | 3:c6b5944187d5 | 929 | |
bcostm | 3:c6b5944187d5 | 930 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 931 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 932 | { |
bcostm | 3:c6b5944187d5 | 933 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 934 | } |
bcostm | 3:c6b5944187d5 | 935 | |
bcostm | 3:c6b5944187d5 | 936 | /* Activate/deactivate the Quad mode */ |
bcostm | 3:c6b5944187d5 | 937 | if (Operation == QSPI_QUAD_ENABLE) |
bcostm | 3:c6b5944187d5 | 938 | { |
bcostm | 3:c6b5944187d5 | 939 | SET_BIT(reg, MX25R6435F_SR_QE); |
bcostm | 3:c6b5944187d5 | 940 | } |
bcostm | 3:c6b5944187d5 | 941 | else |
bcostm | 3:c6b5944187d5 | 942 | { |
bcostm | 3:c6b5944187d5 | 943 | CLEAR_BIT(reg, MX25R6435F_SR_QE); |
bcostm | 3:c6b5944187d5 | 944 | } |
bcostm | 3:c6b5944187d5 | 945 | |
bcostm | 3:c6b5944187d5 | 946 | sCommand.Instruction = WRITE_STATUS_CFG_REG_CMD; |
bcostm | 3:c6b5944187d5 | 947 | |
bcostm | 3:c6b5944187d5 | 948 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 949 | { |
bcostm | 3:c6b5944187d5 | 950 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 951 | } |
bcostm | 3:c6b5944187d5 | 952 | |
bcostm | 3:c6b5944187d5 | 953 | if (HAL_QSPI_Transmit(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 954 | { |
bcostm | 3:c6b5944187d5 | 955 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 956 | } |
bcostm | 3:c6b5944187d5 | 957 | |
bcostm | 3:c6b5944187d5 | 958 | /* Wait that memory is ready */ |
bcostm | 3:c6b5944187d5 | 959 | if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 960 | { |
bcostm | 3:c6b5944187d5 | 961 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 962 | } |
bcostm | 3:c6b5944187d5 | 963 | |
bcostm | 3:c6b5944187d5 | 964 | /* Check the configuration has been correctly done */ |
bcostm | 3:c6b5944187d5 | 965 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 966 | |
bcostm | 3:c6b5944187d5 | 967 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 968 | { |
bcostm | 3:c6b5944187d5 | 969 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 970 | } |
bcostm | 3:c6b5944187d5 | 971 | |
bcostm | 3:c6b5944187d5 | 972 | if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 973 | { |
bcostm | 3:c6b5944187d5 | 974 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 975 | } |
bcostm | 3:c6b5944187d5 | 976 | |
bcostm | 3:c6b5944187d5 | 977 | if ((((reg & MX25R6435F_SR_QE) == 0) && (Operation == QSPI_QUAD_ENABLE)) || |
bcostm | 3:c6b5944187d5 | 978 | (((reg & MX25R6435F_SR_QE) != 0) && (Operation == QSPI_QUAD_DISABLE))) |
bcostm | 3:c6b5944187d5 | 979 | { |
bcostm | 3:c6b5944187d5 | 980 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 981 | } |
bcostm | 3:c6b5944187d5 | 982 | |
bcostm | 3:c6b5944187d5 | 983 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 984 | } |
bcostm | 3:c6b5944187d5 | 985 | |
bcostm | 3:c6b5944187d5 | 986 | /** |
bcostm | 3:c6b5944187d5 | 987 | * @brief This function enables/disables the high performance mode of the memory. |
bcostm | 3:c6b5944187d5 | 988 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 989 | * @param Operation : QSPI_HIGH_PERF_ENABLE or QSPI_HIGH_PERF_DISABLE high performance mode |
bcostm | 3:c6b5944187d5 | 990 | * @retval None |
bcostm | 3:c6b5944187d5 | 991 | */ |
bcostm | 3:c6b5944187d5 | 992 | static uint8_t QSPI_HighPerfMode(QSPI_HandleTypeDef *hqspi, uint8_t Operation) |
bcostm | 3:c6b5944187d5 | 993 | { |
bcostm | 3:c6b5944187d5 | 994 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 995 | uint8_t reg[3]; |
bcostm | 3:c6b5944187d5 | 996 | |
bcostm | 3:c6b5944187d5 | 997 | /* Read status register */ |
bcostm | 3:c6b5944187d5 | 998 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 999 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 1000 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 1001 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 1002 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 1003 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 1004 | sCommand.NbData = 1; |
bcostm | 3:c6b5944187d5 | 1005 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 1006 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 1007 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 1008 | |
bcostm | 3:c6b5944187d5 | 1009 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1010 | { |
bcostm | 3:c6b5944187d5 | 1011 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1012 | } |
bcostm | 3:c6b5944187d5 | 1013 | |
bcostm | 3:c6b5944187d5 | 1014 | if (HAL_QSPI_Receive(&QSPIHandle, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1015 | { |
bcostm | 3:c6b5944187d5 | 1016 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1017 | } |
bcostm | 3:c6b5944187d5 | 1018 | |
bcostm | 3:c6b5944187d5 | 1019 | /* Read configuration registers */ |
bcostm | 3:c6b5944187d5 | 1020 | sCommand.Instruction = READ_CFG_REG_CMD; |
bcostm | 3:c6b5944187d5 | 1021 | sCommand.NbData = 2; |
bcostm | 3:c6b5944187d5 | 1022 | |
bcostm | 3:c6b5944187d5 | 1023 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1024 | { |
bcostm | 3:c6b5944187d5 | 1025 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1026 | } |
bcostm | 3:c6b5944187d5 | 1027 | |
bcostm | 3:c6b5944187d5 | 1028 | if (HAL_QSPI_Receive(&QSPIHandle, &(reg[1]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1029 | { |
bcostm | 3:c6b5944187d5 | 1030 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1031 | } |
bcostm | 3:c6b5944187d5 | 1032 | |
bcostm | 3:c6b5944187d5 | 1033 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 1034 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 1035 | { |
bcostm | 3:c6b5944187d5 | 1036 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1037 | } |
bcostm | 3:c6b5944187d5 | 1038 | |
bcostm | 3:c6b5944187d5 | 1039 | /* Activate/deactivate the Quad mode */ |
bcostm | 3:c6b5944187d5 | 1040 | if (Operation == QSPI_HIGH_PERF_ENABLE) |
bcostm | 3:c6b5944187d5 | 1041 | { |
bcostm | 3:c6b5944187d5 | 1042 | SET_BIT(reg[2], MX25R6435F_CR2_LH_SWITCH); |
bcostm | 3:c6b5944187d5 | 1043 | } |
bcostm | 3:c6b5944187d5 | 1044 | else |
bcostm | 3:c6b5944187d5 | 1045 | { |
bcostm | 3:c6b5944187d5 | 1046 | CLEAR_BIT(reg[2], MX25R6435F_CR2_LH_SWITCH); |
bcostm | 3:c6b5944187d5 | 1047 | } |
bcostm | 3:c6b5944187d5 | 1048 | |
bcostm | 3:c6b5944187d5 | 1049 | sCommand.Instruction = WRITE_STATUS_CFG_REG_CMD; |
bcostm | 3:c6b5944187d5 | 1050 | sCommand.NbData = 3; |
bcostm | 3:c6b5944187d5 | 1051 | |
bcostm | 3:c6b5944187d5 | 1052 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1053 | { |
bcostm | 3:c6b5944187d5 | 1054 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1055 | } |
bcostm | 3:c6b5944187d5 | 1056 | |
bcostm | 3:c6b5944187d5 | 1057 | if (HAL_QSPI_Transmit(&QSPIHandle, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1058 | { |
bcostm | 3:c6b5944187d5 | 1059 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1060 | } |
bcostm | 3:c6b5944187d5 | 1061 | |
bcostm | 3:c6b5944187d5 | 1062 | /* Wait that memory is ready */ |
bcostm | 3:c6b5944187d5 | 1063 | if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 1064 | { |
bcostm | 3:c6b5944187d5 | 1065 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1066 | } |
bcostm | 3:c6b5944187d5 | 1067 | |
bcostm | 3:c6b5944187d5 | 1068 | /* Check the configuration has been correctly done */ |
bcostm | 3:c6b5944187d5 | 1069 | sCommand.Instruction = READ_CFG_REG_CMD; |
bcostm | 3:c6b5944187d5 | 1070 | sCommand.NbData = 2; |
bcostm | 3:c6b5944187d5 | 1071 | |
bcostm | 3:c6b5944187d5 | 1072 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1073 | { |
bcostm | 3:c6b5944187d5 | 1074 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1075 | } |
bcostm | 3:c6b5944187d5 | 1076 | |
bcostm | 3:c6b5944187d5 | 1077 | if (HAL_QSPI_Receive(&QSPIHandle, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1078 | { |
bcostm | 3:c6b5944187d5 | 1079 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1080 | } |
bcostm | 3:c6b5944187d5 | 1081 | |
bcostm | 3:c6b5944187d5 | 1082 | if ((((reg[1] & MX25R6435F_CR2_LH_SWITCH) == 0) && (Operation == QSPI_HIGH_PERF_ENABLE)) || |
bcostm | 3:c6b5944187d5 | 1083 | (((reg[1] & MX25R6435F_CR2_LH_SWITCH) != 0) && (Operation == QSPI_HIGH_PERF_DISABLE))) |
bcostm | 3:c6b5944187d5 | 1084 | { |
bcostm | 3:c6b5944187d5 | 1085 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1086 | } |
bcostm | 3:c6b5944187d5 | 1087 | |
bcostm | 3:c6b5944187d5 | 1088 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 1089 | } |
bcostm | 3:c6b5944187d5 | 1090 | |
bcostm | 3:c6b5944187d5 | 1091 | /** |
bcostm | 3:c6b5944187d5 | 1092 | * @} |
bcostm | 3:c6b5944187d5 | 1093 | */ |
bcostm | 3:c6b5944187d5 | 1094 | |
bcostm | 3:c6b5944187d5 | 1095 | /** |
bcostm | 3:c6b5944187d5 | 1096 | * @} |
bcostm | 3:c6b5944187d5 | 1097 | */ |
bcostm | 3:c6b5944187d5 | 1098 | |
bcostm | 3:c6b5944187d5 | 1099 | /** |
bcostm | 3:c6b5944187d5 | 1100 | * @} |
bcostm | 3:c6b5944187d5 | 1101 | */ |
bcostm | 3:c6b5944187d5 | 1102 | |
bcostm | 3:c6b5944187d5 | 1103 | /** |
bcostm | 3:c6b5944187d5 | 1104 | * @} |
bcostm | 3:c6b5944187d5 | 1105 | */ |
bcostm | 3:c6b5944187d5 | 1106 | |
bcostm | 3:c6b5944187d5 | 1107 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
bcostm | 3:c6b5944187d5 | 1108 |