ST / BSP_B-L475E-IOT01

Contains the BSP driver for the B-L475E-IOT01 board.

Dependents:   mbed-os-example-ble-Thermometer DISCO_L475VG_IOT01-Telegram-BOT DISCO_L475VG_IOT01-sche_cheveux DISCO_L475VG_IOT01-QSPI_FLASH_FILE_SYSTEM ... more

https://os.mbed.com/platforms/ST-Discovery-L475E-IOT01A/

Drivers/BSP/B-L475E-IOT01/stm32l475e_iot01_qspi.c@3:c6b5944187d5, 2017-04-14 (annotated)

Committer:
bcostm
Date:
Fri Apr 14 11:34:20 2017 +0200
Revision:
3:c6b5944187d5
Child:
5:0c70bc6d2dc0
Add BSP/B-L4755-IOT01 folder + files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 3:c6b5944187d5 1 /**
bcostm 3:c6b5944187d5 2 ******************************************************************************
bcostm 3:c6b5944187d5 3 * @file stm32l475e_iot01_qspi.c
bcostm 3:c6b5944187d5 4 * @author MCD Application Team
bcostm 3:c6b5944187d5 5 * @version V1.0.0
bcostm 3:c6b5944187d5 6 * @date 17-March-2017
bcostm 3:c6b5944187d5 7 * @brief This file includes a standard driver for the MX25R6435F QSPI
bcostm 3:c6b5944187d5 8 * memory mounted on STM32L475E IOT01 board.
bcostm 3:c6b5944187d5 9 @verbatim
bcostm 3:c6b5944187d5 10 ==============================================================================
bcostm 3:c6b5944187d5 11 ##### How to use this driver #####
bcostm 3:c6b5944187d5 12 ==============================================================================
bcostm 3:c6b5944187d5 13 [..]
bcostm 3:c6b5944187d5 14 (#) This driver is used to drive the MX25R6435F QSPI external
bcostm 3:c6b5944187d5 15 memory mounted on STM32L475E IOT01 board.
bcostm 3:c6b5944187d5 16
bcostm 3:c6b5944187d5 17 (#) This driver need a specific component driver (MX25R6435F) to be included with.
bcostm 3:c6b5944187d5 18
bcostm 3:c6b5944187d5 19 (#) Initialization steps:
bcostm 3:c6b5944187d5 20 (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
bcostm 3:c6b5944187d5 21 function includes the MSP layer hardware resources initialization and the
bcostm 3:c6b5944187d5 22 QSPI interface with the external memory. The BSP_QSPI_DeInit() can be used
bcostm 3:c6b5944187d5 23 to deactivate the QSPI interface.
bcostm 3:c6b5944187d5 24
bcostm 3:c6b5944187d5 25 (#) QSPI memory operations
bcostm 3:c6b5944187d5 26 (++) QSPI memory can be accessed with read/write operations once it is
bcostm 3:c6b5944187d5 27 initialized.
bcostm 3:c6b5944187d5 28 Read/write operation can be performed with AHB access using the functions
bcostm 3:c6b5944187d5 29 BSP_QSPI_Read()/BSP_QSPI_Write().
bcostm 3:c6b5944187d5 30 (++) The function to the QSPI memory in memory-mapped mode is possible after
bcostm 3:c6b5944187d5 31 the call of the function BSP_QSPI_EnableMemoryMappedMode().
bcostm 3:c6b5944187d5 32 (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
bcostm 3:c6b5944187d5 33 (see the QSPI memory data sheet)
bcostm 3:c6b5944187d5 34 (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by
bcostm 3:c6b5944187d5 35 specifying the block address. You can perform an erase operation of the whole
bcostm 3:c6b5944187d5 36 chip by calling the function BSP_QSPI_Erase_Chip().
bcostm 3:c6b5944187d5 37 (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
bcostm 3:c6b5944187d5 38 (see the QSPI memory data sheet)
bcostm 3:c6b5944187d5 39 (++) Perform erase sector operation using the function BSP_QSPI_Erase_Sector()
bcostm 3:c6b5944187d5 40 which is not blocking. So the function BSP_QSPI_GetStatus() should be used
bcostm 3:c6b5944187d5 41 to check if the memory is busy, and the functions BSP_QSPI_SuspendErase()/
bcostm 3:c6b5944187d5 42 BSP_QSPI_ResumeErase() can be used to perform other operations during the
bcostm 3:c6b5944187d5 43 sector erase.
bcostm 3:c6b5944187d5 44 (++) Deep power down of the QSPI memory is managed with the call of the functions
bcostm 3:c6b5944187d5 45 BSP_QSPI_EnterDeepPowerDown()/BSP_QSPI_LeaveDeepPowerDown()
bcostm 3:c6b5944187d5 46 @endverbatim
bcostm 3:c6b5944187d5 47 ******************************************************************************
bcostm 3:c6b5944187d5 48 * @attention
bcostm 3:c6b5944187d5 49 *
bcostm 3:c6b5944187d5 50 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
bcostm 3:c6b5944187d5 51 *
bcostm 3:c6b5944187d5 52 * Redistribution and use in source and binary forms, with or without modification,
bcostm 3:c6b5944187d5 53 * are permitted provided that the following conditions are met:
bcostm 3:c6b5944187d5 54 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 3:c6b5944187d5 55 * this list of conditions and the following disclaimer.
bcostm 3:c6b5944187d5 56 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 3:c6b5944187d5 57 * this list of conditions and the following disclaimer in the documentation
bcostm 3:c6b5944187d5 58 * and/or other materials provided with the distribution.
bcostm 3:c6b5944187d5 59 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 3:c6b5944187d5 60 * may be used to endorse or promote products derived from this software
bcostm 3:c6b5944187d5 61 * without specific prior written permission.
bcostm 3:c6b5944187d5 62 *
bcostm 3:c6b5944187d5 63 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 3:c6b5944187d5 64 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 3:c6b5944187d5 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 3:c6b5944187d5 66 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 3:c6b5944187d5 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 3:c6b5944187d5 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 3:c6b5944187d5 69 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 3:c6b5944187d5 70 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 3:c6b5944187d5 71 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 3:c6b5944187d5 72 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 3:c6b5944187d5 73 *
bcostm 3:c6b5944187d5 74 ******************************************************************************
bcostm 3:c6b5944187d5 75 */
bcostm 3:c6b5944187d5 76
bcostm 3:c6b5944187d5 77 /* Includes ------------------------------------------------------------------*/
bcostm 3:c6b5944187d5 78 #include "stm32l475e_iot01_qspi.h"
bcostm 3:c6b5944187d5 79
bcostm 3:c6b5944187d5 80 /** @addtogroup BSP
bcostm 3:c6b5944187d5 81 * @{
bcostm 3:c6b5944187d5 82 */
bcostm 3:c6b5944187d5 83
bcostm 3:c6b5944187d5 84 /** @addtogroup STM32L475E_IOT01
bcostm 3:c6b5944187d5 85 * @{
bcostm 3:c6b5944187d5 86 */
bcostm 3:c6b5944187d5 87
bcostm 3:c6b5944187d5 88 /** @defgroup STM32L475E_IOT01_QSPI QSPI
bcostm 3:c6b5944187d5 89 * @{
bcostm 3:c6b5944187d5 90 */
bcostm 3:c6b5944187d5 91
bcostm 3:c6b5944187d5 92 /* Private constants --------------------------------------------------------*/
bcostm 3:c6b5944187d5 93 /** @defgroup STM32L475E_IOT01_QSPI_Private_Constants QSPI Private Constants
bcostm 3:c6b5944187d5 94 * @{
bcostm 3:c6b5944187d5 95 */
bcostm 3:c6b5944187d5 96 #define QSPI_QUAD_DISABLE 0x0
bcostm 3:c6b5944187d5 97 #define QSPI_QUAD_ENABLE 0x1
bcostm 3:c6b5944187d5 98
bcostm 3:c6b5944187d5 99 #define QSPI_HIGH_PERF_DISABLE 0x0
bcostm 3:c6b5944187d5 100 #define QSPI_HIGH_PERF_ENABLE 0x1
bcostm 3:c6b5944187d5 101 /**
bcostm 3:c6b5944187d5 102 * @}
bcostm 3:c6b5944187d5 103 */
bcostm 3:c6b5944187d5 104 /* Private variables ---------------------------------------------------------*/
bcostm 3:c6b5944187d5 105
bcostm 3:c6b5944187d5 106 /** @defgroup STM32L475E_IOT01_QSPI_Private_Variables QSPI Private Variables
bcostm 3:c6b5944187d5 107 * @{
bcostm 3:c6b5944187d5 108 */
bcostm 3:c6b5944187d5 109 QSPI_HandleTypeDef QSPIHandle;
bcostm 3:c6b5944187d5 110
bcostm 3:c6b5944187d5 111 /**
bcostm 3:c6b5944187d5 112 * @}
bcostm 3:c6b5944187d5 113 */
bcostm 3:c6b5944187d5 114
bcostm 3:c6b5944187d5 115
bcostm 3:c6b5944187d5 116 /* Private functions ---------------------------------------------------------*/
bcostm 3:c6b5944187d5 117
bcostm 3:c6b5944187d5 118 /** @defgroup STM32L475E_IOT01_QSPI_Private_Functions QSPI Private Functions
bcostm 3:c6b5944187d5 119 * @{
bcostm 3:c6b5944187d5 120 */
bcostm 3:c6b5944187d5 121 static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi);
bcostm 3:c6b5944187d5 122 static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi);
bcostm 3:c6b5944187d5 123 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
bcostm 3:c6b5944187d5 124 static uint8_t QSPI_QuadMode (QSPI_HandleTypeDef *hqspi, uint8_t Operation);
bcostm 3:c6b5944187d5 125 static uint8_t QSPI_HighPerfMode (QSPI_HandleTypeDef *hqspi, uint8_t Operation);
bcostm 3:c6b5944187d5 126
bcostm 3:c6b5944187d5 127 /**
bcostm 3:c6b5944187d5 128 * @}
bcostm 3:c6b5944187d5 129 */
bcostm 3:c6b5944187d5 130
bcostm 3:c6b5944187d5 131 /* Exported functions ---------------------------------------------------------*/
bcostm 3:c6b5944187d5 132
bcostm 3:c6b5944187d5 133 /** @addtogroup STM32L475E_IOT01_QSPI_Exported_Functions
bcostm 3:c6b5944187d5 134 * @{
bcostm 3:c6b5944187d5 135 */
bcostm 3:c6b5944187d5 136
bcostm 3:c6b5944187d5 137 /**
bcostm 3:c6b5944187d5 138 * @brief Initializes the QSPI interface.
bcostm 3:c6b5944187d5 139 * @retval QSPI memory status
bcostm 3:c6b5944187d5 140 */
bcostm 3:c6b5944187d5 141 uint8_t BSP_QSPI_Init(void)
bcostm 3:c6b5944187d5 142 {
bcostm 3:c6b5944187d5 143 QSPIHandle.Instance = QUADSPI;
bcostm 3:c6b5944187d5 144
bcostm 3:c6b5944187d5 145 /* Call the DeInit function to reset the driver */
bcostm 3:c6b5944187d5 146 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
bcostm 3:c6b5944187d5 147 {
bcostm 3:c6b5944187d5 148 return QSPI_ERROR;
bcostm 3:c6b5944187d5 149 }
bcostm 3:c6b5944187d5 150
bcostm 3:c6b5944187d5 151 /* System level initialization */
bcostm 3:c6b5944187d5 152 BSP_QSPI_MspInit();
bcostm 3:c6b5944187d5 153
bcostm 3:c6b5944187d5 154 /* QSPI initialization */
bcostm 3:c6b5944187d5 155 QSPIHandle.Init.ClockPrescaler = 2; /* QSPI clock = 80MHz / (ClockPrescaler+1) = 26.67MHz */
bcostm 3:c6b5944187d5 156 QSPIHandle.Init.FifoThreshold = 4;
bcostm 3:c6b5944187d5 157 QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE;
bcostm 3:c6b5944187d5 158 QSPIHandle.Init.FlashSize = POSITION_VAL(MX25R6435F_FLASH_SIZE) - 1;
bcostm 3:c6b5944187d5 159 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;
bcostm 3:c6b5944187d5 160 QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
bcostm 3:c6b5944187d5 161
bcostm 3:c6b5944187d5 162 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
bcostm 3:c6b5944187d5 163 {
bcostm 3:c6b5944187d5 164 return QSPI_ERROR;
bcostm 3:c6b5944187d5 165 }
bcostm 3:c6b5944187d5 166
bcostm 3:c6b5944187d5 167 /* QSPI memory reset */
bcostm 3:c6b5944187d5 168 if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)
bcostm 3:c6b5944187d5 169 {
bcostm 3:c6b5944187d5 170 return QSPI_NOT_SUPPORTED;
bcostm 3:c6b5944187d5 171 }
bcostm 3:c6b5944187d5 172
bcostm 3:c6b5944187d5 173 /* QSPI quad enable */
bcostm 3:c6b5944187d5 174 if (QSPI_QuadMode(&QSPIHandle, QSPI_QUAD_ENABLE) != QSPI_OK)
bcostm 3:c6b5944187d5 175 {
bcostm 3:c6b5944187d5 176 return QSPI_ERROR;
bcostm 3:c6b5944187d5 177 }
bcostm 3:c6b5944187d5 178
bcostm 3:c6b5944187d5 179 /* High performance mode enable */
bcostm 3:c6b5944187d5 180 if (QSPI_HighPerfMode(&QSPIHandle, QSPI_HIGH_PERF_ENABLE) != QSPI_OK)
bcostm 3:c6b5944187d5 181 {
bcostm 3:c6b5944187d5 182 return QSPI_ERROR;
bcostm 3:c6b5944187d5 183 }
bcostm 3:c6b5944187d5 184
bcostm 3:c6b5944187d5 185 /* Re-configure the clock for the high performance mode */
bcostm 3:c6b5944187d5 186 QSPIHandle.Init.ClockPrescaler = 1; /* QSPI clock = 80MHz / (ClockPrescaler+1) = 40MHz */
bcostm 3:c6b5944187d5 187
bcostm 3:c6b5944187d5 188 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
bcostm 3:c6b5944187d5 189 {
bcostm 3:c6b5944187d5 190 return QSPI_ERROR;
bcostm 3:c6b5944187d5 191 }
bcostm 3:c6b5944187d5 192
bcostm 3:c6b5944187d5 193 return QSPI_OK;
bcostm 3:c6b5944187d5 194 }
bcostm 3:c6b5944187d5 195
bcostm 3:c6b5944187d5 196 /**
bcostm 3:c6b5944187d5 197 * @brief De-Initializes the QSPI interface.
bcostm 3:c6b5944187d5 198 * @retval QSPI memory status
bcostm 3:c6b5944187d5 199 */
bcostm 3:c6b5944187d5 200 uint8_t BSP_QSPI_DeInit(void)
bcostm 3:c6b5944187d5 201 {
bcostm 3:c6b5944187d5 202 QSPIHandle.Instance = QUADSPI;
bcostm 3:c6b5944187d5 203
bcostm 3:c6b5944187d5 204 /* Call the DeInit function to reset the driver */
bcostm 3:c6b5944187d5 205 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
bcostm 3:c6b5944187d5 206 {
bcostm 3:c6b5944187d5 207 return QSPI_ERROR;
bcostm 3:c6b5944187d5 208 }
bcostm 3:c6b5944187d5 209
bcostm 3:c6b5944187d5 210 /* System level De-initialization */
bcostm 3:c6b5944187d5 211 BSP_QSPI_MspDeInit();
bcostm 3:c6b5944187d5 212
bcostm 3:c6b5944187d5 213 return QSPI_OK;
bcostm 3:c6b5944187d5 214 }
bcostm 3:c6b5944187d5 215
bcostm 3:c6b5944187d5 216 /**
bcostm 3:c6b5944187d5 217 * @brief Reads an amount of data from the QSPI memory.
bcostm 3:c6b5944187d5 218 * @param pData : Pointer to data to be read
bcostm 3:c6b5944187d5 219 * @param ReadAddr : Read start address
bcostm 3:c6b5944187d5 220 * @param Size : Size of data to read
bcostm 3:c6b5944187d5 221 * @retval QSPI memory status
bcostm 3:c6b5944187d5 222 */
bcostm 3:c6b5944187d5 223 uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
bcostm 3:c6b5944187d5 224 {
bcostm 3:c6b5944187d5 225 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 226
bcostm 3:c6b5944187d5 227 /* Initialize the read command */
bcostm 3:c6b5944187d5 228 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 229 sCommand.Instruction = QUAD_INOUT_READ_CMD;
bcostm 3:c6b5944187d5 230 sCommand.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 3:c6b5944187d5 231 sCommand.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 3:c6b5944187d5 232 sCommand.Address = ReadAddr;
bcostm 3:c6b5944187d5 233 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES;
bcostm 3:c6b5944187d5 234 sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS;
bcostm 3:c6b5944187d5 235 sCommand.AlternateBytes = MX25R6435F_ALT_BYTES_NO_PE_MODE;
bcostm 3:c6b5944187d5 236 sCommand.DataMode = QSPI_DATA_4_LINES;
bcostm 3:c6b5944187d5 237 sCommand.DummyCycles = MX25R6435F_DUMMY_CYCLES_READ_QUAD;
bcostm 3:c6b5944187d5 238 sCommand.NbData = Size;
bcostm 3:c6b5944187d5 239 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 240 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 241 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 242
bcostm 3:c6b5944187d5 243 /* Configure the command */
bcostm 3:c6b5944187d5 244 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 245 {
bcostm 3:c6b5944187d5 246 return QSPI_ERROR;
bcostm 3:c6b5944187d5 247 }
bcostm 3:c6b5944187d5 248
bcostm 3:c6b5944187d5 249 /* Reception of the data */
bcostm 3:c6b5944187d5 250 if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 251 {
bcostm 3:c6b5944187d5 252 return QSPI_ERROR;
bcostm 3:c6b5944187d5 253 }
bcostm 3:c6b5944187d5 254
bcostm 3:c6b5944187d5 255 return QSPI_OK;
bcostm 3:c6b5944187d5 256 }
bcostm 3:c6b5944187d5 257
bcostm 3:c6b5944187d5 258 /**
bcostm 3:c6b5944187d5 259 * @brief Writes an amount of data to the QSPI memory.
bcostm 3:c6b5944187d5 260 * @param pData : Pointer to data to be written
bcostm 3:c6b5944187d5 261 * @param WriteAddr : Write start address
bcostm 3:c6b5944187d5 262 * @param Size : Size of data to write
bcostm 3:c6b5944187d5 263 * @retval QSPI memory status
bcostm 3:c6b5944187d5 264 */
bcostm 3:c6b5944187d5 265 uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
bcostm 3:c6b5944187d5 266 {
bcostm 3:c6b5944187d5 267 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 268 uint32_t end_addr, current_size, current_addr;
bcostm 3:c6b5944187d5 269
bcostm 3:c6b5944187d5 270 /* Calculation of the size between the write address and the end of the page */
bcostm 3:c6b5944187d5 271 current_size = MX25R6435F_PAGE_SIZE - (WriteAddr % MX25R6435F_PAGE_SIZE);
bcostm 3:c6b5944187d5 272
bcostm 3:c6b5944187d5 273 /* Check if the size of the data is less than the remaining place in the page */
bcostm 3:c6b5944187d5 274 if (current_size > Size)
bcostm 3:c6b5944187d5 275 {
bcostm 3:c6b5944187d5 276 current_size = Size;
bcostm 3:c6b5944187d5 277 }
bcostm 3:c6b5944187d5 278
bcostm 3:c6b5944187d5 279 /* Initialize the adress variables */
bcostm 3:c6b5944187d5 280 current_addr = WriteAddr;
bcostm 3:c6b5944187d5 281 end_addr = WriteAddr + Size;
bcostm 3:c6b5944187d5 282
bcostm 3:c6b5944187d5 283 /* Initialize the program command */
bcostm 3:c6b5944187d5 284 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 285 sCommand.Instruction = QUAD_PAGE_PROG_CMD;
bcostm 3:c6b5944187d5 286 sCommand.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 3:c6b5944187d5 287 sCommand.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 3:c6b5944187d5 288 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 289 sCommand.DataMode = QSPI_DATA_4_LINES;
bcostm 3:c6b5944187d5 290 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 291 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 292 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 293 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 294
bcostm 3:c6b5944187d5 295 /* Perform the write page by page */
bcostm 3:c6b5944187d5 296 do
bcostm 3:c6b5944187d5 297 {
bcostm 3:c6b5944187d5 298 sCommand.Address = current_addr;
bcostm 3:c6b5944187d5 299 sCommand.NbData = current_size;
bcostm 3:c6b5944187d5 300
bcostm 3:c6b5944187d5 301 /* Enable write operations */
bcostm 3:c6b5944187d5 302 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 3:c6b5944187d5 303 {
bcostm 3:c6b5944187d5 304 return QSPI_ERROR;
bcostm 3:c6b5944187d5 305 }
bcostm 3:c6b5944187d5 306
bcostm 3:c6b5944187d5 307 /* Configure the command */
bcostm 3:c6b5944187d5 308 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 309 {
bcostm 3:c6b5944187d5 310 return QSPI_ERROR;
bcostm 3:c6b5944187d5 311 }
bcostm 3:c6b5944187d5 312
bcostm 3:c6b5944187d5 313 /* Transmission of the data */
bcostm 3:c6b5944187d5 314 if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 315 {
bcostm 3:c6b5944187d5 316 return QSPI_ERROR;
bcostm 3:c6b5944187d5 317 }
bcostm 3:c6b5944187d5 318
bcostm 3:c6b5944187d5 319 /* Configure automatic polling mode to wait for end of program */
bcostm 3:c6b5944187d5 320 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 3:c6b5944187d5 321 {
bcostm 3:c6b5944187d5 322 return QSPI_ERROR;
bcostm 3:c6b5944187d5 323 }
bcostm 3:c6b5944187d5 324
bcostm 3:c6b5944187d5 325 /* Update the address and size variables for next page programming */
bcostm 3:c6b5944187d5 326 current_addr += current_size;
bcostm 3:c6b5944187d5 327 pData += current_size;
bcostm 3:c6b5944187d5 328 current_size = ((current_addr + MX25R6435F_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MX25R6435F_PAGE_SIZE;
bcostm 3:c6b5944187d5 329 } while (current_addr < end_addr);
bcostm 3:c6b5944187d5 330
bcostm 3:c6b5944187d5 331 return QSPI_OK;
bcostm 3:c6b5944187d5 332 }
bcostm 3:c6b5944187d5 333
bcostm 3:c6b5944187d5 334 /**
bcostm 3:c6b5944187d5 335 * @brief Erases the specified block of the QSPI memory.
bcostm 3:c6b5944187d5 336 * @param BlockAddress : Block address to erase
bcostm 3:c6b5944187d5 337 * @retval QSPI memory status
bcostm 3:c6b5944187d5 338 */
bcostm 3:c6b5944187d5 339 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)
bcostm 3:c6b5944187d5 340 {
bcostm 3:c6b5944187d5 341 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 342
bcostm 3:c6b5944187d5 343 /* Initialize the erase command */
bcostm 3:c6b5944187d5 344 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 345 sCommand.Instruction = BLOCK_ERASE_CMD;
bcostm 3:c6b5944187d5 346 sCommand.AddressMode = QSPI_ADDRESS_1_LINE;
bcostm 3:c6b5944187d5 347 sCommand.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 3:c6b5944187d5 348 sCommand.Address = BlockAddress;
bcostm 3:c6b5944187d5 349 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 350 sCommand.DataMode = QSPI_DATA_NONE;
bcostm 3:c6b5944187d5 351 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 352 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 353 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 354 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 355
bcostm 3:c6b5944187d5 356 /* Enable write operations */
bcostm 3:c6b5944187d5 357 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 3:c6b5944187d5 358 {
bcostm 3:c6b5944187d5 359 return QSPI_ERROR;
bcostm 3:c6b5944187d5 360 }
bcostm 3:c6b5944187d5 361
bcostm 3:c6b5944187d5 362 /* Send the command */
bcostm 3:c6b5944187d5 363 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 364 {
bcostm 3:c6b5944187d5 365 return QSPI_ERROR;
bcostm 3:c6b5944187d5 366 }
bcostm 3:c6b5944187d5 367
bcostm 3:c6b5944187d5 368 /* Configure automatic polling mode to wait for end of erase */
bcostm 3:c6b5944187d5 369 if (QSPI_AutoPollingMemReady(&QSPIHandle, MX25R6435F_BLOCK_ERASE_MAX_TIME) != QSPI_OK)
bcostm 3:c6b5944187d5 370 {
bcostm 3:c6b5944187d5 371 return QSPI_ERROR;
bcostm 3:c6b5944187d5 372 }
bcostm 3:c6b5944187d5 373
bcostm 3:c6b5944187d5 374 return QSPI_OK;
bcostm 3:c6b5944187d5 375 }
bcostm 3:c6b5944187d5 376
bcostm 3:c6b5944187d5 377 /**
bcostm 3:c6b5944187d5 378 * @brief Erases the specified sector of the QSPI memory.
bcostm 3:c6b5944187d5 379 * @param Sector : Sector address to erase (0 to 255)
bcostm 3:c6b5944187d5 380 * @retval QSPI memory status
bcostm 3:c6b5944187d5 381 * @note This function is non blocking meaning that sector erase
bcostm 3:c6b5944187d5 382 * operation is started but not completed when the function
bcostm 3:c6b5944187d5 383 * returns. Application has to call BSP_QSPI_GetStatus()
bcostm 3:c6b5944187d5 384 * to know when the device is available again (i.e. erase operation
bcostm 3:c6b5944187d5 385 * completed).
bcostm 3:c6b5944187d5 386 */
bcostm 3:c6b5944187d5 387 uint8_t BSP_QSPI_Erase_Sector(uint32_t Sector)
bcostm 3:c6b5944187d5 388 {
bcostm 3:c6b5944187d5 389 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 390
bcostm 3:c6b5944187d5 391 if (Sector >= (uint32_t)(MX25R6435F_FLASH_SIZE/MX25R6435F_SECTOR_SIZE))
bcostm 3:c6b5944187d5 392 {
bcostm 3:c6b5944187d5 393 return QSPI_ERROR;
bcostm 3:c6b5944187d5 394 }
bcostm 3:c6b5944187d5 395
bcostm 3:c6b5944187d5 396 /* Initialize the erase command */
bcostm 3:c6b5944187d5 397 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 398 sCommand.Instruction = SECTOR_ERASE_CMD;
bcostm 3:c6b5944187d5 399 sCommand.AddressMode = QSPI_ADDRESS_1_LINE;
bcostm 3:c6b5944187d5 400 sCommand.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 3:c6b5944187d5 401 sCommand.Address = (Sector * MX25R6435F_SECTOR_SIZE);
bcostm 3:c6b5944187d5 402 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 403 sCommand.DataMode = QSPI_DATA_NONE;
bcostm 3:c6b5944187d5 404 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 405 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 406 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 407 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 408
bcostm 3:c6b5944187d5 409 /* Enable write operations */
bcostm 3:c6b5944187d5 410 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 3:c6b5944187d5 411 {
bcostm 3:c6b5944187d5 412 return QSPI_ERROR;
bcostm 3:c6b5944187d5 413 }
bcostm 3:c6b5944187d5 414
bcostm 3:c6b5944187d5 415 /* Send the command */
bcostm 3:c6b5944187d5 416 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 417 {
bcostm 3:c6b5944187d5 418 return QSPI_ERROR;
bcostm 3:c6b5944187d5 419 }
bcostm 3:c6b5944187d5 420
bcostm 3:c6b5944187d5 421 return QSPI_OK;
bcostm 3:c6b5944187d5 422 }
bcostm 3:c6b5944187d5 423
bcostm 3:c6b5944187d5 424 /**
bcostm 3:c6b5944187d5 425 * @brief Erases the entire QSPI memory.
bcostm 3:c6b5944187d5 426 * @retval QSPI memory status
bcostm 3:c6b5944187d5 427 */
bcostm 3:c6b5944187d5 428 uint8_t BSP_QSPI_Erase_Chip(void)
bcostm 3:c6b5944187d5 429 {
bcostm 3:c6b5944187d5 430 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 431
bcostm 3:c6b5944187d5 432 /* Initialize the erase command */
bcostm 3:c6b5944187d5 433 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 434 sCommand.Instruction = CHIP_ERASE_CMD;
bcostm 3:c6b5944187d5 435 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 436 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 437 sCommand.DataMode = QSPI_DATA_NONE;
bcostm 3:c6b5944187d5 438 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 439 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 440 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 441 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 442
bcostm 3:c6b5944187d5 443 /* Enable write operations */
bcostm 3:c6b5944187d5 444 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 3:c6b5944187d5 445 {
bcostm 3:c6b5944187d5 446 return QSPI_ERROR;
bcostm 3:c6b5944187d5 447 }
bcostm 3:c6b5944187d5 448
bcostm 3:c6b5944187d5 449 /* Send the command */
bcostm 3:c6b5944187d5 450 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 451 {
bcostm 3:c6b5944187d5 452 return QSPI_ERROR;
bcostm 3:c6b5944187d5 453 }
bcostm 3:c6b5944187d5 454
bcostm 3:c6b5944187d5 455 /* Configure automatic polling mode to wait for end of erase */
bcostm 3:c6b5944187d5 456 if (QSPI_AutoPollingMemReady(&QSPIHandle, MX25R6435F_CHIP_ERASE_MAX_TIME) != QSPI_OK)
bcostm 3:c6b5944187d5 457 {
bcostm 3:c6b5944187d5 458 return QSPI_ERROR;
bcostm 3:c6b5944187d5 459 }
bcostm 3:c6b5944187d5 460
bcostm 3:c6b5944187d5 461 return QSPI_OK;
bcostm 3:c6b5944187d5 462 }
bcostm 3:c6b5944187d5 463
bcostm 3:c6b5944187d5 464 /**
bcostm 3:c6b5944187d5 465 * @brief Reads current status of the QSPI memory.
bcostm 3:c6b5944187d5 466 * @retval QSPI memory status
bcostm 3:c6b5944187d5 467 */
bcostm 3:c6b5944187d5 468 uint8_t BSP_QSPI_GetStatus(void)
bcostm 3:c6b5944187d5 469 {
bcostm 3:c6b5944187d5 470 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 471 uint8_t reg;
bcostm 3:c6b5944187d5 472
bcostm 3:c6b5944187d5 473 /* Initialize the read security register command */
bcostm 3:c6b5944187d5 474 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 475 sCommand.Instruction = READ_SEC_REG_CMD;
bcostm 3:c6b5944187d5 476 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 477 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 478 sCommand.DataMode = QSPI_DATA_1_LINE;
bcostm 3:c6b5944187d5 479 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 480 sCommand.NbData = 1;
bcostm 3:c6b5944187d5 481 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 482 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 483 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 484
bcostm 3:c6b5944187d5 485 /* Configure the command */
bcostm 3:c6b5944187d5 486 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 487 {
bcostm 3:c6b5944187d5 488 return QSPI_ERROR;
bcostm 3:c6b5944187d5 489 }
bcostm 3:c6b5944187d5 490
bcostm 3:c6b5944187d5 491 /* Reception of the data */
bcostm 3:c6b5944187d5 492 if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 493 {
bcostm 3:c6b5944187d5 494 return QSPI_ERROR;
bcostm 3:c6b5944187d5 495 }
bcostm 3:c6b5944187d5 496
bcostm 3:c6b5944187d5 497 /* Check the value of the register */
bcostm 3:c6b5944187d5 498 if ((reg & (MX25R6435F_SECR_P_FAIL | MX25R6435F_SECR_E_FAIL)) != 0)
bcostm 3:c6b5944187d5 499 {
bcostm 3:c6b5944187d5 500 return QSPI_ERROR;
bcostm 3:c6b5944187d5 501 }
bcostm 3:c6b5944187d5 502 else if ((reg & (MX25R6435F_SECR_PSB | MX25R6435F_SECR_ESB)) != 0)
bcostm 3:c6b5944187d5 503 {
bcostm 3:c6b5944187d5 504 return QSPI_SUSPENDED;
bcostm 3:c6b5944187d5 505 }
bcostm 3:c6b5944187d5 506
bcostm 3:c6b5944187d5 507 /* Initialize the read status register command */
bcostm 3:c6b5944187d5 508 sCommand.Instruction = READ_STATUS_REG_CMD;
bcostm 3:c6b5944187d5 509
bcostm 3:c6b5944187d5 510 /* Configure the command */
bcostm 3:c6b5944187d5 511 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 512 {
bcostm 3:c6b5944187d5 513 return QSPI_ERROR;
bcostm 3:c6b5944187d5 514 }
bcostm 3:c6b5944187d5 515
bcostm 3:c6b5944187d5 516 /* Reception of the data */
bcostm 3:c6b5944187d5 517 if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 518 {
bcostm 3:c6b5944187d5 519 return QSPI_ERROR;
bcostm 3:c6b5944187d5 520 }
bcostm 3:c6b5944187d5 521
bcostm 3:c6b5944187d5 522 /* Check the value of the register */
bcostm 3:c6b5944187d5 523 if ((reg & MX25R6435F_SR_WIP) != 0)
bcostm 3:c6b5944187d5 524 {
bcostm 3:c6b5944187d5 525 return QSPI_BUSY;
bcostm 3:c6b5944187d5 526 }
bcostm 3:c6b5944187d5 527 else
bcostm 3:c6b5944187d5 528 {
bcostm 3:c6b5944187d5 529 return QSPI_OK;
bcostm 3:c6b5944187d5 530 }
bcostm 3:c6b5944187d5 531 }
bcostm 3:c6b5944187d5 532
bcostm 3:c6b5944187d5 533 /**
bcostm 3:c6b5944187d5 534 * @brief Return the configuration of the QSPI memory.
bcostm 3:c6b5944187d5 535 * @param pInfo : pointer on the configuration structure
bcostm 3:c6b5944187d5 536 * @retval QSPI memory status
bcostm 3:c6b5944187d5 537 */
bcostm 3:c6b5944187d5 538 uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo)
bcostm 3:c6b5944187d5 539 {
bcostm 3:c6b5944187d5 540 /* Configure the structure with the memory configuration */
bcostm 3:c6b5944187d5 541 pInfo->FlashSize = MX25R6435F_FLASH_SIZE;
bcostm 3:c6b5944187d5 542 pInfo->EraseSectorSize = MX25R6435F_SECTOR_SIZE;
bcostm 3:c6b5944187d5 543 pInfo->EraseSectorsNumber = (MX25R6435F_FLASH_SIZE/MX25R6435F_SECTOR_SIZE);
bcostm 3:c6b5944187d5 544 pInfo->ProgPageSize = MX25R6435F_PAGE_SIZE;
bcostm 3:c6b5944187d5 545 pInfo->ProgPagesNumber = (MX25R6435F_FLASH_SIZE/MX25R6435F_PAGE_SIZE);
bcostm 3:c6b5944187d5 546
bcostm 3:c6b5944187d5 547 return QSPI_OK;
bcostm 3:c6b5944187d5 548 }
bcostm 3:c6b5944187d5 549
bcostm 3:c6b5944187d5 550 /**
bcostm 3:c6b5944187d5 551 * @brief Configure the QSPI in memory-mapped mode
bcostm 3:c6b5944187d5 552 * @retval QSPI memory status
bcostm 3:c6b5944187d5 553 */
bcostm 3:c6b5944187d5 554 uint8_t BSP_QSPI_EnableMemoryMappedMode(void)
bcostm 3:c6b5944187d5 555 {
bcostm 3:c6b5944187d5 556 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 557 QSPI_MemoryMappedTypeDef sMemMappedCfg;
bcostm 3:c6b5944187d5 558
bcostm 3:c6b5944187d5 559 /* Configure the command for the read instruction */
bcostm 3:c6b5944187d5 560 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 561 sCommand.Instruction = QUAD_INOUT_READ_CMD;
bcostm 3:c6b5944187d5 562 sCommand.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 3:c6b5944187d5 563 sCommand.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 3:c6b5944187d5 564 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES;
bcostm 3:c6b5944187d5 565 sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS;
bcostm 3:c6b5944187d5 566 sCommand.AlternateBytes = MX25R6435F_ALT_BYTES_NO_PE_MODE;
bcostm 3:c6b5944187d5 567 sCommand.DataMode = QSPI_DATA_4_LINES;
bcostm 3:c6b5944187d5 568 sCommand.DummyCycles = MX25R6435F_DUMMY_CYCLES_READ_QUAD;
bcostm 3:c6b5944187d5 569 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 570 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 571 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 572
bcostm 3:c6b5944187d5 573 /* Configure the memory mapped mode */
bcostm 3:c6b5944187d5 574 sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
bcostm 3:c6b5944187d5 575
bcostm 3:c6b5944187d5 576 if (HAL_QSPI_MemoryMapped(&QSPIHandle, &sCommand, &sMemMappedCfg) != HAL_OK)
bcostm 3:c6b5944187d5 577 {
bcostm 3:c6b5944187d5 578 return QSPI_ERROR;
bcostm 3:c6b5944187d5 579 }
bcostm 3:c6b5944187d5 580
bcostm 3:c6b5944187d5 581 return QSPI_OK;
bcostm 3:c6b5944187d5 582 }
bcostm 3:c6b5944187d5 583
bcostm 3:c6b5944187d5 584 /**
bcostm 3:c6b5944187d5 585 * @brief This function suspends an ongoing erase command.
bcostm 3:c6b5944187d5 586 * @retval QSPI memory status
bcostm 3:c6b5944187d5 587 */
bcostm 3:c6b5944187d5 588 uint8_t BSP_QSPI_SuspendErase(void)
bcostm 3:c6b5944187d5 589 {
bcostm 3:c6b5944187d5 590 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 591
bcostm 3:c6b5944187d5 592 /* Check whether the device is busy (erase operation is
bcostm 3:c6b5944187d5 593 in progress).
bcostm 3:c6b5944187d5 594 */
bcostm 3:c6b5944187d5 595 if (BSP_QSPI_GetStatus() == QSPI_BUSY)
bcostm 3:c6b5944187d5 596 {
bcostm 3:c6b5944187d5 597 /* Initialize the erase command */
bcostm 3:c6b5944187d5 598 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 599 sCommand.Instruction = PROG_ERASE_SUSPEND_CMD;
bcostm 3:c6b5944187d5 600 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 601 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 602 sCommand.DataMode = QSPI_DATA_NONE;
bcostm 3:c6b5944187d5 603 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 604 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 605 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 606 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 607
bcostm 3:c6b5944187d5 608 /* Send the command */
bcostm 3:c6b5944187d5 609 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 610 {
bcostm 3:c6b5944187d5 611 return QSPI_ERROR;
bcostm 3:c6b5944187d5 612 }
bcostm 3:c6b5944187d5 613
bcostm 3:c6b5944187d5 614 if (BSP_QSPI_GetStatus() == QSPI_SUSPENDED)
bcostm 3:c6b5944187d5 615 {
bcostm 3:c6b5944187d5 616 return QSPI_OK;
bcostm 3:c6b5944187d5 617 }
bcostm 3:c6b5944187d5 618
bcostm 3:c6b5944187d5 619 return QSPI_ERROR;
bcostm 3:c6b5944187d5 620 }
bcostm 3:c6b5944187d5 621
bcostm 3:c6b5944187d5 622 return QSPI_OK;
bcostm 3:c6b5944187d5 623 }
bcostm 3:c6b5944187d5 624
bcostm 3:c6b5944187d5 625 /**
bcostm 3:c6b5944187d5 626 * @brief This function resumes a paused erase command.
bcostm 3:c6b5944187d5 627 * @retval QSPI memory status
bcostm 3:c6b5944187d5 628 */
bcostm 3:c6b5944187d5 629 uint8_t BSP_QSPI_ResumeErase(void)
bcostm 3:c6b5944187d5 630 {
bcostm 3:c6b5944187d5 631 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 632
bcostm 3:c6b5944187d5 633 /* Check whether the device is in suspended state */
bcostm 3:c6b5944187d5 634 if (BSP_QSPI_GetStatus() == QSPI_SUSPENDED)
bcostm 3:c6b5944187d5 635 {
bcostm 3:c6b5944187d5 636 /* Initialize the erase command */
bcostm 3:c6b5944187d5 637 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 638 sCommand.Instruction = PROG_ERASE_RESUME_CMD;
bcostm 3:c6b5944187d5 639 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 640 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 641 sCommand.DataMode = QSPI_DATA_NONE;
bcostm 3:c6b5944187d5 642 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 643 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 644 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 645 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 646
bcostm 3:c6b5944187d5 647 /* Send the command */
bcostm 3:c6b5944187d5 648 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 649 {
bcostm 3:c6b5944187d5 650 return QSPI_ERROR;
bcostm 3:c6b5944187d5 651 }
bcostm 3:c6b5944187d5 652
bcostm 3:c6b5944187d5 653 /*
bcostm 3:c6b5944187d5 654 When this command is executed, the status register write in progress bit is set to 1, and
bcostm 3:c6b5944187d5 655 the flag status register program erase controller bit is set to 0. This command is ignored
bcostm 3:c6b5944187d5 656 if the device is not in a suspended state.
bcostm 3:c6b5944187d5 657 */
bcostm 3:c6b5944187d5 658
bcostm 3:c6b5944187d5 659 if (BSP_QSPI_GetStatus() == QSPI_BUSY)
bcostm 3:c6b5944187d5 660 {
bcostm 3:c6b5944187d5 661 return QSPI_OK;
bcostm 3:c6b5944187d5 662 }
bcostm 3:c6b5944187d5 663
bcostm 3:c6b5944187d5 664 return QSPI_ERROR;
bcostm 3:c6b5944187d5 665 }
bcostm 3:c6b5944187d5 666
bcostm 3:c6b5944187d5 667 return QSPI_OK;
bcostm 3:c6b5944187d5 668 }
bcostm 3:c6b5944187d5 669
bcostm 3:c6b5944187d5 670 /**
bcostm 3:c6b5944187d5 671 * @brief This function enter the QSPI memory in deep power down mode.
bcostm 3:c6b5944187d5 672 * @retval QSPI memory status
bcostm 3:c6b5944187d5 673 */
bcostm 3:c6b5944187d5 674 uint8_t BSP_QSPI_EnterDeepPowerDown(void)
bcostm 3:c6b5944187d5 675 {
bcostm 3:c6b5944187d5 676 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 677
bcostm 3:c6b5944187d5 678 /* Initialize the deep power down command */
bcostm 3:c6b5944187d5 679 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 680 sCommand.Instruction = DEEP_POWER_DOWN_CMD;
bcostm 3:c6b5944187d5 681 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 682 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 683 sCommand.DataMode = QSPI_DATA_NONE;
bcostm 3:c6b5944187d5 684 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 685 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 686 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 687 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 688
bcostm 3:c6b5944187d5 689 /* Send the command */
bcostm 3:c6b5944187d5 690 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 691 {
bcostm 3:c6b5944187d5 692 return QSPI_ERROR;
bcostm 3:c6b5944187d5 693 }
bcostm 3:c6b5944187d5 694
bcostm 3:c6b5944187d5 695 /* --- Memory takes 10us max to enter deep power down --- */
bcostm 3:c6b5944187d5 696 /* --- At least 30us should be respected before leaving deep power down --- */
bcostm 3:c6b5944187d5 697
bcostm 3:c6b5944187d5 698 return QSPI_OK;
bcostm 3:c6b5944187d5 699 }
bcostm 3:c6b5944187d5 700
bcostm 3:c6b5944187d5 701 /**
bcostm 3:c6b5944187d5 702 * @brief This function leave the QSPI memory from deep power down mode.
bcostm 3:c6b5944187d5 703 * @retval QSPI memory status
bcostm 3:c6b5944187d5 704 */
bcostm 3:c6b5944187d5 705 uint8_t BSP_QSPI_LeaveDeepPowerDown(void)
bcostm 3:c6b5944187d5 706 {
bcostm 3:c6b5944187d5 707 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 708
bcostm 3:c6b5944187d5 709 /* Initialize the erase command */
bcostm 3:c6b5944187d5 710 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 711 sCommand.Instruction = NO_OPERATION_CMD;
bcostm 3:c6b5944187d5 712 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 713 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 714 sCommand.DataMode = QSPI_DATA_NONE;
bcostm 3:c6b5944187d5 715 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 716 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 717 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 718 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 719
bcostm 3:c6b5944187d5 720 /* Send the command */
bcostm 3:c6b5944187d5 721 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 722 {
bcostm 3:c6b5944187d5 723 return QSPI_ERROR;
bcostm 3:c6b5944187d5 724 }
bcostm 3:c6b5944187d5 725
bcostm 3:c6b5944187d5 726 /* --- A NOP command is sent to the memory, as the nCS should be low for at least 20 ns --- */
bcostm 3:c6b5944187d5 727 /* --- Memory takes 35us min to leave deep power down --- */
bcostm 3:c6b5944187d5 728
bcostm 3:c6b5944187d5 729 return QSPI_OK;
bcostm 3:c6b5944187d5 730 }
bcostm 3:c6b5944187d5 731
bcostm 3:c6b5944187d5 732 /**
bcostm 3:c6b5944187d5 733 * @brief Initializes the QSPI MSP.
bcostm 3:c6b5944187d5 734 * @retval None
bcostm 3:c6b5944187d5 735 */
bcostm 3:c6b5944187d5 736 __weak void BSP_QSPI_MspInit(void)
bcostm 3:c6b5944187d5 737 {
bcostm 3:c6b5944187d5 738 GPIO_InitTypeDef GPIO_InitStruct;
bcostm 3:c6b5944187d5 739
bcostm 3:c6b5944187d5 740 /* Enable the QuadSPI memory interface clock */
bcostm 3:c6b5944187d5 741 __HAL_RCC_QSPI_CLK_ENABLE();
bcostm 3:c6b5944187d5 742
bcostm 3:c6b5944187d5 743 /* Reset the QuadSPI memory interface */
bcostm 3:c6b5944187d5 744 __HAL_RCC_QSPI_FORCE_RESET();
bcostm 3:c6b5944187d5 745 __HAL_RCC_QSPI_RELEASE_RESET();
bcostm 3:c6b5944187d5 746
bcostm 3:c6b5944187d5 747 /* Enable GPIO clocks */
bcostm 3:c6b5944187d5 748 __HAL_RCC_GPIOE_CLK_ENABLE();
bcostm 3:c6b5944187d5 749
bcostm 3:c6b5944187d5 750 /* QSPI CLK, CS, D0, D1, D2 and D3 GPIO pins configuration */
bcostm 3:c6b5944187d5 751 GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\
bcostm 3:c6b5944187d5 752 GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
bcostm 3:c6b5944187d5 753 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
bcostm 3:c6b5944187d5 754 GPIO_InitStruct.Pull = GPIO_NOPULL;
bcostm 3:c6b5944187d5 755 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
bcostm 3:c6b5944187d5 756 GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
bcostm 3:c6b5944187d5 757 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
bcostm 3:c6b5944187d5 758 }
bcostm 3:c6b5944187d5 759
bcostm 3:c6b5944187d5 760 /**
bcostm 3:c6b5944187d5 761 * @brief De-Initializes the QSPI MSP.
bcostm 3:c6b5944187d5 762 * @retval None
bcostm 3:c6b5944187d5 763 */
bcostm 3:c6b5944187d5 764 __weak void BSP_QSPI_MspDeInit(void)
bcostm 3:c6b5944187d5 765 {
bcostm 3:c6b5944187d5 766 GPIO_InitTypeDef GPIO_InitStruct;
bcostm 3:c6b5944187d5 767
bcostm 3:c6b5944187d5 768 /* QSPI CLK, CS, D0-D3 GPIO pins de-configuration */
bcostm 3:c6b5944187d5 769 __HAL_RCC_GPIOE_CLK_ENABLE();
bcostm 3:c6b5944187d5 770 GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\
bcostm 3:c6b5944187d5 771 GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
bcostm 3:c6b5944187d5 772
bcostm 3:c6b5944187d5 773 HAL_GPIO_DeInit(GPIOE, GPIO_InitStruct.Pin);
bcostm 3:c6b5944187d5 774
bcostm 3:c6b5944187d5 775 /* Reset the QuadSPI memory interface */
bcostm 3:c6b5944187d5 776 __HAL_RCC_QSPI_FORCE_RESET();
bcostm 3:c6b5944187d5 777 __HAL_RCC_QSPI_RELEASE_RESET();
bcostm 3:c6b5944187d5 778
bcostm 3:c6b5944187d5 779 /* Disable the QuadSPI memory interface clock */
bcostm 3:c6b5944187d5 780 __HAL_RCC_QSPI_CLK_DISABLE();
bcostm 3:c6b5944187d5 781 }
bcostm 3:c6b5944187d5 782
bcostm 3:c6b5944187d5 783 /**
bcostm 3:c6b5944187d5 784 * @}
bcostm 3:c6b5944187d5 785 */
bcostm 3:c6b5944187d5 786
bcostm 3:c6b5944187d5 787 /** @addtogroup STM32L475E_IOT01_QSPI_Private_Functions
bcostm 3:c6b5944187d5 788 * @{
bcostm 3:c6b5944187d5 789 */
bcostm 3:c6b5944187d5 790
bcostm 3:c6b5944187d5 791 /**
bcostm 3:c6b5944187d5 792 * @brief This function reset the QSPI memory.
bcostm 3:c6b5944187d5 793 * @param hqspi : QSPI handle
bcostm 3:c6b5944187d5 794 * @retval None
bcostm 3:c6b5944187d5 795 */
bcostm 3:c6b5944187d5 796 static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)
bcostm 3:c6b5944187d5 797 {
bcostm 3:c6b5944187d5 798 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 799
bcostm 3:c6b5944187d5 800 /* Initialize the reset enable command */
bcostm 3:c6b5944187d5 801 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 802 sCommand.Instruction = RESET_ENABLE_CMD;
bcostm 3:c6b5944187d5 803 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 804 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 805 sCommand.DataMode = QSPI_DATA_NONE;
bcostm 3:c6b5944187d5 806 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 807 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 808 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 809 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 810
bcostm 3:c6b5944187d5 811 /* Send the command */
bcostm 3:c6b5944187d5 812 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 813 {
bcostm 3:c6b5944187d5 814 return QSPI_ERROR;
bcostm 3:c6b5944187d5 815 }
bcostm 3:c6b5944187d5 816
bcostm 3:c6b5944187d5 817 /* Send the reset memory command */
bcostm 3:c6b5944187d5 818 sCommand.Instruction = RESET_MEMORY_CMD;
bcostm 3:c6b5944187d5 819 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 820 {
bcostm 3:c6b5944187d5 821 return QSPI_ERROR;
bcostm 3:c6b5944187d5 822 }
bcostm 3:c6b5944187d5 823
bcostm 3:c6b5944187d5 824 /* Configure automatic polling mode to wait the memory is ready */
bcostm 3:c6b5944187d5 825 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 3:c6b5944187d5 826 {
bcostm 3:c6b5944187d5 827 return QSPI_ERROR;
bcostm 3:c6b5944187d5 828 }
bcostm 3:c6b5944187d5 829
bcostm 3:c6b5944187d5 830 return QSPI_OK;
bcostm 3:c6b5944187d5 831 }
bcostm 3:c6b5944187d5 832
bcostm 3:c6b5944187d5 833 /**
bcostm 3:c6b5944187d5 834 * @brief This function send a Write Enable and wait it is effective.
bcostm 3:c6b5944187d5 835 * @param hqspi : QSPI handle
bcostm 3:c6b5944187d5 836 * @retval None
bcostm 3:c6b5944187d5 837 */
bcostm 3:c6b5944187d5 838 static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
bcostm 3:c6b5944187d5 839 {
bcostm 3:c6b5944187d5 840 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 841 QSPI_AutoPollingTypeDef sConfig;
bcostm 3:c6b5944187d5 842
bcostm 3:c6b5944187d5 843 /* Enable write operations */
bcostm 3:c6b5944187d5 844 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 845 sCommand.Instruction = WRITE_ENABLE_CMD;
bcostm 3:c6b5944187d5 846 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 847 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 848 sCommand.DataMode = QSPI_DATA_NONE;
bcostm 3:c6b5944187d5 849 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 850 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 851 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 852 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 853
bcostm 3:c6b5944187d5 854 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 855 {
bcostm 3:c6b5944187d5 856 return QSPI_ERROR;
bcostm 3:c6b5944187d5 857 }
bcostm 3:c6b5944187d5 858
bcostm 3:c6b5944187d5 859 /* Configure automatic polling mode to wait for write enabling */
bcostm 3:c6b5944187d5 860 sConfig.Match = MX25R6435F_SR_WEL;
bcostm 3:c6b5944187d5 861 sConfig.Mask = MX25R6435F_SR_WEL;
bcostm 3:c6b5944187d5 862 sConfig.MatchMode = QSPI_MATCH_MODE_AND;
bcostm 3:c6b5944187d5 863 sConfig.StatusBytesSize = 1;
bcostm 3:c6b5944187d5 864 sConfig.Interval = 0x10;
bcostm 3:c6b5944187d5 865 sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
bcostm 3:c6b5944187d5 866
bcostm 3:c6b5944187d5 867 sCommand.Instruction = READ_STATUS_REG_CMD;
bcostm 3:c6b5944187d5 868 sCommand.DataMode = QSPI_DATA_1_LINE;
bcostm 3:c6b5944187d5 869
bcostm 3:c6b5944187d5 870 if (HAL_QSPI_AutoPolling(&QSPIHandle, &sCommand, &sConfig, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 871 {
bcostm 3:c6b5944187d5 872 return QSPI_ERROR;
bcostm 3:c6b5944187d5 873 }
bcostm 3:c6b5944187d5 874
bcostm 3:c6b5944187d5 875 return QSPI_OK;
bcostm 3:c6b5944187d5 876 }
bcostm 3:c6b5944187d5 877
bcostm 3:c6b5944187d5 878 /**
bcostm 3:c6b5944187d5 879 * @brief This function read the SR of the memory and wait the EOP.
bcostm 3:c6b5944187d5 880 * @param hqspi : QSPI handle
bcostm 3:c6b5944187d5 881 * @param Timeout : Timeout for auto-polling
bcostm 3:c6b5944187d5 882 * @retval None
bcostm 3:c6b5944187d5 883 */
bcostm 3:c6b5944187d5 884 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
bcostm 3:c6b5944187d5 885 {
bcostm 3:c6b5944187d5 886 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 887 QSPI_AutoPollingTypeDef sConfig;
bcostm 3:c6b5944187d5 888
bcostm 3:c6b5944187d5 889 /* Configure automatic polling mode to wait for memory ready */
bcostm 3:c6b5944187d5 890 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 891 sCommand.Instruction = READ_STATUS_REG_CMD;
bcostm 3:c6b5944187d5 892 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 893 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 894 sCommand.DataMode = QSPI_DATA_1_LINE;
bcostm 3:c6b5944187d5 895 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 896 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 897 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 898 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 899
bcostm 3:c6b5944187d5 900 sConfig.Match = 0;
bcostm 3:c6b5944187d5 901 sConfig.Mask = MX25R6435F_SR_WIP;
bcostm 3:c6b5944187d5 902 sConfig.MatchMode = QSPI_MATCH_MODE_AND;
bcostm 3:c6b5944187d5 903 sConfig.StatusBytesSize = 1;
bcostm 3:c6b5944187d5 904 sConfig.Interval = 0x10;
bcostm 3:c6b5944187d5 905 sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
bcostm 3:c6b5944187d5 906
bcostm 3:c6b5944187d5 907 if (HAL_QSPI_AutoPolling(&QSPIHandle, &sCommand, &sConfig, Timeout) != HAL_OK)
bcostm 3:c6b5944187d5 908 {
bcostm 3:c6b5944187d5 909 return QSPI_ERROR;
bcostm 3:c6b5944187d5 910 }
bcostm 3:c6b5944187d5 911
bcostm 3:c6b5944187d5 912 return QSPI_OK;
bcostm 3:c6b5944187d5 913 }
bcostm 3:c6b5944187d5 914
bcostm 3:c6b5944187d5 915 /**
bcostm 3:c6b5944187d5 916 * @brief This function enables/disables the Quad mode of the memory.
bcostm 3:c6b5944187d5 917 * @param hqspi : QSPI handle
bcostm 3:c6b5944187d5 918 * @param Operation : QSPI_QUAD_ENABLE or QSPI_QUAD_DISABLE mode
bcostm 3:c6b5944187d5 919 * @retval None
bcostm 3:c6b5944187d5 920 */
bcostm 3:c6b5944187d5 921 static uint8_t QSPI_QuadMode(QSPI_HandleTypeDef *hqspi, uint8_t Operation)
bcostm 3:c6b5944187d5 922 {
bcostm 3:c6b5944187d5 923 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 924 uint8_t reg;
bcostm 3:c6b5944187d5 925
bcostm 3:c6b5944187d5 926 /* Read status register */
bcostm 3:c6b5944187d5 927 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 928 sCommand.Instruction = READ_STATUS_REG_CMD;
bcostm 3:c6b5944187d5 929 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 930 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 931 sCommand.DataMode = QSPI_DATA_1_LINE;
bcostm 3:c6b5944187d5 932 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 933 sCommand.NbData = 1;
bcostm 3:c6b5944187d5 934 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 935 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 936 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 937
bcostm 3:c6b5944187d5 938 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 939 {
bcostm 3:c6b5944187d5 940 return QSPI_ERROR;
bcostm 3:c6b5944187d5 941 }
bcostm 3:c6b5944187d5 942
bcostm 3:c6b5944187d5 943 if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 944 {
bcostm 3:c6b5944187d5 945 return QSPI_ERROR;
bcostm 3:c6b5944187d5 946 }
bcostm 3:c6b5944187d5 947
bcostm 3:c6b5944187d5 948 /* Enable write operations */
bcostm 3:c6b5944187d5 949 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 3:c6b5944187d5 950 {
bcostm 3:c6b5944187d5 951 return QSPI_ERROR;
bcostm 3:c6b5944187d5 952 }
bcostm 3:c6b5944187d5 953
bcostm 3:c6b5944187d5 954 /* Activate/deactivate the Quad mode */
bcostm 3:c6b5944187d5 955 if (Operation == QSPI_QUAD_ENABLE)
bcostm 3:c6b5944187d5 956 {
bcostm 3:c6b5944187d5 957 SET_BIT(reg, MX25R6435F_SR_QE);
bcostm 3:c6b5944187d5 958 }
bcostm 3:c6b5944187d5 959 else
bcostm 3:c6b5944187d5 960 {
bcostm 3:c6b5944187d5 961 CLEAR_BIT(reg, MX25R6435F_SR_QE);
bcostm 3:c6b5944187d5 962 }
bcostm 3:c6b5944187d5 963
bcostm 3:c6b5944187d5 964 sCommand.Instruction = WRITE_STATUS_CFG_REG_CMD;
bcostm 3:c6b5944187d5 965
bcostm 3:c6b5944187d5 966 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 967 {
bcostm 3:c6b5944187d5 968 return QSPI_ERROR;
bcostm 3:c6b5944187d5 969 }
bcostm 3:c6b5944187d5 970
bcostm 3:c6b5944187d5 971 if (HAL_QSPI_Transmit(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 972 {
bcostm 3:c6b5944187d5 973 return QSPI_ERROR;
bcostm 3:c6b5944187d5 974 }
bcostm 3:c6b5944187d5 975
bcostm 3:c6b5944187d5 976 /* Wait that memory is ready */
bcostm 3:c6b5944187d5 977 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 3:c6b5944187d5 978 {
bcostm 3:c6b5944187d5 979 return QSPI_ERROR;
bcostm 3:c6b5944187d5 980 }
bcostm 3:c6b5944187d5 981
bcostm 3:c6b5944187d5 982 /* Check the configuration has been correctly done */
bcostm 3:c6b5944187d5 983 sCommand.Instruction = READ_STATUS_REG_CMD;
bcostm 3:c6b5944187d5 984
bcostm 3:c6b5944187d5 985 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 986 {
bcostm 3:c6b5944187d5 987 return QSPI_ERROR;
bcostm 3:c6b5944187d5 988 }
bcostm 3:c6b5944187d5 989
bcostm 3:c6b5944187d5 990 if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 991 {
bcostm 3:c6b5944187d5 992 return QSPI_ERROR;
bcostm 3:c6b5944187d5 993 }
bcostm 3:c6b5944187d5 994
bcostm 3:c6b5944187d5 995 if ((((reg & MX25R6435F_SR_QE) == 0) && (Operation == QSPI_QUAD_ENABLE)) ||
bcostm 3:c6b5944187d5 996 (((reg & MX25R6435F_SR_QE) != 0) && (Operation == QSPI_QUAD_DISABLE)))
bcostm 3:c6b5944187d5 997 {
bcostm 3:c6b5944187d5 998 return QSPI_ERROR;
bcostm 3:c6b5944187d5 999 }
bcostm 3:c6b5944187d5 1000
bcostm 3:c6b5944187d5 1001 return QSPI_OK;
bcostm 3:c6b5944187d5 1002 }
bcostm 3:c6b5944187d5 1003
bcostm 3:c6b5944187d5 1004 /**
bcostm 3:c6b5944187d5 1005 * @brief This function enables/disables the high performance mode of the memory.
bcostm 3:c6b5944187d5 1006 * @param hqspi : QSPI handle
bcostm 3:c6b5944187d5 1007 * @param Operation : QSPI_HIGH_PERF_ENABLE or QSPI_HIGH_PERF_DISABLE high performance mode
bcostm 3:c6b5944187d5 1008 * @retval None
bcostm 3:c6b5944187d5 1009 */
bcostm 3:c6b5944187d5 1010 static uint8_t QSPI_HighPerfMode(QSPI_HandleTypeDef *hqspi, uint8_t Operation)
bcostm 3:c6b5944187d5 1011 {
bcostm 3:c6b5944187d5 1012 QSPI_CommandTypeDef sCommand;
bcostm 3:c6b5944187d5 1013 uint8_t reg[3];
bcostm 3:c6b5944187d5 1014
bcostm 3:c6b5944187d5 1015 /* Read status register */
bcostm 3:c6b5944187d5 1016 sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 3:c6b5944187d5 1017 sCommand.Instruction = READ_STATUS_REG_CMD;
bcostm 3:c6b5944187d5 1018 sCommand.AddressMode = QSPI_ADDRESS_NONE;
bcostm 3:c6b5944187d5 1019 sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 3:c6b5944187d5 1020 sCommand.DataMode = QSPI_DATA_1_LINE;
bcostm 3:c6b5944187d5 1021 sCommand.DummyCycles = 0;
bcostm 3:c6b5944187d5 1022 sCommand.NbData = 1;
bcostm 3:c6b5944187d5 1023 sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 3:c6b5944187d5 1024 sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 3:c6b5944187d5 1025 sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 3:c6b5944187d5 1026
bcostm 3:c6b5944187d5 1027 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 1028 {
bcostm 3:c6b5944187d5 1029 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1030 }
bcostm 3:c6b5944187d5 1031
bcostm 3:c6b5944187d5 1032 if (HAL_QSPI_Receive(&QSPIHandle, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 1033 {
bcostm 3:c6b5944187d5 1034 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1035 }
bcostm 3:c6b5944187d5 1036
bcostm 3:c6b5944187d5 1037 /* Read configuration registers */
bcostm 3:c6b5944187d5 1038 sCommand.Instruction = READ_CFG_REG_CMD;
bcostm 3:c6b5944187d5 1039 sCommand.NbData = 2;
bcostm 3:c6b5944187d5 1040
bcostm 3:c6b5944187d5 1041 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 1042 {
bcostm 3:c6b5944187d5 1043 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1044 }
bcostm 3:c6b5944187d5 1045
bcostm 3:c6b5944187d5 1046 if (HAL_QSPI_Receive(&QSPIHandle, &(reg[1]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 1047 {
bcostm 3:c6b5944187d5 1048 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1049 }
bcostm 3:c6b5944187d5 1050
bcostm 3:c6b5944187d5 1051 /* Enable write operations */
bcostm 3:c6b5944187d5 1052 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 3:c6b5944187d5 1053 {
bcostm 3:c6b5944187d5 1054 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1055 }
bcostm 3:c6b5944187d5 1056
bcostm 3:c6b5944187d5 1057 /* Activate/deactivate the Quad mode */
bcostm 3:c6b5944187d5 1058 if (Operation == QSPI_HIGH_PERF_ENABLE)
bcostm 3:c6b5944187d5 1059 {
bcostm 3:c6b5944187d5 1060 SET_BIT(reg[2], MX25R6435F_CR2_LH_SWITCH);
bcostm 3:c6b5944187d5 1061 }
bcostm 3:c6b5944187d5 1062 else
bcostm 3:c6b5944187d5 1063 {
bcostm 3:c6b5944187d5 1064 CLEAR_BIT(reg[2], MX25R6435F_CR2_LH_SWITCH);
bcostm 3:c6b5944187d5 1065 }
bcostm 3:c6b5944187d5 1066
bcostm 3:c6b5944187d5 1067 sCommand.Instruction = WRITE_STATUS_CFG_REG_CMD;
bcostm 3:c6b5944187d5 1068 sCommand.NbData = 3;
bcostm 3:c6b5944187d5 1069
bcostm 3:c6b5944187d5 1070 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 1071 {
bcostm 3:c6b5944187d5 1072 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1073 }
bcostm 3:c6b5944187d5 1074
bcostm 3:c6b5944187d5 1075 if (HAL_QSPI_Transmit(&QSPIHandle, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 1076 {
bcostm 3:c6b5944187d5 1077 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1078 }
bcostm 3:c6b5944187d5 1079
bcostm 3:c6b5944187d5 1080 /* Wait that memory is ready */
bcostm 3:c6b5944187d5 1081 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 3:c6b5944187d5 1082 {
bcostm 3:c6b5944187d5 1083 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1084 }
bcostm 3:c6b5944187d5 1085
bcostm 3:c6b5944187d5 1086 /* Check the configuration has been correctly done */
bcostm 3:c6b5944187d5 1087 sCommand.Instruction = READ_CFG_REG_CMD;
bcostm 3:c6b5944187d5 1088 sCommand.NbData = 2;
bcostm 3:c6b5944187d5 1089
bcostm 3:c6b5944187d5 1090 if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 1091 {
bcostm 3:c6b5944187d5 1092 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1093 }
bcostm 3:c6b5944187d5 1094
bcostm 3:c6b5944187d5 1095 if (HAL_QSPI_Receive(&QSPIHandle, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 3:c6b5944187d5 1096 {
bcostm 3:c6b5944187d5 1097 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1098 }
bcostm 3:c6b5944187d5 1099
bcostm 3:c6b5944187d5 1100 if ((((reg[1] & MX25R6435F_CR2_LH_SWITCH) == 0) && (Operation == QSPI_HIGH_PERF_ENABLE)) ||
bcostm 3:c6b5944187d5 1101 (((reg[1] & MX25R6435F_CR2_LH_SWITCH) != 0) && (Operation == QSPI_HIGH_PERF_DISABLE)))
bcostm 3:c6b5944187d5 1102 {
bcostm 3:c6b5944187d5 1103 return QSPI_ERROR;
bcostm 3:c6b5944187d5 1104 }
bcostm 3:c6b5944187d5 1105
bcostm 3:c6b5944187d5 1106 return QSPI_OK;
bcostm 3:c6b5944187d5 1107 }
bcostm 3:c6b5944187d5 1108
bcostm 3:c6b5944187d5 1109 /**
bcostm 3:c6b5944187d5 1110 * @}
bcostm 3:c6b5944187d5 1111 */
bcostm 3:c6b5944187d5 1112
bcostm 3:c6b5944187d5 1113 /**
bcostm 3:c6b5944187d5 1114 * @}
bcostm 3:c6b5944187d5 1115 */
bcostm 3:c6b5944187d5 1116
bcostm 3:c6b5944187d5 1117 /**
bcostm 3:c6b5944187d5 1118 * @}
bcostm 3:c6b5944187d5 1119 */
bcostm 3:c6b5944187d5 1120
bcostm 3:c6b5944187d5 1121 /**
bcostm 3:c6b5944187d5 1122 * @}
bcostm 3:c6b5944187d5 1123 */
bcostm 3:c6b5944187d5 1124
bcostm 3:c6b5944187d5 1125 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bcostm 3:c6b5944187d5 1126