Contains the BSP driver for the B-L475E-IOT01 board.
Dependents: mbed-os-example-ble-Thermometer DISCO_L475VG_IOT01-Telegram-BOT DISCO_L475VG_IOT01-sche_cheveux DISCO_L475VG_IOT01-QSPI_FLASH_FILE_SYSTEM ... more
https://os.mbed.com/platforms/ST-Discovery-L475E-IOT01A/
Drivers/BSP/B-L475E-IOT01/stm32l475e_iot01_qspi.c@6:9dfa42666f03, 2018-01-19 (annotated)
- Committer:
- bcostm
- Date:
- Fri Jan 19 14:27:51 2018 +0100
- Revision:
- 6:9dfa42666f03
- Parent:
- 5:0c70bc6d2dc0
- Child:
- 7:bfe8272ced90
Update BSP files with STM32Cube L4 V1.11.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bcostm | 3:c6b5944187d5 | 1 | /** |
bcostm | 3:c6b5944187d5 | 2 | ****************************************************************************** |
bcostm | 3:c6b5944187d5 | 3 | * @file stm32l475e_iot01_qspi.c |
bcostm | 3:c6b5944187d5 | 4 | * @author MCD Application Team |
bcostm | 3:c6b5944187d5 | 5 | * @brief This file includes a standard driver for the MX25R6435F QSPI |
bcostm | 3:c6b5944187d5 | 6 | * memory mounted on STM32L475E IOT01 board. |
bcostm | 3:c6b5944187d5 | 7 | @verbatim |
bcostm | 3:c6b5944187d5 | 8 | ============================================================================== |
bcostm | 3:c6b5944187d5 | 9 | ##### How to use this driver ##### |
bcostm | 3:c6b5944187d5 | 10 | ============================================================================== |
bcostm | 3:c6b5944187d5 | 11 | [..] |
bcostm | 3:c6b5944187d5 | 12 | (#) This driver is used to drive the MX25R6435F QSPI external |
bcostm | 3:c6b5944187d5 | 13 | memory mounted on STM32L475E IOT01 board. |
bcostm | 3:c6b5944187d5 | 14 | |
bcostm | 3:c6b5944187d5 | 15 | (#) This driver need a specific component driver (MX25R6435F) to be included with. |
bcostm | 3:c6b5944187d5 | 16 | |
bcostm | 3:c6b5944187d5 | 17 | (#) Initialization steps: |
bcostm | 3:c6b5944187d5 | 18 | (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This |
bcostm | 3:c6b5944187d5 | 19 | function includes the MSP layer hardware resources initialization and the |
bcostm | 3:c6b5944187d5 | 20 | QSPI interface with the external memory. The BSP_QSPI_DeInit() can be used |
bcostm | 3:c6b5944187d5 | 21 | to deactivate the QSPI interface. |
bcostm | 3:c6b5944187d5 | 22 | |
bcostm | 3:c6b5944187d5 | 23 | (#) QSPI memory operations |
bcostm | 3:c6b5944187d5 | 24 | (++) QSPI memory can be accessed with read/write operations once it is |
bcostm | 3:c6b5944187d5 | 25 | initialized. |
bcostm | 3:c6b5944187d5 | 26 | Read/write operation can be performed with AHB access using the functions |
bcostm | 3:c6b5944187d5 | 27 | BSP_QSPI_Read()/BSP_QSPI_Write(). |
bcostm | 3:c6b5944187d5 | 28 | (++) The function to the QSPI memory in memory-mapped mode is possible after |
bcostm | 3:c6b5944187d5 | 29 | the call of the function BSP_QSPI_EnableMemoryMappedMode(). |
bcostm | 3:c6b5944187d5 | 30 | (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 31 | (see the QSPI memory data sheet) |
bcostm | 3:c6b5944187d5 | 32 | (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by |
bcostm | 3:c6b5944187d5 | 33 | specifying the block address. You can perform an erase operation of the whole |
bcostm | 3:c6b5944187d5 | 34 | chip by calling the function BSP_QSPI_Erase_Chip(). |
bcostm | 3:c6b5944187d5 | 35 | (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 36 | (see the QSPI memory data sheet) |
bcostm | 3:c6b5944187d5 | 37 | (++) Perform erase sector operation using the function BSP_QSPI_Erase_Sector() |
bcostm | 3:c6b5944187d5 | 38 | which is not blocking. So the function BSP_QSPI_GetStatus() should be used |
bcostm | 3:c6b5944187d5 | 39 | to check if the memory is busy, and the functions BSP_QSPI_SuspendErase()/ |
bcostm | 3:c6b5944187d5 | 40 | BSP_QSPI_ResumeErase() can be used to perform other operations during the |
bcostm | 3:c6b5944187d5 | 41 | sector erase. |
bcostm | 3:c6b5944187d5 | 42 | (++) Deep power down of the QSPI memory is managed with the call of the functions |
bcostm | 3:c6b5944187d5 | 43 | BSP_QSPI_EnterDeepPowerDown()/BSP_QSPI_LeaveDeepPowerDown() |
bcostm | 3:c6b5944187d5 | 44 | @endverbatim |
bcostm | 3:c6b5944187d5 | 45 | ****************************************************************************** |
bcostm | 3:c6b5944187d5 | 46 | * @attention |
bcostm | 3:c6b5944187d5 | 47 | * |
bcostm | 3:c6b5944187d5 | 48 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
bcostm | 3:c6b5944187d5 | 49 | * |
bcostm | 3:c6b5944187d5 | 50 | * Redistribution and use in source and binary forms, with or without modification, |
bcostm | 3:c6b5944187d5 | 51 | * are permitted provided that the following conditions are met: |
bcostm | 3:c6b5944187d5 | 52 | * 1. Redistributions of source code must retain the above copyright notice, |
bcostm | 3:c6b5944187d5 | 53 | * this list of conditions and the following disclaimer. |
bcostm | 3:c6b5944187d5 | 54 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bcostm | 3:c6b5944187d5 | 55 | * this list of conditions and the following disclaimer in the documentation |
bcostm | 3:c6b5944187d5 | 56 | * and/or other materials provided with the distribution. |
bcostm | 3:c6b5944187d5 | 57 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bcostm | 3:c6b5944187d5 | 58 | * may be used to endorse or promote products derived from this software |
bcostm | 3:c6b5944187d5 | 59 | * without specific prior written permission. |
bcostm | 3:c6b5944187d5 | 60 | * |
bcostm | 3:c6b5944187d5 | 61 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bcostm | 3:c6b5944187d5 | 62 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bcostm | 3:c6b5944187d5 | 63 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bcostm | 3:c6b5944187d5 | 64 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bcostm | 3:c6b5944187d5 | 65 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bcostm | 3:c6b5944187d5 | 66 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bcostm | 3:c6b5944187d5 | 67 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bcostm | 3:c6b5944187d5 | 68 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bcostm | 3:c6b5944187d5 | 69 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bcostm | 3:c6b5944187d5 | 70 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bcostm | 3:c6b5944187d5 | 71 | * |
bcostm | 3:c6b5944187d5 | 72 | ****************************************************************************** |
bcostm | 3:c6b5944187d5 | 73 | */ |
bcostm | 3:c6b5944187d5 | 74 | |
bcostm | 3:c6b5944187d5 | 75 | /* Includes ------------------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 76 | #include "stm32l475e_iot01_qspi.h" |
bcostm | 3:c6b5944187d5 | 77 | |
bcostm | 3:c6b5944187d5 | 78 | /** @addtogroup BSP |
bcostm | 3:c6b5944187d5 | 79 | * @{ |
bcostm | 3:c6b5944187d5 | 80 | */ |
bcostm | 3:c6b5944187d5 | 81 | |
bcostm | 3:c6b5944187d5 | 82 | /** @addtogroup STM32L475E_IOT01 |
bcostm | 3:c6b5944187d5 | 83 | * @{ |
bcostm | 3:c6b5944187d5 | 84 | */ |
bcostm | 3:c6b5944187d5 | 85 | |
bcostm | 3:c6b5944187d5 | 86 | /** @defgroup STM32L475E_IOT01_QSPI QSPI |
bcostm | 3:c6b5944187d5 | 87 | * @{ |
bcostm | 3:c6b5944187d5 | 88 | */ |
bcostm | 3:c6b5944187d5 | 89 | |
bcostm | 3:c6b5944187d5 | 90 | /* Private constants --------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 91 | /** @defgroup STM32L475E_IOT01_QSPI_Private_Constants QSPI Private Constants |
bcostm | 3:c6b5944187d5 | 92 | * @{ |
bcostm | 3:c6b5944187d5 | 93 | */ |
bcostm | 3:c6b5944187d5 | 94 | #define QSPI_QUAD_DISABLE 0x0 |
bcostm | 3:c6b5944187d5 | 95 | #define QSPI_QUAD_ENABLE 0x1 |
bcostm | 3:c6b5944187d5 | 96 | |
bcostm | 3:c6b5944187d5 | 97 | #define QSPI_HIGH_PERF_DISABLE 0x0 |
bcostm | 3:c6b5944187d5 | 98 | #define QSPI_HIGH_PERF_ENABLE 0x1 |
bcostm | 3:c6b5944187d5 | 99 | /** |
bcostm | 3:c6b5944187d5 | 100 | * @} |
bcostm | 3:c6b5944187d5 | 101 | */ |
bcostm | 3:c6b5944187d5 | 102 | /* Private variables ---------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 103 | |
bcostm | 3:c6b5944187d5 | 104 | /** @defgroup STM32L475E_IOT01_QSPI_Private_Variables QSPI Private Variables |
bcostm | 3:c6b5944187d5 | 105 | * @{ |
bcostm | 3:c6b5944187d5 | 106 | */ |
bcostm | 3:c6b5944187d5 | 107 | QSPI_HandleTypeDef QSPIHandle; |
bcostm | 3:c6b5944187d5 | 108 | |
bcostm | 3:c6b5944187d5 | 109 | /** |
bcostm | 3:c6b5944187d5 | 110 | * @} |
bcostm | 3:c6b5944187d5 | 111 | */ |
bcostm | 3:c6b5944187d5 | 112 | |
bcostm | 3:c6b5944187d5 | 113 | |
bcostm | 3:c6b5944187d5 | 114 | /* Private functions ---------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 115 | |
bcostm | 3:c6b5944187d5 | 116 | /** @defgroup STM32L475E_IOT01_QSPI_Private_Functions QSPI Private Functions |
bcostm | 3:c6b5944187d5 | 117 | * @{ |
bcostm | 3:c6b5944187d5 | 118 | */ |
bcostm | 3:c6b5944187d5 | 119 | static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi); |
bcostm | 3:c6b5944187d5 | 120 | static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi); |
bcostm | 3:c6b5944187d5 | 121 | static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout); |
bcostm | 3:c6b5944187d5 | 122 | static uint8_t QSPI_QuadMode (QSPI_HandleTypeDef *hqspi, uint8_t Operation); |
bcostm | 3:c6b5944187d5 | 123 | static uint8_t QSPI_HighPerfMode (QSPI_HandleTypeDef *hqspi, uint8_t Operation); |
bcostm | 3:c6b5944187d5 | 124 | |
bcostm | 3:c6b5944187d5 | 125 | /** |
bcostm | 3:c6b5944187d5 | 126 | * @} |
bcostm | 3:c6b5944187d5 | 127 | */ |
bcostm | 3:c6b5944187d5 | 128 | |
bcostm | 3:c6b5944187d5 | 129 | /* Exported functions ---------------------------------------------------------*/ |
bcostm | 3:c6b5944187d5 | 130 | |
bcostm | 3:c6b5944187d5 | 131 | /** @addtogroup STM32L475E_IOT01_QSPI_Exported_Functions |
bcostm | 3:c6b5944187d5 | 132 | * @{ |
bcostm | 3:c6b5944187d5 | 133 | */ |
bcostm | 3:c6b5944187d5 | 134 | |
bcostm | 3:c6b5944187d5 | 135 | /** |
bcostm | 3:c6b5944187d5 | 136 | * @brief Initializes the QSPI interface. |
bcostm | 3:c6b5944187d5 | 137 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 138 | */ |
bcostm | 3:c6b5944187d5 | 139 | uint8_t BSP_QSPI_Init(void) |
bcostm | 3:c6b5944187d5 | 140 | { |
bcostm | 3:c6b5944187d5 | 141 | QSPIHandle.Instance = QUADSPI; |
bcostm | 3:c6b5944187d5 | 142 | |
bcostm | 3:c6b5944187d5 | 143 | /* Call the DeInit function to reset the driver */ |
bcostm | 3:c6b5944187d5 | 144 | if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 145 | { |
bcostm | 3:c6b5944187d5 | 146 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 147 | } |
bcostm | 3:c6b5944187d5 | 148 | |
bcostm | 3:c6b5944187d5 | 149 | /* System level initialization */ |
bcostm | 3:c6b5944187d5 | 150 | BSP_QSPI_MspInit(); |
bcostm | 3:c6b5944187d5 | 151 | |
bcostm | 3:c6b5944187d5 | 152 | /* QSPI initialization */ |
bcostm | 3:c6b5944187d5 | 153 | QSPIHandle.Init.ClockPrescaler = 2; /* QSPI clock = 80MHz / (ClockPrescaler+1) = 26.67MHz */ |
bcostm | 3:c6b5944187d5 | 154 | QSPIHandle.Init.FifoThreshold = 4; |
bcostm | 3:c6b5944187d5 | 155 | QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; |
bcostm | 3:c6b5944187d5 | 156 | QSPIHandle.Init.FlashSize = POSITION_VAL(MX25R6435F_FLASH_SIZE) - 1; |
bcostm | 3:c6b5944187d5 | 157 | QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE; |
bcostm | 3:c6b5944187d5 | 158 | QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0; |
bcostm | 3:c6b5944187d5 | 159 | |
bcostm | 3:c6b5944187d5 | 160 | if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 161 | { |
bcostm | 3:c6b5944187d5 | 162 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 163 | } |
bcostm | 3:c6b5944187d5 | 164 | |
bcostm | 3:c6b5944187d5 | 165 | /* QSPI memory reset */ |
bcostm | 3:c6b5944187d5 | 166 | if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 167 | { |
bcostm | 3:c6b5944187d5 | 168 | return QSPI_NOT_SUPPORTED; |
bcostm | 3:c6b5944187d5 | 169 | } |
bcostm | 3:c6b5944187d5 | 170 | |
bcostm | 3:c6b5944187d5 | 171 | /* QSPI quad enable */ |
bcostm | 3:c6b5944187d5 | 172 | if (QSPI_QuadMode(&QSPIHandle, QSPI_QUAD_ENABLE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 173 | { |
bcostm | 3:c6b5944187d5 | 174 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 175 | } |
bcostm | 3:c6b5944187d5 | 176 | |
bcostm | 3:c6b5944187d5 | 177 | /* High performance mode enable */ |
bcostm | 3:c6b5944187d5 | 178 | if (QSPI_HighPerfMode(&QSPIHandle, QSPI_HIGH_PERF_ENABLE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 179 | { |
bcostm | 3:c6b5944187d5 | 180 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 181 | } |
bcostm | 3:c6b5944187d5 | 182 | |
bcostm | 3:c6b5944187d5 | 183 | /* Re-configure the clock for the high performance mode */ |
bcostm | 3:c6b5944187d5 | 184 | QSPIHandle.Init.ClockPrescaler = 1; /* QSPI clock = 80MHz / (ClockPrescaler+1) = 40MHz */ |
bcostm | 3:c6b5944187d5 | 185 | |
bcostm | 3:c6b5944187d5 | 186 | if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 187 | { |
bcostm | 3:c6b5944187d5 | 188 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 189 | } |
bcostm | 3:c6b5944187d5 | 190 | |
bcostm | 3:c6b5944187d5 | 191 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 192 | } |
bcostm | 3:c6b5944187d5 | 193 | |
bcostm | 3:c6b5944187d5 | 194 | /** |
bcostm | 3:c6b5944187d5 | 195 | * @brief De-Initializes the QSPI interface. |
bcostm | 3:c6b5944187d5 | 196 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 197 | */ |
bcostm | 3:c6b5944187d5 | 198 | uint8_t BSP_QSPI_DeInit(void) |
bcostm | 3:c6b5944187d5 | 199 | { |
bcostm | 3:c6b5944187d5 | 200 | QSPIHandle.Instance = QUADSPI; |
bcostm | 3:c6b5944187d5 | 201 | |
bcostm | 3:c6b5944187d5 | 202 | /* Call the DeInit function to reset the driver */ |
bcostm | 3:c6b5944187d5 | 203 | if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 204 | { |
bcostm | 3:c6b5944187d5 | 205 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 206 | } |
bcostm | 3:c6b5944187d5 | 207 | |
bcostm | 3:c6b5944187d5 | 208 | /* System level De-initialization */ |
bcostm | 3:c6b5944187d5 | 209 | BSP_QSPI_MspDeInit(); |
bcostm | 3:c6b5944187d5 | 210 | |
bcostm | 3:c6b5944187d5 | 211 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 212 | } |
bcostm | 3:c6b5944187d5 | 213 | |
bcostm | 3:c6b5944187d5 | 214 | /** |
bcostm | 3:c6b5944187d5 | 215 | * @brief Reads an amount of data from the QSPI memory. |
bcostm | 3:c6b5944187d5 | 216 | * @param pData : Pointer to data to be read |
bcostm | 3:c6b5944187d5 | 217 | * @param ReadAddr : Read start address |
bcostm | 3:c6b5944187d5 | 218 | * @param Size : Size of data to read |
bcostm | 3:c6b5944187d5 | 219 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 220 | */ |
bcostm | 3:c6b5944187d5 | 221 | uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size) |
bcostm | 3:c6b5944187d5 | 222 | { |
bcostm | 3:c6b5944187d5 | 223 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 224 | |
bcostm | 3:c6b5944187d5 | 225 | /* Initialize the read command */ |
bcostm | 3:c6b5944187d5 | 226 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 227 | sCommand.Instruction = QUAD_INOUT_READ_CMD; |
bcostm | 3:c6b5944187d5 | 228 | sCommand.AddressMode = QSPI_ADDRESS_4_LINES; |
bcostm | 3:c6b5944187d5 | 229 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 230 | sCommand.Address = ReadAddr; |
bcostm | 3:c6b5944187d5 | 231 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; |
bcostm | 3:c6b5944187d5 | 232 | sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; |
bcostm | 3:c6b5944187d5 | 233 | sCommand.AlternateBytes = MX25R6435F_ALT_BYTES_NO_PE_MODE; |
bcostm | 3:c6b5944187d5 | 234 | sCommand.DataMode = QSPI_DATA_4_LINES; |
bcostm | 3:c6b5944187d5 | 235 | sCommand.DummyCycles = MX25R6435F_DUMMY_CYCLES_READ_QUAD; |
bcostm | 3:c6b5944187d5 | 236 | sCommand.NbData = Size; |
bcostm | 3:c6b5944187d5 | 237 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 238 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 239 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 240 | |
bcostm | 3:c6b5944187d5 | 241 | /* Configure the command */ |
bcostm | 3:c6b5944187d5 | 242 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 243 | { |
bcostm | 3:c6b5944187d5 | 244 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 245 | } |
bcostm | 3:c6b5944187d5 | 246 | |
bcostm | 3:c6b5944187d5 | 247 | /* Reception of the data */ |
bcostm | 3:c6b5944187d5 | 248 | if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 249 | { |
bcostm | 3:c6b5944187d5 | 250 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 251 | } |
bcostm | 3:c6b5944187d5 | 252 | |
bcostm | 3:c6b5944187d5 | 253 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 254 | } |
bcostm | 3:c6b5944187d5 | 255 | |
bcostm | 3:c6b5944187d5 | 256 | /** |
bcostm | 3:c6b5944187d5 | 257 | * @brief Writes an amount of data to the QSPI memory. |
bcostm | 3:c6b5944187d5 | 258 | * @param pData : Pointer to data to be written |
bcostm | 3:c6b5944187d5 | 259 | * @param WriteAddr : Write start address |
bcostm | 3:c6b5944187d5 | 260 | * @param Size : Size of data to write |
bcostm | 3:c6b5944187d5 | 261 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 262 | */ |
bcostm | 3:c6b5944187d5 | 263 | uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size) |
bcostm | 3:c6b5944187d5 | 264 | { |
bcostm | 3:c6b5944187d5 | 265 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 266 | uint32_t end_addr, current_size, current_addr; |
bcostm | 3:c6b5944187d5 | 267 | |
bcostm | 3:c6b5944187d5 | 268 | /* Calculation of the size between the write address and the end of the page */ |
bcostm | 3:c6b5944187d5 | 269 | current_size = MX25R6435F_PAGE_SIZE - (WriteAddr % MX25R6435F_PAGE_SIZE); |
bcostm | 3:c6b5944187d5 | 270 | |
bcostm | 3:c6b5944187d5 | 271 | /* Check if the size of the data is less than the remaining place in the page */ |
bcostm | 3:c6b5944187d5 | 272 | if (current_size > Size) |
bcostm | 3:c6b5944187d5 | 273 | { |
bcostm | 3:c6b5944187d5 | 274 | current_size = Size; |
bcostm | 3:c6b5944187d5 | 275 | } |
bcostm | 3:c6b5944187d5 | 276 | |
bcostm | 3:c6b5944187d5 | 277 | /* Initialize the adress variables */ |
bcostm | 3:c6b5944187d5 | 278 | current_addr = WriteAddr; |
bcostm | 3:c6b5944187d5 | 279 | end_addr = WriteAddr + Size; |
bcostm | 3:c6b5944187d5 | 280 | |
bcostm | 3:c6b5944187d5 | 281 | /* Initialize the program command */ |
bcostm | 3:c6b5944187d5 | 282 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 283 | sCommand.Instruction = QUAD_PAGE_PROG_CMD; |
bcostm | 3:c6b5944187d5 | 284 | sCommand.AddressMode = QSPI_ADDRESS_4_LINES; |
bcostm | 3:c6b5944187d5 | 285 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 286 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 287 | sCommand.DataMode = QSPI_DATA_4_LINES; |
bcostm | 3:c6b5944187d5 | 288 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 289 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 290 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 291 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 292 | |
bcostm | 3:c6b5944187d5 | 293 | /* Perform the write page by page */ |
bcostm | 3:c6b5944187d5 | 294 | do |
bcostm | 3:c6b5944187d5 | 295 | { |
bcostm | 3:c6b5944187d5 | 296 | sCommand.Address = current_addr; |
bcostm | 3:c6b5944187d5 | 297 | sCommand.NbData = current_size; |
bcostm | 3:c6b5944187d5 | 298 | |
bcostm | 3:c6b5944187d5 | 299 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 300 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 301 | { |
bcostm | 3:c6b5944187d5 | 302 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 303 | } |
bcostm | 3:c6b5944187d5 | 304 | |
bcostm | 3:c6b5944187d5 | 305 | /* Configure the command */ |
bcostm | 3:c6b5944187d5 | 306 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 307 | { |
bcostm | 3:c6b5944187d5 | 308 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 309 | } |
bcostm | 3:c6b5944187d5 | 310 | |
bcostm | 3:c6b5944187d5 | 311 | /* Transmission of the data */ |
bcostm | 3:c6b5944187d5 | 312 | if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 313 | { |
bcostm | 3:c6b5944187d5 | 314 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 315 | } |
bcostm | 3:c6b5944187d5 | 316 | |
bcostm | 3:c6b5944187d5 | 317 | /* Configure automatic polling mode to wait for end of program */ |
bcostm | 3:c6b5944187d5 | 318 | if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 319 | { |
bcostm | 3:c6b5944187d5 | 320 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 321 | } |
bcostm | 3:c6b5944187d5 | 322 | |
bcostm | 3:c6b5944187d5 | 323 | /* Update the address and size variables for next page programming */ |
bcostm | 3:c6b5944187d5 | 324 | current_addr += current_size; |
bcostm | 3:c6b5944187d5 | 325 | pData += current_size; |
bcostm | 3:c6b5944187d5 | 326 | current_size = ((current_addr + MX25R6435F_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MX25R6435F_PAGE_SIZE; |
bcostm | 3:c6b5944187d5 | 327 | } while (current_addr < end_addr); |
bcostm | 3:c6b5944187d5 | 328 | |
bcostm | 3:c6b5944187d5 | 329 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 330 | } |
bcostm | 3:c6b5944187d5 | 331 | |
bcostm | 3:c6b5944187d5 | 332 | /** |
bcostm | 3:c6b5944187d5 | 333 | * @brief Erases the specified block of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 334 | * @param BlockAddress : Block address to erase |
bcostm | 3:c6b5944187d5 | 335 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 336 | */ |
bcostm | 3:c6b5944187d5 | 337 | uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress) |
bcostm | 3:c6b5944187d5 | 338 | { |
bcostm | 3:c6b5944187d5 | 339 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 340 | |
bcostm | 3:c6b5944187d5 | 341 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 342 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 343 | sCommand.Instruction = BLOCK_ERASE_CMD; |
bcostm | 3:c6b5944187d5 | 344 | sCommand.AddressMode = QSPI_ADDRESS_1_LINE; |
bcostm | 3:c6b5944187d5 | 345 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 346 | sCommand.Address = BlockAddress; |
bcostm | 3:c6b5944187d5 | 347 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 348 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 349 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 350 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 351 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 352 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 353 | |
bcostm | 3:c6b5944187d5 | 354 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 355 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 356 | { |
bcostm | 3:c6b5944187d5 | 357 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 358 | } |
bcostm | 3:c6b5944187d5 | 359 | |
bcostm | 3:c6b5944187d5 | 360 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 361 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 362 | { |
bcostm | 3:c6b5944187d5 | 363 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 364 | } |
bcostm | 3:c6b5944187d5 | 365 | |
bcostm | 3:c6b5944187d5 | 366 | /* Configure automatic polling mode to wait for end of erase */ |
bcostm | 3:c6b5944187d5 | 367 | if (QSPI_AutoPollingMemReady(&QSPIHandle, MX25R6435F_BLOCK_ERASE_MAX_TIME) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 368 | { |
bcostm | 3:c6b5944187d5 | 369 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 370 | } |
bcostm | 3:c6b5944187d5 | 371 | |
bcostm | 3:c6b5944187d5 | 372 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 373 | } |
bcostm | 3:c6b5944187d5 | 374 | |
bcostm | 3:c6b5944187d5 | 375 | /** |
bcostm | 3:c6b5944187d5 | 376 | * @brief Erases the specified sector of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 377 | * @param Sector : Sector address to erase (0 to 255) |
bcostm | 3:c6b5944187d5 | 378 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 379 | * @note This function is non blocking meaning that sector erase |
bcostm | 3:c6b5944187d5 | 380 | * operation is started but not completed when the function |
bcostm | 3:c6b5944187d5 | 381 | * returns. Application has to call BSP_QSPI_GetStatus() |
bcostm | 3:c6b5944187d5 | 382 | * to know when the device is available again (i.e. erase operation |
bcostm | 3:c6b5944187d5 | 383 | * completed). |
bcostm | 3:c6b5944187d5 | 384 | */ |
bcostm | 3:c6b5944187d5 | 385 | uint8_t BSP_QSPI_Erase_Sector(uint32_t Sector) |
bcostm | 3:c6b5944187d5 | 386 | { |
bcostm | 3:c6b5944187d5 | 387 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 388 | |
bcostm | 3:c6b5944187d5 | 389 | if (Sector >= (uint32_t)(MX25R6435F_FLASH_SIZE/MX25R6435F_SECTOR_SIZE)) |
bcostm | 3:c6b5944187d5 | 390 | { |
bcostm | 3:c6b5944187d5 | 391 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 392 | } |
bcostm | 3:c6b5944187d5 | 393 | |
bcostm | 3:c6b5944187d5 | 394 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 395 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 396 | sCommand.Instruction = SECTOR_ERASE_CMD; |
bcostm | 3:c6b5944187d5 | 397 | sCommand.AddressMode = QSPI_ADDRESS_1_LINE; |
bcostm | 3:c6b5944187d5 | 398 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 399 | sCommand.Address = (Sector * MX25R6435F_SECTOR_SIZE); |
bcostm | 3:c6b5944187d5 | 400 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 401 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 402 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 403 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 404 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 405 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 406 | |
bcostm | 3:c6b5944187d5 | 407 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 408 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 409 | { |
bcostm | 3:c6b5944187d5 | 410 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 411 | } |
bcostm | 3:c6b5944187d5 | 412 | |
bcostm | 3:c6b5944187d5 | 413 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 414 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 415 | { |
bcostm | 3:c6b5944187d5 | 416 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 417 | } |
bcostm | 3:c6b5944187d5 | 418 | |
bcostm | 3:c6b5944187d5 | 419 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 420 | } |
bcostm | 3:c6b5944187d5 | 421 | |
bcostm | 3:c6b5944187d5 | 422 | /** |
bcostm | 3:c6b5944187d5 | 423 | * @brief Erases the entire QSPI memory. |
bcostm | 3:c6b5944187d5 | 424 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 425 | */ |
bcostm | 3:c6b5944187d5 | 426 | uint8_t BSP_QSPI_Erase_Chip(void) |
bcostm | 3:c6b5944187d5 | 427 | { |
bcostm | 3:c6b5944187d5 | 428 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 429 | |
bcostm | 3:c6b5944187d5 | 430 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 431 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 432 | sCommand.Instruction = CHIP_ERASE_CMD; |
bcostm | 3:c6b5944187d5 | 433 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 434 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 435 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 436 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 437 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 438 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 439 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 440 | |
bcostm | 3:c6b5944187d5 | 441 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 442 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 443 | { |
bcostm | 3:c6b5944187d5 | 444 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 445 | } |
bcostm | 3:c6b5944187d5 | 446 | |
bcostm | 3:c6b5944187d5 | 447 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 448 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 449 | { |
bcostm | 3:c6b5944187d5 | 450 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 451 | } |
bcostm | 3:c6b5944187d5 | 452 | |
bcostm | 3:c6b5944187d5 | 453 | /* Configure automatic polling mode to wait for end of erase */ |
bcostm | 3:c6b5944187d5 | 454 | if (QSPI_AutoPollingMemReady(&QSPIHandle, MX25R6435F_CHIP_ERASE_MAX_TIME) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 455 | { |
bcostm | 3:c6b5944187d5 | 456 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 457 | } |
bcostm | 3:c6b5944187d5 | 458 | |
bcostm | 3:c6b5944187d5 | 459 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 460 | } |
bcostm | 3:c6b5944187d5 | 461 | |
bcostm | 3:c6b5944187d5 | 462 | /** |
bcostm | 3:c6b5944187d5 | 463 | * @brief Reads current status of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 464 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 465 | */ |
bcostm | 3:c6b5944187d5 | 466 | uint8_t BSP_QSPI_GetStatus(void) |
bcostm | 3:c6b5944187d5 | 467 | { |
bcostm | 3:c6b5944187d5 | 468 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 469 | uint8_t reg; |
bcostm | 3:c6b5944187d5 | 470 | |
bcostm | 3:c6b5944187d5 | 471 | /* Initialize the read security register command */ |
bcostm | 3:c6b5944187d5 | 472 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 473 | sCommand.Instruction = READ_SEC_REG_CMD; |
bcostm | 3:c6b5944187d5 | 474 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 475 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 476 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 477 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 478 | sCommand.NbData = 1; |
bcostm | 3:c6b5944187d5 | 479 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 480 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 481 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 482 | |
bcostm | 3:c6b5944187d5 | 483 | /* Configure the command */ |
bcostm | 3:c6b5944187d5 | 484 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 485 | { |
bcostm | 3:c6b5944187d5 | 486 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 487 | } |
bcostm | 3:c6b5944187d5 | 488 | |
bcostm | 3:c6b5944187d5 | 489 | /* Reception of the data */ |
bcostm | 3:c6b5944187d5 | 490 | if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 491 | { |
bcostm | 3:c6b5944187d5 | 492 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 493 | } |
bcostm | 3:c6b5944187d5 | 494 | |
bcostm | 3:c6b5944187d5 | 495 | /* Check the value of the register */ |
bcostm | 3:c6b5944187d5 | 496 | if ((reg & (MX25R6435F_SECR_P_FAIL | MX25R6435F_SECR_E_FAIL)) != 0) |
bcostm | 3:c6b5944187d5 | 497 | { |
bcostm | 3:c6b5944187d5 | 498 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 499 | } |
bcostm | 3:c6b5944187d5 | 500 | else if ((reg & (MX25R6435F_SECR_PSB | MX25R6435F_SECR_ESB)) != 0) |
bcostm | 3:c6b5944187d5 | 501 | { |
bcostm | 3:c6b5944187d5 | 502 | return QSPI_SUSPENDED; |
bcostm | 3:c6b5944187d5 | 503 | } |
bcostm | 3:c6b5944187d5 | 504 | |
bcostm | 3:c6b5944187d5 | 505 | /* Initialize the read status register command */ |
bcostm | 3:c6b5944187d5 | 506 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 507 | |
bcostm | 3:c6b5944187d5 | 508 | /* Configure the command */ |
bcostm | 3:c6b5944187d5 | 509 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 510 | { |
bcostm | 3:c6b5944187d5 | 511 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 512 | } |
bcostm | 3:c6b5944187d5 | 513 | |
bcostm | 3:c6b5944187d5 | 514 | /* Reception of the data */ |
bcostm | 3:c6b5944187d5 | 515 | if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 516 | { |
bcostm | 3:c6b5944187d5 | 517 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 518 | } |
bcostm | 3:c6b5944187d5 | 519 | |
bcostm | 3:c6b5944187d5 | 520 | /* Check the value of the register */ |
bcostm | 3:c6b5944187d5 | 521 | if ((reg & MX25R6435F_SR_WIP) != 0) |
bcostm | 3:c6b5944187d5 | 522 | { |
bcostm | 3:c6b5944187d5 | 523 | return QSPI_BUSY; |
bcostm | 3:c6b5944187d5 | 524 | } |
bcostm | 3:c6b5944187d5 | 525 | else |
bcostm | 3:c6b5944187d5 | 526 | { |
bcostm | 3:c6b5944187d5 | 527 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 528 | } |
bcostm | 3:c6b5944187d5 | 529 | } |
bcostm | 3:c6b5944187d5 | 530 | |
bcostm | 3:c6b5944187d5 | 531 | /** |
bcostm | 3:c6b5944187d5 | 532 | * @brief Return the configuration of the QSPI memory. |
bcostm | 3:c6b5944187d5 | 533 | * @param pInfo : pointer on the configuration structure |
bcostm | 3:c6b5944187d5 | 534 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 535 | */ |
bcostm | 3:c6b5944187d5 | 536 | uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo) |
bcostm | 3:c6b5944187d5 | 537 | { |
bcostm | 3:c6b5944187d5 | 538 | /* Configure the structure with the memory configuration */ |
bcostm | 3:c6b5944187d5 | 539 | pInfo->FlashSize = MX25R6435F_FLASH_SIZE; |
bcostm | 3:c6b5944187d5 | 540 | pInfo->EraseSectorSize = MX25R6435F_SECTOR_SIZE; |
bcostm | 3:c6b5944187d5 | 541 | pInfo->EraseSectorsNumber = (MX25R6435F_FLASH_SIZE/MX25R6435F_SECTOR_SIZE); |
bcostm | 3:c6b5944187d5 | 542 | pInfo->ProgPageSize = MX25R6435F_PAGE_SIZE; |
bcostm | 3:c6b5944187d5 | 543 | pInfo->ProgPagesNumber = (MX25R6435F_FLASH_SIZE/MX25R6435F_PAGE_SIZE); |
bcostm | 3:c6b5944187d5 | 544 | |
bcostm | 3:c6b5944187d5 | 545 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 546 | } |
bcostm | 3:c6b5944187d5 | 547 | |
bcostm | 3:c6b5944187d5 | 548 | /** |
bcostm | 3:c6b5944187d5 | 549 | * @brief Configure the QSPI in memory-mapped mode |
bcostm | 3:c6b5944187d5 | 550 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 551 | */ |
bcostm | 3:c6b5944187d5 | 552 | uint8_t BSP_QSPI_EnableMemoryMappedMode(void) |
bcostm | 3:c6b5944187d5 | 553 | { |
bcostm | 3:c6b5944187d5 | 554 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 555 | QSPI_MemoryMappedTypeDef sMemMappedCfg; |
bcostm | 3:c6b5944187d5 | 556 | |
bcostm | 3:c6b5944187d5 | 557 | /* Configure the command for the read instruction */ |
bcostm | 3:c6b5944187d5 | 558 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 559 | sCommand.Instruction = QUAD_INOUT_READ_CMD; |
bcostm | 3:c6b5944187d5 | 560 | sCommand.AddressMode = QSPI_ADDRESS_4_LINES; |
bcostm | 3:c6b5944187d5 | 561 | sCommand.AddressSize = QSPI_ADDRESS_24_BITS; |
bcostm | 3:c6b5944187d5 | 562 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; |
bcostm | 3:c6b5944187d5 | 563 | sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; |
bcostm | 3:c6b5944187d5 | 564 | sCommand.AlternateBytes = MX25R6435F_ALT_BYTES_NO_PE_MODE; |
bcostm | 3:c6b5944187d5 | 565 | sCommand.DataMode = QSPI_DATA_4_LINES; |
bcostm | 3:c6b5944187d5 | 566 | sCommand.DummyCycles = MX25R6435F_DUMMY_CYCLES_READ_QUAD; |
bcostm | 3:c6b5944187d5 | 567 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 568 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 569 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 570 | |
bcostm | 3:c6b5944187d5 | 571 | /* Configure the memory mapped mode */ |
bcostm | 3:c6b5944187d5 | 572 | sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; |
bcostm | 3:c6b5944187d5 | 573 | |
bcostm | 3:c6b5944187d5 | 574 | if (HAL_QSPI_MemoryMapped(&QSPIHandle, &sCommand, &sMemMappedCfg) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 575 | { |
bcostm | 3:c6b5944187d5 | 576 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 577 | } |
bcostm | 3:c6b5944187d5 | 578 | |
bcostm | 3:c6b5944187d5 | 579 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 580 | } |
bcostm | 3:c6b5944187d5 | 581 | |
bcostm | 3:c6b5944187d5 | 582 | /** |
bcostm | 3:c6b5944187d5 | 583 | * @brief This function suspends an ongoing erase command. |
bcostm | 3:c6b5944187d5 | 584 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 585 | */ |
bcostm | 3:c6b5944187d5 | 586 | uint8_t BSP_QSPI_SuspendErase(void) |
bcostm | 3:c6b5944187d5 | 587 | { |
bcostm | 3:c6b5944187d5 | 588 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 589 | |
bcostm | 3:c6b5944187d5 | 590 | /* Check whether the device is busy (erase operation is |
bcostm | 3:c6b5944187d5 | 591 | in progress). |
bcostm | 3:c6b5944187d5 | 592 | */ |
bcostm | 3:c6b5944187d5 | 593 | if (BSP_QSPI_GetStatus() == QSPI_BUSY) |
bcostm | 3:c6b5944187d5 | 594 | { |
bcostm | 3:c6b5944187d5 | 595 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 596 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 597 | sCommand.Instruction = PROG_ERASE_SUSPEND_CMD; |
bcostm | 3:c6b5944187d5 | 598 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 599 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 600 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 601 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 602 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 603 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 604 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 605 | |
bcostm | 3:c6b5944187d5 | 606 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 607 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 608 | { |
bcostm | 3:c6b5944187d5 | 609 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 610 | } |
bcostm | 3:c6b5944187d5 | 611 | |
bcostm | 3:c6b5944187d5 | 612 | if (BSP_QSPI_GetStatus() == QSPI_SUSPENDED) |
bcostm | 3:c6b5944187d5 | 613 | { |
bcostm | 3:c6b5944187d5 | 614 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 615 | } |
bcostm | 3:c6b5944187d5 | 616 | |
bcostm | 3:c6b5944187d5 | 617 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 618 | } |
bcostm | 3:c6b5944187d5 | 619 | |
bcostm | 3:c6b5944187d5 | 620 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 621 | } |
bcostm | 3:c6b5944187d5 | 622 | |
bcostm | 3:c6b5944187d5 | 623 | /** |
bcostm | 3:c6b5944187d5 | 624 | * @brief This function resumes a paused erase command. |
bcostm | 3:c6b5944187d5 | 625 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 626 | */ |
bcostm | 3:c6b5944187d5 | 627 | uint8_t BSP_QSPI_ResumeErase(void) |
bcostm | 3:c6b5944187d5 | 628 | { |
bcostm | 3:c6b5944187d5 | 629 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 630 | |
bcostm | 3:c6b5944187d5 | 631 | /* Check whether the device is in suspended state */ |
bcostm | 3:c6b5944187d5 | 632 | if (BSP_QSPI_GetStatus() == QSPI_SUSPENDED) |
bcostm | 3:c6b5944187d5 | 633 | { |
bcostm | 3:c6b5944187d5 | 634 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 635 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 636 | sCommand.Instruction = PROG_ERASE_RESUME_CMD; |
bcostm | 3:c6b5944187d5 | 637 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 638 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 639 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 640 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 641 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 642 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 643 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 644 | |
bcostm | 3:c6b5944187d5 | 645 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 646 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 647 | { |
bcostm | 3:c6b5944187d5 | 648 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 649 | } |
bcostm | 3:c6b5944187d5 | 650 | |
bcostm | 3:c6b5944187d5 | 651 | /* |
bcostm | 3:c6b5944187d5 | 652 | When this command is executed, the status register write in progress bit is set to 1, and |
bcostm | 3:c6b5944187d5 | 653 | the flag status register program erase controller bit is set to 0. This command is ignored |
bcostm | 3:c6b5944187d5 | 654 | if the device is not in a suspended state. |
bcostm | 3:c6b5944187d5 | 655 | */ |
bcostm | 3:c6b5944187d5 | 656 | |
bcostm | 3:c6b5944187d5 | 657 | if (BSP_QSPI_GetStatus() == QSPI_BUSY) |
bcostm | 3:c6b5944187d5 | 658 | { |
bcostm | 3:c6b5944187d5 | 659 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 660 | } |
bcostm | 3:c6b5944187d5 | 661 | |
bcostm | 3:c6b5944187d5 | 662 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 663 | } |
bcostm | 3:c6b5944187d5 | 664 | |
bcostm | 3:c6b5944187d5 | 665 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 666 | } |
bcostm | 3:c6b5944187d5 | 667 | |
bcostm | 3:c6b5944187d5 | 668 | /** |
bcostm | 3:c6b5944187d5 | 669 | * @brief This function enter the QSPI memory in deep power down mode. |
bcostm | 3:c6b5944187d5 | 670 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 671 | */ |
bcostm | 3:c6b5944187d5 | 672 | uint8_t BSP_QSPI_EnterDeepPowerDown(void) |
bcostm | 3:c6b5944187d5 | 673 | { |
bcostm | 3:c6b5944187d5 | 674 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 675 | |
bcostm | 3:c6b5944187d5 | 676 | /* Initialize the deep power down command */ |
bcostm | 3:c6b5944187d5 | 677 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 678 | sCommand.Instruction = DEEP_POWER_DOWN_CMD; |
bcostm | 3:c6b5944187d5 | 679 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 680 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 681 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 682 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 683 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 684 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 685 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 686 | |
bcostm | 3:c6b5944187d5 | 687 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 688 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 689 | { |
bcostm | 3:c6b5944187d5 | 690 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 691 | } |
bcostm | 3:c6b5944187d5 | 692 | |
bcostm | 3:c6b5944187d5 | 693 | /* --- Memory takes 10us max to enter deep power down --- */ |
bcostm | 3:c6b5944187d5 | 694 | /* --- At least 30us should be respected before leaving deep power down --- */ |
bcostm | 3:c6b5944187d5 | 695 | |
bcostm | 3:c6b5944187d5 | 696 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 697 | } |
bcostm | 3:c6b5944187d5 | 698 | |
bcostm | 3:c6b5944187d5 | 699 | /** |
bcostm | 3:c6b5944187d5 | 700 | * @brief This function leave the QSPI memory from deep power down mode. |
bcostm | 3:c6b5944187d5 | 701 | * @retval QSPI memory status |
bcostm | 3:c6b5944187d5 | 702 | */ |
bcostm | 3:c6b5944187d5 | 703 | uint8_t BSP_QSPI_LeaveDeepPowerDown(void) |
bcostm | 3:c6b5944187d5 | 704 | { |
bcostm | 3:c6b5944187d5 | 705 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 706 | |
bcostm | 3:c6b5944187d5 | 707 | /* Initialize the erase command */ |
bcostm | 3:c6b5944187d5 | 708 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 709 | sCommand.Instruction = NO_OPERATION_CMD; |
bcostm | 3:c6b5944187d5 | 710 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 711 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 712 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 713 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 714 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 715 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 716 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 717 | |
bcostm | 3:c6b5944187d5 | 718 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 719 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 720 | { |
bcostm | 3:c6b5944187d5 | 721 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 722 | } |
bcostm | 3:c6b5944187d5 | 723 | |
bcostm | 3:c6b5944187d5 | 724 | /* --- A NOP command is sent to the memory, as the nCS should be low for at least 20 ns --- */ |
bcostm | 3:c6b5944187d5 | 725 | /* --- Memory takes 35us min to leave deep power down --- */ |
bcostm | 3:c6b5944187d5 | 726 | |
bcostm | 3:c6b5944187d5 | 727 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 728 | } |
bcostm | 3:c6b5944187d5 | 729 | |
bcostm | 3:c6b5944187d5 | 730 | /** |
bcostm | 3:c6b5944187d5 | 731 | * @brief Initializes the QSPI MSP. |
bcostm | 3:c6b5944187d5 | 732 | * @retval None |
bcostm | 3:c6b5944187d5 | 733 | */ |
bcostm | 3:c6b5944187d5 | 734 | __weak void BSP_QSPI_MspInit(void) |
bcostm | 3:c6b5944187d5 | 735 | { |
bcostm | 3:c6b5944187d5 | 736 | GPIO_InitTypeDef GPIO_InitStruct; |
bcostm | 3:c6b5944187d5 | 737 | |
bcostm | 3:c6b5944187d5 | 738 | /* Enable the QuadSPI memory interface clock */ |
bcostm | 3:c6b5944187d5 | 739 | __HAL_RCC_QSPI_CLK_ENABLE(); |
bcostm | 3:c6b5944187d5 | 740 | |
bcostm | 3:c6b5944187d5 | 741 | /* Reset the QuadSPI memory interface */ |
bcostm | 3:c6b5944187d5 | 742 | __HAL_RCC_QSPI_FORCE_RESET(); |
bcostm | 3:c6b5944187d5 | 743 | __HAL_RCC_QSPI_RELEASE_RESET(); |
bcostm | 3:c6b5944187d5 | 744 | |
bcostm | 3:c6b5944187d5 | 745 | /* Enable GPIO clocks */ |
bcostm | 3:c6b5944187d5 | 746 | __HAL_RCC_GPIOE_CLK_ENABLE(); |
bcostm | 3:c6b5944187d5 | 747 | |
bcostm | 3:c6b5944187d5 | 748 | /* QSPI CLK, CS, D0, D1, D2 and D3 GPIO pins configuration */ |
bcostm | 3:c6b5944187d5 | 749 | GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\ |
bcostm | 3:c6b5944187d5 | 750 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; |
bcostm | 3:c6b5944187d5 | 751 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
bcostm | 3:c6b5944187d5 | 752 | GPIO_InitStruct.Pull = GPIO_NOPULL; |
bcostm | 3:c6b5944187d5 | 753 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
bcostm | 3:c6b5944187d5 | 754 | GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; |
bcostm | 3:c6b5944187d5 | 755 | HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); |
bcostm | 3:c6b5944187d5 | 756 | } |
bcostm | 3:c6b5944187d5 | 757 | |
bcostm | 3:c6b5944187d5 | 758 | /** |
bcostm | 3:c6b5944187d5 | 759 | * @brief De-Initializes the QSPI MSP. |
bcostm | 3:c6b5944187d5 | 760 | * @retval None |
bcostm | 3:c6b5944187d5 | 761 | */ |
bcostm | 3:c6b5944187d5 | 762 | __weak void BSP_QSPI_MspDeInit(void) |
bcostm | 3:c6b5944187d5 | 763 | { |
bcostm | 3:c6b5944187d5 | 764 | GPIO_InitTypeDef GPIO_InitStruct; |
bcostm | 3:c6b5944187d5 | 765 | |
bcostm | 3:c6b5944187d5 | 766 | /* QSPI CLK, CS, D0-D3 GPIO pins de-configuration */ |
bcostm | 3:c6b5944187d5 | 767 | __HAL_RCC_GPIOE_CLK_ENABLE(); |
bcostm | 3:c6b5944187d5 | 768 | GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\ |
bcostm | 3:c6b5944187d5 | 769 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; |
bcostm | 3:c6b5944187d5 | 770 | |
bcostm | 3:c6b5944187d5 | 771 | HAL_GPIO_DeInit(GPIOE, GPIO_InitStruct.Pin); |
bcostm | 3:c6b5944187d5 | 772 | |
bcostm | 3:c6b5944187d5 | 773 | /* Reset the QuadSPI memory interface */ |
bcostm | 3:c6b5944187d5 | 774 | __HAL_RCC_QSPI_FORCE_RESET(); |
bcostm | 3:c6b5944187d5 | 775 | __HAL_RCC_QSPI_RELEASE_RESET(); |
bcostm | 3:c6b5944187d5 | 776 | |
bcostm | 3:c6b5944187d5 | 777 | /* Disable the QuadSPI memory interface clock */ |
bcostm | 3:c6b5944187d5 | 778 | __HAL_RCC_QSPI_CLK_DISABLE(); |
bcostm | 3:c6b5944187d5 | 779 | } |
bcostm | 3:c6b5944187d5 | 780 | |
bcostm | 3:c6b5944187d5 | 781 | /** |
bcostm | 3:c6b5944187d5 | 782 | * @} |
bcostm | 3:c6b5944187d5 | 783 | */ |
bcostm | 3:c6b5944187d5 | 784 | |
bcostm | 3:c6b5944187d5 | 785 | /** @addtogroup STM32L475E_IOT01_QSPI_Private_Functions |
bcostm | 3:c6b5944187d5 | 786 | * @{ |
bcostm | 3:c6b5944187d5 | 787 | */ |
bcostm | 3:c6b5944187d5 | 788 | |
bcostm | 3:c6b5944187d5 | 789 | /** |
bcostm | 3:c6b5944187d5 | 790 | * @brief This function reset the QSPI memory. |
bcostm | 3:c6b5944187d5 | 791 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 792 | * @retval None |
bcostm | 3:c6b5944187d5 | 793 | */ |
bcostm | 3:c6b5944187d5 | 794 | static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi) |
bcostm | 3:c6b5944187d5 | 795 | { |
bcostm | 3:c6b5944187d5 | 796 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 797 | |
bcostm | 3:c6b5944187d5 | 798 | /* Initialize the reset enable command */ |
bcostm | 3:c6b5944187d5 | 799 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 800 | sCommand.Instruction = RESET_ENABLE_CMD; |
bcostm | 3:c6b5944187d5 | 801 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 802 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 803 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 804 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 805 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 806 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 807 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 808 | |
bcostm | 3:c6b5944187d5 | 809 | /* Send the command */ |
bcostm | 3:c6b5944187d5 | 810 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 811 | { |
bcostm | 3:c6b5944187d5 | 812 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 813 | } |
bcostm | 3:c6b5944187d5 | 814 | |
bcostm | 3:c6b5944187d5 | 815 | /* Send the reset memory command */ |
bcostm | 3:c6b5944187d5 | 816 | sCommand.Instruction = RESET_MEMORY_CMD; |
bcostm | 3:c6b5944187d5 | 817 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 818 | { |
bcostm | 3:c6b5944187d5 | 819 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 820 | } |
bcostm | 3:c6b5944187d5 | 821 | |
bcostm | 3:c6b5944187d5 | 822 | /* Configure automatic polling mode to wait the memory is ready */ |
bcostm | 3:c6b5944187d5 | 823 | if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 824 | { |
bcostm | 3:c6b5944187d5 | 825 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 826 | } |
bcostm | 3:c6b5944187d5 | 827 | |
bcostm | 3:c6b5944187d5 | 828 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 829 | } |
bcostm | 3:c6b5944187d5 | 830 | |
bcostm | 3:c6b5944187d5 | 831 | /** |
bcostm | 3:c6b5944187d5 | 832 | * @brief This function send a Write Enable and wait it is effective. |
bcostm | 3:c6b5944187d5 | 833 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 834 | * @retval None |
bcostm | 3:c6b5944187d5 | 835 | */ |
bcostm | 3:c6b5944187d5 | 836 | static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi) |
bcostm | 3:c6b5944187d5 | 837 | { |
bcostm | 3:c6b5944187d5 | 838 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 839 | QSPI_AutoPollingTypeDef sConfig; |
bcostm | 3:c6b5944187d5 | 840 | |
bcostm | 3:c6b5944187d5 | 841 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 842 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 843 | sCommand.Instruction = WRITE_ENABLE_CMD; |
bcostm | 3:c6b5944187d5 | 844 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 845 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 846 | sCommand.DataMode = QSPI_DATA_NONE; |
bcostm | 3:c6b5944187d5 | 847 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 848 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 849 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 850 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 851 | |
bcostm | 3:c6b5944187d5 | 852 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 853 | { |
bcostm | 3:c6b5944187d5 | 854 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 855 | } |
bcostm | 3:c6b5944187d5 | 856 | |
bcostm | 3:c6b5944187d5 | 857 | /* Configure automatic polling mode to wait for write enabling */ |
bcostm | 3:c6b5944187d5 | 858 | sConfig.Match = MX25R6435F_SR_WEL; |
bcostm | 3:c6b5944187d5 | 859 | sConfig.Mask = MX25R6435F_SR_WEL; |
bcostm | 3:c6b5944187d5 | 860 | sConfig.MatchMode = QSPI_MATCH_MODE_AND; |
bcostm | 3:c6b5944187d5 | 861 | sConfig.StatusBytesSize = 1; |
bcostm | 3:c6b5944187d5 | 862 | sConfig.Interval = 0x10; |
bcostm | 3:c6b5944187d5 | 863 | sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; |
bcostm | 3:c6b5944187d5 | 864 | |
bcostm | 3:c6b5944187d5 | 865 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 866 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 867 | |
bcostm | 3:c6b5944187d5 | 868 | if (HAL_QSPI_AutoPolling(&QSPIHandle, &sCommand, &sConfig, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 869 | { |
bcostm | 3:c6b5944187d5 | 870 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 871 | } |
bcostm | 3:c6b5944187d5 | 872 | |
bcostm | 3:c6b5944187d5 | 873 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 874 | } |
bcostm | 3:c6b5944187d5 | 875 | |
bcostm | 3:c6b5944187d5 | 876 | /** |
bcostm | 3:c6b5944187d5 | 877 | * @brief This function read the SR of the memory and wait the EOP. |
bcostm | 3:c6b5944187d5 | 878 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 879 | * @param Timeout : Timeout for auto-polling |
bcostm | 3:c6b5944187d5 | 880 | * @retval None |
bcostm | 3:c6b5944187d5 | 881 | */ |
bcostm | 3:c6b5944187d5 | 882 | static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) |
bcostm | 3:c6b5944187d5 | 883 | { |
bcostm | 3:c6b5944187d5 | 884 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 885 | QSPI_AutoPollingTypeDef sConfig; |
bcostm | 3:c6b5944187d5 | 886 | |
bcostm | 3:c6b5944187d5 | 887 | /* Configure automatic polling mode to wait for memory ready */ |
bcostm | 3:c6b5944187d5 | 888 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 889 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 890 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 891 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 892 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 893 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 894 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 895 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 896 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 897 | |
bcostm | 3:c6b5944187d5 | 898 | sConfig.Match = 0; |
bcostm | 3:c6b5944187d5 | 899 | sConfig.Mask = MX25R6435F_SR_WIP; |
bcostm | 3:c6b5944187d5 | 900 | sConfig.MatchMode = QSPI_MATCH_MODE_AND; |
bcostm | 3:c6b5944187d5 | 901 | sConfig.StatusBytesSize = 1; |
bcostm | 3:c6b5944187d5 | 902 | sConfig.Interval = 0x10; |
bcostm | 3:c6b5944187d5 | 903 | sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; |
bcostm | 3:c6b5944187d5 | 904 | |
bcostm | 3:c6b5944187d5 | 905 | if (HAL_QSPI_AutoPolling(&QSPIHandle, &sCommand, &sConfig, Timeout) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 906 | { |
bcostm | 3:c6b5944187d5 | 907 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 908 | } |
bcostm | 3:c6b5944187d5 | 909 | |
bcostm | 3:c6b5944187d5 | 910 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 911 | } |
bcostm | 3:c6b5944187d5 | 912 | |
bcostm | 3:c6b5944187d5 | 913 | /** |
bcostm | 3:c6b5944187d5 | 914 | * @brief This function enables/disables the Quad mode of the memory. |
bcostm | 3:c6b5944187d5 | 915 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 916 | * @param Operation : QSPI_QUAD_ENABLE or QSPI_QUAD_DISABLE mode |
bcostm | 3:c6b5944187d5 | 917 | * @retval None |
bcostm | 3:c6b5944187d5 | 918 | */ |
bcostm | 3:c6b5944187d5 | 919 | static uint8_t QSPI_QuadMode(QSPI_HandleTypeDef *hqspi, uint8_t Operation) |
bcostm | 3:c6b5944187d5 | 920 | { |
bcostm | 3:c6b5944187d5 | 921 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 922 | uint8_t reg; |
bcostm | 3:c6b5944187d5 | 923 | |
bcostm | 3:c6b5944187d5 | 924 | /* Read status register */ |
bcostm | 3:c6b5944187d5 | 925 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 926 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 927 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 928 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 929 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 930 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 931 | sCommand.NbData = 1; |
bcostm | 3:c6b5944187d5 | 932 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 933 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 934 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 935 | |
bcostm | 3:c6b5944187d5 | 936 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 937 | { |
bcostm | 3:c6b5944187d5 | 938 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 939 | } |
bcostm | 3:c6b5944187d5 | 940 | |
bcostm | 3:c6b5944187d5 | 941 | if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 942 | { |
bcostm | 3:c6b5944187d5 | 943 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 944 | } |
bcostm | 3:c6b5944187d5 | 945 | |
bcostm | 3:c6b5944187d5 | 946 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 947 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 948 | { |
bcostm | 3:c6b5944187d5 | 949 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 950 | } |
bcostm | 3:c6b5944187d5 | 951 | |
bcostm | 3:c6b5944187d5 | 952 | /* Activate/deactivate the Quad mode */ |
bcostm | 3:c6b5944187d5 | 953 | if (Operation == QSPI_QUAD_ENABLE) |
bcostm | 3:c6b5944187d5 | 954 | { |
bcostm | 3:c6b5944187d5 | 955 | SET_BIT(reg, MX25R6435F_SR_QE); |
bcostm | 3:c6b5944187d5 | 956 | } |
bcostm | 3:c6b5944187d5 | 957 | else |
bcostm | 3:c6b5944187d5 | 958 | { |
bcostm | 3:c6b5944187d5 | 959 | CLEAR_BIT(reg, MX25R6435F_SR_QE); |
bcostm | 3:c6b5944187d5 | 960 | } |
bcostm | 3:c6b5944187d5 | 961 | |
bcostm | 3:c6b5944187d5 | 962 | sCommand.Instruction = WRITE_STATUS_CFG_REG_CMD; |
bcostm | 3:c6b5944187d5 | 963 | |
bcostm | 3:c6b5944187d5 | 964 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 965 | { |
bcostm | 3:c6b5944187d5 | 966 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 967 | } |
bcostm | 3:c6b5944187d5 | 968 | |
bcostm | 3:c6b5944187d5 | 969 | if (HAL_QSPI_Transmit(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 970 | { |
bcostm | 3:c6b5944187d5 | 971 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 972 | } |
bcostm | 3:c6b5944187d5 | 973 | |
bcostm | 3:c6b5944187d5 | 974 | /* Wait that memory is ready */ |
bcostm | 3:c6b5944187d5 | 975 | if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 976 | { |
bcostm | 3:c6b5944187d5 | 977 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 978 | } |
bcostm | 3:c6b5944187d5 | 979 | |
bcostm | 3:c6b5944187d5 | 980 | /* Check the configuration has been correctly done */ |
bcostm | 3:c6b5944187d5 | 981 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 982 | |
bcostm | 3:c6b5944187d5 | 983 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 984 | { |
bcostm | 3:c6b5944187d5 | 985 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 986 | } |
bcostm | 3:c6b5944187d5 | 987 | |
bcostm | 3:c6b5944187d5 | 988 | if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 989 | { |
bcostm | 3:c6b5944187d5 | 990 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 991 | } |
bcostm | 3:c6b5944187d5 | 992 | |
bcostm | 3:c6b5944187d5 | 993 | if ((((reg & MX25R6435F_SR_QE) == 0) && (Operation == QSPI_QUAD_ENABLE)) || |
bcostm | 3:c6b5944187d5 | 994 | (((reg & MX25R6435F_SR_QE) != 0) && (Operation == QSPI_QUAD_DISABLE))) |
bcostm | 3:c6b5944187d5 | 995 | { |
bcostm | 3:c6b5944187d5 | 996 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 997 | } |
bcostm | 3:c6b5944187d5 | 998 | |
bcostm | 3:c6b5944187d5 | 999 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 1000 | } |
bcostm | 3:c6b5944187d5 | 1001 | |
bcostm | 3:c6b5944187d5 | 1002 | /** |
bcostm | 3:c6b5944187d5 | 1003 | * @brief This function enables/disables the high performance mode of the memory. |
bcostm | 3:c6b5944187d5 | 1004 | * @param hqspi : QSPI handle |
bcostm | 3:c6b5944187d5 | 1005 | * @param Operation : QSPI_HIGH_PERF_ENABLE or QSPI_HIGH_PERF_DISABLE high performance mode |
bcostm | 3:c6b5944187d5 | 1006 | * @retval None |
bcostm | 3:c6b5944187d5 | 1007 | */ |
bcostm | 3:c6b5944187d5 | 1008 | static uint8_t QSPI_HighPerfMode(QSPI_HandleTypeDef *hqspi, uint8_t Operation) |
bcostm | 3:c6b5944187d5 | 1009 | { |
bcostm | 3:c6b5944187d5 | 1010 | QSPI_CommandTypeDef sCommand; |
bcostm | 3:c6b5944187d5 | 1011 | uint8_t reg[3]; |
bcostm | 3:c6b5944187d5 | 1012 | |
bcostm | 3:c6b5944187d5 | 1013 | /* Read status register */ |
bcostm | 3:c6b5944187d5 | 1014 | sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
bcostm | 3:c6b5944187d5 | 1015 | sCommand.Instruction = READ_STATUS_REG_CMD; |
bcostm | 3:c6b5944187d5 | 1016 | sCommand.AddressMode = QSPI_ADDRESS_NONE; |
bcostm | 3:c6b5944187d5 | 1017 | sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
bcostm | 3:c6b5944187d5 | 1018 | sCommand.DataMode = QSPI_DATA_1_LINE; |
bcostm | 3:c6b5944187d5 | 1019 | sCommand.DummyCycles = 0; |
bcostm | 3:c6b5944187d5 | 1020 | sCommand.NbData = 1; |
bcostm | 3:c6b5944187d5 | 1021 | sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; |
bcostm | 3:c6b5944187d5 | 1022 | sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
bcostm | 3:c6b5944187d5 | 1023 | sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
bcostm | 3:c6b5944187d5 | 1024 | |
bcostm | 3:c6b5944187d5 | 1025 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1026 | { |
bcostm | 3:c6b5944187d5 | 1027 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1028 | } |
bcostm | 3:c6b5944187d5 | 1029 | |
bcostm | 3:c6b5944187d5 | 1030 | if (HAL_QSPI_Receive(&QSPIHandle, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1031 | { |
bcostm | 3:c6b5944187d5 | 1032 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1033 | } |
bcostm | 3:c6b5944187d5 | 1034 | |
bcostm | 3:c6b5944187d5 | 1035 | /* Read configuration registers */ |
bcostm | 3:c6b5944187d5 | 1036 | sCommand.Instruction = READ_CFG_REG_CMD; |
bcostm | 3:c6b5944187d5 | 1037 | sCommand.NbData = 2; |
bcostm | 3:c6b5944187d5 | 1038 | |
bcostm | 3:c6b5944187d5 | 1039 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1040 | { |
bcostm | 3:c6b5944187d5 | 1041 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1042 | } |
bcostm | 3:c6b5944187d5 | 1043 | |
bcostm | 3:c6b5944187d5 | 1044 | if (HAL_QSPI_Receive(&QSPIHandle, &(reg[1]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1045 | { |
bcostm | 3:c6b5944187d5 | 1046 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1047 | } |
bcostm | 3:c6b5944187d5 | 1048 | |
bcostm | 3:c6b5944187d5 | 1049 | /* Enable write operations */ |
bcostm | 3:c6b5944187d5 | 1050 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 1051 | { |
bcostm | 3:c6b5944187d5 | 1052 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1053 | } |
bcostm | 3:c6b5944187d5 | 1054 | |
bcostm | 3:c6b5944187d5 | 1055 | /* Activate/deactivate the Quad mode */ |
bcostm | 3:c6b5944187d5 | 1056 | if (Operation == QSPI_HIGH_PERF_ENABLE) |
bcostm | 3:c6b5944187d5 | 1057 | { |
bcostm | 3:c6b5944187d5 | 1058 | SET_BIT(reg[2], MX25R6435F_CR2_LH_SWITCH); |
bcostm | 3:c6b5944187d5 | 1059 | } |
bcostm | 3:c6b5944187d5 | 1060 | else |
bcostm | 3:c6b5944187d5 | 1061 | { |
bcostm | 3:c6b5944187d5 | 1062 | CLEAR_BIT(reg[2], MX25R6435F_CR2_LH_SWITCH); |
bcostm | 3:c6b5944187d5 | 1063 | } |
bcostm | 3:c6b5944187d5 | 1064 | |
bcostm | 3:c6b5944187d5 | 1065 | sCommand.Instruction = WRITE_STATUS_CFG_REG_CMD; |
bcostm | 3:c6b5944187d5 | 1066 | sCommand.NbData = 3; |
bcostm | 3:c6b5944187d5 | 1067 | |
bcostm | 3:c6b5944187d5 | 1068 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1069 | { |
bcostm | 3:c6b5944187d5 | 1070 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1071 | } |
bcostm | 3:c6b5944187d5 | 1072 | |
bcostm | 3:c6b5944187d5 | 1073 | if (HAL_QSPI_Transmit(&QSPIHandle, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1074 | { |
bcostm | 3:c6b5944187d5 | 1075 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1076 | } |
bcostm | 3:c6b5944187d5 | 1077 | |
bcostm | 3:c6b5944187d5 | 1078 | /* Wait that memory is ready */ |
bcostm | 3:c6b5944187d5 | 1079 | if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
bcostm | 3:c6b5944187d5 | 1080 | { |
bcostm | 3:c6b5944187d5 | 1081 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1082 | } |
bcostm | 3:c6b5944187d5 | 1083 | |
bcostm | 3:c6b5944187d5 | 1084 | /* Check the configuration has been correctly done */ |
bcostm | 3:c6b5944187d5 | 1085 | sCommand.Instruction = READ_CFG_REG_CMD; |
bcostm | 3:c6b5944187d5 | 1086 | sCommand.NbData = 2; |
bcostm | 3:c6b5944187d5 | 1087 | |
bcostm | 3:c6b5944187d5 | 1088 | if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1089 | { |
bcostm | 3:c6b5944187d5 | 1090 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1091 | } |
bcostm | 3:c6b5944187d5 | 1092 | |
bcostm | 3:c6b5944187d5 | 1093 | if (HAL_QSPI_Receive(&QSPIHandle, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
bcostm | 3:c6b5944187d5 | 1094 | { |
bcostm | 3:c6b5944187d5 | 1095 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1096 | } |
bcostm | 3:c6b5944187d5 | 1097 | |
bcostm | 3:c6b5944187d5 | 1098 | if ((((reg[1] & MX25R6435F_CR2_LH_SWITCH) == 0) && (Operation == QSPI_HIGH_PERF_ENABLE)) || |
bcostm | 3:c6b5944187d5 | 1099 | (((reg[1] & MX25R6435F_CR2_LH_SWITCH) != 0) && (Operation == QSPI_HIGH_PERF_DISABLE))) |
bcostm | 3:c6b5944187d5 | 1100 | { |
bcostm | 3:c6b5944187d5 | 1101 | return QSPI_ERROR; |
bcostm | 3:c6b5944187d5 | 1102 | } |
bcostm | 3:c6b5944187d5 | 1103 | |
bcostm | 3:c6b5944187d5 | 1104 | return QSPI_OK; |
bcostm | 3:c6b5944187d5 | 1105 | } |
bcostm | 3:c6b5944187d5 | 1106 | |
bcostm | 3:c6b5944187d5 | 1107 | /** |
bcostm | 3:c6b5944187d5 | 1108 | * @} |
bcostm | 3:c6b5944187d5 | 1109 | */ |
bcostm | 3:c6b5944187d5 | 1110 | |
bcostm | 3:c6b5944187d5 | 1111 | /** |
bcostm | 3:c6b5944187d5 | 1112 | * @} |
bcostm | 3:c6b5944187d5 | 1113 | */ |
bcostm | 3:c6b5944187d5 | 1114 | |
bcostm | 3:c6b5944187d5 | 1115 | /** |
bcostm | 3:c6b5944187d5 | 1116 | * @} |
bcostm | 3:c6b5944187d5 | 1117 | */ |
bcostm | 3:c6b5944187d5 | 1118 | |
bcostm | 3:c6b5944187d5 | 1119 | /** |
bcostm | 3:c6b5944187d5 | 1120 | * @} |
bcostm | 3:c6b5944187d5 | 1121 | */ |
bcostm | 3:c6b5944187d5 | 1122 | |
bcostm | 3:c6b5944187d5 | 1123 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
bcostm | 3:c6b5944187d5 | 1124 |