RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Thu Mar 10 04:21:24 2016 +0000
Revision:
9:37222d6ece56
Parent:
5:1390bfcb667c
Document updates

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:702bf7b2b7d8 1 /*******************************************************************************
dkato 0:702bf7b2b7d8 2 * DISCLAIMER
dkato 0:702bf7b2b7d8 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:702bf7b2b7d8 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:702bf7b2b7d8 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:702bf7b2b7d8 6 * all applicable laws, including copyright laws.
dkato 0:702bf7b2b7d8 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:702bf7b2b7d8 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:702bf7b2b7d8 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:702bf7b2b7d8 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:702bf7b2b7d8 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:702bf7b2b7d8 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:702bf7b2b7d8 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:702bf7b2b7d8 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:702bf7b2b7d8 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:702bf7b2b7d8 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:702bf7b2b7d8 17 * and to discontinue the availability of this software. By using this software,
dkato 0:702bf7b2b7d8 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:702bf7b2b7d8 19 * following link:
dkato 0:702bf7b2b7d8 20 * http://www.renesas.com/disclaimer*
dkato 0:702bf7b2b7d8 21 * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
dkato 0:702bf7b2b7d8 22 *******************************************************************************/
dkato 0:702bf7b2b7d8 23
dkato 0:702bf7b2b7d8 24 /**************************************************************************//**
dkato 0:702bf7b2b7d8 25 * @file dma_if.c
dkato 5:1390bfcb667c 26 * $Rev: 1674 $
dkato 5:1390bfcb667c 27 * $Date:: 2015-05-29 16:35:57 +0900#$
dkato 0:702bf7b2b7d8 28 * @brief DMA Driver interface functions
dkato 0:702bf7b2b7d8 29 ******************************************************************************/
dkato 0:702bf7b2b7d8 30
dkato 0:702bf7b2b7d8 31 /*****************************************************************************
dkato 0:702bf7b2b7d8 32 * History : DD.MM.YYYY Version Description
dkato 0:702bf7b2b7d8 33 * : 15.01.2013 1.00 First Release
dkato 0:702bf7b2b7d8 34 ******************************************************************************/
dkato 0:702bf7b2b7d8 35
dkato 0:702bf7b2b7d8 36 /*******************************************************************************
dkato 0:702bf7b2b7d8 37 Includes <System Includes>, "Project Includes"
dkato 0:702bf7b2b7d8 38 *******************************************************************************/
dkato 0:702bf7b2b7d8 39
dkato 0:702bf7b2b7d8 40 #include "dma.h"
dkato 0:702bf7b2b7d8 41
dkato 0:702bf7b2b7d8 42 /******************************************************************************
dkato 0:702bf7b2b7d8 43 Private global tables
dkato 0:702bf7b2b7d8 44 ******************************************************************************/
dkato 0:702bf7b2b7d8 45
dkato 9:37222d6ece56 46 /**************************************************************************//**
dkato 0:702bf7b2b7d8 47 * Function Name: R_DMA_Init
dkato 9:37222d6ece56 48 * @brie Init DMA driver.
dkato 9:37222d6ece56 49 * Check parameter in this function.
dkato 9:37222d6ece56 50 *
dkato 9:37222d6ece56 51 * Description:<br>
dkato 9:37222d6ece56 52 *
dkato 9:37222d6ece56 53 * @param[in] p_dma_init_param :Point of driver init parameter.
dkato 9:37222d6ece56 54 * @param[in,out] p_errno :Pointer of error code.
dkato 9:37222d6ece56 55 * When pointer is NULL, it isn't set error code.
dkato 9:37222d6ece56 56 * error code -
dkato 9:37222d6ece56 57 * OS error num : Registering handler failed.
dkato 9:37222d6ece56 58 * EPERM : Pointer of callback function which called in DMA
dkato 9:37222d6ece56 59 * error interrupt handler is NULL.
dkato 9:37222d6ece56 60 * EFAULT : dma_init_param is NULL.
dkato 9:37222d6ece56 61 * @retval ESUCCESS -
dkato 0:702bf7b2b7d8 62 * Operation successful.
dkato 0:702bf7b2b7d8 63 * EERROR -
dkato 0:702bf7b2b7d8 64 * Error occured.
dkato 0:702bf7b2b7d8 65 ******************************************************************************/
dkato 0:702bf7b2b7d8 66
dkato 0:702bf7b2b7d8 67 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 68 int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 69 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 70 {
dkato 0:702bf7b2b7d8 71 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 72 int_t result_init;
dkato 5:1390bfcb667c 73 int_t was_masked;
dkato 0:702bf7b2b7d8 74
dkato 0:702bf7b2b7d8 75 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 76
dkato 0:702bf7b2b7d8 77 if (NULL == p_dma_init_param)
dkato 0:702bf7b2b7d8 78 {
dkato 0:702bf7b2b7d8 79 /* set error return value */
dkato 0:702bf7b2b7d8 80 retval = (EERROR);
dkato 0:702bf7b2b7d8 81 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 82 }
dkato 0:702bf7b2b7d8 83
dkato 0:702bf7b2b7d8 84 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 85 {
dkato 0:702bf7b2b7d8 86 /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
dkato 0:702bf7b2b7d8 87 if (NULL == p_dma_init_param->p_aio)
dkato 0:702bf7b2b7d8 88 /* <-MISRA 1.2 */
dkato 0:702bf7b2b7d8 89 {
dkato 0:702bf7b2b7d8 90 /* set error return value */
dkato 0:702bf7b2b7d8 91 retval = (EERROR);
dkato 0:702bf7b2b7d8 92 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 93 }
dkato 0:702bf7b2b7d8 94 }
dkato 0:702bf7b2b7d8 95
dkato 5:1390bfcb667c 96 /* disable all irq */
dkato 5:1390bfcb667c 97 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 98 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 99 #else
dkato 5:1390bfcb667c 100 was_masked = __disable_irq();
dkato 5:1390bfcb667c 101 #endif
dkato 5:1390bfcb667c 102
dkato 0:702bf7b2b7d8 103 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 104 {
dkato 5:1390bfcb667c 105 result_init = DMA_Initialize(p_dma_init_param);
dkato 0:702bf7b2b7d8 106 if (ESUCCESS != result_init)
dkato 0:702bf7b2b7d8 107 {
dkato 0:702bf7b2b7d8 108 /* set error return value */
dkato 0:702bf7b2b7d8 109 retval = (EERROR);
dkato 0:702bf7b2b7d8 110 DMA_SetErrCode(result_init, p_errno);
dkato 0:702bf7b2b7d8 111 }
dkato 0:702bf7b2b7d8 112 }
dkato 0:702bf7b2b7d8 113
dkato 5:1390bfcb667c 114 if (0 == was_masked)
dkato 5:1390bfcb667c 115 {
dkato 5:1390bfcb667c 116 __enable_irq();
dkato 5:1390bfcb667c 117 }
dkato 5:1390bfcb667c 118
dkato 0:702bf7b2b7d8 119 return retval;
dkato 0:702bf7b2b7d8 120 }
dkato 0:702bf7b2b7d8 121
dkato 0:702bf7b2b7d8 122 /******************************************************************************
dkato 0:702bf7b2b7d8 123 End of function R_DMA_Init
dkato 0:702bf7b2b7d8 124 ******************************************************************************/
dkato 0:702bf7b2b7d8 125
dkato 9:37222d6ece56 126 /**************************************************************************//**
dkato 0:702bf7b2b7d8 127 * Function Name: R_DMA_UnInit
dkato 9:37222d6ece56 128 * @brie UnInit DMA driver.
dkato 9:37222d6ece56 129 * Check parameter in this function.
dkato 9:37222d6ece56 130 *
dkato 9:37222d6ece56 131 * Description:<br>
dkato 9:37222d6ece56 132 *
dkato 9:37222d6ece56 133 * @param[in,out] p_errno :Pointer of error code
dkato 9:37222d6ece56 134 * When pointer is NULL, it isn't set error code.
dkato 9:37222d6ece56 135 * error code -
dkato 9:37222d6ece56 136 * OS error num : Unegistering handler failed.
dkato 9:37222d6ece56 137 * EACCES : Driver status isn't DMA_DRV_INIT.
dkato 9:37222d6ece56 138 * EBUSY : It has been allocated already in channel.
dkato 9:37222d6ece56 139 * EFAULT : Channel status is besides the status definded in dma_stat_ch_t.
dkato 9:37222d6ece56 140 * @retval ESUCCESS -
dkato 0:702bf7b2b7d8 141 * Operation successful.
dkato 0:702bf7b2b7d8 142 * EERROR -
dkato 0:702bf7b2b7d8 143 * Error occured.
dkato 0:702bf7b2b7d8 144 ******************************************************************************/
dkato 0:702bf7b2b7d8 145
dkato 0:702bf7b2b7d8 146 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 147 int_t R_DMA_UnInit(int32_t * const p_errno)
dkato 0:702bf7b2b7d8 148 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 149 {
dkato 0:702bf7b2b7d8 150 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 151 int_t result_uninit;
dkato 0:702bf7b2b7d8 152 dma_info_drv_t *dma_info_drv;
dkato 0:702bf7b2b7d8 153 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 154 int_t ch_count;
dkato 0:702bf7b2b7d8 155 bool_t ch_stat_check_flag;
dkato 5:1390bfcb667c 156 int_t was_masked;
dkato 0:702bf7b2b7d8 157
dkato 0:702bf7b2b7d8 158 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 159
dkato 0:702bf7b2b7d8 160 dma_info_drv = DMA_GetDrvInstance();
dkato 0:702bf7b2b7d8 161
dkato 5:1390bfcb667c 162 /* disable all irq */
dkato 5:1390bfcb667c 163 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 164 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 165 #else
dkato 5:1390bfcb667c 166 was_masked = __disable_irq();
dkato 5:1390bfcb667c 167 #endif
dkato 5:1390bfcb667c 168
dkato 0:702bf7b2b7d8 169 /* check driver status */
dkato 0:702bf7b2b7d8 170 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 171 {
dkato 0:702bf7b2b7d8 172 if (DMA_DRV_INIT != dma_info_drv->drv_stat)
dkato 0:702bf7b2b7d8 173 {
dkato 0:702bf7b2b7d8 174 /* set error return value */
dkato 0:702bf7b2b7d8 175 retval = EERROR;
dkato 0:702bf7b2b7d8 176 DMA_SetErrCode(EACCES, p_errno);
dkato 0:702bf7b2b7d8 177 }
dkato 0:702bf7b2b7d8 178 else
dkato 0:702bf7b2b7d8 179 {
dkato 0:702bf7b2b7d8 180 ch_stat_check_flag = false;
dkato 0:702bf7b2b7d8 181 ch_count = 0;
dkato 0:702bf7b2b7d8 182 while (false == ch_stat_check_flag)
dkato 0:702bf7b2b7d8 183 {
dkato 0:702bf7b2b7d8 184 /* check channel status */
dkato 0:702bf7b2b7d8 185 dma_info_ch = DMA_GetDrvChInfo(ch_count);
dkato 0:702bf7b2b7d8 186 if ((DMA_CH_UNINIT != dma_info_ch->ch_stat) &&
dkato 0:702bf7b2b7d8 187 (DMA_CH_INIT != dma_info_ch->ch_stat))
dkato 0:702bf7b2b7d8 188 {
dkato 0:702bf7b2b7d8 189 /* set error return value */
dkato 0:702bf7b2b7d8 190 retval = EERROR;
dkato 0:702bf7b2b7d8 191 /* check channel status is busy */
dkato 0:702bf7b2b7d8 192 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 193 {
dkato 0:702bf7b2b7d8 194 /* These 2 cases are intentionally combined. */
dkato 0:702bf7b2b7d8 195 case DMA_CH_OPEN:
dkato 0:702bf7b2b7d8 196 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 197 DMA_SetErrCode(EBUSY, p_errno);
dkato 0:702bf7b2b7d8 198 break;
dkato 0:702bf7b2b7d8 199
dkato 0:702bf7b2b7d8 200 default:
dkato 0:702bf7b2b7d8 201 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 202 break;
dkato 0:702bf7b2b7d8 203 }
dkato 0:702bf7b2b7d8 204 }
dkato 0:702bf7b2b7d8 205
dkato 0:702bf7b2b7d8 206 if ((DMA_CH_NUM - 1) == ch_count)
dkato 0:702bf7b2b7d8 207 {
dkato 0:702bf7b2b7d8 208 /* channel status check end */
dkato 0:702bf7b2b7d8 209 ch_stat_check_flag = true;
dkato 0:702bf7b2b7d8 210 }
dkato 0:702bf7b2b7d8 211 ch_count++;
dkato 0:702bf7b2b7d8 212 }
dkato 0:702bf7b2b7d8 213 }
dkato 0:702bf7b2b7d8 214 /* uninitialize DMA */
dkato 0:702bf7b2b7d8 215 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 216 {
dkato 0:702bf7b2b7d8 217 result_uninit = DMA_UnInitialize();
dkato 0:702bf7b2b7d8 218 if (ESUCCESS != result_uninit)
dkato 0:702bf7b2b7d8 219 {
dkato 0:702bf7b2b7d8 220 /* set error return value */
dkato 0:702bf7b2b7d8 221 retval = EERROR;
dkato 0:702bf7b2b7d8 222 DMA_SetErrCode(result_uninit, p_errno);
dkato 0:702bf7b2b7d8 223 }
dkato 0:702bf7b2b7d8 224 }
dkato 0:702bf7b2b7d8 225 }
dkato 0:702bf7b2b7d8 226
dkato 5:1390bfcb667c 227 if (0 == was_masked)
dkato 5:1390bfcb667c 228 {
dkato 5:1390bfcb667c 229 __enable_irq();
dkato 5:1390bfcb667c 230 }
dkato 5:1390bfcb667c 231
dkato 0:702bf7b2b7d8 232 return retval;
dkato 0:702bf7b2b7d8 233 }
dkato 0:702bf7b2b7d8 234
dkato 0:702bf7b2b7d8 235 /******************************************************************************
dkato 0:702bf7b2b7d8 236 End of function R_DMA_UnInit
dkato 0:702bf7b2b7d8 237 ******************************************************************************/
dkato 0:702bf7b2b7d8 238
dkato 9:37222d6ece56 239 /**************************************************************************//**
dkato 0:702bf7b2b7d8 240 * Function Name: R_DMA_Alloc
dkato 9:37222d6ece56 241 * @brie Open DMA channel.
dkato 9:37222d6ece56 242 * Check parameter in this function mainly.
dkato 9:37222d6ece56 243 *
dkato 9:37222d6ece56 244 * Description:<br>
dkato 9:37222d6ece56 245 *
dkato 9:37222d6ece56 246 * @param[in] channel :Open channel number.
dkato 9:37222d6ece56 247 * If channel is (-1), it looking for free chanel and allocate.
dkato 9:37222d6ece56 248 * @param[in,out] p_errno :Pointer of error code
dkato 9:37222d6ece56 249 * When pointer is NULL, it isn't set error code.
dkato 9:37222d6ece56 250 * error code -
dkato 9:37222d6ece56 251 * EINVAL : Value of the ch is outside the range of DMA_ALLOC_CH(-1) <= ch < DMA_CH_NUM.
dkato 9:37222d6ece56 252 * EACCES : Driver status isn't DMA_DRV_INIT.
dkato 9:37222d6ece56 253 * EBUSY : It has been allocated already in channel.
dkato 9:37222d6ece56 254 * EMFILE : When looking for a free channel, but a free channel didn't exist.
dkato 9:37222d6ece56 255 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 9:37222d6ece56 256 * EFAULT: Channel status is besides the status definded in dma_stat_ch_t.
dkato 9:37222d6ece56 257 * @retval ESUCCESS -
dkato 0:702bf7b2b7d8 258 * Operation successful.
dkato 0:702bf7b2b7d8 259 * EERROR -
dkato 0:702bf7b2b7d8 260 * Error occured.
dkato 0:702bf7b2b7d8 261 ******************************************************************************/
dkato 0:702bf7b2b7d8 262
dkato 0:702bf7b2b7d8 263 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 264 int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 265 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 266 {
dkato 0:702bf7b2b7d8 267 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 268 int_t ercd = ESUCCESS;
dkato 0:702bf7b2b7d8 269 int_t get_ch_num;
dkato 0:702bf7b2b7d8 270 dma_info_drv_t *dma_info_drv;
dkato 5:1390bfcb667c 271 int_t was_masked;
dkato 0:702bf7b2b7d8 272
dkato 0:702bf7b2b7d8 273 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 274
dkato 0:702bf7b2b7d8 275 /* check driver status */
dkato 0:702bf7b2b7d8 276 dma_info_drv = DMA_GetDrvInstance();
dkato 0:702bf7b2b7d8 277
dkato 5:1390bfcb667c 278 /* disable all irq */
dkato 5:1390bfcb667c 279 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 280 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 281 #else
dkato 5:1390bfcb667c 282 was_masked = __disable_irq();
dkato 5:1390bfcb667c 283 #endif
dkato 5:1390bfcb667c 284
dkato 0:702bf7b2b7d8 285 if (ESUCCESS == ercd)
dkato 0:702bf7b2b7d8 286 {
dkato 0:702bf7b2b7d8 287 if (DMA_DRV_INIT != dma_info_drv->drv_stat)
dkato 0:702bf7b2b7d8 288 {
dkato 0:702bf7b2b7d8 289 /* set error return value */
dkato 0:702bf7b2b7d8 290 ercd = EACCES;
dkato 0:702bf7b2b7d8 291 }
dkato 0:702bf7b2b7d8 292 else
dkato 0:702bf7b2b7d8 293 {
dkato 0:702bf7b2b7d8 294 /* check channel of argment */
dkato 0:702bf7b2b7d8 295 if ((DMA_ALLOC_CH <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 296 {
dkato 0:702bf7b2b7d8 297 if (DMA_ALLOC_CH == channel)
dkato 0:702bf7b2b7d8 298 {
dkato 0:702bf7b2b7d8 299 get_ch_num = DMA_GetFreeChannel();
dkato 0:702bf7b2b7d8 300 }
dkato 0:702bf7b2b7d8 301 else
dkato 0:702bf7b2b7d8 302 {
dkato 0:702bf7b2b7d8 303 get_ch_num = DMA_GetFixedChannel(channel);
dkato 0:702bf7b2b7d8 304 }
dkato 0:702bf7b2b7d8 305
dkato 0:702bf7b2b7d8 306 /* check return number or error number */
dkato 0:702bf7b2b7d8 307 if ((DMA_ALLOC_CH < get_ch_num) && (get_ch_num < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 308 {
dkato 0:702bf7b2b7d8 309 /* set channel number to return value */
dkato 0:702bf7b2b7d8 310 retval = get_ch_num;
dkato 0:702bf7b2b7d8 311 }
dkato 0:702bf7b2b7d8 312 else
dkato 0:702bf7b2b7d8 313 {
dkato 0:702bf7b2b7d8 314 /* set error code to error value */
dkato 0:702bf7b2b7d8 315 ercd = get_ch_num;
dkato 0:702bf7b2b7d8 316 }
dkato 0:702bf7b2b7d8 317 }
dkato 0:702bf7b2b7d8 318 else
dkato 0:702bf7b2b7d8 319 {
dkato 0:702bf7b2b7d8 320 /* set error return value */
dkato 0:702bf7b2b7d8 321 ercd = EINVAL;
dkato 0:702bf7b2b7d8 322 }
dkato 0:702bf7b2b7d8 323 }
dkato 0:702bf7b2b7d8 324 }
dkato 0:702bf7b2b7d8 325
dkato 0:702bf7b2b7d8 326 /* occured error check */
dkato 0:702bf7b2b7d8 327 if (ESUCCESS != ercd)
dkato 0:702bf7b2b7d8 328 {
dkato 0:702bf7b2b7d8 329 retval = EERROR;
dkato 0:702bf7b2b7d8 330 DMA_SetErrCode(ercd, p_errno);
dkato 0:702bf7b2b7d8 331 }
dkato 0:702bf7b2b7d8 332
dkato 5:1390bfcb667c 333 if (0 == was_masked)
dkato 5:1390bfcb667c 334 {
dkato 5:1390bfcb667c 335 __enable_irq();
dkato 5:1390bfcb667c 336 }
dkato 5:1390bfcb667c 337
dkato 0:702bf7b2b7d8 338 return retval;
dkato 0:702bf7b2b7d8 339 }
dkato 0:702bf7b2b7d8 340
dkato 0:702bf7b2b7d8 341 /******************************************************************************
dkato 0:702bf7b2b7d8 342 End of function R_DMA_Alloc
dkato 0:702bf7b2b7d8 343 ******************************************************************************/
dkato 0:702bf7b2b7d8 344
dkato 9:37222d6ece56 345 /**************************************************************************//**
dkato 0:702bf7b2b7d8 346 * Function Name: R_DMA_Free
dkato 9:37222d6ece56 347 * @brie Close DMA channel.
dkato 9:37222d6ece56 348 * Check parameter in this function mainly.
dkato 9:37222d6ece56 349 *
dkato 9:37222d6ece56 350 * Description:<br>
dkato 9:37222d6ece56 351 *
dkato 9:37222d6ece56 352 * @param[in] channel :Close channel number.
dkato 9:37222d6ece56 353 * @param[in,out] p_errno :Pointer of error code
dkato 9:37222d6ece56 354 * When pointer is NULL, it isn't set error code.
dkato 9:37222d6ece56 355 * error code -
dkato 9:37222d6ece56 356 * EBADF : Channel status is DMA_CH_INIT.
dkato 9:37222d6ece56 357 * EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
dkato 9:37222d6ece56 358 * EACCES : Driver status isn't DMA_DRV_INIT.
dkato 9:37222d6ece56 359 * EBUSY : It has been start DMA transfer in channel.
dkato 9:37222d6ece56 360 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 9:37222d6ece56 361 * EFAULT: Channel status is besides the status definded in dma_stat_ch_t.
dkato 9:37222d6ece56 362 * @retval ESUCCESS -
dkato 0:702bf7b2b7d8 363 * Operation successful.
dkato 0:702bf7b2b7d8 364 * EERROR -
dkato 0:702bf7b2b7d8 365 * Error occured.
dkato 0:702bf7b2b7d8 366 ******************************************************************************/
dkato 0:702bf7b2b7d8 367
dkato 0:702bf7b2b7d8 368 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 369 int_t R_DMA_Free(const int_t channel, int32_t *const p_errno)
dkato 0:702bf7b2b7d8 370 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 371 {
dkato 0:702bf7b2b7d8 372 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 373 dma_info_drv_t *dma_info_drv;
dkato 0:702bf7b2b7d8 374 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 375 int_t error_code;
dkato 5:1390bfcb667c 376 int_t was_masked;
dkato 0:702bf7b2b7d8 377
dkato 0:702bf7b2b7d8 378 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 379
dkato 5:1390bfcb667c 380 /* disable all irq */
dkato 5:1390bfcb667c 381 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 382 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 383 #else
dkato 5:1390bfcb667c 384 was_masked = __disable_irq();
dkato 5:1390bfcb667c 385 #endif
dkato 5:1390bfcb667c 386
dkato 0:702bf7b2b7d8 387 /* check channel of argument */
dkato 0:702bf7b2b7d8 388 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 389 {
dkato 0:702bf7b2b7d8 390 /* check driver status */
dkato 0:702bf7b2b7d8 391 dma_info_drv = DMA_GetDrvInstance();
dkato 0:702bf7b2b7d8 392
dkato 0:702bf7b2b7d8 393 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 394 {
dkato 0:702bf7b2b7d8 395 /* check driver status */
dkato 0:702bf7b2b7d8 396 if (DMA_DRV_INIT == dma_info_drv->drv_stat)
dkato 0:702bf7b2b7d8 397 {
dkato 0:702bf7b2b7d8 398 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 399
dkato 0:702bf7b2b7d8 400 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 401 {
dkato 0:702bf7b2b7d8 402 if (DMA_CH_OPEN == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 403 {
dkato 0:702bf7b2b7d8 404 DMA_CloseChannel(channel);
dkato 0:702bf7b2b7d8 405 }
dkato 0:702bf7b2b7d8 406 else
dkato 0:702bf7b2b7d8 407 {
dkato 0:702bf7b2b7d8 408 /* set error return value */
dkato 0:702bf7b2b7d8 409 retval = EERROR;
dkato 0:702bf7b2b7d8 410 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 411 {
dkato 0:702bf7b2b7d8 412 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 413 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 414 break;
dkato 0:702bf7b2b7d8 415
dkato 0:702bf7b2b7d8 416 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 417 error_code = EBADF;
dkato 0:702bf7b2b7d8 418 break;
dkato 0:702bf7b2b7d8 419
dkato 0:702bf7b2b7d8 420 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 421 error_code = EBUSY;
dkato 0:702bf7b2b7d8 422 break;
dkato 0:702bf7b2b7d8 423
dkato 0:702bf7b2b7d8 424 default:
dkato 0:702bf7b2b7d8 425 error_code = EFAULT;
dkato 0:702bf7b2b7d8 426 break;
dkato 0:702bf7b2b7d8 427 }
dkato 0:702bf7b2b7d8 428 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 429 }
dkato 0:702bf7b2b7d8 430 }
dkato 0:702bf7b2b7d8 431 }
dkato 0:702bf7b2b7d8 432 else
dkato 0:702bf7b2b7d8 433 {
dkato 0:702bf7b2b7d8 434 /* set error return value */
dkato 0:702bf7b2b7d8 435 retval = EERROR;
dkato 0:702bf7b2b7d8 436 DMA_SetErrCode(EACCES, p_errno);
dkato 0:702bf7b2b7d8 437
dkato 0:702bf7b2b7d8 438 }
dkato 0:702bf7b2b7d8 439 }
dkato 0:702bf7b2b7d8 440 }
dkato 0:702bf7b2b7d8 441 else
dkato 0:702bf7b2b7d8 442 {
dkato 0:702bf7b2b7d8 443 /* set error return value */
dkato 0:702bf7b2b7d8 444 retval = EERROR;
dkato 0:702bf7b2b7d8 445 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 446 }
dkato 0:702bf7b2b7d8 447
dkato 5:1390bfcb667c 448 if (0 == was_masked)
dkato 5:1390bfcb667c 449 {
dkato 5:1390bfcb667c 450 __enable_irq();
dkato 5:1390bfcb667c 451 }
dkato 5:1390bfcb667c 452
dkato 0:702bf7b2b7d8 453 return retval;
dkato 0:702bf7b2b7d8 454 }
dkato 0:702bf7b2b7d8 455
dkato 0:702bf7b2b7d8 456 /******************************************************************************
dkato 0:702bf7b2b7d8 457 End of function R_DMA_Free
dkato 0:702bf7b2b7d8 458 ******************************************************************************/
dkato 0:702bf7b2b7d8 459
dkato 9:37222d6ece56 460 /**************************************************************************//**
dkato 0:702bf7b2b7d8 461 * Function Name: R_DMA_Setup
dkato 9:37222d6ece56 462 * @brie Setup DMA transfer parameter.
dkato 9:37222d6ece56 463 * Check parameter in this function mainly.
dkato 9:37222d6ece56 464 *
dkato 9:37222d6ece56 465 * Description:<br>
dkato 9:37222d6ece56 466 *
dkato 9:37222d6ece56 467 * @param[in] channel :Setup channel number.
dkato 9:37222d6ece56 468 * @param[in] p_ch_setup:Set up parameters.
dkato 9:37222d6ece56 469 * @param[in,out] p_errno :Pointer of error code
dkato 9:37222d6ece56 470 * When pointer is NULL, it isn't set error code.
dkato 9:37222d6ece56 471 * error code -
dkato 9:37222d6ece56 472 * EBADF : Channel status is DMA_CH_INIT.
dkato 9:37222d6ece56 473 * EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
dkato 9:37222d6ece56 474 * EBUSY : It has been start DMA transfer in channel.
dkato 9:37222d6ece56 475 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 9:37222d6ece56 476 * EPERM : The value in p_ch_setup isn't in the right range.
dkato 9:37222d6ece56 477 * EFAULT: Channel status is besides the status definded in dma_stat_ch_t. p_ch_setup is NULL.
dkato 9:37222d6ece56 478 * @retval ESUCCESS -
dkato 0:702bf7b2b7d8 479 * Operation successful.
dkato 0:702bf7b2b7d8 480 * EERROR -
dkato 0:702bf7b2b7d8 481 * Error occured.
dkato 0:702bf7b2b7d8 482 ******************************************************************************/
dkato 0:702bf7b2b7d8 483
dkato 0:702bf7b2b7d8 484 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 485 int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
dkato 0:702bf7b2b7d8 486 int32_t * const p_errno)
dkato 0:702bf7b2b7d8 487 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 488 {
dkato 0:702bf7b2b7d8 489 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 490 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 491 int_t error_code;
dkato 0:702bf7b2b7d8 492 uint32_t cfg_table_count;
dkato 0:702bf7b2b7d8 493 dma_ch_cfg_t ch_cfg_set_table;
dkato 0:702bf7b2b7d8 494 uint32_t set_reqd;
dkato 0:702bf7b2b7d8 495 bool_t check_table_flag;
dkato 5:1390bfcb667c 496 int_t was_masked;
dkato 0:702bf7b2b7d8 497
dkato 0:702bf7b2b7d8 498 /* Resouce Configure Set Table */
dkato 0:702bf7b2b7d8 499 static const dma_ch_cfg_t ch_cfg_table[DMA_CH_CONFIG_TABLE_NUM] =
dkato 0:702bf7b2b7d8 500 {
dkato 0:702bf7b2b7d8 501 {DMA_RS_OSTIM0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 502 {DMA_RS_OSTIM1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 503 {DMA_RS_TGI0A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 504 {DMA_RS_TGI1A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 505 {DMA_RS_TGI2A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 506 {DMA_RS_TGI3A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 507 {DMA_RS_TGI4A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 508 {DMA_RS_TXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 509 {DMA_RS_RXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 510 {DMA_RS_TXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 511 {DMA_RS_RXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 512 {DMA_RS_TXI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 513 {DMA_RS_RXI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 514 {DMA_RS_TXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 515 {DMA_RS_RXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 516 {DMA_RS_TXI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 517 {DMA_RS_RXI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 518 {DMA_RS_TXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 519 {DMA_RS_RXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 520 {DMA_RS_TXI6, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 521 {DMA_RS_RXI6, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 522 {DMA_RS_TXI7, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 523 {DMA_RS_RXI7, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 524 {DMA_RS_USB0_DMA0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 525 {DMA_RS_USB0_DMA1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 526 {DMA_RS_USB1_DMA0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 527 {DMA_RS_USB1_DMA1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 528 {DMA_RS_ADEND, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 529 {DMA_RS_IEBBTD, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 530 {DMA_RS_IEBBTV, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 531 {DMA_RS_IREADY, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 532 {DMA_RS_FLDT, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 533 {DMA_RS_SDHI_0T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 534 {DMA_RS_SDHI_0R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 535 {DMA_RS_SDHI_1T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 536 {DMA_RS_SDHI_1R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 537 {DMA_RS_MMCT, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 538 {DMA_RS_MMCR, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 539 {DMA_RS_SSITXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 5:1390bfcb667c 540 {DMA_RS_SSIRXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 541 {DMA_RS_SSITXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 5:1390bfcb667c 542 {DMA_RS_SSIRXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 543 {DMA_RS_SSIRTI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 5:1390bfcb667c 544 {DMA_RS_SSITXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 5:1390bfcb667c 545 {DMA_RS_SSIRXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 546 {DMA_RS_SSIRTI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 5:1390bfcb667c 547 {DMA_RS_SSITXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 5:1390bfcb667c 548 {DMA_RS_SSIRXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 549 {DMA_RS_SCUTXI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 550 {DMA_RS_SCURXI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 551 {DMA_RS_SCUTXI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 552 {DMA_RS_SCURXI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 553 {DMA_RS_SCUTXI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 554 {DMA_RS_SCURXI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 555 {DMA_RS_SCUTXI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 556 {DMA_RS_SCURXI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 557 {DMA_RS_SPTI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 558 {DMA_RS_SPRI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 559 {DMA_RS_SPTI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 560 {DMA_RS_SPRI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 561 {DMA_RS_SPTI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 562 {DMA_RS_SPRI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 563 {DMA_RS_SPTI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 564 {DMA_RS_SPRI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 565 {DMA_RS_SPTI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 566 {DMA_RS_SPRI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 567 {DMA_RS_SPDIFTXI, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 568 {DMA_RS_SPDIFRXI, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 569 {DMA_RS_CMI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 570 {DMA_RS_CMI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 571 {DMA_RS_MLBCI, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 572 {DMA_RS_SGDEI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 573 {DMA_RS_SGDEI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 574 {DMA_RS_SGDEI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 575 {DMA_RS_SGDEI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 576 {DMA_RS_SCUTXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 577 {DMA_RS_SCURXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 578 {DMA_RS_SCUTXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 579 {DMA_RS_SCURXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 580 {DMA_RS_TI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 581 {DMA_RS_RI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 582 {DMA_RS_TI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 583 {DMA_RS_RI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 584 {DMA_RS_TI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 585 {DMA_RS_RI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 586 {DMA_RS_TI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 587 {DMA_RS_RI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 588 {DMA_RS_LIN0_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 589 {DMA_RS_LIN0_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 590 {DMA_RS_LIN1_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 591 {DMA_RS_LIN1_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 592 {DMA_RS_IFEI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 593 {DMA_RS_OFFI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 594 {DMA_RS_IFEI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 595 {DMA_RS_OFFI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC }
dkato 0:702bf7b2b7d8 596 };
dkato 0:702bf7b2b7d8 597
dkato 0:702bf7b2b7d8 598 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 599 /* dummy init set_reqd */
dkato 0:702bf7b2b7d8 600 set_reqd = CHCFG_REQD_UNDEFINED;
dkato 0:702bf7b2b7d8 601 ch_cfg_set_table = ch_cfg_table[0];
dkato 0:702bf7b2b7d8 602
dkato 0:702bf7b2b7d8 603 /* check channel of argument */
dkato 0:702bf7b2b7d8 604 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 605 {
dkato 0:702bf7b2b7d8 606 if (NULL != p_ch_setup)
dkato 0:702bf7b2b7d8 607 {
dkato 0:702bf7b2b7d8 608 /* check setup parameter */
dkato 0:702bf7b2b7d8 609 /* check AIOCB pointer */
dkato 0:702bf7b2b7d8 610 if (NULL == p_ch_setup->p_aio)
dkato 0:702bf7b2b7d8 611 {
dkato 0:702bf7b2b7d8 612 /* set error return value */
dkato 0:702bf7b2b7d8 613 retval = EERROR;
dkato 0:702bf7b2b7d8 614 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 615 }
dkato 0:702bf7b2b7d8 616
dkato 0:702bf7b2b7d8 617 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 618 {
dkato 0:702bf7b2b7d8 619 /* check DMA transfer unit size for destination */
dkato 0:702bf7b2b7d8 620 if (((int_t)p_ch_setup->dst_width <= DMA_UNIT_MIN) ||
dkato 0:702bf7b2b7d8 621 ((int_t)p_ch_setup->dst_width >= DMA_UNIT_MAX))
dkato 0:702bf7b2b7d8 622 {
dkato 0:702bf7b2b7d8 623 /* set error return value */
dkato 0:702bf7b2b7d8 624 retval = EERROR;
dkato 0:702bf7b2b7d8 625 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 626 }
dkato 0:702bf7b2b7d8 627 }
dkato 0:702bf7b2b7d8 628
dkato 0:702bf7b2b7d8 629 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 630 {
dkato 0:702bf7b2b7d8 631 /* check DMA transfer unit size for source */
dkato 0:702bf7b2b7d8 632 if (((int_t)p_ch_setup->src_width <= DMA_UNIT_MIN) ||
dkato 0:702bf7b2b7d8 633 ((int_t)p_ch_setup->src_width >= DMA_UNIT_MAX))
dkato 0:702bf7b2b7d8 634 {
dkato 0:702bf7b2b7d8 635 /* set error return value */
dkato 0:702bf7b2b7d8 636 retval = EERROR;
dkato 0:702bf7b2b7d8 637 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 638 }
dkato 0:702bf7b2b7d8 639 }
dkato 0:702bf7b2b7d8 640
dkato 0:702bf7b2b7d8 641 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 642 {
dkato 0:702bf7b2b7d8 643 /* check DMA address count direction for destination */
dkato 0:702bf7b2b7d8 644 if (((int_t)p_ch_setup->dst_cnt <= DMA_ADDR_MIN) ||
dkato 0:702bf7b2b7d8 645 ((int_t)p_ch_setup->dst_cnt >= DMA_ADDR_MAX))
dkato 0:702bf7b2b7d8 646 {
dkato 0:702bf7b2b7d8 647 /* set error return value */
dkato 0:702bf7b2b7d8 648 retval = EERROR;
dkato 0:702bf7b2b7d8 649 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 650 }
dkato 0:702bf7b2b7d8 651 }
dkato 0:702bf7b2b7d8 652
dkato 0:702bf7b2b7d8 653 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 654 {
dkato 0:702bf7b2b7d8 655 /* check DMA address count direction for source */
dkato 0:702bf7b2b7d8 656 if (((int_t)(p_ch_setup->src_cnt) <= DMA_ADDR_MIN) ||
dkato 0:702bf7b2b7d8 657 ((int_t)p_ch_setup->src_cnt >= DMA_ADDR_MAX))
dkato 0:702bf7b2b7d8 658 {
dkato 0:702bf7b2b7d8 659 /* set error return value */
dkato 0:702bf7b2b7d8 660 retval = EERROR;
dkato 0:702bf7b2b7d8 661 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 662 }
dkato 0:702bf7b2b7d8 663 }
dkato 0:702bf7b2b7d8 664
dkato 0:702bf7b2b7d8 665 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 666 {
dkato 0:702bf7b2b7d8 667 /* check DMA transfer direction */
dkato 0:702bf7b2b7d8 668 if (((int_t)p_ch_setup->direction <= DMA_REQ_MIN) ||
dkato 0:702bf7b2b7d8 669 ((int_t)p_ch_setup->direction >= DMA_REQ_MAX))
dkato 0:702bf7b2b7d8 670 {
dkato 0:702bf7b2b7d8 671 /* set error return value */
dkato 0:702bf7b2b7d8 672 retval = EERROR;
dkato 0:702bf7b2b7d8 673 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 674 }
dkato 0:702bf7b2b7d8 675 }
dkato 0:702bf7b2b7d8 676
dkato 0:702bf7b2b7d8 677 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 678 {
dkato 0:702bf7b2b7d8 679 /* check DMA transfer resouce */
dkato 0:702bf7b2b7d8 680 check_table_flag = false;
dkato 0:702bf7b2b7d8 681 cfg_table_count = 0;
dkato 0:702bf7b2b7d8 682 while (false == check_table_flag)
dkato 0:702bf7b2b7d8 683 {
dkato 0:702bf7b2b7d8 684 if (p_ch_setup->resource == ch_cfg_table[cfg_table_count].dmars)
dkato 0:702bf7b2b7d8 685 {
dkato 0:702bf7b2b7d8 686 /* check reqd is undefined */
dkato 0:702bf7b2b7d8 687 if (CHCFG_REQD_UNDEFINED == ch_cfg_table[cfg_table_count].reqd)
dkato 0:702bf7b2b7d8 688 {
dkato 0:702bf7b2b7d8 689 /* set reqd value on fixed value */
dkato 0:702bf7b2b7d8 690 if (DMA_REQ_SRC == p_ch_setup->direction)
dkato 0:702bf7b2b7d8 691 {
dkato 0:702bf7b2b7d8 692 set_reqd = CHCFG_SET_REQD_SRC;
dkato 0:702bf7b2b7d8 693 }
dkato 0:702bf7b2b7d8 694 else
dkato 0:702bf7b2b7d8 695 {
dkato 0:702bf7b2b7d8 696 set_reqd = CHCFG_SET_REQD_DST;
dkato 0:702bf7b2b7d8 697 }
dkato 0:702bf7b2b7d8 698 }
dkato 0:702bf7b2b7d8 699 else
dkato 0:702bf7b2b7d8 700 {
dkato 0:702bf7b2b7d8 701 /* set reqd value in channel config table */
dkato 0:702bf7b2b7d8 702 set_reqd = ch_cfg_table[cfg_table_count].reqd;
dkato 0:702bf7b2b7d8 703 }
dkato 0:702bf7b2b7d8 704 /* set channel config table address for DMA_SetParam() */
dkato 0:702bf7b2b7d8 705 ch_cfg_set_table = ch_cfg_table[cfg_table_count];
dkato 0:702bf7b2b7d8 706 check_table_flag = true;
dkato 0:702bf7b2b7d8 707 }
dkato 0:702bf7b2b7d8 708 if (false == check_table_flag)
dkato 0:702bf7b2b7d8 709 {
dkato 0:702bf7b2b7d8 710 /* resource value did not exist in channel config table */
dkato 0:702bf7b2b7d8 711 if ((uint32_t)((sizeof(ch_cfg_table)/sizeof(dma_ch_cfg_t)) - 1U) == cfg_table_count)
dkato 0:702bf7b2b7d8 712 {
dkato 0:702bf7b2b7d8 713 /* set error return value */
dkato 0:702bf7b2b7d8 714 retval = EERROR;
dkato 0:702bf7b2b7d8 715 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 716 check_table_flag = true;
dkato 0:702bf7b2b7d8 717 }
dkato 0:702bf7b2b7d8 718 cfg_table_count++;
dkato 0:702bf7b2b7d8 719 }
dkato 0:702bf7b2b7d8 720 }
dkato 0:702bf7b2b7d8 721 }
dkato 0:702bf7b2b7d8 722
dkato 5:1390bfcb667c 723 /* disable all irq */
dkato 5:1390bfcb667c 724 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 725 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 726 #else
dkato 5:1390bfcb667c 727 was_masked = __disable_irq();
dkato 5:1390bfcb667c 728 #endif
dkato 5:1390bfcb667c 729
dkato 0:702bf7b2b7d8 730 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 731 {
dkato 0:702bf7b2b7d8 732 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 733
dkato 0:702bf7b2b7d8 734 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 735 {
dkato 0:702bf7b2b7d8 736 if (DMA_CH_OPEN == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 737 {
dkato 0:702bf7b2b7d8 738 /* set up parameter */
dkato 0:702bf7b2b7d8 739 DMA_SetParam(channel, p_ch_setup, &ch_cfg_set_table, set_reqd);
dkato 0:702bf7b2b7d8 740 }
dkato 0:702bf7b2b7d8 741 else
dkato 0:702bf7b2b7d8 742 {
dkato 0:702bf7b2b7d8 743 /* set error return value */
dkato 0:702bf7b2b7d8 744 retval = EERROR;
dkato 0:702bf7b2b7d8 745 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 746 {
dkato 0:702bf7b2b7d8 747 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 748 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 749 break;
dkato 0:702bf7b2b7d8 750
dkato 0:702bf7b2b7d8 751 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 752 error_code = EBADF;
dkato 0:702bf7b2b7d8 753 break;
dkato 0:702bf7b2b7d8 754
dkato 0:702bf7b2b7d8 755 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 756 error_code = EBUSY;
dkato 0:702bf7b2b7d8 757 break;
dkato 0:702bf7b2b7d8 758
dkato 0:702bf7b2b7d8 759 default:
dkato 0:702bf7b2b7d8 760 error_code = EFAULT;
dkato 0:702bf7b2b7d8 761 break;
dkato 0:702bf7b2b7d8 762 }
dkato 0:702bf7b2b7d8 763 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 764 }
dkato 0:702bf7b2b7d8 765 }
dkato 0:702bf7b2b7d8 766 }
dkato 5:1390bfcb667c 767
dkato 5:1390bfcb667c 768 if (0 == was_masked)
dkato 5:1390bfcb667c 769 {
dkato 5:1390bfcb667c 770 __enable_irq();
dkato 5:1390bfcb667c 771 }
dkato 0:702bf7b2b7d8 772 }
dkato 0:702bf7b2b7d8 773 else
dkato 0:702bf7b2b7d8 774 {
dkato 0:702bf7b2b7d8 775 /* set error return value */
dkato 0:702bf7b2b7d8 776 retval = EERROR;
dkato 0:702bf7b2b7d8 777 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 778 }
dkato 0:702bf7b2b7d8 779 }
dkato 0:702bf7b2b7d8 780 else
dkato 0:702bf7b2b7d8 781 {
dkato 0:702bf7b2b7d8 782 /* set error return value */
dkato 0:702bf7b2b7d8 783 retval = EERROR;
dkato 0:702bf7b2b7d8 784 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 785 }
dkato 0:702bf7b2b7d8 786
dkato 0:702bf7b2b7d8 787 return retval;
dkato 0:702bf7b2b7d8 788 }
dkato 0:702bf7b2b7d8 789
dkato 0:702bf7b2b7d8 790 /******************************************************************************
dkato 0:702bf7b2b7d8 791 End of function R_DMA_SetParam
dkato 0:702bf7b2b7d8 792 ******************************************************************************/
dkato 0:702bf7b2b7d8 793
dkato 9:37222d6ece56 794 /**************************************************************************//**
dkato 0:702bf7b2b7d8 795 * Function Name: R_DMA_Start
dkato 9:37222d6ece56 796 * @brie Start DMA transfer.
dkato 9:37222d6ece56 797 * Check parameter in this function mainly.
dkato 9:37222d6ece56 798 *
dkato 9:37222d6ece56 799 * Description:<br>
dkato 9:37222d6ece56 800 *
dkato 9:37222d6ece56 801 * @param[in] channel :DMA start channel number.
dkato 9:37222d6ece56 802 * @param[in] p_dma_data:DMA address parameters.
dkato 9:37222d6ece56 803 * @param[in,out] p_errno :Pointer of error code
dkato 9:37222d6ece56 804 * When pointer is NULL, it isn't set error code.
dkato 9:37222d6ece56 805 * error code -
dkato 9:37222d6ece56 806 * EBADF : Channel status is DMA_CH_INIT.
dkato 9:37222d6ece56 807 * EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
dkato 9:37222d6ece56 808 * EBUSY : It has been start DMA transfer in channel.
dkato 9:37222d6ece56 809 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 9:37222d6ece56 810 * EPERM : The value in p_ch_setup isn't in the right range.
dkato 9:37222d6ece56 811 * EFAULT: Channel status is besides the status definded in dma_stat_ch_t. p_dma_data is NULL.
dkato 9:37222d6ece56 812 * @retval ESUCCESS -
dkato 0:702bf7b2b7d8 813 * Operation successful.
dkato 0:702bf7b2b7d8 814 * EERROR -
dkato 0:702bf7b2b7d8 815 * Error occured.
dkato 0:702bf7b2b7d8 816 ******************************************************************************/
dkato 0:702bf7b2b7d8 817
dkato 0:702bf7b2b7d8 818 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 819 int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 820 int32_t * const p_errno)
dkato 0:702bf7b2b7d8 821 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 822 {
dkato 0:702bf7b2b7d8 823 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 824 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 825 int_t error_code;
dkato 5:1390bfcb667c 826 int_t was_masked;
dkato 0:702bf7b2b7d8 827
dkato 0:702bf7b2b7d8 828 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 829
dkato 5:1390bfcb667c 830 /* disable all irq */
dkato 5:1390bfcb667c 831 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 832 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 833 #else
dkato 5:1390bfcb667c 834 was_masked = __disable_irq();
dkato 5:1390bfcb667c 835 #endif
dkato 5:1390bfcb667c 836
dkato 0:702bf7b2b7d8 837 /* check channel of argument */
dkato 0:702bf7b2b7d8 838 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 839 {
dkato 0:702bf7b2b7d8 840 if (NULL != p_dma_data)
dkato 0:702bf7b2b7d8 841 {
dkato 0:702bf7b2b7d8 842 /* check address parameter */
dkato 0:702bf7b2b7d8 843 /* check DMA transfer count destination address is 0 */
dkato 0:702bf7b2b7d8 844 if (0U == p_dma_data->count)
dkato 0:702bf7b2b7d8 845 {
dkato 0:702bf7b2b7d8 846 /* set error return value */
dkato 0:702bf7b2b7d8 847 retval = EERROR;
dkato 0:702bf7b2b7d8 848 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 849 }
dkato 0:702bf7b2b7d8 850
dkato 0:702bf7b2b7d8 851 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 852 {
dkato 0:702bf7b2b7d8 853 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 854
dkato 0:702bf7b2b7d8 855 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 856 {
dkato 0:702bf7b2b7d8 857 if (DMA_CH_OPEN == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 858 {
dkato 0:702bf7b2b7d8 859 /* set bus paramter for DMA */
dkato 0:702bf7b2b7d8 860 DMA_BusParam(channel, p_dma_data);
dkato 0:702bf7b2b7d8 861 /* set up address parameter */
dkato 0:702bf7b2b7d8 862 /* Next register set is 0 */
dkato 0:702bf7b2b7d8 863 DMA_SetData(channel, p_dma_data, 0);
dkato 0:702bf7b2b7d8 864 /* DMA transfer start */
dkato 0:702bf7b2b7d8 865 DMA_Start(channel, false);
dkato 0:702bf7b2b7d8 866 }
dkato 0:702bf7b2b7d8 867 else
dkato 0:702bf7b2b7d8 868 {
dkato 0:702bf7b2b7d8 869 /* set error return value */
dkato 0:702bf7b2b7d8 870 retval = EERROR;
dkato 0:702bf7b2b7d8 871 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 872 {
dkato 0:702bf7b2b7d8 873 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 874 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 875 break;
dkato 0:702bf7b2b7d8 876
dkato 0:702bf7b2b7d8 877 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 878 error_code = EBADF;
dkato 0:702bf7b2b7d8 879 break;
dkato 0:702bf7b2b7d8 880
dkato 0:702bf7b2b7d8 881 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 882 error_code = EBUSY;
dkato 0:702bf7b2b7d8 883 break;
dkato 0:702bf7b2b7d8 884
dkato 0:702bf7b2b7d8 885 default:
dkato 0:702bf7b2b7d8 886 error_code = EFAULT;
dkato 0:702bf7b2b7d8 887 break;
dkato 0:702bf7b2b7d8 888 }
dkato 0:702bf7b2b7d8 889 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 890 }
dkato 0:702bf7b2b7d8 891 }
dkato 0:702bf7b2b7d8 892 }
dkato 0:702bf7b2b7d8 893 }
dkato 0:702bf7b2b7d8 894 else
dkato 0:702bf7b2b7d8 895 {
dkato 0:702bf7b2b7d8 896 /* set error return value */
dkato 0:702bf7b2b7d8 897 retval = EERROR;
dkato 0:702bf7b2b7d8 898 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 899 }
dkato 0:702bf7b2b7d8 900 }
dkato 0:702bf7b2b7d8 901 else
dkato 0:702bf7b2b7d8 902 {
dkato 0:702bf7b2b7d8 903 /* set error return value */
dkato 0:702bf7b2b7d8 904 retval = EERROR;
dkato 0:702bf7b2b7d8 905 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 906 }
dkato 0:702bf7b2b7d8 907
dkato 5:1390bfcb667c 908 if (0 == was_masked)
dkato 5:1390bfcb667c 909 {
dkato 5:1390bfcb667c 910 __enable_irq();
dkato 5:1390bfcb667c 911 }
dkato 5:1390bfcb667c 912
dkato 0:702bf7b2b7d8 913 return retval;
dkato 0:702bf7b2b7d8 914 }
dkato 0:702bf7b2b7d8 915
dkato 0:702bf7b2b7d8 916 /******************************************************************************
dkato 0:702bf7b2b7d8 917 End of function R_DMA_Start
dkato 0:702bf7b2b7d8 918 ******************************************************************************/
dkato 0:702bf7b2b7d8 919
dkato 9:37222d6ece56 920 /**************************************************************************//**
dkato 0:702bf7b2b7d8 921 * Function Name: R_DMA_NextData
dkato 9:37222d6ece56 922 * @brie Set continous DMA mode.
dkato 9:37222d6ece56 923 * Check parameter in this function mainly.
dkato 9:37222d6ece56 924 *
dkato 9:37222d6ece56 925 * Description:<br>
dkato 9:37222d6ece56 926 *
dkato 9:37222d6ece56 927 * @param[in] channel :Continuous DMA channel number.
dkato 9:37222d6ece56 928 * @param[in,out] p_dma_data:DMA address parameters.
dkato 9:37222d6ece56 929 * @param[in,out] p_errno :Pointer of error code
dkato 9:37222d6ece56 930 * When pointer is NULL, it isn't set error code.
dkato 9:37222d6ece56 931 * error code -
dkato 9:37222d6ece56 932 * EBADF : Channel status is DMA_CH_INIT.
dkato 9:37222d6ece56 933 * EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
dkato 9:37222d6ece56 934 * EBUSY : It has been set continous DMA transfer.
dkato 9:37222d6ece56 935 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 9:37222d6ece56 936 * EPERM : The value in p_ch_setup isn't in the right range.
dkato 9:37222d6ece56 937 * EFAULT: Channel status is besides the status definded in dma_stat_ch_t. p_dma_data is NULL.
dkato 9:37222d6ece56 938 * @retval ESUCCESS -
dkato 0:702bf7b2b7d8 939 * Operation successful.
dkato 0:702bf7b2b7d8 940 * EERROR -
dkato 0:702bf7b2b7d8 941 * Error occured.
dkato 0:702bf7b2b7d8 942 ******************************************************************************/
dkato 0:702bf7b2b7d8 943
dkato 0:702bf7b2b7d8 944 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 945 int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 946 int32_t * const p_errno)
dkato 0:702bf7b2b7d8 947 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 948 {
dkato 0:702bf7b2b7d8 949 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 950 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 951 int_t error_code;
dkato 5:1390bfcb667c 952 int_t was_masked;
dkato 0:702bf7b2b7d8 953
dkato 0:702bf7b2b7d8 954 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 955
dkato 5:1390bfcb667c 956 /* disable all irq */
dkato 5:1390bfcb667c 957 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 958 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 959 #else
dkato 5:1390bfcb667c 960 was_masked = __disable_irq();
dkato 5:1390bfcb667c 961 #endif
dkato 5:1390bfcb667c 962
dkato 0:702bf7b2b7d8 963 /* check channel of argument */
dkato 0:702bf7b2b7d8 964 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 965 {
dkato 0:702bf7b2b7d8 966 if (NULL != p_dma_data)
dkato 0:702bf7b2b7d8 967 {
dkato 0:702bf7b2b7d8 968 /* check address parameter */
dkato 0:702bf7b2b7d8 969 /* check DMA transfer count destination address is 0 */
dkato 0:702bf7b2b7d8 970 if (0U == p_dma_data->count)
dkato 0:702bf7b2b7d8 971 {
dkato 0:702bf7b2b7d8 972 /* set error return value */
dkato 0:702bf7b2b7d8 973 retval = EERROR;
dkato 0:702bf7b2b7d8 974 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 975 }
dkato 0:702bf7b2b7d8 976
dkato 0:702bf7b2b7d8 977 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 978 {
dkato 0:702bf7b2b7d8 979 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 980
dkato 0:702bf7b2b7d8 981 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 982 {
dkato 0:702bf7b2b7d8 983 if ((DMA_CH_OPEN == dma_info_ch->ch_stat) ||
dkato 0:702bf7b2b7d8 984 (DMA_CH_TRANSFER == dma_info_ch->ch_stat))
dkato 0:702bf7b2b7d8 985 {
dkato 0:702bf7b2b7d8 986 if (false == dma_info_ch->next_dma_flag)
dkato 0:702bf7b2b7d8 987 {
dkato 0:702bf7b2b7d8 988 /* set up address parameter for continous DMA*/
dkato 0:702bf7b2b7d8 989 DMA_SetNextData(channel, p_dma_data);
dkato 0:702bf7b2b7d8 990 }
dkato 0:702bf7b2b7d8 991 else
dkato 0:702bf7b2b7d8 992 {
dkato 0:702bf7b2b7d8 993 /* set error return value */
dkato 0:702bf7b2b7d8 994 retval = EERROR;
dkato 0:702bf7b2b7d8 995 DMA_SetErrCode(EBUSY, p_errno);
dkato 0:702bf7b2b7d8 996 }
dkato 0:702bf7b2b7d8 997 }
dkato 0:702bf7b2b7d8 998 else
dkato 0:702bf7b2b7d8 999 {
dkato 0:702bf7b2b7d8 1000 /* set error return value */
dkato 0:702bf7b2b7d8 1001 retval = EERROR;
dkato 0:702bf7b2b7d8 1002 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1003 {
dkato 0:702bf7b2b7d8 1004 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 1005 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 1006 break;
dkato 0:702bf7b2b7d8 1007
dkato 0:702bf7b2b7d8 1008 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 1009 error_code = EBADF;
dkato 0:702bf7b2b7d8 1010 break;
dkato 0:702bf7b2b7d8 1011
dkato 0:702bf7b2b7d8 1012 default:
dkato 0:702bf7b2b7d8 1013 error_code = EFAULT;
dkato 0:702bf7b2b7d8 1014 break;
dkato 0:702bf7b2b7d8 1015 }
dkato 0:702bf7b2b7d8 1016 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 1017 }
dkato 0:702bf7b2b7d8 1018 }
dkato 0:702bf7b2b7d8 1019 }
dkato 0:702bf7b2b7d8 1020 }
dkato 0:702bf7b2b7d8 1021 else
dkato 0:702bf7b2b7d8 1022 {
dkato 0:702bf7b2b7d8 1023 /* set error return value */
dkato 0:702bf7b2b7d8 1024 retval = EERROR;
dkato 0:702bf7b2b7d8 1025 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 1026 }
dkato 0:702bf7b2b7d8 1027 }
dkato 0:702bf7b2b7d8 1028 else
dkato 0:702bf7b2b7d8 1029 {
dkato 0:702bf7b2b7d8 1030 /* set error return value */
dkato 0:702bf7b2b7d8 1031 retval = EERROR;
dkato 0:702bf7b2b7d8 1032 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 1033 }
dkato 0:702bf7b2b7d8 1034
dkato 5:1390bfcb667c 1035 if (0 == was_masked)
dkato 5:1390bfcb667c 1036 {
dkato 5:1390bfcb667c 1037 __enable_irq();
dkato 5:1390bfcb667c 1038 }
dkato 5:1390bfcb667c 1039
dkato 0:702bf7b2b7d8 1040 return retval;
dkato 0:702bf7b2b7d8 1041 }
dkato 0:702bf7b2b7d8 1042
dkato 0:702bf7b2b7d8 1043 /******************************************************************************
dkato 0:702bf7b2b7d8 1044 End of function R_DMA_NextData
dkato 0:702bf7b2b7d8 1045 ******************************************************************************/
dkato 0:702bf7b2b7d8 1046
dkato 9:37222d6ece56 1047 /**************************************************************************//**
dkato 0:702bf7b2b7d8 1048 * Function Name: R_DMA_Cancel
dkato 9:37222d6ece56 1049 * @brie Cancel DMA transfer.
dkato 9:37222d6ece56 1050 * Check parameter in this function mainly.
dkato 9:37222d6ece56 1051 *
dkato 9:37222d6ece56 1052 * Description:<br>
dkato 9:37222d6ece56 1053 *
dkato 9:37222d6ece56 1054 * @param[in] channel :Cancel DMA channel number.
dkato 9:37222d6ece56 1055 * @param[in] p_remain :Remain data size of DMA transfer when it stopping.
dkato 9:37222d6ece56 1056 * @param[in,out] p_errno :Pointer of error code
dkato 9:37222d6ece56 1057 * When pointer is NULL, it isn't set error code.
dkato 9:37222d6ece56 1058 * error code -
dkato 9:37222d6ece56 1059 * EBADF : Channel status is DMA_CH_INIT or DMA_CH_OPEN. (DMA stopped)
dkato 9:37222d6ece56 1060 * EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
dkato 9:37222d6ece56 1061 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 9:37222d6ece56 1062 * EFAULT: Channel status is besides the status definded in dma_stat_ch_t. p_remain is NULL.
dkato 9:37222d6ece56 1063 * @retval ESUCCESS -
dkato 0:702bf7b2b7d8 1064 * Operation successful.
dkato 0:702bf7b2b7d8 1065 * EERROR -
dkato 0:702bf7b2b7d8 1066 * Error occured.
dkato 0:702bf7b2b7d8 1067 ******************************************************************************/
dkato 0:702bf7b2b7d8 1068
dkato 0:702bf7b2b7d8 1069 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 1070 int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 1071 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 1072 {
dkato 0:702bf7b2b7d8 1073 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 1074 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 1075 int_t error_code;
dkato 5:1390bfcb667c 1076 int_t was_masked;
dkato 0:702bf7b2b7d8 1077
dkato 0:702bf7b2b7d8 1078 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 1079
dkato 5:1390bfcb667c 1080 /* disable all irq */
dkato 5:1390bfcb667c 1081 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 1082 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 1083 #else
dkato 5:1390bfcb667c 1084 was_masked = __disable_irq();
dkato 5:1390bfcb667c 1085 #endif
dkato 5:1390bfcb667c 1086
dkato 0:702bf7b2b7d8 1087 /* check channel of argument */
dkato 0:702bf7b2b7d8 1088 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 1089 {
dkato 0:702bf7b2b7d8 1090 /* check whether p_remain is NULL */
dkato 0:702bf7b2b7d8 1091 if (NULL != p_remain)
dkato 0:702bf7b2b7d8 1092 {
dkato 0:702bf7b2b7d8 1093 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 1094
dkato 0:702bf7b2b7d8 1095 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 1096 {
dkato 0:702bf7b2b7d8 1097 if (DMA_CH_TRANSFER == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1098 {
dkato 0:702bf7b2b7d8 1099 /* set up address parameter for continous DMA*/
dkato 0:702bf7b2b7d8 1100 DMA_Stop(channel, p_remain);
dkato 0:702bf7b2b7d8 1101 }
dkato 0:702bf7b2b7d8 1102 else
dkato 0:702bf7b2b7d8 1103 {
dkato 0:702bf7b2b7d8 1104 /* set error return value */
dkato 0:702bf7b2b7d8 1105 retval = EERROR;
dkato 0:702bf7b2b7d8 1106 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1107 {
dkato 0:702bf7b2b7d8 1108 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 1109 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 1110 break;
dkato 0:702bf7b2b7d8 1111
dkato 0:702bf7b2b7d8 1112 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 1113 error_code = EBADF;
dkato 0:702bf7b2b7d8 1114 break;
dkato 0:702bf7b2b7d8 1115
dkato 0:702bf7b2b7d8 1116 case DMA_CH_OPEN:
dkato 0:702bf7b2b7d8 1117 error_code = EBADF;
dkato 0:702bf7b2b7d8 1118 break;
dkato 0:702bf7b2b7d8 1119
dkato 0:702bf7b2b7d8 1120 default:
dkato 0:702bf7b2b7d8 1121 error_code = EFAULT;
dkato 0:702bf7b2b7d8 1122 break;
dkato 0:702bf7b2b7d8 1123 }
dkato 0:702bf7b2b7d8 1124 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 1125 }
dkato 0:702bf7b2b7d8 1126 }
dkato 0:702bf7b2b7d8 1127 }
dkato 0:702bf7b2b7d8 1128 else
dkato 0:702bf7b2b7d8 1129 {
dkato 0:702bf7b2b7d8 1130 /* set error return value */
dkato 0:702bf7b2b7d8 1131 retval = EERROR;
dkato 0:702bf7b2b7d8 1132 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 1133 }
dkato 0:702bf7b2b7d8 1134 }
dkato 0:702bf7b2b7d8 1135 else
dkato 0:702bf7b2b7d8 1136 {
dkato 0:702bf7b2b7d8 1137 /* set error return value */
dkato 0:702bf7b2b7d8 1138 retval = EERROR;
dkato 0:702bf7b2b7d8 1139 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 1140 }
dkato 0:702bf7b2b7d8 1141
dkato 5:1390bfcb667c 1142 if (0 == was_masked)
dkato 5:1390bfcb667c 1143 {
dkato 5:1390bfcb667c 1144 __enable_irq();
dkato 5:1390bfcb667c 1145 }
dkato 5:1390bfcb667c 1146
dkato 0:702bf7b2b7d8 1147 return retval;
dkato 0:702bf7b2b7d8 1148 }
dkato 0:702bf7b2b7d8 1149
dkato 0:702bf7b2b7d8 1150 /******************************************************************************
dkato 0:702bf7b2b7d8 1151 End of function R_DMA_Cancel
dkato 0:702bf7b2b7d8 1152 ******************************************************************************/
dkato 0:702bf7b2b7d8 1153