RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Mon Jun 01 08:33:21 2015 +0000
Revision:
0:702bf7b2b7d8
Child:
5:1390bfcb667c
first comit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:702bf7b2b7d8 1 /*******************************************************************************
dkato 0:702bf7b2b7d8 2 * DISCLAIMER
dkato 0:702bf7b2b7d8 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:702bf7b2b7d8 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:702bf7b2b7d8 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:702bf7b2b7d8 6 * all applicable laws, including copyright laws.
dkato 0:702bf7b2b7d8 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:702bf7b2b7d8 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:702bf7b2b7d8 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:702bf7b2b7d8 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:702bf7b2b7d8 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:702bf7b2b7d8 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:702bf7b2b7d8 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:702bf7b2b7d8 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:702bf7b2b7d8 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:702bf7b2b7d8 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:702bf7b2b7d8 17 * and to discontinue the availability of this software. By using this software,
dkato 0:702bf7b2b7d8 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:702bf7b2b7d8 19 * following link:
dkato 0:702bf7b2b7d8 20 * http://www.renesas.com/disclaimer*
dkato 0:702bf7b2b7d8 21 * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
dkato 0:702bf7b2b7d8 22 *******************************************************************************/
dkato 0:702bf7b2b7d8 23
dkato 0:702bf7b2b7d8 24 /**************************************************************************//**
dkato 0:702bf7b2b7d8 25 * @file dma_if.c
dkato 0:702bf7b2b7d8 26 * $Rev: 1317 $
dkato 0:702bf7b2b7d8 27 * $Date:: 2014-12-04 10:43:59 +0900#$
dkato 0:702bf7b2b7d8 28 * @brief DMA Driver interface functions
dkato 0:702bf7b2b7d8 29 ******************************************************************************/
dkato 0:702bf7b2b7d8 30
dkato 0:702bf7b2b7d8 31 /*****************************************************************************
dkato 0:702bf7b2b7d8 32 * History : DD.MM.YYYY Version Description
dkato 0:702bf7b2b7d8 33 * : 15.01.2013 1.00 First Release
dkato 0:702bf7b2b7d8 34 ******************************************************************************/
dkato 0:702bf7b2b7d8 35
dkato 0:702bf7b2b7d8 36 /*******************************************************************************
dkato 0:702bf7b2b7d8 37 Includes <System Includes>, "Project Includes"
dkato 0:702bf7b2b7d8 38 *******************************************************************************/
dkato 0:702bf7b2b7d8 39
dkato 0:702bf7b2b7d8 40 #include "dma.h"
dkato 0:702bf7b2b7d8 41 #include "bsp_util.h"
dkato 0:702bf7b2b7d8 42
dkato 0:702bf7b2b7d8 43 /******************************************************************************
dkato 0:702bf7b2b7d8 44 Private global tables
dkato 0:702bf7b2b7d8 45 ******************************************************************************/
dkato 0:702bf7b2b7d8 46
dkato 0:702bf7b2b7d8 47 /******************************************************************************
dkato 0:702bf7b2b7d8 48 Private global driver semaphore information
dkato 0:702bf7b2b7d8 49 ******************************************************************************/
dkato 0:702bf7b2b7d8 50
dkato 0:702bf7b2b7d8 51 /* driver semaphore define */
dkato 0:702bf7b2b7d8 52 /* ->MISRA 8.8, 8.10, IPA M2.2.2 There is no problem in the description of declaration of
dkato 0:702bf7b2b7d8 53 OS resource itself */
dkato 0:702bf7b2b7d8 54 osSemaphoreDef(sem_dma_drv);
dkato 0:702bf7b2b7d8 55 /* <-MISRA 8.8, 8.10, IPA M2.2.2 */
dkato 0:702bf7b2b7d8 56
dkato 0:702bf7b2b7d8 57 /******************************************************************************
dkato 0:702bf7b2b7d8 58 * Function Name: R_DMA_Init
dkato 0:702bf7b2b7d8 59 * Description : Init DMA driver.
dkato 0:702bf7b2b7d8 60 * Making driver semaphore and check parameter in this function.
dkato 0:702bf7b2b7d8 61 * Arguments : *p_dma_init_param -
dkato 0:702bf7b2b7d8 62 * Point of driver init parameter.
dkato 0:702bf7b2b7d8 63 * *p_errno-
dkato 0:702bf7b2b7d8 64 * Pointer of error code.
dkato 0:702bf7b2b7d8 65 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 66 * error code -
dkato 0:702bf7b2b7d8 67 * OS error num : Registering handler failed.
dkato 0:702bf7b2b7d8 68 * ENOMEM : Making semaphore failed.
dkato 0:702bf7b2b7d8 69 * EPERM : Pointer of callback function which called in DMA
dkato 0:702bf7b2b7d8 70 * error interrupt handler is NULL.
dkato 0:702bf7b2b7d8 71 * EFAULT : dma_init_param is NULL.
dkato 0:702bf7b2b7d8 72 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 73 * Operation successful.
dkato 0:702bf7b2b7d8 74 * EERROR -
dkato 0:702bf7b2b7d8 75 * Error occured.
dkato 0:702bf7b2b7d8 76 ******************************************************************************/
dkato 0:702bf7b2b7d8 77
dkato 0:702bf7b2b7d8 78 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 79 int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 80 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 81 {
dkato 0:702bf7b2b7d8 82 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 83 int_t result_init;
dkato 0:702bf7b2b7d8 84 osSemaphoreId sem_drv_create_id;
dkato 0:702bf7b2b7d8 85
dkato 0:702bf7b2b7d8 86 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 87 sem_drv_create_id = NULL;
dkato 0:702bf7b2b7d8 88
dkato 0:702bf7b2b7d8 89 if (NULL == p_dma_init_param)
dkato 0:702bf7b2b7d8 90 {
dkato 0:702bf7b2b7d8 91 /* set error return value */
dkato 0:702bf7b2b7d8 92 retval = (EERROR);
dkato 0:702bf7b2b7d8 93 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 94 }
dkato 0:702bf7b2b7d8 95
dkato 0:702bf7b2b7d8 96 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 97 {
dkato 0:702bf7b2b7d8 98 /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
dkato 0:702bf7b2b7d8 99 if (NULL == p_dma_init_param->p_aio)
dkato 0:702bf7b2b7d8 100 /* <-MISRA 1.2 */
dkato 0:702bf7b2b7d8 101 {
dkato 0:702bf7b2b7d8 102 /* set error return value */
dkato 0:702bf7b2b7d8 103 retval = (EERROR);
dkato 0:702bf7b2b7d8 104 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 105 }
dkato 0:702bf7b2b7d8 106 }
dkato 0:702bf7b2b7d8 107
dkato 0:702bf7b2b7d8 108 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 109 {
dkato 0:702bf7b2b7d8 110 /* makeing driver semaphore */
dkato 0:702bf7b2b7d8 111 /* make semaphore */
dkato 0:702bf7b2b7d8 112 sem_drv_create_id = osSemaphoreCreate(osSemaphore(sem_dma_drv), 1);
dkato 0:702bf7b2b7d8 113 if (NULL == sem_drv_create_id)
dkato 0:702bf7b2b7d8 114 {
dkato 0:702bf7b2b7d8 115 /* set error return value */
dkato 0:702bf7b2b7d8 116 retval = (EERROR);
dkato 0:702bf7b2b7d8 117 DMA_SetErrCode(ENOMEM, p_errno);
dkato 0:702bf7b2b7d8 118 }
dkato 0:702bf7b2b7d8 119 }
dkato 0:702bf7b2b7d8 120
dkato 0:702bf7b2b7d8 121 if ((ESUCCESS == retval) && (NULL != sem_drv_create_id))
dkato 0:702bf7b2b7d8 122 {
dkato 0:702bf7b2b7d8 123 result_init = DMA_Initialize(p_dma_init_param, sem_drv_create_id);
dkato 0:702bf7b2b7d8 124 if (ESUCCESS != result_init)
dkato 0:702bf7b2b7d8 125 {
dkato 0:702bf7b2b7d8 126 /* set error return value */
dkato 0:702bf7b2b7d8 127 retval = (EERROR);
dkato 0:702bf7b2b7d8 128 DMA_SetErrCode(result_init, p_errno);
dkato 0:702bf7b2b7d8 129 }
dkato 0:702bf7b2b7d8 130 }
dkato 0:702bf7b2b7d8 131
dkato 0:702bf7b2b7d8 132 return retval;
dkato 0:702bf7b2b7d8 133 }
dkato 0:702bf7b2b7d8 134
dkato 0:702bf7b2b7d8 135 /******************************************************************************
dkato 0:702bf7b2b7d8 136 End of function R_DMA_Init
dkato 0:702bf7b2b7d8 137 ******************************************************************************/
dkato 0:702bf7b2b7d8 138
dkato 0:702bf7b2b7d8 139 /******************************************************************************
dkato 0:702bf7b2b7d8 140 * Function Name: R_DMA_UnInit
dkato 0:702bf7b2b7d8 141 * Description : UnInit DMA driver.
dkato 0:702bf7b2b7d8 142 * Delete driver semaphore and check parameter in this function.
dkato 0:702bf7b2b7d8 143 * Arguments : *p_errno-
dkato 0:702bf7b2b7d8 144 * Pointer of error code.
dkato 0:702bf7b2b7d8 145 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 146 * error code -
dkato 0:702bf7b2b7d8 147 * OS error num : Unegistering handler failed.
dkato 0:702bf7b2b7d8 148 * OS error num : Semaphore release failed.
dkato 0:702bf7b2b7d8 149 * OS error num : Semaphore delete failed.
dkato 0:702bf7b2b7d8 150 * EACCES : Driver status isn't DMA_DRV_INIT.
dkato 0:702bf7b2b7d8 151 * EBUSY : It has been allocated already in channel.
dkato 0:702bf7b2b7d8 152 * EFAULT : Wait semaphore failed.
dkato 0:702bf7b2b7d8 153 * Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 154 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 155 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 156 * Operation successful.
dkato 0:702bf7b2b7d8 157 * EERROR -
dkato 0:702bf7b2b7d8 158 * Error occured.
dkato 0:702bf7b2b7d8 159 ******************************************************************************/
dkato 0:702bf7b2b7d8 160
dkato 0:702bf7b2b7d8 161 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 162 int_t R_DMA_UnInit(int32_t * const p_errno)
dkato 0:702bf7b2b7d8 163 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 164 {
dkato 0:702bf7b2b7d8 165 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 166 int_t result_uninit;
dkato 0:702bf7b2b7d8 167 dma_info_drv_t *dma_info_drv;
dkato 0:702bf7b2b7d8 168 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 169 int_t ch_count;
dkato 0:702bf7b2b7d8 170 int32_t sem_wait_status;
dkato 0:702bf7b2b7d8 171 osStatus sem_status;
dkato 0:702bf7b2b7d8 172 bool_t ch_stat_check_flag;
dkato 0:702bf7b2b7d8 173
dkato 0:702bf7b2b7d8 174 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 175
dkato 0:702bf7b2b7d8 176 dma_info_drv = DMA_GetDrvInstance();
dkato 0:702bf7b2b7d8 177
dkato 0:702bf7b2b7d8 178 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 179 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 180 sem_wait_status = osSemaphoreWait(dma_info_drv->sem_drv, osWaitForever);
dkato 0:702bf7b2b7d8 181 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 182 /* semaphore error check */
dkato 0:702bf7b2b7d8 183 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 184 {
dkato 0:702bf7b2b7d8 185 retval = EERROR;
dkato 0:702bf7b2b7d8 186 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 187 }
dkato 0:702bf7b2b7d8 188
dkato 0:702bf7b2b7d8 189 /* check driver status */
dkato 0:702bf7b2b7d8 190 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 191 {
dkato 0:702bf7b2b7d8 192 if (DMA_DRV_INIT != dma_info_drv->drv_stat)
dkato 0:702bf7b2b7d8 193 {
dkato 0:702bf7b2b7d8 194 /* set error return value */
dkato 0:702bf7b2b7d8 195 retval = EERROR;
dkato 0:702bf7b2b7d8 196 DMA_SetErrCode(EACCES, p_errno);
dkato 0:702bf7b2b7d8 197 }
dkato 0:702bf7b2b7d8 198 else
dkato 0:702bf7b2b7d8 199 {
dkato 0:702bf7b2b7d8 200 ch_stat_check_flag = false;
dkato 0:702bf7b2b7d8 201 ch_count = 0;
dkato 0:702bf7b2b7d8 202 while (false == ch_stat_check_flag)
dkato 0:702bf7b2b7d8 203 {
dkato 0:702bf7b2b7d8 204 /* check channel status */
dkato 0:702bf7b2b7d8 205 dma_info_ch = DMA_GetDrvChInfo(ch_count);
dkato 0:702bf7b2b7d8 206 if ((DMA_CH_UNINIT != dma_info_ch->ch_stat) &&
dkato 0:702bf7b2b7d8 207 (DMA_CH_INIT != dma_info_ch->ch_stat))
dkato 0:702bf7b2b7d8 208 {
dkato 0:702bf7b2b7d8 209 /* set error return value */
dkato 0:702bf7b2b7d8 210 retval = EERROR;
dkato 0:702bf7b2b7d8 211 /* check channel status is busy */
dkato 0:702bf7b2b7d8 212 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 213 {
dkato 0:702bf7b2b7d8 214 /* These 2 cases are intentionally combined. */
dkato 0:702bf7b2b7d8 215 case DMA_CH_OPEN:
dkato 0:702bf7b2b7d8 216 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 217 DMA_SetErrCode(EBUSY, p_errno);
dkato 0:702bf7b2b7d8 218 break;
dkato 0:702bf7b2b7d8 219
dkato 0:702bf7b2b7d8 220 default:
dkato 0:702bf7b2b7d8 221 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 222 break;
dkato 0:702bf7b2b7d8 223 }
dkato 0:702bf7b2b7d8 224 }
dkato 0:702bf7b2b7d8 225
dkato 0:702bf7b2b7d8 226 if ((DMA_CH_NUM - 1) == ch_count)
dkato 0:702bf7b2b7d8 227 {
dkato 0:702bf7b2b7d8 228 /* channel status check end */
dkato 0:702bf7b2b7d8 229 ch_stat_check_flag = true;
dkato 0:702bf7b2b7d8 230 }
dkato 0:702bf7b2b7d8 231 ch_count++;
dkato 0:702bf7b2b7d8 232 }
dkato 0:702bf7b2b7d8 233 }
dkato 0:702bf7b2b7d8 234 /* uninitialize DMA */
dkato 0:702bf7b2b7d8 235 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 236 {
dkato 0:702bf7b2b7d8 237 result_uninit = DMA_UnInitialize();
dkato 0:702bf7b2b7d8 238 if (ESUCCESS != result_uninit)
dkato 0:702bf7b2b7d8 239 {
dkato 0:702bf7b2b7d8 240 /* set error return value */
dkato 0:702bf7b2b7d8 241 retval = EERROR;
dkato 0:702bf7b2b7d8 242 DMA_SetErrCode(result_uninit, p_errno);
dkato 0:702bf7b2b7d8 243 }
dkato 0:702bf7b2b7d8 244 }
dkato 0:702bf7b2b7d8 245 /* semaphore release */
dkato 0:702bf7b2b7d8 246 sem_status = osSemaphoreRelease(dma_info_drv->sem_drv);
dkato 0:702bf7b2b7d8 247 if (osOK != sem_status)
dkato 0:702bf7b2b7d8 248 {
dkato 0:702bf7b2b7d8 249 /* set error return value */
dkato 0:702bf7b2b7d8 250 retval = EERROR;
dkato 0:702bf7b2b7d8 251 DMA_SetErrCode((int_t)sem_status, p_errno);
dkato 0:702bf7b2b7d8 252 }
dkato 0:702bf7b2b7d8 253
dkato 0:702bf7b2b7d8 254 if ((osOK == sem_status) && (ESUCCESS == retval))
dkato 0:702bf7b2b7d8 255 {
dkato 0:702bf7b2b7d8 256 /* semaphore delete */
dkato 0:702bf7b2b7d8 257 sem_status = osSemaphoreDelete(dma_info_drv->sem_drv);
dkato 0:702bf7b2b7d8 258 if (osOK != sem_status)
dkato 0:702bf7b2b7d8 259 {
dkato 0:702bf7b2b7d8 260 /* set error return value */
dkato 0:702bf7b2b7d8 261 retval = EERROR;
dkato 0:702bf7b2b7d8 262 DMA_SetErrCode((int_t)sem_status, p_errno);
dkato 0:702bf7b2b7d8 263 }
dkato 0:702bf7b2b7d8 264 }
dkato 0:702bf7b2b7d8 265 }
dkato 0:702bf7b2b7d8 266
dkato 0:702bf7b2b7d8 267 return retval;
dkato 0:702bf7b2b7d8 268 }
dkato 0:702bf7b2b7d8 269
dkato 0:702bf7b2b7d8 270 /******************************************************************************
dkato 0:702bf7b2b7d8 271 End of function R_DMA_UnInit
dkato 0:702bf7b2b7d8 272 ******************************************************************************/
dkato 0:702bf7b2b7d8 273
dkato 0:702bf7b2b7d8 274 /******************************************************************************
dkato 0:702bf7b2b7d8 275 * Function Name: R_DMA_Alloc
dkato 0:702bf7b2b7d8 276 * Description : Open DMA channel.
dkato 0:702bf7b2b7d8 277 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 278 * Arguments : channel -
dkato 0:702bf7b2b7d8 279 * Open channel number.
dkato 0:702bf7b2b7d8 280 * If channel is (-1), it looking for free chanel and allocate.
dkato 0:702bf7b2b7d8 281 * *p_errno -
dkato 0:702bf7b2b7d8 282 * Pointer of error code.
dkato 0:702bf7b2b7d8 283 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 284 * error code -
dkato 0:702bf7b2b7d8 285 * OS error num : Semaphore release failed.
dkato 0:702bf7b2b7d8 286 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 287 * DMA_ALLOC_CH(-1) <= ch < DMA_CH_NUM.
dkato 0:702bf7b2b7d8 288 * EACCES : Driver status isn't DMA_DRV_INIT.
dkato 0:702bf7b2b7d8 289 * EBUSY : It has been allocated already in channel.
dkato 0:702bf7b2b7d8 290 * EMFILE : When looking for a free channel, but a free channel
dkato 0:702bf7b2b7d8 291 * didn't exist.
dkato 0:702bf7b2b7d8 292 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 293 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 294 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 295 * Wait semaphore failed.
dkato 0:702bf7b2b7d8 296 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 297 * Operation successful.
dkato 0:702bf7b2b7d8 298 * EERROR -
dkato 0:702bf7b2b7d8 299 * Error occured.
dkato 0:702bf7b2b7d8 300 ******************************************************************************/
dkato 0:702bf7b2b7d8 301
dkato 0:702bf7b2b7d8 302 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 303 int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 304 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 305 {
dkato 0:702bf7b2b7d8 306 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 307 int_t ercd = ESUCCESS;
dkato 0:702bf7b2b7d8 308 int_t get_ch_num;
dkato 0:702bf7b2b7d8 309 dma_info_drv_t *dma_info_drv;
dkato 0:702bf7b2b7d8 310 int_t sem_wait_status;
dkato 0:702bf7b2b7d8 311 osStatus sem_release_status;
dkato 0:702bf7b2b7d8 312
dkato 0:702bf7b2b7d8 313 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 314
dkato 0:702bf7b2b7d8 315 /* check driver status */
dkato 0:702bf7b2b7d8 316 dma_info_drv = DMA_GetDrvInstance();
dkato 0:702bf7b2b7d8 317
dkato 0:702bf7b2b7d8 318 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 319 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 320 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 321 {
dkato 0:702bf7b2b7d8 322 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 323 sem_wait_status = osSemaphoreWait(dma_info_drv->sem_drv, osWaitForever);
dkato 0:702bf7b2b7d8 324 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 325 /* semaphore error check */
dkato 0:702bf7b2b7d8 326 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 327 {
dkato 0:702bf7b2b7d8 328 ercd = EFAULT;
dkato 0:702bf7b2b7d8 329 }
dkato 0:702bf7b2b7d8 330 }
dkato 0:702bf7b2b7d8 331
dkato 0:702bf7b2b7d8 332 if (ESUCCESS == ercd)
dkato 0:702bf7b2b7d8 333 {
dkato 0:702bf7b2b7d8 334 if (DMA_DRV_INIT != dma_info_drv->drv_stat)
dkato 0:702bf7b2b7d8 335 {
dkato 0:702bf7b2b7d8 336 /* set error return value */
dkato 0:702bf7b2b7d8 337 ercd = EACCES;
dkato 0:702bf7b2b7d8 338 }
dkato 0:702bf7b2b7d8 339 else
dkato 0:702bf7b2b7d8 340 {
dkato 0:702bf7b2b7d8 341 /* check channel of argment */
dkato 0:702bf7b2b7d8 342 if ((DMA_ALLOC_CH <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 343 {
dkato 0:702bf7b2b7d8 344 if (DMA_ALLOC_CH == channel)
dkato 0:702bf7b2b7d8 345 {
dkato 0:702bf7b2b7d8 346 get_ch_num = DMA_GetFreeChannel();
dkato 0:702bf7b2b7d8 347 }
dkato 0:702bf7b2b7d8 348 else
dkato 0:702bf7b2b7d8 349 {
dkato 0:702bf7b2b7d8 350 get_ch_num = DMA_GetFixedChannel(channel);
dkato 0:702bf7b2b7d8 351 }
dkato 0:702bf7b2b7d8 352
dkato 0:702bf7b2b7d8 353 /* check return number or error number */
dkato 0:702bf7b2b7d8 354 if ((DMA_ALLOC_CH < get_ch_num) && (get_ch_num < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 355 {
dkato 0:702bf7b2b7d8 356 /* set channel number to return value */
dkato 0:702bf7b2b7d8 357 retval = get_ch_num;
dkato 0:702bf7b2b7d8 358 }
dkato 0:702bf7b2b7d8 359 else
dkato 0:702bf7b2b7d8 360 {
dkato 0:702bf7b2b7d8 361 /* set error code to error value */
dkato 0:702bf7b2b7d8 362 ercd = get_ch_num;
dkato 0:702bf7b2b7d8 363 }
dkato 0:702bf7b2b7d8 364 }
dkato 0:702bf7b2b7d8 365 else
dkato 0:702bf7b2b7d8 366 {
dkato 0:702bf7b2b7d8 367 /* set error return value */
dkato 0:702bf7b2b7d8 368 ercd = EINVAL;
dkato 0:702bf7b2b7d8 369 }
dkato 0:702bf7b2b7d8 370 }
dkato 0:702bf7b2b7d8 371 /* semaphore release */
dkato 0:702bf7b2b7d8 372 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 373 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 374 {
dkato 0:702bf7b2b7d8 375 sem_release_status = osSemaphoreRelease(dma_info_drv->sem_drv);
dkato 0:702bf7b2b7d8 376 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 377 {
dkato 0:702bf7b2b7d8 378 /* set error return value */
dkato 0:702bf7b2b7d8 379 ercd = (int_t)sem_release_status;
dkato 0:702bf7b2b7d8 380 }
dkato 0:702bf7b2b7d8 381 }
dkato 0:702bf7b2b7d8 382 }
dkato 0:702bf7b2b7d8 383
dkato 0:702bf7b2b7d8 384 /* occured error check */
dkato 0:702bf7b2b7d8 385 if (ESUCCESS != ercd)
dkato 0:702bf7b2b7d8 386 {
dkato 0:702bf7b2b7d8 387 retval = EERROR;
dkato 0:702bf7b2b7d8 388 DMA_SetErrCode(ercd, p_errno);
dkato 0:702bf7b2b7d8 389 }
dkato 0:702bf7b2b7d8 390
dkato 0:702bf7b2b7d8 391 return retval;
dkato 0:702bf7b2b7d8 392 }
dkato 0:702bf7b2b7d8 393
dkato 0:702bf7b2b7d8 394 /******************************************************************************
dkato 0:702bf7b2b7d8 395 End of function R_DMA_Alloc
dkato 0:702bf7b2b7d8 396 ******************************************************************************/
dkato 0:702bf7b2b7d8 397
dkato 0:702bf7b2b7d8 398 /******************************************************************************
dkato 0:702bf7b2b7d8 399 * Function Name: R_DMA_Free
dkato 0:702bf7b2b7d8 400 * Description : Close DMA channel.
dkato 0:702bf7b2b7d8 401 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 402 * Arguments : channel -
dkato 0:702bf7b2b7d8 403 * Close channel number.
dkato 0:702bf7b2b7d8 404 * *p_errno -
dkato 0:702bf7b2b7d8 405 * Pointer of error code.
dkato 0:702bf7b2b7d8 406 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 407 * error code -
dkato 0:702bf7b2b7d8 408 * OS error num : Semaphore release failed.
dkato 0:702bf7b2b7d8 409 * EBADF : Channel status is DMA_CH_INIT.
dkato 0:702bf7b2b7d8 410 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 411 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 412 * EACCES : Driver status isn't DMA_DRV_INIT.
dkato 0:702bf7b2b7d8 413 * EBUSY : It has been start DMA transfer in channel.
dkato 0:702bf7b2b7d8 414 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 415 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 416 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 417 * Wait semaphore failed.
dkato 0:702bf7b2b7d8 418 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 419 * Operation successful.
dkato 0:702bf7b2b7d8 420 * EERROR -
dkato 0:702bf7b2b7d8 421 * Error occured.
dkato 0:702bf7b2b7d8 422 ******************************************************************************/
dkato 0:702bf7b2b7d8 423
dkato 0:702bf7b2b7d8 424 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 425 int_t R_DMA_Free(const int_t channel, int32_t *const p_errno)
dkato 0:702bf7b2b7d8 426 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 427 {
dkato 0:702bf7b2b7d8 428 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 429 dma_info_drv_t *dma_info_drv;
dkato 0:702bf7b2b7d8 430 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 431 int_t sem_wait_status;
dkato 0:702bf7b2b7d8 432 osStatus sem_release_status;
dkato 0:702bf7b2b7d8 433 int_t error_code;
dkato 0:702bf7b2b7d8 434
dkato 0:702bf7b2b7d8 435 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 436
dkato 0:702bf7b2b7d8 437 /* check channel of argument */
dkato 0:702bf7b2b7d8 438 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 439 {
dkato 0:702bf7b2b7d8 440 /* check driver status */
dkato 0:702bf7b2b7d8 441 dma_info_drv = DMA_GetDrvInstance();
dkato 0:702bf7b2b7d8 442
dkato 0:702bf7b2b7d8 443 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 444 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 445 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 446 {
dkato 0:702bf7b2b7d8 447 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 448 sem_wait_status = osSemaphoreWait(dma_info_drv->sem_drv, osWaitForever);
dkato 0:702bf7b2b7d8 449 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 450 /* semaphore error check */
dkato 0:702bf7b2b7d8 451 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 452 {
dkato 0:702bf7b2b7d8 453 retval = EERROR;
dkato 0:702bf7b2b7d8 454 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 455 }
dkato 0:702bf7b2b7d8 456 }
dkato 0:702bf7b2b7d8 457
dkato 0:702bf7b2b7d8 458 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 459 {
dkato 0:702bf7b2b7d8 460 /* check driver status */
dkato 0:702bf7b2b7d8 461 if (DMA_DRV_INIT == dma_info_drv->drv_stat)
dkato 0:702bf7b2b7d8 462 {
dkato 0:702bf7b2b7d8 463 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 464 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 465 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 466 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 467 {
dkato 0:702bf7b2b7d8 468 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 469 sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
dkato 0:702bf7b2b7d8 470 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 471 /* semaphore error check */
dkato 0:702bf7b2b7d8 472 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 473 {
dkato 0:702bf7b2b7d8 474 /* set error return value */
dkato 0:702bf7b2b7d8 475 retval = EERROR;
dkato 0:702bf7b2b7d8 476 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 477 }
dkato 0:702bf7b2b7d8 478 }
dkato 0:702bf7b2b7d8 479
dkato 0:702bf7b2b7d8 480 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 481 {
dkato 0:702bf7b2b7d8 482 if (DMA_CH_OPEN == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 483 {
dkato 0:702bf7b2b7d8 484 DMA_CloseChannel(channel);
dkato 0:702bf7b2b7d8 485 }
dkato 0:702bf7b2b7d8 486 else
dkato 0:702bf7b2b7d8 487 {
dkato 0:702bf7b2b7d8 488 /* set error return value */
dkato 0:702bf7b2b7d8 489 retval = EERROR;
dkato 0:702bf7b2b7d8 490 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 491 {
dkato 0:702bf7b2b7d8 492 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 493 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 494 break;
dkato 0:702bf7b2b7d8 495
dkato 0:702bf7b2b7d8 496 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 497 error_code = EBADF;
dkato 0:702bf7b2b7d8 498 break;
dkato 0:702bf7b2b7d8 499
dkato 0:702bf7b2b7d8 500 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 501 error_code = EBUSY;
dkato 0:702bf7b2b7d8 502 break;
dkato 0:702bf7b2b7d8 503
dkato 0:702bf7b2b7d8 504 default:
dkato 0:702bf7b2b7d8 505 error_code = EFAULT;
dkato 0:702bf7b2b7d8 506 break;
dkato 0:702bf7b2b7d8 507 }
dkato 0:702bf7b2b7d8 508 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 509 }
dkato 0:702bf7b2b7d8 510 /* semaphore release */
dkato 0:702bf7b2b7d8 511 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 512 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 513 {
dkato 0:702bf7b2b7d8 514 sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
dkato 0:702bf7b2b7d8 515 /* semaphore error check */
dkato 0:702bf7b2b7d8 516 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 517 {
dkato 0:702bf7b2b7d8 518 /* set error return value */
dkato 0:702bf7b2b7d8 519 retval = EERROR;
dkato 0:702bf7b2b7d8 520 DMA_SetErrCode((int_t)sem_release_status, p_errno);
dkato 0:702bf7b2b7d8 521 }
dkato 0:702bf7b2b7d8 522 }
dkato 0:702bf7b2b7d8 523 }
dkato 0:702bf7b2b7d8 524 }
dkato 0:702bf7b2b7d8 525 else
dkato 0:702bf7b2b7d8 526 {
dkato 0:702bf7b2b7d8 527 /* set error return value */
dkato 0:702bf7b2b7d8 528 retval = EERROR;
dkato 0:702bf7b2b7d8 529 DMA_SetErrCode(EACCES, p_errno);
dkato 0:702bf7b2b7d8 530
dkato 0:702bf7b2b7d8 531 }
dkato 0:702bf7b2b7d8 532 /* semaphore release */
dkato 0:702bf7b2b7d8 533 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 534 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 535 {
dkato 0:702bf7b2b7d8 536 sem_release_status = osSemaphoreRelease(dma_info_drv->sem_drv);
dkato 0:702bf7b2b7d8 537 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 538 {
dkato 0:702bf7b2b7d8 539 /* set error return value */
dkato 0:702bf7b2b7d8 540 retval = EERROR;
dkato 0:702bf7b2b7d8 541 DMA_SetErrCode((int_t)sem_release_status, p_errno);
dkato 0:702bf7b2b7d8 542 }
dkato 0:702bf7b2b7d8 543 }
dkato 0:702bf7b2b7d8 544 }
dkato 0:702bf7b2b7d8 545 }
dkato 0:702bf7b2b7d8 546 else
dkato 0:702bf7b2b7d8 547 {
dkato 0:702bf7b2b7d8 548 /* set error return value */
dkato 0:702bf7b2b7d8 549 retval = EERROR;
dkato 0:702bf7b2b7d8 550 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 551 }
dkato 0:702bf7b2b7d8 552
dkato 0:702bf7b2b7d8 553 return retval;
dkato 0:702bf7b2b7d8 554 }
dkato 0:702bf7b2b7d8 555
dkato 0:702bf7b2b7d8 556 /******************************************************************************
dkato 0:702bf7b2b7d8 557 End of function R_DMA_Free
dkato 0:702bf7b2b7d8 558 ******************************************************************************/
dkato 0:702bf7b2b7d8 559
dkato 0:702bf7b2b7d8 560 /******************************************************************************
dkato 0:702bf7b2b7d8 561 * Function Name: R_DMA_Setup
dkato 0:702bf7b2b7d8 562 * Description : Setup DMA transfer parameter.
dkato 0:702bf7b2b7d8 563 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 564 * Arguments : channel -
dkato 0:702bf7b2b7d8 565 * Setup channel number.
dkato 0:702bf7b2b7d8 566 * *p_ch_setup -
dkato 0:702bf7b2b7d8 567 * Set up parameters.
dkato 0:702bf7b2b7d8 568 * *p_errno -
dkato 0:702bf7b2b7d8 569 * Pointer of error code.
dkato 0:702bf7b2b7d8 570 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 571 * error code -
dkato 0:702bf7b2b7d8 572 * OS error num : Semaphore release failed.
dkato 0:702bf7b2b7d8 573 * EBADF : Channel status is DMA_CH_INIT.
dkato 0:702bf7b2b7d8 574 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 575 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 576 * EBUSY : It has been start DMA transfer in channel.
dkato 0:702bf7b2b7d8 577 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 578 * EPERM : The value in p_ch_setup isn't in the right range.
dkato 0:702bf7b2b7d8 579 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 580 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 581 * p_ch_setup is NULL.
dkato 0:702bf7b2b7d8 582 * Wait semaphore failed.
dkato 0:702bf7b2b7d8 583 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 584 * Operation successful.
dkato 0:702bf7b2b7d8 585 * EERROR -
dkato 0:702bf7b2b7d8 586 * Error occured.
dkato 0:702bf7b2b7d8 587 ******************************************************************************/
dkato 0:702bf7b2b7d8 588
dkato 0:702bf7b2b7d8 589 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 590 int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
dkato 0:702bf7b2b7d8 591 int32_t * const p_errno)
dkato 0:702bf7b2b7d8 592 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 593 {
dkato 0:702bf7b2b7d8 594 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 595 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 596 int_t sem_wait_status;
dkato 0:702bf7b2b7d8 597 osStatus sem_release_status;
dkato 0:702bf7b2b7d8 598 int_t error_code;
dkato 0:702bf7b2b7d8 599 uint32_t cfg_table_count;
dkato 0:702bf7b2b7d8 600 dma_ch_cfg_t ch_cfg_set_table;
dkato 0:702bf7b2b7d8 601 uint32_t set_reqd;
dkato 0:702bf7b2b7d8 602 bool_t check_table_flag;
dkato 0:702bf7b2b7d8 603
dkato 0:702bf7b2b7d8 604 /* Resouce Configure Set Table */
dkato 0:702bf7b2b7d8 605 static const dma_ch_cfg_t ch_cfg_table[DMA_CH_CONFIG_TABLE_NUM] =
dkato 0:702bf7b2b7d8 606 {
dkato 0:702bf7b2b7d8 607 {DMA_RS_OSTIM0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 608 {DMA_RS_OSTIM1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 609 {DMA_RS_TGI0A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 610 {DMA_RS_TGI1A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 611 {DMA_RS_TGI2A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 612 {DMA_RS_TGI3A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 613 {DMA_RS_TGI4A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 614 {DMA_RS_TXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 615 {DMA_RS_RXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 616 {DMA_RS_TXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 617 {DMA_RS_RXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 618 {DMA_RS_TXI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 619 {DMA_RS_RXI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 620 {DMA_RS_TXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 621 {DMA_RS_RXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 622 {DMA_RS_TXI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 623 {DMA_RS_RXI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 624 {DMA_RS_TXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 625 {DMA_RS_RXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 626 {DMA_RS_TXI6, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 627 {DMA_RS_RXI6, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 628 {DMA_RS_TXI7, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 629 {DMA_RS_RXI7, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 630 {DMA_RS_USB0_DMA0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 631 {DMA_RS_USB0_DMA1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 632 {DMA_RS_USB1_DMA0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 633 {DMA_RS_USB1_DMA1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 634 {DMA_RS_ADEND, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 635 {DMA_RS_IEBBTD, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 636 {DMA_RS_IEBBTV, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 637 {DMA_RS_IREADY, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 638 {DMA_RS_FLDT, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 639 {DMA_RS_SDHI_0T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 640 {DMA_RS_SDHI_0R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 641 {DMA_RS_SDHI_1T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 642 {DMA_RS_SDHI_1R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 643 {DMA_RS_MMCT, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 644 {DMA_RS_MMCR, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 645 {DMA_RS_SSITXI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 646 {DMA_RS_SSIRXI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 647 {DMA_RS_SSITXI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 648 {DMA_RS_SSIRXI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 649 {DMA_RS_SSIRTI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 650 {DMA_RS_SSITXI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 651 {DMA_RS_SSIRXI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 652 {DMA_RS_SSIRTI4, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 653 {DMA_RS_SSITXI5, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 654 {DMA_RS_SSIRXI5, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 655 {DMA_RS_SCUTXI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 656 {DMA_RS_SCURXI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 657 {DMA_RS_SCUTXI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 658 {DMA_RS_SCURXI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 659 {DMA_RS_SCUTXI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 660 {DMA_RS_SCURXI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 661 {DMA_RS_SCUTXI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 662 {DMA_RS_SCURXI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 663 {DMA_RS_SPTI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 664 {DMA_RS_SPRI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 665 {DMA_RS_SPTI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 666 {DMA_RS_SPRI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 667 {DMA_RS_SPTI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 668 {DMA_RS_SPRI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 669 {DMA_RS_SPTI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 670 {DMA_RS_SPRI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 671 {DMA_RS_SPTI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 672 {DMA_RS_SPRI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 673 {DMA_RS_SPDIFTXI, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 674 {DMA_RS_SPDIFRXI, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 675 {DMA_RS_CMI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 676 {DMA_RS_CMI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 677 {DMA_RS_MLBCI, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 678 {DMA_RS_SGDEI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 679 {DMA_RS_SGDEI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 680 {DMA_RS_SGDEI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 681 {DMA_RS_SGDEI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 682 {DMA_RS_SCUTXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 683 {DMA_RS_SCURXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 684 {DMA_RS_SCUTXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 685 {DMA_RS_SCURXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 686 {DMA_RS_TI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 687 {DMA_RS_RI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 688 {DMA_RS_TI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 689 {DMA_RS_RI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 690 {DMA_RS_TI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 691 {DMA_RS_RI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 692 {DMA_RS_TI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 693 {DMA_RS_RI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 694 {DMA_RS_LIN0_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 695 {DMA_RS_LIN0_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 696 {DMA_RS_LIN1_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 697 {DMA_RS_LIN1_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 698 {DMA_RS_IFEI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 699 {DMA_RS_OFFI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 700 {DMA_RS_IFEI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 701 {DMA_RS_OFFI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC }
dkato 0:702bf7b2b7d8 702 };
dkato 0:702bf7b2b7d8 703
dkato 0:702bf7b2b7d8 704 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 705 /* dummy init set_reqd */
dkato 0:702bf7b2b7d8 706 set_reqd = CHCFG_REQD_UNDEFINED;
dkato 0:702bf7b2b7d8 707 ch_cfg_set_table = ch_cfg_table[0];
dkato 0:702bf7b2b7d8 708
dkato 0:702bf7b2b7d8 709 /* check channel of argument */
dkato 0:702bf7b2b7d8 710 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 711 {
dkato 0:702bf7b2b7d8 712 if (NULL != p_ch_setup)
dkato 0:702bf7b2b7d8 713 {
dkato 0:702bf7b2b7d8 714 /* check setup parameter */
dkato 0:702bf7b2b7d8 715 /* check AIOCB pointer */
dkato 0:702bf7b2b7d8 716 if (NULL == p_ch_setup->p_aio)
dkato 0:702bf7b2b7d8 717 {
dkato 0:702bf7b2b7d8 718 /* set error return value */
dkato 0:702bf7b2b7d8 719 retval = EERROR;
dkato 0:702bf7b2b7d8 720 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 721 }
dkato 0:702bf7b2b7d8 722
dkato 0:702bf7b2b7d8 723 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 724 {
dkato 0:702bf7b2b7d8 725 /* check DMA transfer unit size for destination */
dkato 0:702bf7b2b7d8 726 if (((int_t)p_ch_setup->dst_width <= DMA_UNIT_MIN) ||
dkato 0:702bf7b2b7d8 727 ((int_t)p_ch_setup->dst_width >= DMA_UNIT_MAX))
dkato 0:702bf7b2b7d8 728 {
dkato 0:702bf7b2b7d8 729 /* set error return value */
dkato 0:702bf7b2b7d8 730 retval = EERROR;
dkato 0:702bf7b2b7d8 731 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 732 }
dkato 0:702bf7b2b7d8 733 }
dkato 0:702bf7b2b7d8 734
dkato 0:702bf7b2b7d8 735 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 736 {
dkato 0:702bf7b2b7d8 737 /* check DMA transfer unit size for source */
dkato 0:702bf7b2b7d8 738 if (((int_t)p_ch_setup->src_width <= DMA_UNIT_MIN) ||
dkato 0:702bf7b2b7d8 739 ((int_t)p_ch_setup->src_width >= DMA_UNIT_MAX))
dkato 0:702bf7b2b7d8 740 {
dkato 0:702bf7b2b7d8 741 /* set error return value */
dkato 0:702bf7b2b7d8 742 retval = EERROR;
dkato 0:702bf7b2b7d8 743 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 744 }
dkato 0:702bf7b2b7d8 745 }
dkato 0:702bf7b2b7d8 746
dkato 0:702bf7b2b7d8 747 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 748 {
dkato 0:702bf7b2b7d8 749 /* check DMA address count direction for destination */
dkato 0:702bf7b2b7d8 750 if (((int_t)p_ch_setup->dst_cnt <= DMA_ADDR_MIN) ||
dkato 0:702bf7b2b7d8 751 ((int_t)p_ch_setup->dst_cnt >= DMA_ADDR_MAX))
dkato 0:702bf7b2b7d8 752 {
dkato 0:702bf7b2b7d8 753 /* set error return value */
dkato 0:702bf7b2b7d8 754 retval = EERROR;
dkato 0:702bf7b2b7d8 755 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 756 }
dkato 0:702bf7b2b7d8 757 }
dkato 0:702bf7b2b7d8 758
dkato 0:702bf7b2b7d8 759 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 760 {
dkato 0:702bf7b2b7d8 761 /* check DMA address count direction for source */
dkato 0:702bf7b2b7d8 762 if (((int_t)(p_ch_setup->src_cnt) <= DMA_ADDR_MIN) ||
dkato 0:702bf7b2b7d8 763 ((int_t)p_ch_setup->src_cnt >= DMA_ADDR_MAX))
dkato 0:702bf7b2b7d8 764 {
dkato 0:702bf7b2b7d8 765 /* set error return value */
dkato 0:702bf7b2b7d8 766 retval = EERROR;
dkato 0:702bf7b2b7d8 767 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 768 }
dkato 0:702bf7b2b7d8 769 }
dkato 0:702bf7b2b7d8 770
dkato 0:702bf7b2b7d8 771 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 772 {
dkato 0:702bf7b2b7d8 773 /* check DMA transfer direction */
dkato 0:702bf7b2b7d8 774 if (((int_t)p_ch_setup->direction <= DMA_REQ_MIN) ||
dkato 0:702bf7b2b7d8 775 ((int_t)p_ch_setup->direction >= DMA_REQ_MAX))
dkato 0:702bf7b2b7d8 776 {
dkato 0:702bf7b2b7d8 777 /* set error return value */
dkato 0:702bf7b2b7d8 778 retval = EERROR;
dkato 0:702bf7b2b7d8 779 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 780 }
dkato 0:702bf7b2b7d8 781 }
dkato 0:702bf7b2b7d8 782
dkato 0:702bf7b2b7d8 783 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 784 {
dkato 0:702bf7b2b7d8 785 /* check DMA transfer resouce */
dkato 0:702bf7b2b7d8 786 check_table_flag = false;
dkato 0:702bf7b2b7d8 787 cfg_table_count = 0;
dkato 0:702bf7b2b7d8 788 while (false == check_table_flag)
dkato 0:702bf7b2b7d8 789 {
dkato 0:702bf7b2b7d8 790 if (p_ch_setup->resource == ch_cfg_table[cfg_table_count].dmars)
dkato 0:702bf7b2b7d8 791 {
dkato 0:702bf7b2b7d8 792 /* check reqd is undefined */
dkato 0:702bf7b2b7d8 793 if (CHCFG_REQD_UNDEFINED == ch_cfg_table[cfg_table_count].reqd)
dkato 0:702bf7b2b7d8 794 {
dkato 0:702bf7b2b7d8 795 /* set reqd value on fixed value */
dkato 0:702bf7b2b7d8 796 if (DMA_REQ_SRC == p_ch_setup->direction)
dkato 0:702bf7b2b7d8 797 {
dkato 0:702bf7b2b7d8 798 set_reqd = CHCFG_SET_REQD_SRC;
dkato 0:702bf7b2b7d8 799 }
dkato 0:702bf7b2b7d8 800 else
dkato 0:702bf7b2b7d8 801 {
dkato 0:702bf7b2b7d8 802 set_reqd = CHCFG_SET_REQD_DST;
dkato 0:702bf7b2b7d8 803 }
dkato 0:702bf7b2b7d8 804 }
dkato 0:702bf7b2b7d8 805 else
dkato 0:702bf7b2b7d8 806 {
dkato 0:702bf7b2b7d8 807 /* set reqd value in channel config table */
dkato 0:702bf7b2b7d8 808 set_reqd = ch_cfg_table[cfg_table_count].reqd;
dkato 0:702bf7b2b7d8 809 }
dkato 0:702bf7b2b7d8 810 /* set channel config table address for DMA_SetParam() */
dkato 0:702bf7b2b7d8 811 ch_cfg_set_table = ch_cfg_table[cfg_table_count];
dkato 0:702bf7b2b7d8 812 check_table_flag = true;
dkato 0:702bf7b2b7d8 813 }
dkato 0:702bf7b2b7d8 814 if (false == check_table_flag)
dkato 0:702bf7b2b7d8 815 {
dkato 0:702bf7b2b7d8 816 /* resource value did not exist in channel config table */
dkato 0:702bf7b2b7d8 817 if ((uint32_t)((sizeof(ch_cfg_table)/sizeof(dma_ch_cfg_t)) - 1U) == cfg_table_count)
dkato 0:702bf7b2b7d8 818 {
dkato 0:702bf7b2b7d8 819 /* set error return value */
dkato 0:702bf7b2b7d8 820 retval = EERROR;
dkato 0:702bf7b2b7d8 821 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 822 check_table_flag = true;
dkato 0:702bf7b2b7d8 823 }
dkato 0:702bf7b2b7d8 824 cfg_table_count++;
dkato 0:702bf7b2b7d8 825 }
dkato 0:702bf7b2b7d8 826 }
dkato 0:702bf7b2b7d8 827 }
dkato 0:702bf7b2b7d8 828
dkato 0:702bf7b2b7d8 829 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 830 {
dkato 0:702bf7b2b7d8 831 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 832 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 833 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 834 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 835 {
dkato 0:702bf7b2b7d8 836 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 837 sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
dkato 0:702bf7b2b7d8 838 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 839 /* semaphore error check */
dkato 0:702bf7b2b7d8 840 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 841 {
dkato 0:702bf7b2b7d8 842 /* set error return value */
dkato 0:702bf7b2b7d8 843 retval = EERROR;
dkato 0:702bf7b2b7d8 844 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 845 }
dkato 0:702bf7b2b7d8 846 }
dkato 0:702bf7b2b7d8 847
dkato 0:702bf7b2b7d8 848 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 849 {
dkato 0:702bf7b2b7d8 850 if (DMA_CH_OPEN == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 851 {
dkato 0:702bf7b2b7d8 852 /* set up parameter */
dkato 0:702bf7b2b7d8 853 DMA_SetParam(channel, p_ch_setup, &ch_cfg_set_table, set_reqd);
dkato 0:702bf7b2b7d8 854 }
dkato 0:702bf7b2b7d8 855 else
dkato 0:702bf7b2b7d8 856 {
dkato 0:702bf7b2b7d8 857 /* set error return value */
dkato 0:702bf7b2b7d8 858 retval = EERROR;
dkato 0:702bf7b2b7d8 859 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 860 {
dkato 0:702bf7b2b7d8 861 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 862 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 863 break;
dkato 0:702bf7b2b7d8 864
dkato 0:702bf7b2b7d8 865 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 866 error_code = EBADF;
dkato 0:702bf7b2b7d8 867 break;
dkato 0:702bf7b2b7d8 868
dkato 0:702bf7b2b7d8 869 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 870 error_code = EBUSY;
dkato 0:702bf7b2b7d8 871 break;
dkato 0:702bf7b2b7d8 872
dkato 0:702bf7b2b7d8 873 default:
dkato 0:702bf7b2b7d8 874 error_code = EFAULT;
dkato 0:702bf7b2b7d8 875 break;
dkato 0:702bf7b2b7d8 876 }
dkato 0:702bf7b2b7d8 877 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 878 }
dkato 0:702bf7b2b7d8 879 /* semaphore release */
dkato 0:702bf7b2b7d8 880 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 881 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 882 {
dkato 0:702bf7b2b7d8 883 sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
dkato 0:702bf7b2b7d8 884 /* semaphore error check */
dkato 0:702bf7b2b7d8 885 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 886 {
dkato 0:702bf7b2b7d8 887 /* set error return value */
dkato 0:702bf7b2b7d8 888 retval = EERROR;
dkato 0:702bf7b2b7d8 889 DMA_SetErrCode((int_t)sem_release_status, p_errno);
dkato 0:702bf7b2b7d8 890 }
dkato 0:702bf7b2b7d8 891 }
dkato 0:702bf7b2b7d8 892 }
dkato 0:702bf7b2b7d8 893 }
dkato 0:702bf7b2b7d8 894 }
dkato 0:702bf7b2b7d8 895 else
dkato 0:702bf7b2b7d8 896 {
dkato 0:702bf7b2b7d8 897 /* set error return value */
dkato 0:702bf7b2b7d8 898 retval = EERROR;
dkato 0:702bf7b2b7d8 899 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 900 }
dkato 0:702bf7b2b7d8 901 }
dkato 0:702bf7b2b7d8 902 else
dkato 0:702bf7b2b7d8 903 {
dkato 0:702bf7b2b7d8 904 /* set error return value */
dkato 0:702bf7b2b7d8 905 retval = EERROR;
dkato 0:702bf7b2b7d8 906 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 907 }
dkato 0:702bf7b2b7d8 908
dkato 0:702bf7b2b7d8 909 return retval;
dkato 0:702bf7b2b7d8 910
dkato 0:702bf7b2b7d8 911 }
dkato 0:702bf7b2b7d8 912
dkato 0:702bf7b2b7d8 913 /******************************************************************************
dkato 0:702bf7b2b7d8 914 End of function R_DMA_SetParam
dkato 0:702bf7b2b7d8 915 ******************************************************************************/
dkato 0:702bf7b2b7d8 916
dkato 0:702bf7b2b7d8 917 /******************************************************************************
dkato 0:702bf7b2b7d8 918 * Function Name: R_DMA_Start
dkato 0:702bf7b2b7d8 919 * Description : Start DMA transfer.
dkato 0:702bf7b2b7d8 920 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 921 * Arguments : channel -
dkato 0:702bf7b2b7d8 922 * DMA start channel number.
dkato 0:702bf7b2b7d8 923 * *p_dma_data -
dkato 0:702bf7b2b7d8 924 * DMA address parameters.
dkato 0:702bf7b2b7d8 925 * *p_errno -
dkato 0:702bf7b2b7d8 926 * Pointer of error code.
dkato 0:702bf7b2b7d8 927 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 928 * error code -
dkato 0:702bf7b2b7d8 929 * OS error num : Semaphore release failed.
dkato 0:702bf7b2b7d8 930 * EBADF : Channel status is DMA_CH_INIT.
dkato 0:702bf7b2b7d8 931 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 932 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 933 * EBUSY : It has been start DMA transfer in channel.
dkato 0:702bf7b2b7d8 934 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 935 * EPERM : The value in p_ch_setup isn't in the right range.
dkato 0:702bf7b2b7d8 936 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 937 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 938 * p_dma_data is NULL.
dkato 0:702bf7b2b7d8 939 * Wait semaphore release.
dkato 0:702bf7b2b7d8 940 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 941 * Operation successful.
dkato 0:702bf7b2b7d8 942 * EERROR -
dkato 0:702bf7b2b7d8 943 * Error occured.
dkato 0:702bf7b2b7d8 944 ******************************************************************************/
dkato 0:702bf7b2b7d8 945
dkato 0:702bf7b2b7d8 946 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 947 int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 948 int32_t * const p_errno)
dkato 0:702bf7b2b7d8 949 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 950 {
dkato 0:702bf7b2b7d8 951 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 952 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 953 int_t sem_wait_status;
dkato 0:702bf7b2b7d8 954 osStatus sem_release_status;
dkato 0:702bf7b2b7d8 955 int_t error_code;
dkato 0:702bf7b2b7d8 956
dkato 0:702bf7b2b7d8 957 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 958
dkato 0:702bf7b2b7d8 959 /* check channel of argument */
dkato 0:702bf7b2b7d8 960 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 961 {
dkato 0:702bf7b2b7d8 962 if (NULL != p_dma_data)
dkato 0:702bf7b2b7d8 963 {
dkato 0:702bf7b2b7d8 964 /* check address parameter */
dkato 0:702bf7b2b7d8 965 /* check DMA transfer count destination address is 0 */
dkato 0:702bf7b2b7d8 966 if (0U == p_dma_data->count)
dkato 0:702bf7b2b7d8 967 {
dkato 0:702bf7b2b7d8 968 /* set error return value */
dkato 0:702bf7b2b7d8 969 retval = EERROR;
dkato 0:702bf7b2b7d8 970 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 971 }
dkato 0:702bf7b2b7d8 972
dkato 0:702bf7b2b7d8 973 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 974 {
dkato 0:702bf7b2b7d8 975 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 976 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 977 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 978 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 979 {
dkato 0:702bf7b2b7d8 980 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 981 sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
dkato 0:702bf7b2b7d8 982 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 983 /* semaphore error check */
dkato 0:702bf7b2b7d8 984 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 985 {
dkato 0:702bf7b2b7d8 986 /* set error return value */
dkato 0:702bf7b2b7d8 987 retval = EERROR;
dkato 0:702bf7b2b7d8 988 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 989 }
dkato 0:702bf7b2b7d8 990 }
dkato 0:702bf7b2b7d8 991
dkato 0:702bf7b2b7d8 992 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 993 {
dkato 0:702bf7b2b7d8 994 if (DMA_CH_OPEN == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 995 {
dkato 0:702bf7b2b7d8 996 /* set bus paramter for DMA */
dkato 0:702bf7b2b7d8 997 DMA_BusParam(channel, p_dma_data);
dkato 0:702bf7b2b7d8 998 /* set up address parameter */
dkato 0:702bf7b2b7d8 999 /* Next register set is 0 */
dkato 0:702bf7b2b7d8 1000 DMA_SetData(channel, p_dma_data, 0);
dkato 0:702bf7b2b7d8 1001 /* DMA transfer start */
dkato 0:702bf7b2b7d8 1002 DMA_Start(channel, false);
dkato 0:702bf7b2b7d8 1003 }
dkato 0:702bf7b2b7d8 1004 else
dkato 0:702bf7b2b7d8 1005 {
dkato 0:702bf7b2b7d8 1006 /* set error return value */
dkato 0:702bf7b2b7d8 1007 retval = EERROR;
dkato 0:702bf7b2b7d8 1008 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1009 {
dkato 0:702bf7b2b7d8 1010 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 1011 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 1012 break;
dkato 0:702bf7b2b7d8 1013
dkato 0:702bf7b2b7d8 1014 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 1015 error_code = EBADF;
dkato 0:702bf7b2b7d8 1016 break;
dkato 0:702bf7b2b7d8 1017
dkato 0:702bf7b2b7d8 1018 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 1019 error_code = EBUSY;
dkato 0:702bf7b2b7d8 1020 break;
dkato 0:702bf7b2b7d8 1021
dkato 0:702bf7b2b7d8 1022 default:
dkato 0:702bf7b2b7d8 1023 error_code = EFAULT;
dkato 0:702bf7b2b7d8 1024 break;
dkato 0:702bf7b2b7d8 1025 }
dkato 0:702bf7b2b7d8 1026 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 1027 }
dkato 0:702bf7b2b7d8 1028 /* semaphore release */
dkato 0:702bf7b2b7d8 1029 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 1030 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 1031 {
dkato 0:702bf7b2b7d8 1032 sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
dkato 0:702bf7b2b7d8 1033 /* semaphore error check */
dkato 0:702bf7b2b7d8 1034 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 1035 {
dkato 0:702bf7b2b7d8 1036 /* set error return value */
dkato 0:702bf7b2b7d8 1037 retval = EERROR;
dkato 0:702bf7b2b7d8 1038 DMA_SetErrCode((int_t)sem_release_status, p_errno);
dkato 0:702bf7b2b7d8 1039 }
dkato 0:702bf7b2b7d8 1040 }
dkato 0:702bf7b2b7d8 1041 }
dkato 0:702bf7b2b7d8 1042 }
dkato 0:702bf7b2b7d8 1043 }
dkato 0:702bf7b2b7d8 1044 else
dkato 0:702bf7b2b7d8 1045 {
dkato 0:702bf7b2b7d8 1046 /* set error return value */
dkato 0:702bf7b2b7d8 1047 retval = EERROR;
dkato 0:702bf7b2b7d8 1048 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 1049 }
dkato 0:702bf7b2b7d8 1050 }
dkato 0:702bf7b2b7d8 1051 else
dkato 0:702bf7b2b7d8 1052 {
dkato 0:702bf7b2b7d8 1053 /* set error return value */
dkato 0:702bf7b2b7d8 1054 retval = EERROR;
dkato 0:702bf7b2b7d8 1055 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 1056 }
dkato 0:702bf7b2b7d8 1057
dkato 0:702bf7b2b7d8 1058 return retval;
dkato 0:702bf7b2b7d8 1059
dkato 0:702bf7b2b7d8 1060 }
dkato 0:702bf7b2b7d8 1061
dkato 0:702bf7b2b7d8 1062 /******************************************************************************
dkato 0:702bf7b2b7d8 1063 End of function R_DMA_Start
dkato 0:702bf7b2b7d8 1064 ******************************************************************************/
dkato 0:702bf7b2b7d8 1065
dkato 0:702bf7b2b7d8 1066 /******************************************************************************
dkato 0:702bf7b2b7d8 1067 * Function Name: R_DMA_NextData
dkato 0:702bf7b2b7d8 1068 * Description : Set continous DMA mode.
dkato 0:702bf7b2b7d8 1069 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 1070 * Arguments : channel -
dkato 0:702bf7b2b7d8 1071 * Continuous DMA channel number.
dkato 0:702bf7b2b7d8 1072 * *p_dma_data -
dkato 0:702bf7b2b7d8 1073 * DMA address parameters.
dkato 0:702bf7b2b7d8 1074 * *p_errno -
dkato 0:702bf7b2b7d8 1075 * Pointer of error code.
dkato 0:702bf7b2b7d8 1076 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 1077 * error code -
dkato 0:702bf7b2b7d8 1078 * OS error num : Semaphore release failed.
dkato 0:702bf7b2b7d8 1079 * EBADF : Channel status is DMA_CH_INIT.
dkato 0:702bf7b2b7d8 1080 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 1081 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 1082 * EBUSY : It has been set continous DMA transfer.
dkato 0:702bf7b2b7d8 1083 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 1084 * EPERM : The value in p_ch_setup isn't in the right range.
dkato 0:702bf7b2b7d8 1085 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 1086 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 1087 * p_dma_data is NULL.
dkato 0:702bf7b2b7d8 1088 * Wait semaphore failed.
dkato 0:702bf7b2b7d8 1089 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 1090 * Operation successful.
dkato 0:702bf7b2b7d8 1091 * EERROR -
dkato 0:702bf7b2b7d8 1092 * Error occured.
dkato 0:702bf7b2b7d8 1093 ******************************************************************************/
dkato 0:702bf7b2b7d8 1094
dkato 0:702bf7b2b7d8 1095 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 1096 int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 1097 int32_t * const p_errno)
dkato 0:702bf7b2b7d8 1098 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 1099 {
dkato 0:702bf7b2b7d8 1100 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 1101 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 1102 int_t sem_wait_status;
dkato 0:702bf7b2b7d8 1103 osStatus sem_release_status;
dkato 0:702bf7b2b7d8 1104 int_t error_code;
dkato 0:702bf7b2b7d8 1105
dkato 0:702bf7b2b7d8 1106 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 1107
dkato 0:702bf7b2b7d8 1108 /* check channel of argument */
dkato 0:702bf7b2b7d8 1109 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 1110 {
dkato 0:702bf7b2b7d8 1111 if (NULL != p_dma_data)
dkato 0:702bf7b2b7d8 1112 {
dkato 0:702bf7b2b7d8 1113 /* check address parameter */
dkato 0:702bf7b2b7d8 1114 /* check DMA transfer count destination address is 0 */
dkato 0:702bf7b2b7d8 1115 if (0U == p_dma_data->count)
dkato 0:702bf7b2b7d8 1116 {
dkato 0:702bf7b2b7d8 1117 /* set error return value */
dkato 0:702bf7b2b7d8 1118 retval = EERROR;
dkato 0:702bf7b2b7d8 1119 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 1120 }
dkato 0:702bf7b2b7d8 1121
dkato 0:702bf7b2b7d8 1122 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 1123 {
dkato 0:702bf7b2b7d8 1124 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 1125 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 1126 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 1127 {
dkato 0:702bf7b2b7d8 1128 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 1129 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 1130 sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
dkato 0:702bf7b2b7d8 1131 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 1132 /* semaphore error check */
dkato 0:702bf7b2b7d8 1133 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 1134 {
dkato 0:702bf7b2b7d8 1135 /* set error return value */
dkato 0:702bf7b2b7d8 1136 retval = EERROR;
dkato 0:702bf7b2b7d8 1137 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 1138 }
dkato 0:702bf7b2b7d8 1139 }
dkato 0:702bf7b2b7d8 1140
dkato 0:702bf7b2b7d8 1141 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 1142 {
dkato 0:702bf7b2b7d8 1143 if ((DMA_CH_OPEN == dma_info_ch->ch_stat) ||
dkato 0:702bf7b2b7d8 1144 (DMA_CH_TRANSFER == dma_info_ch->ch_stat))
dkato 0:702bf7b2b7d8 1145 {
dkato 0:702bf7b2b7d8 1146 if (false == dma_info_ch->next_dma_flag)
dkato 0:702bf7b2b7d8 1147 {
dkato 0:702bf7b2b7d8 1148 /* set up address parameter for continous DMA*/
dkato 0:702bf7b2b7d8 1149 DMA_SetNextData(channel, p_dma_data);
dkato 0:702bf7b2b7d8 1150 }
dkato 0:702bf7b2b7d8 1151 else
dkato 0:702bf7b2b7d8 1152 {
dkato 0:702bf7b2b7d8 1153 /* set error return value */
dkato 0:702bf7b2b7d8 1154 retval = EERROR;
dkato 0:702bf7b2b7d8 1155 DMA_SetErrCode(EBUSY, p_errno);
dkato 0:702bf7b2b7d8 1156 }
dkato 0:702bf7b2b7d8 1157 }
dkato 0:702bf7b2b7d8 1158 else
dkato 0:702bf7b2b7d8 1159 {
dkato 0:702bf7b2b7d8 1160 /* set error return value */
dkato 0:702bf7b2b7d8 1161 retval = EERROR;
dkato 0:702bf7b2b7d8 1162 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1163 {
dkato 0:702bf7b2b7d8 1164 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 1165 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 1166 break;
dkato 0:702bf7b2b7d8 1167
dkato 0:702bf7b2b7d8 1168 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 1169 error_code = EBADF;
dkato 0:702bf7b2b7d8 1170 break;
dkato 0:702bf7b2b7d8 1171
dkato 0:702bf7b2b7d8 1172 default:
dkato 0:702bf7b2b7d8 1173 error_code = EFAULT;
dkato 0:702bf7b2b7d8 1174 break;
dkato 0:702bf7b2b7d8 1175 }
dkato 0:702bf7b2b7d8 1176 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 1177 }
dkato 0:702bf7b2b7d8 1178
dkato 0:702bf7b2b7d8 1179 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 1180 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 1181 {
dkato 0:702bf7b2b7d8 1182 /* semaphore release */
dkato 0:702bf7b2b7d8 1183 sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
dkato 0:702bf7b2b7d8 1184 /* semaphore error check */
dkato 0:702bf7b2b7d8 1185 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 1186 {
dkato 0:702bf7b2b7d8 1187 /* set error return value */
dkato 0:702bf7b2b7d8 1188 retval = EERROR;
dkato 0:702bf7b2b7d8 1189 DMA_SetErrCode((int_t)sem_release_status, p_errno);
dkato 0:702bf7b2b7d8 1190 }
dkato 0:702bf7b2b7d8 1191 }
dkato 0:702bf7b2b7d8 1192 }
dkato 0:702bf7b2b7d8 1193 }
dkato 0:702bf7b2b7d8 1194 }
dkato 0:702bf7b2b7d8 1195 else
dkato 0:702bf7b2b7d8 1196 {
dkato 0:702bf7b2b7d8 1197 /* set error return value */
dkato 0:702bf7b2b7d8 1198 retval = EERROR;
dkato 0:702bf7b2b7d8 1199 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 1200 }
dkato 0:702bf7b2b7d8 1201 }
dkato 0:702bf7b2b7d8 1202 else
dkato 0:702bf7b2b7d8 1203 {
dkato 0:702bf7b2b7d8 1204 /* set error return value */
dkato 0:702bf7b2b7d8 1205 retval = EERROR;
dkato 0:702bf7b2b7d8 1206 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 1207 }
dkato 0:702bf7b2b7d8 1208
dkato 0:702bf7b2b7d8 1209 return retval;
dkato 0:702bf7b2b7d8 1210
dkato 0:702bf7b2b7d8 1211 }
dkato 0:702bf7b2b7d8 1212
dkato 0:702bf7b2b7d8 1213 /******************************************************************************
dkato 0:702bf7b2b7d8 1214 End of function R_DMA_NextData
dkato 0:702bf7b2b7d8 1215 ******************************************************************************/
dkato 0:702bf7b2b7d8 1216
dkato 0:702bf7b2b7d8 1217 /******************************************************************************
dkato 0:702bf7b2b7d8 1218 * Function Name: R_DMA_Cancel
dkato 0:702bf7b2b7d8 1219 * Description : Cancel DMA transfer.
dkato 0:702bf7b2b7d8 1220 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 1221 * Arguments : channel -
dkato 0:702bf7b2b7d8 1222 * Cancel DMA channel number.
dkato 0:702bf7b2b7d8 1223 * *p_remain -
dkato 0:702bf7b2b7d8 1224 * Remain data size of DMA transfer when it stopping.
dkato 0:702bf7b2b7d8 1225 * *p_errno -
dkato 0:702bf7b2b7d8 1226 * Pointer of error code.
dkato 0:702bf7b2b7d8 1227 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 1228 * error code -
dkato 0:702bf7b2b7d8 1229 * OS error num : Semaphore release failed.
dkato 0:702bf7b2b7d8 1230 * EBADF : Channel status is DMA_CH_INIT or DMA_CH_OPEN.
dkato 0:702bf7b2b7d8 1231 * (DMA stopped)
dkato 0:702bf7b2b7d8 1232 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 1233 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 1234 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 1235 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 1236 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 1237 * p_remain is NULL.
dkato 0:702bf7b2b7d8 1238 * Wait semaphhore failed.
dkato 0:702bf7b2b7d8 1239 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 1240 * Operation successful.
dkato 0:702bf7b2b7d8 1241 * EERROR -
dkato 0:702bf7b2b7d8 1242 * Error occured.
dkato 0:702bf7b2b7d8 1243 ******************************************************************************/
dkato 0:702bf7b2b7d8 1244
dkato 0:702bf7b2b7d8 1245 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 1246 int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 1247 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 1248 {
dkato 0:702bf7b2b7d8 1249 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 1250 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 1251 int_t sem_wait_status;
dkato 0:702bf7b2b7d8 1252 osStatus sem_release_status;
dkato 0:702bf7b2b7d8 1253 int_t error_code;
dkato 0:702bf7b2b7d8 1254
dkato 0:702bf7b2b7d8 1255 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 1256
dkato 0:702bf7b2b7d8 1257 /* check channel of argument */
dkato 0:702bf7b2b7d8 1258 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 1259 {
dkato 0:702bf7b2b7d8 1260 /* check whether p_remain is NULL */
dkato 0:702bf7b2b7d8 1261 if (NULL != p_remain)
dkato 0:702bf7b2b7d8 1262 {
dkato 0:702bf7b2b7d8 1263 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 1264
dkato 0:702bf7b2b7d8 1265 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 1266 {
dkato 0:702bf7b2b7d8 1267 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 1268 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 1269 sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
dkato 0:702bf7b2b7d8 1270 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 1271 /* semaphore error check */
dkato 0:702bf7b2b7d8 1272 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 1273 {
dkato 0:702bf7b2b7d8 1274 /* set error return value */
dkato 0:702bf7b2b7d8 1275 retval = EERROR;
dkato 0:702bf7b2b7d8 1276 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 1277 }
dkato 0:702bf7b2b7d8 1278 }
dkato 0:702bf7b2b7d8 1279
dkato 0:702bf7b2b7d8 1280 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 1281 {
dkato 0:702bf7b2b7d8 1282 if (DMA_CH_TRANSFER == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1283 {
dkato 0:702bf7b2b7d8 1284 /* set up address parameter for continous DMA*/
dkato 0:702bf7b2b7d8 1285 DMA_Stop(channel, p_remain);
dkato 0:702bf7b2b7d8 1286 }
dkato 0:702bf7b2b7d8 1287 else
dkato 0:702bf7b2b7d8 1288 {
dkato 0:702bf7b2b7d8 1289 /* set error return value */
dkato 0:702bf7b2b7d8 1290 retval = EERROR;
dkato 0:702bf7b2b7d8 1291 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1292 {
dkato 0:702bf7b2b7d8 1293 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 1294 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 1295 break;
dkato 0:702bf7b2b7d8 1296
dkato 0:702bf7b2b7d8 1297 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 1298 error_code = EBADF;
dkato 0:702bf7b2b7d8 1299 break;
dkato 0:702bf7b2b7d8 1300
dkato 0:702bf7b2b7d8 1301 case DMA_CH_OPEN:
dkato 0:702bf7b2b7d8 1302 error_code = EBADF;
dkato 0:702bf7b2b7d8 1303 break;
dkato 0:702bf7b2b7d8 1304
dkato 0:702bf7b2b7d8 1305 default:
dkato 0:702bf7b2b7d8 1306 error_code = EFAULT;
dkato 0:702bf7b2b7d8 1307 break;
dkato 0:702bf7b2b7d8 1308 }
dkato 0:702bf7b2b7d8 1309 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 1310 }
dkato 0:702bf7b2b7d8 1311
dkato 0:702bf7b2b7d8 1312 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 1313 {
dkato 0:702bf7b2b7d8 1314 /* semaphore release */
dkato 0:702bf7b2b7d8 1315 sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
dkato 0:702bf7b2b7d8 1316 /* semaphore error check */
dkato 0:702bf7b2b7d8 1317 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 1318 {
dkato 0:702bf7b2b7d8 1319 /* set error return value */
dkato 0:702bf7b2b7d8 1320 retval = EERROR;
dkato 0:702bf7b2b7d8 1321 DMA_SetErrCode((int_t)sem_release_status, p_errno);
dkato 0:702bf7b2b7d8 1322 }
dkato 0:702bf7b2b7d8 1323 }
dkato 0:702bf7b2b7d8 1324 }
dkato 0:702bf7b2b7d8 1325 }
dkato 0:702bf7b2b7d8 1326 else
dkato 0:702bf7b2b7d8 1327 {
dkato 0:702bf7b2b7d8 1328 /* set error return value */
dkato 0:702bf7b2b7d8 1329 retval = EERROR;
dkato 0:702bf7b2b7d8 1330 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 1331 }
dkato 0:702bf7b2b7d8 1332 }
dkato 0:702bf7b2b7d8 1333 else
dkato 0:702bf7b2b7d8 1334 {
dkato 0:702bf7b2b7d8 1335 /* set error return value */
dkato 0:702bf7b2b7d8 1336 retval = EERROR;
dkato 0:702bf7b2b7d8 1337 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 1338 }
dkato 0:702bf7b2b7d8 1339
dkato 0:702bf7b2b7d8 1340 return retval;
dkato 0:702bf7b2b7d8 1341 }
dkato 0:702bf7b2b7d8 1342
dkato 0:702bf7b2b7d8 1343 /******************************************************************************
dkato 0:702bf7b2b7d8 1344 End of function R_DMA_Cancel
dkato 0:702bf7b2b7d8 1345 ******************************************************************************/
dkato 0:702bf7b2b7d8 1346