RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Tue Aug 18 04:00:49 2015 +0000
Revision:
5:1390bfcb667c
Parent:
0:702bf7b2b7d8
Child:
9:37222d6ece56
Update BSP V.203

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:702bf7b2b7d8 1 /*******************************************************************************
dkato 0:702bf7b2b7d8 2 * DISCLAIMER
dkato 0:702bf7b2b7d8 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:702bf7b2b7d8 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:702bf7b2b7d8 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:702bf7b2b7d8 6 * all applicable laws, including copyright laws.
dkato 0:702bf7b2b7d8 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:702bf7b2b7d8 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:702bf7b2b7d8 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:702bf7b2b7d8 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:702bf7b2b7d8 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:702bf7b2b7d8 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:702bf7b2b7d8 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:702bf7b2b7d8 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:702bf7b2b7d8 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:702bf7b2b7d8 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:702bf7b2b7d8 17 * and to discontinue the availability of this software. By using this software,
dkato 0:702bf7b2b7d8 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:702bf7b2b7d8 19 * following link:
dkato 0:702bf7b2b7d8 20 * http://www.renesas.com/disclaimer*
dkato 0:702bf7b2b7d8 21 * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
dkato 0:702bf7b2b7d8 22 *******************************************************************************/
dkato 0:702bf7b2b7d8 23
dkato 0:702bf7b2b7d8 24 /**************************************************************************//**
dkato 0:702bf7b2b7d8 25 * @file dma_if.c
dkato 5:1390bfcb667c 26 * $Rev: 1674 $
dkato 5:1390bfcb667c 27 * $Date:: 2015-05-29 16:35:57 +0900#$
dkato 0:702bf7b2b7d8 28 * @brief DMA Driver interface functions
dkato 0:702bf7b2b7d8 29 ******************************************************************************/
dkato 0:702bf7b2b7d8 30
dkato 0:702bf7b2b7d8 31 /*****************************************************************************
dkato 0:702bf7b2b7d8 32 * History : DD.MM.YYYY Version Description
dkato 0:702bf7b2b7d8 33 * : 15.01.2013 1.00 First Release
dkato 0:702bf7b2b7d8 34 ******************************************************************************/
dkato 0:702bf7b2b7d8 35
dkato 0:702bf7b2b7d8 36 /*******************************************************************************
dkato 0:702bf7b2b7d8 37 Includes <System Includes>, "Project Includes"
dkato 0:702bf7b2b7d8 38 *******************************************************************************/
dkato 0:702bf7b2b7d8 39
dkato 0:702bf7b2b7d8 40 #include "dma.h"
dkato 0:702bf7b2b7d8 41
dkato 0:702bf7b2b7d8 42 /******************************************************************************
dkato 0:702bf7b2b7d8 43 Private global tables
dkato 0:702bf7b2b7d8 44 ******************************************************************************/
dkato 0:702bf7b2b7d8 45
dkato 0:702bf7b2b7d8 46 /******************************************************************************
dkato 0:702bf7b2b7d8 47 * Function Name: R_DMA_Init
dkato 0:702bf7b2b7d8 48 * Description : Init DMA driver.
dkato 5:1390bfcb667c 49 * Check parameter in this function.
dkato 0:702bf7b2b7d8 50 * Arguments : *p_dma_init_param -
dkato 0:702bf7b2b7d8 51 * Point of driver init parameter.
dkato 0:702bf7b2b7d8 52 * *p_errno-
dkato 0:702bf7b2b7d8 53 * Pointer of error code.
dkato 0:702bf7b2b7d8 54 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 55 * error code -
dkato 0:702bf7b2b7d8 56 * OS error num : Registering handler failed.
dkato 0:702bf7b2b7d8 57 * EPERM : Pointer of callback function which called in DMA
dkato 0:702bf7b2b7d8 58 * error interrupt handler is NULL.
dkato 0:702bf7b2b7d8 59 * EFAULT : dma_init_param is NULL.
dkato 0:702bf7b2b7d8 60 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 61 * Operation successful.
dkato 0:702bf7b2b7d8 62 * EERROR -
dkato 0:702bf7b2b7d8 63 * Error occured.
dkato 0:702bf7b2b7d8 64 ******************************************************************************/
dkato 0:702bf7b2b7d8 65
dkato 0:702bf7b2b7d8 66 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 67 int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 68 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 69 {
dkato 0:702bf7b2b7d8 70 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 71 int_t result_init;
dkato 5:1390bfcb667c 72 int_t was_masked;
dkato 0:702bf7b2b7d8 73
dkato 0:702bf7b2b7d8 74 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 75
dkato 0:702bf7b2b7d8 76 if (NULL == p_dma_init_param)
dkato 0:702bf7b2b7d8 77 {
dkato 0:702bf7b2b7d8 78 /* set error return value */
dkato 0:702bf7b2b7d8 79 retval = (EERROR);
dkato 0:702bf7b2b7d8 80 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 81 }
dkato 0:702bf7b2b7d8 82
dkato 0:702bf7b2b7d8 83 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 84 {
dkato 0:702bf7b2b7d8 85 /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
dkato 0:702bf7b2b7d8 86 if (NULL == p_dma_init_param->p_aio)
dkato 0:702bf7b2b7d8 87 /* <-MISRA 1.2 */
dkato 0:702bf7b2b7d8 88 {
dkato 0:702bf7b2b7d8 89 /* set error return value */
dkato 0:702bf7b2b7d8 90 retval = (EERROR);
dkato 0:702bf7b2b7d8 91 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 92 }
dkato 0:702bf7b2b7d8 93 }
dkato 0:702bf7b2b7d8 94
dkato 5:1390bfcb667c 95 /* disable all irq */
dkato 5:1390bfcb667c 96 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 97 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 98 #else
dkato 5:1390bfcb667c 99 was_masked = __disable_irq();
dkato 5:1390bfcb667c 100 #endif
dkato 5:1390bfcb667c 101
dkato 0:702bf7b2b7d8 102 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 103 {
dkato 5:1390bfcb667c 104 result_init = DMA_Initialize(p_dma_init_param);
dkato 0:702bf7b2b7d8 105 if (ESUCCESS != result_init)
dkato 0:702bf7b2b7d8 106 {
dkato 0:702bf7b2b7d8 107 /* set error return value */
dkato 0:702bf7b2b7d8 108 retval = (EERROR);
dkato 0:702bf7b2b7d8 109 DMA_SetErrCode(result_init, p_errno);
dkato 0:702bf7b2b7d8 110 }
dkato 0:702bf7b2b7d8 111 }
dkato 0:702bf7b2b7d8 112
dkato 5:1390bfcb667c 113 if (0 == was_masked)
dkato 5:1390bfcb667c 114 {
dkato 5:1390bfcb667c 115 __enable_irq();
dkato 5:1390bfcb667c 116 }
dkato 5:1390bfcb667c 117
dkato 0:702bf7b2b7d8 118 return retval;
dkato 0:702bf7b2b7d8 119 }
dkato 0:702bf7b2b7d8 120
dkato 0:702bf7b2b7d8 121 /******************************************************************************
dkato 0:702bf7b2b7d8 122 End of function R_DMA_Init
dkato 0:702bf7b2b7d8 123 ******************************************************************************/
dkato 0:702bf7b2b7d8 124
dkato 0:702bf7b2b7d8 125 /******************************************************************************
dkato 0:702bf7b2b7d8 126 * Function Name: R_DMA_UnInit
dkato 0:702bf7b2b7d8 127 * Description : UnInit DMA driver.
dkato 5:1390bfcb667c 128 * Check parameter in this function.
dkato 0:702bf7b2b7d8 129 * Arguments : *p_errno-
dkato 0:702bf7b2b7d8 130 * Pointer of error code.
dkato 0:702bf7b2b7d8 131 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 132 * error code -
dkato 0:702bf7b2b7d8 133 * OS error num : Unegistering handler failed.
dkato 0:702bf7b2b7d8 134 * EACCES : Driver status isn't DMA_DRV_INIT.
dkato 0:702bf7b2b7d8 135 * EBUSY : It has been allocated already in channel.
dkato 5:1390bfcb667c 136 * EFAULT : Channel status is besides the status definded
dkato 5:1390bfcb667c 137 * in dma_stat_ch_t.
dkato 0:702bf7b2b7d8 138 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 139 * Operation successful.
dkato 0:702bf7b2b7d8 140 * EERROR -
dkato 0:702bf7b2b7d8 141 * Error occured.
dkato 0:702bf7b2b7d8 142 ******************************************************************************/
dkato 0:702bf7b2b7d8 143
dkato 0:702bf7b2b7d8 144 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 145 int_t R_DMA_UnInit(int32_t * const p_errno)
dkato 0:702bf7b2b7d8 146 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 147 {
dkato 0:702bf7b2b7d8 148 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 149 int_t result_uninit;
dkato 0:702bf7b2b7d8 150 dma_info_drv_t *dma_info_drv;
dkato 0:702bf7b2b7d8 151 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 152 int_t ch_count;
dkato 0:702bf7b2b7d8 153 bool_t ch_stat_check_flag;
dkato 5:1390bfcb667c 154 int_t was_masked;
dkato 0:702bf7b2b7d8 155
dkato 0:702bf7b2b7d8 156 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 157
dkato 0:702bf7b2b7d8 158 dma_info_drv = DMA_GetDrvInstance();
dkato 0:702bf7b2b7d8 159
dkato 5:1390bfcb667c 160 /* disable all irq */
dkato 5:1390bfcb667c 161 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 162 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 163 #else
dkato 5:1390bfcb667c 164 was_masked = __disable_irq();
dkato 5:1390bfcb667c 165 #endif
dkato 5:1390bfcb667c 166
dkato 0:702bf7b2b7d8 167 /* check driver status */
dkato 0:702bf7b2b7d8 168 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 169 {
dkato 0:702bf7b2b7d8 170 if (DMA_DRV_INIT != dma_info_drv->drv_stat)
dkato 0:702bf7b2b7d8 171 {
dkato 0:702bf7b2b7d8 172 /* set error return value */
dkato 0:702bf7b2b7d8 173 retval = EERROR;
dkato 0:702bf7b2b7d8 174 DMA_SetErrCode(EACCES, p_errno);
dkato 0:702bf7b2b7d8 175 }
dkato 0:702bf7b2b7d8 176 else
dkato 0:702bf7b2b7d8 177 {
dkato 0:702bf7b2b7d8 178 ch_stat_check_flag = false;
dkato 0:702bf7b2b7d8 179 ch_count = 0;
dkato 0:702bf7b2b7d8 180 while (false == ch_stat_check_flag)
dkato 0:702bf7b2b7d8 181 {
dkato 0:702bf7b2b7d8 182 /* check channel status */
dkato 0:702bf7b2b7d8 183 dma_info_ch = DMA_GetDrvChInfo(ch_count);
dkato 0:702bf7b2b7d8 184 if ((DMA_CH_UNINIT != dma_info_ch->ch_stat) &&
dkato 0:702bf7b2b7d8 185 (DMA_CH_INIT != dma_info_ch->ch_stat))
dkato 0:702bf7b2b7d8 186 {
dkato 0:702bf7b2b7d8 187 /* set error return value */
dkato 0:702bf7b2b7d8 188 retval = EERROR;
dkato 0:702bf7b2b7d8 189 /* check channel status is busy */
dkato 0:702bf7b2b7d8 190 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 191 {
dkato 0:702bf7b2b7d8 192 /* These 2 cases are intentionally combined. */
dkato 0:702bf7b2b7d8 193 case DMA_CH_OPEN:
dkato 0:702bf7b2b7d8 194 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 195 DMA_SetErrCode(EBUSY, p_errno);
dkato 0:702bf7b2b7d8 196 break;
dkato 0:702bf7b2b7d8 197
dkato 0:702bf7b2b7d8 198 default:
dkato 0:702bf7b2b7d8 199 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 200 break;
dkato 0:702bf7b2b7d8 201 }
dkato 0:702bf7b2b7d8 202 }
dkato 0:702bf7b2b7d8 203
dkato 0:702bf7b2b7d8 204 if ((DMA_CH_NUM - 1) == ch_count)
dkato 0:702bf7b2b7d8 205 {
dkato 0:702bf7b2b7d8 206 /* channel status check end */
dkato 0:702bf7b2b7d8 207 ch_stat_check_flag = true;
dkato 0:702bf7b2b7d8 208 }
dkato 0:702bf7b2b7d8 209 ch_count++;
dkato 0:702bf7b2b7d8 210 }
dkato 0:702bf7b2b7d8 211 }
dkato 0:702bf7b2b7d8 212 /* uninitialize DMA */
dkato 0:702bf7b2b7d8 213 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 214 {
dkato 0:702bf7b2b7d8 215 result_uninit = DMA_UnInitialize();
dkato 0:702bf7b2b7d8 216 if (ESUCCESS != result_uninit)
dkato 0:702bf7b2b7d8 217 {
dkato 0:702bf7b2b7d8 218 /* set error return value */
dkato 0:702bf7b2b7d8 219 retval = EERROR;
dkato 0:702bf7b2b7d8 220 DMA_SetErrCode(result_uninit, p_errno);
dkato 0:702bf7b2b7d8 221 }
dkato 0:702bf7b2b7d8 222 }
dkato 0:702bf7b2b7d8 223 }
dkato 0:702bf7b2b7d8 224
dkato 5:1390bfcb667c 225 if (0 == was_masked)
dkato 5:1390bfcb667c 226 {
dkato 5:1390bfcb667c 227 __enable_irq();
dkato 5:1390bfcb667c 228 }
dkato 5:1390bfcb667c 229
dkato 0:702bf7b2b7d8 230 return retval;
dkato 0:702bf7b2b7d8 231 }
dkato 0:702bf7b2b7d8 232
dkato 0:702bf7b2b7d8 233 /******************************************************************************
dkato 0:702bf7b2b7d8 234 End of function R_DMA_UnInit
dkato 0:702bf7b2b7d8 235 ******************************************************************************/
dkato 0:702bf7b2b7d8 236
dkato 0:702bf7b2b7d8 237 /******************************************************************************
dkato 0:702bf7b2b7d8 238 * Function Name: R_DMA_Alloc
dkato 0:702bf7b2b7d8 239 * Description : Open DMA channel.
dkato 0:702bf7b2b7d8 240 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 241 * Arguments : channel -
dkato 0:702bf7b2b7d8 242 * Open channel number.
dkato 0:702bf7b2b7d8 243 * If channel is (-1), it looking for free chanel and allocate.
dkato 0:702bf7b2b7d8 244 * *p_errno -
dkato 0:702bf7b2b7d8 245 * Pointer of error code.
dkato 0:702bf7b2b7d8 246 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 247 * error code -
dkato 0:702bf7b2b7d8 248 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 249 * DMA_ALLOC_CH(-1) <= ch < DMA_CH_NUM.
dkato 0:702bf7b2b7d8 250 * EACCES : Driver status isn't DMA_DRV_INIT.
dkato 0:702bf7b2b7d8 251 * EBUSY : It has been allocated already in channel.
dkato 0:702bf7b2b7d8 252 * EMFILE : When looking for a free channel, but a free channel
dkato 0:702bf7b2b7d8 253 * didn't exist.
dkato 0:702bf7b2b7d8 254 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 255 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 256 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 257 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 258 * Operation successful.
dkato 0:702bf7b2b7d8 259 * EERROR -
dkato 0:702bf7b2b7d8 260 * Error occured.
dkato 0:702bf7b2b7d8 261 ******************************************************************************/
dkato 0:702bf7b2b7d8 262
dkato 0:702bf7b2b7d8 263 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 264 int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 265 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 266 {
dkato 0:702bf7b2b7d8 267 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 268 int_t ercd = ESUCCESS;
dkato 0:702bf7b2b7d8 269 int_t get_ch_num;
dkato 0:702bf7b2b7d8 270 dma_info_drv_t *dma_info_drv;
dkato 5:1390bfcb667c 271 int_t was_masked;
dkato 0:702bf7b2b7d8 272
dkato 0:702bf7b2b7d8 273 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 274
dkato 0:702bf7b2b7d8 275 /* check driver status */
dkato 0:702bf7b2b7d8 276 dma_info_drv = DMA_GetDrvInstance();
dkato 0:702bf7b2b7d8 277
dkato 5:1390bfcb667c 278 /* disable all irq */
dkato 5:1390bfcb667c 279 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 280 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 281 #else
dkato 5:1390bfcb667c 282 was_masked = __disable_irq();
dkato 5:1390bfcb667c 283 #endif
dkato 5:1390bfcb667c 284
dkato 0:702bf7b2b7d8 285 if (ESUCCESS == ercd)
dkato 0:702bf7b2b7d8 286 {
dkato 0:702bf7b2b7d8 287 if (DMA_DRV_INIT != dma_info_drv->drv_stat)
dkato 0:702bf7b2b7d8 288 {
dkato 0:702bf7b2b7d8 289 /* set error return value */
dkato 0:702bf7b2b7d8 290 ercd = EACCES;
dkato 0:702bf7b2b7d8 291 }
dkato 0:702bf7b2b7d8 292 else
dkato 0:702bf7b2b7d8 293 {
dkato 0:702bf7b2b7d8 294 /* check channel of argment */
dkato 0:702bf7b2b7d8 295 if ((DMA_ALLOC_CH <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 296 {
dkato 0:702bf7b2b7d8 297 if (DMA_ALLOC_CH == channel)
dkato 0:702bf7b2b7d8 298 {
dkato 0:702bf7b2b7d8 299 get_ch_num = DMA_GetFreeChannel();
dkato 0:702bf7b2b7d8 300 }
dkato 0:702bf7b2b7d8 301 else
dkato 0:702bf7b2b7d8 302 {
dkato 0:702bf7b2b7d8 303 get_ch_num = DMA_GetFixedChannel(channel);
dkato 0:702bf7b2b7d8 304 }
dkato 0:702bf7b2b7d8 305
dkato 0:702bf7b2b7d8 306 /* check return number or error number */
dkato 0:702bf7b2b7d8 307 if ((DMA_ALLOC_CH < get_ch_num) && (get_ch_num < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 308 {
dkato 0:702bf7b2b7d8 309 /* set channel number to return value */
dkato 0:702bf7b2b7d8 310 retval = get_ch_num;
dkato 0:702bf7b2b7d8 311 }
dkato 0:702bf7b2b7d8 312 else
dkato 0:702bf7b2b7d8 313 {
dkato 0:702bf7b2b7d8 314 /* set error code to error value */
dkato 0:702bf7b2b7d8 315 ercd = get_ch_num;
dkato 0:702bf7b2b7d8 316 }
dkato 0:702bf7b2b7d8 317 }
dkato 0:702bf7b2b7d8 318 else
dkato 0:702bf7b2b7d8 319 {
dkato 0:702bf7b2b7d8 320 /* set error return value */
dkato 0:702bf7b2b7d8 321 ercd = EINVAL;
dkato 0:702bf7b2b7d8 322 }
dkato 0:702bf7b2b7d8 323 }
dkato 0:702bf7b2b7d8 324 }
dkato 0:702bf7b2b7d8 325
dkato 0:702bf7b2b7d8 326 /* occured error check */
dkato 0:702bf7b2b7d8 327 if (ESUCCESS != ercd)
dkato 0:702bf7b2b7d8 328 {
dkato 0:702bf7b2b7d8 329 retval = EERROR;
dkato 0:702bf7b2b7d8 330 DMA_SetErrCode(ercd, p_errno);
dkato 0:702bf7b2b7d8 331 }
dkato 0:702bf7b2b7d8 332
dkato 5:1390bfcb667c 333 if (0 == was_masked)
dkato 5:1390bfcb667c 334 {
dkato 5:1390bfcb667c 335 __enable_irq();
dkato 5:1390bfcb667c 336 }
dkato 5:1390bfcb667c 337
dkato 0:702bf7b2b7d8 338 return retval;
dkato 0:702bf7b2b7d8 339 }
dkato 0:702bf7b2b7d8 340
dkato 0:702bf7b2b7d8 341 /******************************************************************************
dkato 0:702bf7b2b7d8 342 End of function R_DMA_Alloc
dkato 0:702bf7b2b7d8 343 ******************************************************************************/
dkato 0:702bf7b2b7d8 344
dkato 0:702bf7b2b7d8 345 /******************************************************************************
dkato 0:702bf7b2b7d8 346 * Function Name: R_DMA_Free
dkato 0:702bf7b2b7d8 347 * Description : Close DMA channel.
dkato 0:702bf7b2b7d8 348 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 349 * Arguments : channel -
dkato 0:702bf7b2b7d8 350 * Close channel number.
dkato 0:702bf7b2b7d8 351 * *p_errno -
dkato 0:702bf7b2b7d8 352 * Pointer of error code.
dkato 0:702bf7b2b7d8 353 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 354 * error code -
dkato 0:702bf7b2b7d8 355 * EBADF : Channel status is DMA_CH_INIT.
dkato 0:702bf7b2b7d8 356 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 357 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 358 * EACCES : Driver status isn't DMA_DRV_INIT.
dkato 0:702bf7b2b7d8 359 * EBUSY : It has been start DMA transfer in channel.
dkato 0:702bf7b2b7d8 360 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 361 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 362 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 363 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 364 * Operation successful.
dkato 0:702bf7b2b7d8 365 * EERROR -
dkato 0:702bf7b2b7d8 366 * Error occured.
dkato 0:702bf7b2b7d8 367 ******************************************************************************/
dkato 0:702bf7b2b7d8 368
dkato 0:702bf7b2b7d8 369 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 370 int_t R_DMA_Free(const int_t channel, int32_t *const p_errno)
dkato 0:702bf7b2b7d8 371 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 372 {
dkato 0:702bf7b2b7d8 373 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 374 dma_info_drv_t *dma_info_drv;
dkato 0:702bf7b2b7d8 375 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 376 int_t error_code;
dkato 5:1390bfcb667c 377 int_t was_masked;
dkato 0:702bf7b2b7d8 378
dkato 0:702bf7b2b7d8 379 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 380
dkato 5:1390bfcb667c 381 /* disable all irq */
dkato 5:1390bfcb667c 382 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 383 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 384 #else
dkato 5:1390bfcb667c 385 was_masked = __disable_irq();
dkato 5:1390bfcb667c 386 #endif
dkato 5:1390bfcb667c 387
dkato 0:702bf7b2b7d8 388 /* check channel of argument */
dkato 0:702bf7b2b7d8 389 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 390 {
dkato 0:702bf7b2b7d8 391 /* check driver status */
dkato 0:702bf7b2b7d8 392 dma_info_drv = DMA_GetDrvInstance();
dkato 0:702bf7b2b7d8 393
dkato 0:702bf7b2b7d8 394 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 395 {
dkato 0:702bf7b2b7d8 396 /* check driver status */
dkato 0:702bf7b2b7d8 397 if (DMA_DRV_INIT == dma_info_drv->drv_stat)
dkato 0:702bf7b2b7d8 398 {
dkato 0:702bf7b2b7d8 399 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 400
dkato 0:702bf7b2b7d8 401 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 402 {
dkato 0:702bf7b2b7d8 403 if (DMA_CH_OPEN == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 404 {
dkato 0:702bf7b2b7d8 405 DMA_CloseChannel(channel);
dkato 0:702bf7b2b7d8 406 }
dkato 0:702bf7b2b7d8 407 else
dkato 0:702bf7b2b7d8 408 {
dkato 0:702bf7b2b7d8 409 /* set error return value */
dkato 0:702bf7b2b7d8 410 retval = EERROR;
dkato 0:702bf7b2b7d8 411 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 412 {
dkato 0:702bf7b2b7d8 413 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 414 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 415 break;
dkato 0:702bf7b2b7d8 416
dkato 0:702bf7b2b7d8 417 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 418 error_code = EBADF;
dkato 0:702bf7b2b7d8 419 break;
dkato 0:702bf7b2b7d8 420
dkato 0:702bf7b2b7d8 421 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 422 error_code = EBUSY;
dkato 0:702bf7b2b7d8 423 break;
dkato 0:702bf7b2b7d8 424
dkato 0:702bf7b2b7d8 425 default:
dkato 0:702bf7b2b7d8 426 error_code = EFAULT;
dkato 0:702bf7b2b7d8 427 break;
dkato 0:702bf7b2b7d8 428 }
dkato 0:702bf7b2b7d8 429 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 430 }
dkato 0:702bf7b2b7d8 431 }
dkato 0:702bf7b2b7d8 432 }
dkato 0:702bf7b2b7d8 433 else
dkato 0:702bf7b2b7d8 434 {
dkato 0:702bf7b2b7d8 435 /* set error return value */
dkato 0:702bf7b2b7d8 436 retval = EERROR;
dkato 0:702bf7b2b7d8 437 DMA_SetErrCode(EACCES, p_errno);
dkato 0:702bf7b2b7d8 438
dkato 0:702bf7b2b7d8 439 }
dkato 0:702bf7b2b7d8 440 }
dkato 0:702bf7b2b7d8 441 }
dkato 0:702bf7b2b7d8 442 else
dkato 0:702bf7b2b7d8 443 {
dkato 0:702bf7b2b7d8 444 /* set error return value */
dkato 0:702bf7b2b7d8 445 retval = EERROR;
dkato 0:702bf7b2b7d8 446 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 447 }
dkato 0:702bf7b2b7d8 448
dkato 5:1390bfcb667c 449 if (0 == was_masked)
dkato 5:1390bfcb667c 450 {
dkato 5:1390bfcb667c 451 __enable_irq();
dkato 5:1390bfcb667c 452 }
dkato 5:1390bfcb667c 453
dkato 0:702bf7b2b7d8 454 return retval;
dkato 0:702bf7b2b7d8 455 }
dkato 0:702bf7b2b7d8 456
dkato 0:702bf7b2b7d8 457 /******************************************************************************
dkato 0:702bf7b2b7d8 458 End of function R_DMA_Free
dkato 0:702bf7b2b7d8 459 ******************************************************************************/
dkato 0:702bf7b2b7d8 460
dkato 0:702bf7b2b7d8 461 /******************************************************************************
dkato 0:702bf7b2b7d8 462 * Function Name: R_DMA_Setup
dkato 0:702bf7b2b7d8 463 * Description : Setup DMA transfer parameter.
dkato 0:702bf7b2b7d8 464 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 465 * Arguments : channel -
dkato 0:702bf7b2b7d8 466 * Setup channel number.
dkato 0:702bf7b2b7d8 467 * *p_ch_setup -
dkato 0:702bf7b2b7d8 468 * Set up parameters.
dkato 0:702bf7b2b7d8 469 * *p_errno -
dkato 0:702bf7b2b7d8 470 * Pointer of error code.
dkato 0:702bf7b2b7d8 471 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 472 * error code -
dkato 0:702bf7b2b7d8 473 * EBADF : Channel status is DMA_CH_INIT.
dkato 0:702bf7b2b7d8 474 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 475 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 476 * EBUSY : It has been start DMA transfer in channel.
dkato 0:702bf7b2b7d8 477 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 478 * EPERM : The value in p_ch_setup isn't in the right range.
dkato 0:702bf7b2b7d8 479 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 480 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 481 * p_ch_setup is NULL.
dkato 0:702bf7b2b7d8 482 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 483 * Operation successful.
dkato 0:702bf7b2b7d8 484 * EERROR -
dkato 0:702bf7b2b7d8 485 * Error occured.
dkato 0:702bf7b2b7d8 486 ******************************************************************************/
dkato 0:702bf7b2b7d8 487
dkato 0:702bf7b2b7d8 488 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 489 int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
dkato 0:702bf7b2b7d8 490 int32_t * const p_errno)
dkato 0:702bf7b2b7d8 491 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 492 {
dkato 0:702bf7b2b7d8 493 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 494 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 495 int_t error_code;
dkato 0:702bf7b2b7d8 496 uint32_t cfg_table_count;
dkato 0:702bf7b2b7d8 497 dma_ch_cfg_t ch_cfg_set_table;
dkato 0:702bf7b2b7d8 498 uint32_t set_reqd;
dkato 0:702bf7b2b7d8 499 bool_t check_table_flag;
dkato 5:1390bfcb667c 500 int_t was_masked;
dkato 0:702bf7b2b7d8 501
dkato 0:702bf7b2b7d8 502 /* Resouce Configure Set Table */
dkato 0:702bf7b2b7d8 503 static const dma_ch_cfg_t ch_cfg_table[DMA_CH_CONFIG_TABLE_NUM] =
dkato 0:702bf7b2b7d8 504 {
dkato 0:702bf7b2b7d8 505 {DMA_RS_OSTIM0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 506 {DMA_RS_OSTIM1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 507 {DMA_RS_TGI0A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 508 {DMA_RS_TGI1A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 509 {DMA_RS_TGI2A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 510 {DMA_RS_TGI3A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 511 {DMA_RS_TGI4A, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 512 {DMA_RS_TXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 513 {DMA_RS_RXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 514 {DMA_RS_TXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 515 {DMA_RS_RXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 516 {DMA_RS_TXI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 517 {DMA_RS_RXI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 518 {DMA_RS_TXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 519 {DMA_RS_RXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 520 {DMA_RS_TXI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 521 {DMA_RS_RXI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 522 {DMA_RS_TXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 523 {DMA_RS_RXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 524 {DMA_RS_TXI6, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 525 {DMA_RS_RXI6, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 526 {DMA_RS_TXI7, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 527 {DMA_RS_RXI7, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 528 {DMA_RS_USB0_DMA0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 529 {DMA_RS_USB0_DMA1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 530 {DMA_RS_USB1_DMA0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 531 {DMA_RS_USB1_DMA1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 532 {DMA_RS_ADEND, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 533 {DMA_RS_IEBBTD, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 534 {DMA_RS_IEBBTV, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 535 {DMA_RS_IREADY, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 536 {DMA_RS_FLDT, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 537 {DMA_RS_SDHI_0T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 538 {DMA_RS_SDHI_0R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 539 {DMA_RS_SDHI_1T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 540 {DMA_RS_SDHI_1R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 541 {DMA_RS_MMCT, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 542 {DMA_RS_MMCR, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 543 {DMA_RS_SSITXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 5:1390bfcb667c 544 {DMA_RS_SSIRXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 545 {DMA_RS_SSITXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 5:1390bfcb667c 546 {DMA_RS_SSIRXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 547 {DMA_RS_SSIRTI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 5:1390bfcb667c 548 {DMA_RS_SSITXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 5:1390bfcb667c 549 {DMA_RS_SSIRXI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 5:1390bfcb667c 550 {DMA_RS_SSIRTI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 5:1390bfcb667c 551 {DMA_RS_SSITXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 5:1390bfcb667c 552 {DMA_RS_SSIRXI5, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 553 {DMA_RS_SCUTXI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 554 {DMA_RS_SCURXI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 555 {DMA_RS_SCUTXI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 556 {DMA_RS_SCURXI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 557 {DMA_RS_SCUTXI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 558 {DMA_RS_SCURXI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 559 {DMA_RS_SCUTXI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 560 {DMA_RS_SCURXI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 561 {DMA_RS_SPTI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 562 {DMA_RS_SPRI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 563 {DMA_RS_SPTI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 564 {DMA_RS_SPRI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 565 {DMA_RS_SPTI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 566 {DMA_RS_SPRI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 567 {DMA_RS_SPTI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 568 {DMA_RS_SPRI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 569 {DMA_RS_SPTI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 570 {DMA_RS_SPRI4, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 571 {DMA_RS_SPDIFTXI, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 572 {DMA_RS_SPDIFRXI, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 573 {DMA_RS_CMI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 574 {DMA_RS_CMI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 575 {DMA_RS_MLBCI, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
dkato 0:702bf7b2b7d8 576 {DMA_RS_SGDEI0, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 577 {DMA_RS_SGDEI1, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 578 {DMA_RS_SGDEI2, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 579 {DMA_RS_SGDEI3, CHCFG_SET_AM_LEVEL, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 580 {DMA_RS_SCUTXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 581 {DMA_RS_SCURXI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 582 {DMA_RS_SCUTXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 583 {DMA_RS_SCURXI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 584 {DMA_RS_TI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 585 {DMA_RS_RI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 586 {DMA_RS_TI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 587 {DMA_RS_RI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 588 {DMA_RS_TI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 589 {DMA_RS_RI2, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 590 {DMA_RS_TI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 591 {DMA_RS_RI3, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 592 {DMA_RS_LIN0_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 593 {DMA_RS_LIN0_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 594 {DMA_RS_LIN1_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 595 {DMA_RS_LIN1_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 596 {DMA_RS_IFEI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 597 {DMA_RS_OFFI0, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC },
dkato 0:702bf7b2b7d8 598 {DMA_RS_IFEI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST },
dkato 0:702bf7b2b7d8 599 {DMA_RS_OFFI1, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC }
dkato 0:702bf7b2b7d8 600 };
dkato 0:702bf7b2b7d8 601
dkato 0:702bf7b2b7d8 602 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 603 /* dummy init set_reqd */
dkato 0:702bf7b2b7d8 604 set_reqd = CHCFG_REQD_UNDEFINED;
dkato 0:702bf7b2b7d8 605 ch_cfg_set_table = ch_cfg_table[0];
dkato 0:702bf7b2b7d8 606
dkato 0:702bf7b2b7d8 607 /* check channel of argument */
dkato 0:702bf7b2b7d8 608 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 609 {
dkato 0:702bf7b2b7d8 610 if (NULL != p_ch_setup)
dkato 0:702bf7b2b7d8 611 {
dkato 0:702bf7b2b7d8 612 /* check setup parameter */
dkato 0:702bf7b2b7d8 613 /* check AIOCB pointer */
dkato 0:702bf7b2b7d8 614 if (NULL == p_ch_setup->p_aio)
dkato 0:702bf7b2b7d8 615 {
dkato 0:702bf7b2b7d8 616 /* set error return value */
dkato 0:702bf7b2b7d8 617 retval = EERROR;
dkato 0:702bf7b2b7d8 618 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 619 }
dkato 0:702bf7b2b7d8 620
dkato 0:702bf7b2b7d8 621 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 622 {
dkato 0:702bf7b2b7d8 623 /* check DMA transfer unit size for destination */
dkato 0:702bf7b2b7d8 624 if (((int_t)p_ch_setup->dst_width <= DMA_UNIT_MIN) ||
dkato 0:702bf7b2b7d8 625 ((int_t)p_ch_setup->dst_width >= DMA_UNIT_MAX))
dkato 0:702bf7b2b7d8 626 {
dkato 0:702bf7b2b7d8 627 /* set error return value */
dkato 0:702bf7b2b7d8 628 retval = EERROR;
dkato 0:702bf7b2b7d8 629 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 630 }
dkato 0:702bf7b2b7d8 631 }
dkato 0:702bf7b2b7d8 632
dkato 0:702bf7b2b7d8 633 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 634 {
dkato 0:702bf7b2b7d8 635 /* check DMA transfer unit size for source */
dkato 0:702bf7b2b7d8 636 if (((int_t)p_ch_setup->src_width <= DMA_UNIT_MIN) ||
dkato 0:702bf7b2b7d8 637 ((int_t)p_ch_setup->src_width >= DMA_UNIT_MAX))
dkato 0:702bf7b2b7d8 638 {
dkato 0:702bf7b2b7d8 639 /* set error return value */
dkato 0:702bf7b2b7d8 640 retval = EERROR;
dkato 0:702bf7b2b7d8 641 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 642 }
dkato 0:702bf7b2b7d8 643 }
dkato 0:702bf7b2b7d8 644
dkato 0:702bf7b2b7d8 645 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 646 {
dkato 0:702bf7b2b7d8 647 /* check DMA address count direction for destination */
dkato 0:702bf7b2b7d8 648 if (((int_t)p_ch_setup->dst_cnt <= DMA_ADDR_MIN) ||
dkato 0:702bf7b2b7d8 649 ((int_t)p_ch_setup->dst_cnt >= DMA_ADDR_MAX))
dkato 0:702bf7b2b7d8 650 {
dkato 0:702bf7b2b7d8 651 /* set error return value */
dkato 0:702bf7b2b7d8 652 retval = EERROR;
dkato 0:702bf7b2b7d8 653 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 654 }
dkato 0:702bf7b2b7d8 655 }
dkato 0:702bf7b2b7d8 656
dkato 0:702bf7b2b7d8 657 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 658 {
dkato 0:702bf7b2b7d8 659 /* check DMA address count direction for source */
dkato 0:702bf7b2b7d8 660 if (((int_t)(p_ch_setup->src_cnt) <= DMA_ADDR_MIN) ||
dkato 0:702bf7b2b7d8 661 ((int_t)p_ch_setup->src_cnt >= DMA_ADDR_MAX))
dkato 0:702bf7b2b7d8 662 {
dkato 0:702bf7b2b7d8 663 /* set error return value */
dkato 0:702bf7b2b7d8 664 retval = EERROR;
dkato 0:702bf7b2b7d8 665 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 666 }
dkato 0:702bf7b2b7d8 667 }
dkato 0:702bf7b2b7d8 668
dkato 0:702bf7b2b7d8 669 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 670 {
dkato 0:702bf7b2b7d8 671 /* check DMA transfer direction */
dkato 0:702bf7b2b7d8 672 if (((int_t)p_ch_setup->direction <= DMA_REQ_MIN) ||
dkato 0:702bf7b2b7d8 673 ((int_t)p_ch_setup->direction >= DMA_REQ_MAX))
dkato 0:702bf7b2b7d8 674 {
dkato 0:702bf7b2b7d8 675 /* set error return value */
dkato 0:702bf7b2b7d8 676 retval = EERROR;
dkato 0:702bf7b2b7d8 677 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 678 }
dkato 0:702bf7b2b7d8 679 }
dkato 0:702bf7b2b7d8 680
dkato 0:702bf7b2b7d8 681 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 682 {
dkato 0:702bf7b2b7d8 683 /* check DMA transfer resouce */
dkato 0:702bf7b2b7d8 684 check_table_flag = false;
dkato 0:702bf7b2b7d8 685 cfg_table_count = 0;
dkato 0:702bf7b2b7d8 686 while (false == check_table_flag)
dkato 0:702bf7b2b7d8 687 {
dkato 0:702bf7b2b7d8 688 if (p_ch_setup->resource == ch_cfg_table[cfg_table_count].dmars)
dkato 0:702bf7b2b7d8 689 {
dkato 0:702bf7b2b7d8 690 /* check reqd is undefined */
dkato 0:702bf7b2b7d8 691 if (CHCFG_REQD_UNDEFINED == ch_cfg_table[cfg_table_count].reqd)
dkato 0:702bf7b2b7d8 692 {
dkato 0:702bf7b2b7d8 693 /* set reqd value on fixed value */
dkato 0:702bf7b2b7d8 694 if (DMA_REQ_SRC == p_ch_setup->direction)
dkato 0:702bf7b2b7d8 695 {
dkato 0:702bf7b2b7d8 696 set_reqd = CHCFG_SET_REQD_SRC;
dkato 0:702bf7b2b7d8 697 }
dkato 0:702bf7b2b7d8 698 else
dkato 0:702bf7b2b7d8 699 {
dkato 0:702bf7b2b7d8 700 set_reqd = CHCFG_SET_REQD_DST;
dkato 0:702bf7b2b7d8 701 }
dkato 0:702bf7b2b7d8 702 }
dkato 0:702bf7b2b7d8 703 else
dkato 0:702bf7b2b7d8 704 {
dkato 0:702bf7b2b7d8 705 /* set reqd value in channel config table */
dkato 0:702bf7b2b7d8 706 set_reqd = ch_cfg_table[cfg_table_count].reqd;
dkato 0:702bf7b2b7d8 707 }
dkato 0:702bf7b2b7d8 708 /* set channel config table address for DMA_SetParam() */
dkato 0:702bf7b2b7d8 709 ch_cfg_set_table = ch_cfg_table[cfg_table_count];
dkato 0:702bf7b2b7d8 710 check_table_flag = true;
dkato 0:702bf7b2b7d8 711 }
dkato 0:702bf7b2b7d8 712 if (false == check_table_flag)
dkato 0:702bf7b2b7d8 713 {
dkato 0:702bf7b2b7d8 714 /* resource value did not exist in channel config table */
dkato 0:702bf7b2b7d8 715 if ((uint32_t)((sizeof(ch_cfg_table)/sizeof(dma_ch_cfg_t)) - 1U) == cfg_table_count)
dkato 0:702bf7b2b7d8 716 {
dkato 0:702bf7b2b7d8 717 /* set error return value */
dkato 0:702bf7b2b7d8 718 retval = EERROR;
dkato 0:702bf7b2b7d8 719 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 720 check_table_flag = true;
dkato 0:702bf7b2b7d8 721 }
dkato 0:702bf7b2b7d8 722 cfg_table_count++;
dkato 0:702bf7b2b7d8 723 }
dkato 0:702bf7b2b7d8 724 }
dkato 0:702bf7b2b7d8 725 }
dkato 0:702bf7b2b7d8 726
dkato 5:1390bfcb667c 727 /* disable all irq */
dkato 5:1390bfcb667c 728 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 729 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 730 #else
dkato 5:1390bfcb667c 731 was_masked = __disable_irq();
dkato 5:1390bfcb667c 732 #endif
dkato 5:1390bfcb667c 733
dkato 0:702bf7b2b7d8 734 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 735 {
dkato 0:702bf7b2b7d8 736 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 737
dkato 0:702bf7b2b7d8 738 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 739 {
dkato 0:702bf7b2b7d8 740 if (DMA_CH_OPEN == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 741 {
dkato 0:702bf7b2b7d8 742 /* set up parameter */
dkato 0:702bf7b2b7d8 743 DMA_SetParam(channel, p_ch_setup, &ch_cfg_set_table, set_reqd);
dkato 0:702bf7b2b7d8 744 }
dkato 0:702bf7b2b7d8 745 else
dkato 0:702bf7b2b7d8 746 {
dkato 0:702bf7b2b7d8 747 /* set error return value */
dkato 0:702bf7b2b7d8 748 retval = EERROR;
dkato 0:702bf7b2b7d8 749 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 750 {
dkato 0:702bf7b2b7d8 751 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 752 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 753 break;
dkato 0:702bf7b2b7d8 754
dkato 0:702bf7b2b7d8 755 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 756 error_code = EBADF;
dkato 0:702bf7b2b7d8 757 break;
dkato 0:702bf7b2b7d8 758
dkato 0:702bf7b2b7d8 759 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 760 error_code = EBUSY;
dkato 0:702bf7b2b7d8 761 break;
dkato 0:702bf7b2b7d8 762
dkato 0:702bf7b2b7d8 763 default:
dkato 0:702bf7b2b7d8 764 error_code = EFAULT;
dkato 0:702bf7b2b7d8 765 break;
dkato 0:702bf7b2b7d8 766 }
dkato 0:702bf7b2b7d8 767 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 768 }
dkato 0:702bf7b2b7d8 769 }
dkato 0:702bf7b2b7d8 770 }
dkato 5:1390bfcb667c 771
dkato 5:1390bfcb667c 772 if (0 == was_masked)
dkato 5:1390bfcb667c 773 {
dkato 5:1390bfcb667c 774 __enable_irq();
dkato 5:1390bfcb667c 775 }
dkato 0:702bf7b2b7d8 776 }
dkato 0:702bf7b2b7d8 777 else
dkato 0:702bf7b2b7d8 778 {
dkato 0:702bf7b2b7d8 779 /* set error return value */
dkato 0:702bf7b2b7d8 780 retval = EERROR;
dkato 0:702bf7b2b7d8 781 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 782 }
dkato 0:702bf7b2b7d8 783 }
dkato 0:702bf7b2b7d8 784 else
dkato 0:702bf7b2b7d8 785 {
dkato 0:702bf7b2b7d8 786 /* set error return value */
dkato 0:702bf7b2b7d8 787 retval = EERROR;
dkato 0:702bf7b2b7d8 788 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 789 }
dkato 0:702bf7b2b7d8 790
dkato 0:702bf7b2b7d8 791 return retval;
dkato 0:702bf7b2b7d8 792 }
dkato 0:702bf7b2b7d8 793
dkato 0:702bf7b2b7d8 794 /******************************************************************************
dkato 0:702bf7b2b7d8 795 End of function R_DMA_SetParam
dkato 0:702bf7b2b7d8 796 ******************************************************************************/
dkato 0:702bf7b2b7d8 797
dkato 0:702bf7b2b7d8 798 /******************************************************************************
dkato 0:702bf7b2b7d8 799 * Function Name: R_DMA_Start
dkato 0:702bf7b2b7d8 800 * Description : Start DMA transfer.
dkato 0:702bf7b2b7d8 801 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 802 * Arguments : channel -
dkato 0:702bf7b2b7d8 803 * DMA start channel number.
dkato 0:702bf7b2b7d8 804 * *p_dma_data -
dkato 0:702bf7b2b7d8 805 * DMA address parameters.
dkato 0:702bf7b2b7d8 806 * *p_errno -
dkato 0:702bf7b2b7d8 807 * Pointer of error code.
dkato 0:702bf7b2b7d8 808 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 809 * error code -
dkato 0:702bf7b2b7d8 810 * EBADF : Channel status is DMA_CH_INIT.
dkato 0:702bf7b2b7d8 811 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 812 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 813 * EBUSY : It has been start DMA transfer in channel.
dkato 0:702bf7b2b7d8 814 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 815 * EPERM : The value in p_ch_setup isn't in the right range.
dkato 0:702bf7b2b7d8 816 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 817 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 818 * p_dma_data is NULL.
dkato 0:702bf7b2b7d8 819 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 820 * Operation successful.
dkato 0:702bf7b2b7d8 821 * EERROR -
dkato 0:702bf7b2b7d8 822 * Error occured.
dkato 0:702bf7b2b7d8 823 ******************************************************************************/
dkato 0:702bf7b2b7d8 824
dkato 0:702bf7b2b7d8 825 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 826 int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 827 int32_t * const p_errno)
dkato 0:702bf7b2b7d8 828 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 829 {
dkato 0:702bf7b2b7d8 830 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 831 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 832 int_t error_code;
dkato 5:1390bfcb667c 833 int_t was_masked;
dkato 0:702bf7b2b7d8 834
dkato 0:702bf7b2b7d8 835 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 836
dkato 5:1390bfcb667c 837 /* disable all irq */
dkato 5:1390bfcb667c 838 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 839 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 840 #else
dkato 5:1390bfcb667c 841 was_masked = __disable_irq();
dkato 5:1390bfcb667c 842 #endif
dkato 5:1390bfcb667c 843
dkato 0:702bf7b2b7d8 844 /* check channel of argument */
dkato 0:702bf7b2b7d8 845 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 846 {
dkato 0:702bf7b2b7d8 847 if (NULL != p_dma_data)
dkato 0:702bf7b2b7d8 848 {
dkato 0:702bf7b2b7d8 849 /* check address parameter */
dkato 0:702bf7b2b7d8 850 /* check DMA transfer count destination address is 0 */
dkato 0:702bf7b2b7d8 851 if (0U == p_dma_data->count)
dkato 0:702bf7b2b7d8 852 {
dkato 0:702bf7b2b7d8 853 /* set error return value */
dkato 0:702bf7b2b7d8 854 retval = EERROR;
dkato 0:702bf7b2b7d8 855 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 856 }
dkato 0:702bf7b2b7d8 857
dkato 0:702bf7b2b7d8 858 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 859 {
dkato 0:702bf7b2b7d8 860 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 861
dkato 0:702bf7b2b7d8 862 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 863 {
dkato 0:702bf7b2b7d8 864 if (DMA_CH_OPEN == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 865 {
dkato 0:702bf7b2b7d8 866 /* set bus paramter for DMA */
dkato 0:702bf7b2b7d8 867 DMA_BusParam(channel, p_dma_data);
dkato 0:702bf7b2b7d8 868 /* set up address parameter */
dkato 0:702bf7b2b7d8 869 /* Next register set is 0 */
dkato 0:702bf7b2b7d8 870 DMA_SetData(channel, p_dma_data, 0);
dkato 0:702bf7b2b7d8 871 /* DMA transfer start */
dkato 0:702bf7b2b7d8 872 DMA_Start(channel, false);
dkato 0:702bf7b2b7d8 873 }
dkato 0:702bf7b2b7d8 874 else
dkato 0:702bf7b2b7d8 875 {
dkato 0:702bf7b2b7d8 876 /* set error return value */
dkato 0:702bf7b2b7d8 877 retval = EERROR;
dkato 0:702bf7b2b7d8 878 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 879 {
dkato 0:702bf7b2b7d8 880 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 881 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 882 break;
dkato 0:702bf7b2b7d8 883
dkato 0:702bf7b2b7d8 884 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 885 error_code = EBADF;
dkato 0:702bf7b2b7d8 886 break;
dkato 0:702bf7b2b7d8 887
dkato 0:702bf7b2b7d8 888 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 889 error_code = EBUSY;
dkato 0:702bf7b2b7d8 890 break;
dkato 0:702bf7b2b7d8 891
dkato 0:702bf7b2b7d8 892 default:
dkato 0:702bf7b2b7d8 893 error_code = EFAULT;
dkato 0:702bf7b2b7d8 894 break;
dkato 0:702bf7b2b7d8 895 }
dkato 0:702bf7b2b7d8 896 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 897 }
dkato 0:702bf7b2b7d8 898 }
dkato 0:702bf7b2b7d8 899 }
dkato 0:702bf7b2b7d8 900 }
dkato 0:702bf7b2b7d8 901 else
dkato 0:702bf7b2b7d8 902 {
dkato 0:702bf7b2b7d8 903 /* set error return value */
dkato 0:702bf7b2b7d8 904 retval = EERROR;
dkato 0:702bf7b2b7d8 905 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 906 }
dkato 0:702bf7b2b7d8 907 }
dkato 0:702bf7b2b7d8 908 else
dkato 0:702bf7b2b7d8 909 {
dkato 0:702bf7b2b7d8 910 /* set error return value */
dkato 0:702bf7b2b7d8 911 retval = EERROR;
dkato 0:702bf7b2b7d8 912 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 913 }
dkato 0:702bf7b2b7d8 914
dkato 5:1390bfcb667c 915 if (0 == was_masked)
dkato 5:1390bfcb667c 916 {
dkato 5:1390bfcb667c 917 __enable_irq();
dkato 5:1390bfcb667c 918 }
dkato 5:1390bfcb667c 919
dkato 0:702bf7b2b7d8 920 return retval;
dkato 0:702bf7b2b7d8 921 }
dkato 0:702bf7b2b7d8 922
dkato 0:702bf7b2b7d8 923 /******************************************************************************
dkato 0:702bf7b2b7d8 924 End of function R_DMA_Start
dkato 0:702bf7b2b7d8 925 ******************************************************************************/
dkato 0:702bf7b2b7d8 926
dkato 0:702bf7b2b7d8 927 /******************************************************************************
dkato 0:702bf7b2b7d8 928 * Function Name: R_DMA_NextData
dkato 0:702bf7b2b7d8 929 * Description : Set continous DMA mode.
dkato 0:702bf7b2b7d8 930 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 931 * Arguments : channel -
dkato 0:702bf7b2b7d8 932 * Continuous DMA channel number.
dkato 0:702bf7b2b7d8 933 * *p_dma_data -
dkato 0:702bf7b2b7d8 934 * DMA address parameters.
dkato 0:702bf7b2b7d8 935 * *p_errno -
dkato 0:702bf7b2b7d8 936 * Pointer of error code.
dkato 0:702bf7b2b7d8 937 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 938 * error code -
dkato 0:702bf7b2b7d8 939 * EBADF : Channel status is DMA_CH_INIT.
dkato 0:702bf7b2b7d8 940 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 941 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 942 * EBUSY : It has been set continous DMA transfer.
dkato 0:702bf7b2b7d8 943 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 944 * EPERM : The value in p_ch_setup isn't in the right range.
dkato 0:702bf7b2b7d8 945 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 946 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 947 * p_dma_data is NULL.
dkato 0:702bf7b2b7d8 948 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 949 * Operation successful.
dkato 0:702bf7b2b7d8 950 * EERROR -
dkato 0:702bf7b2b7d8 951 * Error occured.
dkato 0:702bf7b2b7d8 952 ******************************************************************************/
dkato 0:702bf7b2b7d8 953
dkato 0:702bf7b2b7d8 954 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 955 int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 956 int32_t * const p_errno)
dkato 0:702bf7b2b7d8 957 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 958 {
dkato 0:702bf7b2b7d8 959 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 960 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 961 int_t error_code;
dkato 5:1390bfcb667c 962 int_t was_masked;
dkato 0:702bf7b2b7d8 963
dkato 0:702bf7b2b7d8 964 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 965
dkato 5:1390bfcb667c 966 /* disable all irq */
dkato 5:1390bfcb667c 967 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 968 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 969 #else
dkato 5:1390bfcb667c 970 was_masked = __disable_irq();
dkato 5:1390bfcb667c 971 #endif
dkato 5:1390bfcb667c 972
dkato 0:702bf7b2b7d8 973 /* check channel of argument */
dkato 0:702bf7b2b7d8 974 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 975 {
dkato 0:702bf7b2b7d8 976 if (NULL != p_dma_data)
dkato 0:702bf7b2b7d8 977 {
dkato 0:702bf7b2b7d8 978 /* check address parameter */
dkato 0:702bf7b2b7d8 979 /* check DMA transfer count destination address is 0 */
dkato 0:702bf7b2b7d8 980 if (0U == p_dma_data->count)
dkato 0:702bf7b2b7d8 981 {
dkato 0:702bf7b2b7d8 982 /* set error return value */
dkato 0:702bf7b2b7d8 983 retval = EERROR;
dkato 0:702bf7b2b7d8 984 DMA_SetErrCode(EPERM, p_errno);
dkato 0:702bf7b2b7d8 985 }
dkato 0:702bf7b2b7d8 986
dkato 0:702bf7b2b7d8 987 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 988 {
dkato 0:702bf7b2b7d8 989 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 990
dkato 0:702bf7b2b7d8 991 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 992 {
dkato 0:702bf7b2b7d8 993 if ((DMA_CH_OPEN == dma_info_ch->ch_stat) ||
dkato 0:702bf7b2b7d8 994 (DMA_CH_TRANSFER == dma_info_ch->ch_stat))
dkato 0:702bf7b2b7d8 995 {
dkato 0:702bf7b2b7d8 996 if (false == dma_info_ch->next_dma_flag)
dkato 0:702bf7b2b7d8 997 {
dkato 0:702bf7b2b7d8 998 /* set up address parameter for continous DMA*/
dkato 0:702bf7b2b7d8 999 DMA_SetNextData(channel, p_dma_data);
dkato 0:702bf7b2b7d8 1000 }
dkato 0:702bf7b2b7d8 1001 else
dkato 0:702bf7b2b7d8 1002 {
dkato 0:702bf7b2b7d8 1003 /* set error return value */
dkato 0:702bf7b2b7d8 1004 retval = EERROR;
dkato 0:702bf7b2b7d8 1005 DMA_SetErrCode(EBUSY, p_errno);
dkato 0:702bf7b2b7d8 1006 }
dkato 0:702bf7b2b7d8 1007 }
dkato 0:702bf7b2b7d8 1008 else
dkato 0:702bf7b2b7d8 1009 {
dkato 0:702bf7b2b7d8 1010 /* set error return value */
dkato 0:702bf7b2b7d8 1011 retval = EERROR;
dkato 0:702bf7b2b7d8 1012 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1013 {
dkato 0:702bf7b2b7d8 1014 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 1015 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 1016 break;
dkato 0:702bf7b2b7d8 1017
dkato 0:702bf7b2b7d8 1018 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 1019 error_code = EBADF;
dkato 0:702bf7b2b7d8 1020 break;
dkato 0:702bf7b2b7d8 1021
dkato 0:702bf7b2b7d8 1022 default:
dkato 0:702bf7b2b7d8 1023 error_code = EFAULT;
dkato 0:702bf7b2b7d8 1024 break;
dkato 0:702bf7b2b7d8 1025 }
dkato 0:702bf7b2b7d8 1026 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 1027 }
dkato 0:702bf7b2b7d8 1028 }
dkato 0:702bf7b2b7d8 1029 }
dkato 0:702bf7b2b7d8 1030 }
dkato 0:702bf7b2b7d8 1031 else
dkato 0:702bf7b2b7d8 1032 {
dkato 0:702bf7b2b7d8 1033 /* set error return value */
dkato 0:702bf7b2b7d8 1034 retval = EERROR;
dkato 0:702bf7b2b7d8 1035 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 1036 }
dkato 0:702bf7b2b7d8 1037 }
dkato 0:702bf7b2b7d8 1038 else
dkato 0:702bf7b2b7d8 1039 {
dkato 0:702bf7b2b7d8 1040 /* set error return value */
dkato 0:702bf7b2b7d8 1041 retval = EERROR;
dkato 0:702bf7b2b7d8 1042 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 1043 }
dkato 0:702bf7b2b7d8 1044
dkato 5:1390bfcb667c 1045 if (0 == was_masked)
dkato 5:1390bfcb667c 1046 {
dkato 5:1390bfcb667c 1047 __enable_irq();
dkato 5:1390bfcb667c 1048 }
dkato 5:1390bfcb667c 1049
dkato 0:702bf7b2b7d8 1050 return retval;
dkato 0:702bf7b2b7d8 1051 }
dkato 0:702bf7b2b7d8 1052
dkato 0:702bf7b2b7d8 1053 /******************************************************************************
dkato 0:702bf7b2b7d8 1054 End of function R_DMA_NextData
dkato 0:702bf7b2b7d8 1055 ******************************************************************************/
dkato 0:702bf7b2b7d8 1056
dkato 0:702bf7b2b7d8 1057 /******************************************************************************
dkato 0:702bf7b2b7d8 1058 * Function Name: R_DMA_Cancel
dkato 0:702bf7b2b7d8 1059 * Description : Cancel DMA transfer.
dkato 0:702bf7b2b7d8 1060 * Check parameter in this function mainly.
dkato 0:702bf7b2b7d8 1061 * Arguments : channel -
dkato 0:702bf7b2b7d8 1062 * Cancel DMA channel number.
dkato 0:702bf7b2b7d8 1063 * *p_remain -
dkato 0:702bf7b2b7d8 1064 * Remain data size of DMA transfer when it stopping.
dkato 0:702bf7b2b7d8 1065 * *p_errno -
dkato 0:702bf7b2b7d8 1066 * Pointer of error code.
dkato 0:702bf7b2b7d8 1067 * When pointer is NULL, it isn't set error code.
dkato 0:702bf7b2b7d8 1068 * error code -
dkato 0:702bf7b2b7d8 1069 * EBADF : Channel status is DMA_CH_INIT or DMA_CH_OPEN.
dkato 0:702bf7b2b7d8 1070 * (DMA stopped)
dkato 0:702bf7b2b7d8 1071 * EINVAL : Value of the ch is outside the range of
dkato 0:702bf7b2b7d8 1072 * (-1) < ch < (DMA_CH_NUM + 1).
dkato 0:702bf7b2b7d8 1073 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 1074 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 1075 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 1076 * p_remain is NULL.
dkato 0:702bf7b2b7d8 1077 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 1078 * Operation successful.
dkato 0:702bf7b2b7d8 1079 * EERROR -
dkato 0:702bf7b2b7d8 1080 * Error occured.
dkato 0:702bf7b2b7d8 1081 ******************************************************************************/
dkato 0:702bf7b2b7d8 1082
dkato 0:702bf7b2b7d8 1083 /* ->IPA M1.1.1 If this function is the whole system, it will be called. */
dkato 0:702bf7b2b7d8 1084 int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 1085 /* <-IPA M1.1.1 */
dkato 0:702bf7b2b7d8 1086 {
dkato 0:702bf7b2b7d8 1087 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 1088 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 1089 int_t error_code;
dkato 5:1390bfcb667c 1090 int_t was_masked;
dkato 0:702bf7b2b7d8 1091
dkato 0:702bf7b2b7d8 1092 DMA_SetErrCode(ESUCCESS, p_errno);
dkato 0:702bf7b2b7d8 1093
dkato 5:1390bfcb667c 1094 /* disable all irq */
dkato 5:1390bfcb667c 1095 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 1096 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 1097 #else
dkato 5:1390bfcb667c 1098 was_masked = __disable_irq();
dkato 5:1390bfcb667c 1099 #endif
dkato 5:1390bfcb667c 1100
dkato 0:702bf7b2b7d8 1101 /* check channel of argument */
dkato 0:702bf7b2b7d8 1102 if ((0 <= channel) && (channel < DMA_CH_NUM))
dkato 0:702bf7b2b7d8 1103 {
dkato 0:702bf7b2b7d8 1104 /* check whether p_remain is NULL */
dkato 0:702bf7b2b7d8 1105 if (NULL != p_remain)
dkato 0:702bf7b2b7d8 1106 {
dkato 0:702bf7b2b7d8 1107 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 1108
dkato 0:702bf7b2b7d8 1109 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 1110 {
dkato 0:702bf7b2b7d8 1111 if (DMA_CH_TRANSFER == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1112 {
dkato 0:702bf7b2b7d8 1113 /* set up address parameter for continous DMA*/
dkato 0:702bf7b2b7d8 1114 DMA_Stop(channel, p_remain);
dkato 0:702bf7b2b7d8 1115 }
dkato 0:702bf7b2b7d8 1116 else
dkato 0:702bf7b2b7d8 1117 {
dkato 0:702bf7b2b7d8 1118 /* set error return value */
dkato 0:702bf7b2b7d8 1119 retval = EERROR;
dkato 0:702bf7b2b7d8 1120 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 1121 {
dkato 0:702bf7b2b7d8 1122 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 1123 error_code = ENOTSUP;
dkato 0:702bf7b2b7d8 1124 break;
dkato 0:702bf7b2b7d8 1125
dkato 0:702bf7b2b7d8 1126 case DMA_CH_INIT:
dkato 0:702bf7b2b7d8 1127 error_code = EBADF;
dkato 0:702bf7b2b7d8 1128 break;
dkato 0:702bf7b2b7d8 1129
dkato 0:702bf7b2b7d8 1130 case DMA_CH_OPEN:
dkato 0:702bf7b2b7d8 1131 error_code = EBADF;
dkato 0:702bf7b2b7d8 1132 break;
dkato 0:702bf7b2b7d8 1133
dkato 0:702bf7b2b7d8 1134 default:
dkato 0:702bf7b2b7d8 1135 error_code = EFAULT;
dkato 0:702bf7b2b7d8 1136 break;
dkato 0:702bf7b2b7d8 1137 }
dkato 0:702bf7b2b7d8 1138 DMA_SetErrCode(error_code, p_errno);
dkato 0:702bf7b2b7d8 1139 }
dkato 0:702bf7b2b7d8 1140 }
dkato 0:702bf7b2b7d8 1141 }
dkato 0:702bf7b2b7d8 1142 else
dkato 0:702bf7b2b7d8 1143 {
dkato 0:702bf7b2b7d8 1144 /* set error return value */
dkato 0:702bf7b2b7d8 1145 retval = EERROR;
dkato 0:702bf7b2b7d8 1146 DMA_SetErrCode(EFAULT, p_errno);
dkato 0:702bf7b2b7d8 1147 }
dkato 0:702bf7b2b7d8 1148 }
dkato 0:702bf7b2b7d8 1149 else
dkato 0:702bf7b2b7d8 1150 {
dkato 0:702bf7b2b7d8 1151 /* set error return value */
dkato 0:702bf7b2b7d8 1152 retval = EERROR;
dkato 0:702bf7b2b7d8 1153 DMA_SetErrCode(EINVAL, p_errno);
dkato 0:702bf7b2b7d8 1154 }
dkato 0:702bf7b2b7d8 1155
dkato 5:1390bfcb667c 1156 if (0 == was_masked)
dkato 5:1390bfcb667c 1157 {
dkato 5:1390bfcb667c 1158 __enable_irq();
dkato 5:1390bfcb667c 1159 }
dkato 5:1390bfcb667c 1160
dkato 0:702bf7b2b7d8 1161 return retval;
dkato 0:702bf7b2b7d8 1162 }
dkato 0:702bf7b2b7d8 1163
dkato 0:702bf7b2b7d8 1164 /******************************************************************************
dkato 0:702bf7b2b7d8 1165 End of function R_DMA_Cancel
dkato 0:702bf7b2b7d8 1166 ******************************************************************************/
dkato 0:702bf7b2b7d8 1167