Graphics framework for GR-PEACH. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

Dependents:   ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample GR-PEACH_LCD_4_3inch_Save_to_USB ... more

License

When you use this library, we judge you have agreed to the following contents.

https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

Note

If you import the GraphicsFramework library, please import GR-PEACH_video library and R_BSP library together.



JPEG Converter

The JPEG Converter driver implements encode and decode functionality which uses the JCU of the RZ/A Series.

Hello World!

Import programJCU_HelloWorld

Hello World for JCU(JPEG Codec Unit). JCU is JPEG codec unit of RZ/A1. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

API

Import library

Data Structures

struct bitmap_buff_info_t
Bitmap data setting struct. More...
struct encode_options_t
Encode option setting. More...

Public Types

enum jpeg_conv_error_t {
JPEG_CONV_OK = 0, JPEG_CONV_JCU_ERR = -1, JPEG_CONV_FORMA_ERR = -2, JPEG_CONV_PARAM_ERR = -3,
JPEG_CONV_BUSY = -4, JPEG_CONV_PARAM_RANGE_ERR = -7
}

Error codes.

More...
enum wr_rd_swa_t {
WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT = 1, WR_RD_WRSWA_16BIT = 2, WR_RD_WRSWA_16_8BIT = 3,
WR_RD_WRSWA_32BIT = 4, WR_RD_WRSWA_32_8BIT = 5, WR_RD_WRSWA_32_16BIT = 6, WR_RD_WRSWA_32_16_8BIT = 7
}

Write/Read image pixcel frame buffer swap setting.

More...
enum wr_rd_format_t { WR_RD_YCbCr422 = 0x00, WR_RD_ARGB8888 = 0x01, WR_RD_RGB565 = 0x02 }

Write/Read image pixcel format selects.

More...
enum sub_sampling_t { SUB_SAMPLING_1_1 = 0x00, SUB_SAMPLING_1_2 = 0x01, SUB_SAMPLING_1_4 = 0x02, SUB_SAMPLING_1_8 = 0x03 }

Thinning output image selects.

More...
enum cbcr_offset_t { CBCR_OFFSET_0 = 0x00, CBCR_OFFSET_128 = 0x01 }

Cb/Cr range selects for decode.

More...

Public Member Functions

JPEG_Converter ()
Constructor method of JPEG converter(encode/decode)
virtual ~JPEG_Converter ()
Destructor method of JPEG converter(encode/decode)
JPEG_Converter::jpeg_conv_error_t decode (void *pJpegBuff, bitmap_buff_info_t *psOutputBuff)
Decode JPEG to rinear data.
JPEG_Converter::jpeg_conv_error_t decode (void *pJpegBuff, bitmap_buff_info_t *psOutputBuff, decode_options_t *pOptions)
JPEG data decode to bitmap.
JPEG_Converter::jpeg_conv_error_t encode ( bitmap_buff_info_t *psInputBuff, void *pJpegBuff, size_t *pEncodeSize)
Encode rinear data to JPEG.
JPEG_Converter::jpeg_conv_error_t encode ( bitmap_buff_info_t *psInputBuff, void *pJpegBuff, size_t *pEncodeSize, encode_options_t *pOptions)
Bitmap data encode to JPEG.
JPEG_Converter::jpeg_conv_error_t SetQuality (const uint8_t qual)
Set encode quality.

Correspondence file

A correspondence file of JPEG Converter is as the following table.

JPEGCorrespondence
Width>0(greater than 0)
Height>0(greater than 0)
Color formatYCbCr444, YCbCr422, YCbCr420, YCbCr411
BitmapCorrespondence
Width>0(greater than 0)
Height>0(greater than 0)
Color formatYCbCr422

Notice

You run JPEG converter once destruction each time.

You set whether these JPEG files aren't input, or it check error setting decode(set in "flag" = true). The JPEG file which becomes correspondence outside will be the following condition.

  • File besides the above-mentioned correspondence file.
  • As information in the JPEG file, WIDTH or HEIGHT is larger than output buffer setting.

Buffer area is used encode/decode, set 8 bytes align and non-cash memory area. The output buffer when decoding, is made beyond the size decided in the size of the JPEG file, the format, setting of thinning out. You make output buffer for decode/encode to enough big size in order to stock this result. JPEG Converter, if you do not particularly perform specified, does not check size against the output data at the time of encoding and decoding. You set the output buffer so that there is no effect of corruption by the output data.

Color format

Color format in case to be converted from Bitmap to JPEG is either ARGB8888 or RGB555, YCbCr422. Color format of the If you want to convert from JPEG file to Bitmap file is YCbCr422. You correct "alpha(member of decode_options_t)" of setting and "output_cb_cr_offset(member of decode_options_t)" according to color format when decoding.

  • example
    decode to ARGB8888(WR_RD_ARGB8888 set in format member of bitmap_buff_info_t)
    alpha = 0x01-0xFF
    output_cb_cr_offset = CBCR_OFFSET_0

    decode to YCbCr422(WR_RD_YCbCr422 set in format member of bitmap_buff_info_t)
    alpha = 0
    output_cb_cr_offset = CBCR_OFFSET_0 or CBCR_OFFSET_128

    decode to RGB565(WR_RD_RGB565 set in format member of bitmap_buff_info_t)
    alpha = 0
    output_cb_cr_offset = CBCR_OFFSET_0

Decode/encode settings are optional

If omitted encode/decode settings, it will work with the following settings.
[Decode option setting (member of decode_options_t)]

  • Vertical sub sampling is thinning output image to 1/1.
  • Horizontal sub sampling is thinning output image to 1/1.
  • Output data of Cb/Cr range is -128 to 127.
  • Output data of swap in 8-bit units: 2-1-4-3-6-5-8-7.
  • Alpha value of 0.
  • JPEG format correspondence outside error check.
  • It decode in a synchronous function.

[Encode option setting (member of encode_options_t)]

  • DRI value is 0.
  • Encoding JPEG file start width offset is 0.
  • Encoding JPEG file start height offset is 0.
  • Input data of Cb/Cr range of input data is -128 to 127.
  • Input data swap in 8-bit units: 2-1-4-3-6-5-8-7.
  • It don't check encode size.
  • Quantization Y use default table(Quality75).
  • Quantization C use default table(Quality75).
  • Huffman Y DC use default table.
  • Huffman C DC use default table.
  • Huffman Y AC use default table.
  • Huffman C AC use default table.
  • It encode in a synchronous function.

Synchronous/asynchronous switching

Decoding and encoding setting to operate asynchronously by setting a callback function(decode_options_t and encode_options_t).

Quality

Quality changes are possible. If you want to change the Quality, please specify the table made of Quality you want to change the address of the setting. If you do not want to change the Quality, it will operate at Quality75.

RGA

The RGA library implements fast drawing functionality which uses the RGA of the RZ/A Series.
Supporting compiler is ARMCC, GCC ARM and IAR.

Hello World!

Import programRGA_HelloWorld

Hello World for RGA(Renesas Graphics Architecture). RGA is the Graphics Library of RZ/A1. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

Committer:
dkato
Date:
Mon Apr 24 08:16:23 2017 +0000
Revision:
13:1ee2176ef13f
Parent:
0:37e1e6a45ced
Add "SetQuality()" to JCU.
; Bug fixes.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:37e1e6a45ced 1 /*******************************************************************************
dkato 0:37e1e6a45ced 2 * DISCLAIMER
dkato 0:37e1e6a45ced 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:37e1e6a45ced 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:37e1e6a45ced 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:37e1e6a45ced 6 * all applicable laws, including copyright laws.
dkato 0:37e1e6a45ced 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:37e1e6a45ced 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:37e1e6a45ced 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:37e1e6a45ced 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:37e1e6a45ced 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:37e1e6a45ced 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:37e1e6a45ced 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:37e1e6a45ced 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:37e1e6a45ced 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:37e1e6a45ced 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:37e1e6a45ced 17 * and to discontinue the availability of this software. By using this software,
dkato 0:37e1e6a45ced 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:37e1e6a45ced 19 * following link:
dkato 0:37e1e6a45ced 20 * http://www.renesas.com/disclaimer
dkato 0:37e1e6a45ced 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:37e1e6a45ced 22 *******************************************************************************/
dkato 0:37e1e6a45ced 23 /**
dkato 0:37e1e6a45ced 24 * @file clib_registers.h
dkato 0:37e1e6a45ced 25 * @brief $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
dkato 0:37e1e6a45ced 26 * $Rev: 30 $
dkato 0:37e1e6a45ced 27 * $Date:: 2014-02-13 21:21:47 +0900#$
dkato 0:37e1e6a45ced 28 * - Description: Common code for drivers and more.
dkato 0:37e1e6a45ced 29 */
dkato 0:37e1e6a45ced 30
dkato 0:37e1e6a45ced 31 #ifndef CLIB_REGISTERS_H
dkato 0:37e1e6a45ced 32 #define CLIB_REGISTERS_H
dkato 0:37e1e6a45ced 33
dkato 0:37e1e6a45ced 34 /******************************************************************************
dkato 0:37e1e6a45ced 35 Includes <System Includes> , "Project Includes"
dkato 0:37e1e6a45ced 36 ******************************************************************************/
dkato 0:37e1e6a45ced 37 #include "r_typedefs.h"
dkato 0:37e1e6a45ced 38 #include "r_ospl.h"
dkato 0:37e1e6a45ced 39
dkato 0:37e1e6a45ced 40
dkato 0:37e1e6a45ced 41 #ifdef __cplusplus
dkato 0:37e1e6a45ced 42 extern "C" {
dkato 0:37e1e6a45ced 43 #endif /* __cplusplus */
dkato 0:37e1e6a45ced 44
dkato 0:37e1e6a45ced 45
dkato 0:37e1e6a45ced 46 /******************************************************************************
dkato 0:37e1e6a45ced 47 Typedef definitions
dkato 0:37e1e6a45ced 48 ******************************************************************************/
dkato 0:37e1e6a45ced 49
dkato 0:37e1e6a45ced 50 /******************************************************************************
dkato 0:37e1e6a45ced 51 Macro definitions
dkato 0:37e1e6a45ced 52 ******************************************************************************/
dkato 0:37e1e6a45ced 53
dkato 0:37e1e6a45ced 54 /******************************************************************************
dkato 0:37e1e6a45ced 55 Variable Externs
dkato 0:37e1e6a45ced 56 ******************************************************************************/
dkato 0:37e1e6a45ced 57
dkato 0:37e1e6a45ced 58 /******************************************************************************
dkato 0:37e1e6a45ced 59 Functions Prototypes
dkato 0:37e1e6a45ced 60 ******************************************************************************/
dkato 0:37e1e6a45ced 61
dkato 0:37e1e6a45ced 62 /******************************************************************************
dkato 0:37e1e6a45ced 63 Inline Functions
dkato 0:37e1e6a45ced 64 ******************************************************************************/
dkato 0:37e1e6a45ced 65
dkato 0:37e1e6a45ced 66
dkato 0:37e1e6a45ced 67 /**
dkato 0:37e1e6a45ced 68 * @brief CPG unit of RZ/A1H.
dkato 0:37e1e6a45ced 69 *
dkato 0:37e1e6a45ced 70 * @par Parameters
dkato 0:37e1e6a45ced 71 * None
dkato 0:37e1e6a45ced 72 * @return Pointer to CPG structure.
dkato 0:37e1e6a45ced 73 */
dkato 0:37e1e6a45ced 74 INLINE struct st_cpg *R_Get_CPG_Base(void) {
dkato 0:37e1e6a45ced 75 /* ->QAC 0306 */
dkato 0:37e1e6a45ced 76 #if IODEFINE_H_VERSION >= 100
dkato 0:37e1e6a45ced 77 return &CPG;
dkato 0:37e1e6a45ced 78 #else
dkato 0:37e1e6a45ced 79 return (struct st_cpg *) &CPG;
dkato 0:37e1e6a45ced 80 #endif
dkato 0:37e1e6a45ced 81 /* <-QAC 0306 */
dkato 0:37e1e6a45ced 82 }
dkato 0:37e1e6a45ced 83
dkato 0:37e1e6a45ced 84
dkato 0:37e1e6a45ced 85 /***********************************************************************
dkato 0:37e1e6a45ced 86 * Group: Register_Access
dkato 0:37e1e6a45ced 87 ************************************************************************/
dkato 0:37e1e6a45ced 88
dkato 0:37e1e6a45ced 89 /**
dkato 0:37e1e6a45ced 90 * @brief Set a value to register bit field.
dkato 0:37e1e6a45ced 91 *
dkato 0:37e1e6a45ced 92 * @param in_out_Register Address of register or variable
dkato 0:37e1e6a45ced 93 * @param RegisterName Name of register
dkato 0:37e1e6a45ced 94 * @param BitName Name of bit
dkato 0:37e1e6a45ced 95 * @param Value Writing value
dkato 0:37e1e6a45ced 96 * @return None.
dkato 0:37e1e6a45ced 97 *
dkato 0:37e1e6a45ced 98 * @par Description
dkato 0:37e1e6a45ced 99 * Bit width is got from "RegisterName".
dkato 0:37e1e6a45ced 100 */
dkato 0:37e1e6a45ced 101 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 102 #define R_DRV_SET_REGISTER_BIT_FIELD( \
dkato 0:37e1e6a45ced 103 in_out_Register, RegisterName, BitName, Value ) \
dkato 0:37e1e6a45ced 104 R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
dkato 0:37e1e6a45ced 105 in_out_Register, RegisterName, BitName, Value, \
dkato 0:37e1e6a45ced 106 DRV__BIT_WIDTH__##RegisterName )
dkato 0:37e1e6a45ced 107 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 108
dkato 0:37e1e6a45ced 109
dkato 0:37e1e6a45ced 110 /**
dkato 0:37e1e6a45ced 111 * @brief Set a value to register bit field with width parameter.
dkato 0:37e1e6a45ced 112 *
dkato 0:37e1e6a45ced 113 * @param in_out_Register Address of register or variable
dkato 0:37e1e6a45ced 114 * @param RegisterName Name of register
dkato 0:37e1e6a45ced 115 * @param BitName Name of bit
dkato 0:37e1e6a45ced 116 * @param Value Writing value
dkato 0:37e1e6a45ced 117 * @param BitWidth BitWidth
dkato 0:37e1e6a45ced 118 * @return None.
dkato 0:37e1e6a45ced 119 */
dkato 0:37e1e6a45ced 120 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 121 /* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
dkato 0:37e1e6a45ced 122 /* ->SEC M5.1.3 */
dkato 0:37e1e6a45ced 123 #define R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
dkato 0:37e1e6a45ced 124 in_out_Register, RegisterName, BitName, Value, BitWidth ) \
dkato 0:37e1e6a45ced 125 R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \
dkato 0:37e1e6a45ced 126 in_out_Register, RegisterName##__##BitName, Value, BitWidth )
dkato 0:37e1e6a45ced 127 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
dkato 0:37e1e6a45ced 128 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 129
dkato 0:37e1e6a45ced 130 /* Sub macro */
dkato 0:37e1e6a45ced 131 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 132 /* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
dkato 0:37e1e6a45ced 133 /* ->SEC M5.1.3 */
dkato 0:37e1e6a45ced 134 #define R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \
dkato 0:37e1e6a45ced 135 in_out_Register, RegisterBitName, Value, BitWidth ) \
dkato 0:37e1e6a45ced 136 R_DRV_SET_REGISTER_BIT_FIELD_SUB( \
dkato 0:37e1e6a45ced 137 in_out_Register, RegisterBitName, Value, BitWidth )
dkato 0:37e1e6a45ced 138 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
dkato 0:37e1e6a45ced 139 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 140
dkato 0:37e1e6a45ced 141 /* Sub macro */
dkato 0:37e1e6a45ced 142 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 143 #define R_DRV_SET_REGISTER_BIT_FIELD_SUB( \
dkato 0:37e1e6a45ced 144 in_out_Register, RegisterBitName, Value, BitWidth ) \
dkato 0:37e1e6a45ced 145 R_OSPL_SET_TO_##BitWidth##_BIT_REGISTER( \
dkato 0:37e1e6a45ced 146 (volatile uint##BitWidth##_t*)(in_out_Register), \
dkato 0:37e1e6a45ced 147 DRV__MASK##BitWidth##__##RegisterBitName, \
dkato 0:37e1e6a45ced 148 DRV__SHIFT__##RegisterBitName, \
dkato 0:37e1e6a45ced 149 (uint##BitWidth##_t)(Value) )
dkato 0:37e1e6a45ced 150 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 151
dkato 0:37e1e6a45ced 152
dkato 0:37e1e6a45ced 153 /**
dkato 0:37e1e6a45ced 154 * @brief Get a value from register bit field.
dkato 0:37e1e6a45ced 155 *
dkato 0:37e1e6a45ced 156 * @param RegisterValue Value of register or variable
dkato 0:37e1e6a45ced 157 * @param RegisterName Name of register
dkato 0:37e1e6a45ced 158 * @param BitName Name of bit
dkato 0:37e1e6a45ced 159 * @return Value of shifted bit field.
dkato 0:37e1e6a45ced 160 *
dkato 0:37e1e6a45ced 161 * @par Description
dkato 0:37e1e6a45ced 162 * Bit width is got from "RegisterName".
dkato 0:37e1e6a45ced 163 */
dkato 0:37e1e6a45ced 164 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 165 #define R_DRV_GET_REGISTER_BIT_FIELD( \
dkato 0:37e1e6a45ced 166 RegisterValue, RegisterName, BitName ) \
dkato 0:37e1e6a45ced 167 R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
dkato 0:37e1e6a45ced 168 RegisterValue, RegisterName, BitName, \
dkato 0:37e1e6a45ced 169 DRV__BIT_WIDTH__##RegisterName )
dkato 0:37e1e6a45ced 170 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 171
dkato 0:37e1e6a45ced 172
dkato 0:37e1e6a45ced 173 /**
dkato 0:37e1e6a45ced 174 * @brief Get a value from register bit field with width parameter.
dkato 0:37e1e6a45ced 175 *
dkato 0:37e1e6a45ced 176 * @param RegisterValue Value of register or variable
dkato 0:37e1e6a45ced 177 * @param RegisterName Name of register
dkato 0:37e1e6a45ced 178 * @param BitName Name of bit
dkato 0:37e1e6a45ced 179 * @param BitWidth BitWidth
dkato 0:37e1e6a45ced 180 * @return Value of shifted bit field.
dkato 0:37e1e6a45ced 181 */
dkato 0:37e1e6a45ced 182 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 183 /* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
dkato 0:37e1e6a45ced 184 /* ->SEC M5.1.3 */
dkato 0:37e1e6a45ced 185 #define R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
dkato 0:37e1e6a45ced 186 RegisterValue, RegisterName, BitName, BitWidth ) \
dkato 0:37e1e6a45ced 187 R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \
dkato 0:37e1e6a45ced 188 RegisterValue, RegisterName##__##BitName, BitWidth )
dkato 0:37e1e6a45ced 189 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
dkato 0:37e1e6a45ced 190 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 191
dkato 0:37e1e6a45ced 192 /* Sub macro */
dkato 0:37e1e6a45ced 193 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 194 /* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
dkato 0:37e1e6a45ced 195 /* ->SEC M5.1.3 */
dkato 0:37e1e6a45ced 196 #define R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \
dkato 0:37e1e6a45ced 197 RegisterValue, RegisterBitName, BitWidth ) \
dkato 0:37e1e6a45ced 198 R_DRV_GET_REGISTER_BIT_FIELD_SUB( \
dkato 0:37e1e6a45ced 199 RegisterValue, RegisterBitName, BitWidth )
dkato 0:37e1e6a45ced 200 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
dkato 0:37e1e6a45ced 201 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 202
dkato 0:37e1e6a45ced 203 /* Sub macro */
dkato 0:37e1e6a45ced 204 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 205 #define R_DRV_GET_REGISTER_BIT_FIELD_SUB( \
dkato 0:37e1e6a45ced 206 RegisterValue, RegisterBitName, BitWidth ) \
dkato 0:37e1e6a45ced 207 R_OSPL_GET_FROM_##BitWidth##_BIT_REGISTER( \
dkato 0:37e1e6a45ced 208 (volatile const uint##BitWidth##_t*) &(RegisterValue), \
dkato 0:37e1e6a45ced 209 DRV__MASK##BitWidth##__##RegisterBitName, \
dkato 0:37e1e6a45ced 210 DRV__SHIFT__##RegisterBitName )
dkato 0:37e1e6a45ced 211 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 212
dkato 0:37e1e6a45ced 213
dkato 0:37e1e6a45ced 214 /**
dkato 0:37e1e6a45ced 215 * @brief Returns whether specified value is overflowed from the bit field.
dkato 0:37e1e6a45ced 216 *
dkato 0:37e1e6a45ced 217 * @param RegisterName Name of register
dkato 0:37e1e6a45ced 218 * @param BitName Name of bit
dkato 0:37e1e6a45ced 219 * @param Value Checking value
dkato 0:37e1e6a45ced 220 * @return Whether specified value is overflowed.
dkato 0:37e1e6a45ced 221 */
dkato 0:37e1e6a45ced 222 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 223 #define R_DRV_IS_OVERFLOW_BIT_FIELD( \
dkato 0:37e1e6a45ced 224 RegisterName, BitName, Value ) \
dkato 0:37e1e6a45ced 225 R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \
dkato 0:37e1e6a45ced 226 RegisterName, BitName, Value, DRV__BIT_WIDTH__##RegisterName )
dkato 0:37e1e6a45ced 227 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 228
dkato 0:37e1e6a45ced 229
dkato 0:37e1e6a45ced 230 /**
dkato 0:37e1e6a45ced 231 * @brief Returns whether specified value is overflowed from the bit field.
dkato 0:37e1e6a45ced 232 *
dkato 0:37e1e6a45ced 233 * @param RegisterName Name of register
dkato 0:37e1e6a45ced 234 * @param BitName Name of bit
dkato 0:37e1e6a45ced 235 * @param Value Checking value
dkato 0:37e1e6a45ced 236 * @param BitWidth BitWidth
dkato 0:37e1e6a45ced 237 * @return Whether specified value is overflowed.
dkato 0:37e1e6a45ced 238 */
dkato 0:37e1e6a45ced 239 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 240 /* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
dkato 0:37e1e6a45ced 241 /* ->SEC M5.1.3 */
dkato 0:37e1e6a45ced 242 #define R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \
dkato 0:37e1e6a45ced 243 RegisterName, BitName, Value, BitWidth ) \
dkato 0:37e1e6a45ced 244 R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \
dkato 0:37e1e6a45ced 245 RegisterName##__##BitName, Value, BitWidth )
dkato 0:37e1e6a45ced 246 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
dkato 0:37e1e6a45ced 247 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 248
dkato 0:37e1e6a45ced 249 /* Sub macro */
dkato 0:37e1e6a45ced 250 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 251 /* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
dkato 0:37e1e6a45ced 252 /* ->SEC M5.1.3 */
dkato 0:37e1e6a45ced 253 #define R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \
dkato 0:37e1e6a45ced 254 RegisterBitName, Value, BitWidth ) \
dkato 0:37e1e6a45ced 255 R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \
dkato 0:37e1e6a45ced 256 RegisterBitName, Value, BitWidth )
dkato 0:37e1e6a45ced 257 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
dkato 0:37e1e6a45ced 258 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 259
dkato 0:37e1e6a45ced 260 /* Sub macro */
dkato 0:37e1e6a45ced 261 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 262 #define R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \
dkato 0:37e1e6a45ced 263 RegisterBitName, Value, BitWidth ) \
dkato 0:37e1e6a45ced 264 R_DRV_IsOverflowBitField##BitWidth##_Sub( \
dkato 0:37e1e6a45ced 265 DRV__MASK##BitWidth##__##RegisterBitName, \
dkato 0:37e1e6a45ced 266 DRV__SHIFT__##RegisterBitName, \
dkato 0:37e1e6a45ced 267 Value )
dkato 0:37e1e6a45ced 268 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
dkato 0:37e1e6a45ced 269
dkato 0:37e1e6a45ced 270
dkato 0:37e1e6a45ced 271 /* Sub function */
dkato 0:37e1e6a45ced 272 /* : R_DRV_IsOverflowBitField32_Sub */
dkato 0:37e1e6a45ced 273 /* : R_DRV_IsOverflowBitField16_Sub */
dkato 0:37e1e6a45ced 274 /* : R_DRV_IsOverflowBitField8_Sub */
dkato 0:37e1e6a45ced 275 INLINE bool_t R_DRV_IsOverflowBitField32_Sub( uint32_t const Mask,
dkato 0:37e1e6a45ced 276 int_fast32_t const Shift, uint32_t const Value )
dkato 0:37e1e6a45ced 277 {
dkato 0:37e1e6a45ced 278 return ( ( (uint32_t)(Value) &
dkato 0:37e1e6a45ced 279 ~( (uint32_t)(Mask) >> (Shift) ) )
dkato 0:37e1e6a45ced 280 != 0u );
dkato 0:37e1e6a45ced 281 }
dkato 0:37e1e6a45ced 282
dkato 0:37e1e6a45ced 283 INLINE bool_t R_DRV_IsOverflowBitField16_Sub( uint16_t const Mask,
dkato 0:37e1e6a45ced 284 int_fast32_t const Shift, uint16_t const Value )
dkato 0:37e1e6a45ced 285 {
dkato 0:37e1e6a45ced 286 return ( ( (uint_fast16_t)(Value) &
dkato 0:37e1e6a45ced 287 ~( (uint_fast16_t)(Mask) >> (Shift) ) )
dkato 0:37e1e6a45ced 288 != 0u );
dkato 0:37e1e6a45ced 289 }
dkato 0:37e1e6a45ced 290
dkato 0:37e1e6a45ced 291 INLINE bool_t R_DRV_IsOverflowBitField8_Sub( uint8_t const Mask,
dkato 0:37e1e6a45ced 292 int_fast32_t const Shift, uint8_t const Value )
dkato 0:37e1e6a45ced 293 {
dkato 0:37e1e6a45ced 294 return ( ( (uint_fast8_t)(Value) &
dkato 0:37e1e6a45ced 295 ~( (uint_fast8_t)(Mask) >> (Shift) ) )
dkato 0:37e1e6a45ced 296 != 0u );
dkato 0:37e1e6a45ced 297 }
dkato 0:37e1e6a45ced 298
dkato 0:37e1e6a45ced 299
dkato 0:37e1e6a45ced 300 /**
dkato 0:37e1e6a45ced 301 * @def CPG
dkato 0:37e1e6a45ced 302 * @brief CPG
dkato 0:37e1e6a45ced 303 */
dkato 0:37e1e6a45ced 304 /* 0xFCFE0438 */
dkato 0:37e1e6a45ced 305
dkato 0:37e1e6a45ced 306 #define DRV__BIT_WIDTH__STBCR9 8
dkato 0:37e1e6a45ced 307
dkato 0:37e1e6a45ced 308 enum { /*uint8_t */ DRV__MASK8__STBCR9__MSTP91 = 0x02 }; /* VDC5-0, LVDS */
dkato 0:37e1e6a45ced 309 enum { /*uint8_t */ DRV__MASK8__STBCR9__MSTP90 = 0x01 }; /* VDC5-1 */
dkato 0:37e1e6a45ced 310
dkato 0:37e1e6a45ced 311 enum { /* int_fast32_t */ DRV__SHIFT__STBCR9__MSTP91 = 1 };
dkato 0:37e1e6a45ced 312 enum { /* int_fast32_t */ DRV__SHIFT__STBCR9__MSTP90 = 0 };
dkato 0:37e1e6a45ced 313
dkato 0:37e1e6a45ced 314 #ifdef __cplusplus
dkato 0:37e1e6a45ced 315 } /* extern "C" */
dkato 0:37e1e6a45ced 316 #endif /* __cplusplus */
dkato 0:37e1e6a45ced 317
dkato 0:37e1e6a45ced 318 #endif /* CLIB_REGISTERS_H */
dkato 0:37e1e6a45ced 319
dkato 0:37e1e6a45ced 320
dkato 0:37e1e6a45ced 321