Graphics framework for GR-PEACH. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE
Dependents: ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample GR-PEACH_LCD_4_3inch_Save_to_USB ... more
License
When you use this library, we judge you have agreed to the following contents.
https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE
Note
If you import the GraphicsFramework library, please import GR-PEACH_video library and R_BSP library together.
JPEG Converter
The JPEG Converter driver implements encode and decode functionality which uses the JCU of the RZ/A Series.
Hello World!
Import programJCU_HelloWorld
Hello World for JCU(JPEG Codec Unit). JCU is JPEG codec unit of RZ/A1. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE
API
Import library
Data Structures |
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struct | bitmap_buff_info_t |
Bitmap data setting struct.
More...
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struct | encode_options_t |
Encode option setting.
More...
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Public Types |
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enum |
jpeg_conv_error_t
{
JPEG_CONV_OK = 0, JPEG_CONV_JCU_ERR = -1, JPEG_CONV_FORMA_ERR = -2, JPEG_CONV_PARAM_ERR = -3, JPEG_CONV_BUSY = -4, JPEG_CONV_PARAM_RANGE_ERR = -7 } |
Error codes. More... |
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enum |
wr_rd_swa_t
{
WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT = 1, WR_RD_WRSWA_16BIT = 2, WR_RD_WRSWA_16_8BIT = 3, WR_RD_WRSWA_32BIT = 4, WR_RD_WRSWA_32_8BIT = 5, WR_RD_WRSWA_32_16BIT = 6, WR_RD_WRSWA_32_16_8BIT = 7 } |
Write/Read image pixcel frame buffer swap setting. More... |
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enum | wr_rd_format_t { WR_RD_YCbCr422 = 0x00, WR_RD_ARGB8888 = 0x01, WR_RD_RGB565 = 0x02 } |
Write/Read image pixcel format selects. More... |
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enum | sub_sampling_t { SUB_SAMPLING_1_1 = 0x00, SUB_SAMPLING_1_2 = 0x01, SUB_SAMPLING_1_4 = 0x02, SUB_SAMPLING_1_8 = 0x03 } |
Thinning output image selects. More... |
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enum | cbcr_offset_t { CBCR_OFFSET_0 = 0x00, CBCR_OFFSET_128 = 0x01 } |
Cb/Cr range selects for decode. More... |
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Public Member Functions |
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JPEG_Converter () | |
Constructor method of JPEG converter(encode/decode)
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virtual | ~JPEG_Converter () |
Destructor method of JPEG converter(encode/decode)
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JPEG_Converter::jpeg_conv_error_t | decode (void *pJpegBuff, bitmap_buff_info_t *psOutputBuff) |
Decode JPEG to rinear data.
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JPEG_Converter::jpeg_conv_error_t | decode (void *pJpegBuff, bitmap_buff_info_t *psOutputBuff, decode_options_t *pOptions) |
JPEG data decode to bitmap.
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JPEG_Converter::jpeg_conv_error_t | encode ( bitmap_buff_info_t *psInputBuff, void *pJpegBuff, size_t *pEncodeSize) |
Encode rinear data to JPEG.
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JPEG_Converter::jpeg_conv_error_t | encode ( bitmap_buff_info_t *psInputBuff, void *pJpegBuff, size_t *pEncodeSize, encode_options_t *pOptions) |
Bitmap data encode to JPEG.
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JPEG_Converter::jpeg_conv_error_t | SetQuality (const uint8_t qual) |
Set encode quality.
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Correspondence file
A correspondence file of JPEG Converter is as the following table.
JPEG | Correspondence |
Width | >0(greater than 0) |
Height | >0(greater than 0) |
Color format | YCbCr444, YCbCr422, YCbCr420, YCbCr411 |
Bitmap | Correspondence |
Width | >0(greater than 0) |
Height | >0(greater than 0) |
Color format | YCbCr422 |
Notice
You run JPEG converter once destruction each time.
You set whether these JPEG files aren't input, or it check error setting decode(set in "flag" = true). The JPEG file which becomes correspondence outside will be the following condition.
- File besides the above-mentioned correspondence file.
- As information in the JPEG file, WIDTH or HEIGHT is larger than output buffer setting.
Buffer area is used encode/decode, set 8 bytes align and non-cash memory area. The output buffer when decoding, is made beyond the size decided in the size of the JPEG file, the format, setting of thinning out. You make output buffer for decode/encode to enough big size in order to stock this result. JPEG Converter, if you do not particularly perform specified, does not check size against the output data at the time of encoding and decoding. You set the output buffer so that there is no effect of corruption by the output data.
Color format
Color format in case to be converted from Bitmap to JPEG is either ARGB8888 or RGB555, YCbCr422.
Color format of the If you want to convert from JPEG file to Bitmap file is YCbCr422.
You correct "alpha(member of decode_options_t)" of setting and "output_cb_cr_offset(member of decode_options_t)" according to color format when decoding.
- example
decode to ARGB8888(WR_RD_ARGB8888 set in format member of bitmap_buff_info_t)
alpha = 0x01-0xFF
output_cb_cr_offset = CBCR_OFFSET_0
decode to YCbCr422(WR_RD_YCbCr422 set in format member of bitmap_buff_info_t)
alpha = 0
output_cb_cr_offset = CBCR_OFFSET_0 or CBCR_OFFSET_128
decode to RGB565(WR_RD_RGB565 set in format member of bitmap_buff_info_t)
alpha = 0
output_cb_cr_offset = CBCR_OFFSET_0
Decode/encode settings are optional
If omitted encode/decode settings, it will work with the following settings.
[Decode option setting (member of decode_options_t)]
- Vertical sub sampling is thinning output image to 1/1.
- Horizontal sub sampling is thinning output image to 1/1.
- Output data of Cb/Cr range is -128 to 127.
- Output data of swap in 8-bit units: 2-1-4-3-6-5-8-7.
- Alpha value of 0.
- JPEG format correspondence outside error check.
- It decode in a synchronous function.
[Encode option setting (member of encode_options_t)]
- DRI value is 0.
- Encoding JPEG file start width offset is 0.
- Encoding JPEG file start height offset is 0.
- Input data of Cb/Cr range of input data is -128 to 127.
- Input data swap in 8-bit units: 2-1-4-3-6-5-8-7.
- It don't check encode size.
- Quantization Y use default table(Quality75).
- Quantization C use default table(Quality75).
- Huffman Y DC use default table.
- Huffman C DC use default table.
- Huffman Y AC use default table.
- Huffman C AC use default table.
- It encode in a synchronous function.
Synchronous/asynchronous switching
Decoding and encoding setting to operate asynchronously by setting a callback function(decode_options_t and encode_options_t).
Quality
Quality changes are possible.
If you want to change the Quality, please specify the table made of Quality you want to change the address of the setting.
If you do not want to change the Quality, it will operate at Quality75.
RGA
The RGA library implements fast drawing functionality which uses the RGA of the RZ/A Series.
Supporting compiler is ARMCC, GCC ARM and IAR.
Hello World!
Import programRGA_HelloWorld
Hello World for RGA(Renesas Graphics Architecture). RGA is the Graphics Library of RZ/A1. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE
common/inc/clib_registers.h
- Committer:
- dkato
- Date:
- 2017-04-24
- Revision:
- 13:1ee2176ef13f
- Parent:
- 0:37e1e6a45ced
File content as of revision 13:1ee2176ef13f:
/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /** * @file clib_registers.h * @brief $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION) * $Rev: 30 $ * $Date:: 2014-02-13 21:21:47 +0900#$ * - Description: Common code for drivers and more. */ #ifndef CLIB_REGISTERS_H #define CLIB_REGISTERS_H /****************************************************************************** Includes <System Includes> , "Project Includes" ******************************************************************************/ #include "r_typedefs.h" #include "r_ospl.h" #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /****************************************************************************** Typedef definitions ******************************************************************************/ /****************************************************************************** Macro definitions ******************************************************************************/ /****************************************************************************** Variable Externs ******************************************************************************/ /****************************************************************************** Functions Prototypes ******************************************************************************/ /****************************************************************************** Inline Functions ******************************************************************************/ /** * @brief CPG unit of RZ/A1H. * * @par Parameters * None * @return Pointer to CPG structure. */ INLINE struct st_cpg *R_Get_CPG_Base(void) { /* ->QAC 0306 */ #if IODEFINE_H_VERSION >= 100 return &CPG; #else return (struct st_cpg *) &CPG; #endif /* <-QAC 0306 */ } /*********************************************************************** * Group: Register_Access ************************************************************************/ /** * @brief Set a value to register bit field. * * @param in_out_Register Address of register or variable * @param RegisterName Name of register * @param BitName Name of bit * @param Value Writing value * @return None. * * @par Description * Bit width is got from "RegisterName". */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ #define R_DRV_SET_REGISTER_BIT_FIELD( \ in_out_Register, RegisterName, BitName, Value ) \ R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \ in_out_Register, RegisterName, BitName, Value, \ DRV__BIT_WIDTH__##RegisterName ) /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /** * @brief Set a value to register bit field with width parameter. * * @param in_out_Register Address of register or variable * @param RegisterName Name of register * @param BitName Name of bit * @param Value Writing value * @param BitWidth BitWidth * @return None. */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ /* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */ /* ->SEC M5.1.3 */ #define R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \ in_out_Register, RegisterName, BitName, Value, BitWidth ) \ R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \ in_out_Register, RegisterName##__##BitName, Value, BitWidth ) /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */ /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /* Sub macro */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ /* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */ /* ->SEC M5.1.3 */ #define R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \ in_out_Register, RegisterBitName, Value, BitWidth ) \ R_DRV_SET_REGISTER_BIT_FIELD_SUB( \ in_out_Register, RegisterBitName, Value, BitWidth ) /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */ /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /* Sub macro */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ #define R_DRV_SET_REGISTER_BIT_FIELD_SUB( \ in_out_Register, RegisterBitName, Value, BitWidth ) \ R_OSPL_SET_TO_##BitWidth##_BIT_REGISTER( \ (volatile uint##BitWidth##_t*)(in_out_Register), \ DRV__MASK##BitWidth##__##RegisterBitName, \ DRV__SHIFT__##RegisterBitName, \ (uint##BitWidth##_t)(Value) ) /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /** * @brief Get a value from register bit field. * * @param RegisterValue Value of register or variable * @param RegisterName Name of register * @param BitName Name of bit * @return Value of shifted bit field. * * @par Description * Bit width is got from "RegisterName". */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ #define R_DRV_GET_REGISTER_BIT_FIELD( \ RegisterValue, RegisterName, BitName ) \ R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \ RegisterValue, RegisterName, BitName, \ DRV__BIT_WIDTH__##RegisterName ) /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /** * @brief Get a value from register bit field with width parameter. * * @param RegisterValue Value of register or variable * @param RegisterName Name of register * @param BitName Name of bit * @param BitWidth BitWidth * @return Value of shifted bit field. */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ /* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */ /* ->SEC M5.1.3 */ #define R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \ RegisterValue, RegisterName, BitName, BitWidth ) \ R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \ RegisterValue, RegisterName##__##BitName, BitWidth ) /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */ /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /* Sub macro */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ /* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */ /* ->SEC M5.1.3 */ #define R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \ RegisterValue, RegisterBitName, BitWidth ) \ R_DRV_GET_REGISTER_BIT_FIELD_SUB( \ RegisterValue, RegisterBitName, BitWidth ) /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */ /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /* Sub macro */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ #define R_DRV_GET_REGISTER_BIT_FIELD_SUB( \ RegisterValue, RegisterBitName, BitWidth ) \ R_OSPL_GET_FROM_##BitWidth##_BIT_REGISTER( \ (volatile const uint##BitWidth##_t*) &(RegisterValue), \ DRV__MASK##BitWidth##__##RegisterBitName, \ DRV__SHIFT__##RegisterBitName ) /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /** * @brief Returns whether specified value is overflowed from the bit field. * * @param RegisterName Name of register * @param BitName Name of bit * @param Value Checking value * @return Whether specified value is overflowed. */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ #define R_DRV_IS_OVERFLOW_BIT_FIELD( \ RegisterName, BitName, Value ) \ R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \ RegisterName, BitName, Value, DRV__BIT_WIDTH__##RegisterName ) /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /** * @brief Returns whether specified value is overflowed from the bit field. * * @param RegisterName Name of register * @param BitName Name of bit * @param Value Checking value * @param BitWidth BitWidth * @return Whether specified value is overflowed. */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ /* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */ /* ->SEC M5.1.3 */ #define R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \ RegisterName, BitName, Value, BitWidth ) \ R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \ RegisterName##__##BitName, Value, BitWidth ) /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */ /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /* Sub macro */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ /* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */ /* ->SEC M5.1.3 */ #define R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \ RegisterBitName, Value, BitWidth ) \ R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \ RegisterBitName, Value, BitWidth ) /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */ /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /* Sub macro */ /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */ #define R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \ RegisterBitName, Value, BitWidth ) \ R_DRV_IsOverflowBitField##BitWidth##_Sub( \ DRV__MASK##BitWidth##__##RegisterBitName, \ DRV__SHIFT__##RegisterBitName, \ Value ) /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */ /* Sub function */ /* : R_DRV_IsOverflowBitField32_Sub */ /* : R_DRV_IsOverflowBitField16_Sub */ /* : R_DRV_IsOverflowBitField8_Sub */ INLINE bool_t R_DRV_IsOverflowBitField32_Sub( uint32_t const Mask, int_fast32_t const Shift, uint32_t const Value ) { return ( ( (uint32_t)(Value) & ~( (uint32_t)(Mask) >> (Shift) ) ) != 0u ); } INLINE bool_t R_DRV_IsOverflowBitField16_Sub( uint16_t const Mask, int_fast32_t const Shift, uint16_t const Value ) { return ( ( (uint_fast16_t)(Value) & ~( (uint_fast16_t)(Mask) >> (Shift) ) ) != 0u ); } INLINE bool_t R_DRV_IsOverflowBitField8_Sub( uint8_t const Mask, int_fast32_t const Shift, uint8_t const Value ) { return ( ( (uint_fast8_t)(Value) & ~( (uint_fast8_t)(Mask) >> (Shift) ) ) != 0u ); } /** * @def CPG * @brief CPG */ /* 0xFCFE0438 */ #define DRV__BIT_WIDTH__STBCR9 8 enum { /*uint8_t */ DRV__MASK8__STBCR9__MSTP91 = 0x02 }; /* VDC5-0, LVDS */ enum { /*uint8_t */ DRV__MASK8__STBCR9__MSTP90 = 0x01 }; /* VDC5-1 */ enum { /* int_fast32_t */ DRV__SHIFT__STBCR9__MSTP91 = 1 }; enum { /* int_fast32_t */ DRV__SHIFT__STBCR9__MSTP90 = 0 }; #ifdef __cplusplus } /* extern "C" */ #endif /* __cplusplus */ #endif /* CLIB_REGISTERS_H */